TC74A23F

TC74A23F TOSHIBA | Alldatasheet

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/Gb7/G20Single-chip CD processor with built-in CMOS LCE/LED driver and 4-bit microcontroller /Gb7/G20Operating voltage: At CD on: V DD = 4.5 to 5.5 V (typ. 5.0 V) At CD off: VDD = 3.0 to 5.5 V (only CPU on) /Gb7/G20Current dissipation: At CD on: I DD = 50 mA (typ.) At CD off: IDD = 2 mA (with 4.5 MHz crystal oscillator, only CPU on) At CD off: IDD = 0.3 mA (with 75 kHz crystal oscillator, only CPU on) /Gb7/G20Operating temperature range: Ta = /G2d40~85°C /Gb7/G20Package: QFP100-P-1420-0.65A (0.65-mm pitch, 2.7-mm thick) /Gb7/G20One-time PROM version: TC94AP09F Weight: 1.6 g (typ.)

/Gb7/G20Program memory (ROM): 16-bit /Gb4 8k-step /Gb7/G20Data memory (RAM): 4-bit /Gb4 512-word /Gb7/G20Instruction execution time: 1.89/1.78/40 /G6ds (all one-word instructions)/G20 /Gb7/G20Crystal oscillator frequency: 16.9344 MHz/4.5 MHz/75 kHz /Gb7/G20Stack level: 8 /Gb7/G20AD converter: 6-bit /Gb4 4-channel /Gb7/G20LCD driver: 1/4 duty, 1/2 or 1/3 bias method, 72 segments max /Gb7/G20LED driver: 4-digit /Gb4 14-segment (max), also used as LCD driver switched by software /Gb7/G20I/O port: CMOS I/O port: 16 N-channel open drain I/O port: 4 (max) Output-only port: 4 (max), also used as CD processor pins Input-only port: 4/G20 /Gb7/G20Timer/counter: 8 bit (INTR, instruction cycle, 100/1 kHz selectable as timer clock) 10, 100, or 500 Hz: internal port

2 Hz: Flip-flop port

/Gb7/G20Serial interface: Supports 2/3-line method (data length: 4 or 8 bits) /Gb7/G20Buzzer: Four types: 0.75, 1, 1.5, and 3 kHz Four modes: Continuous, Single-Shot, 10 Hz Intermittent, and 10 Hz Intermittent at 1 Hz Interval) /Gb7/G20Interrupt: 1 external, 3 internal (CD sub-sync, serial interface, 8-bit timer) /Gb7/G20Back-up mode: three types Clock Stop (crystal oscillator off) Hardware Wait (crystal oscillator on but CPU in operation) Software Wait (CPU in intermittent operation) /Gb7/G20Reset function: Power-on reset, built-in supply voltage detector (detection voltage /G3d 2.5 V typ.) CD Processor /Gb7/G20Reliable sync pattern detection, sync signal protection and interpolation /Gb7/G20Built-in EFM decoder and sub code decoder /Gb7/G20High-correction capability using cross interleave read Solomon code (CIRC) logical equation C1 correction: dual C2 correction: quadruple /G20 /Gb7/G20Supports variable speeds. /Gb7/G20Jitter absorption capability of /Gb16 frames /Gb7/G20Built-in 16 KB RAM /Gb7/G20Built-in digital output circuit /Gb7/G20Built-in L/R independent digital attenuators /Gb7/G20Bilingual audio output (Note) /Gb7/G20Sub code Q data are read-timing free and can be output in sync with audio data. (Note)/G20 /Gb7/G20Built-in data slice and analog PLL (adjustment-free VCO used) circuit /Gb7/G20Auto adjustment of loop gain, offset, and balance at focus servo and tracking servo /Gb7/G20RF gain auto adjustment circuit /Gb7/G20Built-in digital equalizer for phase compensation /Gb7/G20Supports different pickups using built-in digital equalizer coefficient RAM. /Gb7/G20Built-in focus and tracking servo control circuit /Gb7/G20Search control supports all modes and realizes high-speed, stable search. /Gb7/G20Lens kick and feed kick use speed control method. /Gb7/G20Built-in AFC circuit and APC circuit for disc motor CLV servo. /Gb7/G20Built-in defect/shock detector /Gb7/G20Built-in 8 times oversampling digital filter and 1-bit DA converter. Note: Output pins for sub code Q data and audio data are also used as LCD driver pins. The function of the pins can be switched by program.

Note: Symbols used for the pins above indicate the following pin functions. Note: When the CD is off, the power supply pins for the controller (MV DD) and the power pins supply for the CD oscillator (XVDD) are on and the CD processor-dedicated power supply pins (indicated by asterisk *) are off. M A R M : CD processor-dedicated pin : Power supply pin : CD processor tri-state output pin : CD processor analog input/output pin : Reference input pin : Controller-dedicated pin COM2 (OT2) MVDD MVSS MXI MXO INTR RST IN2/(VPP) TESTM DVSL LO DVRL DVDD RO DVRR DVSR P2-1 ( HSO in) P2-0 (EMPHin) P4-3 (SCK/SCL) P4-2 (SI0/SI1/SDA) TMAX PDO P2VREF VSS SBOK VDD SBSY DOUT OT22 (COFS) OT21 (SPDA) OT20 (SPCK) TESTC IN1 (BCKin) P2-3 (DATAin) P2-2 (LRCKin) LPFN LPFO PVREF AVSS SLCO RFI AV DD RFCT RFZI RFRP FEI SBAD TEI TEZI FOO FMO DMO REF SEL VDD VSS XVSS XI XO XV DD VCOF TRO TEBC RFGC VREF P3-0 P4-1 (SI2) P4-0 (ADin4/BUZR) P3-3 (ADin3) P3-2 (ADin2) P3-1 (ADin1) P1-3 P1-2 P1-1 P1-0 MV SS MVDD P8-3 (OT18/IPF) P8-2 (OT17/MBOV) P8-1 (S16/AOUT) P8-0 (S15/BCK) S14 (OT18/LRCK) S13 (OT17/SFSY) S12 (OT16/DATA) S11 (OT15/CLCK) S10 (OT14/ZDET) S1 (OT5) M M 3 3 3 R 3 3 3 3 R A A A A A A A A A 3 A A 3 A R A A M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M R M M M M M M M M M M M M M M M R M R M M M M M M M M M M M M M M 100 1 5 10 15 20 25 30 80 75 70 65 60 55 51 HOLD COM1 (OT1) COM4 (OT4) COM3 (OT3) S2 (OT6) S3 (OT7) S4 (OT8) S5 (OT9) S6 (OT10) S7 (OT11) S8 (OT12) S9 (OT13) OT19 ( HSO ) OSC Power supply to controller Controller test input Reset input Hold input Interrupt input CD processor input/output CD test input I/O ports (16) Power supply to controller LCD driver/LED driver output port (LCD: 4 /Gb4 18 /G3d 72 segments max, LED: 18 segments) T C 9 4 A 2 3 F (QPF100 pin) CD function pins switched CD function pins switched together

P3-3 (ADin3) RST TESTM DVSL LO DVRL DVDD RO DVRR DVSR IN1 (BCKin) IN2 P4-3 (SCK/SCL) P4-2 (SI0/SI1/SDA) TMAX PDO P2VREF VCOF SBOK PVREF SBSY DOUT OT22 (COFS) OT21 (SPDA) OT20 (SPCK) TESTC MVSS MVDD AVSS AVDD RFCI RFZI RFRP FEI SBAD TEI TEZI FOO FMO DMO REF SEL TRO TEBC RFGC V REF HOLD P4-0 (ADin4/BUZR) P3-1 (ADin1) P3-2 (ADin2) OT19 ( HSO ) XVSS XO XI XVDD VDD VSS COM1 (OT1) COM2 (OT2) COM3 (OT3) COM4 (OT4) S1 (OT5) P4-1 (SI2) S14 (OT18/LRCK) S13 (OT17/SFSY) S12 (OT16/DATA) S11 (OT15/CLCK) P8-3 (S18/IPF) P8-2 (S17/MBOV) P8-1 (S16/AOUT) P8-0 (S15/BCK) LPFN RFI SLCO P3-0 INTR P2-3 (DATAin) P2-0 (EMPHin) P2-1 ( HSO in) P2-2 (LRCKin) LPFO MXI MXO P1-3 P1-0 S2 (OT6) S10 (OT14/ZDET) X’tal OSC LPF X’tal OSC Port1 MPX Clock gene. CPU clock Timer Interrupt Cont. Port4 BUZR AD Conv. Serial Interface Port3 LCD Driver/Output Port Port8 Bias 1 bit DAC ZDET PWM CD clock VREF SBSY DA SERVO control Digital equalizer Automatic adjustment circuit ROM RAM 16 k SRAM CLV servo VREF Synchronous guarantee EFM decode Sub code decoder Data slicer VREF PLL TMAX VCO Correction circuit Address AD Digital out Audio out Micon interface Data Reg (16 bit) ROM (16 /Gb4 8192 Step) Program Counter Stack Reg. (8Level) G-Reg. R/W Buf. ALU OT19-22 Port2 Power on Reset F/F Reset ZDET, CLCK, DATA, SFSY, LRCK, BCK, MBOV, IPF RAM (4 /Gb4 512 word) Instruction Decoder SBSY CLCK, DATA, SFSY, LRCK, BCK, MBOV, IPF CD ResetP2-0~P2-3 IN1 Reset

Number Symbol Pin Name Function and Operation Remarks

97 COM1/OT1

98 COM2/OT2

99 COM3/OT3

100 COM4/OT4

/output port Common signal output pins for the LCD panel. Those pins configure matrix with S1 to S18 and display up to 72 segments. The LCD can be driven by the 1/2 or 1/3 bias method. When the 1/2 bias method is set, three levels, MV DD, 1/2MVDD, and GND, are output at 2-ms intervals at a 62.5 Hz cycle. When the 1/3 bias method is set, four levels, MV DD, 1/3MVDD, 2/3MVDD, and GND, are output at 1-ms intervals at a 125 Hz cycle (when either the 4.5 MHz or 75 kHz crystal oscillator is used). After system reset or clock stop execution is released, the non-selected waveform (bias voltage) is output. The DISP OFF bit is set to 0 and the common signal is output. These pins can be switched to an output port (Note 1) or LED driver pins by program. They are usually used for digit output to drive the LEDs. MVDD MVDD Bias voltage

Number Symbol Pin Name Function and Operation Remarks 1~9 S1/OT4 S9/OT13 LCD segment output /output port

10 S10/OT14

/ZDET

11 S11/OT15

/CLCK

12 S12/OT16

/DATA

13 S13/OT17

/SFSY

14 S14/OT18

/LRCK LCD segment output /output port /CD signal

15 P8-0/S15

/BCK

16 P8-1/S16

/AOUT

17 P8-2/S17

/MBOV

18 P8-3/S18

/IPF I/O port /LCD segment output /CD signal Segment signal output pins for the LCD panel. Those pins configure a matrix with COM1 to COM4 and display up to 72 segments. When the 1/2 bias method is set, two levels, MVDD and GND, are output. When the 1/3 bias method is set four levels, MVDD, 1/3MVDD, 2/3MVDD, and GND, are output. The S1 to S14 pins can be switched to an output port (Note 1) by program. Port 8 and S15 to S18 pins can be switched pin by pin to an I/O port and segment output pins. When the pins are set to an I/O port, output is N-channel open drain. The S10 to S14 and P8-0 to P8-3 pins can be switched to CD signal input/output pins by program. Setting the CD10 bit to 1 switches the pins to the LRCK, BCK, and AOUT pins as the CD pins in batches. The other pins can be individually switched according to the S14/S15/S16 segment data. CLCK: Inputs/outputs sub code P to W data reading clock. DATA: Outputs sub code P to W data. SFSY: Outputs frame sync signal for playback. LRCK: Outputs channel clock (44.1 kHz). When L channel, outputs Low. When R channel, outputs High. The polarity can be inverted by command. BCK: Outputs bit clock (1.4112 MHz). AOUT: Outputs audio data. MBOV: Outputs buffer-memory-overflow signal. When buffer memory overflows, outputs H. IPF: Outputs interpolation pointing flag. If AOUT output is C2 error detection/correction, outputs High to indicate correction is impossible. ZDET: Outputs 1-bit DAC zero detection flag. Pins set as an output port are used for segment output for the LED driver. The output port can increment OT1 to OT18 by instruction, facilitating access to data in external RAM and ROM. (Note 1) After a system reset, pins also used as output ports are set to LCD output; pins also used as I/O ports are set to I/O port input. MVDD MVDD Bias voltage MVDD MVDD Bias voltage Input instruction MVDD

Number Symbol Pin Name Function and Operation Remarks 21~24 P1-0~P1-3 I/O port 1 4-bit CMOS I/O port. Input/output can be set for each bit by program. The pins can be set to be pulled-up or pulled-down by program. Thus, they can be used as key input pins. When the pins are set to I/O port input, Clock Stop mode and Wait mode can be released, according to the change in input to the pins.

25 P3-0 I/O port 3

26~28 P3-1/ADin1 P3-3/ADin3 I/O port 3 /A/D analog voltage input

29 P4-0/ADin4

/BUZR I/O port 4 /A/D analog voltage input/buzzer output 5-bit CMOS I/O port. Input/output can be set for each bit by program. P3-1 and P4-0 pins are also used as built-in 6-bit 4-channel A/D converter analog input pins. The built-in A/D converter uses successive approximation. The conversion time is 6 instruction cycles (280 /G6ds) when the 75 kHz crystal oscillator is used; 198 /G6ds when the 4.5 MHz crystal oscillator is used; 180 /G6ds when the 16.9344 MHz crystal oscillator is used. A/D analog input can be set for each pin by program. The internal power supply (MV DD) is used as the reference voltage. The P4-0 pin is also used as the buzzer output pin. One of four frequencies: 0.75, 1, 1.5, and 3 kHz, can be selected for buzzer output. The buzzer is output at the selected frequency in one of four modes: Continuous, single-shot,

10 Hz intermittent, and 10 Hz intermittent at 1

Hz interval. Settings for the A/D converter and buzzer, and their control can be performed by program.

33 P2-0/EMPHin

34 P2-1/ HSO in

35 P2-2/LRCKin

36 P2-3/DATAin

/1-bit DAC input

37 IN1/BCKin

89 IN2/ (VPP)

input (VPP input) I/O port 2 is a 4-bit CMOS I/O port. IN1 and IN2 are a 2-bit general-purpose input port. Input/output can be set for each bit of I/O port 2 by program. I/O port 2 and the IN1 pins can be switched to 1-bit DAC input pins by the CD command to support shock-proofing. In this case, the I/O port must be set to input. With the OTP version, the IN2 pin is also used as the program power supply pin. MVDDMVDD RIN1 MVDD MVDD To A/D converter Input instruction MVDDMVDD MVDD

Number Symbol Pin Name Function and Operation Remarks

30 P4-1/S12 I/O port 4/serial data

31 P4-2

/SI0/SI1/SDA /serial data input/output

32 P4-3

/SCK/SCL /serial clock input/output 3-bit CMOS I/O port. Input/output can be set for each bit by program. These pins are also used as serial interface (SIO) circuit input/output pins. SIO is a serial interface supporting 2-line and 3-line methods. Starting from the MSB or LSB, 4 or 8-bit serial data are output to the SO/SDA pin, or data on the SI1 and SI2 pins are input to the device at the clock edge on the SCK/SCL pin. As the serial operating clock (SCK/SCL), an internal (450/225/150/75 kHz) or external clock can be selected. Rising or falling shift can also be selected. The clock and data output can be N-channel open drain. These selections facilitate controlling the LSI and communications between the controllers. When SIO interrupts are enabled, an interrupt is generated as soon as execution of the SIO completes, and the program jumps to address 4. This is effective for performing serial communications at high speed. All SIO inputs incorporate a Schmidt circuit. SIO and its control can be set by program.

38 TESTC

88 TESTM

Input pins for controlling Test mode. When the pins are at High level, the device is in Test mode; at Low level, in normal operation. Normally, set the pins to Low level or NC (pull-down resistors are incorporated). 39~42 OT19/ HSO OT20/SPCK OT21/SPDA OT22/COFS Output port/CD control signal output 4-bit general-purpose output port. After system reset, the pins are set to a Low-level output port. The pins can be switched to CD control output pins by program. Setting OT19 to OT22 to 0 switches all four pins to CD control output pins. Setting OT19 to OT22 and CDIO to 1 enables the pins to be switched as follows according to the segment data contents of the S15 and S16 pins: HSO : Outputs playback speed mode. Normal speed: High Double speed: Low SPCK: Outputs clock for reading processor status signal (176.4 kHz). APCK: Outputs clock for reading processor status signal. SPDA: Outputs processor status signal. COFS: Outputs frame clock for correction (7.35 kHz). MVDD MVDD Input instruction /G2b SI0ON MVDD RIN2

Number Symbol Pin Name Function and Operation Remarks 43 DOUT Digital output in.

44 SBSY

Sub code block sync output pin. When sub code sync is detected, outputs High at the S1 position.

45 SBOK

Sub code Q data CRCC result output pin. When the result is OK, outputs High. 46, 75 V DD 47, 76 V SS Power supply pins for CD digital block. Normally, 5 V is applied. When CD is not used (CD off), the power supply can be set to off except to the controller, enabling only the controller to operate. At this time, 1 must be set in the CDoff bit. If pins from 11 to 18 and 39 to 42 are set as CD control signal input/output pins, setting the CDoff bit to 1 switches all the pins to an output port.

48 P2V REF 2V REF pin for PLL block /Gbe/G20

49 PDO Outputs phase error signal between the EFM

and PLCK signals.

50 TMAX

TMAX detection result output pin. Selected by command bit TMPS. Longer than the specified cycle: Outputs P2VREF. Shorter than the specified cycle: Outputs Low level (VSS). Within the specified cycle: at high impedance 51 LPFN Inverted input pin for low-pass filter amp. 52 LPFO Output pin for low-pass filter amp.

53 PV REF V REF pin for PLL block

54 VCOF VCO filter pin

55 AV SS

Ground pin for analog block /Gbe VDD VDD MVSS P2VREF PVREF P2VREF VCO PVREF AVDD LPFN LPFO PVREF VCOF

Number Symbol Pin Name Function and Operation Remarks

56 SLCO DAC output pin for generating data slice level

57 RFI RF signal input pin

58 AV DD Power supply pin for analog block /Gbe

59 RFCT RFRP signal center level input pin

60 RFZI RFRP zero-cross signal input pin

61 RFRP RF ripple signal input pin

62 FEI Focus error signal input pin

63 SBAD Sub beam addition signal input pin

64 TEI

Tracking error input pin. The pin is read at tracking servo on.

65 TEZI Tracking error/zero-cross signal input pin

66 FOO Focus equalizer output pin

67 TRO Tracking equalizer output pin

68 V REF

Analog reference voltage power supply pin /Gbe VREF Zin1 DAC AVDDRFI SLCO AVDD RFZI 1 k/G57 typ. 32 k /G57 typ. RFCT AVDD RFRP FEI SBAD TEI VREF AVDD TEZI Zin2 1 k/G57 typ. 32 k /G57 typ. AVDD 2VREF/G7e AVSS Rout3

Number Symbol Pin Name Function and Operation Remarks

69 RFGC

Control signal output pin for adjusting RF amplitude. Outputs three-level PWM signal (PWM carrier /G3d 88.2 kHz).

70 TEBC

Tracking balance control signal output pin. Outputs three-level PWM signal (PWM carrier /G3d 88.2 kHz).

71 FMO

Focus equalizer output pin. Outputs three-level PWM signal (PWM carrier /G3d 88.2 kHz).

72 DMO

Disc equalizer output pin. Outputs three-level PWM signal (PWM carrier /G3d 88.2 kHz for DSP block). 73 2V REF Analog reference voltage power supply pin (2 /Gb4 VREF) /Gbe

74 SEL

APC circuit on/off signal output pin. At laser on, high impedance at UHS /G3d High; H level output at UHS /G3d High.

77 XV SS

80 XV DD

Power supply pins for CD crystal oscillator. To control the CD processor power supply and the controller power supply individually, connect the MV DD and MVSS pins to the power supply lines used by the VDD and VSS pins. /Gbe 78 XI 79 XO CD processor crystal oscillator pins CD crystal oscillator input/output pins. Connect a 16.9344 MHz crystal oscillator. The clock is used as the CD system clock and controller system clock. After system reset, this clock is supplied as the controller system clock and starts the CPU. The crystal oscillator can be halted by program. If the 4.5 MHz or 75 kHz oscillator is selected as the controller system clock, the oscillator is halted by program when the CD processor is off. During execution of the CKSTP instruction, oscillation halts. (Note) When switching the controller system clock from the controller oscillator to the CD crystal oscillator, make sure that the CD crystal oscillator is in stable state. P2VREF VREF Rout3 VDD XVDD XVSS XO Rout1 RfXT1 XI

Number Symbol Pin Name Function and Operation Remarks

81 DV SR R-channel D/A converter block ground pin

82 RO R-channel data forward rotation output pin

83 DV RR R-channel reference voltage pin

84 DV DD D/A converter block power supply pin

85 DV RL L-channel reference voltage pin

86 LO L-channel data forward rotation output pin

87 DV SL

L-channel D/A converter block ground pin

90 RST Reset input

Device system reset signal input pin. While the RST is at Low level, reset is applied. When the RST is at High level, the CD block is in operation, and the controller program starts from address 0. Normally, when 2.7 V or higher voltage is supplied to the MV DD when at 0 V, system reset is applied (power-on reset). Fix the pin to High level.

91 HOLD Hold mode control

Input pin used to request or release hold state. Normally, the pin is used for inputting the CD mode selection signal or battery detection signal. Halt states are Clock Stop mode (crystal oscillator stops oscillation) and Wait mode (CPU stops). The modes are entered using the CKSTP and WAIT instructions. By program, Clock Stop mode can be entered by detection of Low level on the HOLD pin or by forced execution. Clock Stop mode can be released by detection of High level on the HOLD pin or change in the HOLD pin input. Executing the CKSTP instruction stops the clock generator and the CPU, entering memory backup state. During memory backup state, current dissipation becomes low (1 /G6dA or below). The display output and CMOS output port automatically become Low level. The N-channel open drain output becomes off. Regardless of the HOLD pin input state, Wait mode is executed and current dissipation becomes low. Crystal oscillator only on or CPU operation suspended can be programmed. When the crystal oscillator only is on, all displays are at Low level. The other pins are in Hold state. When CPU operation is suspended, all states are held except that the CPU is suspended. Wait mode is released by a change of the HOLD pin input. (Note) To use Backup mode, turn off the V DD pin (power supply for CD), and enter Backup mode. DVDD VSS DVSL/DVSR DVDD RO/LO DVRR/DVRL MVDD MVDD

Number Symbol Pin Name Function and Operation Remarks

92 INTR External interrupt

External interrupt input pin. When interrupts are enabled and a pulse of 1.11 to 3.33 /G6ds or more (13.3 to 40 /G6ds when the 75 kHz clock is used) is input to this pin, an interrupt is generated and the program jumps to address 1. Input logic and rising/falling edge can be individually selected for interrupt inputs. The internal 8-bit timer clock can be selected for interrupt inputs. Interrupts can be generated (address 3) by pulse count or the count value. Interrupt inputs are Schmidt inputs. The pin can be used as an input port for inputs such as remote control signals.

93 MXO

94 MXI

Crystal oscillator pins for the controller. The oscillator clock is used as a time base for the clock function as well as the system clock for the controller. After system reset, the CPU starts operation using the 16.9344 MHz CD oscillator (connected to the XI and XO pins). The oscillator is switched to the controller oscillator by program. Either a 4.5 MHz reference oscillator or a 75 kHz oscillator is connected to the MXO and MXI pins. The oscillators are switched by a bit used to select a frequency of 4.5 MHz or 75 kHz. The oscillators incorporate a feedback resistor. Switching frequencies automatically switches the feedback resistor of the crystal oscillator. 75 kHz: Rout2 /G3d 2 K/G57, RfXT2 /G3d 10 M/G57 typ. 4.5 MHz: Rout2 /G3d 2 K/G57, RfXT2 /G3d 1 M/G57 typ. If the operating clock is the CD crystal oscillator, fix the MXI pin to GND. During execution of the CKSTP instruction, oscillation halts. Selection and control of crystal oscillators are done by program. (Note) When the 75 kHz crystal oscillator is used, externally add/connect a 100 k/G57 output resistor. 19, 96 MV DD 20, 95 MV SS Power supply pins for controller block Power supply pins for the controller block. Normally, VDD /G3d 4.5 to 5.5 V. In backup state (when executing the CKSTP instruction), current dissipation becomes low (1 /G6dA or below), dropping the power supply voltage to 2.0 V. If 2.7 V or more is applied to these pins when at 0 V, a system reset is applied to the device and the program starts from address 0 (power-on reset). The CD processor incorporates a power supply detector, which detects the power supply voltage of 2.5 V. (Note) At power-on reset operation, allow 10 to 100 ms while the device power supply voltage rises. When not using the power supply detector function, set the test port pins (TEST#0 to 3) to all 1s so that the CD processor enters Halt state. Setting to Halt state reduces current dissipation by 150 /G6dA (typ.). MVDD MXO Rout2 RfXT2 MXI MVDD MVSS

Maximum Ratings (Ta /G3d/G3d/G3d/G3d 25°C, VDD /G3d/G3d/G3d/G3d MVDD /G3d/G3d/G3d/G3d DVDD /G3d/G3d/G3d/G3d AVDD, MVDD /G3d/G3d/G3d/G3d XVDD) Characteristic Symbol Rating Unit VDD Power supply voltage MVDD /G2d0.3~6.0 (MVDD /G3e/G3dVDD) V (VDD power supply pin) VIN1 /G2d0.3~VDD /G2b 0.3/G20 Input voltage (MVDD power supply pin) VIN2 /G2d0.3~MVDD /G2b 0.3/G20 V Power dissipation P D 1400 mW Operating temperature T opr /G2d40~85 °C Storage temperature T stg /G2d65~150 °C

Electrical characteristics

(unless otherwise specified, Ta /G3d/G3d/G3d/G3d 25°C, VDD /G3d/G3d/G3d/G3d MVDD /G3d/G3d/G3d/G3d XVDD /G3d/G3d/G3d/G3d DVDD /G3d/G3d/G3d/G3d AVDD /G3d/G3d/G3d/G3d 5 V, 2VREF /G3d/G3d/G3d/G3d P2VREF /G3d/G3d/G3d/G3d 4.2 V, VREF /G3d/G3d/G3d/G3d PVREF /G3d/G3d/G3d/G3d 2.1 V) VDD (power supply pins for CD processor block: VDD, XVDD, DVDD, AVDD) Characteristic Symbol Test Circuit Test Condition Min Typ. Max Unit Operating power supply voltage range VDD /Gbe MV DD /G3d XVDD /G3e/G3dVDD /G3d DVDD /G3d AVDD * 4.5 ~ 5.5 V IDD /Gbe/G20(VDD, DVDD, AVDD) operating at 16.9344 MHz /Gbe 50 60 Operating power supply current XIDD /Gbe/G20(XVDD) 16.9344 MHz crystal oscillator connected /Gbe 2.0 /Gbe mA Crystal oscillator standby current XSTBY /Gbe/G20(XVDD) 16.9344 MHz crystal oscillator off /Gbe/G200.01 /Gbe /G6dA/G20 Crystal oscillator frequency f XT /Gbe/G20Ci /G3d Co /G3d 15 pF (Note 1)* /Gbe 16.9344 /Gbe MHz MVDD (power supply pins for CPU block: MVDD, XVDD) (Note 2) Characteristic Symbol Test Circuit Test Condition Min Typ. Max Unit MVDD1 CPU and CD in operation MVDD /G3d XVDD /G3e/G3dVDD /G3d DVDD /G3d AVDD * 4.5 ~ 5.5 MVDD2 CPU in operation (CD off, 4.5 MHz /16.9344 MHz crystal oscillator used) * 4.5 ~ 5.5 Operating power supply voltage range MVDD3 /Gbe CPU in operation (CD off, 75 kHz crystal oscillator used) * 3.0 ~ 5.5 Memory hold voltage range MVHD /Gbe/G20Crystal oscillator stopped (executing CKSTP instruction) * 2.0 ~ 5.5 V MIDD1 /Gbe/G20 XI /G3d 16.9344 MHz crystal oscillator connected /Gbe 3.0 5.0 MIDD2 /Gbe MXI /G3d 4.5 MHz crystal oscillator connected /Gbe 1.4 2.5 MIDD3 /Gbe CPU in operation MXI /G3d 75 kHz crystal oscillator connected /Gbe 0.3 1.0 MIDD4 /Gbe XI /G3d 16.9344 MHz crystal oscillator connected /Gbe 1.5 /Gbe MIDD5 /Gbe MXI /G3d 4.5 MHz crystal oscillator connected /Gbe 0.25 /Gbe Operating power supply current (Note 3) MI DD6 /Gbe Standby mode (crystal oscillator only in operation) MXI /G3d 75 kHz crystal oscillator connected /Gbe 0.1 /Gbe mA Memory hold current MI HD /Gbe/G20Crystal oscillator stopped (executing CKSTP instruction) /Gbe/G200.1 1.0 /G6dA/G20 fMXT1 /Gbe/G204.5 MHz crystal oscillator set (Note 1) * /Gbe/G204.5 /Gbe/G20MHz Crystal oscillator frequency fMXT2 /Gbe/G2075 kHz crystal oscillator set, MVDD /G3d 2.7~5.5 V (Note 1)* /Gbe/G2075 /Gbe kHz Crystal oscillator start time t st /Gbe/G20Crystal oscillator fmxt /G3d 75 kHz /Gbe /Gbe 1.0 s Note 1: Design and set constants according to the crystal oscillator to be connected. Note 2: The power supply/memory hold current is the value obtained by summing the XV DD and MVDD pin currents. Note 3: The values are those when the power supply detector function is operating. Setting the function reduces current dissipation by 150 /G6dA (typ.). (Except in Standby mode) An asterisk (*) indicates the values are guaranteed when VDD /G3d MVDD /G3d XVDD /G3d DVDD /G3d AVDD /G3d 4.5 to 5.5 V, and Ta /G3d /G2d40 to 85/Gb0C.

LCD common output/output port (COM1/OT1 to COM4/OT4) Characteristic Symbol Test Circuit Test Condition Min Typ. Max Unit IOH1 /Gbe V OH /G3d 4.5 V (LCD output) /G2d200 /G2d600 /Gbe /G6dA High level IOH2 /Gbe/G20VOH /G3d 4.5 V (OT output) /G2d15 /G2d30 /Gbe mA IOL1 /Gbe/G20VOL /G3d 0.5 V (LCD output) 200 600 /Gbe /G6dA Output current Low level IOL5 /Gbe/G20VOL /G3d 0.5 V (OT output) 4.0 10 /Gbe mA 1/2 level V BS2 /Gbe/G20No load (LCD output, 1/2 bias method set) 2.3 2.5 2.7 1/3 level V BS1 /Gbe/G20 1.47 1.67 1.87Bias voltage 2/3 level V BS3 /Gbe/G20 No load (LCD output, 1/3 bias method set) 3.13 3.33 3.53 V Segment output, output ports, I/O ports, and CD function output (S1/OT4 to S9/OT13, S10/OT14/ZDET to S14/OT18/LRCK, P8-0/S14/BCK to P8-3/S18/IPF, OT19) Characteristic Symbol Test Circuit Test Condition Min Typ. Max Unit IOH1 /Gbe V OH /G3d 4.5 V (LCD output) /G2d200 /G2d600 /Gbe /G6dA High level IOH4 /Gbe/G20VOH /G3d 4.5 V (OT output, CD output, excluding P8-0 to P8-3 pins) /G2d1.5 /G2d4.0 /Gbe mA IOL1 /Gbe/G20VOL /G3d 0.5 V (LCD output) 200 600 /Gbe /G6dA Output current Low level IOL5 /Gbe/G20VOL /G3d 0.5 V (OT output, CD output) 4.0 10 /Gbe mA Input leakage current I LI /Gbe/G20VIH /G3d 5.0 V, VIL /G3d 0 V (P8-0~P8-3) /Gbe /Gbe /Gb11.0 /G6dA High level V IH /Gbe (P8-0~P8-3, CLCK) MVDD /Gb4 0.8 ~ MV DD Input voltage Low level VIL /Gbe/G20(P8-0~P8-3, CLCK) 0 ~ MVDD /Gb4 0.2 V 1/3 level V BS1 /Gbe/G20 1.47 1.67 1.87 Bias voltage 1/2 level V BS3 /Gbe/G20 No load (LCD output, 1/3 bias method set) 3.13 3.33 3.53 V I/O port (P1-0~P4-3) Characteristic Symbol Test Circuit Test Condition Min Typ. Max Unit High level I OH3 /Gbe V OH /G3d 4.5 V /G2d0.8 /G2d2.0 /Gbe IOL3 /Gbe/G20VOL /G3d 0.5 V (excluding P4-1, P4-2, P4-3 pins) 1.0 3.0 /Gbe Output current Low level IOL5 /Gbe/G20VOL /G3d 0.5 V (P4-1, P4-2, P4-3 pins) 4.0 10 /Gbe mA Input leakage current I LI /Gbe/G20VIH /G3d 5.0 V, VIL /G3d 0 V /Gbe /Gbe /Gb11.0 /G6dA High level V IH /Gbe /Gbe MVDD /Gb4 0.8 ~ MV DD Input voltage Low level VIL /Gbe/G20 /Gbe 0 ~ MVDD /Gb4 0.2 V Input pull-up/down resistance R IN1 /Gbe/G20(P1-0 to P1-3 pins) pull-down/up set 25 50 120 k /G57 HOLD , INTR input port, RST RST input, 1-bit DAC data input (EMPHin/HSO in/LRCKin/DATAin/BCKin) Input port (IN1/IN2) Characteristic Symbol Test Circuit Test Condition Min Typ. Max Unit Input leakage current I LI /Gbe/G20VIH /G3d 5.0 V, VIL /G3d 0 V /Gbe /Gbe /Gb11.0 /G6dA High level V IH /Gbe /Gbe MVDD /Gb4 0.8 ~ MV DD Input voltage Low level VIL /Gbe/G20 /Gbe 0 ~ MVDD /Gb4 0.2 V

A/D converter (ADin1 to ADin4) Characteristic Symbol Test Circuit Test Condition Min Typ. Max Unit Analog input voltage range V AD /Gbe ADin1~ADin4 0 ~ MV DD V Resolution VRES /Gbe/G20 /Gbe /Gbe 6 /Gbe bit Total conversion error /Gbe /Gbe/G20 /Gbe /Gbe /Gb10.5 /Gb11.0 LSB Analog input leakage I LI /Gbe/G20VIH /G3d 5.0 V, VIL /G3d 0 V (ADin1~ADin4) /Gbe /Gbe /Gb11.0 /G6dA DOUT, SBSY, SBOK, SEL, OT19/HSO , OT20/SPCK, OT21/SPDA, OT22/COFS output Characteristic Symbol Test Circuit Test Condition Min Typ. Max Unit High level I OH4 /Gbe V OH /G3d 4.5 V /G2d1.5 /G2d4.0 /Gbe Output current Low level IOL4 /Gbe/G20VOL /G3d 0.5 V 1.5 4.0 /Gbe mA PDO, TMAX, RFGC, TEBC, FMO, DMO, TRO, FOO output Characteristic Symbol Test Circuit Test Condition Min Typ. Max Unit High level I OH6 /Gbe V OH /G3d 3.8 V, P2VREF /G3d 4.2 V (PDO, TMAX) /Gbe /G2d2.0 /Gbe Output current Low level IOL4 /Gbe/G20VOL /G3d 0.5 V, P2VREF /G3d 4.2 V (PDO, TMAX) /Gbe 6.0 /Gbe mA Output resistance R out3 /Gbe/G20(RFGC, TEBC, FMO, DMO, TRO, FOO) /Gbe 3.3 /Gbe k /G57 VREF output voltage V oref /Gbe/G20(RFGC, TEBC, FMO, DMO, PDD) VREF /G3d PVREF /G3d 2.1 V /Gbe 2.1 /Gbe V Transfer delay time (AOUT, SPDA, DATA, SBSY, SBOK) Characteristic Symbol Test Circuit Test Condition Min Typ. Max Unit High level t pLH /Gbe /Gbe /Gbe 10 /Gbe Transfer delay time Low level tpHL /Gbe/G20 /Gbe /Gbe 10 /Gbe ns 1-bit DA converter Characteristic Symbol Test Circuit Test Condition Min Typ. Max Unit Total harmony distortion THD /G2b N /Gbe 1 kHz sine wave, full-scale input /Gbe /G2d85 /G2d78 S/N ratio S/N /Gbe/G20 /Gbe 90 98 /Gbe Dynamic range DR /Gbe/G201 kHz sine wave, based on /G2d60dB input/G20 85 90 /Gbe/G20 Crosstalk CT /Gbe/G201 kHz sine wave, full-scale input /Gbe /G2d90 /G2d85 dB Analog output level DAC out /Gbe/G201 kHz sine wave, full-scale input 1200 1250 1300 mVrms

Characteristic Symbol Test Circuit Test Condition Min Typ. Max Unit Input pull-down resistance R IN2 /Gbe (TESTC, TESTM) /Gbe 10 /Gbe k /G57 XI amp feedback resistance R fXT1 /Gbe/G20(XI-XO)/G20 1.0 2.0 4.0 M /G57 XO output resistance R out1 /Gbe/G20(XO) /Gbe 0.5 /Gbe k /G57 /Gbe/G20When 4.5 MHz crystal set, (MXI-MXO) 0.5 1.0 2.5 MXI amp feedback resistance RfXT2 /Gbe/G20When 75 kHz crystal set, (MXI-MXO)/G20/Gbe 10 /Gbe M/G57 MXO output resistance R out2 /Gbe/G20(MXO)/G20/Gbe 2.0 /Gbe k /G57 /Gbe 10 /Gbe /Gbe 5.0 /Gbe /Gbe 2.5 /Gbe Zin1 /Gbe/G20Set resistance by (RFI) CD command/G20 /Gbe 1.25 /Gbe Input resistance Zin2 /Gbe/G20(TEZI) /Gbe 10 /Gbe k/G57

Weight: 1.6 g (typ.)

/Gb7/G20TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. /Gb7/G20The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. /Gb7/G20The products described in this document are subject to the foreign exchange and foreign trade laws. /Gb7/G20The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. /Gb7/G20The information contained herein is subject to change without notice. 000707EBARESTRICTIONS ON PRODUCT USE