TC7135CBU

TC7135 TELCOM | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 13

Technical content

3-113TELCOM SEMICONDUCTOR, INC. GENERAL DESCRIPTION The TC7135 4-1/2 digit analog-to-digital converter (ADC) offers 50 ppm (1 part in 20,000) resolution with a maximum nonlinearity error of 1 count. An auto-zero cycle reduces zero error to below 10 µV and zero drift to 0.5 µV/°C. Source impedance errors are minimized by a 10 pA maximum input current. Roll-over error is limited to ±1 count. By combining the TC7135 with a TC7211A (LCD) or TC7212A (LED) driver, a 4-1/2 digit display DVM or DPM can be constructed. Overrange and underrange signals support automatic range switching and special display blanking/flash- ing applications. Microprocessor-based measurement systems are sup- ported by BUSY, STROBE, and RUN/HOLD control signals. Remote data acquisition systems with data transfer via UARTs are also possible. The additional control pins and multiplexed BCD outputs make the TC7135 the ideal converter for dis- play or microprocessor-based measurement systems. TC7135

ORDERING INFORMATION

Part No. Package Range TC7135CBU 64-Pin Plastic 0 °C to +70°C Flat Package TC7135CLI 28-Pin PLCC 0 °C to +70°C TC7135CPI 28-Pin Plastic DIP 0 °C to +70°C TC7135 –5V V REF IN ANALOG COMMON UR OR STROBE RUN/HOLD DGND POL CLOCK BUSY 0.1 µF 0.47 µF 1 µFANALOG GROUND 100 kΩ 0.1 µFINPUT +5V TC04 +5V 1/4 CD4030 CLOCK IN +5V BP D D D D 4-1/2 DIGIT LCD SEGMENT D R I V E TC7211A SEG OUT OSC GND 36 +5V +5V CD4081 11 61 51 41 2 5 3 4 7 8 13 11 10 9 2 6 CD4054A OPTIONAL CAP

120 Hz = 3 READING/SEC

B B B B 100 kΩ 100 kΩ 6.8 kΩ 1 µF INT OUT AZ IN BUFF OUT C REF C REF –INPUT +INPUT V V + 2,3,4 6–26 37–40 +5V

FEATURES

n Guaranteed Zero Reading for 0V Input n True Polarity Indication at Zero for Null Detection n Multiplexed BCD Data Output n TTL-Compatible Outputs n Differential Input n Control Signals Permit Interface to UARTs and µProcessors n Auto-Ranging Supported With Overrange and Underrange Signals n Blinking Display Visually Indicates Overrange Condition n Interfaces to TC7211A (LCD) and TC7212A (LED) Display Drivers n Available in DIP and Surface-Mount Packages TYPICAL 4-1/2 DIGIT DVM WITH LCD 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER TC7135-10 11/6/96

3-114 TELCOM SEMICONDUCTOR, INC. ELECTRICAL CHARACTERISTICS: TA = +25°C, fCLOCK = 120 kHz, V+ = +5V, V– = –5V (Figure 1) Symbol Parameter Test Conditions Min Typ Max Unit Analog Display Reading With Notes 2 and 3 –0.0000 ±0.0000 +0.0000 Display Zero Volt Input Reading TC Z Zero Reading Temperature V IN = 0V — 0.5 2 µV/°C Coefficient Note 4 TC FS Full-Scale Temperature V IN = 2V — — 5 ppm/ °C Coefficient Notes 4 and 5 NL Nonlinearity Error Note 6 — 0.5 1 Count DNL Differential Linearity Error Note 6 — 0.01 — LSB Display Reading in V IN = VREF +0.9996 +0.9999 +1.0000 Display Ratiometric Operation Note 2 Reading ±FSE ± Full-Scale Symmetry –V IN = +VIN — 0.5 1 Count Error (Roll-Over Error) Note 7 IIN Input Leakage Current Note 3 — 1 10 pA VN Noise Peak-to-Peak Value Not — 15 — µVP-P Exceeded 95% of Time Digital IIL Input Low Current V IN = 0V — 10 100 µA IIH Input High Current V IN = +5V — 0.08 10 µA VOL Output Low Voltage I OL = 1.6 mA — 0.2 0.4 V VOH Output High Voltage B1, B2, B4, B8, D1–D 5 IOH = 1 mA 2.4 4.4 5 V Busy, Polarity, Overrange, IOH = 10 µA 4.9 4.99 5 V Underrange, Strobe fCLK Clock Frequency Note 8 0 120 1200 kHz Power Supply V+ Positive Supply Voltage 4 5 6 V V– Negative Supply Voltage –3 –5 –8 V I+ Positive Supply Current f CLK = 0 Hz — 1 3 mA I– Negative Supply Current f CLK = 0 Hz — 0.7 3 mA PD Power Dissipation f CLK = 0 Hz — 8.5 30 mW NOTES: 1. Limit input current to under 100µA if input voltages exceed supply voltage. 2. Full-scale voltage = 2V. 3. VIN = 0V. ABSOLUTE MAXIMUM RATINGS* (Note 1) + to V– (Note 2) Package Power Dissipation (TA ≤ 70°C) *Static-sensitive device. Unused devices must be stored in conductive material to protect them from static discharge and static fields. Stresses above those listed under "Absolute Maximum Ratings" may cause perma- nent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. 5. External reference temperature coefficient less than 0.01 ppm/°C. 6. –2V ≤ VIN ≤ +2V. Error of reading from best fit straight line. 7. |VIN| = 1.9959. 8. Specification related to clock frequency range over which the TC7135 correctly performs its various functions. Increased errors result at higher operating frequencies. TC7135 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER

3-115TELCOM SEMICONDUCTOR, INC. TC7135CPI (PDIP) RUN/HOLD STROBE OVERRANGE D1 (LSD) BUSY CLOCK IN POLARITY DIGTAL GND UNDERRANGE (LSB) B1 (MSD) D5 V + +INPUT – INPUT C REF C REF BUFF OUT AZ IN INT OUT ANALOG COM REF IN V – B8 (MSB) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TC7135CBU (PFP) (NOTES 1) NC INT OUT NC AZ IN NC C REF NC NC C REF NC –INPUT NC +INPUT NC l NOTES: 1. NC = No internal connection. CLOCK IN RUN/HOLD TC7135CLI (PLCC) AZ IN POLARITY 12 13 14 15 17 18(MSD) (LSB) (MSB) DIGTAL GND BUSY D1 (LSD) BUFF OUT REF CAP – REF CAP + –INPUT V + 4 3 2 1 27 26 28 INT OUT ANALOG COM REF IN V – UR OR STROBE +INPUT BUFF OUT NC BUSY 63 61 60 59 58 57 56 55 54 53 52 51 50 4964 NC NC NC NC NC STROBE RUN/HOLD DGND POL NC CLOCK IN NC NC NC NC NC NC OVERRANGE UNDERRANGE NC V – REF IN ANALOG COM NC NC NC NC NC NC NC NC NC NC NC NC NC NC PIN CONFIGURATIONS TC7135 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER

3-118 TELCOM SEMICONDUCTOR, INC. Table 1. Internal Analog Gate Status would be closed for a negative input signal. condition exists, the phase is extended to 6200 clock cycles. either supply without loss of linearity. referenced to analog common. ence voltage circuits are shown in Figure 5.

3-121TELCOM SEMICONDUCTOR, INC. TC7135 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER POLARITY Output A positive input is registered by a logic "1" polarity signal. The POLARITY output (pin 23) is valid at the beginning of reference integrate and remains valid until determined dur- ing the next conversion. The POLARITY bit is valid even for a zero reading. Signals less than the converter's LSB will have the signal polarity determined correctly. This is useful in null applica- tions. Digit Drive Outputs Digit drive outputs are positive-going signals. Their scan sequence is D 5, D4, D3, D2 and D1 (pins 12, 17, 18, 19 and 20, respectively). All positive signals are 200 clock pulses wide, except D 5, which is 201 clock pulses. All five digits are continuously scanned, unless an overrange condition occurs. In an overrange condition, all digit drives are held low from the final STROBE pulse until the beginning of the next reference-integrate phase. The scanning sequence is then repeated, providing a blinking visual display. BCD Data Outputs The binary coded decimal (BCD) outputs, B 8, B4, B2 and B1 (pins 16, 15, 14 and 13, respectively) are positive true- logic signals. They become active simultaneously with digit drive signals. In an overrange condition, all data bits are logic "0". APPLICATIONS INFORMATION Component Value Selection Integrating Resistor The integrating resistor (RINT) is determined by the full- scale input voltage and output current of the buffer used to charge the integrator capacitor (C INT). Both the buffer ampli- fier and the integrator have a Class A output stage, with 100 µA of quiescent current. A 20 µA drive current gives negli- gible linearity errors. Values of 5 µA to 40 µA give good results. The exact value of R INT for a 20 µA current is easily calculated: R INT = .Full-scale voltage 20 µA Integrating Capacitor The product of RINT and CINT should be selected to give the maximum voltage swing to ensure tolerance build-up will not saturate integrator swing (approximately 0.3V from either supply). For ±5V supplies, and analog common tied to supply ground, a ±3.5V to ±4V full-scale integrator swing is C INT = = . [10,000 x clock period] x IINT Integrator output voltage swing (10,000) (clock period) (20 µA) Integrator output voltage swing Conversion Timing Line Frequency Rejection A signal-integration period at a multiple of the 60 Hz line frequency will maximize 60 Hz "line noise" rejection. A 100 kHz clock frequency will reject 50 Hz, 60 Hz and 400 Hz noise, corresponding to 2.5 readings per second. A very important characteristic of the CINT is that it has low dielectric absorption to prevent roll-over or ratiometric errors. A good test for dielectric absorption is to use the capacitor with the input tied to the reference. This ratiometric condition should read half-scale 0.9999. Any deviation is probably due to dielectric absorption. Polypropylene capacitors give undetectable errors at reasonable cost. Polystyrene and polycarbonate capacitors may also be used in less critical applications. Auto-Zero and Reference Capacitors The size of the auto-zero capacitor (C AZ ) has some influence on system noise. A large capacitor reduces noise. The reference capacitor (C REF ) should be large enough such that stray capacitance from its nodes to ground is negligible. The dielectric absorption of C REF and CAZ is only impor- tant at power-on, or when the circuit is recovering from an overload. Smaller or cheaper capacitors can be used if accurate readings are not required during the first few seconds of recovery. Reference Voltage The analog input required to generate a full-scale output is V IN = 2 VREF . The stability of the reference voltage is a major factor in overall absolute accuracy of the converter. Therefore, it is recommended that high-quality references be used where high-accuracy, absolute measurements are being made. Suitable references are: Part Type Manufacturer TC04 TelCom Semiconductor TC05 TelCom Semiconductor adequate. A 0.10 µF to 0.47 µF is recommended. In general, the value of CINT is given by:

3-122 TELCOM SEMICONDUCTOR, INC. peaks even when the input is shorted. can be digitally subtracted. nonlinearities during the first few counts of the instrument. supply, the clock should have good PSRR. Table 3. Conversion Rate vs Clock Frequency Several sources exist for LCDs and LED displays. Table 2. Line Frequency Rejection

3-123TELCOM SEMICONDUCTOR, INC. auto-zero gives an overload display of 0000 instead of 0001. Figure 9. Negative Supply Voltage Generator

3-124 TELCOM SEMICONDUCTOR, INC. TC7135 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER TYPICAL APPLICATIONS (Cont.) 4-1/2 Digit ADC With Multiplexed Common Anode LED Display 20 19 18 17 12 1121 5 9–15 bc 777 7 TC7135 7447 BLANK MSD ON ZERO D1 D2 D3 D4 D5 INT OUT AZ IN BUFF OUT fIN +INPUT –INPUT ANALOG COMMON V – REF IN POL C REF +5V +5V 0.47 µF 120 kHz ANALOG INPUT 1 µF 100 kΩ 1 µF 4.7 kΩ 1 µF –5V 100 kΩ 100 kΩ 6.8 kΩ D B C A RBI V + C REF TC04 TC04 TC7211A TC7135 INT OUT AZ IN BUFF OUT +INPUT –INPUT ANALOG COMMON REF IN V – POL V + STROBE OR BP GND Q RS D CLK CD4071 +5V 1/4 CD4030 4-1/2 DIGIT LCD SEGMENT DRIVE +5V +5V –5V 1/4 CD4081 1/2 CD4030 CD4081 1/4 CD4030 CD4013 6.8 kΩ 100 kΩ 100 kΩ 100 kΩ 0.47 µF 1 µF ANALOG INPUT 120 kHz 22 fIN 4-1/2 Digit ADC Interfaced to LCD With Digit Blanking on Overrange

3-125TELCOM SEMICONDUCTOR, INC. TC7135 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER TYPICAL APPLICATIONS (Cont.) 4-1/2 Digit ADC With Multiplexed Common Cathode LED Display TC04 REF IN ANALOG GND INT OUT AZ IN BUFF OUT C REF +5V –5V6.8V UR DGND POLARITY OR STROBE RUN/HOLD CLK IN BUSY SET VREF = 1V 1.22V 100 kΩ ANALOG GND 0.47 µF 100 kΩ 1 µF kΩ 150Ω +5V 150Ω +5V CD4513 BE 1 µF TC7135 –INPUT +INPUT D5 (MSD) B1 (LSB) (LSD) D1 (MSB) B8 100 kΩ SIG IN 0.1 µF +5V fO = 120 kHz C REF V – TC7135 DATA BUS CONTROL ADDRESS BUS 6522 -VIA- PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 CA1 CA2 PB5 PB4 PB0 PB3 PB2PB1 CHANNEL SELECTION GAIN SELECTION SEL 157 POL OR UR STB R/H V+ REF CAP BUF AZ INT INPUT+ VR INPUT– ANALOG COMMON DGND REF VOLTAGE GAIN: 10, 20, 50, 100 15V 15V CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 DIFFERENTIAL MULTIPLEXER DG529 D A D B WR A 1 A 0 EN 5V+ fIN fIN LH0084 4-Channel Data Acquisition System