TC7116CLW

TC7116 TELCOM | Alldatasheet

Document overview

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Technical content

3-203TELCOM SEMICONDUCTOR, INC. 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD VREF TC7116/A 9VVREF 3334 24 kΩ 1 kΩ 39 38 40 0.47 µF 0.1 µF V – 1OSC3OSC2OSC TO ANALOG COMMON (PIN 32)

3 CONVERSIONS/SEC

100 kΩ 47 kΩ 0.22 µF 0.01 µFANALOG INPUT C REF–C REF+ V IN+ V IN– ANALOG COMMON VINT VBUFF C AZ SEGMENT DRIVE 2–19 22–25 POL BP/GND V + MINUS SIGN BACKPLANE DRIVE R OSC 100 pF LCD DISPLAY (TC7116/7116A) OR COMMON ANODE LED DISPLAY (TC7117/7117A) 1 MΩ HLDR DISPLAY HOLD 100 mV TC7117/A +

FEATURES

n Low Temperature Drift Internal Reference n Display Hold Function n Directly Drives LCD or LED Display n Guaranteed Zero Reading With Zero Input n Low Noise for Stable n Auto-Zero Cycle Eliminates Need for Zero Adjustment Potentiometer n True Polarity Indication for Precision Null

Applications

n Convenient 9V Battery Operation (TC7116/TC7116A) n High Impedance CMOS Differential Inputs.... 1012Ω GENERAL DESCRIPTION The TC7116A/TC7117A are 3-1/2 digit CMOS analog- to-digital converters (ADCs) containing all the active components necessary to construct a 0.05% resolution measurement system. Seven-segment decoders, polarity and digit drivers, voltage reference, and clock circuit are integrated on-chip. The TC7116A drives liquid crystal displays (LCDs) and includes a backplane driver. The TC7117A drives common anode light emitting diode (LED) displays directly with an 8-mA drive current per segment. These devices incorporate a display hold (HLDR) function. The displayed reading remains indefinitely, as long as HLDR is held high. Conversions continue, but output data display latches are not updated. The reference low input (V –REF ) is not available as it is with the TC7106/ 7107. V–REF is tied internally to analog common in the TC7116A/7117A devices. The TC7116A/7117A reduces linearity error to less than 1 count. Roll-over error (the difference in readings for equal magnitude but opposite polarity input signals) is below ±1 count. High-impedance differential inputs offer 1 pA leakage current and a 10 12Ω input impedance. The 15 µVP-P noise performance guarantees a “rock solid” reading. The auto-zero cycle guarantees a zero display reading with a 0V input. The TC7116A and TC7117A feature a precision, low- drift internal reference, and are functionally identical to the TC7116/TC7117. A low-drift external reference is not normally required with the TC7116A/TC7117A. AVAILABLE PACKAGES 40-Pin Plastic DIP 40-Pin CerDIP 44-Pin Plastic Quad Flat Package Formed Leads 44-Pin Plastic Chip Carrier PLCC Package Temperature Code Package Range CKW 44-Pin PQFP 0 °C to +70°C CLW 44-Pin PLCC 0 °C to +70°C CPL 40-Pin Plastic DIP 0 °C to +70°C IJL 40-Pin CerDIP – 25 °C to +85°C Figure 1. Typical TC7116/A/7/A Operating Circuit

ORDERING INFORMATION

6 = LCD 7 = LED A or blank* R (reversed pins) or blank (CPL pkg. only) * "A" parts have an improved reference TC Package Code (see below):

3-204 TELCOM SEMICONDUCTOR, INC. 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLDTC7116 TC7116A TC7117 TC7117A ABSOLUTE MAXIMUM RATINGS* Supply Voltage Clock Input Package Power Dissipation, TA ≤ 70°C (Note 2) Operating Temperature *Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to Absolute Maximum Rating Conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Note 3) Parameter Test Conditions Min Typ Max Unit Zero Input Reading V IN = 0V — ±0 — Digital Full Scale = 200 mV Reading Ratiometric Reading V IN = VREF 999 999/1000 1000 Digital VREF = 100 mV Reading Roll-Over Error (Difference in –V IN = +VIN ≅ 200 mV or ≈ 2V – 1 ±0.2 +1 Counts Reading for Equal Positive and Negative Readings Near Full Scale) Linearity (Maximum Deviation From Full Scale = 200 mV or 2V – 1 ±0.2 +1 Counts Best Straight Line Fit) Common-Mode Rejection Ratio (Note 4) V CM = ±1V, VIN = 0V — 50 — µV/V Full Scale = 200 mV Noise (Peak-to-Peak Value Not V IN = 0V — 15 — µV Exceeded 95% of Time) Full Scale = 200 mV Leakage Current at Input V IN = 0V — 1 10 pA Zero Reading Drift V IN = 0V “C” Device: 0°C to +70°C — 0.2 1 µV/°C “I” Device: –25°C to +85°C— 1 2 µv/°C Scale Factor Temperature Coefficient V IN = 199 mV “C” Device: 0°C to +70°C — 1 5 ppm/ °C (Ext Ref = 0 ppm/°C) “I” Device: –25°C to +85°C — — 20 ppm/ °C Input Resistance, Pin 1 Note 6 30 70 — k Ω VIL, Pin 1 TC7116/A Only — — Test +1.5 V VIL, Pin 1 TC7117/A Only — — GND +1.5 V VIH, Pin 1 Both V + – 1.5 — — V Supply Current (Does Not Include V IN = 0V — 0.8 1.8 mA LED Current for 7117/A) Analog Common Voltage 25 k Ω Between Common 2.4 3.05 3.35 V (With Respect to Positive Supply) and Positive Supply Temperature Coefficient of Analog Common "C" Device: 0°C to +70°C (With Respect to Positive Supply) TC7116A/TC7117A — 20 50 ppm/ °C TC7116/TC7117 — 80 — ppm/ °C

3-205TELCOM SEMICONDUCTOR, INC. 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD TC7116 TC7116A TC7117 TC7117A ELECTRICAL CHARACTERISTICS (Cont.) Parameter Test Conditions Min Typ Max Unit Temperature Coefficient of Analog Common "I" Device: –25°C to +85°C — — 75 ppm/ °C (With Respect to Positive Supply) 25 k Ω Between Common and Positive Supply (TC7116A/TC7117A) TC7116/TC7116A ONLY Peak-to-Peak V + to V– = 9V 4 5 6 V Segment Drive Voltage (Note 5) TC7116/TC7116A ONLY Peak-to-Peak V + to V– = 9V 4 5 6 V Backplane Drive Voltage (Note 5) TC7117/TC7117A ONLY Segment V + = 5V 5 8 — mA Sinking Current (Except Pin 19) Segment Voltage = 3V TC7117/TC7117A ONLY Segment V + = 5V 10 16 — mA Sinking Current (Pin 19 Only) Segment Voltage = 3V NOTES: 1. Input voltages may exceed supply voltages, provided input current is limited to ±100 µA. 2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 3. Unless otherwise noted, specifications apply at TA = +25°C, fCLOCK = 48 kHz. TC7116/TC7116A and TC7117/TC7117A are tested in the circuit of Figure 1. 4. Refer to "Differential Input" discussion. 5. Backplane drive is in-phase with segment drive for “OFF” segment, 180° out-of-phase for “ON” segment. Frequency is 20 times conversion rate. Average DC component is less than 50 mV. 6. The TC7116/TC7116A logic inputs have an internal pull-down resistor connected from HLDR, pin 1 to TEST, pin 37. The TC7117/TC7117A logic inputs have an internal pull-down resistor connected from HLDR, pin 1 to GND, pin 21.

3-206 TELCOM SEMICONDUCTOR, INC. TC7116 TC7116A TC7117 TC7117A BP/ GND COMMON 18 19 20 21 23 24 AB 4 POL NC IN HI NC IN LOB 6543 1 4 4 2 A OSC OSC

42 OSC

41 TEST

40 REF HI

F E G A C G

3214 A/Z2

3115 BUFF2

3016 INTE

C D F A B TC7116CLW TC7116ACLW TC7117CLW TC7117ACLW (PLCC) V – C REF C REF B 1 C 1 D 1 G 1 E 1 BP/ GND 1 NC TC7116CKW TC7116ACKW TC7117CKW TC7117ACKW 12 13 14 15 17 18 G 44 43 42 41 39 3840 REF HI COMMON A/Z BUFF INT 34 V 19 20 21 22 D 268 259 2410 2311 IN HI C OSC TEST NC NC HLDR D 2 C 2 B 2 A 2 E 2 NC OSC 2 OSC 1 REFC REFC IN LO A 3 G 3 POL AB 4 (FLAT PACKAGE) D 1 C 1 B 1 A 1 G 1 E 1 TC7116IPL TC7116AIPL TC7117CPL TC7117ACPL (PDIP) OSC 1 TEST V COMMON C AZ HLDR D C 2 B 2 A 2 E 2 D 3 B 3 E 3 AB 4 (MINUS SIGN) 10's 100's 1000's (TC7116/7117) (TC7116A/TC7117A) 100's OSC 2 OSC 3 REF C + REF C – REF V + IN V – IN VBUFF V INT V – G C A G BP/GNDPOL D 1 C 1 B 1 A 1 G 1 E 1 1's NOTES: 1. NC = No internal connection. 2. Pins 9, 25, 40, and 56 are connected to the die substrate. The potential at these pins is approximately V . No external connections should be made. HLDR TC7116IJL TC7116AIJL TC7117IJL TC7117AIJL (CerDIP) OSC 1 TEST V COMMON C AZ HLDR D C 2 B 2 A 2 E 2 D 3 B 3 E 3 AB 4 (MINUS SIGN) 10's 100's 1000's (TC7116/7117) (TC7116A/TC7117A) 100's OSC 2 OSC 3 REF C + REF C – REF V + IN V – IN VBUFF V INT V – G C A G BP/GNDPOL D 1 C 1 B 1 A 1 G 1 E 1 1's PIN CONFIGURATIONS 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD

3-207TELCOM SEMICONDUCTOR, INC. PIN DESCRIPTION 40-Pin PDIP/ 44-Pin 40-PinCerDIP Plastic Quad Pin Number Flat Package Normal Pin Number Symbol Description 1 8 HLDR Hold pin, Logic 1 holds present display reading. 29 D 1 Activates the D section of the units display. 31 0 C 1 Activates the C section of the units display. 41 1 B 1 Activates the B section of the units display. 51 2 A 1 Activates the A section of the units display. 61 3 F 1 Activates the F section of the units display. 71 4 G 1 Activates the G section of the units display. 81 5 E 1 Activates the E section of the units display. 91 6 D 2 Activates the D section of the tens display. 10 17 C 2 Activates the C section of the tens display. 11 18 B 2 Activates the B section of the tens display. 12 19 A 2 Activates the A section of the tens display. 13 20 F 2 Activates the F section of the tens display. 14 21 E 2 Activates the E section of the tens display. 15 22 D 3 Activates the D section of the hundreds display. 16 23 B 3 Activates the B section of the hundreds display. 17 24 F 3 Activates the F section of the hundreds display. 18 25 E 3 Activates the E section of the hundreds display. 19 26 AB 4 Activates both halves of the 1 in the thousands display. 20 27 POL Activates the negative polarity display. 21 28 BP LCD backplane drive output (TC7116/TC7116A). GND Digital ground (TC7117/TC7117A). 22 29 G 3 Activates the G section of the hundreds display. 23 30 A 3 Activates the A section of the hundreds display. 24 31 C 3 Activates the C section of the hundreds display. 25 32 G 2 Activates the G section of the tens display. 26 34 V – Negative power supply voltage. 27 35 V INT Integrator output. Connection point for integration capacitor. See Integration Capacitor section for additional details. 28 36 V BUFF Integration resistor connection. Use a 47 kΩ resistor for 200 mV full-scale range and a 470 kΩ resistor for 2V full-scale range. 29 37 C AZ The size of the auto-zero capacitor influences system noise. Use a 0.47 µF capacitor for 200 mV full scale and a 0.047 µF capacitor for 2V full scale. See Auto-Zero Capacitor paragraph for more details. 30 38 V –IN The analog LOW input is connected to this pin. 31 39 V +IN The analog HIGH input is connected to this pin. 39 40 COMMON This pin is primarily used to set the analog common- mode COMMON voltage for battery operation or in systems where the input signal is referenced to the power supply. See Analog Common paragraph for more details. It also acts as a reference voltage source. TC7116 TC7116A TC7117 TC7117A 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD

3-208 TELCOM SEMICONDUCTOR, INC. TC7116 TC7116A TC7117 TC7117A PIN DESCRIPTION (Cont.) 40-Pin CerDIP 44-Pin 40-Pin PDIP Plastic Quad Pin Number Flat Package Normal Pin Number Symbol Description 33 41 C –REF See pin 34. 34 42 C +REF A 0.1 µF capacitor is used in most applications. If a large, common-mode voltage exists (e.g., the VIN– pin is not at analog common), and a 200 mV scale is used, a 1 µF capacitor is recommended and will hold the roll-over error to 0.5 count. 35 43 V + Positive power supply voltage. 36 44 V +REF The analog input required to generate a full-scale output (1999 counts). Place 100 mV between pins 32 and 36 for 199.9 mV full scale. Place 1V between pins 32 and 36 for 2V full scale. See paragraph on Reference Voltage. 37 3 TEST Lamp test. When pulled HIGH (to V +), all segments will be turned on and the display should read –1888. It may also be used as a negative supply for externally- generated decimal points. See Test paragraph for more details. 38 4 OSC 3 See pin 40. 39 6 OSC 2 See pin 40. 40 7 OSC 1 Pins 40, 39 and 38 make up the oscillator section. For a 48 kHz clock (3 readings per sec), connect pin 40 to the junction of a 1 00 kΩ resistor and a 1 00 pF capacitor. The 100 kΩ resistor is tied to pin 39 and the 100 pF capacitor is tied to pin 38. 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD

3-211TELCOM SEMICONDUCTOR, INC. about 10 mA under these conditions. Figure 9 is the digital section of the TC7117/TC7117A. drive common anode LED displays. Figure 8. TC7116/TC7116A Digital Section

2 OSC 3OSC 1

3-212 TELCOM SEMICONDUCTOR, INC. 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLDTC7116 TC7116A TC7117 TC7117A TC7117 TC7117A THOUSANDS HUNDREDS TENS UNITS OSC V DIGITAL GND TEST TO SWITCH DRIVERS FROM COMPARATOR OUTPUT CLOCK 7-SEGMENT DECODE 7-SEGMENT DECODE 7-SEGMENT DECODE 40 38 0.5 mA 8 mA 500Ω V + LATCH ~70 kΩ System Timing The clocking method used for the TC7116/TC7116A and TC7117/TC7117A is shown in Figure 9. Three clocking methods may be used: (1) An external oscillator connected to pin 40. (2) A crystal between pins 39 and 40. (3) An RC network using all three pins. The oscillator frequency is 4 4 before it clocks the decade counters. It is then further divided to form the three convert-cycle phases: signal integrate (1000 counts), refer- ence deintegrate (0 to 2000 counts), and auto-zero (1000 to 3000 counts). For signals less than full scale, auto-zero gets the unused portion of reference deintegrate. This makes a complete measure cycle of 4000 (16,000 clock pulses) independent of input voltage. For 3 readings per second, an oscillator frequency of 48 kHz would be used. To achieve maximum rejection of 60-Hz pickup, the signal-integrate cycle should be a multiple of 60 Hz. Oscil- lator frequencies of 240 kHz, 120 kHz, 80 kHz, 60 kHz, 48 kHz, 40 kHz, etc. should be selected. For 50 Hz rejection, oscillator frequencies of 200 kHz, 100 kHz, 66-2/3 kHz, 50 kHz, 40 kHz, etc. would be suitable. Note that 40 kHz (2.5 readings per second) will reject both 50 Hz and 60 Hz. HOLD Reading Input When HLDR is at a logic HIGH the latch will not be updated. Analog-to-digital conversions will continue but will not be updated until HLDR is returned to LOW. To continu- ously update the display, connect to test (TC7116/TC7116A) or ground (TC7117/TC7117A), or disconnect. This input is CMOS compatible with 70 kΩ typical resistance to TEST (TC7116/TC7116A) or ground (TC7117/TC7117A).Figure 9. TC7117/TC7117A Digital Section

3-213TELCOM SEMICONDUCTOR, INC. 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD TC7116 TC7116A TC7117 TC7117A COMPONENT VALUE SELECTION Auto-Zero Capacitor The size of the auto-zero capacitor has some influ- ence on system noise. For 200 mV full scale, where noise is very important, a 0.47 µF capacitor is recommended. On the 2V scale, a 0.047 µF capacitor increases the speed of recovery from overload and is adequate for noise on this scale. Reference Capacitor A 0.1 µF capacitor is acceptable in most applications. However, where a large common-mode voltage exists (i.e., the V –IN pin is not at analog common), and a 200-mV scale is used, a larger value is required to prevent roll-over error. Generally, 1 µF will hold the roll-over error to 0.5 count in this instance. Integrating Capacitor The integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance build-up will not saturate the integrator swing (approximately 0.3V from either supply). In the TC7116/TC7116A or the TC7117/ TC7117 A, when the analog common is used as a reference, a nominal ±2V full- scale integrator swing is acceptable. For the TC7117/TC7117A, with ±5V supplies and analog com- mon tied to supply ground, a ±3.5V to ±4V swing is nominal. For 3 readings per second (48 kHz clock), nominal values for C INT are 0.22 µ1F and 0.10 µF, respectively. If different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the output swing. The integrating capacitor must have low dielectric ab- sorption to prevent roll-over errors. Polypropylene capaci- tors are recommended for this application. Integrating Resistor Both the buffer amplifier and the integrator have a class A output stage with 100 µA of quiescent current. They can supply 20 µA of drive current with negligible nonlinearity. The integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2V full scale, 470 kΩ is near optimum and, similarly, 47 kΩ for 200 mV full scale. Oscillator Components For all frequency ranges, a 100-kΩ resistor is recom- mended; the capacitor is selected from the equation: For a 48 kHz clock (3 readings per second), C = 100 pF.Figure 10. Negative Power Supply Generation With TC7660 VREF +V + TC7117 TC7117A 10 µF V IN V IN COM GND 10 µF V IN V – (–5V)5 +5V TC7660 26 TC04 LED DRIVE Reference Voltage To generate full-scale output (2000 counts), the analog input requirement is VIN = 2 VREF . Thus, for the 200 mV and 2V scale, VREF should equal 100 mV and 1V, respectively. In many applications, where the ADC is connected to a transducer, a scale factor exists between the input voltage and the digital reading. For instance, in a measuring system the designer might like to have a full-scale reading when the voltage from the transducer is 700 mV. Instead of dividing the input down to 200 mV, the designer should use the input voltage directly and select V REF = 350 mV. Suitable values for integrating resistor and capacitor would be 120 kΩ and 0.22 µF. This makes the system slightly quieter and also avoids a divider network on the input. The TC7117/TC7117A, with ±5V supplies, can accept input signals up to ±4V. Another advantage of this system is when a digital reading of zero is desired for V IN ≠ 0. Temperature and weighing systems with a variable tare are examples. This offset reading can be conveniently generated by connecting the voltage transducer between V +IN and analog common, and the variable (or fixed) offset voltage between analog com- mon and V –IN. TC7117/TC7117A POWER SUPPLIES The TC7117/TC7117A are designed to operate from ±5V supplies. However, if a negative supply is not available, it can be generated with a TC7660 DC-to-DC converter and two capacitors. Figure 10 shows this application. In selected applications, a negative supply is not re- quired. The conditions for using a single +5V supply are: (1) The input signal can be referenced to the center of the common-mode range of the converter. (2) The signal is less than ±1.5V. (3) An external reference is used. RCf = .