TC7109CLW

TC7109 TELCOM | Alldatasheet

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3-91TELCOM SEMICONDUCTOR, INC.

FEATURES

n Zero-Integrator Cycle for Fast Recovery From Input Overloads n Eliminates Cross -Talk in Multiplexed Systems n 12-Bit Plus Sign Integrating A/D Converter With Overrange Indication n Sign Magnitude Coding Format n True Differential Signal Input and Differential Reference Input n No Zero Adjustment Needed n TTL-Compatible, Byte-Organized Tri-State Outputs n UART Handshake Mode for Simple Serial Data Transmission

ORDERING INFORMATION

A or blank* Package Temperature Code Package Range CKW 44-Pin PQFP 0 °C to +70°C CLW 44-Pin PLCC 0 °C to +70°C CPL 40-Pin Plastic DIP 0 °C to +70°C IJL 40-Pin CerDIP –25 °C to +85°C * The "A" version has a higher IOUT on the digital lines. TC7109 TC7109A 12-BIT µP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS GENERAL DESCRIPTION The TC7109A is a 12-bit plus sign, CMOS low-power analog-to-digital converter (ADC). Only eight passive com- ponents and a crystal are required to form a complete dual-slope integrating ADC. The improved V OH source current TC7109A has fea- tures that make it an attractive per-channel alternative to analog multiplexing for many data acquisition applica- tions. These features include typical input bias current of 1pA drift of less than 1µV/°C, input noise typically 15µV P-P, and auto-zero. True differential input and reference allow measurement of bridge-type transducers such as load cells, strain gauges, and temperature transducers. The TC7109A provides a versatile digital interface. In the direct mode, chip select and HIGH/LOW byte enables control parallel bus interface. In the handshake mode, the TC7109A will operate with industry-standard UARTs in controlling serial data transmission — ideal for remote data logging. Control and monitoring of conversion timing is provided by the RUN/HOLD input and STATUS output. For applications requiring more resolution, see the TC500, 15-bit plus sign ADC data sheet. The TC7109A has improved overrange recovery per- formance and higher output drive capability than the origi- nal TC7109. All new (or existing) designs should specify the TC7109A wherever possible. FUNCTIONAL BLOCK DIAGRAM INPUT HI AZBUFF C AZ INT BUFFER INTEGRATOR AZ ZI AZ ZI DE (+) AZ INT AZ COMPARATOR COMP OUT 3130 C REF AZ DE (–) ZI COMMON INPUT LO INT 37 36 REF IN DE (–) DE (–) DE (+) R INT C INT 3839 REF CAP REF CAP ZI 6.2V 10 µA 28 40 V+V – REF OUT 17 3 4 5 6 7 8 9 10 11 12 13 14 22 6 2 2 23 24 25 21 TO ANALOG SECTION COMP OUT AZ INT DE (–) ZI CONVERSION CONTROL LOGIC OSCILLATOR AND CLOCK CIRCUITRY HANDSHAKE LOGIC 15 16 LBEN HBEN CE/LOAD GND

14 LATCHES

16 THREE-STATE OUTPUTS

+ + REF IN– B12 B11 B10 LATCH CLOCK TC7109/A-7 11/6/96

3-92 TELCOM SEMICONDUCTOR, INC. ABSOLUTE MAXIMUM RATINGS* Reference Input Voltage (Low to High (Note 1) .. V+ to V– Power Dissipation, T A < 70°C, (Note 3) Operating Temperature Range ELECTRICAL CHARACTERISTICS: All parameters with V+ = +5V, V– = –5V, GND = 0V, TA = +25°C, unless otherwise indicated. Symbol Parameter Test Conditions Min Typ Max Unit Analog Overload Recovery Time — 0 1 Measurement (TC7109A) Cycle Zero Input Reading V IN = 0V – 0000 8 ±00008 +00008 Octal Reading Full Scale = 409.6 mV Ratio Metric Reading V IN = VREF 37778 37778 40008 Octal Reading VREF = 204.8 mV 4000 8 NL Nonlinearity (Max Deviation Full Scale = 409.6 mV to –1 ±0.2 +1 Count From Best Straight Line Fit) 2.048V Over Full Operating Temperature Range Roll-Over Error (Difference in Full Scale = 409.6 mV to –1 ±0.02 +1 Count Reading for Equal Positive and 2.048V Over Full Operating Negative Inputs Near (Full Scale) Temperature Range CMRR Input Common-Mode V CM ±1V, VIN = 0V — 50 — µV/V Rejection Ratio Full Scale = 409.6 mV VCMR Common-Mode Voltage Input High, Input Low, V –+1.5 — V +–1 V Range and Common Pins eN Noise (P-P Value Not V IN = 0V — 15 — µV Exceeded 95% of Time) Full Scale = 409.6 mV IIN Leakage Current at Input V IN, All Packages: +25°C— 1 1 0 p A C Device: 0°C ≤ TA ≤ +70°C 20 100 pA I Device: –25°C ≤ TA ≤ +85°C 100 250 pA M Device: –55°C ≤ TA ≤ +125°C2 5 n A TC ZS Zero Reading Drift V IN = 0V — 0.2 1 µV/°C TC FS Scale-Factor V IN = 408.9 mV = >77708 —15 µV/°C Temperature Coefficient Reading, Ext Ref = 0 ppm/ °C I+ Supply Current V IN = 0V, Crystal Oscillator — 700 1500 µA (V+ to GND) 3.58 MHz Test Circuit IS Supply Current (V+ to V–) Pins 2–21, 25, 26, 27, 29 Open — 700 1500 µA *Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to Absolute Maximum Rating Conditions for extended periods may affect device reliability. NOTES: 1. Input voltages may exceed supply voltages if input current is limited to ±100 µA. 2. Connecting any digital inputs or outputs to voltages greater than V + or less than GND may cause destructive device latch- up. Therefore, it is recommended that inputs from sources other than the same power supply should not be applied to the TC7109A before its power supply is established. In multiple supply systems, the supply to the device should be activated first. 3. This limit refers to that of the package and will not occur during normal operation. TC7109 TC7109A 12-BIT µP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

3-93TELCOM SEMICONDUCTOR, INC. ELECTRICAL CHARACTERISTICS (Cont.) Symbol Parameter Test Conditions Min Typ Max Unit VREF Ref Out Voltage Referenced to V +, 25 kΩ – 2.4 – 2.8 – 3.2 V Between V+ and Ref Out TC REF Ref Out Temperature 25 k Ω Between V+ and Ref Out — 80 — ppm/ °C Coefficient 0 °C ≤ TA ≤ +70°C Digital VOH Output High Voltage TC7109: I OUT = 100 µA 3.5 4.3 — V TC7109A: IOUT = 700 µA Pins 3–16, 18, 19, 20 VOL Output Low Voltage I OUT = 1.6 mA — 0.2 0.4 V Output Leakage Current Pins 3–16 High Impedance — ±0.01 ±1 µA Control I/O Pins 18, 19, 20 V OUT = V+–3V — 5 — µA Pull-Up Current Mode Input at GND Control I/O Loading HBEN, Pin 19; LBEN, Pin 18 — — 50 pF VIH Input High Voltage Pins 18–21, 26, 27 2.5 — — V Referenced to GND VIL Input Low Voltage Pins 18-21, 26, 27 — — 1 V Referenced to GND Input Pull-Up Current Pins 26, 27; V OUT = V+–3V — 5 — µA Pins 17, 24; VOUT = V+–3V 25 µA Input Pull-Down Current Pin 21; V OUT = GND = +3V — 1 — µA Oscillator Output Current, High VOUT = 2.5V — 1 — mA Oscillator Output Current, Low VOUT = 2.5V — 1.5 — mA Buffered Oscillator Output V OUT = 2.5V — 2 — mA Current, High Buffered Oscillator Output V OUT = 2.5V — 5 — mA Current, Low tW Mode Input Pulse Width 60 — — nsec HANDLING PRECAUTIONS: These devices are CMOS and must be handled correctly to prevent damage. Package and store only in conductive foam, anti-static tubes, or other conducting material. Use proper anti-static handling procedures. Do not connect in circuits under "power-on" conditions, as high transients may cause permanent damage. TC7109 TC7109A 12-BIT µP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

3-94 TELCOM SEMICONDUCTOR, INC. TC7109 TC7109A 12-BIT µP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS PIN CONFIGURATIONS NC = NO INTERNAL CONNECTION TC7109A TC7109 (CPL, IJL, MJL) (PDIP) (CerDIP) STATUS POL OR TEST LBEN HBEN CE/LOAD REF OUT IN HI IN LO COMMON V + SEND RUN/HOLD BUFF OSC OUT OSC SEL OSC IN MODE GND OSC OUT V – BUFF AZ INT REF IN+ REF CAP + REF CAP – REF IN– 12B 11B 10B INT IN HI 12 13 14 15 17 18 BUFF OSC OUT AZ NC BUFF 44 43 42 41 39 3840 GND 37 36 35 34 19 20 21 22

268 REF OUT

2410 SEND

B TC7109ACKW TC7109CKW RUN/HOLD V – COMMON IN LO REF IN+ REF CAP + REF CAP – REF IN– V + STATUS POL OR 11B 10B NC OSC SEL OSC OUT OSC IN MODE NC CE/LOAD HBEN LBEN TEST 12B (PQFP) 33 INT IN HI 18 19 20 21 23 24 BUFF OSC OUT AZ NC BUFF 6543 1 4 4 2 GND 43 42 41 40 25 26 27 28

3214 REF OUT

3016 SEND

B TC7109ACLW TC7109CLW (PLCC) RUN/HOLD V – COMMON IN LO REF IN+ REF CAP + REF CAP – REF IN– V + STATUS POL OR 11B 10B NC OSC SEL OSC OUT OSC IN MODE NC CE/LOAD HBEN LBEN TEST 12B

3-95TELCOM SEMICONDUCTOR, INC. TC7109/A PIN DESCRIPTION 40-Pin PDIP Pin Number Symbol Description 1 GND Digital ground, 0V, ground return for all digital logic. 2 STATUS Output HIGH during integrate and deintegrate until data is latched. Output LOW when analog section is in auto-zero or zero-integrator configuration. 3 POL Polarity — High for positive input. 4 OR Overrange — High if overranged. 5B 12 Bit 12 (Most Significant Bit) 6B 11 Bit 11 7B 10 Bit 10 8B 9 Bit 9 9B 8 Bit 8

10 B 7 Bit 7

11 B 6 Bit 6

12 B 5 Bit 5

13 B 4 Bit 4

14 B 3 Bit 3

15 B 2 Bit 2

16 B 1 Bit 1 (Least Significant Bit)

17 TEST Input High — Normal operation. Input LOW — Forces all bit outputs HIGH. Note: This input is used for test purposes only.

18 Low-Byte Enable — With MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW,

taking this pin LOW activates low-order byte outputs, B1–B8. With MODE (Pin 21) HIGH, this pin serves as low-byte flag output used in handshake mode. See Figures 7, 8, and 9.

19 High-Byte Enable — With MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW,

taking this pin LOW activates high-order byte outputs, B9–B12, POL, OR. With MODE (Pin 21) HIGH, this pin serves as high-byte flag output used in handshake mode. See Figures 7, 8, and 9.

20 Chip Enable/Load — With MODE (Pin 21) LOW, CE/LOAD serves as a master

output enable. When HIGH, B1–B12, POL, OR outputs are disabled. When MODE (Pin 21) is HIGH, a load strobe is used in handshake mode. See Figure 7, 8, and 9.

21 MODE Input LOW — Direct output mode where CE/LOAD (Pin 20), HBEN (Pin 19), and

LBEN (Pin 18) act as inputs directly controlling byte outputs. Input Pulsed HIGH — Causes immediate entry into handshake mode and output of data as in Figure 9. Input HIGH — Enables CE/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin 18) as outputs, handshake mode will be entered and data output as in Figures 7 and 8 at conversions completion.

22 OSC IN Oscillator Input

23 OSC OUT Oscillator Output

24 OSC SEL Oscillator Select — Input HIGH configures OSC IN, OSC OUT, BUF OSC OUT as

RC oscillator — clock will be same phase and duty cycle as BUF OSC OUT. Input LOW configures OSC IN, OSC OUT for crystal oscillator — clock frequency will be 1/58 of frequency at BUF OSC OUT.

25 BUF OSC OUT Buffered Oscillator Output

26 Input HIGH — Conversions continuously performed every 8192 clock pulses. Input LOW — Conversion in progress completed; converter will stop in auto-zero seven counts before integrate. HBEN CE/LOAD RUN/HOLD All Three-State Data Bits TC7109 TC7109A 12-BIT µP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS LBEN

3-96 TELCOM SEMICONDUCTOR, INC.

27 SEND Input — Used in handshake mode to indicate ability of an external device to

28 V – Analog Negative Supply — Nominally –5V with respect to GND (Pin 1). 29 REF OUT Reference Voltage Output — Nominally 2.8V down from V + (Pin 40).

30 BUFFER Buffer Amplifier Output

31 AUTO-ZERO Auto-Zero Node — Inside foil of CAZ . 32 INTEGRATOR Integrator Output — Outside foil of CINT. 33 COMMON Analog Common — System is auto-zeroed to COMMON.

34 INPUT LOW Differential Input Low Side

35 INPUT HIGH Differential Input High Side

36 REF IN + Differential Reference Input Positive

37 REF CAP + Reference Capacitor Positive

38 REF CAP – Reference Capacitor Negative

39 REF IN – Differential Reference Input Negative

40 V + Positive Supply Voltage — Nominally +5V with respect to GND (Pin 1). NOTE: All digital levels are positive true. Figure 1. TC7109A UART Interface (Send Any Word to UART to Transmit Latest Result) should have 100kΩ pull-up resistors to +5V.

3-97TELCOM SEMICONDUCTOR, INC. Figure 2. TC7109A Parallel Interface With 8048/8049 Microcomputer to return to zero, is proportional to the input signal. Deintegrate (DE), and (4) Zero Integrator (ZI). referred to the input is less than 10µV.

3-98 TELCOM SEMICONDUCTOR, INC. TC7109 TC7109A 12-BIT µP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS reference for (+) or (–) input voltages will cause a roll-over error. This error can be held to less than 0.5 count worst case by using a large reference capacitor in comparison to the stray capacitance. To minimize roll-over error from these sources, keep the reference common-mode voltage near or at analog common. Digital Section The digital section is shown in the block diagram (Fig- ure 4) and includes the clock oscillator and scaling circuit, a 12-bit binary counter with output latches and TTL com- patible three-state output drivers, UART handshake logic, polarity, overrange, and control logic. Logic levels are re- ferred to as LOW or HIGH. Inputs driven from TTL gates should have 3 kΩ to 5 kΩ pull-up resistors added for maximum noise immunity. For minimum power consumption, all inputs should swing from GND (LOW) to V + (HIGH). STATUS Output During a conversion cycle, the STATUS output goes HIGH at the beginning of signal integrate and goes LOW one-half clock period after new data from the conversion has been stored in the output latches (see Figure 3). The signal may be used as a "data valid" flag to drive interrupts, or for monitoring the status of the converter. (Data will not change while status is LOW.) MODE Input The output mode of the converter is controlled by the MODE input. The converter is in its "direct" output mode, when the MODE input is LOW or left open. The output data is directly accessible under the control of the chip and byte enable inputs (this input is provided with a pull-down resistor to ensure a LOW Level when the pin is left open). When the MODE input is pulsed high, the converter enters the UART handshake mode and outputs the data in 2 bytes, then returns to "direct" mode. When the MODE input is kept HIGH, the converter will output data in the handshake mode at the end of every conversion cycle. With MODE = 0 (direct bus transfer), the send input should be tied to V +. (See "Handshake Mode.") RUN/HOLD Input With the RUN/HOLD input high, or open, the circuit operates normally as a dual-slope ADC, as shown in Figure 3. Conversion cycles operate continuously with the output latches updated after zero crossing in the deintegrate mode. An internal pull-up resistor is provided to ensure a HIGH level with an open input. Zero-Integrator Phase The ZI phase only occurs when an input overrange condition exists. The function of the ZI phase is to eliminate residual charge on the integrator capacitor after an overrange measurement. Unless removed, the residual charge will be transferred to the auto-zero capacitor and cause an error in the succeeding conversion. The ZI phase virtually eliminates hysteresis or "cross talk" in multiplexed systems. An overrange input on one channel will not cause an error on the next channel mea- sured. This feature is especially useful in thermocouple measurements, where unused (or broken thermocouple) inputs are pulled to the positive supply rail. During ZI, the reference capacitor is charged to the reference voltage. The signal inputs are disconnected from the buffer and integrator. The comparator output is con- nected to the buffer input, causing the integrator output to be driven rapidly to 0V (Figure 3). The ZI phase only occurs following an overrange and lasts for a maximum of 1024 clock periods. Differential Input The TC7109A has been optimized for operation with analog common near digital ground. With +5V and –5V power supplies, a full ±4V full-scale integrator swing maxi- mizes the analog section's performance. A typical CMRR of 86 dB is achieved for input differential voltages anywhere within the typical common-mode range of 1V below the positive supply to 1.5V above the negative supply. However, for optimum performance, the IN HI and IN LO inputs should not come within 2V of either supply rail. Since the integrator also swings with the common-mode voltage, care must be exercised to ensure the integrator output does not saturate. A worst-case condition is near a full-scale negative differential input voltage with a large positive common-mode voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common-mode voltage. In such cases, the integrator swing can be reduced to less than the recommended ±4V full-scale value, with some loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity. Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. Roll-over voltage is the main source of common-mode error, caused by the reference capacitor losing or gaining charge due to stray capacity on its nodes. With a large common-mode voltage, the reference capacitor can gain charge (increase voltage) when called upon to deintegrate a positive signal and lose charge (decrease voltage) when called upon to deintegrate a negative input signal. This difference in

3-99TELCOM SEMICONDUCTOR, INC.

14 THREE-STATE OUTPUTS

Figure 4. Digital Section Figure 3. Conversion Timing (RUN/HOLD Pin High)

3-100 TELCOM SEMICONDUCTOR, INC. Figure 5. TC7109A RUN/HOLD Operation integrate phase of the next conversion. measured determines the conversion time. eliminates the acquisition of erroneous data. Table 1. TC7109A Direct Mode Timing Requirements Figure 6. TC7109A Direct Mode Output Timing

7 COUNTS

3-101TELCOM SEMICONDUCTOR, INC. Handshake Mode An alternative means of interfacing the TC7109A to digital systems is provided when the handshake output mode of the TC7109A becomes active in controlling the flow of data instead of passively responding to chip and byte enable inputs. This mode allows a direct interface between the TC7109A and industry-standard UARTs with no external logic required. The TC7109A provides all the control and flag signals necessary to sequence the two bytes of data into the UART and initiate their transmission in serial form when triggered into the handshake mode. The cost of designing remote data acquisition stations is reduced using serial data transmission to minimize the number of lines to the central controlling processor. The MODE input controls the handshake mode. When the MODE input is held HIGH, the TC7109A enters the handshake mode after new data has been stored in the output latches at the end of every conversion performed (see Figures 7 and 8). Entry into the handshake mode may be triggered on demand by the MODE input. At any time during the conversion cycle, the LOW-to-HIGH transition of a short pulse at the MODE input will cause immediate entry into the handshake mode. If this pulse occurs while new data is being stored, the entry into handshake mode is delayed until the data is stable. The MODE input is ignored in the handshake mode, and until the converter completes the output cycle and clears the handshake mode, data updating will be inhibited (see Figure 9). When the MODE input is HIGH or when the converter enters the handshake mode, the chip and byte enable inputs become TTL-compatible outputs which provide the output cycle control signals (see Figures 7, 8 and 9). The SEND input is used by the converter as an indica- tion of the ability of the receiving device (such as a UART) to accept data in the handshake mode. The sequence of the output cycle with SEND held HIGH is shown in Figure 7. The handshake mode (internal MODE HIGH) is entered after the data latch pulse (the CE/LOAD, LBEN and HBEN terminals are active as outputs since MODE remains HIGH). The HIGH level at the SEND input is sensed on the same HIGH-to-LOW internal clock edge. On the next LOW- to-HIGH internal clock edge, the high-order byte (bits 9 through 12, POL, and OR) outputs are enabled and the CE/ LOAD and the HBEN outputs assume a LOW level. The CE/LOAD output remains LOW for one full internal clock period only; the data outputs remain active for 1-1/2 inter- nal clock periods; and the high-byte enable remains LOW for 2 clock periods. The CE/LOAD output LOW level or LOW-to-HIGH edge may be used as a synchronizing sig- nal to ensure valid data, and the byte enable as an output may be used as a byte identification flag. With SEND remaining HIGH the converter completes the output cycle using CE/LOAD and LBEN while the low-order byte out- puts (bits 1 through 8) are activated. When both bytes are sent, the handshake mode is terminated. The typical UART interfacing timing is shown in Figure 8. The SEND input is used to delay portions of the sequence, or handshake, to ensure correct data transfer. This timing diagram shows an industry-standard HD6403 or CDP1854 CMOS UART to interface to serial data channels. The SEND input to the TC7109A is driven by the TBRE (Transmitter Buffer Regis- ter Empty) output of the UART, and the CE/LOAD input of the TC7109A drives the TBRL (Transmitter Buffer Register Load) input to the UART. The eight transmitter buffer regis- ter inputs accept the parallel data outputs. With the UART transmitter buffer register empty, the SEND input will be HIGH when the handshake mode is entered after new data is stored. The high-order byte outputs become active and the CE/LOAD and HBEN inputs will go LOW after SEND is sensed. When CE/LOAD goes HIGH at the end of one clock period, the high-order byte data is clocked into the UART transmitter buffer register. The UART TBRE output will go LOW, which halts the output cycle with the HBEN output LOW, and the high-order byte outputs active. When the UART has transferred the data to the transmitter regis- ter and cleared the transmitter buffer register, the TBRE returns HIGH. The high-order byte outputs are disabled on the next TC7109A internal clock HIGH-to-LOW edge, and one-half internal clock later, the HBEN output returns HIGH. The CE/LOAD and LBEN outputs go LOW at the same time as the low-order byte outputs become active. When the CE/LOAD returns HIGH at the end of one clock period, the low-order data is clocked into the UART transmitter buffer register, and TBRE again goes LOW. The next TC7109A internal clock HIGH-to-LOW edge will sense when TBRE returns to a HIGH, disabling the data inputs. One-half internal clock later, the handshake mode is cleared, and the CE/LOAD, HBEN and LBEN terminals return HIGH and stay active, if MODE still remains HIGH. Handshake output sequences may be performed on demand by triggering the converter into handshake mode with a LOW-to-HIGH edge on the MODE input. A hand- shake output sequence triggered is shown in Figure 9. The SEND input is LOW when the converter enters handshake mode. The whole output sequence is controlled by the SEND input, and the sequence for the first (high order) byte is similar to the sequence for the second byte. Figure 9 also shows that the output sequence can take longer than a conversion cycle. New data will not be latched when the handshake mode is still in progress and is there- fore lost. TC7109 TC7109A 12-BIT µP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

3-103TELCOM SEMICONDUCTOR, INC. Figure 9. TC7109A Handshake Triggered by MODE Input multiple of the 60 Hz period for optimum 60 Hz line rejection. capacitors and a feedback device are added to the oscillator. 33.33 ms, which will give better than 40 dB, 60 Hz rejection. is at GND, the clock will be 1/58 of the input frequency.

3.58 MHz

3-105TELCOM SEMICONDUCTOR, INC. The inner foil of CAZ should be connected to pin 31 and the outer foil to the RC summing junction. The inner foil of C INT should be connected to the RC summing junction and the outer foil to pin 32 for best rejection of stray pickups. For low leakage at temperatures above +85°C, use Teflon capacitors. Reference Capacitor A 1 µF capacitor is recommended for most circuits. However, where a large common-mode voltage exists, a larger value is required to prevent roll-over error (e.g., the reference low is not analog common), and a 409.6 mV scale is used. The roll-over error will be held to 0.5 count with a 10 µF capacitor. For temperatures above +80°C use Teflon or equivalent capacitors for their low leakage characteristics. Reference Voltage To generate full-scale output of 4096 counts, the analog input required is V IN = 2 VREF . For 409.6 mV full scale, use a reference of 204.8 mV. In many applications, where the ADC is connected to a transducer, a scale factor will exist between the input voltage and the digital reading. For instance, in a measuring system, the designer might like to have a full-scale reading when the voltage for the transducer is 700 mV. Instead of dividing the input down to 409.6 mV, the designer should use the input voltage directly and select V REF = 350 mV. Suitable values for integrating resistor and capacitor would be 34 kΩ and 0.15 µF. This makes the system slightly quieter and also avoids a divider network on the input. Another advantage of this system occurs when temperature and weight measurements with an offset or tare are desired for non-zero input. The offset may be introduced by connecting the voltage output of the transducer between common and analog high, and the offset voltage between common and analog low, observing polarities carefully. In processor-based systems using the TC7109A, it may be more desirable to use software and perform this type of scaling or tare subtraction digitally. Reference Sources A major factor in the absolute accuracy of the ADC is the stability of the reference voltage. The 12-bit resolution of the TC7109A is one part in 4096, or 244 ppm. Thus, for the on- board reference temperature coefficient of 70 ppm/°C, a temperature difference of 3°C will introduce a one-bit abso- lute error. Where the ambient temperature is not controlled, or where high-accuracy absolute measurements are being made, it is recommended that an external high-quality reference be used. A reference output (pin 29) is provided which may be used with a resistive divider to generate a suitable reference voltage (20 mA may be sunk without significant variation in output voltage). A pull-up bias device is provided which sources about 10 µA. The output voltage is nominally 2.8V below V +. When using the on-board reference, REF OUT (pin 29) should be connected to REF– (pin 39), and REF+ should be connected to the wiper of a precision potentiom- eter between REF OUT and V +. The test circuit shows the circuit for a 204.8 mV reference, generated by a 2 kΩ precision potentiometer in series with a 24 kΩ fixed resistor. Interfacing Direct Mode Combinations of chip-enable and byte-enable control signals which may be used when interfacing the TC7109A to parallel data lines are shown in Figure 12. The CE/LOAD input may be tied low, allowing either byte to be controlled by its own enable (Figure 12A). Figure 12B shows the HBEN and LBEN as flag inputs, and CE/LOAD as a master enable, which could be the READ strobe available from most microprocessors. Figure 12C shows a configuration where the two byte enables are connected together. The CE/LOAD is a chip enable, and the HBEN and LBEN may be used as a second chip enable, or connected to ground. The 14 data outputs will be enabled at the same time. In the direct MODE, SEND should be tied to V Figure 13 shows interfacing several TC7109A's to a bus, ganging the HBEN and LBEN signals to several con- verters together, and using the CE/LOAD input to select the desired converter. Figures 14–19 give practical circuits utilizing the paral- lel three-state output capabilities of the TC7109A. Figure 14 shows parallel interface to the Intel MCS-48, -80 and - 85 systems via an 8255 PPI, where the TC7109A data outputs are active at all times. The 8155 I/O ports may be used in an identical manner. This interface can be used in a read-after-update sequence, as shown in Figure 15. The data is accessed by the high-to-low transition of the STA- TUS driving an interrupt to the microprocessor. The RUN/HOLD input is also used to initiate conver- sions under software control. Figure 16 gives an interface to Motorola MC6800 or MOS Technology MCS650X sys- tem. An interrupt is generated through the Control Register B, CB1 line from the high-to-low transition of the STATUS output. The RUN/HOLD pin is controlled by CB2 through Control Register B, allowing software control of conver- sions. TC7109 TC7109A 12-BIT µP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

3-110 TELCOM SEMICONDUCTOR, INC. connected to the control line on the PPI. and the interrupt may be used to reset the MODE bit. converted data with minimum component count. one serial line with additional components. Figure 20. TC7109A Handshake Interface to MCS-6800, MCS650X Microprocessors

3-111TELCOM SEMICONDUCTOR, INC.

6402 CMOS UART

Figure 21. Handshake Interface for Multiplexed Converters or average, of an input voltage over a fixed period of time. held, the integrating converter averages the effects of noise. periods are an integral multiple of the measurement period. frequency noise (Figure 22). Figure 22. Normal Mode Rejection of Dual-Slope Converter as a