TC7107

TC7106 TELCOM | Alldatasheet

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3-183TELCOM SEMICONDUCTOR, INC. TC7106 TC7106A TC7107 TC7107A Figure 1. TC7106/A/7/A Typical Operating Circuit

3 CONVERSIONS/SEC

ORDERING INFORMATION

6 = LCD 7 = LED A or blank* R (reversed pins) or blank (CPL pkg only) * "A" parts have an improved reference TC Package Code (see below): Package Temperature Code Package Pin Layout Range CKW 44-Pin PQFP Formed Leads 0 °C to +70°C CLW 44-Pin PLCC — 0 °C to +70°C CPL 40-Pin PDIP Normal 0 °C to +70°C IPL 40-Pin PDIP Normal – 25 °C to +85°C IJL 40-Pin CerDIP Normal – 25 °C to +85°C GENERAL DESCRIPTION The TC7106A and TC7107A 3-1/2 digit direct-display drive analog-to-digital converters allow existing 7106/7107 based systems to be upgraded. Each device has a preci- sion reference with a 20ppm/°C max temperature coeffi- cient. This represents a 4 to 7 times improvement over similar 3-1/2 digit converters. Existing 7106 and 7107 based systems may be upgraded without changing external pas- sive component values. The TC7107A drives common anode light emitting diode (LED) displays directly with 8mA per segment. A low-cost, high-resolution indicating meter requires only a display, four resistors, and four capacitors. The TC7106A low power drain and 9V battery operation make it suitable for portable applications. The TC7106A/TC7107A reduces linearity error to less than 1 count. Rollover error – the difference in readings for equal magnitude but opposite polarity input signals – is below ±1 count. High impedance differential inputs offer 1pA leakage current and a 10 12Ω input impedance. The differential reference input allows ratiometric measurements for ohms or bridge transducer measurements. The 15µVP–P noise performance guarantees a “rock solid” read- ing. The auto-zero cycle guarantees a zero display read- ing with a zero-volts input.

FEATURES

n Internal Reference with Low Temperature Drift n Drives LCD (TC7106) or LED (TC7107) Display Directly n Guaranteed Zero Reading With Zero Input n Low Noise for Stable Display n Auto-Zero Cycle Eliminates Need for Zero Adjustment n True Polarity Indication for Precision Null

Applications

n Convenient 9 V Battery Operation (TC7106A) n High Impedance CMOS Differential Inputs.... 1012Ω n Differential Reference Inputs Simplify Ratiometric Measurements 3-1/2 DIGIT A/D CONVERTERS TC7106/6A/7/7A-7 11/4/96

3-184 TELCOM SEMICONDUCTOR, INC. ELECTRICAL CHARACTERISTICS (Note 3) TC7106/A & TC7107/A Parameters Test Conditions Min Typ Max Unit Zero Input Reading V IN = 0.0 V – 000.0 ±000.0 +000.0 Digital Full-Scale = 200.0mV Reading Ratiometric Reading V IN = VREF 999 999/1000 1000 Digital VREF = 100 mV Reading Roll-Over Error (Difference in V –IN = +V+ IN ≅ 200mV – 1 ±0.2 +1 Counts Reading for Equal Positive and Negative Reading Near Full-Scale) Linearity (Max. Deviation From Full-Scale = 200mV – 1 ±0.2 +1 Counts Best Straight Line Fit) or Full-Scale = 2.000 V Common-Mode V CM = ±1V, VIN = 0V, — 50 — µV/V Rejection Ratio (Note 4) Full Scale = 200.0 mV Noise (Pk – Pk Value Not V IN = 0 V — 15 — µV Exceeded 95% of Time) Full-Scale = 200.0mV Leakage Current @ Input V IN = 0 V — 1 10 pA Zero Reading Drift V IN = 0 V “C” Device = 0°C to +70°C — 0.2 1 µV/°C VIN = 0 V “I” Device = – 25°C to +85°C — 1.0 2 µV/°C Scale Factor V IN = 199.0mV, Temperature Coefficient “C” Device = 0 °C to +70°C — 1 5 ppm/ °C (Ext. Ref = 0ppm°C) VIN = 199.0mV — — 20 ppm/ °C “I” Device = – 25°C to +85°C Supply Current (Does Not V IN = 0 — 0.8 1.8 mA Include LED Current For TC7107/A) ABSOLUTE MAXIMUM RATINGS* TC7106A Package Power Dissipation (Note 2) (TA ≤ 70°C) Operating Temperature TC7107A Supply Voltage Power Dissipation (Note 2) (TA ≤ 70°C) Operating Temperature *Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to Absolute Maximum Rating Conditions for extended periods may affect device reliability. TC7106 TC7106A TC7107 TC7107A 3-1/2 DIGIT A/D CONVERTERS

3-185TELCOM SEMICONDUCTOR, INC. ELECTRICAL CHARACTERISTICS (Cont.) (Note 3) TC7106/A & TC7107/A Parameters Test Conditions Min Typ Max Unit Analog Common Voltage 25k Ω Between Common 2.7 3.05 3.35 V (With Respect to Pos. Supply) and Pos. Supply Temp. Coeff. of 25k Ω Between Common Analog Common and Pos. Supply (With Respect 0 °C ≤ TA ≤ +70°C 7106A/7A 20 50 ppm/°C to Pos. Supply) ("C", Commercial Temp. Range Devices)7106/7 80 — ppm/ °C Temp. Coeff. of 25k Ω Between Common Analog Common and Pos. Supply (With Respect – 25 °C ≤ T A ≤ 85°C — — 75 ppm/ °C to Pos. Supply) (“I,” Industrial Temp. Range Devices) TC7106A ONLY Pk – Pk V + to V– = 9V 4 5 6 V Segment Drive Voltage (Note 5) TC7106A ONLY Pk – Pk V + to V– = 9V 4 5 6 V Backplane Drive Voltage (Note 5) TC7107A ONLY V Segment Sinking Current (Except Pin 19) Segment Voltage = 3V TC7107A ONLY V + = 5.0V 10 16 — mA Segment Sinking Current (Pin 19) Segment Voltage = 3V NOTES: 1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA. 2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 3. Unless otherwise noted, specifications apply to both the TC7106/A and TC7107/A at T A = 25°C, fCLOCK = 48 kHz. Parts are tested in the circuit of Figure 1. 4. Refer to “Differential Input” discussion. 5. Backplane drive is in phase with segment drive for “OFF” segment, 180° out of phase for “ON” segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV. TC7106 TC7106A TC7107 TC7107A 3-1/2 DIGIT A/D CONVERTERS

3-186 TELCOM SEMICONDUCTOR, INC. TC7106 TC7106A TC7107 TC7107A 3-1/2 DIGIT A/D CONVERTERS PIN CONFIGURATIONS TC7106ACPL TC7107AIPL OSC 1 TEST V ANALOG COMMON C AZ V + D NORMAL PIN CONFIGURATION C 2 B 2 A 2 E 2 D 3 B 3 E 3 AB 4 (MINUS SIGN) 10's 100's 1000's (7106A/7107A) 100's OSC 2 OSC 3 REF V – REF C + REF C – REF V + IN V – IN VBUFF V INT V – G C A G BP/GNDPOL TC7106AIJL TC7107AIJL 100's 1000's 100's REVERSE PIN CONFIGURATION D 1 C 1 B 1 A 1 G 1 E 1 1's V + D 2 C 2 B 2 A 2 E 2 D 3 B 3 E 3 AB 4 (MINUS SIGN) POL D 1 C 1 B 1 A 1 G 1 E 1 1's 10's OSC TEST V ANALOG COMMON CAZ OSC 2 OSC REF V – REF C + REF C – REF V + IN V – IN VBUFF V INT V – G C A G BP/GND (7106A/7107A) NC G 2 NC NC TEST OSC 3 NC OSC 2 OSC 1 D 1 C 1 12 13 14 15 16 17 18 19 20 21 22 38 37 36 35 34 REF HIA1 TC7106ACKW TC7107ACKW (FLAT PACKAGE) 394041424344 REF LO C REF C REF COM IN HI IN LO A/Z BUFF INT G 1 D 2 C 2 D 3 C 3 G 3 BP/GND POL AB 4 REF LO C REF G 1 D 2 C 2 NC D 3 18 19 20 21 22 23 24 25 26 27 28 44 43 42 41 40 A1B3 TC7106ACLW TC7107ACLW (PLCC) 123456 C 1 D 1 NC OSC 1 OSC 2 OSC 3 TEST REF HI AB 4 POL NC BP/GND G 3 C 3 G 2 C REF COMMON IN HI NC IN LO A/Z BUFF INT

3-187TELCOM SEMICONDUCTOR, INC. PIN DESCRIPTION Pin No. Pin No. 40-Pin PDIP 40-Pin PDIP (Normal) (Reverse) Symbol Description 1 (40) V + Positive supply voltage. 2 (39) D 1 Activates the D section of the units display. 3 (38) C 1 Activates the C section of the units display. 4 (37) B 1 Activates the B section of the units display. 5 (36) A 1 Activates the A section of the units display. 6 (35) F 1 Activates the F section of the units display. 7 (34) G 1 Activates the G section of the units display. 8 (33) E 1 Activates the E section of the units display. 9 (32) D 2 Activates the D section of the tens display. 10 (31) C 2 Activates the C section of the tens display. 11 (30) B 2 Activates the B section of the tens display. 12 (29) A 2 Activates the A section of the tens display. 13 (28) F 2 Activates the F section of the tens display. 14 (27) E 2 Activates the E section of the tens display. 15 (26) D 3 Activates the D section of the hundreds display. 16 (25) B 3 Activates the B section of the hundreds display. 17 (24) F 3 Activates the F section of the hundreds display. 18 (23) E 3 Activates the E section of the hundreds display. 19 (22) AB 4 Activates both halves of the 1 in the thousands display. 20 (21) POL Activates the negative polarity display. 21 (20) BP LCD Backplane drive output (TC7106A). Digital ground (TC7107A). 22 (19) G 3 Activates the G section of the hundreds display. 23 (18) A 3 Activates the A section of the hundreds display. 24 (17) C 3 Activates the C section of the hundreds display. 25 (16) G 2 Activates the G section of the tens display. 26 (15) V – Negative power supply voltage. 27 (14) V INT Integrator output. Connection point for integration capacitor. See INTEGRATING CAPACITOR section for more details 28 (13) V BUFF Integration resistor connection. Use a 47kΩ resistor for a 200mV full- scale range and a 470kΩ resistor for 2V full-scale range. 29 (12) C AZ The size of the auto-zero capacitor influences system noise. Use a 0.47µF capacitor for 200mV full scale, and a 0.047µF capacitor for 2V full scale. See Paragraph on AUTO-ZERO CAPACITOR for more details. 30 (11) V –IN The analog LOW input is connected to this pin. 31 (10) V + IN The analog HIGH input signal is connected to this pin. 32 (9) ANALOG This pin is primarily used to set the analog common-mode voltage for battery operation or in systems where the input signal is referenced to the power supply. It also acts as a reference voltage source. See paragraph on ANALOG COMMON for more details. 33 (8) C –REF See pin 34. COMMON GND TC7106 TC7106A TC7107 TC7107A 3-1/2 DIGIT A/D CONVERTERS

3-188 TELCOM SEMICONDUCTOR, INC. TC7106 TC7106A TC7107 TC7107A 3-1/2 DIGIT A/D CONVERTERS GENERAL THEORY OF OPERATION DUAL SLOPE CONVERSION PRINCIPLES (All Pin Designations Refer to the 40-Pin DIP) The TC7106A and TC7107A are dual slope, integrating analog-to-digital converters. An understanding of the dual slope conversion technique will aid in following the detailed operation theory. The conventional dual slope converter measurement cycle has two distinct phases:

• Input Signal Integration
• Reference Voltage Integration (Deintegration) The input signal being converted is integrated for a fixed time period (T SI). Time is measured by counting clock pulses. An opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The reference integration time is directly proportional to the input signal (T RI). (Figure 2A). In a simple dual slope converter a complete conversion requires the integrator output to “ramp-up” and “ramp- down.” A simple mathematical equation relates the input signal, reference voltage and integration time: V IN(t)dt = Figure 2A. Basic Dual Slope Converter RC ∫ TSI VR TRI RC0 where: VR = Reference Voltage TSI = Signal Integration Time (Fixed) TRI = Reference Voltage Integration Time (Variable) For a constant VIN: VIN = VR TRI TSI REF VOLTAGE ANALOG INPUT SIGNAL DISPLAY SWITCH DRIVER CONTROL LOGIC INTEGRATOR OUTPUT CLOCK COUNTER POLARITY CONTROL PHASE CONTROL VIN VIN VFULL SCALE 1/2 VFULL SCALE VARIABLE REFERENCE INTEGRATE TIME FIXED SIGNAL INTEGRATE TIME INTEGRATOR C COMPARATOR +/– PIN DESCRIPTION (Cont.) Pin No. Pin No. 40-Pin PDIP 40-Pin PDIP (Normal) (Reverse) Symbol Description 34 (7) C + REF A 0.1µF capacitor is used in most applications. If a large common- mode voltage exists (for example, the V–IN pin is not at analog common), and a 200mV scale is used, a 1µF capacitor is recom- mended and will hold the roll-over error to 0.5 count. 35 (6) V –REF See pin 36. 36 (5) V + REF The analog input required to generate a full-scale output (1999 counts). Place 100mV between pins 35 and 36 for 199.9mV full-scale. Place 1V between pins 35 and 36 for 2V full scale. See paragraph on REFERENCE VOLTAGE. 37 (4) Test Lamp test. When pulled HIGH (to V +) all segments will be turned on and the display should read –1888. It may also be used as a negative supply for externally-generated decimal points. See paragraph under TEST for additional information. 38 (3) OSC 3 See pin 40. 39 (2) OSC 2 See pin 40. 40 (1) OSC 1 Pins 40, 39, 38 make up the oscillator section. For a 48kHz clock (3 readings per section), connect pin 40 to the junction of a 100kΩ resistor and a 100pF capacitor. The 100kΩ resistor is tied to pin 39 and the 100pF capacitor is tied to pin 38.

3-189TELCOM SEMICONDUCTOR, INC. The dual slope converter accuracy is unrelated to the integrating resistor and capacitor values as long as they are stable during a measurement cycle. An inherent benefit is noise immunity. Noise spikes are integrated or averaged to zero during the integration periods. Integrating ADCs are immune to the large conversion errors that plague succes- sive approximation converters in high-noise environments. Interfering signals with frequency components at multiples of the averaging period will be attenuated. Integrating ADCs commonly operate with the signal integration period set to a multiple of the 50/60 Hz power line period. (Figure 2B) Figure 2B. Normal-Mode Rejection of Dual Slope Converter ANALOG SECTION In addition to the basic signal integrate and deintegrate cycles discussed, the circuit incorporates an auto-zero cycle. This cycle removes buffer amplifier, integrator, and comparator offset voltage error terms from the conversion. A true digital zero reading results without adjusting external potentiometers. A complete conversion consists of three cycles: an auto-zero, signal-integrate and reference-inte- grate cycle. Auto-Zero Cycle During the auto-zero cycle the differential input signal is disconnected from the circuit by opening internal analog gates. The internal nodes are shorted to analog common (ground) to establish a zero-input condition. Additional ana- log gates close a feedback loop around the integrator and comparator. This loop permits comparator offset voltage error compensation. The voltage level established on C AZ compensates for device offset voltages. The offset error referred to the input is less than 10µV. The auto-zero cycle length is 1000 to 3000 counts. NORMAL MODE REJECTION (dB) 0.1/T 1/T 10/T INPUT FREQUENCY T = MEASUREMENT PERIOD Signal Integrate Cycle When the auto-zero loop is opened, the internal differ- ential inputs connect to V+IN and V–IN. The differential input signal is integrated for a fixed time period. The signal integration period is 1000 counts. The externally set clock frequency is divided by four before clocking the internal counters. The integration time period is: T SI = x 1000 where: fOSC = External Clock Frequency The differential input voltage must be within the device common-mode range (1V of either supply) when the con- verter and measured system share the same power supply common (ground). If the converter and measured system do not share the same power supply common, V –IN should be tied to analog common. Polarity is determined at the end of the signal integrate phase. The sign bit is a true polarity indication in that signals less than 1 LSB are correctly determined. This allows precision null detection, limited only by device noise and auto-zero residual offsets. Reference Integrate Cycle The final phase is reference integrate or de-integrate. V –IN is internally connected to analog common and V+IN is connected across the previously charged reference capaci- tor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal and is between 0 and 2000 counts. The digital reading displayed is: DIGITAL SECTION (TC7106A) The TC7106A (Figure 3) contains all the segment driv- ers necessary to directly drive a 3 -1/2 digit liquid crystal display (LCD). An LCD backplane driver is included. The backplane frequency is the external clock frequency divided by 800. For three conversions/second the backplane fre- quency is 60Hz with a 5V nominal amplitude. When a segment driver is in phase with the backplane signal the segment is “OFF.” An out of phase segment drive signal causes the segment to be “ON” or visible. This AC drive configuration results in negligible DC voltage across each LCD segment. This insures long LCD display life. The polarity segment driver is “ON” for negative analog inputs. If V +IN and V–IN are reversed, this indicator will reverse. fOSC 1000 x VIN VREF TC7106 TC7106A TC7107 TC7107A 3-1/2 DIGIT A/D CONVERTERS

3-190 TELCOM SEMICONDUCTOR, INC. Figure 3. TC7106A Block Diagram

7 SEGMENT

2 OSC 3OSC 1

3-192 TELCOM SEMICONDUCTOR, INC. Figure 5. TC7107A Block Diagram

3-193TELCOM SEMICONDUCTOR, INC. Oscillator Components R OSC (Pin 40 to Pin 39) should be 100kΩ . COSC is selected using the equation: For fOSC of 48kHz, COSC is 100pF nominally. Note that fOSC is divided by four to generate the TC7106A internal control clock. The backplane drive signal is derived by dividing f OSC by 800. To achieve maximum rejection of 60Hz noise pickup, the signal-integrate period should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz, etc. should be selected. For 50 Hz rejection, oscillator frequencies of 200kHz, 100kHz, 66 2/3kHz, 50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5 read- ings/second) will reject both 50Hz and 60Hz. Reference Voltage Selection A full-scale reading (2000 counts) requires the input signal be twice the reference voltage. Required Full-Scale Voltage* V REF 200.0mV 100.0mV 2.000V 1.000V * VFS = 2 VREF In some applications a scale factor other than unity may exist between a transducer output voltage and the required digital reading. Assume, for example, a pressure transducer output is 400mV for 2000 lb/in 2. Rather than dividing the input voltage by two the reference voltage should be set to 200mV. This permits the transducer input to be used directly. The differential reference can also be used when a digital zero reading is required when V IN is not equal to zero. This is common in temperature measuring instrumentation. A compensating offset voltage can be applied between analog common and V –IN. The transducer output is con- nected between V+IN and analog common. The internal voltage reference potential available at analog common will normally be used to supply the convert- er's reference. This potential is stable whenever the supply potential is greater than approximately 7V. In applications where an externally-generated reference voltage is desired, refer to Figure 7. f OSC = 0.45 RC Integrating Capacitor – C INT C INT should be selected to maximize the integrator output voltage swing without causing output saturation. Due to the TC7106A/7107A superior temperature coefficient specification, analog common will normally supply the differ- ential voltage reference. For this case a ±2V full-scale integrator output swing is satisfactory. For 3 readings/ second (f OSC = 48kHz) a 0.22µF value is suggested. If a different oscillator frequency is used, CINT must be changed in inverse proportion to maintain the nominal ±2 V integrator swing. An exact expression for CINT is: C INT = VINT Where: fOSC = Clock frequency at Pin 38 VFS = Full-scale input voltage R INT = Integrating resistor VINT = Desired full-scale integrator output swing C INT must have low dielectric absorption to minimize rollover error. A polypropylene capacitor is recommended. Integrating Resistor – R INT The input buffer amplifier and integrator are designed with class A output stages. The output stage idling current is 100µA. The integrator and buffer can supply 20µA drive currents with negligible linearity errors. R INT is chosen to remain in the output stage linear drive region but not so large that printed circuit board leakage currents induce errors. For a 200mV full-scale, R INT is 47kΩ . 2.0V full-scale requires 470kΩ . Component Nominal Full-Scale Voltage Value 200.0mV 2.000V C AZ 0.47µF 0.047 µF R INT 47kΩ 470kΩ C INT 0.22µF 0.22 µF Note:1. fOSC = 48kHz (3 readings/sec) VFS R INT fOSC (4000) ( ) ( ) TC7106 TC7106A TC7107 TC7107A 3-1/2 DIGIT A/D CONVERTERS

3-197TELCOM SEMICONDUCTOR, INC. signer, a diode may be used instead of the resistor. Figure 15. Diode or Resistor Limits Package Power Dissipation Note: 1. Contact LCD manufacturer for full product listing/specifications.