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2019-10-01C 1 © 2012-2019 KIOXIA Corporation MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1G BIT (128M 8 BIT) CMOS NAND E2PROM
DESCRIPTION
The TC58NVG0S3HTA00 is a single 3.3V 1Gbit (1,140,850,688bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 128) bytes 64 pages 1024 blocks. The device has a 2176-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2176-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes 8 Kbytes: 2176 bytes 64 pages). The TC58NVG0S3HTA00 is a seria l-type memory device which utiliz es the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed, making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
Organization x 8 Memory cell array 2176 64K 8 Register 2176 8 Page size 2176 bytes Block size (128K 8K) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy Mode control Serial input/output Command control Number of valid blocks Min 1004 blocks Max 1024 blocks Power supply V CC 2.7V to 3.6V Access time Cell array to register 25 s max Read Cycle Time 25 ns min (C L=50pF) Program/Erase time Auto Page Program 300 s/page typ. Auto Block Erase 2.5 ms/block typ. Operating current Read (25 ns cycle) 30 mA max. Program (avg.) 30 mA max Erase (avg.) 30 mA max Standby 50 A max Package TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.) 8 bit ECC for each 512Byte is required.
2019-10-01C 2 © 2012-2019 KIOXIA Corporation PIN ASSIGNMENT (TOP VIEW) PIN NAMES I/O1 to I/O8 I/O port CE Chip enable WE Write enable RE Read enable CLE Command latch enable ALE Address latch enable WP Write protect RY / BY Ready/Busy VCC Power supply VSS Ground NC No Connection NC NC NC NC I/O8 I/O7 I/O6 I/O5 NC NC NC V CC VSS NC NC NC I/O4 I/O3 I/O2 I/O1 NC NC NC NC 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 NC NC NC NC NC NC RY/BY RE CE NC NC VCC VSS NC NC CLE ALE WE WP NC NC NC NC NC 8 8 TC58NVG0S3HTA00
2019-10-01C 3 © 2012-2019 KIOXIA Corporation BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS SYMBOL RATING VALUE UNIT VCC Power Supply Voltage 0.6 to 4.6 V VIN Input Voltage 0.6 to 4.6 V VI/O Input / Output Voltage 0.6 to VCC 0.3 ( 4.6 V) V PD Power Dissipation 0.3 W TSTG Storage Temperature 55 to 150 °C TOPR Operating Temperature 0 to 70 °C Note: Avoid locations where the device may be exposed to water (wet, rain, dew condensation, etc.) CAPACITANCE *(Ta 25°C, f 1 MHz) SYMBOL PARAMETER CONDITION MIN MAX UNIT CIN Input V IN 0 V 10 pF COUT Output V OUT 0 V 10 pF * This parameter is periodically sampled and is not tested for e very device. I/O Control circuit Status register Command register Column buffer Column decoder Data register Sense amp Memory cell array Control circuit HV generator Row address decoder Logic control RY / BY VCC I/O1 VSS I/O8 CE CLE ALE WE RE RY / BY Row address buffer decoder to WP Address register
2019-10-01C 4 © 2012-2019 KIOXIA Corporation VALID BLOCKS SYMBOL PARAMETER MIN TYP. MAX UNIT NVB Number of Valid Blocks 1004 1024 Blocks NOTE: The device occasionally c ontains unusable blocks. Refer to Application Note (13) toward the end of this document. The first block (Block 0) is guaranteed to be a valid block at the time of shipment. The specification for the minimum number of valid blocks is applicable over lifetime. DC OPERATING CONDITIONS SYMBOL PARAMETER MIN TYP. MAX UNIT VCC Power Supply Voltage 2.7 3 . 6 V VIH High Level Input Voltage V CC x 0.8 V CC 0.3 V VIL Low Level Input Voltage 0.3* V CC x 0.2 V * 2 V (pulse width lower than 20 ns) DC CHARACTERISTICS (Ta 0 to 70°C, VCC 2.7 to 3.6V) SYMBOL PARAMETER CONDITION MIN TYP. MAX UNIT IIL Input Leakage Current V IN 0 V to VCC 10 A ILO Output Leakage Current V OUT 0 V to VCC 10 A ICCO1 Serial Read Current CE VIL, IOUT 0 mA, tRC 25 ns 30 mA ICCO2 Programming Current 30 mA ICCO3 Erasing Current 30 mA ICCS Standby Current CE VCC 0.2 V, WP 0 V/VCC 50 A VOH High Level Output Voltage I OH 0.1 mA V CC – 0.2 V VOL Low Level Output Voltage I OL 0.1 mA 0 . 2 V IOL (RY / BY ) Output Current of RY / BY p i n VOL 0.2 V 4 m A
2019-10-01C 5 © 2012-2019 KIOXIA Corporation AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta 0 to 70°C, VCC 2.7 to 3.6V) SYMBOL PARAMETER MIN MAX UNIT tCLS CLE Setup Time 12 n s tCLH CLE Hold Time 5 n s tCS C E Setup Time 20 n s tCH C E Hold Time 5 n s tWP Write Pulse Width 12 n s tALS ALE Setup Time 12 n s tALH ALE Hold Time 5 n s tDS Data Setup Time 12 n s tDH Data Hold Time 5 n s tWC Write Cycle Time 25 n s tWH W E High Hold Time 10 n s tWW W P H i g h t o W E Low 100 n s tRR Ready to RE Falling Edge 20 n s tRW Ready to WE Falling Edge 20 ns tRP Read Pulse Width 12 ns tRC Read Cycle Time 25 n s tREA R E Access Time 20 ns tCEA C E Access Time 25 ns tCLR CLE Low to RE Low 10 n s tAR ALE Low to RE Low 10 n s tRHOH R E High to Output Hold Time 25 n s tRLOH R E Low to Output Hold Time 5 n s tRHZ R E High to Output High Impedance 60 ns tCHZ C E High to Output High Impedance 20 ns tCSD C E High to ALE or CLE Don’t Care 0 n s tREH R E High Hold Time 10 n s tIR Output-High-Impedance-to-RE Falling Edge 0 n s tRHW R E H i g h t o W E Low 30 n s tWHC W E H i g h t o C E Low 30 n s tWHR W E H i g h t o R E Low 60 n s tWB W E High to Busy 100 ns tRST Device Reset Time (Ready/Read/Program/Erase) 5/5/10/500 s *1: tCLS and tALS cannot be shorter than tWP *2: tCS should be longer than tWP + 8ns.
2019-10-01C 6 © 2012-2019 KIOXIA Corporation AC TEST CONDITIONS PARAMETER CONDITION VCC: 2.7 to 3.6V Input level V CC 0.2 V, 0.2 V Input pulse rise and fall time 3 ns Input comparison level V CC / 2 Output data comparison level V CC / 2 Output load C L (50 pF) 1 TTL Note: Busy to ready time depends on the pull-up resistor tied t o the RY / BY p i n . (Refer to Application Note (9) toward the end of this document) PROGRAMMING / ERASING / READING CHARACTERISTICS (Ta 0 to 70°C, VCC 2.7 to 3.6V) SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES tPROG Programming Time 300 700 s tDCBSYW2 Data Cache Busy Time in Write Cache (following 15h) 700 s (2) N Number of Partial Program Cycles in the Same Page 4 ( 1 ) tBERASE Block Erasing Time 2 . 5 5 m s tR Memory Cell Array to Starting Address 25 s tDCBSYR1 Data Cache Busy in Read Cache (following 31h and 3Fh) 25 s tDCBSYR2 Data Cache Busy in Page Copy (following 3Ah) 30 s (1) Refer to Application Note (12) toward the end of this docum ent. (2) t DCBSYW2 depends on the timing between internal programming time and data in time. Data Output When tREH is long, output buffers are disabled by /RE=High, and the hold time of data output depends on tRHOH (25ns MIN). Under this condition, the waveforms look like Normal Serial Read Mode. When tREH is short, output buffers are not disabled by /RE=High , and the hold time of data output depends on tRLOH (5ns MIN). Under this condition, output buffers are disabled by the rising edge of CLE, ALE, /CE or the falling edge of /WE, and waveforms look like Extended Data Output Mode.
2019-10-01C 7 © 2012-2019 KIOXIA Corporation TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data Command Input Cycle Timing Diagram CLE ALE CE W E Hold Time tDH Setup Time tDS I/O : VIH or VIL tCS tDH tDS tALS tALH tWP tCLS tCH tCLH : VIH or VIL C E CLE W E ALE I/O
2019-10-01C 8 © 2012-2019 KIOXIA Corporation Address Input Cycle Timing Diagram Data Input Cycle Timing Diagram DIN2175 WE tWP tWP tWH tWP tALS tWC DIN1 DIN0 tDH tDS tCLH tCH ALE CLE CE I/O tDH tDS tDH tDS tCS tCLS tCH tCS tALH PA8 to 15 CA8 to 11 : VIH or VIL tDH tDS tCLS CLE tALS tALH tWP tWH tWP CA0 to 7 tDH tDS tCS tCS CE WE ALE I/O tDH tDS tWP tWH tDH tDS tWP tWH tWC PA0 to 7 tCLH tCH tCH
2019-10-01C 9 © 2012-2019 KIOXIA Corporation Serial Read Cycle Timing Diagram Status Read Cycle Timing Diagram tREH tCHZ C E tRHZ tREA tRC tRR tRHZ tREA tRHZ tREA R E RY / B Y I/O tRHOH tRHOH tRHOH tRP tRP tRP : VIH or VIL tCEA tCEA : VIH or VIL *: 70h represents the hexadecimal number tWHR W E tDH tDS tCLS tCLR tCS tCLH tCH tWP Status output 70h* tWHC tIR tREA tRHZ tCHZ C E CLE R E RY / B Y I/O tRHOH tCEA
2019-10-01C 10 © 2012-2019 KIOXIA Corporation Read Cycle Timing Diagram Read Cycle Timing Diagram: When Interrupted by CE tCLR 30h PA8 to 15 PA0 to 7 CA8 to 11 CA0 to 7 I/O tCS tCLS tCLH tCH tDH tDS tWC tALS tALH W E CLE C E ALE R E tDH tDS tDH tDS tDH tDS tDH tDS tALH tR tDH tDS tWB tCS tCLS tCLH tCH tALS tRC tRR tREA Col. Add. N Data out from Col. Add. N 00h DOUT N DOUT N 1 RY / B Y tCEA 30h PA8 to 15 PA0 to 7 CA8 to 11 CA0 to 7 I/O tCS tCLS tCLH tCH tDH tDS tWC tALS tALH W E CLE C E ALE R E tDH tDS tDH tDS tDH tDS tDH tDS tALH tCLR tR tDH tDS tWB tCS tCLS tCLH tCH tALS tRC tRR tREA Col. Add. N 00h DOUT N DOUT N 1 RY / BY tCHZ tRHZ tRHOH Data out from Col. Add. N tCSD tCEA
2019-10-01C 11 © 2012-2019 KIOXIA Corporation Read Cycle with Data Cache Timing Diagram (1/2) 30h PA8 to 15 PA0 to 7 CA8 to 11 CA0 to 7 I/O tDH tDS tWC tALS tALH W E CLE C E ALE R E tDH tDS tDH tDS tDH tDS tDH tDS tALH tR tDH tDS tWB tALS tRC tRR tREA Column address N * 00h DOUT DOUT RY / B Y tCEA Page address M DOUT 31h tDH tDS tWB tDCBSYR1 31h tDH tDS tWB DOUT tRR tREA tDCBSYR1 tCLR tCLR tCEA Page address M Data out from Col. Add. 0 Data out from Col. Add. 0 Page address M 1 tRW tCS tCLS tCLH tCH Continues to o f n e x t p a g e 1 * The column address will be reset to 0 by the 31h command input . tCS tCLS tCLH tCH tCS tCLS tCLH tCH tCS tCLS tCLH tCH
2019-10-01C 12 © 2012-2019 KIOXIA Corporation Read Cycle with Data Cache Timing Diagram (2/2) Continues from o f p r e v i o u s p a g e 1 I/O W E CLE C E ALE R E RY / B Y DOUT tCLR tWB 31h tDH tDS tWB 31h tDH tDS tRC tRR tREA Page address M 1 Page address M x tCLR tWB tRC tRR tREA tCEA 3Fh tDH tDS DOUT DOUT
1 DOUT
M 2 tDCBSYR1 tDCBSYR1 tDCBSYR1 tCLR Data out from Col. Add. 0 Data out from Col. Add. 0 Data out from Col. Add. 0 tCEA DOUT DOUT
1 DOUT DOUT
Make sure to terminate the operation with 3Fh command.
2019-10-01C 13 © 2012-2019 KIOXIA Corporation Column Address Change in Read Cycle Timing Diagram (1/2) tCLR I/O tCS tCLS tCLH tCH tWC tALS tALH tR CLE C E ALE R E tDH tDS tDH tDS tALH tWB tCS tCLS tCLH tCH tALS tRC tREA tCEA tRR Page address P Page address P Data out from Column address A 00h CA0 to 7 tDH tDS CA8 to 11 tDH tDS PA0 to 7 tDH tDS PA8 to 15 tDH tDS 30h DOUT A DOUT A 1 DOUT A N W E Continues from o f n e x t p a g e 1 R Y / BY Column address A
2019-10-01C 14 © 2012-2019 KIOXIA Corporation Column Address Change in Read Cycle Timing Diagram (2/2) I/O tCS tCLS tCLH tCH 05h CA0 to 7 CA8 to 11 tWC tALS tALH CLE C E ALE R E tDH tDS tDH tDS tDH tDS Column address B E0h tDH tDS tALH tCS tCLS tCLH tCH tALS tREA DOUT A N tRHW Page address P Data out from Column address B tRC tCLR tCEA tIR DOUT B N’ DOUT B 1 DOUT B Continues from o f p r e v i o u s p a g e 1 W E R Y / BY tWHR
2019-10-01C 15 © 2012-2019 KIOXIA Corporation Data Output Timing Diagram Command Dout Dout I/O tRC tDH tRP tRP W E CLE C E ALE R E tRLOH tREH tREA tRHZ tREA tCS tCLS tCLH tCH tRP tRR tREA tRLOH tDS RY / B Y tCHZ tRHOH tRHOH tCEA Dout tALH
2019-10-01C 16 © 2012-2019 KIOXIA Corporation Auto-Program Operation Timing Diagram 80h CA0 to 7 CA8 to 11 tCLS tCLS tALS tDS tDH W E CLE CE ALE R E RY / B Y : VIH or VIL tCLH tCH tCS tDS tDH tALH I/O : Do not input data while data is being output. tCS tDH tDS tDH tPROG tWB tDS tALH tALS * M: up to 2175 Column address N DINN DIN N+1 DINM* 10h 70h Status output PA8 to 15 PA0 to 7
2019-10-01C 17 © 2012-2019 KIOXIA Corporation Auto-Program Operation with Data Cache Timing Diagram (1/3) PA8 to 15 tCLS CA0 to 7 tALS tDS tDH PA0 to 7 80h W E CLE CE ALE R E RY / B Y : VIH or VIL tCLH tCH tCS tCLS tDS tDH tALH I/O CA8 to 11 : Do not input data while data is being output. tCS tDH 15h 80h tDS tDH tDCBSYW2 DINN DIN N+1 tWB tDS tALH tALS DINM* Continues to 1 of next page CA0 to 7 * M: up to 2175 Column address N
2019-10-01C 18 © 2012-2019 KIOXIA Corporation Auto-Program Operation with Data Cache Timing Diagram (2/3) : VIH or VIL : Do not input data while data is being output. PA8 to 15 tCLS CA0 to 7 tALS tDS tDH PA0 to 7 80h W E CLE CE ALE R E RY / B Y tCLH tCH tCS tCLS tDS tDH tALH I/O CA8 to 11 tCS Continued from 1 of previous page tDH 15h 80h tDS tDH tDCBSYW2 DINN DIN N+1 tWB tDS tALH tALS DINM* CA0 to 7 Repeat a max of 62 times (in order to program pages 1 to 62 of a block). * M: up to 2175 Column address N
2019-10-01C 19 © 2012-2019 KIOXIA Corporation Auto-Program Operation with Data Cache Timing Diagram (3/3) (*1) tPROG: Since the last page’s programming by 10h command is initiated after the previous cache program, the tPROG during cache programming is given by the following equation. tPROG tPROG of the last page tPROG of the previous page A A (command input cycle address input cycle data input cycle time of the last page) If “A” exceeds the tPROG of previous page, tPROG of the last page is tPROG max. (Note) Make sure to terminate the operation with 80h-10h comma nd sequence. If the operation is terminated by 80h-15h command sequence, mon itor I/O 6 (Ready / Busy) by issuing the Status Read command (7 0h) and make sure the previous page program operation is completed. If the page program operation is completed, issue FFh reset be fore the next operation. 70h tCLS tALS tDS tDH W E CLE CE ALE R E RY / BY : VIH or VIL tCLH tCH tCS tCLS tDS tDH tALH I/O : Do not input data while data is being output. tCS tDH tDS tDH tPROG (*1) tWB tDS tALH tALS DINM* Continued from 2 of previous page 80h CA0 to 7 CA8 to 11 PA0 to 7 PA8 to 15 DINN DIN N+1 10h Status output * M: up to 2175 Column address N
2019-10-01C 20 © 2012-2019 KIOXIA Corporation Auto Block Erase Timing Diagram tCS 60h PA8 to 15 W E CLE C E ALE R E RY / B Y : VIH or VIL tCLS tCLH tCLS PA0 to 7 tDS tDH tALS : Do not input data while data is being output. Auto Block Erase Setup command I/O D0h 70h Status output tWB tBERASE Busy Status Read command Erase Start command tALH
2019-10-01C 21 © 2012-2019 KIOXIA Corporation ID Read Operation Timing Diagram : VIH or VIL WE CLE RE tCEA CE ALE I/O tAR ID Read command Address Maker code Device code tREA tCLS tCS tDS tCH tALH tALS tCLS tCS tCH tALH 98h 90h 00h tDH tREA F1h tREA See Table 5 tREA See Table 5 tREA See Table 5 3rd Data 4th Data 5th Data
2019-10-01C 22 © 2012-2019 KIOXIA Corporation PIN FUNCTIONS The device is a serial access memory which utilizes time-sharing input of address information. Command Latch Enable: CLE The CLE input signal is used to control loading of the operation mode command into the internal command register. The command is latched into the command register from the I/O port on the rising edge of the WE signal while CLE is High. Address Latch Enable: ALE The ALE signal is used to control loading address information i nto the internal address register. Address information is latched into the address register from the I/O p ort on the rising edge of WE while ALE is High. Chip Enable: CE The device goes into a low-power Standby mode when CE goes High while the device is in Ready state. The CE signal is ignored when the device is in Busy state (RY / BY L), such as during a Program, Erase or Read operation, and will not enter Standby mode even if the CE input goes High. Write Enable: WE The WE signal is used to control the ac quisition of data from the I/O port. Read Enable: RE The RE signal controls serial data output. Data is available tREA after the falling edge of RE The internal column address counter is also incremented (Address = Address + 1) on this falling edge. I/O Port: I/O1 to 8 The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from the device. Write Protect: WP The WP signal is used to protect the device from accidental programmi ng or erasing. The internal voltage regulator is reset when WP is Low. This signal is usually used to protect the data during the power-on/off sequence when input signals are invalid. Ready/Busy: RY / BY The RY / BY output signal is used to indicate the operating condition of the device. The RY / BY signal is in Busy state (RY / BY = L) during the Program, Erase and Read operations and will return to Ready state (RY / BY = H) after completion of the oper ation. The output buffer for this signal is an open drain and has to be pulled up to VCC with an appropriate resistor. If RY / BY signal is not pulled up to VCC (“Open” state), device operation cannot be guaranteed.
The Program operation works on page units while the Erase operation works on block units. clock cycles, as shown in Table 1. Table 1. Addressing
128 Page Buffer
64 Pages1 block
signals, as shown in Table 2. Table 2. Logic Table signal goes Low, Program or Erase is inhibited (Refer to Application Note (10) toward end of this document). the device. Reset or Status Read command can be input during Read Busy.
Table 3. Command table (HEX) Table 4. Read mode operation states
2019-10-01C 26 © 2012-2019 KIOXIA Corporation DEVICE OPERATION Read Mode Read mode is set when the "00h" and “30h” commands are issued to the Command register. Between the two commands, a start address for the Read mode needs to be issued. After the initial power on sequence, “00h” command is latched into the internal command register. Th en the Read operation after the power on sequence is executed by the setti ng of only four address cycles and “30h” command. The sequence and the block diagram are shown below (Refer to the timing chart for detail). Random Column Address Change in Read Cycle RY / B Y WE CLE RE 00h CE ALE I/O M+2 Busy M M+1 30h Page Address N Column Address M Page Address N tR Start-address input A data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising edge of WE in the 30h command input cycle (after the address information has been latched). The device will be in the Busy state during this tran sfe r period. After the transfer period, the device returns to Ready state. Serial data can be output synchronously with the RE clock from the start address designated in the address input cycle. Cell array Select page N M m Data Cache Page Buffer I/O1 to 8: m 2175 Start-address input RY / B Y WE CLE 00h CE ALE I/O Col. M Page N Busy M Page N 30h M1 M2 M3 05h E0h M’ M’1 M’2 M’3 M’4 Col. M’ Page N Col. M Start from Col. M Start from Col. M’ tR RE Select page N M M’ During the serial data output from the Data Cache, the column address can be changed by inputting a new column address using the 05h and E0h commands. The data is read out in serially starting at the new column address. Random Column Address Change operation can be done multiple times within the same page.
2019-10-01C 27 © 2012-2019 KIOXIA Corporation Read with Data Cache The device has a Read with Data Cache that enables the high speed read operation shown below. When the block address changes, this sequence has to be started from the beginning. If the 31h command is issued to the device, the data content of the next page is transferred to the Page Buffer during serial data out from the Data Cache, reducing the t R (Data transfer from memory cell to data register). 1. Normal read. Data is transferred from Page N to Data Cache t hrough Page Buffer. During this time period, the device outputs Busy state for tR max. 2. After the Ready/Busy signal returns to Ready, 31h command is issued and data is transferred to Data Cache from Page Buffer again. This data transfer takes tDCBSYR1 max and the completion of this time period can be detected by Ready/Busy signal. 3. Data of Page N 1 is transferred to Page Buffer from cell while the data of Page N in Data Cache can be read out by /RE clock simultaneously. 4. The 31h command makes data of Page N 1 transfer to Data Cache from Page Buffer after the completion of the transfer from cell to Page Buffer. The device outputs Busy state for tDCBSYR1 max. This Busy period depends on the combination of the internal data transfer time from cell to Page Buffer and the serial data out time. 5. Data of Page N 2 is transferred to Page Buffer from cell while the data of Page N + 1 in Data Cache can be read out by /RE clock simultaneously. 6. The 3Fh command makes the data of Page N 2 transfer to the Data Cache from the Page Buffer after the completion of the transfer from cell to Page Buffer. The device outputs Busy state for tDCBSYR1 max. This Busy period depends on the combination of the internal data transfer time from cell to Page Buffer and the serial data out time. 7. Data of Page N 2 in Data Cache can be read out, but since the 3Fh command does not transfer the data from the memory cell to Page Buffer, the device can accept new command input immediately after the completion of serial data out. Page N 2Data Cache Page Buffer Cell Array Page N Page N 1 Page N 30h 31h & RE c l o c k Page N 2 Page N 1 31h & RE c l o c k 3Fh & RE c l o c k Page N Page N 1 Page N 2 RY / B Y WE CLE 00h CE ALE I/O tR 30h Col. M Page N 0 1 2 3 31h 0 1 2 3 Page Address N Column 0 2175 Page Address N 1 2175 3Fh 0 1 2 3 Page Address N 2 2175 1 2 4 3 5 tDCBSYR1 t DCBSYR1 tDCBSYR1 RE
2019-10-01C 28 © 2012-2019 KIOXIA Corporation Auto Page Program Operation The device carries out an Auto Page Program operation when it receives a "10h" Program command after the address and data have been input. The sequence of command, address and data input is shown below (Refer to the detailed timing chart). Random Column Address Change in Auto Page Program Operation The column address can be changed by the 85h command during the data input sequence of the Auto Page Program operation. Two address input cycles after the 85h command are recognized as a new column address for the data input. After the new data is input to the new column address, the 10h command initiates the actual data program into the selected page automatically. The Random Column Address Change operation can be repeated multiple times within the same page. The data is transferred (programmed) from the Data Cache via the Page Buffer to the selected page on the rising edge of WE following input of the “10h” command. After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until succes s is achieved or until the maximum loop number set in the device is reached. 80h Page N Col. M 85h Din Din 10h Status Din Din Din Din Col. M’ Din Din 70h 90hBUSY RY / B Y CLE 80h ALE I/O Page P CE WE Col. M Din Din Din Din 10h 10h Status output Data RE Selected page Program Data input Read & verification Data input Col. M Col. M’ Selected page Read & verification Program
2019-10-01C 29 © 2012-2019 KIOXIA Corporation Auto Page Program Operation with Data Cache The device has an Auto Page Program with Data Cache operation enabling the high speed program operation shown below. When the block address changes, this sequence has to be started from the beginning. Issuing the 15h command to the device after serial data input initiates the program operation with Data Cache. 1. Data for Page N is input to Data Cache. 2. Data is transferred to the Page Buffer by the 15h command. D uring the transfer the Ready/Busy signal outputs Busy state (tDCBSYW2). 3. Data is programmed to the selected page while the data for P age N 1 is input to the Data Cache. 4. By the 15h command, the data in the Data Cache is transferre d to the Page Buffer after the programming of Page N is completed. The device outputs Busy state from the 15h command until the Data Cache becomes empty. The duration of this period depends on timing between the internal programming of Page N and serial data input for Page N 1 (tDCBSYW2). 5. Data for Page N P is input to the Data Cache while the data of the Page N P 1 is being programmed. 6. The programming with Data Cache is terminated by the 10h com mand. When the device becomes Ready state, it shows that the internal programming of the Page N P is completed. NOTE: Since the last page’s programming by the 10h command is initiated after the previous cache program, the tPROG during cache programming is given by the following: tPROG tPROG for the last page tPROG of the previous page ( command input cycle address input cycle data input cycle time of the previous page) RY / BY CLE ALE I/O CE WE Page N 80h Add Add Status Output Din Din Din 15h 70h Page N 1 80h Add Add Add
1 Status Output
Page N P 80h Add Add Add 3 4 Status Output Din Din Din 10h 70h 5 6 Add Add Add tDCBSYW2 t DCBSYW2 tPROG (NOTE) RE Data Cache Page Buffer Cell Array Page N P 2 3
6 Page N
Data for Page N 1 Data for Page N Data for Page N Data for Page N 1 Page N 1 Data for Page N P Page N P 1
2019-10-01C 30 © 2012-2019 KIOXIA Corporation Pass/Fail status for each page programmed by the Auto Page Program with Data Cache operation can be detected by the Status Read operation. I/O1: Pass/Fail of the current page program operation. I/O2: Pass/Fail of the prev ious page program operation. The Pass/Fail status on I/O1 and I/O2 are valid under the following conditions. Status on I/O1: Page Buffer Ready/Busy is Ready. The Page Buffer Ready/Busy is output on I/O6 by Status Read operation or RY / BY pin after the 10h command. Status on I/O2: Data Ca che Read/Busy is Ready. The Data Cache Ready/Busy is output on I/O7 by Status Read operation or RY / BY pin after the 15h command. 80h…15h 70h Status Out Page 1 Page 1 Page 2 70h Status Out 70h Status Out Page 2 70h Status Out 80h…15h Page N 1 80h…10h Page N Page N 1 Page N 70h Status Out 80h…15h I/O2=> I/O1=> Invalid Invalid Page 1 Invalid Page N 2 Invalid Invalid Invalid Page N 1 Page N Page 1 Page 2 70h Status Out If the Page Buffer Busy returns to Ready before the next 80h co mmand input and Status Read is done during this Ready period, the Status Read provides the Pass/Fail result for Page 2 on I/O1 and the Pass/Fail result for Page1 on I/O2. Example) RY / BY pin Data Cache Busy Page Buffer Busy
2019-10-01C 31 © 2012-2019 KIOXIA Corporation Page Copy (2) By using Page Copy (2), data in a page can be copied to another page after the data has been read out. When the block address changes (increments) this sequence has to be started from the beginning. Page Copy (2) operation is as follows. 1. Data for Page N is transferred to the Data Cache. 2. Data for Page N is read out. 3. Address for Page M is input. If the data needs to be changed , changed data is input. 4. Data Cache for Page M is transferred to the Page Buffer. 5. After the Ready state, Data for Page N P1 is output from the Data Cache while the data of Page M is being programmed. When changing data, changed data is input. 4 5 tR tDCBSYW2 tDCBSYR2 RY / BY Command input Address CA0 to CA11, PA0 to PA15 (Page N) Address input 30 Address input 8C A Data input 15 00 Address input 3A Data output Address CA0 to CA11, PA0 to PA15 (Page M) Address CA0 to CA11, PA0 to PA15 (Page N+P1) A Data output Col = 0 start Col = 0 start Data Cache Page Buffer Cell Array 1 2 3 4 5 Page N Data for Page N Data for Page N Page M Page N + P1 Data for Page N + P1 Data for Page M
2019-10-01C 32 © 2012-2019 KIOXIA Corporation 6. Address for Page (M R1) is input. If the data needs to be changed, changed data is input. 7. After programming of page M is completed, Data Cache for Pag e M R1 is transferred to the Page Buffer. 8. By the 15h command, the data in the Page Buffer is programme d to Page M R1. Data for Page N P2 is transferred to the Data cache. 9. The data in the Page Buffer is programmed to Page M Rn 1. Data for Page N Pn is transferred to the Data Cache. RY / BY 8 9 tDCBSYW2 t DCBSYR2 t DCBSYR2 When changing data, changed data is input. Command input Address CA0 to CA11, PA0 to PA15 (Page M+R1) B 00 Address input 3A Data output Address input 8C Data input 15 00 Address input 3A Data output Address CA0 to CA11, PA0 to PA15 (Page N+P2) Address CA0 to CA11, PA0 to PA15 (Page N+Pn) A B A Col = 0 start Col = 0 start Data Cache Page Buffer Cell Array 6 7 8 Page M Data for Page M R1 Data for Page M R1 Data for Page N P2 Data for Page N Pn Page M R1 Page N + P2 Page N P1 Page M Rn 1 Page N Pn Page M + Rn 1
2019-10-01C 33 © 2012-2019 KIOXIA Corporation 10. Address for Page (M Rn) is input. If the data needs to be changed, changed data is input. 11. By issuing the 10h command, the data in the Page Buffer is programmed to Page M Rn. (*1) Since the last page’s programming by the 10h command is initiated after the previous cache program, the tPROG here will be expected as the following: tPROG tPROG of the last page tPROG of the previous page ( command input cycle address input cycle + data output/input cycle time of the last page) NOTE) Data input is required only if previous data output needs to be altered. If the data has to be changed, locate the desired address with the column and page address input after the 8Ch command, and change only the data that needs be changed. If the data does not have to be changed, data input cycles are not required. Make sure WP is held to High when the Page Copy (2) operation is performed. Also make sure the Page Copy operation is terminated with 8Ch-10h command sequence. RY / BY tPROG (*1) Command input Address CA0 to CA11, PA0 to PA15 (Page M+Rn) Address input 8C Data input 10 70 Status output B B Data Cache Page Buffer Page M Rn 1 Data for Page M Rn Data for Page M Rn Page M + Rn 10 11
2019-10-01C 34 © 2012-2019 KIOXIA Corporation Auto Block Erase The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0h” which follows the Erase Setup command “60h”. This two-cycle process for Erase operations acts as an extra layer of protection from accidental erasure of data due to external noise. The device automatically executes the Erase and Verify operations. Pass I/O Fail RY / B Y
60 D0 70
input: 2 cycles Status Read command Busy Erase Start command
Table 5. Code table
2019-10-01C 36 © 2012-2019 KIOXIA Corporation 4th Data Description I/O8 I/O7 I/O 6 I/O5 I/O4 I/O3 I/O2 I/O1 Page Size (without redundant area) 1 KB 2 KB 4 KB 8 KB Block Size (without redundant area) 64 KB 128 KB 256 KB 512 KB I/O Width x8 x16 0 Reserved 0 0 1 5th Data Description I/O8 I/O7 I/O 6 I/O5 I/O4 I/O3 I/O2 I/O1 District Number
1 District
2 Districts
4 Districts
8 Districts
R e s e r v e d 0 1 1 1 1 0
The device automatically implements the execution and verification of the Program and Erase operations. can also be used during a Read operation to monitor the Ready/Busy status. The resulting information is outlined in Table 6. Table 6. Status output table The Pass/Fail status on I/O1 and I/O2 is only valid during a Program/Erase operation when the device is in the Ready state. During an Auto Page Program or Auto Block Erase operation this bit indicates the Pass/Fail result. current page program operation and therefore this bit is only valid when I/O6 shows the Ready state. with Data Cache. This status is valid when I/O7 shows the Ready State.
2019-10-01C 38 © 2012-2019 KIOXIA Corporation An application example with multiple devices is shown in the figure below. System Design Note: If the RY / BY pin signals from multiple devices are wired together as shown in the diagram, the Status Read function can be used to determine the status of each individual device. Reset The Reset mode stops all operations. For example, in case of a Program or Erase operation, the internally generated voltage is discharged to 0 volts and the device enters the Wait state. Reset during a Cache Program/Page Copy may not just stop the most recent page program but it may also stop the previous program at a page depending on when the FF reset is input. The response to a “FFh” Reset command input during the various device operations is as follows: When a Reset (FFh) command is input during Program operation Device CLE CE Device CE Device CE Device N CE N Device N 1 CE N+1 ALE WE R E RY / B Y WE RE Status on Device 1 70h CE ALE I/O 70h Status on Device N RY / B Y CLE CE N Busy I/O1 to I/O8 Internal generated voltage 80 10 FF 00 RY / BY tRST (max 10 s)
2019-10-01C 39 © 2012-2019 KIOXIA Corporation When a Reset (FFh) command is input during Erase operation When a Reset (FFh) command is input during Read operation When a Reset (FFh) command is input during Ready When a Status Read command (70h) is input after a Reset When two or more Reset commands are input in succession RY / BY FF FF (3) (2) (1) T h e s e c o n d c o m mand is invalid, but the third c o m m and is valid. FF FF FF I/O status : Pass/Fail Pass : Ready/Busy Ready FF 70 RY / BY
00 FF 00
tRST (max 5 s) Internal generated voltage D0 FF 00 RY / BY tRST (max 500 s) RY / BY tRST (max 5 s) FF
2019-10-01C 40 © 2012-2019 KIOXIA Corporation APPLICATION NOTES AND COMMENTS (1) Power-on/off sequence The timing sequence shown in the figure below is necessary for the power-on/off sequence. The device’s internal initialization starts after the power supply reaches an appropriate level during the power-on sequence. During the initialization the device Ready/Busy signal indicates the Busy state as shown in the figure below. In this time period, the acceptable commands are FFh or 70h. The WP signal is useful for protecti ng against data corruption at power-on/off. (2) Power-on Reset The following sequence is necessary because some input signals may not be stable at power-on. (3) Prohibition of unspecified commands The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle. (4) Restriction of commands while in the Busy state During the Busy state, do not input any command except 70h and FFh. VIL Operation 0 V VCC 2.7 V 2.5 V VIL Don’t care Don’t care VIH CE , WE , RE W P CLE, ALE Invalid RY / BY 1 ms max 100 s max Don’t care Invalid 1 ms max 100 s max ≥ 1ms 2.7 V 2.5 V 0.5 V 0.5 V Invalid FF Reset Power on
2019-10-01C 41 © 2012-2019 KIOXIA Corporation (5) Acceptable commands after Serial Data Input command “80h” Once the Serial Data Input command “80h” has been input, do not input any command other than the Column Address Change in Serial Data Input command “85h”, Auto Page Program command “10h”, Auto Page Program with Data Cache Command “15h”, or the Reset command “FFh”. If a command other than “85h”, “10h”, “15h” or “FFh” is input, the Program operation is not performed and the device operation is set to the mode that the input command specifies. (6) Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to the MSB (most significant bit) page of the block. Random page address programming is prohibited. W E RY / B Y 80 FF Address input Command other than Programming cannot be executed. 10 XX Mode specified by the command. DATA IN: Data (1) Page 0 Data register Page 2 Page 1 Page 31 Page 63 (1) (2) (3) (32) (64) Data (64) From the LSB page to MSB page DATA IN: Data (1) Page 0 Data register Page 2 Page 1 Page 31 Page 63 (2) (32) (3) (1) (64) Data (64) e.g.) Random page program (Prohibition)
2019-10-01C 42 © 2012-2019 KIOXIA Corporation (7) Status Read during a Read operation The device status can be read out by inputting the Status Read command “70h” in Read mode. Once the device has been set to Status Read mode by a “70h” command, the device will not return to Read mode unless the Read command “00h” is input during [A]. If the Read command “00h” is input during [A], Status Read mode is reset, and the device returns to Read mode. In this case, data output starts automatically from address N and address input is unnecessary (8) Auto programming failure (9) RY / BY : termination for the Ready/Busy pin (RY / BY A pull-up resistor needs to be used for termination because the RY / BY buffer consists of an open drain circuit. Address N Command CE WE RY / BY RE [A] Status Read command input Status Read Status output This data may vary from device to device. We recommend to use this data as a reference for selecting a resistor value. VCC VCC Device VSS R RY / BY CL 1.5 s 1.0 s 0.5 s 0 1 K 4 K 3 K 2 K 15 ns 10 ns 5 ns tf tr R tr tf VCC 3 . 3 V Ta 25°C CL 50 pF tf Ready VCC tr Busy Fail 80 10 80 10 Address M Data input
70 I/O
N Data input If the programming result for page address M is Fail, do not tr y to program the page to address N in another block without the data input sequence. Because the previous input data has been lost in the Data Cache, the same input sequence of 80h command, address and data have to be executed. M N
2019-10-01C 43 © 2012-2019 KIOXIA Corporation (10) Note regarding the WP signal The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming Disable Programming Enable Erasing Disable Erasing WP tWW (100 ns MIN) 80 10 WE RY / BY DIN WP tWW (100 ns MIN) 60 D0 WE RY / BY DIN WP tWW (100 ns MIN) 80 10 WE RY / BY DIN WP tWW (100 ns MIN) 60 D0 WE RY / BY DIN
2019-10-01C 44 © 2012-2019 KIOXIA Corporation (11) When five address cycles are input Although the device may read in a fifth address, it is ignored inside the chip. Read operation Program operation CLE CE WE ALE I/O Address input Ignored 80h Data input CLE Address input 00h CE WE ALE I/O RY / BY Ignored 30h
2019-10-01C 45 © 2012-2019 KIOXIA Corporation (12) Several programming cycles on the same page (Partial Page Program) Each segment can be programmed individually as follows: Number of partial program cycles in the same page must not exceed 4. Data Pattern 4 Data Pattern 1 All 1 s All 1 s All 1 s All 1 s 1st programming 2nd programming 4th programming Result Data Pattern 1 Data Pattern 2 Data Pattern 4 Data Pattern 2
2019-10-01C 46 © 2012-2019 KIOXIA Corporation (13) Invalid blocks (bad blocks) The device occasionally contains unusable blocks. Therefore, th e following issues must be recognized: Please do not perform an erase operation to bad blocks. It may be impossible to recover the bad block’s information if the information is erased. Check if the device has any bad blocks after installation into the system. Refer to the test flow for bad block detection. Bad blocks which are detected by the test flow must be managed as unusable blocks by the system. A bad block does not affect the performance of good blocks because it is isolated from the bit lines by select gates. The number of valid blocks over the device lifetime is as follows: MIN TYP. MAX UNIT Valid (Good) Block Number 1004 1024 Blocks Bad Block Test Flow Regarding invalid blocks, bad block mark is in whole pages. Ple ase read one column of any page in each block. If the data of the column is 00 (Hex), define the block as a bad block. *1: No erase operation is allowed to detected bad blocks Bad Block Bad Block Pass Read Check Start Bad Block *1 Last Block END Yes Fail Block No 1 No Block No. Block No. 1
2019-10-01C 47 © 2012-2019 KIOXIA Corporation (14) Failure phenomena for Program, Erase and Read operations The device may fail during a Program or Erase operation. The following possible failure modes should be considered when implementing a highly reliable system. FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENCE Block Erase Failure Status Read after Erase Block Replacement Page Programming Failure Status Read after Program Block Replacement Read Bit Error Check the ECC status at host controller and take appropriate measures such as rewrite in consideration of Wear Leveling before uncorrectable ECC error occurs. ECC: Error Correction Code. 8 bi t correction per 512 Bytes is necessary. Block Replacement Program Erase When an error occurs during an Erase operation, prevent future accesses to this bad block (by creating a table within the system or by using another appropriate scheme). (15) Do not turn off the power before the Write/Erase operation is complete. Avoid using the device when the battery is low. Power shortage and/or power failure before the Write/Erase operation is complete will cause loss of data and/or damage to data. (16) Please refer to KIOXIA soldering temperature profile for details. When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, prevent further system accesses to Block A (by creating a bad block table or by using another appropriate scheme). Block A Block B Error occurs Buffer memory
2019-10-01C 48 © 2012-2019 KIOXIA Corporation (17) Reliability Guidance This reliability guidance is i ntended to provide some guidance related to using NAND Flash with 8 bit ECC for each 512 bytes. NAND Flash memory cells are gradually w orn out and the reliability level of memory cells is degraded by repeating Write and Erase operation of ‘0’ data in each block. For detailed reliability data, please refer to the reliability note for each product. Although random bit errors may occur during use, it does not necessarily mean that a block is bad. Generally, a block should be marked as bad when a program statu s failure or erase status failure is detected. The reliability of NAND Flash memo ry cells during the actual us age on system level depends on the usage and environmental conditions. KIOXIA adopts the checker p attern data, 0x55 & 0xAA for alternative Write/Erase cycles, for the reliability test. Write/Erase Endurance Write/Erase endurance failures may occur in a cell, page, or bl ock, and are detected by doing a Status Read after either an Auto Page Program or Auto Block Erase operation. The cumulative bad block count will increase along with the number of Write/Erase cycles. Data Retention The data in NAND Flash memory may change after a certain amount of storage time. This is due to charge loss or charge gain. After block erasure and reprogrammi ng, the block may become usable again. Data Retention time is gener ally influenced by the numbe r of Write/Erase cycles and temperature. Here is a graph plotting the relationship between Write/Erase Endurance and Data Retention. Read Disturb A Read operation may disturb the data in NAND Flash memory. The data may change due to charge gain. Usually, bit errors occur on other pages in the block, no t the page being read. After a large number of read cycles (between block erases), a tiny charge may build up and can cause a cell to be soft programmed to another state. After block erasure and repro gramming, the block may become usable again. Read Disturb capability is generally influenced by the number of Write/Erase cycles. Data Retention [Years] Write/Erase Endurance [Cycles]
2019-10-01C 49 © 2012-2019 KIOXIA Corporation (18) NAND Management NAND Management such as Bad Block Management, ECC treatment and Wear Leveling, but not limited to these treatments, should be recognized and incorporated in the system design. ECC treatment for read data is mandatory against random bit errors, and host should monitor ECC status to take appropriate measures such as rewrite in consideration of W ear Leveling before uncorrectable Error occurs. To realize robust system design generally it is necessa ry to prevent the concentration of Write/Erase cycles at the spec ific blocks by adopting Wear Leve ling which manages to distribute Write/Erase cycles evenly among NAND Flash memory. And also it is necessary to avoid dummy ‘0’ data write, e.g. ‘0’ data padding, which accelerate block endurance degradation. Continuous Write and Erase cycling with high percentage of '0' bits in data pattern can lead to faster block endurance degradation. Example: NAND cell array with ‘0’ data padding 010010000000 010110000000 101000000000 110010000000 001100000000 101010000000 010100000000 101010000000 010011111111 010111111111 101001111111 110011111111 001101111111 101011111111 010101111111 101011111111 : “1” data cell : “0” data cell 1 0 User data area User data area Remaining area Remaining area (a) Accelerate block endurance degradation by fixed dummy “0” data write (b) “1” data for Remaining area (Recommended)
2019-10-01C 50 © 2012-2019 KIOXIA Corporation Package Dimensions Weight: 0.53g (typ.)
2019-10-01C 51 © 2012-2019 KIOXIA Corporation
Revision History
Date Rev. Description 2012-02-17 0.10 Initial Release 2012-07-06 0.20 Described ECC bit number: 8, Changed tBERASE, R evised ID Table, Corrected typo. 2012-08-31 1.00 Deleted TE NTATIVE/TBD notation. 2018-12-14 1.10 Corrected ty po, and described some notes. Removed Soldering Temperature and added note in ABSOLUTE MAXIMUM RATINGS, and added comments in APPLICATION NOTES AND COMMENTS. Removed the word "Recommended" from the title of DC OPERATING CONDITIONS and AC CHARACTERISTICS AND OPERATING CONDITIONS. Renewed Reliability Guidance and added NAND Management. Changed “RESTRICTIONS ON PRODUCT USE”. 2019-10-01 2.00 Rebrand as "KIOXIA"
2019-10-01C 52 © 2012-2019 KIOXIA Corporation RESTRICTIONS ON PRODUCT USE KIOXIA Corporation and its subsidiaries and affiliates are collectively referred to as “KIOXIA”. Hardware, software and systems described in this document are collectively referred to as “Product”. KIOXIA reserves the right to m ake changes to the information in this document and related Product without notice. This document and any information herein may not be reproduced without prior written permission from KIOXIA. Even with KIOXIA's written permission, reproduction is permissible only if reproduction is without alteration/omission. Though KIOXIA works continually to improve Product's quality a nd reliability, Product can malfunction or fail. Customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant KIOXIA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "Reliability Information" in KIOXIA Corporation’s website and (b) the instructions for the application with which the Product will be used with or for. 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