TC58BVG2S0HTA00 KIOXIA | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 53
Technical content
2019-10-01C 1 © 2013-2019 KIOXIA Corporation MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
4 GBIT (512M 8 BIT) CMOS NAND E2PROM
DESCRIPTION
The TC58BVG2S0HTA00 is a single 3.3V 4Gbit (4,429,185,024 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (4096 128) bytes 64 pages 2048 blocks. The device has a 4224-byte static register which allows program and read data to be transferred between the register and the memory cell array in 4224-bytes increments. The Erase operation is implemented in a single block unit (256 Kbytes 8 Kbytes: 4224 bytes 64 pages). The TC58BVG2S0HTA00 is a serial -type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed , making the device most suitable for applications such as solid -state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. The TC58BVG2S0HTA00 has ECC logic on the chip and 8bit read errors f or each 528Bytes can be corrected internally.
FEATURES
Organization Memory cell array 4224 128K 8 Register 4224 8 Page size 4224 bytes Block size (256K 8K) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Read, Multi Page Program, Multi Block Erase, ECC Status Read Mode control Serial input/output Command control Number of valid blocks Min 2008 blocks Max 2048 blocks Power supply VCC 2.7V to 3.6V Access time Cell array to register 55 s typ. (Single Page Read) / 90 s typ. (Multi Page Read) Read Cycle Time 25 ns min (CL=50pF) Program/Erase time Auto Page Program 340 s/page typ. Auto Block Erase 2.5 ms/block typ. Operating current Read (25 ns cycle) 30 mA max Program (avg.) 30 mA max Erase (avg.) 30 mA max Standby 50 A max Package TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.) 8bit ECC for each 528Byte is implemented on the chip.
2019-10-01C 2 © 2013-2019 KIOXIA Corporation PIN ASSIGNMENT (TOP VIEW) PIN NAMES I/O1 to I/O8 I/O port CE Chip enable WE Write enable RE Read enable CLE Command latch enable ALE Address latch enable WP Write protect RY / BY Ready/Busy VCC Power supply VSS Ground NC No Connection NC NC NC NC I/O8 I/O7 I/O6 I/O5 NC NC NC VCC VSS NC NC NC I/O4 I/O3 I/O2 I/O1 NC NC NC NC 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 NC NC NC NC NC NC RY/BY RE CE NC NC VCC VSS NC NC CLE ALE WE WP NC NC NC NC NC TC58BVG2S0HTA00
2019-10-01C 3 © 2013-2019 KIOXIA Corporation BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS SYMBOL RATING VALUE UNIT VCC Power Supply Voltage 0.6 to 4.6 V VIN Input Voltage 0.6 to 4.6 V VI/O Input /Output Voltage 0.6 to VCC 0.3 ( 4.6 V) V PD Power Dissipation 0.3 W TSTG Storage Temperature 55 to 150 °C TOPR Operating Temperature 0 to 70 °C Note: Avoid locations where the device may be exposed to water (wet, rain, dew condensation, etc.) CAPACITANCE *(Ta 25°C, f 1 MHz) SYMBOL PARAMETER CONDITION MIN MAX UNIT CIN Input VIN 0 V 10 pF COUT Output VOUT 0 V 10 pF * This parameter is periodically sampled and is not tested for every device. I/O Control circuit Status register Command register Column buffer Column decoder Data register 0 Sense amp Memory cell array Control circuit HV generator Row address decoder Logic control RY / BY VCC I/O1 VSS CE CLE ALE WE RE RY / BY Row address buffer decoder to WP ECC Logic Address register Data register 1 I/O8
2019-10-01C 4 © 2013-2019 KIOXIA Corporation VALID BLOCKS SYMBOL PARAMETER MIN TYP. MAX UNIT NVB Number of Valid Blocks 2008 2048 Blocks NOTE: The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document. The first block (Block 0) is guaranteed to be a valid block at the time of shipment. The specification for the minimum number of valid blocks is applicable over lifetime. DC OPERATING CONDITIONS SYMBOL PARAMETER MIN TYP. MAX UNIT VCC Power Supply Voltage 2.7 3.6 V VIH High Level Input Voltage VCC x 0.8 VCC 0.3 V VIL Low Level Input Voltage 0.3* VCC x 0.2 V * 2 V (pulse width lower than 20 ns) DC CHARACTERISTICS (Ta 0 to 70°C, VCC 2.7 to 3.6V) SYMBOL PARAMETER CONDITION MIN TYP. MAX UNIT IIL Input Leakage Current VIN 0 V to VCC 10 A ILO Output Leakage Current VOUT 0 V to VCC 10 A ICCO1 Serial Read Current CE VIL, IOUT 0 mA, tRC 25 ns 30 mA ICCO2 Programming Current 30 mA ICCO3 Erasing Current 30 mA ICCS Standby Current CE VCC 0.2 V, WP 0 V/VCC 50 A VOH High Level Output Voltage IOH 0.1 mA VCC – 0.2 V VOL Low Level Output Voltage IOL 0.1 mA 0.2 V IOL (RY / BY ) Output Current of RY / BY pin VOL 0.2 V 4 mA
2019-10-01C 5 © 2013-2019 KIOXIA Corporation AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta 0 to 70°C, VCC 2.7 to 3.6V) SYMBOL PARAMETER MIN MAX UNIT tCLS CLE Setup Time 12 ns tCLH CLE Hold Time 5 ns tCS CE Setup Time 20 ns tCH CE Hold Time 5 ns tWP Write Pulse Width 12 ns tALS ALE Setup Time 12 ns tALH ALE Hold Time 5 ns tDS Data Setup Time 12 ns tDH Data Hold Time 5 ns tWC Write Cycle Time 25 ns tWH WE High Hold Time 10 ns tWW WP High to WE Low 100 ns tRR Ready to RE Falling Edge 20 ns tRW Ready to WE Falling Edge 20 ns tRP Read Pulse Width 12 ns tRC Read Cycle Time 25 ns tREA RE Access Time 20 ns tCEA CE Access Time 25 ns tCLR CLE Low to RE Low 10 ns tAR ALE Low to RE Low 10 ns tRHOH RE High to Output Hold Time 25 ns tRLOH RE Low to Output Hold Time 5 ns tRHZ RE High to Output High Impedance 60 ns tCHZ CE High to Output High Impedance 20 ns tCSD CE High to ALE or CLE Don’t Care 0 ns tREH RE High Hold Time 10 ns tIR Output-High-Impedance-to-RE Falling Edge 0 ns tRHW RE High to WE Low 30 ns tWHC WE High to CE Low 30 ns tWHR WE High to RE Low 60 ns tWB WE High to Busy 100 ns tRST Device Reset Time (Ready/Read/Program/Erase) 5/5/10/500 s *1: tCLS and tALS cannot be shorter than tWP. *2: tCS should be longer than tWP + 8ns.
2019-10-01C 6 © 2013-2019 KIOXIA Corporation AC TEST CONDITIONS PARAMETER CONDITION VCC: 2.7 to 3.6V Input level VCC-0.2V, 0.2V Input pulse rise and fall time 3 ns Input comparison level VCC / 2 Output data comparison level VCC / 2 Output load CL (50 pF) 1 TTL Note: Busy to ready time depends on the pull-up resistor tied to the RY / BY pin. (Refer to Application Note (9) toward the end of this document) PROGRAMMING / ERASING / READING CHARACTERISTICS (Ta 0 to 70°C, VCC 2.7 to 3.6V) SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES tPROG Average Programming Time (Single Page) 340 700 s Average Programming Time (Multi Page) 370 700 s tDCBSYW1 Busy Time in Multi Page Program(following 11h) 0.5 1 s N Number of Partial Program Cycles in the Same Page 4 (1) tBERASE Block Erasing Time 2.5 5 ms tR Memory Cell Array to Starting Address (Single Page) 55 220 Memory Cell Array to Starting Address (Multi Page) 90 420 (1) Refer to Application Note (12) toward the end of this document. Data Output When tREH is long, output buffers are disabled by /RE=High, and the hold time of data output depend s on tRHOH (25ns MIN). Under this condition, the waveforms look like Normal Serial Read Mode. When tREH is short, output buffers are not disabled by /RE=High, and the hold time of data output depend s on tRLOH (5ns MIN). Under this condition, output buffers are disabled by the rising edge of CLE, ALE, /CE or the falling edge of /WE, and waveforms look like Extended Data Output Mode.
2019-10-01C 7 © 2013-2019 KIOXIA Corporation TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data Command Input Cycle Timing Diagram CLE ALE CE WE Hold Time tDH Setup Time tDS I/O : VIH or VIL tCS tDH tDS tALS tALH tWP tCLS tCH tCLH : VIH or VIL CE CLE WE ALE I/O
2019-10-01C 8 © 2013-2019 KIOXIA Corporation Address Input Cycle Timing Diagram Data Input Cycle Timing Diagram WE tWP tWP tWH tWP tALS tWC tDH tDS DIN0 DIN1 tCLH tCH ALE CLE CE I/O DIN4223 tDH tDS tDH tDS tCS tCLS tCH tCS tALH PA16 PA8 to 15 CA8 to 12 : VIH or VIL tDH tDS tCLS CLE tALS tALH tWP tWH tWP CA0 to 7 tDH tDS tCS tCS CE WE ALE I/O tDH tDS tWP tWH tDH tDS tWP tWH tWC tDH tDS tWP tWH tWC PA0 to 7 tCLH tCH tCH
2019-10-01C 9 © 2013-2019 KIOXIA Corporation Serial Read Cycle Timing Diagram Status Read Cycle Timing Diagram tREH tCHZ CE tRHZ tREA tRC tRR tRHZ tREA tRHZ tREA RE RY / BY I/O tRHOH tRHOH tRHOH tRP tRP tRP : VIH or VIL tCEA Colu tCEA Colu : VIH or VIL *: 70h/71h represent the hexadecimal number tWHR WE tDH tDS tCLS tCLR tCS tCLH tCH tWP Status output 70h/71h* tWHC tIR tREA tRHZ tCHZ CE CLE RE RY / BY I/O tRHOH tCEA
2019-10-01C 10 © 2013-2019 KIOXIA Corporation ECC Status Read Cycle Timing Diagram : VIH or VIL * ECC Status output should be read for all 8 sector information. ** 7Ah command can be input to the device from [after RY / BY returns to High] to [before Dout or Next command input]. tWHR WE tDH tDS tCLS tCLR tCS tCLH tCH tWP Status output 7Ah* tWHC tIR tREA CE CLE RE RY / BY I/O tCEA Status output tREA Status output tREA Status output tREA Sector1 Sector2 Sector3 Sector4 Status output tREA Sector8
2019-10-01C 11 © 2013-2019 KIOXIA Corporation Read Cycle Timing Diagram Read Cycle Timing Diagram: When Interrupted by CE 30h PA16 PA8 to 15 PA0 to 7 CA8 to 12 CA0 to 7 I/O tCS tCLS tCLH tCH tDH tDS tWC tALS tALH WE CLE CE ALE RE tDH tDS tDH tDS tDH tDS tDH tDS tALH tR tDH tDS tWB tCS tCLS tCLH tCH tALS tRC tREA Col. Add. N Data out from Col. Add. N tDH tDS 00h DOUT N RY / BY 70h 00h status output tCLR tCLR tREA 30h PA16 PA8 to 15 PA0 to 7 CA8 to 12 CA0 to 7 I/O tCS tCLS tCLH tCH tDH tDS tWC tALS tALH WE CLE CE ALE RE tDH tDS tDH tDS tDH tDS tDH tDS tALH tCLR tR tDH tDS tWB tCS tCLS tCLH tCH tALS tRC tREA Col. Add. N tDH tDS 00h DOUT N RY / BY tCHZ tRHZ tRHOH Data out from Col. Add. N tCSD 70h 00h status output DOUT N+1 tREA tCLR
2019-10-01C 12 © 2013-2019 KIOXIA Corporation Column Address Change in Read Cycle Timing Diagram (1/2) RY / BY tCLR I/O tCS tCLS tCLH tCH tWC tALS tALH tR CLE CE ALE RE tDH tDS tDH tDS tALH tWB tCS tCLS tCLH tCH tALS tRC tREA Page address P Page address P Data out from Column address A 00h CA0 to 7 tDH tDS CA8 to 12 tDH tDS PA0 to 7 tDH tDS PA8 to 15 tDH tDS PA16 tDH tDS 30h DOUT A DOUT A 1 DOUT A N WE Column address A 70h Status Output 00h tCLR Continues to of next page
2019-10-01C 13 © 2013-2019 KIOXIA Corporation Column Address Change in Read Cycle Timing Diagram (2/2) I/O tCS tCLS tCLH tCH 05h CA0 to 7 CA8 to 12 tWC tALS tALH CLE CE ALE RE tDH tDS tDH tDS tDH tDS Column address B E0h tDH tDS tALH tCS tCLS tCLH tCH tALS tREA DOUT A N tRHW Page address P Data out from Column address B tRC tCLR tCEA tIR DOUT B N’ DOUT B 1 DOUT B WE RY / BY tWHR Continues from of previous page
2019-10-01C 14 © 2013-2019 KIOXIA Corporation Data Output Timing Diagram Command I/O tRC tDH tRP tRP WE CLE CE ALE RE tRLOH tREH tREA tRHZ tREA tCS tCLS tCLH tCH tRP tRR tREA tRLOH tDS RY / BY tCHZ tRHOH tRHOH tCEA Dout Dout tALH Dout
2019-10-01C 15 © 2013-2019 KIOXIA Corporation Auto-Program Operation Timing Diagram CA0 to 7 tCLS tCLS tALS tDS tDH WE CLE CE ALE RE RY / BY : VIH or VIL tCLH tCH tCS tDS tDH tALH I/O : Do not input data while data is being output. tCS tDH tDS tDH tPROG tWB tDS tALH tALS * M: up to 4223 Column address N CA8 to 12 DINN DINM* 10h 70h Status output PA0 to 7 PA8 to 15 PA16 80h DIN N+1 tRW
2019-10-01C 16 © 2013-2019 KIOXIA Corporation Multi-Page Program Operation Timing Diagram (1/2) Continues to 1 of next page I/O tCLS tALS tDS tDH 80h WE CLE CE ALE RE RY / BY : VIH or VIL tCLH tCH tCS tCLS tDS tDH tALH : Do not input data while data is being output. tCS tDH tDS tDH tDCBSYW1 DINN DIN N+1 tWB 81h tDS 11h tALH tALS DIN4223 PA16 CA0 to 7 CA8 to 12 PA0 to 7 PA8 to 15 Page Address M District-0 CA0 to 7
2019-10-01C 17 © 2013-2019 KIOXIA Corporation Multi-Page Program Operation Timing Diagram (2/2) Continues from 1 of previous page 71h tCLS tALS tDS tDH WE CLE CE ALE RE RY / BY : VIH or VIL tCLH tCH tCS tCLS tDS tDH tALH I/O : Do not input data while data is being output. tCS tDH tDS tDH tPROG tWB tDS tALH tALS DIN4223 81h CA0 to 7 CA8 to 12 PA0 to 7 PA8 to 15 PA16 DIN N+1 10h DINN Page Address M District-1 Status output
2019-10-01C 18 © 2013-2019 KIOXIA Corporation Auto Block Erase Timing Diagram tCS 60h PA8 to 15 WE CLE CE ALE RE RY / BY : VIH or VIL tCLS tCLH tCLS PA0 to 7 tDS tDH tALS : Do not input data while data is being output. Auto Block Erase Setup command I/O D0h 70h tWB tBERASE Busy Status Read command Erase Start command Status output tALH PA16
2019-10-01C 19 © 2013-2019 KIOXIA Corporation Multi Block Erase Timing Diagram : VIH or VIL : Do not input data while data is being output. 60h P A8 to 15 WE CLE CE ALE RE RY / BY tCS tCLS tCLH tCLS PA0 to 7 tDS tDH tALS D0h 71h tWB tBERASE Busy Status Read command Auto Block Erase Setup command I/O tALH Repeat 2 times (District-0,1) PA16 Status output Erase Start command
2019-10-01C 20 © 2013-2019 KIOXIA Corporation Copy Back Program with Random Data Input I/O I/O1=0 Successful Program I/O1=1 Error in Program Status Read command WE CLE RE I/Ox ALE CE tWC tWB Col Add1 00h 35h Col Add2 Row Add1 Row Add2 Row Add3 Col Add1 Col Add2 Row Add1 Data1 DataN 10h 70h Row Add2 Row Add3 tR Busy Busy tWB tPROG tWHR Copy Back Program Data Input Command Column Address Row Address Column Address Row Address 70h 00h t I/O Data1 DataN 85h I/O1=0 Successful Read I/O1=1 Error in Read RY/BY
2019-10-01C 21 © 2013-2019 KIOXIA Corporation ID Read Operation Timing Diagram : VIH or VIL WE CLE RE tCEA CE ALE I/O tAR ID Read command Address Maker code Device code tREA tCLS tCS tDS tCH tALH tALS tCLS tCS tCH tALH tDH 90h 00h 98h tREA DCh tREA tREA See Table 5 See Table 5 tREA If Fail See Table 5 3rd Data 4th Data 5th Data
2019-10-01C 22 © 2013-2019 KIOXIA Corporation PIN FUNCTIONS The device is a serial access memory which utilizes time-sharing input of address information. Command Latch Enable: CLE The CLE input signal is used to control loading of the operation mode command into the internal command register. The command is latched into the command register from the I/O port on the rising edge of the WE signal while CLE is High. Address Latch Enable: ALE The ALE signal is used to control loading address information into the internal address register. Address information is latched into the address register from the I/O port on the rising edge of WE while ALE is High. Chip Enable: CE The device goes into a low-power Standby mode when CE goes High while the device is in Ready state. The CE signal is ignored when the device is in Busy state (RY / BY L), such as during a Program, Erase or Read operation, and will not enter Standby mode even if the CE input goes High. Write Enable: WE - - - - - - - - The WE signal is used to control the acquisition of data from the I/O port. Read Enable: RE The RE signal controls serial data output. Data is available tREA after the falling edge of RE The internal column address counter is also incremented (Address = Address 1) on this falling edge. I/O Port: I/O1 to 8 The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from the device. Write Protect: WP - - - - - - - - The WP signal is used to protect the device from accidental programming or erasing. The internal voltage regulator is reset when WP is Low. This signal is usually used to protect the data during the po wer-on/off sequence when input signals are invalid. Ready/Busy: RY / BY The RY / BY output signal is used to indicate the operating c ondition of the device. The RY / BY signal is in Busy state (RY / BY = L) during the Program, Erase and Read operations and will retur n to Ready state (RY / BY = H) after completion of the operation. The output buffer for this signal is an open drain and has to be pulled up to VCC with an appropriate resistor.
The Program operation works on page units while the Erase operation works on block units. redundancy or for other uses. consecutive clock cycles, as shown in Table 1. Table 1. Addressing
64 Pages1 block
signals, as shown in Table 2. Table 2. Logic Table signal goes Low, Program or Erase operation is inhibited (Refer to Application Note (10) toward the end of this document). the device. Reset or Status Read command can be input during Read Busy.
Table 3. Command table (HEX) Table 4. Read mode operation states
2019-10-01C 26 © 2013-2019 KIOXIA Corporation DEVICE OPERATION Read Mode Read mode is set when the "00h" and “30h” commands are issued to the Command register. Between the two commands, a start address for the Read mode needs to be issued. After the initial power-on sequence, “00h” command is latched into the internal command register. Then the Read operation after the power-on sequence is executed by the setting of only five address cycles and “30h” command. The sequence of the block diagram are shown below (Refer to the detailed timing chart). Random Column Address Change in Read Cycle During the serial data output from the register, the column address can be changed by inputting a new column address using the 05h and E0h commands. The data is read out in serially starting at the new column address. Random Column Address Change operation can be done multiple times within the same page. Start-address input RY / BY WE CLE RE 00h CE ALE I/O Busy 30h Page Address N Column Address M M M+1 M+2 Page Address N tR Start-address input Status 70h 00h A data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising edge of WE in the 30h command input cycle (after the address information has been latched). The device will be in the Busy state during this transfer period. After the transfer period, the device returns to Ready state. Serial data can be output synchronously with the RE clock from the start address designated in the address input cycle. Cell array Select page N M m Data Cache Page Buffer I/O1 to 8: m 4223 RY / BY WE CLE 00h CE ALE I/O Col. M Page N Busy Page N 30h 05h E0h Col. M’ M M1 M’ M’1 M’2 M’3 M’4 Page N Col. M Start from Col. M Start from Col. M’ tR M2 M3 RE 70h Statu s 00h Select page N M M’
2019-10-01C 27 © 2013-2019 KIOXIA Corporation Multi Page Read Operation The device has a Multi Page Read operation. The sequence of command and address input is shown below. Same page address (PA0 to PA5) within each District has to be selected. The data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising edge of WE in the 30h command input cycle (after the 2 Districts’ address information has been latched). The device will be in the Busy state during this transfer period. After the transfer period, the device returns to Ready state. Serial data can be output synchronously with the RE clock from the start address designated in the address input cycle. RY / BY Command input Page Address PA0 to PA16 (District 0) tR Address input Page Address PA0 to PA16 (District 1) Address input A A RY / BY Command input Column + Page Address CA0 to CA12, PA0 to PA16 (District 0) Address input Column Address CA0 to CA12 (District 0) Address input B B A A Data output RY / BY Command input Column + Page Address CA0 to CA12, PA0 to PA16 (District 1) Address input Column Address CA0 to CA12 (District 1) Address input B B Data output (District 0) (District 1) (3 cycles) (3 cycles) (5 cycles) (5 cycles) (2 cycles) (2 cycles) Pass Fail ”1” ”0” I/O1 ECC Status command <7Ah> can be used only for Single Page Read. It is not supported for Multi Page Read operation. Selected page Reading District 0 District 1 Selected page
2019-10-01C 28 © 2013-2019 KIOXIA Corporation Internal addressing in relation to the Districts To use the Multi Page Read operation, the internal addressing should be considered in relation to the District. The device consists of 2 Districts. Each District consists of 1024 erase blocks. The allocation rule is as follows: District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046 District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047 Address input restriction for the Multi Page Read operation There are the following restrictions in using Multi Page Read: (Restriction) Maximum one block should be selected from each District. Same page address (PA0 to PA5) within two districts has to be selected. For example: (60) [District 0, Page Address 0x00000] (60) [District 1, Page Address 0x00040] (30) (60) [District 0, Page Address 0x00001] (60) [District 1, Page Address 0x00041] (30) (Acceptance) There is no order limitation of the District for the address input. For example, the following operation is accepted: (60) [District 0] (60) [District 1] (30) (60) [District 1] (60) [District 0] (30) It requires no mutual address relation between the selected blocks from each District. Operating restriction during the Multi Page Read operation Make sure WP is held to High when the Multi Page Read operation is performed.
2019-10-01C 29 © 2013-2019 KIOXIA Corporation ECC & Sector definition for ECC Internal ECC logic generates Error Correction Code during busy time in program operation. The ECC logic manages 9bit error detection and 8bit error correction in each 528Bytes of main data and spare data. A section of main field (512Bytes) and spare field (16Bytes) are paired for ECC. During Read operation, the device executes ECC of itself. Once Read operation is executed, Status Read Command (70h) can be issued to check the read status. The read status remains until other valid commands are executed. To use ECC function, below limitation must be considered. - A sector is the minimum unit for program operation and the number of program per page must not exceed 4. 4KByte Page Assignment Note) The Internal ECC manages all data of Main area and Spare area. Definition of 528Byte Sector Note) The ECC parity code generated by internal ECC is stored in column addresses 4224-4351 and the user cannot access to these specific addresses. While using the Partial Page Program, the user must program the data to main field and spare field simultaneously by the definition of sector. 1st Main 2nd Main 3rd Main 4th Main 5th Main 6th Main 7th Main 8th Main 1st Spare 2nd Spare 3rd Spare 4th Spare 5th Spare 6th Spare 7th Spare 8th Spare 512B 512B 512B 512B 512B 512B 512B 512B 16B 16B 16B 16B 16B 16B 16B 16B Sector Column Address (Byte) Main Field Spare Field 1st Sector 0 to 511 4,096 to 4,111 2nd Sector 512 to 1,023 4,112 to 4,127 3rd Sector 1,024 to 1,535 4,128 to 4,143 4th Sector 1,536 to 2,047 4,144 to 4,159 5th Sector 2,048 to 2,559 4,160 to 4,175 6th Sector 2,560 to 3,071 4,176 to 4,191 7th Sector 3,072 to 3,583 4,192 to 4,207 8th Sector 3,584 to 4,095 4,208 to 4,223
2019-10-01C 30 © 2013-2019 KIOXIA Corporation Auto Page Program Operation The device carries out an Auto Page Program operation when it receives a "10h" Program command after the address and data have been input. The sequence of command, address and data input is shown below (Refer to the detailed timing chart). Random Column Address Change in Auto Page Program Operation The column address can be changed by the 85h command during the data input sequence of the Auto Page Program operation. Two address input cycles after the 85h command are recognized as a new column address for the data input. After the new data is input to the new column address, the 10h command initiates the actual data program into the selected page automatically. T he Random Column Address Change operation can be repeated multiple times within the same page. CLE 80h ALE I/O Page P CE WE Col. M Din 10h 70h Din Din Din Data Status Out RE RY / BY The data is transferred (programmed) from the Data Cache via the Page Buffer to the selected page on the rising edge of WE following input of the “10h” command. After programming, the programmed data is transferred back to the Page Buffer to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. Selected page Program Data input Read & verification 80h Page N Col. M 85h Din Din 10h Status Din Din Din Din Col. M’ Din Din 70h Busy Data input Selected page Read & verification Program Col. M Col. M’
2019-10-01C 31 © 2013-2019 KIOXIA Corporation Multi Page Program The device has a Multi Page Program, which enables even higher speed program operation compared to Auto Page Program. The sequence of command, address and data input is shown below (Refer to the detailed timing chart). Although two Districts are programmed simultaneously, Pass/Fail is not available for each page by “70h” command when the program operation completes. The status bit of I/O 1 is set to “1” when any of the pages fail. Limitation in addressing with Multi Page Program is shown below. Multi Page Program NOTE: Any command between 11h and 81h is prohibited except 70h and FFh. The 71h command Status description is as below. STATUS OUTPUT I/O1 describes the Pass/Fail condition of District 0 and 1(OR data of I/O2 and I/O3). If one of the Districts fails during Multi Page Program operation, it shows “Fail”. I/O2 to 3 show the Pass/Fail condition of each District. I/O1 Chip Status : Pass/Fail Pass: 0 Fail: 1 I/O2 District 0 Chip Status : Pass/Fail Pass: 0 Fail: 1 I/O3 District 1 Chip Status : Pass/Fail Pass: 0 Fail: 1 I/O4 Not Used Invalid I/O5 Not Used Invalid I/O6 Ready/Busy Ready: 1 Busy: 0 I/O7 Ready/Busy Ready: 1 Busy: 0 I/O8 Write Protect Protect: 0 Not Protect: 1 Data Input 80h 11h District 0 (1024 Block) Block 0 Block 2 Block 2044 Block 2046 81h 10h District 1 (1024 Block) Block 1 Block 3 Block 2045 Block 2047 I/O1 to 8 I/O1 Pass Fail ”1” ”0” tDCBSYW1 tPROG CA0 to CA12 : Valid PA0 to PA5 : Valid’ PA6 : District0’ PA7 to PA16 : Valid’ 80h Address & Data Input 11h CA0 to CA12 : Valid PA0 to PA5 : Valid PA6 : District1 PA7 to PA16 : Valid 81h Address & Data Input 10h 70h/71h Note RY / BY
2019-10-01C 32 © 2013-2019 KIOXIA Corporation Internal addressing in relation to the Districts To use the Multi Page Program operation, the internal addressing should be considered in relation to the District. The device consists of 2 Districts. Each District consists of 1024 erase blocks. The allocation rule is as follows: District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046 District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047 Address input restriction for the Multi Page Program operation There are the following restrictions in using Multi Page Program: (Restriction) Maximum one block should be selected from each District. Same page address (PA0 to PA5) within two Districts has to be selected. For example: (80) [District 0, Page Address 0x00000] (11) (81) [District 1, Page Address 0x00040] (10) (80) [District 0, Page Address 0x00001] (11) (81) [District 1, Page Address 0x00041] (10) (Acceptance) There is no order limitation of the District for the address input. For example, the following operation is accepted: (80) [District 0] (11) (81) [District 1] (10) (80) [District 1] (11) (81 ) [District 0] (10) It requires no mutual address relation between the selected blocks from each District. Operating restriction during the Multi Page Program operation (Restriction) The operation must be terminated with “10h” command. Once the operation has started, no commands other than the commands shown in the timing diagram are allowed to be input except for Status Read command and Reset command.
2019-10-01C 33 © 2013-2019 KIOXIA Corporation Auto Block Erase The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0h” which follows the Erase Setup command “60h”. This two-cycle process for Erase operations acts as an extra layer of protection from accidental erasure of data due to external noise. The device automatically executes the Erase and Verify operations. Multi Block Erase The Multi Block Erase operation starts by selecting two block addresses before D0h command as in the below diagram. The device automatically executes the Erase and Verify operations and the result can be monitored by checking the status with 71h Status Read command. For details on 71h Status Read command, refer to section “Multi Page Program”. Internal addressing in relation to the Districts To use the Multi Block Erase operation, the internal addressing should be considered in relation to the District. The device consists of 2 Districts. Each District consists of 1024 erase blocks. The allocation rule is as follows: District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046 District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047 Address input restriction for the Multi Block Erase There are the following restrictions in using Multi Block Erase: (Restriction) Maximum one block should be selected from each District. For example; (60) [District 0] (60) [District 1] (D0) (Acceptance) There is no order limitation of the District for the address input. For example, the following operation is accepted: (60) [District 1] (60) [District 0] (D0) It requires no mutual address relation between the selected blocks from each District. Make sure to terminate the operation with D0h command. If the operation needs to be terminated before D0h command input, input the FFh reset command to terminate the operation. Pass I/O Fail RY / BY Block Address input: 3 cycles Status Read command Busy Erase Start command Pass I/O Fail RY / BY Block Address input: 3 cycles District 0 Status Read command Busy Erase Start command Block Address input: 3 cycles District 1
2019-10-01C 34 © 2013-2019 KIOXIA Corporation READ FOR COPY-BACK WITH DATA OUTPUT TIMING GUIDE Copy-Back operation is a sequence execution of Read for Copy-Back and of Copy-Back Program with the destination page address. A read operation with “35h” command and the address of source page moves the whole 4224 bytes data into the internal data buffer. Bit errors are checked by sequential reading the data or by reading the status in read after read busy time (tR) to check if uncorrectable error occurs. In the case of there is no bit error or no uncorrectable error, the data don’t need to be reloaded. Therefore Copy -Back Program operation is initiated by issuing Page -Copy Data-Input command (85h) with the destination page address. Actual programming operation begins after Program Confirm command (10h) is issued. Once the program process starts, the Status Read command (70h) may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the RY / BY output, or the Status Bit (I/O7) of the Status Register. When the Copy -Back Program is complete d, the Write Status Bit (I/O1) may be checked. The command register remains in Status Read mode until another valid command is written to the command register. During Copy-Back Program, the data modification is possible using Random Data Input command (85h) as shown below. Page Copy-Back Program Operation NOTE: 1. Copy-Back Program operation is allowed only within the same district. Page Copy-Back Program Operation with Random Data Input Col. Add.1,2 & Page Add.1,2,3 Source Address I/Ox 00h Add.(5Cycles) tR 35h I/Ox Col. Add.1,2 & Page Add.1,2,3 Destination Address tPROG Data Output 85h Add.(5Cycles) Data 85h Add.(2Cycles) Data 10h 70h Col. Add.1,2 There is no limitation for the number of repetition I/O1 Pass Fail ”1” ”0” 70h A A A A 00h RY / BY RY / BY Col. Add.1,2 & Page Add.1,2,3 Source Address I/Ox I/O1 Pass Fail ”1” ”0” Col. Add.1,2 & Page Add.1,2,3 Destination Address tR tPROG Data Output I/O1 Pass Fail ”1” ”0” 00h Add.(5 Cycles) 35h 70h Add.(5 Cycles) 00h 10h 70h 85h RY / BY
Table 5. Code table
2019-10-01C 36 © 2013-2019 KIOXIA Corporation 4th Data Description I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 Page Size (without redundant area) 1 KB 2 KB 4 KB 8 KB Block Size (without redundant area) 64 KB 128 KB 256 KB 512 KB I/O Width x8 x16 0 Reserved 0 0 1 5th Data Description I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 District Number
1 District
2 Districts
4 Districts
8 Districts
ECC engine on chip With ECC engine 1 Reserved 1 1 1 1 0
The device automatically implements the execution and verification of the Program and Erase operations. The resulting information is outlined in Table 6. Table 6. Status output table The Pass/Fail status on I/O1 is only valid during a Program/Erase/Read operation when the device is in the Ready state.
2019-10-01C 38 © 2013-2019 KIOXIA Corporation ECC Status Read The ECC Status Read function is used to monitor the Error Correction Status. The device can correct up to 8bit errors. ECC can be performed on the NAND Flash main and spare areas. The ECC Status Read function can also show the number of errors in a sector as a result of an ECC check during a Read operation. 8 7 6 5 4 3 2 I/O1 Sector Information ECC Status ECC Status I/O4 to I/O1 ECC Status
0000 No Error
0001 1bit error(Correctable) 0010 2bit error(Correctable) 0011 3bit error(Correctable) 0100 4bit error(Correctable) 0101 5bit error(Correctable) 0110 6bit error(Correctable) 0111 7bit error(Correctable) 1000 8bit error(Correctable)
1111 Uncorrectable Error
I/O8 to I/O5 Sector Information 0000 1st Sector (Main and Spare area) 0001 2nd Sector (Main and Spare area) 0010 3rd Sector (Main and Spare area) 0011 4th Sector (Main and Spare area) 0100 5th Sector (Main and Spare area) 0101 6th Sector (Main and Spare area) 0110 7th Sector (Main and Spare area) 0111 8th Sector (Main and Spare area) Other Reserved
2019-10-01C 39 © 2013-2019 KIOXIA Corporation Reset The Reset mode stops all operations. For example, in case of a Program or Erase operation, the internally generated voltage is discharged to 0 volts and the device enters the Wait state. The response to a “FFh” Reset command input during the various device operations is as follows: When a Reset (FFh) command is input during Program operation Internal generated voltage FF RY / BY tRST (max 10 s)
2019-10-01C 40 © 2013-2019 KIOXIA Corporation When a Reset (FFh) command is input during Erase operation When a Reset (FFh) command is input during Read operation When a Reset (FFh) command is input during Ready When a Status Read command (70h) is input after a Reset When two or more Reset commands are input in succession RY / BY FF FF (3) (2) (1) The second command is invalid, but the third command is valid. FF FF FF I/O status : Pass/Fail Pass : Ready/Busy Ready FF RY / BY FF RY / BY tRST (max 5 s) Internal generated voltage FF RY / BY tRST (max 500 s) RY / BY tRST (max 5 s) FF
2019-10-01C 41 © 2013-2019 KIOXIA Corporation APPLICATION NOTES AND COMMENTS (1) Power-on/off sequence The timing sequence shown in the figure below is necessary for the power-on/off sequence. The device’s internal initialization starts after the power supply reaches an appropriate level during the power-on sequence. During the initialization the device Ready/Busy signal indicates the Busy state as shown in the figure below. In this time period, the acceptable commands are FFh or 70h. The WP signal is useful for protecting against data corruption at power-on/off. (2) Power-on Reset The following sequence is necessary because some input signals may not be stable at power-on. (3) Prohibition of unspecified commands The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle. (4) Restriction of commands while in the Busy state During the Busy state, do not input any command except 70h, 71h and FFh. FF Reset Power on VIL Operation 0 V VCC 2.7 V 2.5 V VIL Don’t care Don’t care VIH CE , WE , RE WP CLE, ALE Invalid Invalid RY / BY 1 ms max 100 s max Don’t care Invalid 1 ms max 100 s max ≥ 1ms 2.7 V 2.5 V 0.5 V 0.5 V
2019-10-01C 42 © 2013-2019 KIOXIA Corporation (5) Acceptable commands after Serial Data Input command “80h” Once the Serial Data Input command “80h” has been input, do not input any command other than the Column Address Change in Serial Data Input command “85h”, Auto Page Program command “10h”, Multi Page Program command “11h” or the Reset command “FFh”. If a command other than “85h”, “10h”, “11h” or “FFh” is input, the Program operation is not performed and the device operation is set to the mode that the input command specifies. (6) Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to the MSB (most significant bit) page of the block. Random page address programming is prohibited. DATA IN: Data (1) Page 0 Data register Page 2 Page 1 Page 31 Page 63 (1) (2) (3) (32) (64) Data (64) From the LSB page to MSB page DATA IN: Data (1) Page 0 Data register Page 2 Page 1 Page 31 Page 63 (2) (32) (3) (1) (64) Data (64) e.g.) Random page program (Prohibition) Command other than Programming cannot be executed. XX Mode specified by the command. WE RY / BY FF Address input
2019-10-01C 43 © 2013-2019 KIOXIA Corporation (7) Status Read during a Read operation The device status can be read out by inputting the Status Read command “70h” in Read mode. Once the device has been set to Status Read mode by a “70h” command, the device will not return to Read mode unless the Read command “00h” is input during [A]. If the Read command “00h” is input during [A], Status Read mode is reset, and the device returns to Read mode. In this case, data output starts automatically from address N and address input is unnecessary. (8) Auto programming failure (9) RY / BY : termination for the Ready/Busy pin (RY / BY A pull-up resistor needs to be used for termination because the RY / BY buffer consists of an open drain circuit. Address N Command CE WE RY / BY RE [A] Status Read command input Status Read Status output This data may vary from device to device. We recommend to use this data as a reference for selecting a resistor value. VCC VCC Device VSS R RY / BY CL tf Ready VCC tr Busy 1.5 s 1.0 s 0.5 s
1 K
4 K
3 K
2 K
R tr tf VCC 3.3 V Ta 25°C CL 50 pF Fail 80 10 80 10 Address M Data input
70 I/O
N Data input If the programming result for page address M is Fail, do not try to program the page to address N in another block without the data input sequence. Because the previous input data has been lost in the Data Cache, the same input sequence of 80h command, address and data have to be executed. M N
2019-10-01C 44 © 2013-2019 KIOXIA Corporation (10) Note regarding the WP signal The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming Disable Programming Enable Erasing Disable Erasing WP tWW (100 ns MIN) WE RY / BY DIN WP tWW (100 ns MIN) WE RY / BY DIN WP tWW (100 ns MIN) WE RY / BY DIN WP tWW (100 ns MIN) WE RY / BY DIN
2019-10-01C 45 © 2013-2019 KIOXIA Corporation (11) When six address cycles are input Although the device may read in a sixth address, it is ignored inside the chip. Read operation Program operation CLE CE WE ALE I/O Address input Ignored 80h Data input CLE Address input 00h CE WE ALE I/O RY / BY Ignored 30h
2019-10-01C 46 © 2013-2019 KIOXIA Corporation (12) Several programming cycles on the same page (Partial Page Program) ECC Parity Code is generated during program operation on Main area (512 byte) + Spare area (16byte).While using the Partial Page Program, the user must program the data to main field and spare field simultaneously by the definition of sector in section “ECC & Sector definition for ECC”. For example, each segment can be programmed individually as follows: Number of partial program cycles in the same page must not exceed 4.
2019-10-01C 47 © 2013-2019 KIOXIA Corporation (13) Invalid blocks (bad blocks) The device occasionally contains unusable blocks. Therefore, the following issues must be recognized: Please do not perform an erase operation to bad blocks. It may be impossible to recover the bad block’s information if the information is erased. Check if the device has any bad blocks after installation into the system. Refer to the test flow for bad block detection. Bad blocks which are detected by the test flow must be managed as unusable blocks by the system. A bad block does not affect the performance of good blocks because it is isolated from the bit lines by select gates. The number of valid blocks over the device lifetime is as follows: MIN TYP. MAX UNIT Valid (Good) Block Number 2008 2048 Blocks Bad Block Test Flow Regarding invalid blocks, bad block mark is in whole pages. Please read one column of any page in each block. If the data of the column is 00 (Hex), define the block as a bad block. For Bad Block Test Flow during Read Check, regardless of Status Read result (ECC Pass or Fail), use the read data value to make judgement for Bad Block. *1: No erase operation is allowed to detected bad blocks. Bad Block Bad Block Pass Read Check Start Entry Bad Block *1 Last Block End Yes Fail Block No 1 No Block No. Block No. 1
2019-10-01C 48 © 2013-2019 KIOXIA Corporation (14) Failure phenomena for Program, Erase and Read operations The device may fail during a Program, Erase or Read operation. The following possible failure modes should be considered when implementing a highly reliable system. FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENCE Block Erase Failure Status Read after Erase Block Replacement Page Programming Failure Status Read after Program Block Replacement Read 9bit Failure (uncorrectable error) Check the ECC correction status by Status Read or ECC Status Read and take appropriate measures such as rewrite in consideration of Wear Leveling before uncorrectable ECC error occurs. ECC: Error Correction Code. 8 bit correction per 528Bytes is executed in a device. Block Replacement Program Erase When an error occurs during an Erase operation, prevent future accesses to this bad block (by creating a table within the system or by using another appropriate scheme). (15) Do not turn off the power before the Write/Erase operation is completed. Avoid using the device when the battery is low. Power shortage and/or power failure before the Write/Erase operation is completed will cause loss of data and/or damage to data. (16) Please refer to KIOXIA soldering temperature profile for detail. When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, prevent further system accesses to Block A (by creating a bad block table or by using another appropriate scheme). Block A Block B Error occurs Buffer memory
2019-10-01C 49 © 2013-2019 KIOXIA Corporation (17) Reliability Guidance This reliability guidance is intended to notify some guidance related to using NAND Flash with 8 bit ECC for each 512 bytes. NAND Flash memory cells are gradually worn out and the reliability level of memory cells is degraded by repeating Write and Erase operation of ‘0’ data in each block. For detailed reliability data, please refer to the reliability note for each product. Although random bit errors may occur during use, it does not necessarily mean that a block is bad. Generally, a block should be marked as bad when a program status failure or erase status failure is detected. The reliability of NAND F lash memory cells during the a ctual usage on system level depends on the usage and environmental conditions. KIOXIA adopts the checker pattern data, 0x55 & 0xAA for alternative Write/Erase cycles, for the reliability test. Write/Erase Endurance Write/Erase endurance failures may occur in a cell, page, or block, and are detected by doing a Status Read after either an Auto Page Program or Auto Block Erase operation. The cumulative bad block count will increase along with the number of Write/Erase cycles. Data Retention The data in NAND Flash memory may change after a certain amount of storage time. This is due to charge loss or charge gain. After block erasure and reprogramming, the block may become usable again. Data Retention time is generally influenced by the number of Write/Erase cycles and temperature. Here is a graph plotting the relationship between Write/Erase Endurance and Data Retention. Read Disturb A Read operation may disturb the data in NAND F lash memory. The data may change due to charge gain. Usually, bit errors occur on other pages in the block, not the page being read. After a large number of read cycles (between block erases), a tiny charge may build up and can cause a cell to be soft programmed to another state. After block erasure and reprogramming, the block may become usable again. Read Disturb capability is generally influenced by the number of Write/Erase cycles. Write/Erase Endurance [Cycles] Data Retention [Years]
2019-10-01C 50 © 2013-2019 KIOXIA Corporation (18) NAND Management NAND Management such as Bad Block Management, ECC treatment and Wear Leveling, but not limited to these treatments, should be recognized and incorporated in the system design. ECC treatment for read data is mandatory against random bit errors, and host should monitor ECC status to take appropriate measures such as rewrite in consideratio n of Wear Leveling before uncorrectable Error occurs. To realize robust system design, generally it is necessary to prevent the concentration of Write/Erase cycles at the specific blocks by adopting Wear Leveling which manages to distribute Write/Erase cycles evenly among NAND Flash memory. And also it is necessary to avoid dummy ‘0’ data write, e.g. ‘0’ data padding, which accelerate block endurance degradation. Continuous Write and Erase cycling with high percentage of '0' bits in data pattern can lead to faster block endurance degradation. Example: NAND cell array with ‘0’ data padding 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 : “1” data cell : “0” data cell User data area User data area Remaining area Remaining area (a) Accelerate block endurance degradation by fixed dummy “0” data write (b) “1” data for Remaining area (Recommended)
2019-10-01C 51 © 2013-2019 KIOXIA Corporation Package Dimensions Weight: 0.53 g (typ.)
2019-10-01C 52 © 2013-2019 KIOXIA Corporation
Revision History
Date Rev. Description 2013-03-15 0.10 Preliminary version 2013-07-05 1.00 Deleted TENTATIVE notation. Clarification for the Package Weight. 2018-06-01 1.10 Corrected typo, and described some notes. Attached Reliability Guidance and NAND Management. Changed “RESTRICTIONS ON PRODUCT USE”. 2019-10-01 2.00 Rebrand as "KIOXIA" Corrected typo and described some notes. Removed Soldering Temperature and added notes in ABSOLUTE MAXIMUM RATINGS, and added comments in APPLICATION NOTES AND COMMENTS.
2019-10-01C 53 © 2013-2019 KIOXIA Corporation RESTRICTIONS ON PRODUCT USE KIOXIA Corporation and its subsidiaries and affiliates are collectively referred to as “KIOXIA”. Hardware, software and systems described in this document are collectively referred to as “Product”. KIOXIA reserves the right to make changes to the information in this document and related Product without notice. This document and any information herein may not be reproduced without prior written permission from KIOXIA. Even with KIOXIA's written permission, reproduction is permissible only if reproduction is without alteration/omission. Though KIOXIA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant KIOXIA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "Reliability Information" in KIOXIA Corporation’s website and (b) the instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. KIOXIA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS. PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH MA Y CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT ("UNINTENDED USE"). Except for specific applications as expressly stated in this document, Unintended Use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, lifesaving and/or life supporting medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, and devices related to power plant. IF YOU USE PRODUCT FOR UNINTENDED USE, KIOXIA ASSUMES NO LIABILITY FOR PRODUCT. For details, please contact your KIOXIA sales representative or contact us via our website. Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part. Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. The information contained herein is presented only as guidance for Product use. No responsibility is assumed by KIOXIA for any infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, KIOXIA (1) ASSUMES NO LIABILITY WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT. Do not use or otherwise make available Product or related software or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). Product and related software and technology may be controlled under the applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations. Please contact your KIOXIA sales representative for details as to environmental matters such as the RoHS compatibility of Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. KIOXIA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS.