TC57256AD-15 | DigiCamel IC Datasheet

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TC57256AD TOSHIBA | Alldatasheet

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32,768 WORD X 8 BIT CMOS UV ERASABLE AND TC57256AD-15 ELECTRICALLY PROGRAMMABEL. READ ONLY TC5725 D MEMORY Cc 6AD-20 _ SILICON STACKED GATE MOS _ ee

DESCRIPTION

The TC57256AD is a 32,768 word x 8 bit CMOS __evel signal to the CE input. Advanced CMOS techn- ultraviolet light erasable and electrically programmable nology reduces the maximum active current to 30 read only memory. For read operation, the TC mA/6.7MHz and standby current to 100A 57256AD's access time is 150ns, and the TC57256AD For program operation, the programming is achieved operates from a single 5-volt power supply and has by using the high speed programming mode. low power standby mode which reduces the power TC57256A0 is fabricated with the CMOS technology dissipation without increasing access time. The and the N-channel silicon double layer gate MOS standby mode is achieved by applying a TTL-high technology.

FEATURES

© Peripheral circuit: CMOS © Single SV power supply Memory cell N-MOS © Full static operation © Low power dissipation © High speed programming mode 30mA/6. 7MHZ (atcive) © Inputs and outputs TTL compatible 100uA (standby) © Pin compatiole with ROM TC53257P and © Fast access time TC57256AD-15 150ns TMM23256P EPROM i27256 1C57256AD-20 200ns © Standard 28 pin DIP cerdip Package PIN CONNECTION (TOP VIEW) BLOCK DIAGRAM PIN NAMES MODE SELECTION fantay | Ares ings] [pin TE TBE | Vw [Voc | Ge~ Or fo Oo ~ On Outputs (inputs) MODE ~ (20) (22) a) (28) lon 13, 15 ~ 19) POWER ce Chip Enable Input 1 Read To Lot av | DateOu —— TE | Output Enable input | Output Deselect | * | _H 5V BV | High impedance | Active | Ver Pr garam Supply Standby | H || | 8V | High impedance 1 Standby 7] a Program Lon Data in = Power S i” a hib: + po ____ Mec | ‘Power SyPW Volteae ‘Program inhibie T H Hj 12.8v| 6v | High Impedance | Active | GND Ground — Froaram Verify | s Et Data Out | a em * > Hort FE OO ~715-

INTEGRATED CIRCUIT TOSHIBA MOS INTEGRATED CIRCUIT OSHIBA TC57256AD-15,TC57256AD~20 TECHNICAL DATA SILICON STACKED GATE MOS 32,768 WORD x 8 BIT CMOS UV ERASABLE AND ELECTRICALLY PROGRAMMABLE READ ONLY MEMORY The TC57256AD is a 32,768 word 8 bit CMOS ultraviolet light erasable and electri- cally programmable read only memory. For read operation, the TC57256AD's access time is 150ns,and the TC57256AD operates from a single 5-volt power supply and has low power standby mode which reduces the power dissipation without increasing access time. The standby mode is achieved by applying a TTL-high level signal to the CE input. Advanced CMOS technology reduces the maximum active current to 30mA/6.7MHz and standby current to 100uA. For program operation, the programming is achieved by using the high speed progranming mode. For program operation, the programming is achieved by using high speed programming mode, TC57256AD is fabricated with the CMOS technology and the N-channel silicon double layer gate MOS technology. . : + Single 5V power supply Peripheral circuit: C¥OS + Full static operation lemory cell 2 NoMOS + High speed programming mode . how power San earl + Inputs and outputs TTL compatible Standby: 100uA. + Pin compatible with ROM TC53257P, yt TMM23256P, TMM27256AD and TC57256D * Fast secsss times + Standard 28 pin DIP cerdi Ki 1TC57256AD-15 1{50ns ar pin +P Package TC57256AD-20 200ns. BLOCK DIAGRAM ¥y v _ PIN CONNECTION (TOP VIEW) go S8P NGS OS Gs OS OE OF VppQil 230 Vez OE OE cE aed2 ar ali ore eIRCULT OUTPUT BUFFERS args 26) Al3 ass 25p) as 400 4 asds za ao ae couumy commun 7/0 ass 235 al. Bol 2 DECODER CIRCUIT asQ7 220 OE ASO & sada zip aio ase ee: 2p cE xo 2 now MEMORY CELL oon 28p 08 Ase 8 DECODER apebea otdie vB os moot 3 32,768x0ite o2 Gis 16H 04 s1Z0 R130 owpdae asf os ase PIN NAMES _, MODE SELECTION j00~ 07 [Outputs (Inputs) MODE (20) }(22)] (1)_ |(28)(4213, 15 v19 GE lohip Enatie Input — Read 2 weet dE [output Enable Input Output Deselect| * | # | 5v | High Impedance | “““*¥* Ypp [Program Supply Standby HT | High Impedance Voltage [Program [u [a] Data In | sec [Pewee Supply Voltage||Program Inhibit] H | H | 6v | High Impedance | Active 50) Program Verify [aid [eround Tor D ~817—

TOSHIBA TECHNICAL DATA TC57256AD-15,1C57256AD-20 MAXIMUM. RATINGS ITEM RATING Vcc Power Supply Voltage -0.6% 7.0 Vv Vp Progran Supply Voltage =0.6414.0 VIN Input Voltage “20.64 7.0 a Vr/o Input /Output Voltage =0.60 Vcc+0.5 v TSOLDER Soldering Temperature Time "260 « 10 °C+ sec TsTRG Storage Temperature 654 wm °c ToPR Operating Temperature 40085 °c READ OPERATION D.C. RECOMMENDED OPERATING CONDITIONS Input High Voltage [| 2.2 | - Voc+0. 3 VIL Input Low Voltage -0.3 - 0.8 * Vcc Power Supply Voltage 4.75 5.00 | 5.25 v Vpp Power Supply Voltage vec-0.6 | Voc | Voct0.6 D.C. and OPERATING CHARACTERISTICS (Ta=-40% 85°C, Vcc=5V! 5%) J tE-ov [e~6.7emie] - [| - | 30 eo] | Von [output High Voltage Tou=-400uA 2.4 = Tpp1 [Vcc Current Vpp=Vcc + 0.6V - +10 je Leakage Current - ff -818—

OSHIBA TC57256AD~-15,1C57256AD-20 TECHNICAL DATA A.C. CHARACTERISTICS (Ta=~40~ 85°C, Voc=5V#5%, Vpp=V¢c#0.6V) TC57256AD-15 | TC57256AD-20 SYMBOL PARAMETER | TEST ce IN tacc | Address Access Time | GE-OE-vr, | - (| 150 [| = | 200 tce _| CE to Output valid = uso | - | 200 CoE OE to Output Valid - 70 - 70 "FL CE to Output in High-z | OE=Vvy, 0 60 0 60 tpr2 | OE to Output in High-Z | CE=Vzz, 0 60 0 60 tou Output Data Hold Time | CE-OE=Vy_, o [- [oo 7] - A.C. TEST CONDITIONS * Output Load : 1 TTL Gate and Cy=100pF + Input Pulse Rise and Fall Times : 10ns Max. + Input Pulse Levels 1 0.45V% 2.40 + Timing Measurement Reference Level: Inputs 0.8V and 2.2V, Outputs 0.8V and 2.0V CAPACITANCE *(Ta=25°C, f=LMHz) Cin Input Capacitance Viy=0Vv [ - | 4 6 Output Capacitance Voursov | - | 8 12 * This parameter is periodically sampled and is not 100% tested. TIMING WAVEFORMS (READ) norma XK | tow tog N ‘op } ~819-

OSHIBA . TC57256AD~15,1C57256AD~20 TECHNICAL DATA TIMING WAVEFORMS (PROGRAM) (Voc=6V#0.25V, Vpp=12.5V#0.5V) oa AO~14 > sas fy a FF a Brsrarataatatatatatetatetat t PIII \\ cwecerececevecicocerececiicerecectceal a | \\ 22m) seas 1 RISES [rons | | ons toe ft rp +t on i | | | tps pe | * t Note 1. Vg¢ must be applied simultaneously or before Vpp and cut off simultaneously cr after Vp. 2. Removing the device from socket and setting the device in socket with Vpp=12.5V may cause permanent: damage to the device. 3. The Vp supply voltage is permitted up to 14V fcr program operation. So the voltage over 14V should not be applied tc the Vpp terminal. When the switching pulse voltage is applied to the Vpp terminal, the overshoot voltage of its pulse should not be exceeded 14V. —821—

TOSHIBA TC57256AD-15,1C57256AD-20 TECHNICAL DATA ERASURE CHARACTERISTICS The TC57256AD's erasure is achieved by applying shortwave ultraviolet light which has a wavelength of 25374 (Aagstroms) to the chip through the transparent window. Then intergrated does (uitraviclet light intensity [w/cm*] x exposure time [sec.]) for erasure should be a minimum of 15 [w+ sec/cm*], When the Toshiba sterilizing lamp GL-15 is used and the device is exposed at a distance of lcm from the lamp surface, the erasure will be achieved within 60 minutes. And using commercial lamps whose ultraviolet light intensity is a 12000 [uw/cm?} will reduce the exposure time to about 20 minutes. (In this case, the integrated does is 12000 [uw/cem?] x (20x 60) [sec] #15 [w+ sec/cm?].) The TC57256AD's erasure begins to occur when exposed to light with wavelength shorter than 4000A. The sunlight and the flourescent lamps will include 3000~ 40008 wavelength components. Therefore when used under such lighting for extended periods of time, the opaque seals-Toshiba EPROM Protect Seal AC901-are avcilable. OPERATION INFORMATION The TC57256AD's six operation modes are listed in the following table. Mode selection can be achieved by applying TTL level signal to all inputs. PIN NAMES (NUMBER)| CE | OE | vpp | vcc 09 “07 power Read L Data Oct . Read Operation [Oo pesele a] sv | sv biigh tepeaance ] “tS (taz-4on asec) POUEPUL Deselect __ # face musdence Standby x High Impedance | Standby Prograin | Data In Program Operation arerereres . or ee . Program Inhibit 12.5V | 6V | High Impedance Active (Ta=25 + 5°C) Beem Zonet [a |e | High Impedance Program Verify | * | 1 | Data Out Note: H; Viy, Ls Vip. *} Vrq or Vy, READ MODE The TC57256AD has two control functions. The chip enable (CE) controls the operation power and should be used for device selection. The output enable (OE) control the output buffers, independent of device selection. Assuming that CE=0E=Vy,, the output data is valid at the outputs after address access time from stabilizing of all addresses. The CE to output valid (cg) is equal to the address access time (tacc). Assuming that CE=Vr_ and all addresses are valid, the output data is valid at the outputs after tog from the falling edge of OE. OUTPUT DESELECT MODE Assuming that CE=Vy7q or OF=Vzq, the outputs will be in a high impedance state. So two or more TC57256AD's can be connected together on a common bus line. When CE is decoded for device selection, all deselected devices are in low power standby mode. —822—

OSHIBA TC57256AD~15,1C57256AD~20 TECHNICAL DATA ee STANDBY MODE The TC57256AD has a low power standby mode controlled by the CE signal. By applying a high level to the CE input, the TC57256AD is placed in the standby mode which reduce the operating current to 100uA by applying MOS-high level (Vcc) and then the outputs are in a high impedance state, independent of the OE inputs. PROGRAM MODE Initially, when received by customers, all bits of the TC57256AD are in the "1" state which is erased state. Therefore the program operation is to introduce "0's" data into the desired bit locations by electrically programming. The TC57256AD is in the programming mode when the Vpp input is at 12.5V and CE is at TTL-Low under OE=Vzq. The TC57256AD can be programmed any location at any time either individually, sequentially, or at random. PROGRAM VERIFY MODE The verify mode is to check =hat desired data is correctly programmed on the programmed bits. The verify is accomplished with OE at Vy,. PROGRAM INHIBIT MODE Under the condition that the program voltage (+12.5V) is applied to Vpp terminal, a high level CE input inhisits the TC57256AD from being programmed. Programming of two or more TC57256AD's in parallel with different data is easily accomplished, That is, all inputs except for CE and OE may be commonly connected, and a TTL low level program pulse is applied to the CE of the desired device only and TTL high level signal is applied to the other devices. HIGH SPEED PROGRAMMING MODE The program time can be greatly decreased by using this high speed programming mode. The device is set up in the high speed programming mode when the program- ming voltage (+12.5V) is app-ied to the Vpp terminal with Vcg=6V. The programming is achieved by applying a single TTL low level Ims pulse to the CE input after addresses and data are stable. Then the programmed data is verified by using Program Verify Mode If the programmed data is not correct, another program pulse of lms is applied and then the programmed data is verified. This should be repeated until the program operates correctly (max. 25 times) After correctly programming the selected address, the additional program pulse with width of 3 times more than that needed for initial programming is applied. When programming has been completed, the data in all addresses should be verified with Vcc=Vpp=5v. —823—

TOSHIBA TC57256AD-15 ,TC57256AD—-20 TECHNICAL DATA HIGH SPEED PROGRAM MODE FLOW CHART : ADDRESS Sita > yes ~ a | ADDRESS = OVERPROORAM SX PULSES OF Imeec NELT ADDRESS OR ONB PULSE OF 3X meee DURATION fast x0, Yoo= 809 Vp = 800 Rend PAIL or —824—

JISHIBA TC57256AD~15,1C57256AD-20 TECHNICAL DATA eee : ELECTRIC SIGNATURE MODE Electire signature mode allows to read out a code from TC37256AD which identifies its manufacturer and device type. The programming equipment may reads out manufacturer code and device code from TC57256AD by using this mode before program operation and automatically set program voltage (Vpp) and algorithm. Electric Signature mode is set up when 12V is applied to address line A9 and the rest of address lines is set to Vi1, in read operation. Data output in this conditions is manufacturer code. Device code is identified when address AO is set to Viq- These two codes possess an odd parity with the parity bit of MSB (07). The following table shows electire signature of TCS7256AD. PINS AO o7 06 05 04 03 02 ol 00 HEX. SIGNATURE Go) [a9 fas) | ar | ae |asy fas) faz) |e | vara Notes: A9=12V+0.5v ALVAB, A1OVA14, TE, OE=Vyy 825 -

TOSHIBA TC57256AD-15,1C57256AD-20 TECHNICAL DATA ne a OUTLINE DRAWINGS Unit in m svruar. a. ore. ze zs a5 a fs oe at of ao 20 07 16 18 —-. -3 nose Dy 2 Tes¢¢s 6768 59 101 2 i le ci 3 1524403 { +018 \\ "025-010 3 254025 1354025 a —— 1 74nAX. ° reeest) note 2 wore a Note 1. Each lead pitch is 2.54mm. All leads are located within 0.25mm of their true longitudinal position with respect No.1 and No.28. 2. This value is measured at the end of leads. 3. All dimensions are in millimeters. —826—

Product Information

TC57256AD-15 specifications and overview.

Summary

32,768 WORD X 8 BIT CMOS UV ERASABLE AND PROGRAMMABEL READ ONLY ELECTRICALLY

Description

32,768 WORD X 8 BIT CMOS UV ERASABLE AND PROGRAMMABEL READ ONLY ELECTRICALLY

Source title TC57256AD-15 Datasheet(PDF) - Toshiba Semiconductor

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