TC571000D TOSHIBA | Alldatasheet
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Technical content
70571001D-15, -20, -200, -25
DESCRIPTION
The TC571000D/TC571001D is a 131,072 word*8 bit CMOS ultraviolet light erasable end electrically programmable read only memory. The TC571000D is JEDEC standard pin configuration and the TC571001D is compatible with 28 pin 1M bit Mask ROM. Both products are packed in 32 pin standard cerdip package. TC571000D/TC571001D is fabricated with the CMOS technology. Advanced circuit tech- niques provide both high speed and low power features with a maximum operating current of 30mA/6.7MHz and access time of 15(ns/200ns/250ns. The programming times of the TC571000D/TC571001D except overhead times of EPROM pro- grammer is only 14 seconds by using the high speed programming algorithm. FEATURES. + Peripheral circuit: CMOS + Single 5V power supply Meniory cell : N-MOS * Full static operation + Access Time * Righ speed programming operation: tpy 0.1ms [__[-15 J -20 J -25 | -200 + Input and output TIL compatible 5Vz10% = + SEDEt : [teup Jow70C] 00s 85°C 0~ 70°C C standard 32 pin: TC571000D [ace | 1505s|200es]250ns | 2000s] * 14 MOM compatible + 105720010 + Low power dissipation * Standard 32 pin DIP cerdip package Active : 30mA/6.7NEZ Standby: 100yA(Ta=85°C) PIN CONNECTION] (TOP VIEW) (Reference) ver di azhvec = wep dn azpyec ars qi 2h vec" [ a0~ ai6|address Inputs are g2 31) PON OEd2 apr = ‘A122 2mpale Al5g3 30PNc Als g3 sopNC ATQ3. 26Nal3 DO~D7 |Outputs (Inputs) Al2q4 Bpas Al2q4 oop als AGg4 25pas ; aids wpaig. ads «= zapara. «= ASS za bag | cE [chip Enable input A6T6 27p as Abg6 27p as A4geé 23pall ‘Out 1c Enabli AS? 26Pag AS q7 26p ag Agg7 22pale oF taput meee asds 23P all a4 gs 25Pau a2gs 2paio - Ass 24 0E a3g9 24P aie alge 20p TE Program Control a2qio «= aparo = 210 asbano aoqio — 19hD7 Input aogi2 = 21pp7 Aogi2 2pp7 piti2izpps cc |Vcc Supply Voltage pegs mopos po g13 op Dé p2q13) ise ¥ Program Supply pid ispps pidis 9b ps axpqi4 —ispp3 PP | voltage p2qis isp D4 pois 8p De ¢571000D 1¢571001D Te531000P |_ Nc [Fe connection —H97 —
Vep GND Voc 00 01 02 03 04 05 06 07 TEo OE, CE.PON Es Ne 7 COLUNN COLUMN LO A2o0 DECODER C1RCUIT Bo Mo AGO = sed s Ago = Row MEMORY CELL
9 ARRAY
aio ° 2 DECODER 131,07 2x 8bits alloy 3 Ai2 0 s A130 alge A150 A160 NODE _SELECTION| el Ed a Active [output Deserece | * | * | # | sv [High Impedance [Program | [ct | | progran tonbir E* 1 tt oy | ocasv nett : : ctive pat. | « | oman Westy De pt pt *: Hor L MAXIMUM RATINGS] [seeo. | ee a Voc Power Supply Voltage 70.6% 7.0 Program Supply Voltage 0.6% 14.0 Input/Output Voltage 0.6% VoctO.5 [7 [Pover bissipacion ‘| +s | ® | Soldering Temperature Time 260+ 10 [*c- sec | — 1-98 —
T6571000D-15, -20, -200, -25 1C5710010D-15, -20, -200, -25 READ OPERATION D.C. RECOMMENDED OPERATING CONDITIONS owt ["ie [input High Voleage [22 | = |vect0.3] 2.2 | = |vecw.3 | [Wr [tnpue Lov Voltage | 0.9 | - | 0.8 | -0.3 [- | 08 |, Ver VPP Power Supply Voltage D.C. AND OPERATING CHARACTERISTICS (ta=-40% 85°C) TEST CONDITION | MEN. | 7¥P. | MAK. | UNIT [tur [input current | Ymrovveo | = | = [aio [va | Tecou CEeOv femme | - | - | 30_| = Tovroma _[feuge [= [30 a Standby Current a [You | Output High Voltage Tppi__[VeP currene _———~dippeVocs0-8V Si «dT * 0 | va | Output Leakage Current | VouT=0.4V~ Vcc [- | - | 10 | wa | Ta=0~% 70°C for TC571000D/TC571001D-15, ~200 A.C. CHARACTERSITICS (Ta=-40~ 85°C, VPP=VCcz0.6V) SYMBOL PARAMETER 28 -20,-200 -38 UNIT] AE lkace [Address Access Time [= [aso | - | 200 | - | 250 | [For [OE co ouepuc vasa «| ~- | 70 | - | 70 | - | 100 | [Fon | FOH co Output Valid [= [7% [= [70 | = | 300 _| TE to Output in wighz | 0 | 60 | 0 | 60 | 0 | 90 | OE co Output in High-z o | | o | o {| o | 9% | [Fors | POH to Output in Bigh-z | 0 | 60 | 0 | 60 | o | 90 | [For | Output Data Hold Tine {0 | - | 0 | - | © 1- | Ta=0~ 70°C for TC571000D/TC571001D=15 , -200 A.C. TEST CONDITIONS + Output Load 1 1 TYL Gate and CL=100pF + Input Pulse Rise and Fall Time : 1Ons Max. + Input Pulse Levels + 0.45V 50 2.4V + Timing Measurement Reference Level: Inputs 0.8V and 2.2V Outputs 0.8V and 2.0V —H-99—
70571001D-15, -20, -200, -25 v, toe Lf, ad oo UUM, ” ATT: = YY \\ Wil.
D.C. RECOMMENDED OPERATING CONDITIONS [sna | _——sPammwerer SSN P| OT a [vx _[anput tow voltage SSS fd ie| [voc | Yee Fover Supply Voieege + @.00 | 6.25 | 50] ° [sno [| _rawveren [rast cowormzon [umn | ov. [vax. | omer ] [tur | Fapot current [¥yyr0~¥gq | - | - [10 | oa [You [oveput nigh voieaye _[Towr-t00sa__[2.< [- | - |v _| [ou | osepue tow Vonage [fous?-tea | - | - [ea pv _| [cc [Wee suppiy current [| = |= |= | 20 [m= | [tee2 [Ver Suppiy Current _|Wereisov | - | - | 30 | = | [im [#9 Auto Select veivage | - pus [wo fs |v _| [snao. | Farmeren [res comprrion [ wan. [ ove, [vax [uNi? ] [eas [aaivens setup time | - | 2 |- |- |» | [an [address soue time [= | 2 [= |=] «| [ces [er serup rie |S dT PT - Ce [eas [bata Seip tise +f dt P= |= | [pq [tata Beid Fine | dT P= = [evs _[Wr setup tine | dP P= [Pe [ers [Frogren Pulse wan | = ———*ieso9s fot [ots | as | [for [OE co ourpue vaine | = | - | - | 10 | | [ori [Ge co tuepur sa mish | oe | - | - | 9] | A.C. TEST CONDITIONS * Output Load : 1 TTL Gate and C,(100pF) + Input Pulse Rise and Fall Time : 10ns Max. + Input Pulse Levels : 0.45V and 2.4V + Timing Measurement Reference Level: Input 0.8V and 2.2V, Output 0.8V and 2.0V —H-101 —
1C571000D-15, -20, -200, -25 HIGH SPEED PROGRAM OPERATION TIMING CHART toes ‘cen vE tog | tore wet oop —{ sami pr tos leo od a °° YL Note: 1. Vc must be applied simultaneously or before Vpp and cut off simul- taneously or after Vpp. 2, Removing the device from socket and setting the device in socket with Vpp#i2.75V may cause permanent damage to the device. 3. The Vpp supply voltage is permitted up to 14V for program operation, s0 the voltage over 14V should not be applied to the Vpp terminal. When the switching pulse voltage is applied to the Vpp terminal, the overshoot voltage of its pulse should not be exceeded 14V. —H-102 —
t + te (@ ERASURE CHARACTERISTICS The TC571000D/TC571001D's erasure is achieved by applying shortwave ultraviolet light which has a wavelength of 2537A (Angstroms) to the chip through the trans- parent window, Then integrated dose (Ultraviolet light intensity [W/cm?] x exposure time [sec.]) for erasure should be a minimum of 15 [W-+ sec/cm?]. When the Toshiba sterilizing lamp GL-15 is used and the device is exposed at a dis- tance of lem from the lamp surface, the erasure will be achieved within 60 minutes. And using commercial lamps whose ultraviolet light intensity is a 12000 [uW/cm?] will reduce the exposure time to about 20 minutes. (In this case, the integrated dose is 12000 [uW/em?] x (10« 60) [sec] #15 [W+ sec/cm*].) The TCS71000D/1C571001D's erasure begins to occur when exposed to light with wavelength shorter then 4000A. The sunlight and the flourescent lamps will include 3000 4000K wavelength components. Therefore when used under such lighting for extended periods of time, the opeque seals - Toshiba EPROM Protect Seal AC901 ~ are available. OPERATION INFORMATION The 1C571000D/TC571001D's six operation modes are listed in the following table. Mode selection can be achieved by applying TTL level signal to all inputs. READ pee Te [eft [pata cue | Acti oven Say Program Inhibit 12.75v| 6.25vl— Active Note: 8; Vay, Ls Voz. *3 Voy or Vay — H-103 —
1C5710000-15, -20, -200, -25 1C571001D-15, -20, -200, -25 The TC571000D/TC571001D has three control functions. The chip enable (CE) controls the operation power and should be used for device selection. The output enable (OE) and the program control (PCN) control the output buffers. independent of device selection. Assuming in that CE-OE=Vrr and PCH*VrH, the output data is valid at the output after address access time from stabilizing of all addresses. The CE to output valid (tog) is equal to the address access time (tacc). Assuming that CE=Vy,, PGM=Vzy and all addresses are valid, the output data is valid at the outputs after tog from the falling edge of OE. And assuming that CE=OE*Vz; and all addresses are valid, the output data is valid at the outputs after tpgy from the rising edge of PGM. ‘DUTPUT-DESELECT RODE] Assuming that CE=Vzq or OE=Vyq, the outputs will be in a high impedance state. So two ormore ROMs can be connected together on a common bus line. When CE is decoded for device selection, all deselected devices are in low power standby mode. The TC571000D/TC571001D has a low power standby mode controlled by the CE signal. By applying a high level to the CE input, the TC571000D/TC571001D is placed in the standby mode which reduce the operating current to 100uA by applying MOS-high level (Vcc) and then the outputs are in a high impedance state, independent of the OE inputs. Initially, when received by customers, all bits of the 1C571000D/TC571001D are in the "1" state which is erased state. Therefore the program operation is to introduce "0's" data into the desired bit locations by electrically programming. The levels required for all inputs are TTL. The TC571000D/TC571001D can be programmed any location at anytime —— either individually, sequentially, or at random. — H-104 —
[PROGRAM VERIFY MODE] The verify mode is to check that the desired data is correctly programmed on the programmed bits. The verify is accomplished with OE and CE at Vz, and POM at Vzy. Under the condition that the program voltage (+12.75V) is applied to Vpp terminal, a high level CE or PGH input inhibits the 1C571000D/TC571001D from being programmed. Programming of two or more EPROMs in parallel with different data is easily ac- complished. That is, all inputs except for CE or PCM may be commonly connected, and a TTL low level program pulse is applied to the CE and POM of the desired device only and TTL high level signal is applied to the other devices. The device is set up in the high speed programming mode when the programming voltage (#12.75V) is applied to the Vpp terminal with Voc=6.25V and PGM=Vzy. The programming is achieved by applying a single TTL low level 0.1ms pulse the PG input after addresses and data are stable. Then the programmed data is verified by using Program Verify Mode. If the programmed data is not correct, another program pulse of 0.lms is applied and then programmed data is verified. This should be repeated until the program operates correctly (max. 25 times). When programming has been completed, the data in all addresses should be verified with Voc=Vpp=5v. —H-105 —
1C571000D-15, -20, -200, -25 HIGH SPEED PROGRAM OPERATION FLOW CHART Vor = 6.25+0.25V Vpp = 1.2.7540.25V ADDRESS = START ADDRESS Lx-0 | <at> YES ADDRESS ‘= NEXT ADDRESS ADDRESS 7? Voc = 5 Vpp = 5Y <te> ALL BYTES OK Gary) — H-106 —
1C571000D-15, -20, -200, -25 ELECTRIC SIGHATURE MODE] Electric signature mode allows to read out a code from TC571000D/TC571001D which identifies ic's manufacturer and device type. ‘The programming equipment may read out manufacturer code and device code from TC571000D/TC571001D by using this mode before program operation and automatically set program voltage (Vpp) and algorithm. Electric Signature mode is set up when 12V is applied to address line A9 and the rest of address lines is set to Vz, in read operation. Data output in this con- ditions is manufacturer code. Device code is identified when address AO is set to Vrq- These two codes possess an odd parity with the parity bit of MSB (07). The following table shows electric signature of TC571000D/1C571001D. i HEX. romans ———P" [so [or | o» [os To [o> [on [or | mo [5B wanofacturs one [EP 2 oto tr t2 [ole le | se] i ¢571000D y 2 | nevice code [2 fo fe fefo fata To 7 6] Pepepe pepe pe pe por Notes: A9=12V+0.5V Al~vas, Al0~vAl6, CE, OB=VrL PGN=ViIn —H-107 —
TC571000D-15, -20, -200, -25 1C571001D-15, -20, -200, -25 OUTLINE DRAWINGS} Unit in m “| END R100 3 3 3 R064 MARK } Z| = al 3 ToS Se i 889=01 nL 420>05 7 ; 3 3 Lp13t02 5 al EE rl ree 2.54401 0.46+0.05 3 3 q
4 MAX *
Note 1. Each lead pitch is 2.54mm. All leads are located within 0.25mm of their true longitudinal position with respect No.1 and No.32 leads. 2. This value is measured at the end of leads. 3. All dimensions are in millimeters. — H-108 —