TC54 TELCOM | Alldatasheet

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Technical content

4-279TELCOM SEMICONDUCTOR, INC. TC54

FEATURES

Custom ± 1.0%

APPLICATIONS

n Battery Voltage Monitoring n Microprocessor Reset n System Brownout Protection n Switching Circuit in Battery Backup n Level Discriminator GENERAL DESCRIPTION The TC54 Series are CMOS voltage detectors, suited especially for battery-powered applications because of their extremely low 1µA operating current and small surface- mount packaging. Each part is laser trimmed to the desired threshold voltage which can be specified from 2.1V to 6.0V, in 0.1V steps. The device includes a comparator, low-current high- precision reference, laser-trimmed divider, hysteresis circuit and output driver. The TC54 is available with either an open- drain or complementary output stage. In operation, the TC54's output (V OUT ) remains in the logic HIGH state as long as VIN is greater than the specified threshold voltage (V–DET ). When VIN falls below V–DET , the output is driven to a logic LOW. VOUT remains LOW until VIN rises above V–DET by an amount VHYST , whereupon it resets to a logic HIGH. FUNCTIONAL BLOCK DIAGRAM VOLTAGE DETECTOR Output form: N = Nch Open Drain C = CMOS Output Detected Voltage: Ex: 21 = 2.1V; 60 = 6.0V Extra Feature Code: Fixed: 0 Tolerance: 1 = ± 1.0% (custom) 2 = ± 2.0% (standard) Temperature: E: – 40°C to + 85°C Package Type and Pin Count: CB: SOT-23A-3*, MB: SOT-89-3, ZB: TO-92-3 Taping Direction: Standard Taping Reverse Taping No suffix: TO-92 Bulk *SOT-23A-3 is equivalent to EIAJ (SC-59).

ORDERING INFORMATION

PART CODE TC54 V X XX X X X XX XXX TC54-10 11/8/96 VOUT TC54VC only VSS VIN VREF TC54VN has open-drain output. TC54VC has complementary output. PIN CONFIGURATIONS 13 2 VIN VIN VSS VIN VSS VOUT VSS VOUT VOUT TC54 TC54 TC54 *SOT-23A-3 SOT-89-3 TO-92 *SOT-23A-3 is equivalent to EIAJ (SC-59)

4-280 TELCOM SEMICONDUCTOR, INC. TC54 VOLTAGE DETECTOR ELECTRICAL CHARACTERISTICS: TA = 25°C, unless otherwise specified. Symbol Parameter Test Conditions Min Typ Max Unit VIN Operating Voltage V –DET = 2.1 to 6.0V 1.5 10.0 V ISS Quiescent Current V IN = 2.1V 1.0 3.0 3.0V 1.3 3.4 µA 4.0V 1.6 3.8 5.0V 2.0 4.2 V–DET Threshold Voltage (V –DET )( V –DET )V x 0.98 x 1.02 VHYST Hysteresis Range (V –DET )( V –DET )( V –DET )V x 0.02 x 0.05 x 0.08 IOUT Output Current Nch V DS = 0.5 V IN = 2.1V 7.7 mA 3.0V 10.1 4.0V 11.5 5.0V 13.0 Pch VDS = 2.1V V IN = 8.0V – 10.0 TC (V–DET ) Tempco of (V –DET ) – 40 °C ≤ TA ≤ 85°C ± 100 ppm/°C ABSOLUTE MAXIMUM RATINGS* Power Dissipation: (T A ≤ 70°C) * Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to Absolute Maximum Rating Conditions for extended periods may affect device reliability. Pin No. Symbol Description 1V IN Analog input. This pin is both the power supply input and the voltage to be monitored. 2V OUT Digital output. This output goes low when VIN drops below V–DET and returns high when VIN rises above V–DET + VHYST . (See timing chart). 3V SS Ground terminal. PIN DESCRIPTION

4-281TELCOM SEMICONDUCTOR, INC. TC54 VOLTAGE DETECTOR TIMING CHART MARKING VIN DETECT VOLTAGE V DET MINIMUM OPERATING VOLTAGE VHYST VDET OUTPUT VOLTAGE RELEASE VOLTAGE RESET VOLTAGEOR GROUND LEVEL GROUND LEVEL a = output (Nch or CMOS) plus first voltage digit 23456 Nch M N P R S CMOS C D E F H ex: CMOS 3.x = uuuu b = first voltage decimal (0-9) ex: CMOS 3.4 = uuuu c & d = assembly lot number D a, b & c = 54_ (fixed) d = output (C = CMOS, N = Nch) e = first voltage digit (2-6) f = first voltage decimal (0-9) g = extra feature code : fixed : 0 h = detecting accuracy 1 = ± 1.0% (custom), 2 = ± 2.0% (standard) i, j, k & l = assembly lot number SOT-89-3SOT-23A-3 TO-92 DESCRIPTION OF OPERATION Refer to the Timing Chart below. In normal steady-state operation, when VIN > V–DET , the output will be at a logic high. In the case of the TC54V, this is an open-drain condition. If and when the input falls below V –DET , the output will pull down (Logic 0) to VSS . Generally, VOUT can pull down to within 0.5V of VSS at rated output current and input voltage. (See the Electrical Characteristics section). The output, VOUT , will stay valid until the input voltage falls below the Minimum Operating Voltage, VIN(MIN), of 1.5V. Below this minimum operating voltage, the output is undefined. During power-up or anytime V IN has fallen below VIN (MIN), VOUT will remain undefined until VIN rises above VIN(MIN), at which time the output will become valid. VOUT will be in its active low state while VIN(MIN) < VIN < V+DET . (V+DET = V–DET + VHYST ). If and when the input rises above V+DET , the output will assume its inactive state. (High for TC54VC, open-drain for TC54VN). Refer to TelCom Semiconductor Application Note #2, Using the TC54 Voltage Detector.