TC528128B TOSHIBA | Alldatasheet
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Technical content
SILICON GATE CMOS target spec 131,072WORDSx8BITS MULTIPORT DRAM
DESCRIPTION
‘The TC528128B isa CMOS multiport memory equipped with a 131,072-words by 8-bits dynamic random access memory (RAM) port and a 256-words by 8-bits static serial access memory (SAM) port. The TC528128B supports three types of operations; Random access to and from the RAM port, high speed serial access to and from the SAM port and bidirectional transfer of data between any selected row in the RAM port and the SAM port. The RAM port and the SAM port can be accessed independently except when data is being transferred between them internally. In addition to the conventional multiport videoram operating modes, the TC528128B features the block write and flash write functions on the RAM port and a split register data transfer capability on the SAM port. The TC528 128B is fabricated using Toshiba's CMOS silicon gate process as well as advanced circuit designs to provide low power dissipation and wide operating margins. FEATURES KEY PARAMETERS + Single power supply of SV£10% with a built-in ITEM 15281288 + All inputs and outputs : TTL Compatible mac RAS Access Time ; © Organization (Max.) }00ns RAM Port: 131,072 wordsX8bits as SAM Port: 256 wordsX8bits a Access Time ax. + RAM Port Fast Page Mode Read - Modify - Write baa Column Address Access | 451° | sone CAS before RAS Refresh, Hidden Refresh Time (Max.) RAS only Refresh, Write per Bit Cycle Time (Min.) 150s Flash Write, Block Write 512 refresh cycles / 8ms rage Move Cycle Time + SAM Port SoarAcw High Speed Serial Read / Write Capability 256 Nal Access Time Tap Locations Max.) Fuily Static Register Serial Cycle Time (Min.) + RAM- SAM Bidirectional Transfer Tec) | RAM Operating Current Read / Write / Pseudo Write Transfer (SAM : Standby) 90mA | 75mA Real Time Read Transfer 5 , 224 | SAM Operating Current ; . CC2A Split Read / Write Transfer (RAM: Standby) S0mA | S0mA. + Package "TC5281288) ; $0140-P-400 Standby Current TC528128BZ : Z1P40-P-475 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 6-113
a PIN CONNECTION (TOP VIEW) TC5281288) s¢ 110 40) Vss1 sio1 G2 39f) sio8 si02 G3 38{) s!iO7 sio3 Q« 37) si06 si04 Qs 36) siOS DT/OE Gs 35) SE wi/io1 7 3a w8/108 w2/102 Cs 330 W7/107 w3/103 Gs 32) W6/106 w4/104 J 10 31) W5/105 Veer Qn 30) Vss2 We/WE Giz 29 OSF NC 13 28) NC RAS Uis 27) TS NC Q1s 26) QSF A8 C16 2s) AO AG 17 2a At AS Qi8 23) A2 Aa Tio 2p a3 Vec2 420 21 A7 C114 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
ornare BE. rie a — |] CONTROL ee FLASH (8bit) pane [em | “ve fo = ! ——— i bs = — = = =sh= — rs)" 4 [= =sh= 8/5 512x256x8 Sie ie =aa= 3 |S fase] ceut Ae =an= as oo | = ca == TET oe L | sthatsoe’ Ke S| veo {FP TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-115,
Livan [eoroweswes [ere i a a a a a a RECOMMENDED D.C. OPERATING CONDITIONS (Ta = 0~70°C) i CAPACITANCE (Vcc=5V, f=1MHz, Ta=25°C) i a a Note: This parameter is periodically sampled and is not 100% tested. C-116 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
D.C. ELECTRICAL CHARACTERISTICS (Vcc = 5V + 10%, Ta = 0~70°C) sf waresmsy mf [=| [fa RAS, CAS Cycling) rs Pe [ow [Po |= | oR Sa mor fee fo fef=fe} [| (RAS, CAS = Vy) [am Pow f= T= =] marae fae fw [=] [=] | RAS Cycling, CAS = Vy (wee) [Peon [= =P] co a od oe RAS = Vy... CAS Cycling’ rca [am [ewe [= P| mA comromcenmamna [mm [so [= [= [=| RAS Cycling, CAS Before RAS os Fi [oe [= fm |= DATA TRANSFER CURRENT standby | tcc [=| me f- fs | | RAS, CAS Cycling! rie io [=P] ed RAS, CAS Cycling (Rew) [ae Po [=P [=P] De] nopeapeger fam [we |) [fe RAS, CAS Cycling) es p= Pe fel T | = onee [oan [me | oe | nor INPUT LEAKAGE CURRENT 1 10 OVSVjyS6.5V, All other pins not under test=0V uty OUTPUT LEAKAGE CURRENT OVSVour £5.5V, OutputDisable low nA [OUTPUT “H" LEVEL VOLTAGE v , v prperea fm fet OUTPUT “L” LEVEL VOLTAGE pTeaeww [eft TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C117
ELECTRICAL CHARACTERISTICS AND RECOMMENDED A.C. OPERATING CONDITIONS (Vcc = 5V + 10%, Ta = 0~70°C)(Notes: 5, 6, 7) frvwen| rsvp | fac [Rent Reatorwre poe ine [sof wolf (SN CS fre [Fat PageMoieGee Tine Ot SE] a a ed Time fese [Ase Tine ew RAS eo) tax [Access Time from Column Address | [4s] 50 teac Access Time from CAS a ee | fom _[AscewTine romaine |__| lore [OwaButerTun-omDely | tao of mm] | fae [RAS Pcs tine mt] fess [RASPonewam || To) 00] owe) [| fe [RAS Pe wat i Rage MORO) | 0 000] To Tapoo] | ass [RAS HoTIne st fesw [CAS HoTIne mt a a ee fas, (Coton Asso RAStaTne fas] [mt] cre CAS to RAS Precharge Time a ee [| fcr CRS Pcs Tine aaeeMaiy [vol | of | [| fase [Rowadtessertpime TOT] fasw [RowAden voting |] C| fase [Come Atuessecuptine Oo pean [Cotwnatiennarins st |_| fix [Conn Ada Hainer RAS] 5[— [| [1 xcs [ReadConmandseurtine | tT tT fac [ReotCommantotine tf] Jteen [Read Command Hold Time refezencedioRAS | 0] |] ju | Write Command Hold Time a ee (| sce [Wee Command Haine towne RAS] 55] [7m] | wr [Wee Conmandranewan st] SS fom [Nate CommantneaStaatine fot sf] C-118 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
fos [pam saptine ot fox [aime ss fom aa Reine emearoRAS [fm] fives Wee Cond SecUp eof ot few —_[RAS@ WEDS Tie [oJ Faw [Cote Ass WEDD Tine [|| few [CRS WEDeS Fm || faze [Danio Heo fama [Puat@OEDeRs Time af fol m cen [Asn Tinstew Ef |e sce ——[Owpa Bue Tuna aky ew GE [0 To] — of 20 foc [OE wDemDeayTime | fear JOE CommaromTne ol fal] nox [RAS Haine teensdwOE [5] ese [ERSSecp Fine oreAT Bee ARG ol | vol] [J fem [CAS Haine oc CABcoe RASCH [||| || fe [RAS Petane wTATAGHeTine of || a ese [WB SeOp TR few [BHT ss se [PSFSeUpTnetemetwRAS [ofa] fe [DSF HotTine wewseto RASC [|| sp) fm [PSFHteTinetomssioRAS@——[ss[ [| || isc [PSF Se UpTinertewnesiotAS [of [af] |] fem [DSF Ho TinereweweAS [slat fue [Wee FecBiNikDaaseOpTine | of [of] | | fsa [Wie ecb DaaHaWTne [sf | st] a Fee [BP Rik HsTine Ea I [ [eatiaenaatmacs | SL MT (Real Time Read Transfer) [frites teatmeseartasen | | || L| Address (Real Time Read Transfer) [™ [rattnckactanes | LT | (Real Time Read Transfer) TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C119
SYMBOL PARAMETER {0 Tat Nore [IBC [WAT WAX far [DT RAS Presta Tine a RAS to First SC Delay Time (Read Transfer) [80] [100] | [| tasD ‘Column Address to First SC Delay Time 45 30) (Read Transfer) tree Last SC to DT Lead Time 3 5 (Real Time Read Transfer) lises | Last SC to RAS Set-Up Time (Serial Input) | 3 | 30 | | Jiro __ [RAS to First SC Delay Time (Serial Inpu) [25] | 25] [| soz. Serial Output Buffer Tumn-off Delay fromRAS | 10] 50) 50) (Pseudo Write Transfer) tswis Serial Write Disable Set-Up Time [| of UT tgwitt Serial Write Disable Hold Time a a C120 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
NOTES: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. 2. All voltage are referenced to Vss. 3. These parameters depend on cycle rate. 4, These parameters depend on output loading. Specified values are obtained with the output open. 5. Aninitial pause of 200ps is required after power-up followed by any 8 RAS cycles (DT/OE “high”) and any 8 SC cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS initialization cycles instead of 8 RAS cycles are required. 6. AC measurements assume ty = Sns. 7. Virncminy 49d Vir, max ate reference levels for measuring timing of input signals. Also, transition times are measured between Vj, and Vi. 8, RAM port outputs are measured with a load equivalent to 1 TTL load and 100pF. Dour reference levels : Voy / Vox. = 2.0V /O.8V. 9. SAM port outputs are measured with a load equivalent to | TTL load and 30pF. Dourteference levels : Voy / Vox = 2.0V /O.8V. 10, tog gas. YOEZ Amman. "Sz Aman) ANG ts Ez, ¢man,) define the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. 11, Bither tacyy oF tagit must he satisfied for a read cycles. 12. These parameters are referenced to CAS leading edge of early write cycles and to WB / WE leading edge in OE-controlled write cycles and read-modify-write cycles. 13. twesstawps tewn and twp are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If twes > twes min.» the cycle is an early write cycles and the data out pin will remain open circuit (high impedance) throughout the entire cycle: If tawp2 tw cin.» two Tew imin. 89d tawo® AWD (min, the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell : If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate, 14, Operation within the tcp imax) limit insures that tac jmax.) CaN he met. tac (max. iS Specified as a reference point only : If tacp is greater than the specified {RCD (max. limit, then access time is controlled by tcc. 15, Operation within the tgp (max, limit insures that tac gmax) CAN BE Met. teap mary iS Specified as a reference point only: If tgap is greater than the specified tia ¢max. limit, then access time is controlled by tay: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C121
os ee R= CVI7 roan DS. 0_ st =p PT eal ee ee Zivwer C-122 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
WRITE CYCLE (EARLY WRITE) tow, co ae | | tow va = Pe ay a pete TT Te ee ow aie ST eer “te our YO ggg Pee ‘WM! data 0: Write Disable 1: Write Enable TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-123
WRITE CYCLE (OE CONTROLLED WRITE) eae ee os Ye (—_—— HT or “LT a ee C-124 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
ms yt ——— a a js —S con = ps ee Sa te wa loo [soa tus, iar! ea (Tk Loy Yor oven {ose “HT of “L" _vo [tf Precae L Somat | WM! data 0: Write Disable 1: Write Enable TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C125
tesa] ws at edit St oe geet [eH RE who ue a = ea “HT on *L" C-126 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
FAST PAGE MODE WRITE CYCLE (EARLY WRITE) we Aad a eaccpe an meee pe | rane os Es fe ee el] torn tren | is cour ow ggg THT on “Ut Po |Win ee ‘WM! data 0: Write Disable 1: Write Enable TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-127
FAST PAGE MODE READ-MODIFY-WRITE CYCLE ais ea eee, wore ye Dy can [town [oun ee egal eine DOE Vi Oy ey MGM —ee SESS Set ces a fe ee ES [Tmo | WM! data 0: Write Disable 1: Write Enable C-128 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
a ae teas] we ee | KA SAT hE oth oft" TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-129
CAS BEFORE RAS REFRESH CYCLE ms ht ee NT - Note: AQ-A8 = Don’t Care (“H* or “L") 27H" or “UL C-130 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
ox Nai i, St oe ey
2 THT or “Lt
rr — wm tt L | —2" wisieL fone tas =] (Delayed Write) (Early Write) cent or tt C-132 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
lhe, [a . page | A i GY MMMM Wi HT or “Ut TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-133
a te = 4 “iin er 8’ oH or “Ut |? | Panini || Paez | C134 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
ca } | tay | toon mi SS San, cele | DO tes eB % ee a re a) ‘WMI data 0: Write Disable *3 COLUMN SELECT WIMO1 - Column 0 (Ac = 0, Age = 0 Watton W2/102 - Column 1 (Ajc=0, Age = 1 eo W3/103 - Column 2 (Ajc = 1, Age = 0 \\. W4/l04 - Column 3 (Aye= 1, Age = 1 = 1 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-135
PAGE MODE BLOCK WRITE CYCLE ET ey ronan in U7 yeoW WO UN = MY = MULL a oes “HT or “LT | | Don't Care Block Write (Non Mask) WMI data 0: Write Disable |: Write Enable *3 COLUMN SELECT WI/MOI - Colume 0 (Aye = 0, Age = 0 Walton W2/102 - Column | (Aje = 0, Age = | oy W3/103 - Column 2 (Aye = 1, Age = 0 \\. ~ W4/l04 - Column 3 (Aye = I, Age= I -4 C-136 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
READ TRANSFER CYCLE (Previous Transfer is WRITE TRANSFER CYCLE) we = os te mlb = =o | we, se = tte ira pu Note > SE = Vy nu on “tt TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-137
REAL TIME READ TRANSFER CYCLE . — —— soo Ie 3 Oe a Nate 3S | -” “= z ro slot 0 3 es) Eon ENED Cl x ~ TAP MB (A7) THT or “LY C-138 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
a SPLIT READ TRANSFER CYCLE foe “ws see =a on a iy 2 a NEY GB) [esa ride) (0b) a dh 8h | Note: SE = Vi TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-139
PSEUDO WRITE TRANSFER CYCLE mas ye } os tr ule aly VT RAD a 7 | «lA TT Ree ON — our Yor" patour_ J oata-our) pew tHE of “Lr C-140 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
a WRITE TRANSFER CYCLE ms Yeo ) “ . = | toon oi: Ee Sry pe el U ase yor TAP SB ant Previous =} 1+ New Row oata vmrowes ya eae wee TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-141
SPLIT WRITE TRANSFER CYCLE wt —— ae os Ym | Net
2 Ts |
wal | ene BB) [estan rite) do dB da ah] ee YM MY MM Lower SAM 0~ 127 Upper SAM 128~ 255 STH oe *L" Note: SE = Vy C-142 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
a SERIAL READ CYCLE (SE=Vj1) as yn ser air ki ba [eee sca er Note : $8 Vi oH ores SERIAL READ CYCLE (SE Controlled Outputs) ws Yu ty tren AAA ew | — J Ss SJ - al) Cour Yor X ontur Ml onur P— oes {TRB NGA, NL, “Hr on “te TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-143
SERIAL WRITE CYCLE (SE=Vj,) Ws ym h aan he se ye fchallcbolibellcb thou Note : SE= Va “Hon SERIAL WRITE CYCLE (SE Controlled Inputs) ° ws yr . rs} ton _ tee Jt te J oe —] tse od tsce swo NI Y | N [Ef | Pit aon Cie, Hes si01 ~s108- L our Ye >? 8 THT or “LT C-144 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
ADDRESS INPUTS : Ag ~ Ag The 17 address bits required to decode 8 bits of the 1,048,576 cell locations within the dynamic RAM memory array of the TC528128B are multiplexed onto 9 address input pins (Ag~Ag). Nine row address bits are latched on the falling edge of the row address strobe (RAS) and the following eight column address bits are latched on the falling edge of the column address strobe (CAS). ROW ADDRESS STROBE : RAS A random access cycle or a data transfer cycle begins at the falling edge of RAS. RAS is the control input that latches the row address bits and the states of CAS, DT/OE, WB/WE, SE and DSF to invoke the various random access and data transfer operating modes shown in Table 2. RAS has minimum and maximum pulse widths and a minimum precharge requirement which must be maintained for proper device operation and data integrity. The RAM port is placed in standby mode when the RAS control is held “high”. COLUMN ADDRESS STROBE : CAS CAS is the control input that latches the column address bits and the state of the special function input DSF to select, in conjunction with the RAS control, either read / write operations or the special block write feature on the RAM port when the DSF input is held “low” at the falling edge of RAS. Refer to the operation truth table shown in Table 1. CAS has minimum and maximum pulse widths and a minimum precharge requirement which must be maintained for proper device operation and data integrity. CAS also acts as an output enable for the output buffers on the RAM port DATA TRANSFER/OUTPUT ENABLE : DT/OE The DT/OE input is a multifunction pin. When DT/OE is “high” at the falling edge of RAS, RAM port ‘operations are performed and DT/OE is used as an output enable control. When the DT/OE is “low” at the falling edge of RAS, a data transfer operation is started between the RAM port and the SAM port. TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C145
WRITE PER BIT/WRITE ENABLE : WB/WE The WB/WE input is also a multifunction pin, When WB/WE is “high” at the falling edge of RAS, during RAM port operations, it is used to write data into the memory array in the same manner as a standard DRAM. When WB/WE is “low” at the falling edge of RAS, during RAM port operations, the write-per-hit function is enabled, The WB/WE input also determines the direction of data transfer between the RAM array and the serial register (SAM). When WB/ WE is “high” at the falling edge of RAS, the data is transferred from RAM to SAM. (read transfer). When WB/WE is “low” at the falling edge of RAS, the data is transferred from SAM to RAM (masked-write transfer). WRITE MASK DATA/DATA INPUT AND OUTPUT : W,/10,;~Wg/10g When the write-per-bit function is enabled, the mask data on the W,/1O, pins is latched into the write mask register (WM1) at the falling edge of RAS. Data is written into the DRAM on data lines where the write-mask data is a logic “1”, Writing is inhibited on data lines where the write-mask data is a logic “0”. The write-mask data is valid for only one cycle. Data is written into the RAM port during a write or read-modify-write cycle. The input data is latched at the falling edge of either CAS or WB/WE, whichever occurs late. During an early- write cycle, the outputs are in the high impedance state. Data is read out of the RAM port during a read or read- modify-write cycle. The output data becomes valid on the W,/10, pins after the specified access times from RAS, CAS, DT/OE and column address are satisfied and will remain valid as long as CAS and DT/OE are kept “low”. ‘The outputs will retum to the high-impedance state at the rising edge of either CAS or DT/OE. whichever occurs first. SERIAL CLOCK : SC All operations of the SAM port are synchronized with the serial clock SC. Data is shifted in or out of the SAM registers at the rising edge of SC. In a serial read, the output data becomes valid on the SIO pins after the maximum specified serial access time tsca from the rising edge of SC. The serial clock SC also increments the &-bits serial pointer (7-bits in split register mode) which is used to select the SAM address. The pointer address is incremented in a wrap-around mode to select sequential locations after the starting location which is determined by the column address in the read transfer cycle. When the pointer reaches the most significant address location (decimal 255), the next SC clock will place it at the least significant address location (decimal 0). The serial clock SC must he held at a constant Vj or Vj_ level during read / pseudo write / write transfer operations and should not he clocked while the SAM port is in the standby mode to prevent the SAM pointer from being incremented C146 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
-)) OO SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS— SERIAL ENABLE : SE ‘The SE input is used to enable serial access operation. In a serial read cycle, SE is used as an output control. Ina serial write cycle, SE is used as a write enable control. When SE is “high”, serial access is disabled, however, the serial address pointer location is still incremented when SC is clocked even when SE is “high” SPECIAL FUNCTION CONTROL INPUT : DSF The DSF input is latched at the falling edge of RAS and CAS and allows for the selection of various random port and data transfer operating modes. In addition to the conventional multiport DRAM, the special features consisting of flash write, block write, load color register and split read / write transfer can be invoked. SPECIAL FUNCTION OUTPUT : QSF QSF is an output signal which, during split register mode, indicates which half of the split SAM is being accessed. QSF “low” indicates that the lower split SAM (Bit 0~127) is being accessed and QSF “high” indicates that the upper split SAM (Bit 128~255) is being accessed. QSF is monitored so that after it toggles and after allowing for a delay of tsrs, split read / write transfer operation can be performed on the non-active split SAM. SERIAL INPUT/OUTPUT : SIO1~SIO8 Serial input and serial output share common I/O pins. Serial input or output mode is determined by the most recent read, write or pseudo write transfer cycle. When a read transfer cycle is performed, the SAM port is in the output mode. When a write or pseudo write transfer cycle is performed, the SAM port is switched from ‘output mode to input mode. During subsequent write transfer cycle, the SAM remains in the input mode. ‘TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 0-147
The RAM port and data transfer operating of the TC524258B are determined by the state of CAS, DT/OE, WB/WE, SE and DSF at the falling edge of RAS and by the state of DSF at the falling edge of CAS. The Table 1 and the Table 2 show the operation truth table and the functional truth table for a listing of all available RAM port and transfer operation, respectively. —, Table 1. Operaton Truth Table CAS fallingedge . DSF) r - ‘RAS falingedge yO ° ° 1 1 ee - I — oof fe CRS before RAS Refresh = — | 1 0 0 © Masked Write Transfer SPI Write Transfer with Masked Write Transfer _Splt Wet Transfer with fan nn my fi Fa} 0 1 * Read transfer SplitRead Transfer Read Transfer Split Read Transfer | Aa A nn LE 0 * Renate per Bit Masked Fash Write Masked Block Write Masked Flash Write pepe oro Teese Load Color | Block Write Load Color 2. Functional Truth Table a eet me De | Function ee Oe server [| 0 |e fo fol = [om [ow [ome | [+ fool | Jpeswowtenin Te ['o [oo Toft + [ow for PP fe yt intone | Te oo [fee Pom Powe [ome [Ts Peel | Jenetomee Pe Pe Pept ew Pow PP TP | frwnmnonte Pe Ppp fe Pw PP ty] fw ede Le Pe fef eo [vm [een wae | [ow fool | Column Column Toad Masked Block Wetie ° AICTE Select use cel A A OG ed use | fenewe ef Te Pepe 6 eo oom fs [fom Tt || Column Column Block Write A2C-7C Select lor . Color jw ee Pee PT Pee TY *:“O" or “I”, TAP : SAM start address , : not used 7 If the special function control input (DSF) is in the “low” state at the falling edges of RAS and CAS, only the conventional multiport DRAM operating features can be invoked: CAS-before-RAS refresh, write transfer, pseudo-write transfer, read transfer and read write modes. If the DSF input is “high” at the falling edge of RAS, special features such as split write transfer, split read transfer, flash write and load color register can be invoked. If the DSF input is “low” at the falling edge of RAS and “high” at the falling edge of CAS, the block write special feature can be invoked, C-148 ‘TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
maintained throughout the fast page mode write or read-modify-write cycle. performing a memory cycle at each of the 512 rows in the DRAM array within the specified 8ms refresh period. accomplished with “RAS-Only” cycle. successive CAS-before-RAS refresh cycle, CAS can remain “low” while cycling RAS. RAS after the specified RAS-precharge period (Refer to Figure 1). Figure 1. Hidden Refresh Cycle
WB / WE is held “low” at the falling edge of RAS, during a random access operation, the write-mask is enabled. so that new data is written. The truth table of the write-per-bit function is shown in Table 3. Table 3. Truth table for write-per-bit function
2002 TT ute CALE - ow Cll [Clejolojoje[ojo}
Figure 2. Write-per-bit timing cycle Figure 3. Corresponding bit-map 0-150 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
color register cycle is initiated by holding CAS, WB/WE, DT/OE and DSF “high” at the falling edge of RAS. but the memory cells on the row address latched at the falling edge of RAS are refreshed. enable the flash write operation for selected 1/O blocks (Refer to Figure 4 and 5). completed in less than 92.2 seconds. Figure 4. Flash Write Timing
2s SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS SAM PORT OPERATION The TC528128B is provided with a 256 words by 8 bits serial access memory (SAM) which can be operated in the single register mode or the split register mode. SINGLE REGISTER MODE When operating in the single register mode, high speed serial read or write operations can be performed through the SAM port independent of the RAM port operations, except during read / write / pseudo-write transfer cycles. The preceding transfer operation determines the direction of data flow through the SAM port. If the preceding transfer operation is a read transfer, the SAM port is in the output mode. If the preceding transfer operation is a write or pseudo write transfer, the SAM port is in the input mode. The pseudo write transfer operation only switches the SAM port from output mode to input mode; Data is not transferred from SAM to RAM. Serial data can be read out of the SAM port after a read transfer (RAM->SAM) has been performed. The data is shifted out of the SAM port starting at any of the 256 bits locations. ‘The TAP location corresponds to the column address selected at the falling edge of CAS during the read transfer cycle. The SAM registers are configured as circular data registers. The data is shifted out sequentially starting from the selected tap location to the most significant bit and then wraps around to the least significant bit, as illustrated below. Start, address : Tap location ‘Subsequent real-time read transfer may be performed on-the-fly as many times as desired, within the refresh constraints of the DRAM array. Simultaneous serial read operation can be performed with some timing restrictions. A pseudo write transfer cycle is performed to change the SAM port from output mode to input mode in order to write data into the serial registers through the SAM port. A write transfer cycle must be used subsequently to load the SAM data into the RAM row selected by the row address at the falling edge of RAS. The starting location in the SAM registers for the next serial write is selected by the column address at the falling edge of CAS. The truth table for single register mode SAM operation is shown in Table 4. TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-155
Table 4, Truth Table for SAM Port Operation SAM PORT DI/OE at the - OPERATION | falling edge of RAS| S© | SE FUNCTION Preceded by a Serial Output Mode Enable Serial Read | oa Transfe eral Output [_H__ [Disable Serial Read fansier Sesial input Mode [__L [Enable Serial Write Write Transf Serial Inpu rite Transfer anes | _H__ [Disable Serial Write « Enable Serial Write Serial Input Mode nadie Serial NIH _| Pseudo Write Transfer |_H_ [Dissbte Serial Wriee | SPLIT REGISTER MODE In split register mode, data can be shifted into or out of one half of the SAM while a split read or split write transfer is being performed on the other half of the SAM. A normal (Non-split) read / write / pseudo write transfer operation must precede any split read / write transfer operation. The non-split read, write and pseudo write transfer will set the SAM port into output mode or input mode. The split read and write transfers will not change the SAM port mode set by preceding normal transfer operation. RAM port operation may be performed independently except during split transfers. In the split register mode, serial data can be shifted in or out of one of the split SAM registers starting from any at the 128 tap locations, excluding the last address of each split SAM, data is shifted in or out sequentially starting from the selected tap location to the most significant bit (127 or 255) of the first split SAM and then the SAM pointer moves to the tap location selected for the second split SAM to shift data in or out sequentially starting from this tap location to the most significant bit (255 or 127) and finally wraps around to the least significant bit, as illustrated in the example below. Tap location Tap location ro ro PTR (0 GEE==FE REFRESH The SAM data registers are static flip-flop, therefore a refresh is not required. 0-156 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
Figure 11. (a) Normal (Non-split) Transfer (b) Split Transfer of the serial register will be reloaded from the RAM array.
‘A write transfer cycle consist of loading the content of the SAM register into a selected row of the RAM array, If the SAM data to be transferred must first be loaded through the SAM port, a pseudo write transfer operation must precede the write transfer cycles. However, if the SAM port data to be transferred into the RAM. was previously loaded into the SAM via a read transfer, the SAM to RAM transfer can be executed simply by performing a write transfer directly. A write transfer is invoked by holding CAS “high”, DT/OE “low”, WB/WE “low”, SE “low” and DSF “low” at the falling edge of RAS. This write transfer is selectively controlled per RAM I/O block by setting the mask data on the W/10; lines at the falling edge of RAS (same as in the write- per-bit operation). Figure 15 and 16 show the timing diagram and block diagram for write transfer operations, respectively. Ao~hs Wilda 82m YUK__ SAM Start WM SRS ////////// MMM Ws /10)~Wa 104 sc S10;~SI0g ose Yas je UMM eEEE@@@@EEeL : Mask Data ( © : Not Transferred 1: Transferred Figure 15, Write Transfer Timing ‘The row address selected at the falling edge of RAS determines the RAM row address into which the data will be transferred. The column address selected at the falling edge of CAS determines the start address of the serial pointer of the SAM. After the write transfer is completed, the SIO lines are set in the input mode so that serial data synchronized with the SC clock can be loaded. C-160 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
SAM Start Address to $10;~SI05 N ‘ON Aom~As | 3 256xBbits C>) § |= LLL ste z 4 512 x 256 x 8bits ow eo Memory Cell Array Wy/10, — W2/!02 — W3/103, Wal 10a Ws/I0s — We/I0g = W7/107 We / 10g Mask y+ ye or “ oye “ =o" aye Data @ @ Transfer operation Transfer operation is inhibited. is inhibited. Figure 16, Block Diagram for Write Transfer Operation ‘When consecutive write transfer operations are performed, new data must not be written into the serial register until the RAS cycle of the preceding write transfer is completed. Consequently, the SC clock must be held at a constant Vy, or Vij; during the RAS cycle. A rising edge of the SC Clock is only allowed after the specified delay tsp from the rising edge of RAS, at which time a new row of data can be written in the serial register. PSEUDO WRITE TRANSFER CYCLE A pseudo write transfer cycle must be performed before loading data into the serial register after a read transfer operation has been executed. The only purpose of a pseudo write transfer is to change the SAM port mode from output mode to input mode (A data transfer from SAM to RAM does not occur). After the serial register is loaded with new data, a write transfer cycle must be performed to transfer the data from SAM to RAM. A pseudo write transfer is invoked by holding CAS “high”, DT/OE “low”, WB/WE “low”, SE “high” and DSF “low” at the falling edge of RAS. The timing conditions are the same as the one for the write transfer cycle except for the state of SE at the falling edge of RAS. TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. c-161
and the pointer is incremented from this location by cycling the SC clock. Figure 25. Example of Split SAM Registerr Operation Sequence C-166 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
The next operation is a pseudo write transfer which switches the SAM port from output mode to input mode in preparation for either write transfers or split write transfers. The column address latched at the falling edge of CAS during the pseudo write transfer sets the serial register tap location. Serial data will be written into the SAM starting from this location, TRANSFER OPERATION WITHOUT CAS During all transfer Cycles, the CAS input clock must be cycled, so that the column address are latched at the falling edge of CAS, to set the SAM tap location. If CAS was maintained at a constant “high” level during a transfer cycle, the SAM pointer location would be undefined. Therefore a transfer cycle with CAS held “high” is not allowed (Refer to the illustration below). RR" Proper BS —\\ [ Transfer cycle Address ZIMA 82 YUK — SAM Start WILL rr [——_ oO _ [rr us Allowed address YY ow YW TAP LOCATION SELECTION IN SPLIT TRANSFER OPERATION (a) Ina split transfer operation, column addresses AOC through A6C must be latched at the falling edge of CAS in order to set the tap location in one of the split SAM registers. During a split transfer, column address A7C is controlled internally and therefore it is ignored internally at the falling edge of CAS. RAS BT 7 [—— addresses ZK Row Xda tap address MU son aon ‘ADC~ABC (A7C is don't care:High or Low) During a split transfer, it is not allowed to set the last address location (AOC~A6C=7F), in either the lower SAM or the upper SAM, as the tap location. TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-167
SPLIT TRANSFER CYCLE AFTER NORMAL TRANSFER CYCLE A split transfer may be performed following a normal transfer (Read / Write / Pseudo-Write transfer) Provided that a minimum delay of 30ns from the rising edge of the first clock SC is satisfied (Refer to the illustration shown below). 2 ip en Cn ee ose ! -—— QSF X : —__ sc H J U LJ L Lo. Transfer Operation Sond jntiset Tontie __ exe transfer Operation is allowed. ‘ ! NORMAL READ TRANSFER CYCLE AFTER NORMAL READ TRANSFER CYCLE Another read transfer may be performed following the read transfer provided that a minimum delay of 30ns from the rising edge of the first clock SC is satisfied (Refer to the illustration shown below). H a rs Oe ce DoE > | [—— DSF i ee QSF X + ee Transfer Operation | Bens yaleet Transfey || Next Transfer Operation is allow i ! TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. C-169
NORMAL TRANSFER AFTER SPLIT TRANSFER A normal transfer (read / write / pseudo write) may be performed following split transfer operation provided that a 30ns minimun delay is satisfied after the QSF signal toggles. CD Split Transfer» iq 3008 Min. _,__ Normal Transfer Operation Allowed POWER-UP Power must be applied to the RAS and DT/OE input signals to pull them “high” before or at the same time as the Voc supply is tuned on. After power-up, a pause of 200 seconds minimum is required with RAS and DT/OE held “high”. After the pause, a minimum of 8 RAS and 8 SC dummy cycles must be performed to stabilize the internal circuitry, before valid read, write or transfer operations can begin. During the initialization period, the DT/OE signal must be held “high”. If the internal refresh counter is used, a minimum 8 CAS-before: RAS initialization cycles are required instead of 8 RAS cycles, INITIAL STATE AFTER POWER-UP When power is achieved with RAS, CAS. DT/OE and WB/WE held “high”, the internal state of the TC528128B is automatically set as follows. However, the initial state can not be guaranteed for various power-up conditions and input signal levels. Therefore, it is recommended that the initial state be set after the initialization of the device is performed (200 seconds pause followed by a minimum of 8 RAS cycles and 8 SC cycles) and before valid operations begin. (is State after power-up SAM port Tnput Mode [Color Register WMI Register Write Enable TAP pointer invalid C170 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.