TC520ACOE

TC520A TELCOM | Alldatasheet

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Technical content

3-39TELCOM SEMICONDUCTOR, INC. TC520A TC520A-1 9/16/96 B LOADCMPTR CMPTRDVDGND CEVDD A D IN OSC OUT DCLK OSC IN D OUT READ 1 14 21 3 31 2 41 1 51 0 TC520ACPD TC520ACOE D INB LOAD DVDGND CEVDD D CLKA D OUTOSC OUT READOSC IN N/CN/C FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION LOGIC CONTROL GATE 8-BIT COUNTER ÷256 8-BIT SHIFT REG. ÷4 GATE SYSCLK A B CMPTR CE DV GATE TIME OUT FORCE AUTO-ZERO POLARITY BIT CLEAR COUNT VDD GND 16-BIT COUNTER 18-BIT SHIFT REGISTER GATE OVERRANGE BIT

8 READ

SERIAL INTERFACE ADAPTER FOR TC500 A/D CONVERTER FAMILY

FEATURES

n Converts TC500/500A/510/514 to Serial Operation n Programmable Conversion Rate and Resolution for Maximum Flexibility n Supports up to 17 Bits of Accuracy Plus Polarity Bit n Low Power Operation: Typically 7.5mW n 14-Pin DIP or 16-Pin SOIC Packages n Polled or Interrupt Mode Operation

ORDERING INFORMATION

Part No. Package Temp. Range TC520ACOE 16-Pin SOIC (Wide) 0 °C to +70°C TC520ACPD 14-Pin Plastic DIP 0 °C to +70°C TC500EV Evaluation Kit for TC500 Family EVALUATION KIT AVAILABLE GENERAL DESCRIPTION The TC520A Serial Interface Adapter provides logic control for TelCom's TC500/500A/510/514 family of dual slope, integrating A/D converters. It directly manages TC500 converter phase control signals A, B, and CMPTR thereby reducing host processor task loading and software complex- ity. Communication with the TC520A is accomplished over a 3 wire serial port. Key converter operating parameters are programmable for complete user flexibility. Data conversion initiated when the CE input is brought low. The converted data (plus overrange and polarity bits) are held in an 18 bit shift register until read by the processor, or until the next conversion is completed. Data may be clocked out of the TC520A at any time, and at any rate the user prefers. A Data Valid (DV) output is driven active at the start of each conversion cycle indicating the 18 bit shift register update has just been completed. This signal may be polled by the processor, or can be used as data ready interrupt. The TC520A timebase can be derived from an external frequency source of up to 6MHz; or can operate from its own external crystal. It requires a single 5V logic supply and dissipates less than 7.5mW.

3-40 TELCOM SEMICONDUCTOR, INC. TC520A SERIAL INTERFACE ADAPTER FOR TC500 A/D CONVERTER FAMILY ELECTRICAL CHARACTERISTICS: VDD = 5V, fosc = 1 MHz, TA = +25°C, unless otherwise specified. Symbol Parameter Min Typ Max Unit Supply VDD Operating Voltage Range 4.5 5 5.5 V IDD Supply Current — 0.8 1.5 mA Input Characteristics VIL Low Input Voltage — — 0.8 V VIH High Input Voltage 2.0 — — V IIL Input Leakage Current — — 10 µA IPD Pull-down Current (CE) — 5 — µA IPU Pull-up Current (READ, LOAD) — 5 — µA Output Characteristics (IOUT = 250 µA, VDD = 5V) VOL Low Output Voltage — 0.2 0.3 V VOH High Output Voltage 3.5 4.3 — V tR , tF C L = 10pF, Rise/Fall Times — — 250 nsec Oscillator (OSCIN, OSCOUT ) fXTL Crystal Frequency — 1.0 4.0 MHz fOSC External Frequency (OSCIN) — — 6.0 MHz Timing Characteristics tRD READ Delay Time 250 — — nsec tRS Data Read Setup Time 1 — — µsec tDRS D CLK to DOUT Delay 450 — — nsec tLS LOAD Setup Time 1 — — µsec tDLS Data Load Setup Time 50 — — nsec tPWL D CLK Pulse Width Low Time 150 — — nsec tPWH D CLK Pulse Width High Time 150 — — nsec tLDL Load Default Low Time 250 — — nsec tLDS Load Default Setup Time 250 — — nsec Parameter tIZ Integrator ZERO Time — 0.5 — msec tAZI Autozero (RESET) Time at Power-Up — 100 — msec ABSOLUTE MAXIMUM RATINGS* * Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the Operational Specifications is not implied. Any exposure to Absolute Maximum Rating Conditions may affect device reliability.

3-41TELCOM SEMICONDUCTOR, INC. TC520A SERIAL INTERFACE ADAPTER FOR TC500 A/D CONVERTER FAMILY Pin No. Pin No. 14-Pin PDIP 16-Pin SOIC Package Package Symbol Description 11 V DD Input. +5V ±10% power supply input with respect to DGND. 2 2 DGND Input. Digital Ground. 3 3 CMPTR Input, active high or low (depending on polarity of the voltage input to A/D converter). This pin connects directly to the zero-crossing comparator output (CMPTR) of the TC5xx A/D converter. A High-to-Low state change on this pin causes the TC520A to terminate the de-integrate phase of conversion. 4 4 B Output, active high. The A and B outputs of the TC520A connect directly to the A and B inputs of the TC5xx A/D converter connected to the TC520A. The binary code on A, B determines the conversion phase of the TC5xx A/D converter: (A, B) = 01 places the TC5xx A/D converter into the Auto Zero phase; (A, B) =10 for Integrate phase (INT); (A, B) =11 for De-integrate phase INT) and (A, B) = 00 for Integrator Zero phase (IZ). Please see the TC500 family data sheets for a complete description of these phases of operation. 5 5 A Output, active high. See pin 4 description above. 6 6 OSC OUT Input. This pin connects to one side of an AT-cut crystal having a effective series resistance of 100Ω (typ) and a parallel capacitance of 20pF (typ). If an external frequency source is used to clock the TC520A, this pin must be left floating. 7 7 OSC IN Input. This pin connects to the other side of the crystal described in pin 6 above. The TC520A may also be clocked from an external frequency source connected to this pin. The external frequency source must be a pulse train having a duty cycle of 30% (minimum); rise and fall times of 15nsec and a min/ max amplitude of 0 to V IH. If an external frequency source is used, pin 6 must be left floating. A maximum operating frequency of 4MHz (crystal) or 6MHz (external clock source) is permitted. 8 N/C No connection on 16 pin package version. 9 N/C No connection on 16 pin package version. 8 10 READ Input, active low, level and negative edge triggered. A high-to low transition on READ loads serial port output shift register with the most recent converted data. Data is loaded such that the first bit transmitted from the TC520A to the processor is the overrange bit (OVR), followed by the polarity bit (POL) (high = input positive; low = input negative). This is followed by a 16 bit data word (MSB first). (OVR is available at the D OUT as soon as READ is brought low. This bit may be used as the 17th data bit if so desired.) The DOUT pin of the serial port is enabled only when READ is held low. Otherwise, DOUT remains in a high impedance state. A serial port read access cycle is terminated at any time by bringing READ high. 91 1 D OUT Output, logic level. Serial port output pin. This pin is enabled only when READ is low (see READ pin description). 10 12 D CLK Input, positive and negative edge triggered. Serial port clock. With READ low, serial data is clocked into the TC520A at each low-to-high transition of DCLK , and clocked out of the TC520A on each high-to-low transition of DCLK . A maximum serial port DCLK frequency of 3MHz is permitted. PIN DESCRIPTIONS DETAILED DESCRIPTION The TC520A input and output signals are outlined in the table below.

3-42 TELCOM SEMICONDUCTOR, INC. TC520A SERIAL INTERFACE ADAPTER FOR TC500 A/D CONVERTER FAMILY PIN DESCRIPTIONS (Cont.) Pin No. Pin No. 14-Pin PDIP 16-Pin SOIC Package Package Symbol Description 11 13 D IN Input, logic level. Serial port input pin. The TC5xx A/D converter integration time (TINT) and Autozero time (TAZ) values are determined by the LOAD VALUE byte clocked into this pin. This initialization must take place at power up, and can be rewritten (or modified and rewritten) at any time. The LOAD VALUE is clocked into DIN MSB first. 12 14 LOAD Input, active low; level and edge triggered. The LOAD VALUE is clocked into the 8 bit shift register on board the TC520A while LOAD is held low. The LOAD VALUE is then transferred into the TC520A internal timebase counter (and becomes effective) when LOAD is returned high. If so desired, LOAD can be momentarily pulsed low (eliminating the need to clock a LOAD VALUE into D IN). In this case, the current state of DIN is clocked into the TC520A timebase counter selecting either a count of 65536 (DIN = High), or count of 32768 (DIN = Low). 13 15 DV Output, active low. DV is brought any time the TC520A is in the AZ phase of conversion. This occurs when either the TC520A initiates a normal AZ phase by setting A, B, equal to 01; or when CE is pulled high (which overrides the normal A, B sequencing and forces an AZ state). DV is returned high when the TC520A exits AZ. 14 16 CE Input, active low, level triggered. Conversion will be continuously performed as long as CE remains low. Pulling CE high causes the conversion process to be halted, and forces the TC520 into the AZ mode for as long as CE remains high. CE should be taken high whenever it is necessary to momentarily suspend conversion (for example: to change the address lines of an input multiplexer). CE should be pulled high only when the TC520A enters an AZ phase (i.e. when DV is low). This is necessary to avoid excessively long integrator discharge times which could result in erroneous conversion. This pin should be grounded if unused. It should be left floating if a 0.01µF RESET capacitor is connected to it (see Applications section). DETAILED DESCRIPTION (CONT.) TC520A Timing The TC520A consists of a serial port and state machine. The state machine provides control timing to both the TC5xx A/D converter connected to the TC520A, as well as sequen- tial timing for TC520A internal operation. All timing is de- rived from the frequency source at OSC IN and OSCout. This frequency source can be either an externally-provided clock signal, or external crystal. If an external clock is used, it must be connected to the OSC IN pin and OSCOUT must remain floating. If a crystal is used, it must be connected between the OSC IN and OSCOUT and physically located as close to the OSC IN and OSC OUT pins as possible. The incoming fre- quency is internally divided by 4 and the resulting clock (SYSCLK) controls all timing functions. TC5xx A/D Converter Control Signals The TC520A control outputs (A, B) and control input (CMPTR) connect directly to the corresponding pins of the TC5xx A/D converter. A conversion is consummated when A, B have been sequenced through the required 4 phases of conversion: Auto Zero (AZ), Integrate (INT), De-integrate INT) and Integrator Zero (IZ) (See Figure 1). The Auto Zero phase compensates for offset errors in the TC5xx A/D converter. The integrate phase connects the voltage to be converted to the TC5xx A/D converter input (resulting in an integrator output dv/dt directly proportional to the magnitude of the applied input voltage). Actual A/D conversion (count- ing) is initiated at the start of the D INT phase and terminates when the integrator output crosses 0V. The integrator output is then forced to 0V during the IZ phase and the converter is ready for another cycle. Please see the TC500/500A/510/ 514 data sheet for a complete description of these phases. The number of SYSCLK periods (counts) for the AZ and INT phases is determined by the LOAD VALUE. The LOAD VALUE is a single byte that must be loaded into the most significant byte of 16 bit counter on-board the TC520A during initialization. The lower byte of this counter is pre-loaded to a value of 0FFH (256 10) and cannot be changed. The LOAD VALUE (upper 8 bits of the counter) can be programmed over a range of 0FFH to 00H (corresponding to

3-43TELCOM SEMICONDUCTOR, INC. TC520A SERIAL INTERFACE ADAPTER FOR TC500 A/D CONVERTER FAMILY a range of AZ = INT = 256 counts to 65536 counts). (See Figure 2). The LOAD VALUE sets the number of counts for both the AZ and INT phases and directly affects resolution and speed of conversion. The greater the number of counts allowed for AZ and INT; the greater the A/D resolution, but the slower the conversion speed. The time period required for the DINT phase is a function of the amount of voltage stored on the integrator during the INT phase, and the value of V REF . The DINT phase is initiated by the TC520A immediately after the INT phase, and termi- nated when the TC5xx A/D converter changes the state of the CMPTR input of the TC520A (indicating a zero crossing). In general, the maximum number of counts chosen for D INT is twice that of INT (with VREF chosen at VIN (max)/2). Choosing these values guarantees a full count (maximum resolution) during D INT when VIN = VIN(max). The IZ phase is initiated immediately following the DINT phase maintained until the CMPTR input transitions high. This indicates the integrator is initialized and ready for another conversion cycle. This phase typically takes 2msec. Serial Port Control Signals Communication to and from the TC520A is accom- plished over a 3 wire serial port. Data is clocked into D IN on the rising edge of DCLK and clocked out of DOUT on the falling edge of DCLK . READ must be low to read from the serial port and can be taken high at any time, which terminates the read cycle, and releases D OUT to a high impedance state. Con- version data is shifted to the processor from DOUT in the following order: Overrange bit (which can also be used as the 17th data bit), Polarity bit, conversion data (MSB first).

APPLICATIONS

TC500 Series A/D Converter Component Selection The TC500/500A/510/514 data sheet details the equa- tions necessary to calculate values for integration resistor INT) and capacitor (CINT); auto zero and reference capaci- tors CREF and CAZ and voltage reference VREF . All equations apply when using the TC520A, except integration time (TINT) and Autozero time (TAZ ) are functions of the SYSCLK period (timebase frequency and LOAD VALUE). TelCom offers a ready-to-use TC5xx A/D converter design tool on a 3 1/2 inch diskette (Windows format). The TC500 Design Spread- sheet is an Excel-based spreadsheet that calculates values for all components as well as the TC520A LOAD VALUE. It also calculates overall converter performance such as noise rejection, converter speed, etc. This software is included in the TC500EV hardware evaluation kit and is also available free of charge from your local TelCom representative. TC520A Initialization Initialization of the TC520A consists of: (1) Power-On RESET of the TC500/520A (forcing the TC520A into an AZ phase). (2) Initializing the TC520A LOAD VALUE. Power-On RESET The TC520A powers-up with A, B = 00 (IZ Phase), awaiting a high logic state on CMPTR, which must be initiated by forcing the TC520A into the AZ phase. This can be accomplished in one of two ways: (1) External hardware (processor or logic) can momen- tarily taking LOAD or CE low for a minimum of 100 msec (tAZI); or (2) A .01µF RESET capacitor can be connected from CE to V CC to generate a power-on pulse on CE. Load Value Initialization The LOAD VALUE is the preset value (high byte of the SYSCLK timing counter) which determines the number of counts allocated to the AZ and INT phases of conversion. This value can be calculated using the TC520A spreadsheet within the TC500 Design Spreadsheet software, or can be setup as shown in the following example: (1)Select V REF , TDINT Choose the TC5xx A/D converter reference voltage (VREF ) to be half of the maximum A/D converter input voltage. For example, if VIN max = 2.5V; choose VREF = 1.75V. This forces the maximum de- integration time (TDINT) to be equal to twice the maximum integration time (TINT) ensuring a full count (maximum resolution) during DINT. (2)Calculate TINT The TC520A counter length is 16 bits (65536). Allowing the full 65536 counts for TDINT results in a maximum T INT = 65536/2 or 32768. (3)Select SYSCLK Frequency SYSCLK frequency directly affects conversion time. The faster the SYSCLK, the faster the conversion time. The upper limit SYSCLK frequency is deter- mined by the worst case delay of the TC500 com- parator (which for the TC500 and TC500A is 3.2µsec). While a faster value for SYSCLK can be used, operation is optimized (error minimized) by choosing a SYSCLK period (1/SYSCLK frequency) that is greater than 3.2µsec. Choosing T SYSCLK =

3-46 TELCOM SEMICONDUCTOR, INC. Figure 4. TC520A Timing Diagram