TC514100JL TOSHIBA | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 24

Technical content

4,194,304 WORD x 1 BIT DYNAMIC RAM * This is advanced information and specifications are subject to change without notice. DESCRIPTICN The TC514100JL/ZL is the new generation dynamic RAM organized 4,194,304 words by 1 bit. The TCS141005L/ZL utilizes TOSHIBA's CMOS Silicon gate process technology as well as advanced circuit techniques to provide wide operating margins, both internally and to the system user. Multiplexed address inputs permit the TC514100JL/ZL to be packaged in a standard 26/20 pin plastic SOJ and 20 pin plastic ZIP. The package size provides high system bit densities and is compatible with widely available automated testing and inser- tion equipment. System oriented features include single power supply of 5V 10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL.

FEATURES

+ 4,194,304 word by 1 bit organization +'Low Power + Fast access time and cycle time 550mW Operating (TC514100JL/ZL-80) [Fics /RE-BOTAAG] © «6B Operating (7052420051/21-10) 2.2aW MAK. Standby Column Address » Output unlatched at cycle end allows [cnc 88 Access Tine] —20ne_| Zins] * Common 1/0 capabsiicy wsing "EARLY weaModiepeieiee Fast Page Node + Read-Modify-Write, CAS before RAS refresh, i RAS-only refresh, Hidden refresh, Fast we: Page Mode and Test Mode capability eit + Single power supply of 5V+10% with a + All inputs and outputs TTL compatible te budle-in Vgg generator + 1024 refresh cycles/128ms + Package Plastic SOJ: TC514100JL PIN CONHECTION (TOP VIEW) Plastic ZIP: TCS14100ZL Plastic SOJ Plastic ZIP Din? 26p VSS A9[T} ps. BLOCK DIAGRAM wared2 asboour nour ff? EATS RAS G3 == -24 CAS Din [83 $44 ¥SS NCg4 2BpN.C. fas tt} if WRITE WRITE © AlOgs 22h ag nets iG] Aro ro 4) oDIN = {10} N.C. BUFFER AOg9 18p a8 aot Fad — 5 Algo 17H 47 Ane fal a3 Po wweo3 tapas arti AS ae NT 2a) a8 ae BUFF ERS(11)| DECODER PIN NAMES Azo tao coe | RAS [Row Address Strobe ‘A5O REFRESH I 025 D r ATO ig & _ of ma) o mas ie ete A-25

TC514100JL/ZL—10 ; a eeeeeeeSSSSSSSSSSSSSSSSSSSSSSSSSSS ABSOLUTE MAXIMUM RATINGS [re Sota |S | TES] [oueput Voltage «| Vou if mtn va [Operating Tenperature | Topas Pt a [Storage Temperature «| STSIG 45550] *e | 1] [Power Dissipacion | Pp) P80 aw [Short Circuit Gueput Current | Your | 50] =a] 1] RECOMMENDED DC OPERATING CONDITIONS (Ta=0% 70°C) [-swmpou [PARAMETER MIN. | TYP, | MAX, | ONET [NOTE] [Voc [Supply Voltage Sid 4S SO] 5s 2 [Vin [input High Voltage SS«dt ew «dd i [Viz ___| tnput Low Voltage =o = | 08 Pv pd DC ELECTRICAL CHARACTERISTICS (Vcc=5V#10%, Ta=0~ 70°C) [svison[ ____ PARAMETER SSS~SCS~«*MEN, [MAX JUNT TS NOTES] Operating Current [resisioosi/zu-80] - [200 | Igc, |Average Power Supply Operating Current BA 13,4,5 (RAS, CAS, Address Cycling: tac=tpc MIN.) [resisioosz/at-10| - | 25 | Standby Current ee EEL ! (RAS=CAS=VyR) : RAS Only Refresh Current [100 | Toc3 Average Power Supply Current, RAS Only Mode TESHI00I W/2L eof ~ 100 3,5 (RAS cycling, CAS*Vrw: tRc-tre MIN.) [resiaioosu/er-s0[ - | 8s | Fast Page Mode Current > Teca Average Power Supply Current, Fast Page Mode [resssnoornzu-eo] = | 60 | 3,4,5 (RAS-Vz,, CHS, Address Cycling: tpotpg MIN.) [resi«00L/zi-10| - | 50 | Standby Current Icgcs |Power Supply Standby Current vA pes lima Pape | bef "AS Before RAS Refresh Current - Icce |Average Power Supply Current, CAS Before [pestsioosn7a1-e0] - [200 | 3 RAS Mode (RAS, CAS Cycling: tpc=tpc MIN.) [resienoorn/zi-10] - | 8s | * Battery Back Up Current . Average Power Supply Current, Battery Back Up Mode Icc7 |(CAS=CAS Before RAS Cycling or 0.2V, WRITE=Vcc-0.2V vA | 3,6 AOQ~ 10=Vc¢c-0.2V or 0.2V, Dyy#Voc-0.2V, 0.2V or OPEN: tro=125us, tras=tras MIN. wuss, Input Leakage Current | 2] || Pins Not Under Test=0V) Output Leakage Curren’ Jor[Gom atin, viversso ef ao| mm | Vv Output Level [Yow _foicme Love voteare Goue-sauy | - | Output Level [vou [apie Hoven etenge Coomera df | A-26

TC514100JL/ZL—80 TC514100JL/ZL—10 . a ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Vec=5V#10%, Taz0V70°C) (Notes 7, 8, 9) [wan | max. urn] max. | [fio Raadon Sead or Wite Gle ine [uso - [reo | - [|_| [inm [Read-roaityive cycle Tine [a7s [= [ao = [=| _| [ere [vast Page Node Gale tine | so| - | | - [=] | row regres fT Te [Te Cycle Time [fac [access Tine ow MEd = = 800 fo [Feat [Access Tine from GSS =| 20 (| | as roa [faa [Access Tine from cohma Mivess [=| 40 | - | 50] aw [20,26 [Foe [access Tine from CHS Precharge [=| es _|- [38 [= [x0 | a [Forr oucput suffer turmott Delay [of 20 [| 0| 2 [n [ui | [fr [transition tine (Rise and a) | 3 [ 0 | sf [= [> _| Ar [eaas [RAS Pulse wien | 80 | 10,000 [ao0 | 10,000 | ==» |_| [Faas? [EAS Pulse wiaen Gast Page Mode) | 0 | 200,000 [200 | 200,00 [= | [ras [iowa tie Tf t- | | [resi [ead iota tine Si oo | foo [ds | [FRHcP [GAS Precharge to RAS Hold time | 45 [= [55 | =f ns | [fens [GAS Potce wien «| 20 | 20,000 | 25 | 20,000 | ns | | [Encp _[BAS vo CAS Delay Time ~~~ | 60 as | 75 | as Las [Enso [RAS co Gotuen address Delay Tie [us| 40 | 20 | so | m» [a6 | [ecae [ene co RAS Precharge Time | S| - [sot - [=] | [fcr [GAS Precharge time | 0 | fo | ns | [Fasx [Row address set-up tine | [= To [= fs | [FRA [Row Address Wold Time | x0 |= [is[- [|_| [ease coluan Address Set-Up Time | 0 | =| | - |» |_| [ecai[cotwn Address Wold Tine | as{_- [| - |=l | fo [Sig eee tet [et [el | to RAS - [Hint [cohuan Address to WAS Tead Fe [Oe = = [ =f | [enc [Read Comand Set-tp time i [=| ef = |_| [exci [Read Comand Wid Tine | 0 | - | 0] - |» |u| fom [Sage re [ot = fet = T= de | to RAS [tact |iwite Comand told aes | = ed A-27

TC514100JL/ZL—10 : SE ne ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) SYMBOL PARAMETER 2L-80 21-10 UNITS [ man. Tmax. [rere [eax | fue fase mm ese erm Te To Ts [= Te [| twoR |RAS 75 [twp [rite comand Pulse width | us| - | 20 | - [ns || [Fav [ite comand eo RAS Lead ime | 20 | - [a5 [= [ne |] [Fein |irice Comand co OHS lead Tine | 20 | - | 2 |= ]ae |] [fos [Bata Set-tp time dP = | ps [tox [pata wera tine as | = | 20 | - das (aa [torr [bate Hold Tine referenced to mS | 60 | - | 75 | - [ns | | [fReF [Refresh Period Sd? i ate | - | a fms | [twos [Write Command Set-Up Time | o [= of = Tas faa] [tow [CAS to WAYTE Delay Tine a [tru [RAS to WRITE Delay Time [eo | ~ fi00 [= ns fae | CAS Precharge to WRITE Delay Time 45 u "CPWD {(Fast Page Mode) |tosn [CAS Set-up Tine (CAS before RAS cycle) | 5 | - | 5 | - [ne |] [cur CAS Ho1d Tine (CAS before RAS cycle) | a5 [| - | 20 | - [ns | | [eae RAS to CAS Precharge Time | 0 (| - | 0 [= [ns | t CAS Precharge Time CPT | (CAS before RAS Counter Test Cycle) [fwts [Write Command Set-Up Tine(fest Vode Y=)| 10 [ - | 10 [> [ee] ] [fri [weite comand Hold Time (Test Mode mm) | 10 | - [10 | - [as || WRITE to RAS Precharge Time lo 10 (CAS before RAS Cycle) WRITE to RAS Hold Time fw feremwreas Le [= fe [= Je | A-28

TC514100JL/ZL—80 TC514100JL/ZL—10 . a ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS IN TEST MODE (Vec*5V#10%, Ta=0~70°C) (Notes 7, 8, 9) TC5141003L/ | SYMBOL PARAMETER ZL-80 ZL-10 UNIT pe ee ee [ie [Fanon Bent ov We pede ime [ass [aes [| [ere |ast Ree tote Gee tie S| PE = Ld [ine [seae Bee fom BB | a fe eae [peceee Bie tee = Te as Fag [Fesess Bias From Comm Aaaeess [= [| = [| fone] [een [Access Tine fron GH Frecteree | ~ [| s0| - | € | ws [30 | fas [ES ee wan | | ucwo [ ae | Tosco |e || Veangp [FS Poise wen Gast Fone vous) | 08 | 200,000_[ 305 | 200,00 [me [| fase wee PT Tet Tf | fese [Omit | ffm finer [SS Precterse commie [sof ff fel | fxs [GE Pave mam =i a | aesowo | a0 | t0s000 | mw || fan [Sim Mies ines [et - [st - Tel | CAPACITANCE (Vcc=SV#10%, f=1MHz, Ta=0~70°C) a a [eta | nvoe Copcteance GAS, OS, WT | |_| A A-29

a eSSSSSSSSSSSSSSSSSSSSSSSsSssssssseeee NOTES: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause per- manent damage to the device. 2, All voltages are referenced to Vss. 3. Tec, Toc3> Tecq» Tece» Igc7 depend on cycle rate. 4. Icc1, Iccy depend on output loading. Specified values are obtained with the output open. 5. Column address can be changed once or less while RAS=Vyy, and CAS@=Vzy. 6, tRas(max.)=lus is only applied to refresh of battery-back up. tpag(max.)=10us is applied to functional operating. 7, An initial pause of 200s is required after power-up followed by 8 RAS only refresh cycles before proper device operation is achieved. In case of using internal - refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh cycles are required. 8, AC measurements assume ty=5ns. 9. Vry(min.) and Vyz_(max.) are reference levels for measuring timing of input signals. Also, transition times are measured between Vyzy and Vqy. 10. Measured with a load equivalent to 2 TTL loads and 100pF. 11. torr(max.) defines the time at which the output achieves the open circuit con- dition and is not referenced to output voltage levels. 12, Either trcy or try must be satisfied for a read cycle. 13. These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in read-modify-write.cycles. 14. twos, trwD» tcwD» tawp and tcpyp are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If twos? twcs (min.), the cycle is an early write cycle and data out pin will remain open circuit * (high impedance) through the entire cycle; If trwp2 trwp(min.), tcwp 2 tewp(min.) tawp2 tawp(min.) and tcpyp2 tcpyp(min.) (Fast Page Mode), the cycle is a read~modify- write cycle and data out will contain data read from the selected cell: . If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. Operation within the tpcp(max.) limit insures that trac(max.) can be met. . trcp(max.) is specified as a reference point only: If trop is greater than the specified trcp(max.) limit, then access time is controlled by teac- 16. Operation within the trap(max.) limit insures that trac(max.) can be met. tnap(max.) is specified as a reference point only: If tap is greater than the specified tpan(max.) limit, then access time is controlled by tags A-30

TC514100JL/ZL—80 TC514100JUL/ZL-10 . a Come | ae | | trac ke | OFF 2 "HY or "LI"

TC514100JL/ZL—80 TC514100JL/ZL—10 . WRITE CYCLE (EARLY WRITE) we a — =—— ae wer{ [| oy TMNT MT : 2 "H" or "LN

TC514100JL/ZL—80 TC514100JL/ZL—10 - a tASR aay case | [Lowe tal | torr . snc |__| ZA: "Ht or "LY

TC514100JL/ZL—80 TC514100JL/ZL—10 : we YIE— TRASP 0 OO Pe! von TDK 2 KD ee WOM con = IM com » NIL traD sna | ' RRH | tres tRcg “RCH “pes tRCH | tal _| ita ‘cuz OFF bs ‘OFF i ‘OFF . : "A" or "L" A-34

TC514100JL/ZL—80 TC514100JL/ZL—10 - me — ae = “4 aH Yin— L | iw WaTTE "Teele SM, Wee), xe), a . 2 "H" or "L"

TC514100JL/ZL—80 TC514100JUL/ZL-—10 : FAST PAGE MODE READ-MONIFY-WRITE CYCLE — Wu tRASP MS wn fr ™—“COCOCOCCSC(CNCNC#Cd Lee wow St TIN == MiKo pee) Op = XIII “aH JE nw T= || vows F feue - ‘CAC tal _| taal _| = cor oe OE) RE) fort” fon e . : "H" or "L" A-36

mT | a,

TC514100JL/ZL—80 TC514100JL/ZL—10 ; | tore NOTE: AQ~\\A10="H" or “LM 2 "HM or "L"

TC514100JL/ZL—80 TC514100JL/ZL—-10 — HIDDEN REFRESH CYCLE (READ) taal | _ trac ‘OFF . : "H" or "LY

TC514100JL/ZL—80 TC514100JL/ZL—10 : HIDDEN REFRESH CYCLE (WRITE, ire oy TED ) Za: "H" or "L"

TC514100JL/ZL—80 TC514100JL/ZL—10 ~ mye = a READ CYCLE [ [ft | [|| torr Dout Yo. — r_ | a | vu | | Za: "RY or "LM ‘DS ‘pH A-41

TC514100JL/ZL—80 TC514100JL/ZL—10 , = 8 Lymm NOTE: Dyyy AOVALO: "A" or "L" 2 "H" or "L"

a |_| woe LDA MOK 28 KOT ne — ) | trac ay tor I: "8" ot "L" ,

TC514100JL/ZL—80 TC514100JL/ZL—10 , [tmp | ta | roma TDR" SR LLL | tom, _ | a | LT few ter] [| | Vin — > — , @: 'H" or "Lu"

TC514100JL/ZL—80 TC514100JL/ZL—10 — FAST PAGE MODE READ CYCLE IN THE TEST MODE mE Vin — tRASP | ee tne. 7 top. =A | tasr | Ran, tasc tcan | tasc Lc vonaso TDA 0 WO KO 2 KO 2» MITT *RAD tRcH | | It RRA ee tres, snes RCE rF wes trou 1 wml | iia tRAC | p p | t tori bs [torr i= torr ZZ: "H" or "L" A-45

TC514100JUL/ZL—80 TC514100JL/ZL—10 : FAST PAGE MODE WRITE CYCLE (EARLY WRITE) IN TEH TEST MODE ve a tAR na | sous 8 “TI sow HOM exe» WOK eo = KO con » | arene re me a aa A ox ee . A: "EH" or "LY" A-46

TC514100JL/ZL-—80 TC514100JL/ZL-10 - TEST MODE The TC514100J/z is the RAM organized 4,194,304 words by 1 bit, it is internally organized 524,288 words by 8 bits. In "Test Mode", data are written into 8 sectors in parallel and retrieved the same way. AlOR, AlOC and AOC are not used. If, upon read~ ing, all bits are equal (all "1"s or "O"s), the data output pin indicates a "1", If any of the bits differed, the data output pin would indicate a "O", Fig. 1 shows the block diagram of TC514100J/Z. In "Test Mode", the 4M DRAM can be tested as if it were a 512K DRAM. “WRITE, CAS Before RAS Refresh Cycle" puts the device into "Test Mode". And “CAS Before RAS Refresh Cycle" or "RAS Only Refresh Cycle" puts it back into "Normal Mode". In the Test Mode, "WRITE, CAS Before RAS Refresh Cycle" performs the refresh operation with the internal refresh address counter. The "Test Mode" function reduces test times (1/8 in case of N test pattern). A-47

TC514100JL/ZL—-80 TC514100JL/ZL—10 _TOSIAIOONE 10 BLOCK DIAGRAM IN THE TEST MODE Yoo Aior,Aioc, 4c A1or,A1 0c Aoc A ° | Normal fee Te ‘a exe ILD el ; > ee I | El eel Loe alll a —— vm Atoc Adc. Fig. 1 A-48