TC514100AP-80 | DigiCamel IC Datasheet

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TC514100AP TOSHIBA | Alldatasheet

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Technical content

fe ptt t pee op See ee ie pate (Us Bes SR i 4,194,304 WORD x 1 BIT DYNAMIC RAM —*_—‘This_ is advanced information and specifica- tions are subject to change without notice.

DESCRIPTION

‘The TCS1410VAP/AJ/ASJ/AZ is the new generation dynamie RAM organized 4,194,304 words by 1 bit. The TC514100APVAJ/ASJ/AZ utilizes TOSHIBA’s CMOS Silicon gate process technology as well as advanced circuit techniques to provide wide operating margins, both internally and to the system user. Multiplexed address inputs permit the TC514"00AP/AJ/ASJ/AZ to be packaged in a standard 18 pin plastic DIP, 26/20 pin plastic SOJ (300/350mil} and 20 pin plastic ZIP. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. System oriented features include single power supply of 5V+10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL.

FEATURES

4,194,304 word by Ibit organization © Low Power * Fast access time and cycle time 660mW MAX. Operating |S ATOOAPIATASTIAZ — 60 (TC514100AP/AJ/ASJ/AZ — 60) taac BAS Access Time 6ans 5.5mW MAX. Standby ; Le Calamin Aaaias © Outputs unlatched at cycle end allows two- Access Time 3ons dimensional chip selection (actA Aces Te [20m] * Common WO capability using “EARLY SS Made = © Read-Modify-Write, CAS before RAS refresh, Mode and Test Mode capability © Single power supply of 5V+10% ‘ ‘ . with a builtin Vu generator ® All inputs and outputs TTL compatible © 1024 refresh cycles/I6ms © Package 'TC514100AP__: DIP18-P-300E EIN. NAMES TC514100AJ_—: SOJ26-P-350 O=AIGAddress Inputs | WRITE [Readrwrite input _| TC514100ASJ : S0J26-P-300A _RAS_[Row Address Sobe | Vec TC514100AZ _; ZIP20-P-400A Diy [Data in Tvss_[Ground Dour [Data Oui NC [No Connection [cas “Jcotumn Adures Strobe] [| PIN CONNECTION (TOP VIEW) BLOCK DIAGRAM WRITE o Plastic O1F Plastic 501 Plastic 21° mo LD ° Om : ee = purren Smif ~Tahvss otf ae hivys SLE oe Aide tstas NCR DNC Dafa oe BUFFER wots iapas A105 Alaa” geet y | WRITE coumn | | ars 13Be? sod ashas weiss BA no oop ay Sous cout argy 12Ha6 aigio far “CP2 folnc. At o-| BUFFERS (11D rej_DECODER aide thas Ads tebe aol 3 a7 o-| q Pe a8 OF] ij BS} icze | Atear Ag O| ROW FITTAI= ot i wo Lo]. Fr os [Lae | mae ES is A-49

Input Vortage [vw Peer Pv Output Voltage [vor | ser Pv Power Supply Voltage [ve [ser [ov Operating Temperature [tom [oe [oe Tt Storage Temperaiure [tro | =ssso [oe Tt Soldering Temperature Time | tsouver | 260-10 | verse |_| [rower owspaton | | md] Sm Tid [snore Grew Output cures | tow | Sd mm Pd RECOMMENDED OC OPERATING CONDITIONS (Ta = 0~70°C) | vec__[Supaiyvortge | as | so =| ss | CYC | vu [input high vorase |e | - (| os |v | 2 Input Low Voltoge a | A-50

DC ELECTRICAL CHARACTERISTICS (Vcc =5V + 10%, Ta =0~70°c) SYMBOL PARAMETER UNITS } NOTES \\ ornare ee Operating ¢ TC5S14100AP/AM/ 120 A 3,4 lect verage Power Supply Operating Current - m (RAS, TAS, Address Cycling: tac= tac MIN. ) ASUAZ-60 5 STANDBY CURRENT lec2__| Power Supply Standby Current 2 | ma {RAS = TAS = Vin) RAS ONLY REFRESH CURRENT Tes14100ap/ay lees Average Power Supply Current, RAS Only Mode ASAZ-60 3.5 (RAS Cycling, TAS = Vin: tre= tac MIN. ) " ; fast Pace woe cuRnewt «tan page mes 1¢514108/A,/ was leca verage Power Supply Current, Fast Page Mode m, AS 2 (RAS = Vy, TAS, Address Cycling: tec= tec MIN, ) 'SUAZ-60 5 STANDBY CURRENT | Ices _| Power Supply Standby Current mA | (RAS = CAS = Vcc - 0.2V) } ee GHS BEFORE RAS REFRESH CURRENT ; scsis100arvaut ie lece | Average Power Supply Current, CAS Before RAS /ASiAz-60 bie Mode (RAS, CAS Cycling: tac= tac MIN. } Az INPUT LEAKAGE CURRENT (any input except TF) Input Leakage Current, any input pA {OVS Vin $6.5V, All Other Pins Not Under Test = OV) QUTPUT LEAKAGE CURRENT tow te dic pA (Dour is disabled, OVS VoyrS 5.5V) OUTPUT LEVEL Vou “ye 24 Output “H” Level Voltage (lour= -SmA) y OUTPUT LEVEL % | Output “L" Level Voltage (lour = 4.2mA) A-51

ELECTRICAL CHARACTGERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) SYMBOL PARAMETER: UNITS) NOTES: ae [ewe [wate command ruse wis | ve fT | [in| witeConmand wo wedfine Sd] | [tom | wate commend to Stead vime | fs | [ios [owoseruptme Ee Ts [tow [oaroatine | ts J [wer | Retemeerod | Tt Ts | [ace | Wite Conmand secvp Tine SS WATE owytine Sid [nwo [RAS to WATE Osay time | | fw a [tawo, | column addres to WATE oeay Time | go | = tw 8 [nat [SH recharge OWRTE vey Tne Siw ff TAS Set-Up Time a (CAS before RAS Cycle) ee TAS Hold Time a ‘on (CAS before RAS Cycle) ® | - [lt | nH [invc [RAS to CAS Precharge Time | | ts | TES Precharge Time (CAS before RAS Counter Test ter ns Cycle) Write Command Set-Up Time (Test Mode In} t Write Command Hold Time wt | (Test Mode In) t WRITE to RAS Precharge Time Wh _| (CAS before RAS Cycle) WRITE to RAS Hold Time twrn . (CAS before RAS Cycle) A-53

ELECTRICAL CHARACTGERISTICS AND RECOMMENDED AC OPERATING CONDITIONS IN ELECTRICAL CHARACTGERISTICS AND RECOMMENDED AC OPERATING CONDITIONS IN THE TEST MODE (Vec = 5V + 10%, Ta = 0~70°C) (Notes 6, 7, 8) SYMBOL PARAMETER UNIT] NOTES a | even aa wine Gee Tne aw Sac Access Time from RAS Fo. | os [afar] a er [is | cen Tie tom coun ares Pas fo | [ion | Ace Tine ton OE madwge SP wf Lun [snigime a mice | RAS Hold Time from GRE Prechorge fos Pape Moa) [as | a PO | [ios | OS rake wees | | CAPACITANCE (Vcc = 5V + 10%, f = 1MHz, Ta= 0~70°C) a [a ras Gontaneto=aio og) Ga ey) Co | oviput Capacitanceo) TCC Cd A-54

NOTES: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. 2, All voltages are referenced to Vgs. 3. Icci, Ieca, Icc4, Icce depend on cycle rate. 4. Icc1, Icca depend on output loading. Specified values are obtained with the output open. 5. Column address can be changed once or less While RAS= Viz, and CAS=Vin. 6. An initial pause of 200ps is required after power-up followed by 8 RAS only refresh cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 TAS before RAS refresh cycles instead of 8 RAS only refresh cycles are required. 7. AC measurements assume tr=5ns. 8. Vin (min.) and Vy, (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between Vjy and VIL. 9. Measured with a load equivalent to 2 TTL loads and 100pF. 10. torr (max.) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 11. Either trci or trr must be satisfied for a read cycle. 12. These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in Read-Modify-Write cycles. 13. twes, trwp, town, tawp and tcpwp are not restrictive operating parameters. ‘They are included in the data sheet as electrical characteristics only. If twos2twcs(min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) throughout the entire cycle; If trwp2 trwp Gnin.), tewo2 town (min.), tawp2 tawp (min.) and topwo= tcpwp (min.) (Fast Page Mode), the cycle is a Read-Modify-Write cycle and the data out will contain data read from the selected cell: If neither of the above sets of conditions is satisfied, the condition of the data out {at access time) is indeterminate. 14. Operation within the trop (max.) limit insures that trac (max.) can be met. tcp (max.) is specified as a reference point only: If trcp is greater than the specified trop (max.) limit, then access time is controlled by tcac. . 15, Operation within the trap (max.) limit insures that trac (max.)can be met. trap (max.) is specified as a reference point only: If trap is greater than the specified tran (max.) limit, then access time is controlled by tan. A-55

TC514100AP/AJ/ASJ/AZ-60 : thar jie |Lorg |

TC514100AP/AJ/ASJ/AZ-60 — gt ZA on":

TC514100AP/AJ/ASJ/AZ-60 . ol ar] wane

TC514100AP/AJ/ASJ/AZ-60 . FAST PAGE MODE WRITE CYCLE (EARLY WRITE; pA AS A tase. A E GAH AA: *w on “u" A-60

FAST PAGE MODE READ-MODIFY.WRITE CYCLE ah ell ae Om =e Ooms :

TC514100AP/AJ/ASJ/AZ-60 ; orem W Por a a | OPEN gee __.

om “QU COTZIIII. Note: AO~A10= “H" or “L” 2 oe u :

TC514100AP/AJ/ASJ/AZ-60 . ZA oe

TC514100AP/AJ/ASJ/AZ-6O _ HIDDEN REFRESH CYCLE (WRITE wn SS Dour Vou "ao OPEN

TC514100AP/AJ/ASJ/AZ-60 . ts —I| | WRTECYELE "He ont"

WRITE, CAS BEFORE RAS REFRESH CYCLE won "a Le Note: Djy, AO~A10= “H" or “L” Aen :

ee SSSSSSSSSSSSSSSSSsssesee TEST MODE The TC5I4100AP/AJ/ASJ/AZ is the RAM organized 4,194,304 words by 1 bits, it is internally organized 524,288 words by 8 bits. In “Test Mode”, data are written into 8 sectors in parallel and retrieved the same way. Ajor, Aioc and Aoc are not used. If, upon reading, all bits equal (all “1"s or “O"s), the data output pin indicates a“1”. If any of the bits differed, the data output pin would indicate a“0”. Fig.1 shows the block diagram of TC514100AP/AJ/ASJ/AZ. In “Test Mode”, the 4M DRAM can be tested as if it were a512K DRAM. “WRITE, TAS Before RAS Refresh Cycle” puts the device into “Test Mode”, And “CAS Before RAS Refresh Cycle” or “RAS Only Refresh Cycle” puts it back into “Normal Mode”. In the Test Mode, “WRITE, TAS Before RAS Refresh Cycle” performs the refresh operation with the internal refresh address counter. The “Test Mode” function reduces test times (1/8 in case of N test pattern), A-68

TC514100AP/AJ/ASJ/AZ-60 | BLOCK DIAGRAM _IN THE TEST MODE 22k (ica I wormel || Rae Ae Be [sata }e ir Lcmomndlf| lee aces ior Atoc: Aoc [ern Fig. 1 A-69

Product Information

TC514100AP-80 specifications and overview.

Summary

4,194,304 WORD x BIT DYNAMIC RAM

Description

4,194,304 WORD x BIT DYNAMIC RAM

Source title TC514100AP-80 Datasheet(PDF) - Toshiba Semiconductor

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