TC511664BJ

TC511664B TOSHIBA | Alldatasheet

Document overview

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Technical content

65,536 WORD x 16 BIT DYNAMIC RAM

DESCRIPTION

The TC511664BJ/BZ is the new generation dynamic RAM organized 65,536 words by 16 bits. The "TC511664BJ/BZ utilizes TOSHIBA's CMOS Silicon gate process technology as well as advanced circuit techniques to provide wide operating margins, both internally and to the system user. Multiplexed address inputs permit the TC511664BJ/BZ to be packaged in a standard 40 pin plastic SOJ and 40 pin plastic ZIP, The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. System oriented features include single power supply of 5V+10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL,

FEATURES

© 65,536 word by 16 bit organization @ Single power supply of 5V+10% with a built © Fast access time and cycle time in Vpp generator [—Fresirecenz—eoia] * Lew Fewer 633mW MAX. Operating (TC511664BJ/BZ—80) [tac [RAS Access Time #0ns [100s | 495m MAX. Operating (TC511664BJ/BZ—10) [ian [Column Acdress Access Time | 45ns_ | Sns_| 5,5mW MAX. Standby licac [AS Aceu Time | 30 | 35ns | Outputs unlatched at cycle end allows two- Smansional chip selesiton EAS refresh 4 [tec [Fast Page Mode cycle Time _| | s5ns_] SS only vaireeh fre Write y ioc [Fast Page Mode Cycle Time | sins | 65s RAS-only refresh, Hidden refresh, Byte-Write F and Fast Page Mode capability E © All inputs and outputs TTL compatible @ 256 refresh cycles/4ms @ Package 1C511664BJ:SOJ40-P-400 TC511664BZ:Z1P40 —P—475 PIN CONNECTION (TOP VIEW) PIN NAMES i ‘i [sywsou Tame — sol Plastic ZIP boa (address Inputs | mh Bp wou won He fy on Read/Upper Byte Write tos U6 as) vor wore fs} $21 °° Input Se 3p wore vor FR EG] wor Read/lower Byte Write the 3H Ne wie ee nowt ‘“e a ah a wos [TE tor [OE [output Enable X the 3D ne ~ fe Hy [vss [Ground a fn xe ate is [xc |Nocennecion | Ste bh M a B aa Tho np as we fe EB Ye a fe HS NeW oe ah Ho A-401

TC511664BJ/BZ-80, TC511664BJ/BZ-10 BLOCK DIAGRAM oo 8'0'8'0 8'0 8’0 80 8'0 80 80 pe — m° FD | on ea AppRess | [CODER BUFFER (8) rf : ARO as AGO ROW F 2 — i oo NB, Fol | Te JJ * NO.1 CLOCK me A-402

TC511664BJ/BZ-80, TC511664BJ/BZ-10 a ABSOLUTE MAXIMUM RATINGS Se [rower Disipation [Pp | 700 «| mw [ shore Cirevit Outpat Curent | tos 1 0 | ma RECOMMENDED DC OPERATING CONDITIONS (Ta =0~70°c) [sawor [ramen am [ov max [own [nore | [veo Tinput High Voltage ke | sv 2 DC ELECTRICAL CHARACTERISTICS (Vcc = 5V+ 10%, Ta=0~70°c) [woo] —anameren— mans | ma | ur wore | GrenaTiNg CuARENT Peanecmare| - |e | eee a FL BRR Spey cor RAS ONLY REFRESH CURRENT [resiresapyazeo] - | 115 | = | Freese Herod a fSreanee[ pay | 3 | FAST PAGE MODE CURRENT [resiveseameze0| - | 70 | = | eR BL Cura Fs age age fSamamee[ pe] ™ || STANDBY core cu tes | Faye ae Se cet TAS saFonE MAS nEFRETN CON [resireeuae| [18 | mA 3 | [Extteraeeamrccmjeuttes reneane |< w] eur LEAKAGE CURRENT [ow [Sanam te tm | ou’ a ae [vox [SUM vouatnezim SL | YT | A-403

TC511664BJ/BZ-80, TC511664BJ/BZ-10 a ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Vcc =5V + 10%, Ta =0~70°c)(Notes 6, 7, 8) [exc | Random Read or write CyleTime 35 | | wo | = Tis [| [tnnew | Read-Modifywrite Cycle Time | wo | | eas | | ns || [xc [Fast Page Move cietime ts | | os | Tl | | [ tonany | Fast Page Mode Read-Modify-write Cycle Time | soo | =| a0 | | ns || [tac | Access Time fromRaS | | go | 100 ns |o.tas | [tcac | AccessTime tomes | | 0] = fas | ns [ote | | tan | Access Time from Column Address | = | as | = | 5s | ns Jos | [icon [Access Time from TAS Precharge | | so ~ | cos [| liz [Sto oupintowz to | fo [ K- fo | [tore | Output autter Tumrott ey ——SSSSSC*dT (| fo | | fo | [er | Transvon Time (nse ang rat) S| | sof 3 | | fe | [tmp [RAS Precharge Time ts | = Of wo f= lr || [tus [RAS pute wien 80 | 10,000 | 100 | 10,000 | rs | | [tase | FAS Pulse wistn (Fastagewod) | €0 | 100.00 | 100 | ooo0o | m |_| [ee [WB HolsTime Ta | = Pls | Tr || [cm [SH time co | too | i | [teas [CAS Pulse ween 30 | 10.000 | as | 10.000 [ons [| | taco [RAS to AS Delay time. | co | so | co | sis [ts | | trap | RAS to Column Address Delay Time | ts | as | ts | as | ons [ts | [car [CAS to WAS Precharge Time Ct | Ls | - Tos | | [to [CS Prechargetime To | CP tT fl | | [tase | Row Address SevupTime TE | | oh | = fo | [uss | Row Agsres Hold Time SSC vo | = to | - tm] | [use | cotumn adaren setuptine SSCs oh | = fo | = tm] _| [team | Column Address Hold time ts | Ls | to || [tax__| Column Address Hold Time referenced toMAS | ss | - | os | - || | [tr | Column Address to RAS lead Time | as | | os | | os | | [iacs [Read Command seuptime | | - fo | - [io | | [ txcx [Read Command Hold Time] | = | | Tl [| [sam [Read Command Hold Time referencedtoM@S | 0 | | o | - | |u| [twon | Write Command Hold Time ts | Ls | To | | [wer [write Command Hold Time referenced oS 8s | - | | - [om | | [tw [write Command Pulse with | ts | OP ts | oT os | | [rm [Write Command to WAS tead time | wo | - | 2 | - [ow | | [tom [write Command to TAF ead time | 0 | — | | - || | [to [oseseeuptine io | = fo | Pm fe | [toc [oatenos tine | Ps | Pe | A-404

TC511664BJ/BZ-80, TC511664BJ/BZ-10 a ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) suet nie [rns [wae | ns | ae _| loa lo tod iments ms Ts | - Po [= Po | liar [aeamreica CT | HT rT [incr Lwrte commana seurtine To | fo [ = fos ts a a [ewe [aE t0 WE OeayTine SSSSCSC~ ro | tof = Ps fs [tenn] CAS recharge to WE Deny Tine (ran Page Mos) | 70 | - [oo | = Tos fa | [aap [column Adesso WE Delaytine | os | | os | Po [| Tign [eHS setup Time before MS Gaay | s | - | s | - Tot | [iene [CAS Hols Tine CAS before Gey | | - Lot - Tot | [ase [Sto CAS recharge ting CT | To | = tr fT [ror eas Precharge Time CAE before MS Counter Tene | wo | — [ao | = [os | - [aon [RSMo TimereteencedtwooE | | To | = Pow P| 1 liom [otacmtine SS SSCi | os TN TP [8 | lie [OF te ow vey SSSSCSC~d to | - Po [| PT 4 [tote Oviput Butter Turn OF Demy Time fomoe | o | wo | o { 2 [im | wo | ° licte [OE command voting TO | | oo | Po | [toon ovpuroisabiesetuptime SST | - to | Post | [icy [Masted waite setup tine To | — 1 oo | = to || [ms | Masked Write Hold tine Retereneadto S| o | - fo | - [at | [ic [Masked Write Hold time Referenced oS 0 | - | ol - [ul] | CAPACITANCE (Voc = 5V + 10%, f= MHz, Ta = 0~70°C) a [e _| mt capacance omar, WS, cas, ow.ow. oH] | 7 |_| [eo Tinpuvourout copactancewormvor [= | Tt | A-405

TC511664BJ/BZ-80, TC511664BJ/BZ-10 NOTES: 1, Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. 2, All voltages are referenced to Vss. 3. Icci, Iecs, Ieca, Iecs depend on cycle rate. 4. cca, Ica depend om output loading. Specified values are obtained with the outputs open. 5. Column Address can be changed once or less while RAS=Vy, and CAS=Vin. 6. An initial pause of 200ps is required after power-up followed by 8 RAS only refresh cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 TAS before RAS refresh cycles instead of 8 RAS only refresh cycles are required. 7, AC measurements assume tr=5ns. 8 Vin (min,)and Viz (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between Vi and Vit. 9. Measured with a load equivalent to 1 TTL load and 50pF, 10. torr (max.) and togz (max.) define the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. 11, Either trci or taru must be satisfied for a read cycle. 12, These parameters are referenced to CAS leading edge in early write cycles and to UW, LW leading edge in read-modify-write cycles. 13. twes, trwo, towD, tawp and tcpwp are not restrictive operating parameters, They are included in the data sheet as electrical characteristics only. If twos®twcs(min.) the cycle is an early write cycle and data out pins will remain open circuit (high impedance) through the entire cycle; If trw2 trwo (min.), towo® town (min.), tawp2 tawp (min.) and tcpwo2 tcpwo (min.), the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell: If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate, 14, Operation within the tcp (max,) limit insures that trac(max.)can be met. tacp (max.) is specified as a reference point only: If trcp is greater than the specified tncp (max.) limit, then access time is controlled by tcac. as a reference point only: If trap is greater than the specified tap (max.) limit, then access time is controlled by taa. A-406

TC511664BJ/BZ-80, TC511664BJ/BZ-10 READ CYCLE we ho a er La 7 Lea | eg ea || Te es wo AE ae

TC511664BJ/BZ-80, TC511664BJ/BZ-10 WRITE CYCLE (EARLY WRITE) tec ms —— ee va — SL en «Clann ea Val | oT i Noy [ta | tT vu —-GF yin Wy, a YY a ci | Ete va — SS SS ee ——— Note: Doyr= OPEN B:-w oe A-408 )

1C511664BJ/BZ-80, TC511664BJ/BZ-10 UPPER BYTE WRITE CYCLE (EARLY WRITE) tac a a rr en Ny IT | ee [Ba TT I Note: Doyr= OPEN Zhe oe A-409

TC511664BJ/BZ-80, TC511664BJ/BZ-10 LOWER BYTE WRITE CYCLE (EARLY WRITE) tee ws v i a ‘a — rR a ree Ww —-wy bp YY P \\ —GYfffVyi yyy WY. foe [tone Note: Doyrs OPEN Bi cw ov A-410

TC511664BJ/BZ-80, TC511664BJ/BZ-10 WRITE CYCLE (OE CONTROLLED WRITE; ac «eo . ee a == —, [tw JT Le YYW “ op YY. _—— ZEEE, EEE —QGOWWW ih, — a YOO. Note: Dour= OPEN Bev ot A411

TC511664BJ/BZ-80, TC511664BJ/BZ-10 UPPER BYTE WRITE CYCLE OF CONTROLLED WRITE) a oT .. NEY a tMcK tons. tots See ae YT. yy, yy toeo Os ton Note: Dour # OPEN Bait oe A412

7TC511664BJ/BZ-80, TC511664BJ/BZ-10 Ee. e_LpE_LLS LOWER BYTE WRITE CYCLE (OE CONTROLLED WRITE) tre wu — [| ms ———S i = <2o/yt NIELS ten. oe a a | he ‘“ —YYYYYY QT woul [fs ‘" —Qyyynwr YY YYYZIlIC=Z$JW WV ~ Ya — y yy toro, Note: Dour OPEN Bw oe A-413

TC511664BJ/BZ-80, TC511664BJ/BZ-10 READ-MODIFY-WRITE CYCLE eo OR wT ——-, ZA on A414

TC511664BJ/BZ-80, TC511664BJ/BZ-10 me = = | ws, 4 aN NE ° von a PY: | Vo. — [| 7 in . Zire oe

TC511664BJ/BZ-80, TC511664BJ/BZ-10 READ-MODIFY-LOWER-BYTE-WRITE CYCLE cas =r WV 7 aig ce TT fo | ia T———— ontn eS A-416 |

TC511664BJ/BZ-80, TC511664BJ/BZ-10 FAST PAGE MODE READ CYCLE on See 0G 8; 22 taRH “Tw JE Eg mI yl | A417

TC511664BJ/BZ-80, TC511664BJ/BZ-10 FAST PAGE MODE WRITE CYCLE (EARLY WRITE) =D vee => = oF lie TX _t Half | sll | pot ~ 9 0 a i ee [T tom "| [T ton | ie Nou: Dour OPEN ZA ore AAIB

TC511664BJ/BZ-80, TC511664BJ/BZ-10 FAST PAGE MODE UPPER BYTE WRITE CYCLE (EARLY WRITE) re gic a a a a a scbeltel) elle, | mt | mo! Diet =< = en = ae Ct al geal pe vos~ Vm yy ae pth omy Note: Dour# OPEN Ds on A-419

TC511664BJ/BZ-80, TC511664BJ/BZ-10 FAST PAGE MODE LOWER BYTE WRITE CYCLE (EARLY WRITE) “ “) ind paamaa sit ws tee A-420

TC511664BJ/BZ-80, TC511664BJ/BZ-10 FAST PAGE MODE READ-MODIFY-WRITE CYCLE So fe 4 a n2 = —e ae A ww \\ Heil EE 9 EE rah er eal to w nes i ie Van a a | ° TI iL . Set ape are = (}-_{} A-421

TC511664BJ/BZ-80, TC511664BJ/BZ-10 FAST PAGE MODE READ-MODIFY-UPPER-BYTE-WRITE CYCLE mo es sn a wo (ei ED TE ATT | eo cama) i Dl See ae va — , Ks pe A-422

TC511664BJ/BZ-80, TC511664BJ/BZ-10 FAST PAGE MODE READ-MODIFY-LOWER-BYTE-WRITE CYCLE we Se = = oh mr ings mr ne in we —— ei iM pa ret cp TESCO TROT a A-423

TC511664BJ/BZ-80, TC511664BJ/BZ-10 RAS ONLY REFRESH CYCLE a | * wo \\/ R} | TRaH Note: Din, UW, LW, OE=H* or “L \\Z TAS BEFORE RAS REFRESH CYCLE tac aS “u — ae tour Note: Din, UW, LW, DE, AO~A7=“H" or “L" \\Z A424

TC511664BJ/BZ-80, TC511664BJ/BZ-10 HIDDEN REFRESH CYCLE (READ) mw HT ol = Loy MJ nw Pot = ID —QGW — - CY. YYYLYUUUuwwy “yy Note; Diy= OPEN QB: “# ou A-425 )

TC511664BJ/BZ-80, TC511664BJ/BZ-10 aoe eX ow > co

TC511664BJ/BZ-80, TC511664BJ/BZ-10 vu [| ss —] fom » 27h

TC511664BJ/BZ-80, TC511664BJ/BZ-10 son svn cxun owen nem wn wt —.——- mw * DOG oe « WCW. A-428

TC511664BJ/BZ-80, TC511664BJ/BZ-10 CAS BEFORE RAS REFRESH COUNTER TEST READ CYCLE _ ws aT : == Note: Da = OPEN 7 A-429

TC511664BJ/BZ-80, TC511664BJ/BZ-10 oer +) * ee

7TC511664BJ/BZ-80, TC511664BJ/BZ-10 TAS BEFORE RAS. REFRESH COUNTER. TEST. READ-MODIFY-WRITE CYCLE wT 4 vor F orn oS, B: “HE of “LY

TC511664BJ/BZ-80, TC511664BJ/BZ-10

APPLICATION INFORMATION

‘The 16 address bits required to decode 1 of the 65,536 cell locations within the TC511664BJ/BZ are multiplexed onto the 8 address inputs and latched into the on-chip address latches by externally applying two negative going TTL-level clocks. ‘The first clock, the Row address Strobe (RAS), latches the 8 row address bits into the chip, The second clock, the Column Address Strobe (CAS), subsequently latches the 8 column address bits into the chip. Each of these signals, RAS and CAS triggers a sequence of events which are controlled by different delayed internal clocks, ‘The two clock chains are linked together logically in such a way that the address multiplexing operation is done outside of the critical path timing sequence for read data access. The later events in the TAS clock sequence are inhibited until the occurrence of a delayed signal derived from the RAS clock chain. The “gated CAS” feature allows the CAS clock to be externally activated as soon as the Row Address Hold Time specification (tran) has been satisfied and the address inputs have been changed from Row address to Column address information. Data Inputs ‘A write cycle is performed by bringing UW and LW low during the RAS/CAS operation. The falling edge of TAS or LW strobes data on /O1~I/08 into the on-chip data latch. And the falling edge of TAS or UW strobes data on /O9~1V/O16 into the on-chip data latch. In an early write cycle, LW and UW are brought low prior to TAS and the data is strobed in by CAS with setup and hold times referenced to this signal. In derayed write or read modify write cycle, TAS will already be low, thus the data will be strobed in by LW and UW with setup and hold times referenced to these signals. In derayed or read modify write, OE must be high to bring the output buffers to high inpedance prior to impressing data on the I/O lines. Data Outputs ‘The three-state output buffers provide direct TTL compatibility with a fan-out of a standard TTL load, Data-out is the same polarity as data-in, The outputs are in the high-impedance state until TAS is brought low. In a read cycle the outputs go active after the access time interval trac and tozA are satisfied. ‘The outputs become valid after the access time has elapsed and remains valid while CAS and OF are low. TAS or OE going high returns it to a high impedance state. In an early-write cycle, the outputs are always in the high-impedance state. In a delayed-write or read-modify-write cycle, the outputs will follow the sequence for the read cycle. ‘The OE controls the impedance of the output buffers. In the logic high position the buffers will remain in ahigh impedance state. When the OE input is brought to a logical low level, the output buffers are enabled. Both CAS and DE can control the outputs. Thus in a read operation, either OB or CAS returning high forces the outputs into the high impedance state. A-432

TC511664BJ/BZ-80, TC511664BJ/BZ-10 RAS ONLY REFRESH Refresh of the dynamic cell matrix is accomplished by performing a memory cycle at each of the 256 row addresses (A0~A7) within each 4 millisecond time interval. Although any normal memory cycle will perform the refresh operation, this function is most easily accomplished with “RAS-only” cycles, RAS only refresh results in a substantial reduction in operating power. This reduction in power is reflected in the I¢c3 specification. BEFORE RAS REFRESH TAS before RAS refreshing available on the TC511664BJ/BZ offers an alternate refresh method. If TAS is held on low for the specified period (tcsp) before RAS goes to low, on chip refresh control clock generations and the refresh address counter are enabled, and an internal refresh operation takes place. After the refresh operation is performed, the refresh address counter is automatically incremented in preparation for the next CAS before RAS refresh operation. FAST PAGE MODE . The “Fast Page Mode” feature of the TC511664BJ/BZ allows for successive memory operations at ed multiple column locations of the same row address with increased speed without an increase in power. Be This is done by strobing the row address into the chip and maintaining the RAS signal at a logic 0 ee throughout all successive memory cycles in which the row address is common. This “Fast page Mode” of operation will not dissipate the power associated with the negative going edge of RAS. Also, the time required for strobing in a new address is eliminated, thereby decreasing the access and cycle times. HIDDEN REFRESH An optional feature of the TC511664BJ/BZ is that refresh cycles may be performed while maintaining valid data at the output pins. This is referred to as Hidden Refresh. Hidden Refresh is performed by holding CAS at Vit and taking RAS high and after a specified precharge period (tap), executing a CAS before RAS refresh cycle. (see Figure below) MEMORY CYCLE REFRESH CYCLE REFRESH CYCLE . SVS \\_S | This feature allows a refresh cycle to be “Hidden” among data cycles without affecting the data availability. A-433

TC511664BJ/BZ-80, TC511664BJ/BZ-10 RE REFRESH. ST ‘The internal refresh operation of TC511664BJ/BZ can be tested by “OAS BEFORE RAS REFRESH COUNTER TEST”. This cycle performs READ/WRITE operation taking the internal counter address as row address and the input address as column address, ‘The test is performed aftera minimum of 8 CAS before RAS cycles as initialization cycles. The test procedure is as follows. ® Write “0” into all the memory cells at normal write mode. ® Select one certain column address and read “0” out and write “I” in each cell by performing “CAS BEFORE RAS REFRESH COUNTER TEST (READ-MODIFY-WRITE CYCLE)”. Repeat this operation 256 times. @® Check “1” out of 256 bits at normal read mode, which was written at @. @® Using the same column as ®, read “1” out and write “0” in each cell performing “CAS BEFORE RAS REFRESH COUNTER TEST”, Repeat this operation 266 times. © Check “0” out of 256 bits at normal read mode, which was written at ©. ® Perform the above @ to © to the complement data. A-434