TC511001P-12

TC511001P TOSHIBA | Alldatasheet

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1,048, 576woRox1 BIT DYNAMICRAM — TC511001P/J/Z-85, TC511001P/J/Z-10 SILICON GATE CMOS TC511001P/J/Z-12 The TC511001P/J/Z is the new generation dynamic _and is compatible with widely available automated testing RAM organized 1,048,576 words by 1 bit. The and insertion equipment. System oriented features TC511001P/J/Z utilizes TOSHIBA’s CMOS Silicon gate _ include single power supply of 5V + 10% tolerance, process technology as well as advanced circuit techniques direct interfacing capability with high performance logic to provide wide operating margins, both internally and _ families such as Schottky TTL. The special feature of to the system user. Multiplexed address inputs permit the TC511001P/J/Z is nibble mode, allowing the user to TC511001P/J/Z to be packaged in a standard 18 pin serially access 4 bits of data at a high data rate. “Test plastic DIP, 26/20 pin plastic SOJ and 20/19 pin plastic Mode"” function is implemented from Revision C. ZIP. The package size provides high system bit densities @ 1,048,576 word by 1 bit organization @ Low Power: © Fast access time and cycle time 385mW MAX. Operating (TC511001P/J/Z-86) — = 330mW MAX. Operating (TC511001P/J/Z-10) EK ee 275mW MAX. Operating (TC511001P/J/Z-12) trac __RAS Access Time Sine 100ns __120ns 5.5mW MAX. Standby tan Solumn Address Access |” yong Gone Ons © Output unlatched at cycle end allows two-dimensional Toae CAS Access Time 30 Sins One clip selection cac CAS AcoessTime | 30ns_35ns_40ns @ Common 1/O capability using “EARLY WRITE” tre CycleTime 165ns 190ns —-220ns operation twcac Mbble Mode Access 20ns —-20ns._— (Bn © Read-Modity-Write, CAS before RAS refresh, AAS: Nits Moda Oya — only refresh, Hidden refresh, Nibble Mode and Test tne Time ae vel 40ns — 40ns_— 5 Ons Mode capability ~— — © Ail inputs and output TTL compatible © Single power supply of 5V + 10% with a built-in Vee © 512 refresh cycles/8ms generator © Packing Plastic DIP: TC511001P _ ; - Plastic SOJ: TC511001J (PIN CONNECTION (ror view) Plastic ZIP : TC511001Z Plastic DIP Plastic SOJ Plastic ZIP ‘BLOCK DIAGRAM Div “aebves Pay Ves wht _ warred2 37 bdour 2 a PDoyr 4 fa [Os Pw Pour mee char TAR SEAT merplte vee Yee ; ; are aspa ras ES zy nde asbar nods, as bae ifelrr WHITE D i i aady — wepas May iepas ey To. sds pas MGB isbas softies ne veodas _lepae ran veo bl Slaw ——_ asp? ay a7 ho} po SOPFERS (10: DECODER AO~ AQ __ Address Inputs age Dw | Datta too | Lem eSbal | Dour Data Out | 190-1 | Sorrens(a0) PY S (Ras Flow Address Strobe == [WRITE | Readrite inout_ wre Power (+5V) _ aias Ground 1 3eBaaron TF Test Function

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TEM SOS™””~™O SS SYMBOL” RATING | UNITS | NOTES Input Voltage ~)Viw a7 ee ee ee Test Mode Input Voltage =i~io6 PV Output Voltage Vout “157 Vv 7 Power Supply Voitage Vec [a7 Vv aT Operating Temperature | torn = 70 ae 1 Storage Temperature Tst¢__ =55~ 150 _ | a Soldering Temperature* Time _ _| Tsovoer ___260°10 _ °Crsec 1 Power Dissipation Po 600 mW i Short Circuit Output Current _ | tour 80 mA RECOMMENDED DC OPERATING CONDITIONS (73 - 0 ~ 70°c) SYMBOL - PARAMETER __ | _MIN. TYP. MAX. [UNIT [| NOTES Vee Supply Voltage 45 5.0 55 v 2 Vin Input High Voltage 24 = 65 Vv 2 Viv input Low Voltage =1.0 = 08 vf. 2 Vinirri_ | Test Enable input High Voltage Voc +4.5 = 105 Vv 2 Miva) Test Disable Input Low Voltage 1.0 = Voc +1.0 Vv 2 DE ELECTRICAL CHARACTERISTICS (Vcc- 5 + 10%, Ta = 0~ 70°C) “OPERATING CURRENT ~ TC511001P/5/2-85 = ~70 mA leer Average Power Supply Operating Current TC511001°/i/2-10 =~ [60 | mA} 3,4 (RAS, CAS, Address Cycling: tac= tac MIN.) FC511001P/4/2-12 =__|s0 mA STANDBY CURRENT loco Power Supply Standby Current - 2 mA 1/3 (RAS = CAS = Vin) — of RAS ONLY REFRESH CURRENT 1€517001P/i/2-86 = ee Ices Average Power Supply Current, RAS Only Mode FC511001P//Z-10 a 60 | mA_|3 (RAS Cycling, CAS = Vin: tac= tacMIN.) _[ Tesii001//212 | — 50 | mA __ . NIBBLE MODE CURRENT TC511001F 2.85] — 50 | “mA loca Average Power Supply Current, Nitible Mode Te5110010/4/2.10_ | — “49 | ma] 3,4 (RAS = V\\__, CAS Cycling: tyo= tcMIN.) FE511001P/5/2-12 = 30 mA lees Power Supply Standby Current - 1 mA ___| MRAS = CAS = vec-0.2V) _ | CAS BEFORE RAS REFRESH CURRENT |_TC511001P//2-85 = 10 | mA | lece Average Power Supply Current, CAS Before Tes11001r//2-10 | — “60 | mA | 3 __| RAS Mode (RAS, CAS Cycling: tre= tac MIN.) TCS11001P/I/z-12 = 50 mA INPUT LEAKAGE CURRENT (any input except TF) hay Input Leakage Current, any input (OV < Vins. 6.5V, =10 10 HA All Other Pins Not Under Test = OV) INPUT LEAKAGE CURRENT (only TF) rn 10 "| - 1 10 1 THE | (ov S Vinite) < Vec + 0.5V, All Other Pins Not Under Test = 0V) ou OUTPUT LEAKAGE CURRENT _ — Ta | 1 ~ 1) | ouris disabled, OVS VouTS 55) oe 10 wt te TEST FUNCTION INPUT CURRENT = mA (Vee + 4.5V S$ Vintrr) S10.5V) OUTPUT LEVEL CO 2 > v. Z on Output "H” Level Voltage (louT=—5mA) ae _ v — Vou ouTpur Lever - 04 v | Output "Li" Level Voltage ours 4.2mA) a —116~

(Vec = SV + 10%, Ta= 0~ 70°C) (Notes 5, 6, 7) . Te511001P/ | Tc511001P/_ | TC511001P/ SYMBOL PARAMETER _ 9/285 | 210 J/Z212___| UNIT |NOTES. tRC Random Read orWrite Cycle Time | 165 | — | 190 | — | 220 | — ns tre Read Write Cycle Time _ 90 | — | 220 | — | 25 | — [rs | tne Nibble Mode Cycle Time Ta [= f 40 | — | 50 | - | ns tam | Nibble Mode ReadWrite CycleTime | 65 | — | 65 | — | 80 | ~ | ns taac | Access Time fromRAS SSs*~<C~s:CSC«E=Ci‘ “YTS «| to | — (| 120 ons 8,13 teac Acces TimefromCASSS—~<CS~SS dC] 35; — | 40 | ns [8,13 TAA ‘Recess Time from Column Address | - | 45 | — | so | - | 60 | ns [814 Torr | Output Buffer Turn Off Delay «|S 30 0 0 ns |9 i Transition Time (Rise and Fall) =| 3 so. 3 3 ns | 7 inp | BAS Precharge time ——~S*dY CO] «|| - | 80 | pe 18 imag | RAS PulseWidih ——S~S*~S*~CS*~ «STB 10000100 20 ny TCAS TASPulseWidth ——SSS™=~<CSsS~SC~SSC «90,000 3D 40 ns taco __| RAS to CAS Delay Time 25 25 | 6 | 25 | 80 | ns [13 TRAD RAS to Column Address Delay Time 20 20 | 50 | 20 | 60 | ns [14 _ tere | CASto RAS Precharge Time “10 to | - | 10 | - | ns teen CAS Precharge Time _ 15 15 20 nsf tASR Row Address Set-Up Time [0 | 0 += 0 ns TRAH RowAddresHoldTime sd = 15 15 _ tcan ‘Column Address Hold Time S| 0 | =| 20 ~25 os | tan Cun ‘Address Hold Time referenced 6 | - 5 90 ns that | Column Address to RAS LeadTime «| 45 «| — ‘| 60 ns tres | Read Command Se-Up Time 0, - | |; - [| 0 ns || ' “Read Command Hold Time referenced to > a tary fod Command Hold Time referenced to of _ 0 _ ° ns 10 two Write Command Hold Time | 20 | = | 20 | ~ | 25 | wer Write Command Hold Time referenced to 65 T - ~ | - 90 ns RAS “twe | Write Command Pulse Width | 20 | | 20 | =| 28 os__ tawe Write Command to RAS Lead Time 20 | — ml = 30 | — | ns tew. | Write Command toCAS Lead Time | 20 -«| — | 25 | — 30 | - [mw | | tos _| Data-inSetUp Time | of - | 07 - of - [os [un | [tH Data-In Hold Time ee oe ee 25 ns tor DataInHoid Time referenced toRAS | 65 | — | 75 = ‘90 t= ns. -1l7—

ELECTRICAL CHARACTERISTICS AND RECOMMENDED ACIOPERATING CONDITIONS conn sro Tesi1001P/ | Tcs11001e/ | TC511001°/ SYMBOL PARAMETER J/Z-85 J/210 W2AZ UNITS |NOTES Write Command Set-Up Time o|] - oo] - | of] - [ons [a2 [Sew | CAS to WRITE Detay Tine i RAS toWRITE Delay Time [es [ = | 100 [ - | iz0 [ = [ns | 12 | tawo | Column Address to WAITE Delay Time 4a [ - | 8 | = | 6 | - | ms | 12 | tesa __| CAS Set-Up Time (CAS before RAS) 10 10 =e ns _ CAS Hold Time (CAS before RAS) 30 Ce RAS Precharge to CAS Active Time a of = [of - [as terr TAS Precharge Time (CAS before HAS 50 | - | 50 | - |» | - | ns | Counter Test) = teas __| Nibble Mode Pulse Width 20 | - | 20 2 | - | || Nibble Mode CAS Precharge Time [| 10«| — | 10 is | - | | Nibbie Mode RAS Hold Time 2 | - [| 2 }- | 2] [na di Nibble Mode CAS to WRITE Delay Time 20 | = | 2 | - | 2 ns || seers [a fet Teo Test Mode Enable Set-Up Time referenced 0 0 0 | - | ns || to RAS _ a Test Mode Enable Hoid Time referenced ° 0 0 = | hs to RAS Test Mode Enable Hold Time referenced — | 6 0 | - | ns to CAS SCAPACITS ACITANCE! (Vo0 = SV # 10%, f= IMHz, Ta= 0~ 70°C) PARAMETER MAX. Input Capacitance (Ay ~ Ay, Din) 5 Input Capacitance (RAS, CAS, WRITE, TF) ee Co Output Capacitance (Dour) = 7 [pF | —118—

NOTES: 1. Stresses greater than those listed under “Absolute Maximum Ratings" may cause permanent damage to the device, 2. All Voltages are referenced to Vss- 3. Icc1, lees, Ieca. Hees depend on cycle rate. 4. lcci, leca depend on output loading. Specified values are obtained with the output open. 5. An initial pause of 200us is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS initializa- tion cycles instead of 8 RAS cycles are required. 6. AC measurements assume tr = Ss. 7. Vin min.) and Vi (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between V\\,, and Vi. . 8. Measured with a load equivalent to 2 TTL loads and 100pF. 9. torr(max.) define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 10. Either tacy OF tay Must be satisfied for a read cycle, 11. These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in read-write cycles. 12. twes, tawo: tewo and tawo are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If twes 2 twes(min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) throughout the entire cycle; If tawo 2 tawo (min.), tewo 2 tcwo ({min.} and tawo 2 tawo (min.), the cycle is a read-write cycle and the data out will contain data read from the selected cell: If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. reference point only: If taco is greater than the specified taco (max.) limit, then access time is controlled by tcac. reference point only: If teap is greater than the specified tgap(max.) limit, then access time is controlled by tan. ~119—

oy (a ” sone eS DOE Dour Yoh oven - Y/7Xivaur0 oxrap @ WRITE CYCLE (EARLY WRITE) pales

@ READ-WRITE CYCLE ‘Rw ‘RAS ras vin — TAR tRsH tcsH somas 1 TX avistos DX siete K/L LK te be tees, [te] [a vy _ ou [tae : er tH y ~ a oun" 77MM = WLLL Z: “H" or “LU NOTE: “TF” pin should be connected to V\\(rF) level or open, if "Test Mode” is not used. —121—

ES RE ANG DTI RE TOLAG Ane een oe a ~ TC511001P/J/2-85,TC511001P/J/Z-10 @ RAS ONLY REFRESH CYCLE tre ae oo] aS Vu — tRAS. * Er TT —— Ib tasR ‘RAH acme MMMM My cmc MMM, Dour ven eens OPEN ou a: HY on hL © CAS BEFORE RAS REFRESH CYCLE tre a tRP . —— cas ES Vin — t rs vy — RPC — ~ Vin — ' CAS vin torr ° Dour Vo! OPEN You — “H" or UL NOTE: WRITE = “H" or “L", AO ~ AQ = “H" or “L" “TE pin should be connected to Vi_(1F) level or open, if “Test Mode” is not used. —124—

a Soe Telos ee ‘ oa @ CAS BEFORE RAS REFRESH COUNTER TEST CYCLE ee MMMM MMMM UL <n - a ie —_—l3 torr tRos | ToLZ, | | tRRH vere | i Z WRITE CYCLE | ve 7 see HT 7 1 vere ZILLI VT See MMMM, cee READ-WRITE CYCLE taa YE Peavy ET

—-Tes11001P//2-85,Tc511001P//z-10 tt” a Test ioorPyaae ea ~~ aap C @ HIDDEN REFRESH CYCLE (READ) sow LLM @ HIDDEN REFRESH CYCLE (WRITE) tre tac -; i PRATT ow tt — TUTOR a= XLII Dour You— SCPE Biwew ems _——

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APPLICATION INFORMATION

ADDRESSING _ The 20 address bits required to decode 1 of the CAS is active(\\ow). Data read from the selected cell 1,048,576 cell locations within the TC511001P/J/Z will be available at the output within the specified are multiplexed onto the 10 address inputs and access time. latched into the on-chip address latches by externally applying two negative going TTL-level clocks. DATA OUTPUT CONTROL The first clock, the Row Address Strobe (RAS), The normal condition of the Data Output (Dour) latches the 10 row address bits into the chip. The of the TC511001P/J/Z is the high impedance (open second clock, the Column Address Strobe (CAS), circuit) state. This is to say, anytime CAS is at @ high subsequently latches the 10 column address bits into level, the Dour pin will be floating. The only time the chip. Each of these signals, RAS, and CAS, the output will turn on and contain either a logic 0 triggers a sequence of events which are controlled by or logic 1 is at access time during a read cycle. Dout different delayed internal clocks. will remain valid from access time until CAS is taken The two clock chains are linked together logically back to the inactive (high level) condition. in such a way that the address multiplexing operation is done outside of the critical path timing sequence NIBBLE MODE for read data access. The later events in the CAS Nibble mode operation allows faster successive clock sequence are inhibited until the occurrence of data operation on 4 bits. The first of 4 bits is accessed a delayed signal derived from the RAS clock chain. in the usual manner with read data coming out at This "gated CAS” feature allows the CAS clock to be tcac time. By keeping RAS low, CAS can be cycled externally activated as soon as the Row Address Hold up and then down, to read or write the next three Time specification (tray) has been satisfied and the pages at high data rate (faster than tcac). Row and address inputs have been changed from Row address column addresses need only be supplied for the first to Column address information. access of the cycles. From then on, the falling edge of CAS will activate the next bit. After four bits have DATA INPUT/OUTPUT been accessed, the next bit will be the same as the Data to be written into a selected cell is latched first bit accessed (wrap-around method). into an on-chip register by a combination of WRITE and CAS while RAS is active. The later of the signals (0, O)—> (0, 1) (1,0) (1,1) (WRITE or CAS) to make its negative transition is the TE J) strobe for the Data In (Dix ) register. This permits several options in the write cycle timing. In a write Address AQ determines the starting point of the cir- cycle, if the WRITE input is brought_low (active) cular 4 bits nibble. Row AQ and column AQ provide prior to CAS, the Din is strobed by CAS and the the two binary bits needed to select one of four bits. set-up and hold times are referenced to CAS. If the From then on, successive bits come out in a binary input data is not available at CAS time or if it is de- fashion; 00 + 01 + 10> 11 with AQ row being the sired that the cycle is a read-write cycle, the WRITE least significant address. signal will be delayed until after CAS has made its A nibble cycle can be a read, write, or delayed negative transition. In this “delayed write cycle’ write cycle. Any conbinations of reads and writes or the data input set-up and hold times are referenced late writes will be allowed. In addition, the circular to the negative edge of WRITE rather than CAS. wrap-around will continue for as long as RAS is kept (To illustrate this feature, Din is referenced to low. WRITE in the timing diagrams depicting the read- write and nibble mode write cycles while the “early RAS ONLY REFRESH write” cycle diagram shows Din referenced to CAS). Refresh of the dynamic cell matrix is accomplished Data is retrieved from the memory in a read cycle by performing a memory cycle at each of the 512 by maintaining WRITE in the inactive or high state row address (AO ~ A8) within each 8 millisecond throughout the portion of the memory cycle in which time interval. Although any normal memory cycle —127-

ee ee HERS ieee ees UU eae ae es uta meee tulle hela i entail | Tes11001P/4/z-85,TeBT1001P/J/2-10 will perform the refresh operation, this function is perparation for the next CAS before RAS refresh most easily accomplished with “RAS-only” cycles. operation. CAS BEFORE RAS REFRESH HIDDEN REFRESH CAS before RAS refreshing available on the An optional feature of the TC511001P/J/Z is that TC511001P/J/Z offers an alternate refresh method. refresh cycles may be performed while maintaining If CAS is held on tow for the specified period (tesp) valid data at the output pin. This referred to as before RAS goes to low, on chip refresh control Hidden Refresh. Hidden Refresh is performed by clock generators and the refresh address counter are holding CAS at Vi. and taking RAS high and after enabled, and an internal refresh operation takes place. a specified precharge period (tap), executing a CAS After the refresh operation is performed, the refresh before RAS refresh cycle, (see Figure below) address counter is automatically incremented in MEMORY CYCLE. REFRESH CYCLE REFEESH CYCLE AS vas | This feature allows a refresh cycle to be “hidden” write mode. among data cycles without affecting the data avail- (2) Select one certain column address and read “0” ability. out_and write "1" in each cell by performing CAS BEFORE RAS REFRESH COUNTER TEST CAS BEFORE RAS REFRESH COUNTER (READ-WRITE CYCLE). Repeat this operation TEST 512 times. The internal refresh operation of TC511001P/J/Z (3) Check ""1” out of 512 bits at normal read mode, can be tested by CAS BEFORE RAS REFRESH which was written at (2). COUNTER TEST. This cycle performs READ/ — (@) Using the same column as (2), read “1” out and WRITE operation taking the internal counter address write “0” in each cell performing CAS BEFORE as row address and the input address as column RAS REFRESH COUNTER TEST. address. Repeat this operation 512 times. The test is performed after a minimum of 8CAS —— (&) Check “0” out of 512 bits at normal read mode, before RAS cycles as initialization cycles. The test which was written at procedure is as follows. © Perform the above (1) to (6) the complement data. @ Write “0” into all the memory cells at normal —128—

The TC511001P/J/Z is the RAM organized parts, the data output pin indicates a complementary 1,048,576 words by 1 bit, it is internally organized data for bad parts. And also, if any of the bits dif- 262,144 words by 4 bits. In “Test Mode”, data would fered, the data output pin would indicate a high be written into a number of sectors (4 sectors) in impedance state for bad parts. Fig. 1 shows: the block parallel and retrieved the same way. \\f, upon reading, diagram of TC511001P/J/Z including its truth table all bits are equal (all “H” or “L”), the data output when “Test Mode” is used. pin indicates a same data as all bits. In this case, the In test mode, IMDRAM can be tested as if it were data output pin indicates an expected data for good 256K DRAM by the following method. Block Diagram in Test Mode an.am an.am_[asex [4 3 sora 5 BLOCK [-— ° an, am 4 ane caer 2_| ani B Lf Nen BLOCK x : an, An 256K ——O 0, ~ BLOCK [= > ° am ve _ D a a Non ~ . BLOCK -— D TF Pin = Super Voltage; Test Mode TF Pin = Viverr) level or Hi-Z; Normal Truth Table in Test Mode Function ale Dour fol[ofolo] o oe Otherwise __|_Hiz Fig. 1 —129—

| -TC511001P/4/z-85,TC511001P//2-10 tt “Test Mode’ function is performed on any of the On the other hand, normal operation requires the timing cycles except Nibble mode when “TF” pin is “TE” pin be connected to Vi. irr) level, or left un- held on “super voltage (Vcc + 4.5V (Vcc = BV + connected on the printed wiring board. 10%), max. voltage = 10.5V)” for the specified period The ‘Test Mode” function reduces test times (1/4; (tres, treHp and tree ; see Fig. 2). The address input in case of using N test pattern). This ‘‘Test Mode’’ of AQ is ignored in the ‘Test Mode”. function is implemented from Revision "C”’. Vin RAS s Vin — wey — oS ‘In vin — (PTEHC(O ns) tres|( one) v ~ pp THF) Vin(IF) — Fig. 2. Test Mode Cycle —130—

@ Plastic DIP Unit: in mm 1g 17 16 15 14 15 12 11 10 ca p~——_ R10 2 a1 2 3 4065 67 B89 220MAX. 262t028 UAH ARERR RG Sts yyy) oe A son zsazo2s | | l[J[sssoas” wl onerees |[fostois “lg NOTE: Each lead pitch is 254mm. All leads are located within 0.25mm of their true longitudinal position with respect to No. 1 and No. 18 leads. All dimensions are in millimeters. —131—

® Plastic SOU 1209 ~ 1727 ootye. Unit: in mm Ny ; E NEE en i TI r}oafa iwpex por 3 | 3| 3] 2 : 6 3s] & 123 45 9 10111213 Ht W998 HZAE) |i i Mong 2 @ Plastic ZIP 2E3MAX SOMAX, Unit in mm rNDex vor ag HOOAAnaaD mMHoOoOognRaaap - +a0° i ost oh Trier 2 4 6 8 12 14 16 18 20 NOTE: Each lead pitch is 1.27mm. All dimensions are in millimeters. Toshiba does not assume any responsibility for use of any circuitry described; no circuit patent licenses are implied, and Toshiba reserves the right, at any time without notice, to change said circuitry. ~132—