TC511000Z-12

TC511000P TOSHIBA | Alldatasheet

Document overview

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Technical content

a . we x1 BIT DY! 1,048,576 WORD x1 BITDYNAMICRAM = —TC54141Q00P/J/Z-85, TC511000P/J/Z-10 SILICON GATE CMOS TC51 1000P/J/Z-12

DESCRIPTION

The TC511000P/J/Z is the new generation dynamic ZIP. The package size provides high system bit densities RAM organized 1,048,576 words by 1 bit. The and is compatible with widely available automated testing TC511000P/J/Z utilizes TOSHIBA’s CMOS Silicon gate and. insertion equipment. System oriented features process technology as well as advanced circuit techniques include single power supply of 5V + 10% tolerance, direct to provide wide operating margins, both internally and to. _— interfacing capability with high performance logic the system user. Multiplexed address inputs permit the families such as Schottky TTL. “Test Mode” function is TC511000P/J/Z to be packaged in a standerd 18 pin _implemented from Revision C. plastic DIP, 26/20 pin plastic SOJ and 20/19 pin plastic

FEATURES

© 1,048,576 word by 1 bit organization © Low Power © Fast access time and cycle time 385mW MAX. Operating (TC51 1000P//Z-85) ee 330mW MAX. Operating (TC511000P//Z-10) 5110008 70/2 86-10-72_ | 275mW MAX. Operating (TC51 1000P/J/Z-12) trac! RAS Access Time 85ns 100 ns 120 ns | 5.5mW MAX. Standby | tan [Solum Address Access | gens Ons 60 mj) 8 Output unlatched at cycle end allows two-dimensional [cAS Acca Tine | ee ous Som), uP etection [tere |CAS Access Time __| 2508 __Z3ns__20 8 |e Common \\/O capability using “EARLY WRITE” trac | Cycle Time _ 165 ns 190 ns__ 2200s ‘operation tec [Fin Page Mode Cycle sors S5ns One| — @ Read-Modity-Write, CAS before RAS refresh, RAS: me a only refresh, Hidden refresh, Fast Page Mode and Test © Single power supply of 5V + 10% with a built-in Vi Mode capability geet "88 @ All inputs and output TTL compatible © 512 refresh cycles/8 ms PIN CONNECTION irr View © Package Plastic DIP : TC511000P . Plastic SOJ : TC511000) Plastic DIP Plastic SOJ Plastic Z1P Plastic ZIP. : TC511000Z ware qs iw bogyr wrth Bho the; wars ashen ARGS ath boos RIEL , nods pas SO Pow 2 ES emer mde usher nods aepas Rar 38 o- aed? has aigio | 27pa7 ote |tF WRITE P 7 veods 30pae veces de ae 2: 2] ar | Dour aa fa Ey A OENERATOR, “© ror~, “Address Inputs ° a RAS Row Address Strobe ne Dour Data Out soo ia Pica TAS Column Address Strobe n° Row Et q [WRITE "| Read/Write input 490 ADDRESS Oy ic Veo _ Power (+5V) | -_ TF Test Function GENERATOR GupsTRate Bias |—°Yce No. ~__No Connection GENERATOR vss -15-

ITEM SYMBOL RATING UNITS ‘NOTES Input Voltage VIN -1~7 Vv 1 Test Function Input Voltage Vint) —1~ 10.5 Vv. 1 Output Voltage: Vout. -1~7 v 1 Power Supply Voltage. Veo. 177 Vv. 1 Operating Temperature Torr o~70 °c 1 Storage Temperature Tste -85~150 | °C 1 Soldering Temperature* Time. TsoLveR 260-10 °Crsec 1 Power Dissipation Po 600 mW 1 Short Circuit Output Current 50 mA 1 RECOMMENDED DC OPERATING GONDITIONS (Ta = 0~ 70°C) SYMBOL PARAMETER TYP. MAX. NOTES input High Voitige———SSSSSSSd Cn 2 Input Low Voltage — [aro [os ve Vin (Te) | Test Enable Input High Voltage _ = ws | vi {| 2 Vit (te) | Test Disable Input Low Voltage =1.0 = Vec #1.0 v 2 De ELECTRICAL CHARACTERISTICS (v.. = 5V + 10%, Ta= 0~ 70°C) OPERATING CURRENT | te511000/4/2-65 = 70 leet | Average Power Supply Operating Current Fes11000r/s/2-107 | =] 60 ma | 3.4 (RAS, CAS, Address Cycling : tac * tac MIN.) Tesioooriz12_ | — | 50 STANDBY CURRENT | Ieee Power Supply Standby Current 2 mA {RAS = CAS = Vin) "RAS ONLY REFRESH CURRENT Tesiio0er/i/z05 | — | 70 lees | Average Power Supply Current, RAS Only Mode TC511000P/J/2-10__ 60 | mA 3 (RAS Cycling, CAS = Vin: tac = tac MIN.) FC511000P/N/Z-12 50 FAST PAGE MODE CURRENT. TC511000P//Z-85 50 lees Average Power Supply Current, Fast Page Mode [rest1o00p//z10 | _— | 40 ma | 3.4 | _____| (RAS = Vit, CAS, Address Cycling: tec = tec MIN.) |Test1000°/4/212 [=| 30. 4 STANDBY CURRENT | lees. Power Supply Standby Current 1 mA (RAS = CAS = Vcc-0.2V) {__/ CAS BEFORE RAS REFRESH CURRENT resrso00rze5 | — | 70 | loos Average Power Supply Current, CAS Before Tesi000r//z10 | — | 60 mA | 3 —— RAS Mode (RAS, CAS. Cycting: tac =tae MIN.) TCS11000P/5/Z-12 50 INPUT LEAKAGE CURRENT (any input except TF) Io Input Leakage Current, any input (OV & Vin $6.5V, All Other 10 uA Pins Not Under Test = OV) a

1 INPUT LEAKAGE CURRENT (only TF) 40 A

ime(u) (OV SVin (TF) SVcc + 0.5V, All Other Pins Not Under Test = OV) ” |

1 OUTPUT LEAKAGE CURRENT 10 uA a

ow) (Dour is disabled, OV S Vout S$ 5.5V) an . 4 j TEST FUNCTION INPUT CURRENT 1 mA TF (Voc + 4.5V $ Vin(Te) $10.5V) OUTPUT LEVEL OUTPUT LEVEL Vou Output “L Level Voltage (lout = 4.2 mA) | - | 04 ~16—

~46511000P/J/Z-85, TC511000P/J/2-10 (Voc = BV # 10%, Ta = 0 ~ 70°C) (Notes 5, 6, 7) —— — ~~) tes11000P7 [| TC511000P__ | TC511000P/ 7 SYMBOL PARAMETER 312-85 ZNO MZA2 NOTES __ twin. Tmax. | Min, MIN. | MAX. trc Random Read or Write Cycle Time 15 | 190 | — | 220 - tawe | _Read-Write Cycle Time [190 | = | 220 | — | 258 = [ons ~ Fast Page Mode Read-Write Cycle Time | 75 = 85 = 106 fons | trac Access Time from RAS = 85 = joo | = 8.13 “Access Time from CAS. es ee ee ee 30 | ns | 8,13 ‘Access Time from Column Address - | 4 | - so | - | 60 8.14 ‘Access Time from CAS Precharge = 45 | - so | — 65 8 teiz___|_ CAS to Output in LowZ ee ee “5 | - | 6 [= 8 torr | Ovtput Buffer Tur-off Delay | 0 | 30 | 0 30 o | 35 9 tap RAS Precharge Time 70 = 80 = 90 = [rs | tras _|_ RAS Pulse Width ~ | 85 | 10,000 | 100 120 | 10,000] ns | RAS Pulse Width (Fast Page Mode) | 85 [100,000] 100 |100,000{ 120 |100,000/ ns |_| RAS Hold Time 2 | 2 | 30 | = | ns _| CAS Hold Time ~ [es | - | i00 = 120 = [os _| CHS Pulse Width “25 [| 10,000 25 | 10,000) 30 | 10,000/ ns _| "RAS to CAS Delay Time | 8 60 25 25 90 [| ns | 13 | CAS to RAS Precharge Time io | - | wm] - {| wo | - [ os | top | GAS Precharge Time (Fast Page Mode) io | —- |. | — | 15 [ons [| | Row Address SetUp Time 0 = o/| - [| 0 [ons || Row Address Hold Time _ 15 = 15 = 15 | ns_| Column Address Set-Up Time oo; - | 0 0 [ns _| TCAH Column Address Hold Time | 20. = 20 25 [ons |_| tan Column Address Hold Time referenced | g¢ 5 | - | ‘90 p= | | tRAL Column Address to RAS Lead Time 45 "50 60 [ns |_| trcs | Read Command Set-Up Time | 0 0 of; - [ow] | tacu | Read Command Hold Time TO 0 0 [ons | 10 | to RAS __ Write Command Hold Time 20 2 | - | 2 | — | os | Write Command Hold Time referenced | 6¢ 5 90 _ twe Write Command Pulse Width 20 20 25 — | ons | trwe__|_Write Command to RAS Lead Time 20 25 30 = [1s | Write CommandtoCAS Lead Time | 20 | — | 25 30 — | ns _| tos Data Set Up Time 0] 3 + - ns ton “Data Hold Time | 0 | = 20 25 | — | os tour Data Hold Time referencedtoRAS | 65 | — | 75 | — | 90 = ns “tree | RefreshPeiod SCE | | | OT 8

~— TC511000P/4/2-85,TC511000P/J/2-10 ELECTRICAL CHARACTERISTICS AND’ RECOMMENDED AC OPERATING CONDITIONS (Continue) - Tes11000P/ | TC511000°/ | TC511000P/ SYMBOL, PARAMETER J/2-85 JZAO WZA2Z UNIT [NOTES twes Write Command Set-Up Time | 0 | — | 0 = 0 [a2 | towo ‘CAS to WRITE Delay Time 28 = 25 = 30 [_tewo | RAS to WATE Dety Time a tawo Column Address to WRITE Delay Time | 45 = 50 | — | 60 CAS Set-Up Time (CAS before RAS: tosr Cycle) 10 10 | - | 10 CAS Hold Time (CAS before RAS. taec__| RAStoCASPrechargeTime | 0 | - {| of ~ | of —- | CAS Precharge Time (CAS before RAS tept Counter Test Cycle) i - iad 60 Ten | CAS Precharge Time i ee t Test Mode Enable Set-Up Time ° 0 n Tes referenced to RAS s t Test Mode Enable Hold Time 0 0 h TEHR | referenced to RAS s t Test Mode Enable Hold Tire 0 _ 0 0 7 hs STERC | referencedtoCAS ~78—

ea ee ee CS eb cae aa Corp aoa pag seule nao SON Pe Ne or ade Ho a ‘i ‘GAPACITANCE (Vcc = 5V + 10%, f= 1 MHz, Ta=0~ 70°C) PARAMETER MIN. MAX UNIT Ch Input Capacitance (AO ~ A9, Din) _ = 5 pF Cy ~ Input Capacitance (RAS, CAS, WRITE, TF) = 7 pF Output Capacitance (Dout ) = 7 oF NOTES: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. 2. A\\ll Voltages are referenced to Vss . 3. leer, Iee3. Ieca, loos depend on cycle rate. 4. lccy « leca_ depend on output loading. Specified values are obtained with the output open. 5. An initial pause of 200us is required after power-up followed by 8 RAS cycles before proper device opera- tion is achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS initialization cycles instead of 8 RAS cycles are required. 6. AC measurements assume ty= 5ns. 7. Vin min.) and Vj, (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between Vi and Vi._ 8. Measured with a load equivalent to 2 TTL loads and 100pF. 9. torr(max.) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 10. Either tacu Or tanr must be satisfied for a read cycle. 11. These parameters are referenced to CAS leading edge in early write cycles anc to WRITE leading edge in read-write cycles 12. twes, tawo, tewo and tawo are not restrictive operating parameters. They are included the data sheet as electrical characteristics only. If twes = twcs(min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle; If tawo tawolmin.), tewo 2 tewo(min.) and tawo2 tawolmin.), the cycle is a read-write cycle and data out will contain data read from the selected cell: If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeter- minate. reference point only: If taco is greater than the specified tac (max.) limit, then access time is controlled by teac 14, Operation within the taap(max.) limit insures that taac(max.) can be met. taap(max.) is specified as a reference point only: If teap is greater than the specified tyap(max.) limit, then access time is controlled by tan -719—

_—Tesitoooriayets: oer 70n0r/4/2 Ue TIMING WAVEFORMS @ READ CYCLE tae —_ tap we vu — _ tras | Vn — tosH toRP trop SESH tcRP AR trap | | lesan _| enn ///), Gime //), cme RCH Vie — a tan TRAC | tOFF ZA: “HW or "L" NOTE: ‘'TF” pin should be connected to Vi, (TF) level or open, if “Test Mode” is not used.

eg 1681 10008/3/2 wo ea _. oo Ey [eo || aes | wou DO TELL ve ML an" “TTT == == SUT _ CDHR :SHYor"L® NOTE: “TF” pin should be connected to Vit (TF) level or open, if “Test Mode” is not used.

Se TCRIIOOOP/NZ-12) 0 @ READ-WRITE CYCLE an = __ fasny | fas tase [| [ecu] owe" TX WIN ITM | | _ | i tps ‘DE | vt, LLL = WLLL trac [| ' oL tone lL} NOTE: “TF” pin should be connected to Vit (TF) level or open, if “Test Mode” is not used.

| 7€511000P/J/Z-85, TC511000P/J/Z-10 --1C511000P/4/2-12 @ FAST PAGE MODE READ CYCLE trp —~ Vin —— + Lae / Vn — _ tesH treo °ESH _| °RcD cas fcr. tcp | | Vin — a teas ; #——4 toas T tan veau | i wonno * T7X_ 208 WOK 2oe OX 0c» VOX 20» KIL: vIn — * tres \\ ll es0p SERCH tres tow var | | | Vin Poac toac tcac | | ron oem nto toLz {| or| touz torr sue | |torr NOTE: “TF” pin should be connected to Vit (TF) level or open, if “Test Mode”’ is riot used. -33-

© -TC511000P/J/Z-85,TC511000P/J/Z-10 ss” a Testio00p/zi2 ee ee © FAST PAGE MODE WRITE CYCLE (EARLY WRITE) Vin — trasP nono DN WX KK 2 SOX co MTL a Iewon | MS i; c Les — Vin — i - L ine “ ou 1 ees ws as ae mmm "HM or"L® NOTE: “TF” pin should be connected to V\\_ (TF) level or open, if “Test Mode” is not used. —84—

@ FAST PAGE MODE READ-WRITE CYCLE vin — a = | Nsom ee } i tRab , = : poe f Ecar | sone vn Dh ADK om Meme 1K orm III M wef |e) || = tps ‘pH \\ 2 tL |tpe soy a ve “LLL XR MLK trac toral _| ToPA = NOTE: “TF” pin should be connected to Vi (TF) level or open, if “Test Mode” is not used. a

© -TC511000P/J/Z-85.TC511000P/J/Z-10, ee - .,rrt—=“‘e @ RAS ONLY REFRESH CYCLE toRP tRPC NOTE: WRITE =H" or “L", AQ = “H" or “L" “TF” pin should be connected to Vit (TF) level-or open, if “Test Mode” is not used.

@ CAS BEFORE RAS REFRESH CYCLE ee 5 tRp RAS tm tRPo : CAS VIL — torr You — NOTE: WAITE =H" or "L", AO~ AQ= "H" or “L” “TE” pin should be connected to Vi. (TF) level or open, if ‘Test Mode” is not used. -s-

_ TC@B11000P/J/Z-85,TCE11000P/J/Z-10 _ Tes00rs212 00 rr rs—sS @ HIDDEN REFRESH CYCLE (READ) Vin — ‘Ras TRAS Ea ee’ “ Psa} | im tasR. [| tcaH | | a one nn SE meneen | //, Gn von — = iD ZA: Hr" orl" NOTE: “TF pin should be connected to Vi. (TF) level or open, if “Test Mode"" is not used.

@ HIDDEN REFRESH CYCLE (WRITE) pes toy CpER EQ: "H" or "i" NOTE: “TF” pin should be connected to V\\_ (TF) level or open, if “Test Mode” is not used.

'TC511000P/u/Z-85,TCS11000P/J/Z-10—t™S TC511000P/J/Z-12 oo : © CAS BEFORE RAS REFRESH COUNTER TEST CYCLE me ~ MS vn ee’ _ ones yn LLL LLL LLL READ CYCLE | - MAE ea cove a FRcs | Foz | | cool WRITE CYCLE | | ~ weve Vin — | i ftw | , Een LLL LLL Le) LLL TLL | "ps, toe | ‘rE READ-WRITE CYCLE | | a | fore, WRITE Yin —— tres te — LLL LLL KL, NOTE: “TF” pin should be connected to Vi, (TF) level or open, if “Test Mode” is not used. —90—

ae | -¥C511000P/J/2-85, TC511000P/J/2-10 Ce OBA ROOR 2-12 ACs EE NORA eA aU Ran pera en teiee. ea nae unimn cE en TM eee The TC511000P/J/Z is the RAM organized parts, the data output pin indicates a complementary 1,048,576 words by 1 bit, it is internally organized data for bad parts. And also, if any of the bits 262,144 words by 4 bits. In “Test Mode”, data would differed, the deta output pin would indicate a high be written into a number of sectors (4 sectors) in impedance state for bad parts. Fig. 1 shows the block parallel and retrieved the same way. If upon reading, diagram of TC511000P/J/Z including its truth table all bits are equal (all "H’” or “L"), the data output when “Test Mode’ is used. pin indicates a same data as all bits. In this case, the In test mode, IMORAM can be tested as if it were data output pin indicates an expected data for good 256K DRAM by the following method. Block Diagram in Test Mode An, Am an,am_[asex [+ 2 won 9 — Be] LY 7, x ae ao TF An, Am y BLOCK al | ; ~~ - BLOCK [— | —> i ne a TF > ne keh meme [2ser 2 ——T BLOCK v TF Pin = Super voltage; Test Mode TF Pin = Vii (tr) level or High-Z; Normal Truth Table in Test Mode Function fo fo foyfo | o | fi tayaya fa | otherwise _ Fig. 1 —91—

sna aE AAPG a PE cpa ACE OU ena tg Maa eo fae ira Pap RN Bt eno AeA a Pe Oa Nee EAE Dae ao “Test Mode” function is performed on any of the On the other hand, normal operation requires the timing cycles including fast page mode when “TF” “TF” pin be connected to Vi, (TF) level, or left un- pin is held on “super voltage (Vec +4.5V (Veco = 5V connected on the printed wiring board. + 10%), max. voltage = 10.5V)" for the specified The “Test Mode” function reduces test times (1/4; period (tres, treuR and treyc : see Fig. 2). The in case of using N test pattern). This “Test Mode” address input of AQ is ignored in the “Test Mode”. function is implemented from Revision “C”. vin — TES Ik ry vin — | —~ VE oRS ven — UTEHC(O a8) *TES| (Ons) trEHR(o ne | Vin(tF) — — — Vo 1F (TF) Vin(tF) — Fig. 2 Test Mode Cycle @ Plastic DIP 18 17 16 15 14 13 1211 10 Unit: in mm ci R190 2 Tes «5 67 8 9 228MAK. 2624028 FS 3| - GOO E naa ( ome —\\— a a a a - O25. obs 2544025 14+015 ol = assis 3 Note: Each lead pitch is 2.54mm. All leads are located within 0.25mm of their true longitudinal position with respéct to No, 1 and No, 18 leads. All dimensions are in millimeters. ~92—

ES Se en epee tree ee en ge onsen Ceecspon oe cen euE ete: ® Plastic SOJ Unit inmm 26 25 24 23 22 18171615 ql eo 25 26 7574 S38 AS S)- NY H = SS —_. : t . rape B al als INDEX DOT 2 | “31 3 vd kK) — bu ercru oortres )—~ 1234 5 9 10111213 ase~o.76 cI : i9999- JAA Zk aver ry rarqee_|é Note: Each lead pitch is 1.27mm. All dimensions are in millimeters. ~93-