TC387

TC38X INFINEON | Alldatasheet

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Technical content

V 1.2, 2021-03 TC38x 32-Bit Single-Chip Microcontroller AD/AE-Step 32-Bit Single-Chip Microcontroller 32-Bit Microcontroller OPEN MARKET VERSION

81726 Munich, Germany

© 2021 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be reg arded as a guarantee of conditions or characteristics. With respect to any examples or hints given he rein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and condi tions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com) Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support de vices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety o r effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human bo dy or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. OPEN MARKET VERSION

Data Sheet 3 V 1.2 2021-03

Revision History

Page or Item Subjects (major c hanges since previous revision) V 0.4, 2017-02 Version 0.4 is the first version of this document V 0.6, 2017-06 The history is documented in the last chapter V 0.7, 2018-05 The history is documented in the last chapter V 0.71, 2018-07 The history is documented in the last chapter V 1.0, 2018-09 The history is documented in the last chapter V 1.1, 2019-09 The history is documented in the last chapter V 1.2, 2021-03 The history is documented in the last chapter OPEN MARKET VERSION

Data Sheet 4 V 1.2, 2021-03 Trademarks of Infineon Technologies AG AURIX™, C166™, C anPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, C o o l S E T ™ , CORECONTROL™, CROSSAVE™ , DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™ , EconoDUAL™, EconoPIM™, EconoPACK™, EiceDRIVER ™, eupec™, FCOS™, HITFET™, Hyb ridPACK™, I²RF™, ISOFACE™, IsoPACK™, MI PAQ™, ModSTACK™, my-d ™, NovalithIC™, Opti MOS™, ORIGA™, POWERCODE™; PRIMARION™ , PrimePACK™, PrimeSTA CK™, PRO-SIL™, PROF ET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™. Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, AR M™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetoot h™ of Bluetooth SIG Inc. CAT-i q™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Lt d. EMV™ of EMVCo, LLC (Visa H oldings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexR ay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Int ernationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICRO TEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Allianc e, Inc. MIPS™ of MIPS Technol ogies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Rese arch Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. R ED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of S irius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIY O YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2011-11-11 OPEN MARKET VERSION

Data Sheet 5 V 1.2, 2021-03 Table of Contents OPEN MARKET VERSION

Data Sheet 6 V 1.2, 2021-03 OPEN MARKET VERSION

Data Sheet 7 V 1.2, 2021-03

1 Summary of Features

The TC38x product family has the following features:

• High Performance Microcontroller with four CPU cores
• Four 32-bit super-scalar TriCo re CPUs (TC1.6.2P), each having the following features: – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Multiply-accumulate u nit able to sustain 2 MAC operations per cycle – Fully pipelined Floating point unit (FPU) – up to 300 MHz operation at full temperature range – up to 240/96 Kbyte Data Scratch-Pad RAM (DSPR) – up to 64 Kbyte Instructio n Scratch-Pad RAM (PSPR) – up to 64 Kbyte Data RAM (DLMU) – 32 Kbyte Instruction Cache (ICACHE) – 16 Kbyte Data Cache (DCACHE)
• Lockstepped shadow cores for two TC1.6.2P
• Multiple on-chip memories – All embedded NVM and S RAM are ECC protected – up to 10 Mbyte Program Flash Memory (PFLASH) – up to 512 Kbyte Data Flash Mem ory (DFLASH 0) usable for EEPROM emulation – 128 Kbyte Memory (LMU) – BootROM (BROM)
• 128-Channel DMA Controlle r with safe data transfer
• Sophisticated interrupt system (ECC protected)
• High performance on -chip bus structure – 64-bit Cross Bar Interconnect (SRI) giving fast parallel acces s between bus masters, CPUs and memories – 32-bit System Peripheral Bus ( SPB) for on-chip peripheral and functional units – SRI to SPB bus br idges (SFI Bridge)
• Optional Hardware Security Module (HSM) on some variants
• Safety Management Unit (SMU) handling safety monitor alarms
• Memory Test Unit with ECC, Memor y Initialization and MBIST functions (MTU)
• Hardware I/O Monitor (IOM) for checking of digital I/O
• Versatile On-chip Peripheral Units – 24 Asynchronous/Synchronous Serial Channels (ASCLIN) with hard ware LIN support (V1.3, V2.0, V2.1 and J2602) up to 50 MBaud – 5 Queued SPI Interface Channels (QSPI) with master and slave capability up to 50 Mbit/s – 1 High Speed Serial Link (HSSL) for serial inter-processor com munication up to 320 Mbit/s – 3 serial Micro Second Bus int erfaces (MSC) for serial port expansion to external power devices – 3 MCMCAN Modules with 4 CAN node s for high efficiency data handling via FIFO buffering – 25 Single Edge Nibble Transmissi on (SENT) channels for connection to sensors –2 F l e x R a yTM module with 2 channels (E-Ray) supporting V2.1 OPEN MARKET VERSION

Data Sheet 8 V 1.2, 2021-03 – One Generic Timer Module (GTM) p roviding a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management – One Capture / Compare 6 module (Two kernels CCU60 and CCU61) – One General Purpose 12 Timer Unit (GPT120) – 4 channel Peripheral Sensor Inte rface conforming to V1.3 (PSI5) – 1 Peripheral Sensor Interface with Serial PHY (PSI5-S) – 2 Inter-Integrated Cir cuit Bus Interface (I2C) conforming to V2.1 – 1 IEEE802.3 Ethernet MAC with RG MII, RMII and MII interfaces (ETH)

• Versatile Successive Approximation ADC (VADC) – Cluster of 16 independent ADC kernels – Input voltage range from 0 V to 5.5V (ADC supply)
• Delta-Sigma ADC (DSADC) – 10 channels
• Digital programmable I/O ports
• On-chip debug support for OCDS Level 1 (CPUs, DMA, On Chip Buses)
• multi-core debugging, real time tracing, and calibration
• four/five wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface
• Power Management System and on-chip regulators
• Clock Generation Unit with Sy stem PLL and Peripheral PLL
• Embedded Voltage Regulator
• Qualified for automotive applicat ion according to AEC-Q100 (only applicable after delivery release of the corresponding sales codes)
• ISO 26262 Safety Element out of Context for safety requirements up to ASIL D (only applicable for sales codes listed within a released Safety Package Release Note from IFX) OPEN MARKET VERSION

Data Sheet 9 V 1.2, 2021-03

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies:

• The derivative itself, i.e. its function set, the temperature range, and the supply voltage
• The package and the type of delivery. Table 1-1 Platform Feature Overview Feature TC38x CPUs Type TC1.6.2 Cores / Checker Cores 4 / 2 Max. Freq. 300 MHz Cache per CPU Program 32 KB Data 16 KB SRAM per CPU PSPR 64 KB DSPR 240 KB for CP U0,1 / 96 KB else DLMU 64 KB SRAM global LMU 128 KB DAM 64 KB Extension Memory TCM - MB XCM -M B XTM -K B Program Flash Size 10 MB Banks 3 x 3 MB, 1 x 1 MB Data Flash Size (single-ended) 512 KB (DF0) + 128 KB (DF1) DMA Channels 128 CONVCTRL Modules 1 EVADC Primary Groups/Channels 8 / 64 Secondary Groups/Channels 4 / 64 Fast Compare Channels 4 EDSADC Channels 10 OPEN MARKET VERSION

Data Sheet 10 V 1.2, 2021-03 GTM Clusters 9 (5 @ 200MHz, 4 @ 100MHz) TIM (8 ch) 7 TOM (16 ch) 5 ATOM (8 ch) 9 MCS (8 ch) 7 CMU / ICM 1 / 1 PSM 2 TBU channels1) 4 (TBU0-3) SPE 4 CMP / MON 1 / 1 BRC / DPLL 1 / 1 CDTM modules 6 DTM modules 20 (8 on TOM, 12 on ATOM) Timer GPT12 1 CCU6 1 STM Modules 4 FlexRay Modules 2 Channels 2 CAN Modules 3 Nodes 3 x 4 of which support TT-CAN 1 QSPI Modules 5 HSCI Channels - ASCLIN Modules 24 I2C Interfaces 2 SENT Channels 25 PSI5 Modules 4 PSI5-S Modules 1 HSSL Channels 1 MSC Channels 3 SDMMC eMMC/SD Interface 0 Ethernet (10/100Mbit/1Gbit) Modules 1 FCE Modules 1 Safety Support SMU yes IOM yes SPU Modules - RIF Modules - HSPDM Modules - Table 1-1 Platform Feature Overview (cont’d) Feature TC38x OPEN MARKET VERSION

Data Sheet 11 V 1.2, 2021-03 Security HSM+ 1 Debug OCDS yes MCDS no miniMCDS yes miniMCDS TRAM 8 KB AGBT No Low Power Features Standby RAM 2 SCR yes Packages Type FBGA-516 / LFBGA-292 I/O Type 5V C M O S / 3 . 3V C M O S / L V D S Tambient Range −40 … +150°C 1) TBU3 has special purpose as angle clock. Table 1-1 Platform Feature Overview (cont’d) Feature TC38x OPEN MARKET VERSION

Pin Definition and Functions Data Sheet 12 V 1.2, 2021-03

2 Pin Definition and Functions

The following figures are showing the Logic Symbols for the package variants:

• BGA516 ( Figure 2-1)
• BGA292 ( Figure 2-2) Figure 2-1 Logic Symbol for the package variant BGA516 P20.9 P20.14 P15.0 P15.2 P15.4 P15.1 P15.3P14.0 P15.10 P15.11 P15.12 P15.6 P15.13 P15.7 P15.14 P15.15 P14.4 P15.8 P14.1 P14.3 P14.5 P15.5 P14.11 P14.12 P14.13 P14.7 P14.15 P14.6 P14.9P14.10 P14.8 P14.2 P13.0 P13.1 P13.2 P13.3 P13.9 P13.4 P13.5 P13.6 P13.7 P13.10P13.12 P13.13 P13.14 P13.11P13.15 P14.14 P12.0P12.1P11.0P11.1 P11.2 P11.4 P11.3 P11.6P11.5 P11.7 P11.9 P11.8 P11.10 P11.11 P11.12 P11.14 P11.13 P11.15 P10.0P10.3 P10.1 P10.9 P10.11 P10.4 P10.10 P10.15 P10.13 P10.2 P10.14 P10.6 P10.5P10.8 P10.7 P02.0 P02.2 P02.1 P02.5 P02.3 P02.13 P02.11 P02.12 P02.4 P02.15 P02.14 P02.6 P01.0 P02.7 P01.1 P02.8 P01.2 P02.9 P01.8 P01.9 P01.11 P02.10 P01.10 P00.0 P01.13 P01.4 P01.12 P01.3 P01.15 P01.6 P01.14 P01.5 P00.15 P01.7 P00.13 P00.14 P34.3 P34.2 P34.5 P33.8 P34.4 P32.2 P32.5 P32.4 P32.3 P32.7P32.6 P31.1 P31.0 P31.3 P31.2 P31.4 P31.5 P31.6 P31.7 P31.8 P31.10 P31.9 P31.12 P31.11 P31.14 P31.13 P31.15 P30.2P30.0 P30.1 P30.3 P30.5 P30.4 P30.8P30.6 P30.9P30.7 P30.10 P30.11 P30.14 P30.15P30.13 P30.12 P26.0 P25.0 P23.0 P23.1 P23.2 P25.2 P23.3 P25.1 P25.4 P23.5 P23.6P23.7 P25.3 P22.4 P25.7 P25.5 P25.8 P25.9 P25.10 P22.5 P25.11 P25.12P23.4 P25.14 P25.13 P25.15 P25.6 P24.1P24.0 P24.3P24.2 P24.5P24.4 P22.7 P24.9 P22.6 P24.8 P22.8 P22.2P22.3 P22.0P22.1 P24.6 P24.7 P24.11P24.10 P24.13 P22.11 P24.12 P22.10 P24.15 P22.9 P24.14 P21.0 P21.1 P21.2 P21.3 P21.4 P21.5 P20.0P20.2 P20.3 P21.7 / TDO P20.1 P20.8P20.7 P20.11 P21.6 / TDI P20.10 P20.13P20.12 P20.6 VFLEX VDDM VDDM VDDM VDDP3 VDDP3 VDDP3 VDDP3 VSSM VSSM VSSM P32.0 / VGATE VAREF VAGND VAREF VAGND NC NC NC NC NC NC NC NC NC NC NC NCNC NC NC NC NCNC NC NCNC NC NC NC NC NC NC NCNC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC1 NC1 NC1 NC1 NC1 NC1NC1 VEVRS B P32.1 / VGATE VAREF VAGND P33.0 P33.1 P33.2 P33.3 P33.4 P33.5 P33.6 P33.7 P34.1 P33.9 P33.10 P33.11 P33.12 P33.13 P33.14 P33.15 ESR1 ESR0 TRST TCK TMS PORSTP00.1 P00.2 P00.3 P00.4 P00.5 P00.6 P00.7 P00.8P00.9 P00.10 P00.11 P00.12 AN47AN46 AN45AN44 AN43 AN42 AN41 AN40 AN39 / P40.9 AN38 / P40.8 AN37 / P40.7 AN36 / P40.6 AN35 AN34 AN33 / P40.5 AN32 / P40.4 AN71 / P41.3 AN70 / P41.2 AN69 / P41.1 AN68 / P41.0 AN67 / P40.15 AN66 AN65 AN64 / P41.8 AN63 / P41.7 AN62 / P41.6 AN61AN60 AN59 AN58 AN57AN56 AN55 / P41.5 AN54 / P41.4 AN53 AN52 AN51 AN50 AN49 AN48 AN31 AN30 AN29 / P40.14 AN28 / P40.13 AN27 / P40.3 AN26 / P40.2 AN25 / P40.1 AN24 / P40.0 AN23 AN22 AN21 AN20 AN19 / P40.12 AN18 / P40.11 AN17 / P40.10 AN16 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 XTAL1XTAL2 VDD VDD VDD VDDVDD VDD VDD VDD VDD VDD VEXT VEXT VEXT VEXT VEXT VEXT VEXT VEXT VEXT VEXT VEXT VEXTVEXT VEXT VEXT VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSVSS VSS VSS VSS VSS VSSVSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VEXT A A B B C C D D E E F F G G H H J J K K L L M M N N P P R R T T U U V V W W Y Y AA AA AB AB AC AC AD AD AE AE AF AF AG AG AH AH AJ AJ AK AK TC38xpd - (top view) OPEN MARKET VERSION

Pin Definition and Functions Data Sheet 13 V 1.2, 2021-03 Figure 2-2 Logic Symbol for the package variant BGA292 P20.9 P20.14 P15.0 P15.2 P15.4 P15.1 P15.3P14.0 P15.6 P15.7 P14.4 P15.8 P14.1 P14.3 P14.5 P15.5 P14.7 P14.6 P14.9P14.10 P14.8 P14.2 P13.0 P13.1 P13.2 P13.3 P12.0P12.1P11.0P11.1 P11.2 P11.4 P11.3 P11.6P11.5 P11.7 P11.9 P11.8 P11.10 P11.11 P11.12 P11.14 P11.13 P11.15 P10.0P10.3 P10.1P10.4 P10.2P10.6 P10.5P10.8 P10.7 P02.0 P02.2 P02.1 P02.5 P02.3 P02.11 P02.4 P02.6 P02.7P02.8 P02.9 P02.10 P00.0 P01.4 P01.3 P01.6 P01.5 P01.7 P34.3 P34.2 P34.5 P33.8 P34.4 P32.2 P32.5 P32.4 P32.3 P32.7P32.6 P23.0 P23.1 P23.2 P23.3P23.5 P23.6P23.7 P22.4 P22.5 P23.4 P22.7P22.6 P22.8 P22.2P22.3 P22.0P22.1 P22.11P22.10 P22.9 P21.0 P21.1 P21.2 P21.3 P21.4 P21.5 P20.0P20.2 P20.3 P21.7 / TDO P20.1 P20.8P20.7 P20.11 P21.6 / TDI P20.10 P20.13P20.12 P20.6 VFLEX VDDM VDDP3 VDDP3 VSSM P32.0 / VGATE VAREF VAGND VAREF VAGND NC NC1 NC1 NC1 VEVRS B P32.1 / VGATE P33.0 P33.1 P33.2 P33.3 P33.4 P33.5 P33.6 P33.7 P34.1 P33.9 P33.10 P33.11 P33.12 P33.13 P33.14 P33.15 ESR1 ESR0 TRST TCK TMS PORSTP00.1 P00.2 P00.3 P00.4 P00.5 P00.6 P00.7 P00.8P00.9 P00.10 P00.11 P00.12 AN47AN46 AN45AN44 AN43 AN42 AN41 AN40 AN39 / P40.9 AN38 / P40.8 AN37 / P40.7 AN36 / P40.6 AN35 AN34 AN33 / P40.5 AN32 / P40.4 AN31 AN30 AN29 / P40.14 AN28 / P40.13 AN27 / P40.3 AN26 / P40.2 AN25 / P40.1 AN24 / P40.0 AN23 AN22 AN21 AN20 AN19 / P40.12 AN18 / P40.11 AN17 / P40.10 AN16 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 XTAL1XTAL2 VDD VDD VDD VDD VDD VDD VDD VDDVDD VDD VEXT VEXT VEXT VEXT VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VEXT A A B B C C D D E E F F G G H H J J K K L L M M N N P P R R T T U U V V W W Y Y TC38xpd - (top view) OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 14 V 1.2, 2021-03

2.1 BGA516 Package Varian t Pin Configuration

Table 2-1 Port 00 Functions Ball Symbol Ctrl. Buffer Type Function M6 P00.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN4_10 Mux input channel 4 of TIM module 5 GTM_TIM3_IN0_1 Mux input channel 0 of TIM module 3 GTM_TIM2_IN0_1 Mux input channel 0 of TIM module 2 CCU61_CTRAPA Trap input capture CCU60_T12HRE External timer start 12 MSC0_INJ0 Injection signal from port GETH_MDIOA MDIO Input P00.0 O0 General-purpose output GTM_TOUT9 O1 GTM muxed output IOM_REF0_9 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output ASCLIN3_ATX O3 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 4 Reserved CAN10_TXD O5 CAN transmit output node 0 —O 6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 GETH_MDIO O MDIO Output OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 15 V 1.2, 2021-03 M7 P00.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN5_11 Mux input channel 5 of TIM module 5 GTM_TIM3_IN1_1 Mux input channel 1 of TIM module 3 GTM_TIM2_IN1_1 Mux input channel 1 of TIM module 2 CCU60_CC60INB T12 capture input 60 ASCLIN3_ARXE Receive input EDSADC_DSCIN5A Modulator clock input, channel 5 CAN10_RXDA CAN receive input node 0 PSI5_RX0A RXD inputs (receive data) channel 0 CCU61_CC60INA T12 capture input 60 SENT_SENT0B Receive input channel 0 EDSADC_DSCIN7B Modulator clock input, channel 7 EVADC_G9CH11 AI Analog input channel 11, group 9 EDSADC_EDS5NA Negative analog input channel 5, pin A P00.1 O0 General-purpose output GTM_TOUT10 O1 GTM muxed output IOM_REF0_10 Reference input 0 ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 3 Reserved EDSADC_DSCOUT5 O4 Modulator clock output EDSADC_DSCOUT7 O5 Modulator clock output SENT_SPC0 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 16 V 1.2, 2021-03 N6 P00.2 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM5_IN6_11 Mux input channel 6 of TIM module 5 GTM_TIM3_IN1_2 Mux input channel 1 of TIM module 3 GTM_TIM2_IN1_2 Mux input channel 1 of TIM module 2 EDSADC_DSDIN7B Digital datastream input, channel 7 EDSADC_DSDIN5A Digital datastream input, channel 5 SENT_SENT1B Receive input channel 1 EVADC_G9CH10 AI Analog input channel 10, group 9 EDSADC_EDS5PA Positive analog input channel 5, pin A P00.2 O0 General-purpose output GTM_TOUT11 O1 GTM muxed output IOM_REF0_11 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output CAN21_TXD O3 CAN transmit output node 1 PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 QSPI3_SLSO4 O6 Master slave select output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 17 V 1.2, 2021-03 N7 P00.3 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM5_IN7_10 Mux input channel 7 of TIM module 5 GTM_TIM3_IN2_1 Mux input channel 2 of TIM module 3 GTM_TIM2_IN2_1 Mux input channel 2 of TIM module 2 CCU60_CC61INB T12 capture input 61 EDSADC_DSCIN3A Modulator clock input, channel 3 EDSADC_ITR5F Trigger/Gate input, channel 5 PSI5_RX1A RXD inputs (receive data) channel 1 CAN03_RXDA CAN receive input node 3 CAN21_RXDA CAN receive input node 1 PSI5S_RXA RX data input SENT_SENT2B Receive input channel 2 CCU61_CC61INA T12 capture input 61 ASCLIN12_ARXA Receive input EVADC_G9CH9 AI Analog input channel 9, group 9 EDSADC_EDS5NB Negative analog input channel 5, pin B P00.3 O0 General-purpose output GTM_TOUT12 O1 GTM muxed output IOM_REF0_12 Reference input 0 ASCLIN3_ASLSO O2 Slave select signal output ASCLIN12_ATX O3 Transmit output EDSADC_DSCOUT3 O4 Modulator clock output —O 5 Reserved SENT_SPC2 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 18 V 1.2, 2021-03 P6 P00.4 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM6_IN4_1 Mux input channel 4 of TIM module 6 GTM_TIM3_IN3_1 Mux input channel 3 of TIM module 3 GTM_TIM2_IN3_1 Mux input channel 3 of TIM module 2 SCU_E_REQ2_2 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT3B Receive input channel 3 EDSADC_DSDIN3A Digital datastream input, channel 3 EDSADC_SGNA Carrier sign signal input ASCLIN10_ARXA Receive input GTM_DTMA5_0 CDTM5_DTM4 GTM_DTMT3_0 CDTM3_DTM0 EVADC_G9CH8 AI Analog input channel 8, group 9 EDSADC_EDS5PB Positive analog input channel 5, pin B P00.4 O0 General-purpose output GTM_TOUT13 O1 GTM muxed output IOM_REF0_13 Reference input 0 PSI5S_TX O2 TX data output CAN11_TXD O3 CAN transmit output node 1 PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 —O 5 Reserved SENT_SPC3 O6 Transmit output CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 19 V 1.2, 2021-03 P7 P00.5 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN4_1 Mux input channel 4 of TIM module 3 GTM_TIM3_IN0_11 Mux input channel 0 of TIM module 3 GTM_TIM2_IN4_1 Mux input channel 4 of TIM module 2 CCU60_CC62INB T12 capture input 62 EDSADC_DSCIN2A Modulator clock input, channel 2 PSI5_RX2A RXD inputs (receive data) channel 2 CCU61_CC62INA T12 capture input 62 SENT_SENT4B Receive input channel 4 CAN11_RXDB CAN receive input node 1 ASCLIN12_ARXB Receive input GTM_DTMT1_1 CDTM1_DTM0 EVADC_G9CH7 AI Analog input channel 7, group 9 P00.5 O0 General-purpose output GTM_TOUT14 O1 GTM muxed output IOM_REF0_14 Reference input 0 EDSADC_CGPWMN O2 Negative carrier generator output QSPI3_SLSO3 O3 Master slave select output EDSADC_DSCOUT2 O4 Modulator clock output EVADC_FC0BFLOUT O5 Boundary flag output, FC channel 0 SENT_SPC4 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 20 V 1.2, 2021-03 P9 P00.6 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN5_1 Mux input channel 5 of TIM module 3 GTM_TIM3_IN1_14 Mux input channel 1 of TIM module 3 GTM_TIM2_IN5_1 Mux input channel 5 of TIM module 2 EDSADC_ITR4F Trigger/Gate input, channel 4 EDSADC_DSDIN2A Digital datastream input, channel 2 SENT_SENT5B Receive input channel 5 ASCLIN5_ARXA Receive input GTM_DTMT3_1 CDTM3_DTM0 EVADC_G9CH6 AI Analog input channel 6, group 9 P00.6 O0 General-purpose output GTM_TOUT15 O1 GTM muxed output IOM_REF0_15 Reference input 0 EDSADC_CGPWMP O2 Positive carrier generator output —O 3 Reserved PSI5_TX2 O4 TXD outputs (send data) IOM_REF1_15 Reference input 1 EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 SENT_SPC5 O6 Transmit output CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 21 V 1.2, 2021-03 R6 P00.7 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN6_1 Mux input channel 6 of TIM module 3 GTM_TIM3_IN2_11 Mux input channel 2 of TIM module 3 GTM_TIM2_IN6_1 Mux input channel 6 of TIM module 2 CCU61_CC60INC T12 capture input 60 SENT_SENT6B Receive input channel 6 EDSADC_DSCIN4A Modulator clock input, channel 4 GPT120_T2INA Trigger/gate input of timer T2 CCU61_CCPOS0A Hall capture input 0 CCU60_T12HRB External timer start 12 GTM_DTMT0_2 CDTM0_DTM0 EVADC_G9CH5 AI Analog input channel 5, group 9 EDSADC_EDS4NA Negative analog input channel 4, pin A P00.7 O0 General-purpose output GTM_TOUT16 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output EVADC_FC2BFLOUT O3 Boundary flag output, FC channel 2 EDSADC_DSCOUT4 O4 Modulator clock output EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 SENT_SPC6 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 22 V 1.2, 2021-03 R9 P00.8 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN7_1 Mux input channel 7 of TIM module 3 GTM_TIM3_IN3_11 Mux input channel 3 of TIM module 3 GTM_TIM2_IN7_1 Mux input channel 7 of TIM module 2 CCU61_CC61INC T12 capture input 61 SENT_SENT7B Receive input channel 7 EDSADC_DSDIN4A Digital datastream input, channel 4 GPT120_T2EUDA Count direction control input of timer T2 CCU61_CCPOS1A Hall capture input 1 CCU60_T13HRB External timer start 13 ASCLIN10_ARXB Receive input EVADC_G9CH4 AI Analog input channel 4, group 9 EDSADC_EDS4PA Positive analog input channel 4, pin A P00.8 O0 General-purpose output GTM_TOUT17 O1 GTM muxed output QSPI3_SLSO6 O2 Master slave select output ASCLIN10_ATX O3 Transmit output —O 4 Reserved EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 SENT_SPC7 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 23 V 1.2, 2021-03 R7 P00.9 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM4_IN0_7 Mux input channel 0 of TIM module 4 GTM_TIM1_IN0_1 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_1 Mux input channel 0 of TIM module 0 CCU61_CC62INC T12 capture input 62 SENT_SENT8B Receive input channel 8 CCU61_CCPOS2A Hall capture input 2 EDSADC_DSCIN1A Modulator clock input, channel 1 EDSADC_ITR3F Trigger/Gate input, channel 3 GPT120_T4EUDA Count direction control input of timer T4 CCU60_T13HRC External timer start 13 CCU60_T12HRC External timer start 12 ASCLIN13_ARXA Receive input EVADC_G9CH3 AI Analog input channel 3, group 9 EDSADC_EDS4NB Negative analog input channel 4, pin B P00.9 O0 General-purpose output GTM_TOUT18 O1 GTM muxed output QSPI3_SLSO7 O2 Master slave select output ASCLIN3_ARTS O3 Ready to send output EDSADC_DSCOUT1 O4 Modulator clock output ASCLIN4_ATX O5 Transmit output SENT_SPC8 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 24 V 1.2, 2021-03 R10 P00.10 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM4_IN1_11 Mux input channel 1 of TIM module 4 GTM_TIM1_IN1_1 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_1 Mux input channel 1 of TIM module 0 SENT_SENT9B Receive input channel 9 EDSADC_DSDIN1A Digital datastream input, channel 1 EVADC_G9CH2 AI Analog input channel 2, group 9 EDSADC_EDS4PB Positive analog input channel 4, pin B P00.10 O0 General-purpose output GTM_TOUT19 O1 GTM muxed output ASCLIN4_ASCLK O2 Shift clock output ASCLIN13_ATX O3 Transmit output —O 4 Reserved —O 5 Reserved SENT_SPC9 O6 Transmit output CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 T6 P00.11 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM4_IN2_11 Mux input channel 2 of TIM module 4 GTM_TIM1_IN2_1 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_1 Mux input channel 2 of TIM module 0 CCU60_CTRAPA Trap input capture EDSADC_DSCIN0A Modulator clock input, channel 0 CCU61_T12HRE External timer start 12 SENT_SENT10B Receive input channel 10 ASCLIN13_ARXB Receive input EVADC_G9CH1 AI Analog input channel 1, group 9 EVADC_FC3CH0 Analog input FC channel 3 P00.11 O0 General-purpose output GTM_TOUT20 O1 GTM muxed output ASCLIN4_ASLSO O2 Slave select signal output ASCLIN13_ATX O3 Transmit output EDSADC_DSCOUT0 O4 Modulator clock output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 25 V 1.2, 2021-03 T7 P00.12 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM4_IN3_11 Mux input channel 3 of TIM module 4 GTM_TIM1_IN3_1 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_1 Mux input channel 3 of TIM module 0 ASCLIN3_ACTSA Clear to send input EDSADC_DSDIN0A Digital datastream input, channel 0 ASCLIN4_ARXA Receive input SENT_SENT11B Receive input channel 11 EVADC_G9CH0 AI Analog input channel 0, group 9 EVADC_FC2CH0 Analog input FC channel 2 P00.12 O0 General-purpose output GTM_TOUT21 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 T2 P00.13 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN5_2 Mux input channel 5 of TIM module 6 GTM_TIM5_IN0_1 Mux input channel 0 of TIM module 5 GTM_TIM4_IN0_1 Mux input channel 0 of TIM module 4 EDSADC_DSDIN6A Digital datastream input, channel 6 P00.13 O0 General-purpose output GTM_TOUT167 O1 GTM muxed output —O 2 Reserved —O 3 Reserved CCU_EXTCLK1 O4 External Clock 1 —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 26 V 1.2, 2021-03 U2 P00.14 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN6_2 Mux input channel 6 of TIM module 6 GTM_TIM5_IN7_1 Mux input channel 7 of TIM module 5 GTM_TIM4_IN7_1 Mux input channel 7 of TIM module 4 EDSADC_DSCIN6A Modulator clock input, channel 6 P00.14 O0 General-purpose output GTM_TOUT166 O1 GTM muxed output —O 2 Reserved —O 3 Reserved EDSADC_DSCOUT6 O4 Modulator clock output —O 5 Reserved —O 6 Reserved —O 7 Reserved U1 P00.15 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN7_2 Mux input channel 7 of TIM module 6 GTM_TIM5_IN1_1 Mux input channel 1 of TIM module 5 GTM_TIM4_IN1_1 Mux input channel 1 of TIM module 4 EDSADC_ITR6F Trigger/Gate input, channel 6 P00.15 O0 General-purpose output GTM_TOUT168 O1 GTM muxed output —O 2 Reserved —O 3 Reserved CCU_EXTCLK0 O4 External Clock 0 —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-1 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 27 V 1.2, 2021-03 Table 2-2 Port 01 Functions Ball Symbol Ctrl. Buffer Type Function J2 P01.0 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN4_1 Mux input channel 4 of TIM module 5 GTM_TIM4_IN4_1 Mux input channel 4 of TIM module 4 GTM_TIM2_IN6_13 Mux input channel 6 of TIM module 2 CAN21_RXDE CAN receive input node 1 EDSADC_ITR6E Trigger/Gate input, channel 6 CAN03_RXDF CAN receive input node 3 ASCLIN6_ARXB Receive input P01.0 O0 General-purpose output GTM_TOUT155 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved K1 P01.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN1_2 Mux input channel 1 of TIM module 5 GTM_TIM4_IN1_2 Mux input channel 1 of TIM module 4 EDSADC_ITR8E Trigger/Gate input, channel 8 ERAY1_RXDA1 Receive Channel A1 SENT_SENT15B Receive input channel 15 P01.1 O0 General-purpose output GTM_TOUT159 O1 GTM muxed output —O 2 Reserved —O 3 Reserved ASCLIN6_ATX O4 Transmit output —O 5 Reserved —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 28 V 1.2, 2021-03 K2 P01.2 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN5_1 Mux input channel 5 of TIM module 5 GTM_TIM4_IN5_1 Mux input channel 5 of TIM module 4 EDSADC_DSCIN7A Modulator clock input, channel 7 P01.2 O0 General-purpose output GTM_TOUT156 O1 GTM muxed output —O 2 Reserved CAN03_TXD O3 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 —O 4 Reserved CAN21_TXD O5 CAN transmit output node 1 EDSADC_DSCOUT7 O6 Modulator clock output —O 7 Reserved M10 P01.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN5_2 Mux input channel 5 of TIM module 4 GTM_TIM2_IN0_14 Mux input channel 0 of TIM module 2 GTM_TIM0_IN5_8 Mux input channel 5 of TIM module 0 QSPI3_SLSIB Slave select input EDSADC_ITR7F Trigger/Gate input, channel 7 EVADC_G9CH14 AI Analog input channel 14, group 9 P01.3 O0 General-purpose output GTM_TOUT111 O1 GTM muxed output —O 2 Reserved —O 3 Reserved QSPI3_SLSO9 O4 Master slave select output CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 —O 6 Reserved —O 7 Reserved Table 2-2 Port 01 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 29 V 1.2, 2021-03 M9 P01.4 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN6_2 Mux input channel 6 of TIM module 4 GTM_TIM2_IN1_14 Mux input channel 1 of TIM module 2 GTM_TIM0_IN6_8 Mux input channel 6 of TIM module 0 CAN01_RXDC CAN receive input node 1 EDSADC_ITR7E Trigger/Gate input, channel 7 EVADC_G9CH13 AI Analog input channel 13, group 9 P01.4 O0 General-purpose output GTM_TOUT112 O1 GTM muxed output —O 2 Reserved ASCLIN9_ASLSO O3 Slave select signal output QSPI3_SLSO10 O4 Master slave select output —O 5 Reserved —O 6 Reserved —O 7 Reserved N10 P01.5 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN3_2 Mux input channel 3 of TIM module 5 GTM_TIM2_IN3_7 Mux input channel 3 of TIM module 2 GTM_TIM2_IN2_7 Mux input channel 2 of TIM module 2 QSPI3_MRSTC Master SPI data input EDSADC_DSCIN8A Modulator clock input, channel 8 ASCLIN9_ARXA Receive input EVADC_G9CH12 AI Analog input channel 12, group 9 P01.5 O0 General-purpose output GTM_TOUT113 O1 GTM muxed output —O 2 Reserved —O 3 Reserved QSPI3_MRST O4 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 —O 5 Reserved EDSADC_DSCOUT8 O6 Modulator clock output —O 7 Reserved Table 2-2 Port 01 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 30 V 1.2, 2021-03 N9 P01.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN6_2 Mux input channel 6 of TIM module 5 GTM_TIM5_IN5_3 Mux input channel 5 of TIM module 5 GTM_TIM2_IN5_7 Mux input channel 5 of TIM module 2 QSPI3_MTSRC Slave SPI data input EDSADC_DSDIN8A Digital datastream input, channel 8 P01.6 O0 General-purpose output GTM_TOUT114 O1 GTM muxed output ASCLIN12_ATX O2 Transmit output ASCLIN9_ASCLK O3 Shift clock output QSPI3_MTSR O4 Master SPI data output —O 5 Reserved —O 6 Reserved —O 7 Reserved P10 P01.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN7_2 Mux input channel 7 of TIM module 5 GTM_TIM2_IN7_7 Mux input channel 7 of TIM module 2 QSPI3_SCLKC Slave SPI clock inputs EDSADC_ITR8F Trigger/Gate input, channel 8 ASCLIN9_ARXB Receive input P01.7 O0 General-purpose output GTM_TOUT115 O1 GTM muxed output —O 2 Reserved ASCLIN9_ATX O3 Transmit output QSPI3_SCLK O4 Master SPI clock output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-2 Port 01 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 31 V 1.2, 2021-03 L1 P01.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN4_2 Mux input channel 4 of TIM module 5 GTM_TIM5_IN0_10 Mux input channel 0 of TIM module 5 GTM_TIM4_IN4_2 Mux input channel 4 of TIM module 4 CAN00_RXDF CAN receive input node 0 ERAY1_RXDB1 Receive Channel B1 EDSADC_DSDIN9A Digital datastream input, channel 9 SENT_SENT17B Receive input channel 17 ASCLIN0_ARXC Receive input CAN20_RXDE CAN receive input node 0 ASCLIN7_ARXB Receive input P01.8 O0 General-purpose output GTM_TOUT162 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved L2 P01.9 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN2_1 Mux input channel 2 of TIM module 5 GTM_TIM5_IN1_11 Mux input channel 1 of TIM module 5 GTM_TIM4_IN2_1 Mux input channel 2 of TIM module 4 EDSADC_DSCIN9A Modulator clock input, channel 9 SENT_SENT16B Receive input channel 16 P01.9 O0 General-purpose output GTM_TOUT160 O1 GTM muxed output ASCLIN7_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved EDSADC_DSCOUT9 O6 Modulator clock output —O 7 Reserved Table 2-2 Port 01 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 32 V 1.2, 2021-03 M2 P01.10 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN5_2 Mux input channel 5 of TIM module 5 GTM_TIM5_IN2_9 Mux input channel 2 of TIM module 5 GTM_TIM4_IN5_3 Mux input channel 5 of TIM module 4 EDSADC_ITR9F Trigger/Gate input, channel 9 SENT_SENT18B Receive input channel 18 GTM_DTMT3_2 CDTM3_DTM0 P01.10 O0 General-purpose output GTM_TOUT163 O1 GTM muxed output ASCLIN7_ASCLK O2 Shift clock output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved M1 P01.11 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN7_3 Mux input channel 7 of TIM module 5 GTM_TIM5_IN3_11 Mux input channel 3 of TIM module 5 GTM_TIM4_IN7_2 Mux input channel 7 of TIM module 4 EDSADC_ITR9E Trigger/Gate input, channel 9 SENT_SENT19B Receive input channel 19 GTM_DTMA5_1 CDTM5_DTM4 P01.11 O0 General-purpose output GTM_TOUT165 O1 GTM muxed output ASCLIN7_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-2 Port 01 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 33 V 1.2, 2021-03 N2 P01.12 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN0_3 Mux input channel 0 of TIM module 6 GTM_TIM5_IN0_2 Mux input channel 0 of TIM module 5 GTM_TIM4_IN0_2 Mux input channel 0 of TIM module 4 P01.12 O0 General-purpose output GTM_TOUT158 O1 GTM muxed output ASCLIN7_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved ERAY1_TXDA O6 Transmit Channel A —O 7 Reserved N1 P01.13 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN1_3 Mux input channel 1 of TIM module 6 GTM_TIM5_IN3_1 Mux input channel 3 of TIM module 5 GTM_TIM4_IN3_1 Mux input channel 3 of TIM module 4 P01.13 O0 General-purpose output GTM_TOUT161 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 —O 3 Reserved CAN00_TXD O4 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 CAN20_TXD O5 CAN transmit output node 0 ERAY1_TXDB O6 Transmit Channel B —O 7 Reserved Table 2-2 Port 01 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 34 V 1.2, 2021-03 P2 P01.14 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN2_3 Mux input channel 2 of TIM module 6 GTM_TIM5_IN6_3 Mux input channel 6 of TIM module 5 GTM_TIM4_IN6_3 Mux input channel 6 of TIM module 4 P01.14 O0 General-purpose output GTM_TOUT164 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved ERAY1_TXENA O6 Transmit Enable Channel A —O 7 Reserved P1 P01.15 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN3_3 Mux input channel 3 of TIM module 6 GTM_TIM5_IN6_1 Mux input channel 6 of TIM module 5 GTM_TIM4_IN6_1 Mux input channel 6 of TIM module 4 EDSADC_DSDIN7A Digital datastream input, channel 7 P01.15 O0 General-purpose output GTM_TOUT157 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-2 Port 01 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 35 V 1.2, 2021-03 Table 2-3 Port 02 Functions Ball Symbol Ctrl. Buffer Type Function G6 P02.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_2 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_2 Mux input channel 0 of TIM module 0 CCU61_CC60INB T12 capture input 60 ASCLIN2_ARXG Receive input CCU60_CC60INA T12 capture input 60 SCU_E_REQ3_2 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GTM_DTMA0_0 CDTM0_DTM4 P02.0 O0 General-purpose output GTM_TOUT0 O1 GTM muxed output IOM_REF0_0 Reference input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO1 O3 Master slave select output EDSADC_CGPWMN O4 Negative carrier generator output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 ERAY0_TXDA O6 Transmit Channel A CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 36 V 1.2, 2021-03 H7 P02.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_2 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_2 Mux input channel 1 of TIM module 0 ERAY0_RXDA2 Receive Channel A2 ASCLIN2_ARXB Receive input CAN00_RXDA CAN receive input node 0 SCU_E_REQ2_1 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P02.1 O0 General-purpose output GTM_TOUT1 O1 GTM muxed output IOM_REF0_1 Reference input 0 QSPI4_SLSO7 O2 Master slave select output QSPI3_SLSO2 O3 Master slave select output EDSADC_CGPWMP O4 Positive carrier generator output —O 5 Reserved —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 37 V 1.2, 2021-03 H6 P02.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_2 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_2 Mux input channel 2 of TIM module 0 CCU61_CC61INB T12 capture input 61 CCU60_CC61INA T12 capture input 61 SENT_SENT14B Receive input channel 14 P02.2 O0 General-purpose output GTM_TOUT2 O1 GTM muxed output IOM_REF0_2 Reference input 0 ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI3_SLSO3 O3 Master slave select output PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ERAY0_TXDB O6 Transmit Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 38 V 1.2, 2021-03 J7 P02.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN3_2 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_2 Mux input channel 3 of TIM module 0 EDSADC_DSCIN5B Modulator clock input, channel 5 ERAY0_RXDB2 Receive Channel B2 CAN02_RXDB CAN receive input node 2 ASCLIN1_ARXG Receive input MSC1_SDI1 Upstream assynchronous input signal PSI5_RX0B RXD inputs (receive data) channel 0 SENT_SENT13B Receive input channel 13 P02.3 O0 General-purpose output GTM_TOUT3 O1 GTM muxed output IOM_REF0_3 Reference input 0 ASCLIN2_ASLSO O2 Slave select signal output QSPI3_SLSO4 O3 Master slave select output EDSADC_DSCOUT5 O4 Modulator clock output —O 5 Reserved —O 6 Reserved CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 39 V 1.2, 2021-03 J6 P02.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_1 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_1 Mux input channel 4 of TIM module 0 CCU61_CC62INB T12 capture input 62 EDSADC_DSDIN5B Digital datastream input, channel 5 QSPI3_SLSIA Slave select input CCU60_CC62INA T12 capture input 62 I2C0_SDAA Serial Data Input 0 CAN11_RXDA CAN receive input node 1 CAN0_ECTT1 External CAN time trigger input SENT_SENT12B Receive input channel 12 P02.4 O0 General-purpose output GTM_TOUT4 O1 GTM muxed output IOM_REF0_4 Reference input 0 ASCLIN2_ASCLK O2 Shift clock output QSPI3_SLSO0 O3 Master slave select output PSI5S_CLK O4 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. I2C0_SDA O5 Serial Data Output ERAY0_TXENA O6 Transmit Enable Channel A CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 40 V 1.2, 2021-03 K7 P02.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_1 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_1 Mux input channel 5 of TIM module 0 EDSADC_DSCIN4B Modulator clock input, channel 4 I2C0_SCLA Serial Clock Input 0 PSI5_RX1B RXD inputs (receive data) channel 1 PSI5S_RXB RX data input QSPI3_MRSTA Master SPI data input SENT_SENT3C Receive input channel 3 CAN0_ECTT2 External CAN time trigger input P02.5 O0 General-purpose output GTM_TOUT5 O1 GTM muxed output IOM_REF0_5 Reference input 0 CAN11_TXD O2 CAN transmit output node 1 QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 EDSADC_DSCOUT4 O4 Modulator clock output I2C0_SCL O5 Serial Clock Output ERAY0_TXENB O6 Transmit Enable Channel B CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 41 V 1.2, 2021-03 K6 P02.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN0_10 Mux input channel 0 of TIM module 3 GTM_TIM1_IN6_1 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_1 Mux input channel 6 of TIM module 0 CCU60_CC60INC T12 capture input 60 SENT_SENT2C Receive input channel 2 EDSADC_DSDIN4B Digital datastream input, channel 4 EDSADC_ITR5E Trigger/Gate input, channel 5 GPT120_T3INA Trigger/gate input of core timer T3 CCU60_CCPOS0A Hall capture input 0 CCU61_T12HRB External timer start 12 QSPI3_MTSRA Slave SPI data input P02.6 O0 General-purpose output GTM_TOUT6 O1 GTM muxed output IOM_REF0_6 Reference input 0 PSI5S_TX O2 TX data output QSPI3_MTSR O3 Master SPI data output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX00 O5 Control of external analog multiplexer interface 0 —O 6 Reserved CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 42 V 1.2, 2021-03 L7 P02.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN1_10 Mux input channel 1 of TIM module 3 GTM_TIM1_IN7_1 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_1 Mux input channel 7 of TIM module 0 CCU60_CC61INC T12 capture input 61 SENT_SENT1C Receive input channel 1 EDSADC_DSCIN3B Modulator clock input, channel 3 EDSADC_ITR4E Trigger/Gate input, channel 4 GPT120_T3EUDA Count direction control input of core timer T3 PSI5_RX2B RXD inputs (receive data) channel 2 CCU60_CCPOS1A Hall capture input 1 QSPI3_SCLKA Slave SPI clock inputs CCU61_T13HRB External timer start 13 P02.7 O0 General-purpose output GTM_TOUT7 O1 GTM muxed output IOM_REF0_7 Reference input 0 —O 2 Reserved QSPI3_SCLK O3 Master SPI clock output EDSADC_DSCOUT3 O4 Modulator clock output EVADC_EMUX01 O5 Control of external analog multiplexer interface 0 SENT_SPC1 O6 Transmit output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 43 V 1.2, 2021-03 L6 P02.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN2_10 Mux input channel 2 of TIM module 3 GTM_TIM3_IN0_2 Mux input channel 0 of TIM module 3 GTM_TIM2_IN0_2 Mux input channel 0 of TIM module 2 CCU60_CC62INC T12 capture input 62 SENT_SENT0C Receive input channel 0 CCU60_CCPOS2A Hall capture input 2 EDSADC_DSDIN3B Digital datastream input, channel 3 EDSADC_ITR3E Trigger/Gate input, channel 3 GPT120_T4INA Trigger/gate input of timer T4 CCU61_T12HRC External timer start 12 CCU61_T13HRC External timer start 13 GTM_DTMA0_1 CDTM0_DTM4 P02.8 O0 General-purpose output GTM_TOUT8 O1 GTM muxed output IOM_REF0_8 Reference input 0 QSPI3_SLSO5 O2 Master slave select output ASCLIN8_ASCLK O3 Shift clock output PSI5_TX2 O4 TXD outputs (send data) IOM_REF1_15 Reference input 1 EVADC_EMUX02 O5 Control of external analog multiplexer interface 0 GETH_MDC O6 MDIO clock CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 44 V 1.2, 2021-03 K9 P02.9 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN2_2 Mux input channel 2 of TIM module 4 GTM_TIM3_IN3_10 Mux input channel 3 of TIM module 3 GTM_TIM0_IN2_10 Mux input channel 2 of TIM module 0 SENT_SENT20B Receive input channel 20 ASCLIN8_ARXA Receive input P02.9 O0 General-purpose output GTM_TOUT116 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 ASCLIN8_ATX O3 Transmit output —O 4 Reserved CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 —O 6 Reserved —O 7 Reserved L10 P02.10 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN3_2 Mux input channel 3 of TIM module 4 GTM_TIM3_IN4_11 Mux input channel 4 of TIM module 3 GTM_TIM0_IN3_10 Mux input channel 3 of TIM module 0 ASCLIN2_ARXC Receive input CAN01_RXDE CAN receive input node 1 SENT_SENT21B Receive input channel 21 ASCLIN8_ARXB Receive input P02.10 O0 General-purpose output GTM_TOUT117 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 45 V 1.2, 2021-03 L9 P02.11 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN4_3 Mux input channel 4 of TIM module 4 GTM_TIM3_IN5_12 Mux input channel 5 of TIM module 3 GTM_TIM0_IN7_7 Mux input channel 7 of TIM module 0 SENT_SENT22B Receive input channel 22 EVADC_G9CH15 AI Analog input channel 15, group 9 P02.11 O0 General-purpose output GTM_TOUT118 O1 GTM muxed output —O 2 Reserved ASCLIN8_ASLSO O3 Slave select signal output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved F2 P02.12 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN0_3 Mux input channel 0 of TIM module 5 GTM_TIM4_IN0_3 Mux input channel 0 of TIM module 4 GTM_TIM3_IN6_12 Mux input channel 6 of TIM module 3 SENT_SENT23B Receive input channel 23 P02.12 O0 General-purpose output GTM_TOUT151 O1 GTM muxed output QSPI3_SLSO5 O2 Master slave select output QSPI4_SLSO4 O3 Master slave select output ASCLIN6_ASLSO O4 Slave select signal output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 46 V 1.2, 2021-03 F1 P02.13 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN2_2 Mux input channel 2 of TIM module 5 GTM_TIM4_IN2_3 Mux input channel 2 of TIM module 4 GTM_TIM3_IN7_11 Mux input channel 7 of TIM module 3 SENT_SENT24B Receive input channel 24 P02.13 O0 General-purpose output GTM_TOUT153 O1 GTM muxed output QSPI3_SLSO7 O2 Master slave select output QSPI4_SLSO6 O3 Master slave select output CAN00_TXD O4 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 CAN20_TXD O5 CAN transmit output node 0 —O 6 Reserved —O 7 Reserved G2 P02.14 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN3_3 Mux input channel 3 of TIM module 5 GTM_TIM4_IN3_3 Mux input channel 3 of TIM module 4 GTM_TIM2_IN4_14 Mux input channel 4 of TIM module 2 CAN20_RXDD CAN receive input node 0 CAN00_RXDH CAN receive input node 0 P02.14 O0 General-purpose output GTM_TOUT154 O1 GTM muxed output ASCLIN6_ASCLK O2 Shift clock output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 47 V 1.2, 2021-03 G1 P02.15 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN1_3 Mux input channel 1 of TIM module 5 GTM_TIM4_IN1_3 Mux input channel 1 of TIM module 4 GTM_TIM2_IN5_14 Mux input channel 5 of TIM module 2 P02.15 O0 General-purpose output GTM_TOUT152 O1 GTM muxed output QSPI3_SLSO6 O2 Master slave select output QSPI4_SLSO5 O3 Master slave select output ASCLIN6_ATX O4 Transmit output —O 5 Reserved ERAY1_TXENB O6 Transmit Enable Channel B —O 7 Reserved Table 2-4 Port 10 Functions Ball Symbol Ctrl. Buffer Type Function F12 P10.0 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN0_12 Mux input channel 0 of TIM module 4 GTM_TIM1_IN4_2 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_2 Mux input channel 4 of TIM module 0 GPT120_T6EUDB Count direction control input of core timer T6 ASCLIN11_ARXA Receive input GETH_RXERC Receive Error MII GTM_DTMA5_2 CDTM5_DTM4 P10.0 O0 General-purpose output GTM_TOUT102 O1 GTM muxed output ASCLIN11_ATX O2 Transmit output QSPI1_SLSO10 O3 Master slave select output —O 4 Reserved —O 5 Reserved ASCLIN22_ATX O6 Transmit output —O 7 Reserved Table 2-3 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 48 V 1.2, 2021-03 G12 P10.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN4_12 Mux input channel 4 of TIM module 4 GTM_TIM1_IN1_3 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_3 Mux input channel 1 of TIM module 0 GPT120_T5EUDB Count direction control input of timer T5 QSPI1_MRSTA Master SPI data input GTM_DTMT0_1 CDTM0_DTM0 P10.1 O0 General-purpose output GTM_TOUT103 O1 GTM muxed output QSPI1_MTSR O2 Master SPI data output QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 MSC0_EN1 O4 Chip Select EVADC_FC1BFLOUT O5 Boundary flag output, FC channel 1 —O 6 Reserved —O 7 Reserved F10 P10.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN5_12 Mux input channel 5 of TIM module 4 GTM_TIM1_IN2_3 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_3 Mux input channel 2 of TIM module 0 CAN02_RXDE CAN receive input node 2 MSC0_SDI1 Upstream assynchronous input signal QSPI1_SCLKA Slave SPI clock inputs GPT120_T6INB Trigger/gate input of core timer T6 SCU_E_REQ2_0 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GTM_DTMT2_2 CDTM2_DTM0 P10.2 O0 General-purpose output GTM_TOUT104 O1 GTM muxed output IOM_MON2_9 Monitor input 2 —O 2 Reserved QSPI1_SCLK O3 Master SPI clock output MSC0_EN0 O4 Chip Select EVADC_FC3BFLOUT O5 Boundary flag output, FC channel 3 —O 6 Reserved —O 7 Reserved Table 2-4 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 49 V 1.2, 2021-03 F11 P10.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN6_10 Mux input channel 6 of TIM module 4 GTM_TIM1_IN3_3 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_3 Mux input channel 3 of TIM module 0 QSPI1_MTSRA Slave SPI data input SCU_E_REQ3_0 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T5INB Trigger/gate input of timer T5 P10.3 O0 General-purpose output GTM_TOUT105 O1 GTM muxed output IOM_MON2_10 Monitor input 2 —O 2 Reserved QSPI1_MTSR O3 Master SPI data output MSC0_EN0 O4 Chip Select —O 5 Reserved CAN02_TXD O6 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 —O 7 Reserved G11 P10.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN7_3 Mux input channel 7 of TIM module 4 GTM_TIM1_IN6_2 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_2 Mux input channel 6 of TIM module 0 QSPI1_MTSRC Slave SPI data input CCU60_CCPOS0C Hall capture input 0 GPT120_T3INB Trigger/gate input of core timer T3 ASCLIN11_ARXB Receive input ASCLIN22_ARXA Receive input P10.4 O0 General-purpose output GTM_TOUT106 O1 GTM muxed output IOM_MON2_11 Monitor input 2 ASCLIN22_ATX O2 Transmit output QSPI1_SLSO8 O3 Master slave select output QSPI1_MTSR O4 Master SPI data output MSC0_EN0 O5 Chip Select —O 6 Reserved —O 7 Reserved Table 2-4 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 50 V 1.2, 2021-03 G10 P10.5 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM4_IN3_13 Mux input channel 3 of TIM module 4 GTM_TIM1_IN2_4 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_4 Mux input channel 2 of TIM module 0 PMS_HWCFG4IN HWCFG4 pin input CAN20_RXDA CAN receive input node 0 MSC0_INJ1 Injection signal from port ASCLIN22_ARXB Receive input P10.5 O0 General-purpose output GTM_TOUT107 O1 GTM muxed output IOM_REF2_9 Reference input 2 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO8 O3 Master slave select output QSPI1_SLSO9 O4 Master slave select output GPT120_T6OUT O5 External output for overflow/underflow detection of core timer T6 ASCLIN2_ASLSO O6 Slave select signal output PSI5_TX3 O7 TXD outputs (send data) Table 2-4 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 51 V 1.2, 2021-03 F9 P10.6 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM4_IN2_13 Mux input channel 2 of TIM module 4 GTM_TIM1_IN3_4 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_4 Mux input channel 3 of TIM module 0 PSI5_RX3C RXD inputs (receive data) channel 3 ASCLIN2_ARXD Receive input QSPI3_MTSRB Slave SPI data input PMS_HWCFG5IN HWCFG5 pin input ASCLIN23_ARXA Receive input P10.6 O0 General-purpose output GTM_TOUT108 O1 GTM muxed output IOM_REF2_10 Reference input 2 ASCLIN2_ASCLK O2 Shift clock output QSPI3_MTSR O3 Master SPI data output GPT120_T3OUT O4 External output for overflow/underflow detection of core timer T3 CAN20_TXD O5 CAN transmit output node 0 QSPI1_MRST O6 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 —O 7 Reserved Table 2-4 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 52 V 1.2, 2021-03 F8 P10.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_3 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_3 Mux input channel 0 of TIM module 0 GPT120_T3EUDB Count direction control input of core timer T3 ASCLIN2_ACTSA Clear to send input QSPI3_MRSTB Master SPI data input SCU_E_REQ0_2 ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CCU60_CCPOS1C Hall capture input 1 ASCLIN23_ARXB Receive input P10.7 O0 General-purpose output GTM_TOUT109 O1 GTM muxed output IOM_REF2_11 Reference input 2 ASCLIN23_ATX O2 Transmit output QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 —O 4 Reserved CAN20_TXD O5 CAN transmit output node 0 CAN12_TXD O6 CAN transmit output node 2 —O 7 Reserved Table 2-4 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 53 V 1.2, 2021-03 G9 P10.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN0_13 Mux input channel 0 of TIM module 4 GTM_TIM1_IN5_2 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_2 Mux input channel 5 of TIM module 0 CAN12_RXDB CAN receive input node 2 GPT120_T4INB Trigger/gate input of timer T4 QSPI3_SCLKB Slave SPI clock inputs SCU_E_REQ1_2 ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CCU60_CCPOS2C Hall capture input 2 CAN20_RXDB CAN receive input node 0 P10.8 O0 General-purpose output GTM_TOUT110 O1 GTM muxed output ASCLIN2_ARTS O2 Ready to send output QSPI3_SCLK O3 Master SPI clock output ASCLIN23_ATX O4 Transmit output —O 5 Reserved —O 6 Reserved —O 7 Reserved B8 P10.9 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN0_5 Mux input channel 0 of TIM module 6 GTM_TIM4_IN1_4 Mux input channel 1 of TIM module 4 GTM_TIM0_IN1_10 Mux input channel 1 of TIM module 0 SENT_SENT15C Receive input channel 15 ASCLIN6_ARXD Receive input P10.9 O0 General-purpose output GTM_TOUT265 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-4 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 54 V 1.2, 2021-03 B7 P10.10 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN1_5 Mux input channel 1 of TIM module 6 GTM_TIM4_IN2_4 Mux input channel 2 of TIM module 4 GTM_TIM0_IN2_11 Mux input channel 2 of TIM module 0 SENT_SENT16C Receive input channel 16 P10.10 O0 General-purpose output GTM_TOUT266 O1 GTM muxed output ASCLIN6_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved A7 P10.11 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN2_5 Mux input channel 2 of TIM module 6 GTM_TIM4_IN5_4 Mux input channel 5 of TIM module 4 GTM_TIM0_IN5_9 Mux input channel 5 of TIM module 0 SENT_SENT19C Receive input channel 19 P10.11 O0 General-purpose output GTM_TOUT269 O1 GTM muxed output ASCLIN6_ASCLK O2 Shift clock output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-4 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 55 V 1.2, 2021-03 A6 P10.13 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN3_5 Mux input channel 3 of TIM module 6 GTM_TIM4_IN4_4 Mux input channel 4 of TIM module 4 GTM_TIM0_IN4_9 Mux input channel 4 of TIM module 0 SENT_SENT18C Receive input channel 18 P10.13 O0 General-purpose output GTM_TOUT268 O1 GTM muxed output ASCLIN6_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved B5 P10.14 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN3_4 Mux input channel 3 of TIM module 4 GTM_TIM0_IN3_11 Mux input channel 3 of TIM module 0 SENT_SENT17C Receive input channel 17 P10.14 O0 General-purpose output GTM_TOUT267 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved A5 P10.15 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN6_4 Mux input channel 6 of TIM module 4 GTM_TIM0_IN6_9 Mux input channel 6 of TIM module 0 P10.15 O0 General-purpose output GTM_TOUT270 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-4 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 56 V 1.2, 2021-03 Table 2-5 Port 11 Functions Ball Symbol Ctrl. Buffer Type Function K15 P11.0 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN0_4 Mux input channel 0 of TIM module 4 GTM_TIM2_IN0_7 Mux input channel 0 of TIM module 2 ASCLIN3_ARXB Receive input GTM_DTMA2_1 CDTM2_DTM4 P11.0 O0 General-purpose output GTM_TOUT119 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 3 Reserved —O 4 Reserved CAN11_TXD O5 CAN transmit output node 1 GETH_TXD3 O6 Transmit Data —O 7 Reserved K14 P11.1 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN1_5 Mux input channel 1 of TIM module 4 GTM_TIM2_IN1_6 Mux input channel 1 of TIM module 2 P11.1 O0 General-purpose output GTM_TOUT120 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output ASCLIN3_ATX O3 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 4 Reserved CAN12_TXD O5 CAN transmit output node 2 GETH_TXD2 O6 Transmit Data —O 7 Reserved OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 57 V 1.2, 2021-03 F15 P11.2 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN1_3 Mux input channel 1 of TIM module 3 GTM_TIM2_IN1_3 Mux input channel 1 of TIM module 2 P11.2 O0 General-purpose output GTM_TOUT95 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO5 O3 Master slave select output QSPI1_SLSO5 O4 Master slave select output MSC0_EN1 O5 Chip Select GETH_TXD1 O6 Transmit Data CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 G15 P11.3 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN2_2 Mux input channel 2 of TIM module 3 GTM_TIM2_IN2_2 Mux input channel 2 of TIM module 2 MSC0_SDI3 Upstream assynchronous input signal QSPI1_MRSTB Master SPI data input P11.3 O0 General-purpose output GTM_TOUT96 O1 GTM muxed output —O 2 Reserved QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 ERAY0_TXDA O4 Transmit Channel A —O 5 Reserved GETH_TXD0 O6 Transmit Data CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 Table 2-5 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 58 V 1.2, 2021-03 J15 P11.4 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN2_5 Mux input channel 2 of TIM module 4 GTM_TIM2_IN2_6 Mux input channel 2 of TIM module 2 GETH_RXCLKB Receive Clock MII P11.4 O0 General-purpose output GTM_TOUT121 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output —O 3 Reserved —O 4 Reserved CAN13_TXD O5 CAN transmit output node 3 GETH_TXER O6 Transmit Error MII GETH_TXCLK O7 Transmit Clock Output for RGMII J13 P11.5 I SLOW / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN3_5 Mux input channel 3 of TIM module 4 GTM_TIM2_IN3_8 Mux input channel 3 of TIM module 2 GETH_TXCLKA Transmit Clock Input for MII GETH_GREFCLK Gigabit Reference Clock input for RGMII (125 MHz high precission) P11.5 O0 General-purpose output GTM_TOUT122 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved CAN20_TXD O5 CAN transmit output node 0 —O 6 Reserved —O 7 Reserved Table 2-5 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 59 V 1.2, 2021-03 J14 P11.6 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN3_2 Mux input channel 3 of TIM module 3 GTM_TIM2_IN3_2 Mux input channel 3 of TIM module 2 QSPI1_SCLKB Slave SPI clock inputs P11.6 O0 General-purpose output GTM_TOUT97 O1 GTM muxed output ERAY0_TXENB O2 Transmit Enable Channel B QSPI1_SCLK O3 Master SPI clock output ERAY0_TXENA O4 Transmit Enable Channel A MSC0_FCLP O5 Shift-clock direct part of the differential signal GETH_TXEN O6 Transmit Enable MII and RMII GETH_TCTL Transmit Control for RGMII CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 K13 P11.7 I SLOW / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN4_5 Mux input channel 4 of TIM module 4 GTM_TIM2_IN4_7 Mux input channel 4 of TIM module 2 GETH_RXD3A Receive Data 3 MII and RGMII (RGMII can use RXD3A only) CAN11_RXDD CAN receive input node 1 P11.7 O0 General-purpose output GTM_TOUT123 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-5 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 60 V 1.2, 2021-03 K12 P11.8 I SLOW / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN5_5 Mux input channel 5 of TIM module 4 GTM_TIM2_IN5_8 Mux input channel 5 of TIM module 2 GETH_RXD2A Receive Data 2 MII and RGMII (RGMII can use RXD2A only) CAN12_RXDD CAN receive input node 2 P11.8 O0 General-purpose output GTM_TOUT124 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved F14 P11.9 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN4_2 Mux input channel 4 of TIM module 3 GTM_TIM2_IN4_2 Mux input channel 4 of TIM module 2 QSPI1_MTSRB Slave SPI data input ERAY0_RXDA1 Receive Channel A1 GETH_RXD1A Receive Data 1 MII, RMII and RGMII (RGMII can use RXD1A only) P11.9 O0 General-purpose output GTM_TOUT98 O1 GTM muxed output —O 2 Reserved QSPI1_MTSR O3 Master SPI data output —O 4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 Table 2-5 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 61 V 1.2, 2021-03 G14 P11.10 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN5_2 Mux input channel 5 of TIM module 3 GTM_TIM2_IN5_2 Mux input channel 5 of TIM module 2 GTM_TIM2_IN0_9 Mux input channel 0 of TIM module 2 CAN03_RXDD CAN receive input node 3 ERAY0_RXDB1 Receive Channel B1 ASCLIN1_ARXE Receive input SCU_E_REQ6_3 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) MSC0_SDI0 Upstream assynchronous input signal GETH_RXD0A Receive Data 0 MII, RMII and RGMII (RGMII can use RXD0A only) QSPI1_SLSIA Slave select input P11.10 O0 General-purpose output GTM_TOUT99 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO3 O3 Master slave select output QSPI1_SLSO3 O4 Master slave select output —O 5 Reserved —O 6 Reserved CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-5 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 62 V 1.2, 2021-03 F13 P11.11 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN6_2 Mux input channel 6 of TIM module 3 GTM_TIM3_IN0_14 Mux input channel 0 of TIM module 3 GTM_TIM2_IN6_2 Mux input channel 6 of TIM module 2 GETH_CRSDVA Carrier Sense / Data Valid combi-signal for RMII GETH_RXDVA Receive Data Valid MII GETH_CRSB Carrier Sense MII GETH_RCTLA Receive Control for RGMII P11.11 O0 General-purpose output GTM_TOUT100 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO4 O3 Master slave select output QSPI1_SLSO4 O4 Master slave select output MSC0_EN0 O5 Chip Select ERAY0_TXENB O6 Transmit Enable Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 G13 P11.12 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN7_2 Mux input channel 7 of TIM module 3 GTM_TIM2_IN7_2 Mux input channel 7 of TIM module 2 GETH_REFCLKA Reference Clock input for RMII (50 MHz) GETH_TXCLKB Transmit Clock Input for MII GETH_RXCLKA Receive Clock MII P11.12 O0 General-purpose output GTM_TOUT101 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 GTM_CLK2 O3 CGM generated clock ERAY0_TXDB O4 Transmit Channel B CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CCU_EXTCLK1 O6 External Clock 1 CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-5 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 63 V 1.2, 2021-03 K11 P11.13 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN6_5 Mux input channel 6 of TIM module 4 GTM_TIM2_IN6_7 Mux input channel 6 of TIM module 2 GETH_RXERA Receive Error MII I2C1_SDAA Serial Data Input 0 CAN13_RXDD CAN receive input node 3 P11.13 O0 General-purpose output GTM_TOUT125 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved I2C1_SDA O6 Serial Data Output —O 7 Reserved J12 P11.14 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN7_4 Mux input channel 7 of TIM module 4 GTM_TIM2_IN7_8 Mux input channel 7 of TIM module 2 GETH_CRSDVB Carrier Sense / Data Valid combi-signal for RMII GETH_RXDVB Receive Data Valid MII GETH_CRSA Carrier Sense MII I2C1_SCLA Serial Clock Input 0 CAN20_RXDF CAN receive input node 0 P11.14 O0 General-purpose output GTM_TOUT126 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved I2C1_SCL O6 Serial Clock Output —O 7 Reserved Table 2-5 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 64 V 1.2, 2021-03 J11 P11.15 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN7_5 Mux input channel 7 of TIM module 4 GTM_TIM0_IN7_8 Mux input channel 7 of TIM module 0 GETH_COLA Collision MII P11.15 O0 General-purpose output GTM_TOUT127 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-6 Port 12 Functions Ball Symbol Ctrl. Buffer Type Function K17 P12.0 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN0_5 Mux input channel 0 of TIM module 4 GTM_TIM3_IN0_7 Mux input channel 0 of TIM module 3 CAN00_RXDC CAN receive input node 0 GETH_RXCLKC Receive Clock MII GTM_DTMA4_0 CDTM4_DTM4 P12.0 O0 General-purpose output GTM_TOUT128 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved GETH_MDC O6 MDIO clock —O 7 Reserved Table 2-5 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 65 V 1.2, 2021-03 K16 P12.1 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN1_6 Mux input channel 1 of TIM module 4 GTM_TIM3_IN1_6 Mux input channel 1 of TIM module 3 GETH_MDIOC MDIO Input P12.1 O0 General-purpose output GTM_TOUT129 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved —O 7 Reserved GETH_MDIO O MDIO Output Table 2-7 Port 13 Functions Ball Symbol Ctrl. Buffer Type Function G17 P13.0 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM3_IN5_3 Mux input channel 5 of TIM module 3 GTM_TIM2_IN5_3 Mux input channel 5 of TIM module 2 ASCLIN10_ARXC Receive input ASCLIN21_ARXA Receive input P13.0 O0 General-purpose output GTM_TOUT91 O1 GTM muxed output ASCLIN10_ATX O2 Transmit output QSPI2_SCLKN O3 Master SPI clock output (LVDS N line) MSC0_EN1 O4 Chip Select MSC0_FCLN O5 Shift-clock inverted part of the differential signal —O 6 Reserved CAN10_TXD O7 CAN transmit output node 0 Table 2-6 Port 12 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 66 V 1.2, 2021-03 F17 P13.1 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM3_IN6_3 Mux input channel 6 of TIM module 3 GTM_TIM2_IN6_3 Mux input channel 6 of TIM module 2 I2C0_SCLB Serial Clock Input 1 CAN10_RXDD CAN receive input node 0 ASCLIN10_ARXD Receive input P13.1 O0 General-purpose output GTM_TOUT92 O1 GTM muxed output —O 2 Reserved QSPI2_SCLKP O3 Master SPI clock output (LVDS P line) —O 4 Reserved MSC0_FCLP O5 Shift-clock direct part of the differential signal I2C0_SCL O6 Serial Clock Output —O 7 Reserved G16 P13.2 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM3_IN7_3 Mux input channel 7 of TIM module 3 GTM_TIM2_IN7_3 Mux input channel 7 of TIM module 2 GPT120_CAPINA Trigger input to capture value of timer T5 into CAPREL register I2C0_SDAB Serial Data Input 1 P13.2 O0 General-purpose output GTM_TOUT93 O1 GTM muxed output ASCLIN10_ASCLK O2 Shift clock output QSPI2_MTSRN O3 Master SPI data output (LVDS N line) MSC0_FCLP O4 Shift-clock direct part of the differential signal MSC0_SON O5 Data output - inverted part of the differential signal I2C0_SDA O6 Serial Data Output ASCLIN21_ATX O7 Transmit output Table 2-7 Port 13 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 67 V 1.2, 2021-03 F16 P13.3 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM3_IN0_3 Mux input channel 0 of TIM module 3 GTM_TIM2_IN0_3 Mux input channel 0 of TIM module 2 ASCLIN21_ARXB Receive input P13.3 O0 General-purpose output GTM_TOUT94 O1 GTM muxed output ASCLIN10_ASLSO O2 Slave select signal output QSPI2_MTSRP O3 Master SPI data output (LVDS P line) —O 4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal ASCLIN21_ATX O6 Transmit output —O 7 Reserved B16 P13.4 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM6_IN0_4 Mux input channel 0 of TIM module 6 GTM_TIM5_IN3_4 Mux input channel 3 of TIM module 5 GTM_TIM3_IN3_8 Mux input channel 3 of TIM module 3 P13.4 O0 General-purpose output GTM_TOUT253 O1 GTM muxed output —O 2 Reserved —O 3 Reserved MSC2_EN0 O4 Chip Select MSC2_FCLN O5 Shift-clock inverted part of the differential signal —O 6 Reserved CAN23_TXD O7 CAN transmit output node 3 A16 P13.5 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM6_IN1_4 Mux input channel 1 of TIM module 6 GTM_TIM5_IN4_4 Mux input channel 4 of TIM module 5 GTM_TIM3_IN4_9 Mux input channel 4 of TIM module 3 CAN23_RXDD CAN receive input node 3 P13.5 O0 General-purpose output GTM_TOUT254 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved MSC2_FCLP O5 Shift-clock direct part of the differential signal —O 6 Reserved —O 7 Reserved Table 2-7 Port 13 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 68 V 1.2, 2021-03 B15 P13.6 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM6_IN2_4 Mux input channel 2 of TIM module 6 GTM_TIM5_IN5_4 Mux input channel 5 of TIM module 5 GTM_TIM3_IN5_10 Mux input channel 5 of TIM module 3 P13.6 O0 General-purpose output GTM_TOUT255 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved MSC2_SON O5 Data output - inverted part of the differential signal —O 6 Reserved —O 7 Reserved A15 P13.7 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM6_IN3_4 Mux input channel 3 of TIM module 6 GTM_TIM5_IN6_4 Mux input channel 6 of TIM module 5 GTM_TIM3_IN6_10 Mux input channel 6 of TIM module 3 P13.7 O0 General-purpose output GTM_TOUT256 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved MSC2_SOP O5 Data output - direct part of the differential signal —O 6 Reserved —O 7 Reserved Table 2-7 Port 13 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 69 V 1.2, 2021-03 A14 P13.9 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN4_4 Mux input channel 4 of TIM module 6 GTM_TIM4_IN7_6 Mux input channel 7 of TIM module 4 GTM_TIM2_IN7_12 Mux input channel 7 of TIM module 2 I2C1_SCLB Serial Clock Input 1 P13.9 O0 General-purpose output GTM_TOUT248 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 3 Reserved —O 4 Reserved CAN21_TXD O5 CAN transmit output node 1 I2C1_SCL O6 Serial Clock Output —O 7 Reserved B13 P13.10 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN5_4 Mux input channel 5 of TIM module 6 GTM_TIM5_IN1_5 Mux input channel 1 of TIM module 5 GTM_TIM3_IN1_8 Mux input channel 1 of TIM module 3 PSI5_RX3A RXD inputs (receive data) channel 3 P13.10 O0 General-purpose output GTM_TOUT251 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-7 Port 13 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 70 V 1.2, 2021-03 A13 P13.11 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN6_4 Mux input channel 6 of TIM module 6 GTM_TIM5_IN0_9 Mux input channel 0 of TIM module 5 GTM_TIM3_IN0_9 Mux input channel 0 of TIM module 3 ASCLIN0_ARXE Receive input ASCLIN7_ARXD Receive input P13.11 O0 General-purpose output GTM_TOUT250 O1 GTM muxed output —O 2 Reserved —O 3 Reserved PSI5_TX3 O4 TXD outputs (send data) —O 5 Reserved —O 6 Reserved —O 7 Reserved B12 P13.12 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN7_4 Mux input channel 7 of TIM module 6 GTM_TIM4_IN0_6 Mux input channel 0 of TIM module 4 GTM_TIM0_IN0_11 Mux input channel 0 of TIM module 0 ASCLIN3_ARXH Receive input I2C1_SDAB Serial Data Input 1 CAN21_RXDB CAN receive input node 1 P13.12 O0 General-purpose output GTM_TOUT249 O1 GTM muxed output ASCLIN7_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved I2C1_SDA O6 Serial Data Output —O 7 Reserved Table 2-7 Port 13 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 71 V 1.2, 2021-03 A12 P13.13 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN5_5 Mux input channel 5 of TIM module 5 GTM_TIM3_IN5_9 Mux input channel 5 of TIM module 3 MSC2_INJ0 Injection signal from port PSI5_RX3B RXD inputs (receive data) channel 3 P13.13 O0 General-purpose output GTM_TOUT262 O1 GTM muxed output ASCLIN7_ASCLK O2 Shift clock output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved B11 P13.14 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN2_4 Mux input channel 2 of TIM module 5 GTM_TIM3_IN2_7 Mux input channel 2 of TIM module 3 P13.14 O0 General-purpose output GTM_TOUT252 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved A11 P13.15 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN7_4 Mux input channel 7 of TIM module 5 GTM_TIM3_IN7_9 Mux input channel 7 of TIM module 3 P13.15 O0 General-purpose output GTM_TOUT264 O1 GTM muxed output ASCLIN7_ASLSO O2 Slave select signal output —O 3 Reserved PSI5_TX3 O4 TXD outputs (send data) —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-7 Port 13 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 72 V 1.2, 2021-03 Table 2-8 Port 14 Functions Ball Symbol Ctrl. Buffer Type Function G21 P14.0 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN3_5 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_5 Mux input channel 3 of TIM module 0 SENT_SENT17D Receive input channel 17 P14.0 O0 General-purpose output GTM_TOUT80 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 ERAY0_TXDA O3 Transmit Channel A ERAY0_TXDB O4 Transmit Channel B CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 73 V 1.2, 2021-03 F20 P14.1 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN4_3 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_3 Mux input channel 4 of TIM module 0 ERAY0_RXDA3 Receive Channel A3 ASCLIN0_ARXA Receive input SENT_SENT18D Receive input channel 18 ERAY0_RXDB3 Receive Channel B3 CAN01_RXDB CAN receive input node 1 SCU_E_REQ3_1 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) PMS_PINAWKP PINA ( P14.1) pin input P14.1 O0 General-purpose output GTM_TOUT81 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 K18 P14.2 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN5_3 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_3 Mux input channel 5 of TIM module 0 PMS_HWCFG2IN HWCFG2 pin input P14.2 O0 General-purpose output GTM_TOUT82 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO1 O3 Master slave select output —O 4 Reserved —O 5 Reserved ASCLIN2_ASCLK O6 Shift clock output —O 7 Reserved Table 2-8 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 74 V 1.2, 2021-03 G19 P14.3 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN6_3 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_3 Mux input channel 6 of TIM module 0 PMS_HWCFG3IN HWCFG3 pin input ASCLIN2_ARXA Receive input MSC0_SDI2 Upstream assynchronous input signal SCU_E_REQ1_0 ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P14.3 O0 General-purpose output GTM_TOUT83 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO3 O3 Master slave select output ASCLIN1_ASLSO O4 Slave select signal output ASCLIN3_ASLSO O5 Slave select signal output —O 6 Reserved —O 7 Reserved G20 P14.4 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN7_2 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_2 Mux input channel 7 of TIM module 0 PMS_HWCFG6IN HWCFG6 pin input GTM_DTMT0_0 CDTM0_DTM0 P14.4 O0 General-purpose output GTM_TOUT84 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved GETH_PPS O6 Pulse Per Second —O 7 Reserved Table 2-8 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 75 V 1.2, 2021-03 F19 P14.5 I FAST / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN0_4 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_4 Mux input channel 0 of TIM module 0 PMS_HWCFG1IN HWCFG1 pin input GTM_DTMA2_0 CDTM2_DTM4 P14.5 O0 General-purpose output GTM_TOUT85 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved ERAY0_TXDB O6 Transmit Channel B ERAY1_TXDB O7 Transmit Channel B G18 P14.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_4 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_4 Mux input channel 1 of TIM module 0 P14.6 O0 General-purpose output GTM_TOUT86 O1 GTM muxed output —O 2 Reserved QSPI2_SLSO2 O3 Master slave select output CAN13_TXD O4 CAN transmit output node 3 —O 5 Reserved ERAY0_TXENB O6 Transmit Enable Channel B ERAY1_TXENB O7 Transmit Enable Channel B Table 2-8 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 76 V 1.2, 2021-03 J18 P14.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN7_10 Mux input channel 7 of TIM module 4 GTM_TIM1_IN0_5 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_5 Mux input channel 0 of TIM module 0 ERAY0_RXDB0 Receive Channel B0 ERAY1_RXDB0 Receive Channel B0 CAN10_RXDB CAN receive input node 0 CAN13_RXDA CAN receive input node 3 ASCLIN9_ARXC Receive input ASCLIN20_ARXA Receive input P14.7 O0 General-purpose output GTM_TOUT87 O1 GTM muxed output ASCLIN0_ARTS O2 Ready to send output QSPI2_SLSO4 O3 Master slave select output ASCLIN9_ATX O4 Transmit output —O 5 Reserved —O 6 Reserved ASCLIN20_ATX O7 Transmit output F18 P14.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN2_3 Mux input channel 2 of TIM module 3 GTM_TIM2_IN2_3 Mux input channel 2 of TIM module 2 ERAY0_RXDA0 Receive Channel A0 CAN02_RXDD CAN receive input node 2 ASCLIN1_ARXD Receive input ERAY1_RXDA0 Receive Channel A0 P14.8 O0 General-purpose output GTM_TOUT88 O1 GTM muxed output ASCLIN5_ASLSO O2 Slave select signal output ASCLIN7_ASLSO O3 Slave select signal output —O 4 Reserved —O 5 Reserved —O 6 Reserved ASCLIN20_ATX O7 Transmit output Table 2-8 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 77 V 1.2, 2021-03 J17 P14.9 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN3_3 Mux input channel 3 of TIM module 3 GTM_TIM2_IN3_3 Mux input channel 3 of TIM module 2 ASCLIN0_ACTSA Clear to send input QSPI2_MRSTFN Master SPI data input (LVDS N line) ASCLIN9_ARXD Receive input ASCLIN20_ARXB Receive input P14.9 O0 General-purpose output GTM_TOUT89 O1 GTM muxed output CAN23_TXD O2 CAN transmit output node 3 MSC0_EN1 O3 Chip Select CAN10_TXD O4 CAN transmit output node 0 ERAY0_TXENB O5 Transmit Enable Channel B ERAY0_TXENA O6 Transmit Enable Channel A ERAY1_TXENA O7 Transmit Enable Channel A J16 P14.10 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN4_3 Mux input channel 4 of TIM module 3 GTM_TIM2_IN4_3 Mux input channel 4 of TIM module 2 CAN23_RXDA CAN receive input node 3 QSPI2_MRSTFP Master SPI data input (LVDS P line) P14.10 O0 General-purpose output GTM_TOUT90 O1 GTM muxed output —O 2 Reserved MSC0_EN0 O3 Chip Select ASCLIN1_ATX O4 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ERAY0_TXDA O6 Transmit Channel A ERAY1_TXDA O7 Transmit Channel A Table 2-8 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 78 V 1.2, 2021-03 A20 P14.11 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN1_4 Mux input channel 1 of TIM module 5 GTM_TIM3_IN1_9 Mux input channel 1 of TIM module 3 MSC2_SDI1 Upstream assynchronous input signal P14.11 O0 General-purpose output GTM_TOUT258 O1 GTM muxed output —O 2 Reserved —O 3 Reserved MSC2_EN2 O4 Chip Select MSC2_SOP O5 Data output - direct part of the differential signal —O 6 Reserved —O 7 Reserved B19 P14.12 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN4_3 Mux input channel 4 of TIM module 6 GTM_TIM5_IN4_5 Mux input channel 4 of TIM module 5 GTM_TIM3_IN4_8 Mux input channel 4 of TIM module 3 MSC2_SDI0 Upstream assynchronous input signal P14.12 O0 General-purpose output GTM_TOUT261 O1 GTM muxed output ASCLIN5_ASCLK O2 Shift clock output ASCLIN7_ASCLK O3 Shift clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved A19 P14.13 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN5_3 Mux input channel 5 of TIM module 6 GTM_TIM5_IN3_5 Mux input channel 3 of TIM module 5 GTM_TIM3_IN3_6 Mux input channel 3 of TIM module 3 P14.13 O0 General-purpose output GTM_TOUT260 O1 GTM muxed output —O 2 Reserved —O 3 Reserved MSC2_EN1 O4 Chip Select CAN22_TXD O5 CAN transmit output node 2 —O 6 Reserved —O 7 Reserved Table 2-8 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 79 V 1.2, 2021-03 B18 P14.14 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN6_3 Mux input channel 6 of TIM module 6 GTM_TIM5_IN2_3 Mux input channel 2 of TIM module 5 GTM_TIM3_IN2_8 Mux input channel 2 of TIM module 3 CAN22_RXDD CAN receive input node 2 P14.14 O0 General-purpose output GTM_TOUT259 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output ASCLIN7_ATX O3 Transmit output MSC2_EN0 O4 Chip Select CAN23_TXD O5 CAN transmit output node 3 —O 6 Reserved —O 7 Reserved A18 P14.15 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN7_3 Mux input channel 7 of TIM module 6 GTM_TIM5_IN6_5 Mux input channel 6 of TIM module 5 GTM_TIM3_IN6_9 Mux input channel 6 of TIM module 3 MSC2_INJ1 Injection signal from port ASCLIN5_ARXD Receive input ASCLIN7_ARXA Receive input CAN23_RXDC CAN receive input node 3 P14.15 O0 General-purpose output GTM_TOUT263 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-8 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 80 V 1.2, 2021-03 Table 2-9 Port 15 Functions Ball Symbol Ctrl. Buffer Type Function G25 P15.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN3_4 Mux input channel 3 of TIM module 3 GTM_TIM2_IN3_4 Mux input channel 3 of TIM module 2 P15.0 O0 General-purpose output GTM_TOUT71 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO13 O3 Master slave select output —O 4 Reserved CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output —O 7 Reserved F23 P15.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN4_4 Mux input channel 4 of TIM module 3 GTM_TIM2_IN4_4 Mux input channel 4 of TIM module 2 CAN02_RXDA CAN receive input node 2 ASCLIN1_ARXA Receive input QSPI2_SLSIB Slave select input SCU_E_REQ7_2 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.1 O0 General-purpose output GTM_TOUT72 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_SLSO5 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 81 V 1.2, 2021-03 H24 P15.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN5_4 Mux input channel 5 of TIM module 3 GTM_TIM2_IN5_4 Mux input channel 5 of TIM module 2 QSPI2_SLSIA Slave select input SENT_SENT10D Receive input channel 10 QSPI2_MRSTE Master SPI data input P15.2 O0 General-purpose output GTM_TOUT73 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SLSO0 O3 Master slave select output —O 4 Reserved CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output —O 7 Reserved G22 P15.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN6_4 Mux input channel 6 of TIM module 3 GTM_TIM2_IN6_4 Mux input channel 6 of TIM module 2 CAN01_RXDA CAN receive input node 1 ASCLIN0_ARXB Receive input QSPI2_SCLKA Slave SPI clock inputs P15.3 O0 General-purpose output GTM_TOUT74 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SCLK O3 Master SPI clock output —O 4 Reserved MSC0_EN1 O5 Chip Select —O 6 Reserved —O 7 Reserved Table 2-9 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 82 V 1.2, 2021-03 F22 P15.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN7_4 Mux input channel 7 of TIM module 3 GTM_TIM2_IN7_4 Mux input channel 7 of TIM module 2 I2C0_SCLC Serial Clock Input 2 QSPI2_MRSTA Master SPI data input SCU_E_REQ0_0 ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT11D Receive input channel 11 P15.4 O0 General-purpose output GTM_TOUT75 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MRST O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 ASCLIN19_ATX O4 Transmit output —O 5 Reserved I2C0_SCL O6 Serial Clock Output CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-9 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 83 V 1.2, 2021-03 K19 P15.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN0_4 Mux input channel 0 of TIM module 3 GTM_TIM2_IN0_4 Mux input channel 0 of TIM module 2 ASCLIN1_ARXB Receive input I2C0_SDAC Serial Data Input 2 QSPI2_MTSRA Slave SPI data input SCU_E_REQ4_3 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.5 O0 General-purpose output GTM_TOUT76 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MTSR O3 Master SPI data output —O 4 Reserved MSC0_EN0 O5 Chip Select I2C0_SDA O6 Serial Data Output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 F21 P15.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN2_14 Mux input channel 2 of TIM module 2 GTM_TIM1_IN0_6 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_6 Mux input channel 0 of TIM module 0 QSPI2_MTSRB Slave SPI data input ASCLIN19_ARXA Receive input P15.6 O0 General-purpose output GTM_TOUT77 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MTSR O3 Master SPI data output —O 4 Reserved QSPI2_SCLK O5 Master SPI clock output ASCLIN3_ASCLK O6 Shift clock output CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-9 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 84 V 1.2, 2021-03 J20 P15.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_5 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_5 Mux input channel 1 of TIM module 0 ASCLIN3_ARXA Receive input QSPI2_MRSTB Master SPI data input ASCLIN19_ARXB Receive input P15.7 O0 General-purpose output GTM_TOUT78 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MRST O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 ASCLIN19_ATX O4 Transmit output —O 5 Reserved —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 J19 P15.8 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_5 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_5 Mux input channel 2 of TIM module 0 QSPI2_SCLKB Slave SPI clock inputs SCU_E_REQ5_0 ERU Channel 5 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.8 O0 General-purpose output GTM_TOUT79 O1 GTM muxed output —O 2 Reserved QSPI2_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved ASCLIN3_ASCLK O6 Shift clock output CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-9 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 85 V 1.2, 2021-03 B24 P15.10 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM4_IN1_7 Mux input channel 1 of TIM module 4 GTM_TIM2_IN1_8 Mux input channel 1 of TIM module 2 P15.10 O0 General-purpose output GTM_TOUT242 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved A24 P15.11 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM4_IN2_6 Mux input channel 2 of TIM module 4 GTM_TIM2_IN2_8 Mux input channel 2 of TIM module 2 P15.11 O0 General-purpose output GTM_TOUT243 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved B23 P15.12 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM4_IN3_6 Mux input channel 3 of TIM module 4 GTM_TIM2_IN3_6 Mux input channel 3 of TIM module 2 P15.12 O0 General-purpose output GTM_TOUT244 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-9 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 86 V 1.2, 2021-03 A23 P15.13 I FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM4_IN4_6 Mux input channel 4 of TIM module 4 GTM_TIM2_IN4_9 Mux input channel 4 of TIM module 2 P15.13 O0 General-purpose output GTM_TOUT245 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved B22 P15.14 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN5_6 Mux input channel 5 of TIM module 4 GTM_TIM2_IN5_12 Mux input channel 5 of TIM module 2 P15.14 O0 General-purpose output GTM_TOUT246 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved A22 P15.15 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN6_6 Mux input channel 6 of TIM module 4 GTM_TIM2_IN6_9 Mux input channel 6 of TIM module 2 P15.15 O0 General-purpose output GTM_TOUT247 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-9 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 87 V 1.2, 2021-03 Table 2-10 Port 20 Functions Ball Symbol Ctrl. Buffer Type Function N25 P20.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_7 Mux input channel 6 of TIM module 1 GTM_TIM1_IN4_9 Mux input channel 4 of TIM module 1 GTM_TIM0_IN6_7 Mux input channel 6 of TIM module 0 CAN03_RXDC CAN receive input node 3 CCU_PAD_SYSCLK Sysclk input CAN21_RXDC CAN receive input node 1 CBS_TGI0 Trigger input SCU_E_REQ6_0 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T6EUDA Count direction control input of core timer T6 P20.0 O0 General-purpose output GTM_TOUT59 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output —O 4 Reserved HSCT0_SYSCLK_OUT O5 sys clock output —O 6 Reserved —O 7 Reserved CBS_TGO0 O Trigger output M24 P20.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN4_11 Mux input channel 4 of TIM module 4 GTM_TIM3_IN3_5 Mux input channel 3 of TIM module 3 GTM_TIM2_IN3_5 Mux input channel 3 of TIM module 2 CBS_TGI1 Trigger input GTM_DTMA1_1 CDTM1_DTM4 P20.1 O0 General-purpose output GTM_TOUT60 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved CBS_TGO1 O Trigger output OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 88 V 1.2, 2021-03 N24 P20.2 I S / PU / VEXT General-purpose input This pin is latched at power on reset release to enter test mode. TESTMODE Testmode Enable Input M25 P20.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN5_11 Mux input channel 5 of TIM module 4 GTM_TIM3_IN4_5 Mux input channel 4 of TIM module 3 GTM_TIM2_IN4_5 Mux input channel 4 of TIM module 2 ASCLIN3_ARXC Receive input GPT120_T6INA Trigger/gate input of core timer T6 P20.3 O0 General-purpose output GTM_TOUT61 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI0_SLSO9 O3 Master slave select output QSPI2_SLSO9 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CAN21_TXD O6 CAN transmit output node 1 —O 7 Reserved L22 P20.6 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN0_1 Mux input channel 0 of TIM module 6 GTM_TIM3_IN6_5 Mux input channel 6 of TIM module 3 GTM_TIM2_IN6_5 Mux input channel 6 of TIM module 2 CAN12_RXDA CAN receive input node 2 ASCLIN9_ARXE Receive input P20.6 O0 General-purpose output GTM_TOUT62 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output QSPI0_SLSO8 O3 Master slave select output QSPI2_SLSO8 O4 Master slave select output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-10 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 89 V 1.2, 2021-03 L24 P20.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN7_5 Mux input channel 7 of TIM module 3 GTM_TIM2_IN7_5 Mux input channel 7 of TIM module 2 GTM_TIM1_IN5_8 Mux input channel 5 of TIM module 1 GTM_TIM6_IN1_1 Mux input channel 1 of TIM module 6 CAN00_RXDB CAN receive input node 0 ASCLIN1_ACTSA Clear to send input ASCLIN9_ARXF Receive input P20.7 O0 General-purpose output GTM_TOUT63 O1 GTM muxed output ASCLIN9_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved CAN12_TXD O5 CAN transmit output node 2 —O 6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 L25 P20.8 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN2_1 Mux input channel 2 of TIM module 6 GTM_TIM1_IN7_3 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_3 Mux input channel 7 of TIM module 0 P20.8 O0 General-purpose output GTM_TOUT64 O1 GTM muxed output ASCLIN1_ASLSO O2 Slave select signal output QSPI0_SLSO0 O3 Master slave select output QSPI1_SLSO0 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-10 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 90 V 1.2, 2021-03 K22 P20.9 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN3_1 Mux input channel 3 of TIM module 6 GTM_TIM3_IN5_5 Mux input channel 5 of TIM module 3 GTM_TIM2_IN5_5 Mux input channel 5 of TIM module 2 CAN03_RXDE CAN receive input node 3 ASCLIN1_ARXC Receive input QSPI0_SLSIB Slave select input SCU_E_REQ7_0 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P20.9 O0 General-purpose output GTM_TOUT65 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO1 O3 Master slave select output QSPI1_SLSO1 O4 Master slave select output —O 5 Reserved —O 6 Reserved CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 K24 P20.10 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN6_6 Mux input channel 6 of TIM module 3 GTM_TIM2_IN6_6 Mux input channel 6 of TIM module 2 P20.10 O0 General-purpose output GTM_TOUT66 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO6 O3 Master slave select output QSPI2_SLSO7 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-10 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 91 V 1.2, 2021-03 K25 P20.11 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN7_6 Mux input channel 7 of TIM module 3 GTM_TIM2_IN7_6 Mux input channel 7 of TIM module 2 QSPI0_SCLKA Slave SPI clock inputs P20.11 O0 General-purpose output GTM_TOUT67 O1 GTM muxed output —O 2 Reserved QSPI0_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 J24 P20.12 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN0_5 Mux input channel 0 of TIM module 3 GTM_TIM2_IN0_5 Mux input channel 0 of TIM module 2 QSPI0_MRSTA Master SPI data input IOM_PIN_13 GPIO pad input to FPC P20.12 O0 General-purpose output GTM_TOUT68 O1 GTM muxed output IOM_MON0_13 Monitor input 0 —O 2 Reserved QSPI0_MRST O3 Slave SPI data output IOM_MON2_0 Monitor input 2 IOM_REF2_0 Reference input 2 QSPI0_MTSR O4 Master SPI data output —O 5 Reserved —O 6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 Table 2-10 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 92 V 1.2, 2021-03 J25 P20.13 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN1_4 Mux input channel 1 of TIM module 3 GTM_TIM2_IN1_4 Mux input channel 1 of TIM module 2 QSPI0_SLSIA Slave select input IOM_PIN_14 GPIO pad input to FPC P20.13 O0 General-purpose output GTM_TOUT69 O1 GTM muxed output IOM_MON0_14 Monitor input 0 —O 2 Reserved QSPI0_SLSO2 O3 Master slave select output QSPI1_SLSO2 O4 Master slave select output QSPI0_SCLK O5 Master SPI clock output —O 6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 H25 P20.14 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN2_4 Mux input channel 2 of TIM module 3 GTM_TIM2_IN2_4 Mux input channel 2 of TIM module 2 QSPI0_MTSRA Slave SPI data input IOM_PIN_15 GPIO pad input to FPC P20.14 O0 General-purpose output GTM_TOUT70 O1 GTM muxed output IOM_MON0_15 Monitor input 0 —O 2 Reserved QSPI0_MTSR O3 Master SPI data output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-10 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 93 V 1.2, 2021-03 Table 2-11 Port 21 Functions Ball Symbol Ctrl. Buffer Type Function R22 P21.0 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN0_11 Mux input channel 0 of TIM module 4 GTM_TIM3_IN4_6 Mux input channel 4 of TIM module 3 GTM_TIM2_IN4_6 Mux input channel 4 of TIM module 2 QSPI4_MRSTDN Master SPI data input (LVDS N line) DMU_FDEST Enter destructive debug mode ASCLIN11_ARXC Receive input ASCLIN17_ARXB Receive input P21.0 O0 General-purpose output GTM_TOUT51 O1 GTM muxed output ASCLIN11_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSM_HSM1 O Pin Output Value P22 P21.1 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN1_13 Mux input channel 1 of TIM module 4 GTM_TIM3_IN5_6 Mux input channel 5 of TIM module 3 GTM_TIM2_IN5_6 Mux input channel 5 of TIM module 2 QSPI4_MRSTDP Master SPI data input (LVDS P line) ASCLIN11_ARXD Receive input ASCLIN18_ARXA Receive input GTM_DTMA4_1 CDTM4_DTM4 P21.1 O0 General-purpose output GTM_TOUT52 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSM_HSM2 O Pin Output Value OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 94 V 1.2, 2021-03 R24 P21.2 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN4_11 Mux input channel 4 of TIM module 5 GTM_TIM1_IN0_7 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_7 Mux input channel 0 of TIM module 0 QSPI2_MRSTCN Master SPI data input (LVDS N line) SCU_EMGSTOP_POR T_B Emergency stop Port Pin B input request ASCLIN3_ARXGN Differential Receive input (low active) HSCT0_RXDN Rx data QSPI4_MRSTCN Master SPI data input (LVDS N line) ASCLIN11_ARXE Receive input GTM_DTMA1_0 CDTM1_DTM4 P21.2 O0 General-purpose output GTM_TOUT53 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved GETH_MDC O5 MDIO clock —O 6 Reserved —O 7 Reserved P24 P21.3 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN5_12 Mux input channel 5 of TIM module 5 GTM_TIM1_IN1_6 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_6 Mux input channel 1 of TIM module 0 QSPI2_MRSTCP Master SPI data input (LVDS P line) ASCLIN3_ARXGP Differential Receive input (high active) GETH_MDIOD MDIO Input HSCT0_RXDP Rx data QSPI4_MRSTCP Master SPI data input (LVDS P line) P21.3 O0 General-purpose output GTM_TOUT54 O1 GTM muxed output ASCLIN11_ASCLK O2 Shift clock output ASCLIN18_ATX O3 Transmit output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved GETH_MDIO O MDIO Output Table 2-11 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 95 V 1.2, 2021-03 R25 P21.4 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM5_IN6_12 Mux input channel 6 of TIM module 5 GTM_TIM1_IN2_6 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_6 Mux input channel 2 of TIM module 0 ASCLIN18_ARXB Receive input P21.4 O0 General-purpose output GTM_TOUT55 O1 GTM muxed output ASCLIN11_ASLSO O2 Slave select signal output ASCLIN18_ATX O3 Transmit output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSCT0_TXDN O Tx data P25 P21.5 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM5_IN7_11 Mux input channel 7 of TIM module 5 GTM_TIM1_IN3_6 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_6 Mux input channel 3 of TIM module 0 ASCLIN11_ARXF Receive input P21.5 O0 General-purpose output GTM_TOUT56 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output ASCLIN11_ATX O3 Transmit output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSCT0_TXDP O Tx data Table 2-11 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 96 V 1.2, 2021-03 N22 P21.6/TDI I FAST / PD / PU2 / VEXT / ES3 General-purpose input PD during Reset and in DAP/DAPE or JTAG mode. After Reset release and when not in DAP/DAPE or JTAG mode: PU. In Standby mode: HighZ. GTM_TIM4_IN2_12 Mux input channel 2 of TIM module 4 GTM_TIM1_IN4_8 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_8 Mux input channel 4 of TIM module 0 GPT120_T5EUDA Count direction control input of timer T5 ASCLIN3_ARXF Receive input CBS_TGI2 Trigger input TDI JTAG Module Data Input P21.6 O0 General-purpose output GTM_TOUT57 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved GPT120_T3OUT O7 External output for overflow/underflow detection of core timer T3 CBS_TGO2 O Trigger output DAP3 I/O DAP: DAP3 Data I/O Table 2-11 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 97 V 1.2, 2021-03 N21 P21.7/TDO I FAST / PU2 / VEXT / ES4 General-purpose input GTM_TIM4_IN3_12 Mux input channel 3 of TIM module 4 GTM_TIM1_IN5_7 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_7 Mux input channel 5 of TIM module 0 GPT120_T5INA Trigger/gate input of timer T5 CBS_TGI3 Trigger input GETH_RXERB Receive Error MII P21.7 O0 General-purpose output GTM_TOUT58 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved GPT120_T6OUT O7 External output for overflow/underflow detection of core timer T6 CBS_TGO3 O Trigger output DAP2 I/O DAP: DAP2 Data I/O TDO O JTAG Module Data Output Table 2-12 Port 22 Functions Ball Symbol Ctrl. Buffer Type Function W25 P22.0 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN1_7 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_7 Mux input channel 1 of TIM module 0 QSPI4_MTSRB Slave SPI data input ASCLIN6_ARXE Receive input P22.0 O0 General-purpose output GTM_TOUT47 O1 GTM muxed output ASCLIN3_ATXN O2 Differential Transmit output (low active) QSPI4_MTSR O3 Master SPI data output QSPI4_SCLKN O4 Master SPI clock output (LVDS N line) MSC1_FCLN O5 Shift-clock inverted part of the differential signal —O 6 Reserved ASCLIN6_ATX O7 Transmit output Table 2-11 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 98 V 1.2, 2021-03 W24 P22.1 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN0_8 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_8 Mux input channel 0 of TIM module 0 QSPI4_MRSTB Master SPI data input ASCLIN7_ARXE Receive input P22.1 O0 General-purpose output GTM_TOUT48 O1 GTM muxed output ASCLIN3_ATXP O2 Differential Transmit output (high active) QSPI4_MRST O3 Slave SPI data output IOM_MON2_4 Monitor input 2 IOM_REF2_4 Reference input 2 QSPI4_SCLKP O4 Master SPI clock output (LVDS P line) MSC1_FCLP O5 Shift-clock direct part of the differential signal —O 6 Reserved ASCLIN7_ATX O7 Transmit output Y25 P22.2 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN3_7 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_7 Mux input channel 3 of TIM module 0 QSPI4_SLSIB Slave select input P22.2 O0 General-purpose output GTM_TOUT49 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output QSPI4_SLSO3 O3 Master slave select output QSPI4_MTSRN O4 Master SPI data output (LVDS N line) MSC1_SON O5 Data output - inverted part of the differential signal —O 6 Reserved —O 7 Reserved Table 2-12 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 99 V 1.2, 2021-03 Y24 P22.3 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN4_4 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_4 Mux input channel 4 of TIM module 0 QSPI4_SCLKB Slave SPI clock inputs ASCLIN5_ARXC Receive input P22.3 O0 General-purpose output GTM_TOUT50 O1 GTM muxed output —O 2 Reserved QSPI4_SCLK O3 Master SPI clock output QSPI4_MTSRP O4 Master SPI data output (LVDS P line) MSC1_SOP O5 Data output - direct part of the differential signal —O 6 Reserved —O 7 Reserved W21 P22.4 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN0_8 Mux input channel 0 of TIM module 3 ASCLIN7_ARXF Receive input GTM_DTMA3_0 CDTM3_DTM4 P22.4 O0 General-purpose output GTM_TOUT130 O1 GTM muxed output ASCLIN4_ASLSO O2 Slave select signal output —O 3 Reserved QSPI0_SLSO12 O4 Master slave select output —O 5 Reserved CAN13_TXD O6 CAN transmit output node 3 —O 7 Reserved W22 P22.5 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN1_7 Mux input channel 1 of TIM module 3 QSPI0_MTSRC Slave SPI data input CAN13_RXDC CAN receive input node 3 P22.5 O0 General-purpose output GTM_TOUT131 O1 GTM muxed output ASCLIN4_ATX O2 Transmit output —O 3 Reserved QSPI0_MTSR O4 Master SPI data output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-12 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 100 V 1.2, 2021-03 V21 P22.6 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN2_6 Mux input channel 2 of TIM module 3 GTM_TIM2_IN6_14 Mux input channel 6 of TIM module 2 QSPI0_MRSTC Master SPI data input ASCLIN4_ARXC Receive input P22.6 O0 General-purpose output GTM_TOUT132 O1 GTM muxed output —O 2 Reserved —O 3 Reserved QSPI0_MRST O4 Slave SPI data output IOM_MON2_0 Monitor input 2 IOM_REF2_0 Reference input 2 CAN21_TXD O5 CAN transmit output node 1 —O 6 Reserved —O 7 Reserved V22 P22.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN3_7 Mux input channel 3 of TIM module 3 QSPI0_SCLKC Slave SPI clock inputs CAN21_RXDF CAN receive input node 1 P22.7 O0 General-purpose output GTM_TOUT133 O1 GTM muxed output ASCLIN4_ASCLK O2 Shift clock output ASCLIN17_ATX O3 Transmit output QSPI0_SCLK O4 Master SPI clock output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-12 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 101 V 1.2, 2021-03 U21 P22.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN0_4 Mux input channel 0 of TIM module 5 GTM_TIM3_IN4_7 Mux input channel 4 of TIM module 3 QSPI0_SCLKB Slave SPI clock inputs P22.8 O0 General-purpose output GTM_TOUT134 O1 GTM muxed output ASCLIN5_ASCLK O2 Shift clock output —O 3 Reserved QSPI0_SCLK O4 Master SPI clock output CAN22_TXD O5 CAN transmit output node 2 —O 6 Reserved —O 7 Reserved U22 P22.9 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN1_10 Mux input channel 1 of TIM module 5 GTM_TIM3_IN5_7 Mux input channel 5 of TIM module 3 QSPI0_MRSTB Master SPI data input ASCLIN4_ARXD Receive input CAN22_RXDE CAN receive input node 2 GTM_DTMA3_1 CDTM3_DTM4 P22.9 O0 General-purpose output GTM_TOUT135 O1 GTM muxed output —O 2 Reserved —O 3 Reserved QSPI0_MRST O4 Slave SPI data output IOM_MON2_0 Monitor input 2 IOM_REF2_0 Reference input 2 —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-12 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 102 V 1.2, 2021-03 T21 P22.10 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN2_8 Mux input channel 2 of TIM module 5 GTM_TIM3_IN6_7 Mux input channel 6 of TIM module 3 QSPI0_MTSRB Slave SPI data input P22.10 O0 General-purpose output GTM_TOUT136 O1 GTM muxed output ASCLIN4_ATX O2 Transmit output —O 3 Reserved QSPI0_MTSR O4 Master SPI data output CAN23_TXD O5 CAN transmit output node 3 —O 6 Reserved —O 7 Reserved T22 P22.11 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN3_10 Mux input channel 3 of TIM module 5 GTM_TIM3_IN7_7 Mux input channel 7 of TIM module 3 CAN23_RXDE CAN receive input node 3 ASCLIN17_ARXA Receive input P22.11 O0 General-purpose output GTM_TOUT137 O1 GTM muxed output ASCLIN4_ASLSO O2 Slave select signal output ASCLIN17_ATX O3 Transmit output QSPI0_SLSO10 O4 Master slave select output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-12 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 103 V 1.2, 2021-03 Table 2-13 Port 23 Functions Ball Symbol Ctrl. Buffer Type Function AC25 P23.0 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN7_1 Mux input channel 7 of TIM module 6 GTM_TIM1_IN5_4 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_4 Mux input channel 5 of TIM module 0 CAN10_RXDC CAN receive input node 0 P23.0 O0 General-purpose output GTM_TOUT41 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AB24 P23.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN6_1 Mux input channel 6 of TIM module 6 GTM_TIM1_IN6_4 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_4 Mux input channel 6 of TIM module 0 MSC1_SDI0 Upstream assynchronous input signal ASCLIN6_ARXF Receive input P23.1 O0 General-purpose output GTM_TOUT42 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output QSPI4_SLSO6 O3 Master slave select output GTM_CLK0 O4 CGM generated clock CAN10_TXD O5 CAN transmit output node 0 CCU_EXTCLK0 O6 External Clock 0 ASCLIN6_ASCLK O7 Shift clock output OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 104 V 1.2, 2021-03 AB25 P23.2 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN5_1 Mux input channel 5 of TIM module 6 GTM_TIM1_IN6_5 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_5 Mux input channel 6 of TIM module 0 ASCLIN7_ARXC Receive input P23.2 O0 General-purpose output GTM_TOUT43 O1 GTM muxed output —O 2 Reserved —O 3 Reserved CAN23_TXD O4 CAN transmit output node 3 CAN12_TXD O5 CAN transmit output node 2 —O 6 Reserved —O 7 Reserved AA24 P23.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN4_2 Mux input channel 4 of TIM module 6 GTM_TIM1_IN7_4 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_4 Mux input channel 7 of TIM module 0 MSC1_INJ0 Injection signal from port ASCLIN6_ARXA Receive input CAN12_RXDC CAN receive input node 2 CAN23_RXDB CAN receive input node 3 P23.3 O0 General-purpose output GTM_TOUT44 O1 GTM muxed output ASCLIN7_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-13 Port 23 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 105 V 1.2, 2021-03 AA25 P23.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN3_2 Mux input channel 3 of TIM module 6 GTM_TIM1_IN7_5 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_5 Mux input channel 7 of TIM module 0 P23.4 O0 General-purpose output GTM_TOUT45 O1 GTM muxed output ASCLIN6_ASLSO O2 Slave select signal output QSPI4_SLSO5 O3 Master slave select output —O 4 Reserved MSC1_EN0 O5 Chip Select —O 6 Reserved —O 7 Reserved AA22 P23.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN2_2 Mux input channel 2 of TIM module 6 GTM_TIM1_IN2_7 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_7 Mux input channel 2 of TIM module 0 ASCLIN16_ARXA Receive input P23.5 O0 General-purpose output GTM_TOUT46 O1 GTM muxed output ASCLIN6_ATX O2 Transmit output QSPI4_SLSO4 O3 Master slave select output —O 4 Reserved MSC1_EN1 O5 Chip Select CAN22_TXD O6 CAN transmit output node 2 —O 7 Reserved Y22 P23.6 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN1_2 Mux input channel 1 of TIM module 6 GTM_TIM4_IN2_7 Mux input channel 2 of TIM module 4 GTM_TIM1_IN2_10 Mux input channel 2 of TIM module 1 CAN22_RXDC CAN receive input node 2 P23.6 O0 General-purpose output GTM_TOUT138 O1 GTM muxed output ASCLIN16_ATX O2 Transmit output —O 3 Reserved QSPI0_SLSO11 O4 Master slave select output CAN11_TXD O5 CAN transmit output node 1 —O 6 Reserved —O 7 Reserved Table 2-13 Port 23 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 106 V 1.2, 2021-03 Y21 P23.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN0_2 Mux input channel 0 of TIM module 6 GTM_TIM4_IN3_7 Mux input channel 3 of TIM module 4 GTM_TIM1_IN3_10 Mux input channel 3 of TIM module 1 CAN11_RXDC CAN receive input node 1 ASCLIN16_ARXB Receive input P23.7 O0 General-purpose output GTM_TOUT139 O1 GTM muxed output ASCLIN16_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-14 Port 24 Functions Ball Symbol Ctrl. Buffer Type Function U29 P24.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN0_6 Mux input channel 0 of TIM module 6 GTM_TIM4_IN0_8 Mux input channel 0 of TIM module 4 P24.0 O0 General-purpose output GTM_TOUT222 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-13 Port 23 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 107 V 1.2, 2021-03 U30 P24.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN1_6 Mux input channel 1 of TIM module 6 GTM_TIM4_IN1_8 Mux input channel 1 of TIM module 4 P24.1 O0 General-purpose output GTM_TOUT223 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved T29 P24.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN2_6 Mux input channel 2 of TIM module 6 GTM_TIM4_IN2_8 Mux input channel 2 of TIM module 4 P24.2 O0 General-purpose output GTM_TOUT224 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved T30 P24.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN3_6 Mux input channel 3 of TIM module 6 GTM_TIM4_IN3_8 Mux input channel 3 of TIM module 4 P24.3 O0 General-purpose output GTM_TOUT225 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-14 Port 24 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 108 V 1.2, 2021-03 R29 P24.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN4_5 Mux input channel 4 of TIM module 6 GTM_TIM4_IN4_7 Mux input channel 4 of TIM module 4 P24.4 O0 General-purpose output GTM_TOUT226 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved R30 P24.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN5_5 Mux input channel 5 of TIM module 6 GTM_TIM4_IN5_7 Mux input channel 5 of TIM module 4 P24.5 O0 General-purpose output GTM_TOUT227 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved P29 P24.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN6_5 Mux input channel 6 of TIM module 6 GTM_TIM4_IN6_7 Mux input channel 6 of TIM module 4 P24.6 O0 General-purpose output GTM_TOUT228 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-14 Port 24 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 109 V 1.2, 2021-03 P30 P24.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN7_5 Mux input channel 7 of TIM module 6 GTM_TIM4_IN7_7 Mux input channel 7 of TIM module 4 P24.7 O0 General-purpose output GTM_TOUT229 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved N29 P24.8 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN0_5 Mux input channel 0 of TIM module 5 P24.8 O0 General-purpose output GTM_TOUT230 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved N30 P24.9 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN1_6 Mux input channel 1 of TIM module 5 P24.9 O0 General-purpose output GTM_TOUT231 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-14 Port 24 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 110 V 1.2, 2021-03 M29 P24.10 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN2_5 Mux input channel 2 of TIM module 5 P24.10 O0 General-purpose output GTM_TOUT232 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved M30 P24.11 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN3_6 Mux input channel 3 of TIM module 5 P24.11 O0 General-purpose output GTM_TOUT233 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved L29 P24.12 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN4_6 Mux input channel 4 of TIM module 5 P24.12 O0 General-purpose output GTM_TOUT234 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-14 Port 24 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 111 V 1.2, 2021-03 L30 P24.13 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN5_6 Mux input channel 5 of TIM module 5 P24.13 O0 General-purpose output GTM_TOUT235 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved K29 P24.14 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN6_6 Mux input channel 6 of TIM module 5 P24.14 O0 General-purpose output GTM_TOUT236 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved K30 P24.15 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN7_5 Mux input channel 7 of TIM module 5 P24.15 O0 General-purpose output GTM_TOUT237 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-14 Port 24 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 112 V 1.2, 2021-03 Table 2-15 Port 25 Functions Ball Symbol Ctrl. Buffer Type Function AG30 P25.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN0_7 Mux input channel 0 of TIM module 6 GTM_TIM3_IN0_12 Mux input channel 0 of TIM module 3 P25.0 O0 General-purpose output GTM_TOUT206 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AF30 P25.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN1_7 Mux input channel 1 of TIM module 6 GTM_TIM3_IN1_11 Mux input channel 1 of TIM module 3 P25.1 O0 General-purpose output GTM_TOUT207 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AF29 P25.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN2_7 Mux input channel 2 of TIM module 6 GTM_TIM3_IN2_9 Mux input channel 2 of TIM module 3 P25.2 O0 General-purpose output GTM_TOUT208 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 113 V 1.2, 2021-03 AE30 P25.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN3_7 Mux input channel 3 of TIM module 6 GTM_TIM3_IN3_9 Mux input channel 3 of TIM module 3 P25.3 O0 General-purpose output GTM_TOUT209 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AE29 P25.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN4_6 Mux input channel 4 of TIM module 6 GTM_TIM3_IN4_10 Mux input channel 4 of TIM module 3 P25.4 O0 General-purpose output GTM_TOUT210 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AD30 P25.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN5_6 Mux input channel 5 of TIM module 6 GTM_TIM3_IN5_11 Mux input channel 5 of TIM module 3 P25.5 O0 General-purpose output GTM_TOUT211 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-15 Port 25 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 114 V 1.2, 2021-03 W29 P25.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN6_6 Mux input channel 6 of TIM module 6 GTM_TIM3_IN6_14 Mux input channel 6 of TIM module 3 P25.6 O0 General-purpose output GTM_TOUT212 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AD29 P25.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN7_6 Mux input channel 7 of TIM module 6 GTM_TIM3_IN7_10 Mux input channel 7 of TIM module 3 P25.7 O0 General-purpose output GTM_TOUT213 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AC29 P25.8 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN0_9 Mux input channel 0 of TIM module 4 P25.8 O0 General-purpose output GTM_TOUT214 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-15 Port 25 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 115 V 1.2, 2021-03 AC30 P25.9 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN1_9 Mux input channel 1 of TIM module 4 P25.9 O0 General-purpose output GTM_TOUT215 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AB29 P25.10 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN2_9 Mux input channel 2 of TIM module 4 P25.10 O0 General-purpose output GTM_TOUT216 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AB30 P25.11 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN3_9 Mux input channel 3 of TIM module 4 P25.11 O0 General-purpose output GTM_TOUT217 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-15 Port 25 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 116 V 1.2, 2021-03 AA29 P25.12 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN4_8 Mux input channel 4 of TIM module 4 P25.12 O0 General-purpose output GTM_TOUT218 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AA30 P25.13 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN5_8 Mux input channel 5 of TIM module 4 P25.13 O0 General-purpose output GTM_TOUT219 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Y29 P25.14 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN6_8 Mux input channel 6 of TIM module 4 P25.14 O0 General-purpose output GTM_TOUT220 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-15 Port 25 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 117 V 1.2, 2021-03 Y30 P25.15 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN7_8 Mux input channel 7 of TIM module 4 P25.15 O0 General-purpose output GTM_TOUT221 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-16 Port 26 Functions Ball Symbol Ctrl. Buffer Type Function AG29 P26.0 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN6_9 Mux input channel 6 of TIM module 6 GTM_TIM3_IN6_11 Mux input channel 6 of TIM module 3 P26.0 O0 General-purpose output GTM_TOUT212 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-15 Port 25 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 118 V 1.2, 2021-03 Table 2-17 Port 30 Functions Ball Symbol Ctrl. Buffer Type Function AJ21 P30.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN0_10 Mux input channel 0 of TIM module 4 P30.0 O0 General-purpose output GTM_TOUT190 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AK21 P30.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN1_10 Mux input channel 1 of TIM module 4 P30.1 O0 General-purpose output GTM_TOUT191 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AJ22 P30.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN2_10 Mux input channel 2 of TIM module 4 P30.2 O0 General-purpose output GTM_TOUT192 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 119 V 1.2, 2021-03 AK22 P30.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN3_10 Mux input channel 3 of TIM module 4 P30.3 O0 General-purpose output GTM_TOUT193 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AJ23 P30.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN4_9 Mux input channel 4 of TIM module 4 P30.4 O0 General-purpose output GTM_TOUT194 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AK23 P30.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN5_9 Mux input channel 5 of TIM module 4 P30.5 O0 General-purpose output GTM_TOUT195 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-17 Port 30 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 120 V 1.2, 2021-03 AJ24 P30.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN6_9 Mux input channel 6 of TIM module 4 P30.6 O0 General-purpose output GTM_TOUT196 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AK24 P30.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN7_9 Mux input channel 7 of TIM module 4 P30.7 O0 General-purpose output GTM_TOUT197 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AJ25 P30.8 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN0_8 Mux input channel 0 of TIM module 6 GTM_TIM5_IN0_6 Mux input channel 0 of TIM module 5 P30.8 O0 General-purpose output GTM_TOUT198 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-17 Port 30 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 121 V 1.2, 2021-03 AK25 P30.9 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN1_8 Mux input channel 1 of TIM module 6 GTM_TIM5_IN1_7 Mux input channel 1 of TIM module 5 P30.9 O0 General-purpose output GTM_TOUT199 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AJ26 P30.10 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN2_8 Mux input channel 2 of TIM module 6 GTM_TIM5_IN2_6 Mux input channel 2 of TIM module 5 P30.10 O0 General-purpose output GTM_TOUT200 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AK26 P30.11 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN3_8 Mux input channel 3 of TIM module 6 GTM_TIM5_IN3_7 Mux input channel 3 of TIM module 5 P30.11 O0 General-purpose output GTM_TOUT201 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-17 Port 30 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 122 V 1.2, 2021-03 AJ27 P30.12 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN4_7 Mux input channel 4 of TIM module 6 GTM_TIM5_IN4_7 Mux input channel 4 of TIM module 5 P30.12 O0 General-purpose output GTM_TOUT202 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AK27 P30.13 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN5_7 Mux input channel 5 of TIM module 6 GTM_TIM5_IN5_7 Mux input channel 5 of TIM module 5 P30.13 O0 General-purpose output GTM_TOUT203 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AJ28 P30.14 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN6_7 Mux input channel 6 of TIM module 6 GTM_TIM5_IN6_7 Mux input channel 6 of TIM module 5 P30.14 O0 General-purpose output GTM_TOUT204 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-17 Port 30 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 123 V 1.2, 2021-03 AK28 P30.15 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN7_7 Mux input channel 7 of TIM module 6 GTM_TIM5_IN7_6 Mux input channel 7 of TIM module 5 P30.15 O0 General-purpose output GTM_TOUT205 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-18 Port 31 Functions Ball Symbol Ctrl. Buffer Type Function AJ12 P31.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN0_13 Mux input channel 0 of TIM module 2 P31.0 O0 General-purpose output GTM_TOUT174 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AK12 P31.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN1_9 Mux input channel 1 of TIM module 2 P31.1 O0 General-purpose output GTM_TOUT175 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-17 Port 30 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 124 V 1.2, 2021-03 AJ13 P31.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN2_9 Mux input channel 2 of TIM module 2 P31.2 O0 General-purpose output GTM_TOUT176 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AK13 P31.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN3_14 Mux input channel 3 of TIM module 2 P31.3 O0 General-purpose output GTM_TOUT177 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AJ14 P31.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN4_12 Mux input channel 4 of TIM module 2 P31.4 O0 General-purpose output GTM_TOUT178 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-18 Port 31 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 125 V 1.2, 2021-03 AK14 P31.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN5_13 Mux input channel 5 of TIM module 2 P31.5 O0 General-purpose output GTM_TOUT179 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AJ15 P31.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN6_12 Mux input channel 6 of TIM module 2 P31.6 O0 General-purpose output GTM_TOUT180 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AK15 P31.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN7_14 Mux input channel 7 of TIM module 2 P31.7 O0 General-purpose output GTM_TOUT181 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-18 Port 31 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 126 V 1.2, 2021-03 AJ16 P31.8 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN0_9 Mux input channel 0 of TIM module 6 GTM_TIM5_IN0_7 Mux input channel 0 of TIM module 5 SENT_SENT20C Receive input channel 20 P31.8 O0 General-purpose output GTM_TOUT182 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AK16 P31.9 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN1_9 Mux input channel 1 of TIM module 6 GTM_TIM5_IN1_8 Mux input channel 1 of TIM module 5 SENT_SENT21C Receive input channel 21 P31.9 O0 General-purpose output GTM_TOUT183 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AJ17 P31.10 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN2_9 Mux input channel 2 of TIM module 6 GTM_TIM5_IN2_7 Mux input channel 2 of TIM module 5 SENT_SENT22C Receive input channel 22 P31.10 O0 General-purpose output GTM_TOUT184 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-18 Port 31 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 127 V 1.2, 2021-03 AK17 P31.11 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN3_9 Mux input channel 3 of TIM module 6 GTM_TIM5_IN3_8 Mux input channel 3 of TIM module 5 SENT_SENT23C Receive input channel 23 P31.11 O0 General-purpose output GTM_TOUT185 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AJ18 P31.12 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN4_8 Mux input channel 4 of TIM module 6 GTM_TIM5_IN4_8 Mux input channel 4 of TIM module 5 SENT_SENT24C Receive input channel 24 P31.12 O0 General-purpose output GTM_TOUT186 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AK18 P31.13 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN5_8 Mux input channel 5 of TIM module 6 GTM_TIM5_IN5_8 Mux input channel 5 of TIM module 5 P31.13 O0 General-purpose output GTM_TOUT187 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-18 Port 31 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 128 V 1.2, 2021-03 AJ19 P31.14 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN6_8 Mux input channel 6 of TIM module 6 GTM_TIM5_IN6_8 Mux input channel 6 of TIM module 5 P31.14 O0 General-purpose output GTM_TOUT188 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AK19 P31.15 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN7_8 Mux input channel 7 of TIM module 6 GTM_TIM5_IN7_7 Mux input channel 7 of TIM module 5 P31.15 O0 General-purpose output GTM_TOUT189 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-18 Port 31 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 129 V 1.2, 2021-03 Table 2-19 Port 32 Functions Ball Symbol Ctrl. Buffer Type Function AE22 P32.0 I SLOW / PU1 / VEXT / ES General-purpose input P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC GTM_TIM3_IN2_5 Mux input channel 2 of TIM module 3 GTM_TIM2_IN2_5 Mux input channel 2 of TIM module 2 P32.0 O0 General-purpose output GTM_TOUT36 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved AD22 P32.1 I SLOW / PU1 / VEXT / ES General-purpose input P32.1 / External Pass Device gate control for EVRC GTM_TIM3_IN3_15 Mux input channel 3 of TIM module 3 P32.1 O0 General-purpose output GTM_TOUT37 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 130 V 1.2, 2021-03 AE23 P32.2 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN3_8 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_8 Mux input channel 3 of TIM module 0 CAN03_RXDB CAN receive input node 3 ASCLIN3_ARXD Receive input CAN21_RXDD CAN receive input node 1 P32.2 O0 General-purpose output GTM_TOUT38 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 3 Reserved —O 4 Reserved —O 5 Reserved PMS_DCDCSYNCO O6 DC-DC synchronization output —O 7 Reserved AE24 P32.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_5 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_5 Mux input channel 4 of TIM module 0 P32.3 O0 General-purpose output GTM_TOUT39 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 3 Reserved ASCLIN3_ASCLK O4 Shift clock output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CAN21_TXD O6 CAN transmit output node 1 —O 7 Reserved Table 2-19 Port 32 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 131 V 1.2, 2021-03 AD23 P32.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_5 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_5 Mux input channel 5 of TIM module 0 ASCLIN1_ACTSB Clear to send input MSC1_SDI2 Upstream assynchronous input signal ASCLIN15_ARXA Receive input P32.4 O0 General-purpose output GTM_TOUT40 O1 GTM muxed output PMS_DCDCSYNCO O2 DC-DC synchronization output —O 3 Reserved GTM_CLK1 O4 CGM generated clock MSC1_EN0 O5 Chip Select CCU_EXTCLK1 O6 External Clock 1 CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 AA20 P32.5 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN5_9 Mux input channel 5 of TIM module 5 GTM_TIM4_IN1_14 Mux input channel 1 of TIM module 4 GTM_TIM3_IN5_8 Mux input channel 5 of TIM module 3 SENT_SENT10C Receive input channel 10 P32.5 O0 General-purpose output GTM_TOUT140 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 —O 3 Reserved —O 4 Reserved —O 5 Reserved CAN02_TXD O6 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 —O 7 Reserved Table 2-19 Port 32 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 132 V 1.2, 2021-03 AB20 P32.6 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN6_9 Mux input channel 6 of TIM module 5 GTM_TIM4_IN4_15 Mux input channel 4 of TIM module 4 GTM_TIM3_IN6_8 Mux input channel 6 of TIM module 3 CAN02_RXDC CAN receive input node 2 CBS_TGI4 Trigger input ASCLIN2_ARXF Receive input ASCLIN6_ARXC Receive input SENT_SENT11C Receive input channel 11 P32.6 O0 General-purpose output GTM_TOUT141 O1 GTM muxed output —O 2 Reserved —O 3 Reserved QSPI2_SLSO12 O4 Master slave select output CAN22_TXD O5 CAN transmit output node 2 —O 6 Reserved —O 7 Reserved CBS_TGO4 O Trigger output AB21 P32.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN7_8 Mux input channel 7 of TIM module 5 GTM_TIM4_IN0_15 Mux input channel 0 of TIM module 4 GTM_TIM3_IN7_8 Mux input channel 7 of TIM module 3 CBS_TGI5 Trigger input CAN22_RXDB CAN receive input node 2 SENT_SENT12C Receive input channel 12 ASCLIN15_ARXB Receive input P32.7 O0 General-purpose output GTM_TOUT142 O1 GTM muxed output ASCLIN6_ATX O2 Transmit output —O 3 Reserved ASCLIN15_ATX O4 Transmit output —O 5 Reserved —O 6 Reserved —O 7 Reserved CBS_TGO5 O Trigger output Table 2-19 Port 32 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 133 V 1.2, 2021-03 Table 2-20 Port 33 Functions Ball Symbol Ctrl. Buffer Type Function AD15 P33.0 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN0_13 Mux input channel 0 of TIM module 3 GTM_TIM1_IN4_6 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_6 Mux input channel 4 of TIM module 0 EDSADC_ITR0E Trigger/Gate input, channel 0 SENT_SENT13C Receive input channel 13 IOM_PIN_0 GPIO pad input to FPC GTM_DTMT1_2 CDTM1_DTM0 EVADC_G10CH7 AI Analog input channel 7, group 10 P33.0 O0 General-purpose output GTM_TOUT22 O1 GTM muxed output IOM_MON0_0 Monitor input 0 IOM_GTM_0 GTM-provided inputs to EXOR combiner ASCLIN5_ATX O2 Transmit output —O 3 Reserved ASCLIN15_ATX O4 Transmit output —O 5 Reserved EVADC_FC2BFLOUT O6 Boundary flag output, FC channel 2 —O 7 Reserved OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 134 V 1.2, 2021-03 AE15 P33.1 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN1_15 Mux input channel 1 of TIM module 3 GTM_TIM1_IN5_6 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_6 Mux input channel 5 of TIM module 0 EDSADC_ITR1E Trigger/Gate input, channel 1 PSI5_RX0C RXD inputs (receive data) channel 0 EDSADC_DSCIN2B Modulator clock input, channel 2 SENT_SENT9C Receive input channel 9 ASCLIN8_ARXC Receive input IOM_PIN_1 GPIO pad input to FPC EVADC_G10CH6 AI Analog input channel 6, group 10 P33.1 O0 General-purpose output GTM_TOUT23 O1 GTM muxed output IOM_MON0_1 Monitor input 0 IOM_GTM_1 GTM-provided inputs to EXOR combiner ASCLIN3_ASLSO O2 Slave select signal output QSPI2_SCLK O3 Master SPI clock output EDSADC_DSCOUT2 O4 Modulator clock output EVADC_EMUX02 O5 Control of external analog multiplexer interface 0 —O 6 Reserved —O 7 Reserved Table 2-20 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 135 V 1.2, 2021-03 AD16 P33.2 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN2_14 Mux input channel 2 of TIM module 3 GTM_TIM1_IN6_6 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_6 Mux input channel 6 of TIM module 0 EDSADC_ITR2E Trigger/Gate input, channel 2 SENT_SENT8C Receive input channel 8 EDSADC_DSDIN2B Digital datastream input, channel 2 IOM_PIN_2 GPIO pad input to FPC EVADC_G10CH5 AI Analog input channel 5, group 10 P33.2 O0 General-purpose output GTM_TOUT24 O1 GTM muxed output IOM_MON0_2 Monitor input 0 IOM_GTM_2 GTM-provided inputs to EXOR combiner ASCLIN3_ASCLK O2 Shift clock output QSPI2_SLSO10 O3 Master slave select output PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 EVADC_EMUX01 O5 Control of external analog multiplexer interface 0 EVADC_FC3BFLOUT O6 Boundary flag output, FC channel 3 ASCLIN14_ATX O7 Transmit output Table 2-20 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 136 V 1.2, 2021-03 AE16 P33.3 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN3_12 Mux input channel 3 of TIM module 3 GTM_TIM1_IN7_6 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_6 Mux input channel 7 of TIM module 0 PSI5_RX1C RXD inputs (receive data) channel 1 SENT_SENT7C Receive input channel 7 EDSADC_DSCIN1B Modulator clock input, channel 1 ASCLIN14_ARXA Receive input IOM_PIN_3 GPIO pad input to FPC EVADC_G10CH4 AI Analog input channel 4, group 10 P33.3 O0 General-purpose output GTM_TOUT25 O1 GTM muxed output IOM_MON0_3 Monitor input 0 IOM_GTM_3 GTM-provided inputs to EXOR combiner ASCLIN5_ASCLK O2 Shift clock output QSPI4_SLSO2 O3 Master slave select output EDSADC_DSCOUT1 O4 Modulator clock output EVADC_EMUX00 O5 Control of external analog multiplexer interface 0 —O 6 Reserved ASCLIN14_ATX O7 Transmit output Table 2-20 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 137 V 1.2, 2021-03 AD17 P33.4 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM4_IN4_10 Mux input channel 4 of TIM module 4 GTM_TIM1_IN0_10 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_10 Mux input channel 0 of TIM module 0 EDSADC_ITR0F Trigger/Gate input, channel 0 SENT_SENT6C Receive input channel 6 EDSADC_DSDIN1B Digital datastream input, channel 1 CCU61_CTRAPC Trap input capture ASCLIN5_ARXB Receive input ASCLIN14_ARXB Receive input IOM_PIN_4 GPIO pad input to FPC GTM_DTMT2_0 CDTM2_DTM0 EVADC_G10CH3 AI Analog input channel 3, group 10 P33.4 O0 General-purpose output GTM_TOUT26 O1 GTM muxed output IOM_MON0_4 Monitor input 0 IOM_GTM_4 GTM-provided inputs to EXOR combiner ASCLIN2_ARTS O2 Ready to send output QSPI2_SLSO12 O3 Master slave select output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 EVADC_FC0BFLOUT O6 Boundary flag output, FC channel 0 CAN13_TXD O7 CAN transmit output node 3 Table 2-20 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 138 V 1.2, 2021-03 AE17 P33.5 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM4_IN5_10 Mux input channel 5 of TIM module 4 GTM_TIM1_IN1_8 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_8 Mux input channel 1 of TIM module 0 EDSADC_DSCIN0B Modulator clock input, channel 0 EDSADC_ITR1F Trigger/Gate input, channel 1 GPT120_T4EUDB Count direction control input of timer T4 PSI5S_RXC RX data input ASCLIN2_ACTSB Clear to send input CCU61_CCPOS2C Hall capture input 2 PSI5_RX2C RXD inputs (receive data) channel 2 SENT_SENT5C Receive input channel 5 CAN13_RXDB CAN receive input node 3 IOM_PIN_5 GPIO pad input to FPC EVADC_G10CH2 AI Analog input channel 2, group 10 P33.5 O0 General-purpose output GTM_TOUT27 O1 GTM muxed output IOM_MON0_5 Monitor input 0 IOM_GTM_5 GTM-provided inputs to EXOR combiner QSPI0_SLSO7 O2 Master slave select output QSPI1_SLSO7 O3 Master slave select output EDSADC_DSCOUT0 O4 Modulator clock output EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 EVADC_FC2BFLOUT O6 Boundary flag output, FC channel 2 ASCLIN5_ASLSO O7 Slave select signal output Table 2-20 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 139 V 1.2, 2021-03 AD18 P33.6 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN2_9 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_9 Mux input channel 2 of TIM module 0 EDSADC_ITR2F Trigger/Gate input, channel 2 GPT120_T2EUDB Count direction control input of timer T2 SENT_SENT4C Receive input channel 4 CCU61_CCPOS1C Hall capture input 1 EDSADC_DSDIN0B Digital datastream input, channel 0 ASCLIN8_ARXD Receive input IOM_PIN_6 GPIO pad input to FPC GTM_DTMT2_1 CDTM2_DTM0 EVADC_G10CH1 AI Analog input channel 1, group 10 P33.6 O0 General-purpose output GTM_TOUT28 O1 GTM muxed output IOM_MON0_6 Monitor input 0 IOM_GTM_6 GTM-provided inputs to EXOR combiner ASCLIN2_ASLSO O2 Slave select signal output QSPI2_SLSO11 O3 Master slave select output PSI5_TX2 O4 TXD outputs (send data) IOM_REF1_15 Reference input 1 EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 EVADC_FC1BFLOUT O6 Boundary flag output, FC channel 1 PSI5S_TX O7 TX data output Table 2-20 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 140 V 1.2, 2021-03 AE18 P33.7 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN3_9 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_9 Mux input channel 3 of TIM module 0 CAN00_RXDE CAN receive input node 0 GPT120_T2INB Trigger/gate input of timer T2 CCU61_CCPOS0C Hall capture input 0 SCU_E_REQ4_0 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT14C Receive input channel 14 IOM_PIN_7 GPIO pad input to FPC EVADC_G10CH0 AI Analog input channel 0, group 10 P33.7 O0 General-purpose output GTM_TOUT29 O1 GTM muxed output IOM_MON0_7 Monitor input 0 IOM_GTM_7 GTM-provided inputs to EXOR combiner ASCLIN2_ASCLK O2 Shift clock output QSPI4_SLSO7 O3 Master slave select output ASCLIN8_ATX O4 Transmit output —O 5 Reserved EVADC_FC3BFLOUT O6 Boundary flag output, FC channel 3 —O 7 Reserved Table 2-20 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 141 V 1.2, 2021-03 AD19 P33.8 I FAST / HighZ / VEVRSB General-purpose input GTM_TIM1_IN4_7 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_7 Mux input channel 4 of TIM module 0 ASCLIN2_ARXE Receive input SCU_EMGSTOP_POR T_A Emergency stop Port Pin A input request IOM_PIN_8 GPIO pad input to FPC P33.8 O0 General-purpose output GTM_TOUT30 O1 GTM muxed output IOM_MON0_8 Monitor input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI4_SLSO2 O3 Master slave select output —O 4 Reserved CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 SMU_FSP0 O FSP[1..0] Output Signals - Generated by SMU_core Table 2-20 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 142 V 1.2, 2021-03 AE19 P33.9 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN1_9 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_9 Mux input channel 1 of TIM module 0 IOM_PIN_9 GPIO pad input to FPC P33.9 O0 General-purpose output GTM_TOUT31 O1 GTM muxed output IOM_MON0_9 Monitor input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI4_SLSO1 O3 Master slave select output ASCLIN2_ASCLK O4 Shift clock output CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ATX O6 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-20 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 143 V 1.2, 2021-03 AD20 P33.10 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM4_IN4_14 Mux input channel 4 of TIM module 4 GTM_TIM1_IN0_9 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_9 Mux input channel 0 of TIM module 0 QSPI4_SLSIA Slave select input CAN01_RXDD CAN receive input node 1 ASCLIN0_ARXD Receive input IOM_PIN_10 GPIO pad input to FPC P33.10 O0 General-purpose output GTM_TOUT32 O1 GTM muxed output IOM_MON0_10 Monitor input 0 QSPI1_SLSO6 O2 Master slave select output QSPI4_SLSO0 O3 Master slave select output ASCLIN1_ASLSO O4 Slave select signal output PSI5S_CLK O5 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. —O 6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 SMU_FSP1 O FSP[1..0] Output Signals - Generated by SMU_core AE20 P33.11 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN2_8 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_8 Mux input channel 2 of TIM module 0 QSPI4_SCLKA Slave SPI clock inputs IOM_PIN_11 GPIO pad input to FPC P33.11 O0 General-purpose output GTM_TOUT33 O1 GTM muxed output IOM_MON0_11 Monitor input 0 ASCLIN1_ASCLK O2 Shift clock output QSPI4_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved EDSADC_CGPWMN O6 Negative carrier generator output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-20 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 144 V 1.2, 2021-03 AD21 P33.12 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN0_6 Mux input channel 0 of TIM module 3 GTM_TIM2_IN0_6 Mux input channel 0 of TIM module 2 QSPI4_MTSRA Slave SPI data input CAN00_RXDD CAN receive input node 0 PMS_PINBWKP PINB (P33.12) pin input IOM_PIN_12 GPIO pad input to FPC P33.12 O0 General-purpose output GTM_TOUT34 O1 GTM muxed output IOM_MON0_12 Monitor input 0 ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI4_MTSR O3 Master SPI data output ASCLIN1_ASCLK O4 Shift clock output CAN22_TXD O5 CAN transmit output node 2 EDSADC_CGPWMP O6 Positive carrier generator output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 Table 2-20 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 145 V 1.2, 2021-03 AE21 P33.13 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN1_5 Mux input channel 1 of TIM module 3 GTM_TIM2_IN1_5 Mux input channel 1 of TIM module 2 ASCLIN1_ARXF Receive input EDSADC_SGNB Carrier sign signal input QSPI4_MRSTA Master SPI data input MSC1_INJ1 Injection signal from port CAN22_RXDA CAN receive input node 2 P33.13 O0 General-purpose output GTM_TOUT35 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI4_MRST O3 Slave SPI data output IOM_MON2_4 Monitor input 2 IOM_REF2_4 Reference input 2 QSPI2_SLSO6 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-20 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 146 V 1.2, 2021-03 AA19 P33.14 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM5_IN0_8 Mux input channel 0 of TIM module 5 GTM_TIM4_IN5_14 Mux input channel 5 of TIM module 4 GTM_TIM2_IN0_8 Mux input channel 0 of TIM module 2 QSPI2_SCLKD Slave SPI clock inputs CBS_TGI6 Trigger input P33.14 O0 General-purpose output GTM_TOUT143 O1 GTM muxed output —O 2 Reserved QSPI2_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 CBS_TGO6 O Trigger output AB19 P33.15 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM5_IN1_9 Mux input channel 1 of TIM module 5 GTM_TIM4_IN6_12 Mux input channel 6 of TIM module 4 GTM_TIM2_IN1_7 Mux input channel 1 of TIM module 2 CBS_TGI7 Trigger input P33.15 O0 General-purpose output GTM_TOUT144 O1 GTM muxed output —O 2 Reserved QSPI2_SLSO11 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 CBS_TGO7 O Trigger output Table 2-20 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 147 V 1.2, 2021-03 Table 2-21 Port 34 Functions Ball Symbol Ctrl. Buffer Type Function AB16 P34.1 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM5_IN3_9 Mux input channel 3 of TIM module 5 GTM_TIM3_IN4_12 Mux input channel 4 of TIM module 3 GTM_TIM2_IN3_9 Mux input channel 3 of TIM module 2 EVADC_G10CH11 AI Analog input channel 11, group 10 P34.1 O0 General-purpose output GTM_TOUT146 O1 GTM muxed output ASCLIN4_ATX O2 Transmit output —O 3 Reserved CAN00_TXD O4 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 CAN20_TXD O5 CAN transmit output node 0 —O 6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 AA17 P34.2 I SLOW / PU1 / VEVRSB / ES General-purpose input GTM_TIM5_IN4_9 Mux input channel 4 of TIM module 5 GTM_TIM3_IN5_13 Mux input channel 5 of TIM module 3 GTM_TIM2_IN4_8 Mux input channel 4 of TIM module 2 ASCLIN4_ARXB Receive input CAN00_RXDG CAN receive input node 0 CAN20_RXDC CAN receive input node 0 EVADC_G10CH10 AI Analog input channel 10, group 10 P34.2 O0 General-purpose output GTM_TOUT147 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 148 V 1.2, 2021-03 AB17 P34.3 I SLOW / PU1 / VEVRSB / ES General-purpose input GTM_TIM5_IN5_10 Mux input channel 5 of TIM module 5 GTM_TIM3_IN6_13 Mux input channel 6 of TIM module 3 GTM_TIM2_IN5_9 Mux input channel 5 of TIM module 2 EVADC_G10CH9 AI Analog input channel 9, group 10 P34.3 O0 General-purpose output GTM_TOUT148 O1 GTM muxed output ASCLIN4_ASCLK O2 Shift clock output —O 3 Reserved QSPI2_SLSO10 O4 Master slave select output —O 5 Reserved —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 AA18 P34.4 I SLOW / PU1 / VEVRSB / ES General-purpose input GTM_TIM5_IN6_10 Mux input channel 6 of TIM module 5 GTM_TIM3_IN7_12 Mux input channel 7 of TIM module 3 GTM_TIM2_IN6_8 Mux input channel 6 of TIM module 2 QSPI2_MRSTD Master SPI data input EVADC_G10CH8 AI Analog input channel 8, group 10 P34.4 O0 General-purpose output GTM_TOUT149 O1 GTM muxed output ASCLIN4_ASLSO O2 Slave select signal output —O 3 Reserved QSPI2_MRST O4 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 —O 5 Reserved —O 6 Reserved CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Table 2-21 Port 34 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 149 V 1.2, 2021-03 AB18 P34.5 I FAST / PU1 / VEVRSB / ES General-purpose input GTM_TIM5_IN7_9 Mux input channel 7 of TIM module 5 GTM_TIM4_IN7_12 Mux input channel 7 of TIM module 4 GTM_TIM2_IN7_9 Mux input channel 7 of TIM module 2 QSPI2_MTSRD Slave SPI data input ASCLIN8_ARXE Receive input P34.5 O0 General-purpose output GTM_TOUT150 O1 GTM muxed output ASCLIN8_ATX O2 Transmit output —O 3 Reserved QSPI2_MTSR O4 Master SPI data output —O 5 Reserved —O 6 Reserved CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-22 Analog Inputs Ball Symbol Ctrl. Buffer Type Function AA15 AN0 I D / HighZ / VDDM Analog Input 0 EVADC_G0CH0 Analog input channel 0, group 0 EDSADC_EDS3PA Positive analog input channel 3, pin A AB15 AN1 I D / HighZ / VDDM Analog Input 1 EVADC_G0CH1 Analog input channel 1, group 0 EDSADC_EDS3NA Negative analog input channel 3, pin A AD14 AN2 I D / HighZ / VDDM Analog Input 2 EVADC_G0CH2 Analog input channel 2, group 0 EDSADC_EDS0PA Positive analog input channel 0, pin A AB14 AN3 I D / HighZ / VDDM Analog Input 3 EVADC_G0CH3 Analog input channel 3, group 0 EDSADC_EDS0NA Negative analog input channel 0, pin A AA14 AN4 I D / HighZ / VDDM Analog Input 4 EVADC_G11CH0 Analog input channel 0, group 11 EVADC_G0CH4 Analog input channel 4, group 0 AE14 AN5 I D / HighZ / VDDM Analog Input 5 EVADC_G11CH1 Analog input channel 1, group 11 EVADC_G0CH5 Analog input channel 5, group 0 Table 2-21 Port 34 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 150 V 1.2, 2021-03 AA13 AN6 I D / HighZ / VDDM Analog Input 6 EVADC_G11CH2 Analog input channel 2, group 11 EVADC_G0CH6 Analog input channel 6, group 0 AB13 AN7 I D / HighZ / VDDM Analog Input 7 EVADC_G11CH3 Analog input channel 3, group 11 EVADC_G0CH7 Analog input channel 7, group 0 AD13 AN8 I D / HighZ / VDDM Analog Input 8 EVADC_G11CH4 Analog input channel 4, group 11 EVADC_G1CH0 Analog input channel 0, group 1 AB12 AN9 I D / HighZ / VDDM Analog Input 9 EVADC_G11CH5 Analog input channel 5, group 11 EVADC_G1CH1 Analog input channel 1, group 1 AE13 AN10 I D / HighZ / VDDM Analog Input 10 EVADC_G11CH6 Analog input channel 6, group 11 EVADC_G1CH2 Analog input channel 2, group 1 AD12 AN11 I D / HighZ / VDDM Analog Input 11 EVADC_G11CH7 Analog input channel 7, group 11 EVADC_G1CH3 Analog input channel 3, group 1 AA12 AN12 I D / HighZ / VDDM Analog Input 12 EVADC_G1CH4 Analog input channel 4, group 1 EDSADC_EDS0PB Positive analog input channel 0, pin B AD11 AN13 I D / HighZ / VDDM Analog Input 13 EVADC_G1CH5 Analog input channel 5, group 1 EDSADC_EDS0NB Negative analog input channel 0, pin B AB11 AN14 I D / HighZ / VDDM Analog Input 14 EVADC_G1CH6 Analog input channel 6, group 1 EDSADC_EDS3PB Positive analog input channel 3, pin B AA11 AN15 I D / HighZ / VDDM Analog Input 15 EVADC_G1CH7 Analog input channel 7, group 1 EDSADC_EDS3NB Negative analog input channel 3, pin N AD10 AN16 I D / HighZ / VDDM Analog Input 16 EVADC_G2CH0 Analog input channel 0, group 2 EVADC_FC0CH0 Analog input FC channel 0 AB10 AN17/P40.10 I S / HighZ / VDDM Analog Input 17 SENT_SENT10A Receive input channel 10 EVADC_G2CH1 Analog input channel 1, group 2 EVADC_FC1CH0 Analog input FC channel 1 Table 2-22 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 151 V 1.2, 2021-03 AD9 AN18/P40.11 I S / HighZ / VDDM Analog Input 18 SENT_SENT11A Receive input channel 11 EVADC_G11CH8 Analog input channel 8, group 11 EVADC_G2CH2 Analog input channel 2, group 2 AD8 AN19/P40.12 I S / HighZ / VDDM Analog Input 19 SENT_SENT12A Receive input channel 12 EVADC_G11CH9 Analog input channel 9, group 11 EVADC_G2CH3 Analog input channel 3, group 2 AE8 AN20 I D / HighZ / VDDM Analog Input 20 EVADC_G2CH4 Analog input channel 4, group 2 EDSADC_EDS2PA Positive analog input channel 2, pin A AE7 AN21 I D / HighZ / VDDM Analog Input 21 EVADC_G2CH5 Analog input channel 5, group 2 EDSADC_EDS2NA Negative analog input channel 2, pin A AA10 AN22 I D / HighZ / VDDM Analog Input 22 EVADC_G2CH6 Analog input channel 6, group 2 Y10 AN23 I D / HighZ / VDDM Analog Input 23 EVADC_G2CH7 Analog input channel 7, group 2 AD7 AN24/P40.0 I S / HighZ / VDDM Analog Input 24 SENT_SENT0A Receive input channel 0 EVADC_G3CH0 Analog input channel 0, group 3 CCU60_CCPOS0D Hall capture input 0 EDSADC_EDS2PB Positive analog input channel 2, pin B AD6 AN25/P40.1 I S / HighZ / VDDM Analog Input 25 SENT_SENT1A Receive input channel 1 EVADC_G3CH1 Analog input channel 1, group 3 CCU60_CCPOS1B Hall capture input 1 EDSADC_EDS2NB Negative analog input channel 2, pin B AC7 AN26/P40.2 I S / HighZ / VDDM Analog Input 26 SENT_SENT2A Receive input channel 2 EVADC_G3CH2 Analog input channel 2, group 3 CCU60_CCPOS1D Hall capture input 1 EVADC_G11CH10 Analog input channel 10, group 11 AC6 AN27/P40.3 I S / HighZ / VDDM Analog Input 27 SENT_SENT3A Receive input channel 3 EVADC_G3CH3 Analog input channel 3, group 3 CCU60_CCPOS2B Hall capture input 2 EVADC_G11CH11 Analog input channel 11, group 11 Table 2-22 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 152 V 1.2, 2021-03 AB7 AN28/P40.13 I S / HighZ / VDDM Analog Input 28 SENT_SENT13A Receive input channel 13 EVADC_G3CH4 Analog input channel 4, group 3 EVADC_G4CH4 Analog input channel 4, group 4 AB6 AN29/P40.14 I S / HighZ / VDDM Analog Input 29 SENT_SENT14A Receive input channel 14 EVADC_G3CH5 Analog input channel 5, group 3 EVADC_G4CH5 Analog input channel 5, group 4 AA9 AN30 I D / HighZ / VDDM Analog Input 30 EVADC_G3CH6 Analog input channel 6, group 3 EVADC_G4CH6 Analog input channel 6, group 4 Y9 AN31 I D / HighZ / VDDM Analog Input 31 EVADC_G3CH7 Analog input channel 7, group 3 EVADC_G4CH7 Analog input channel 7, group 4 W9 AN32/P40.4 I S / HighZ / VDDM Analog Input 32 SENT_SENT4A Receive input channel 4 EVADC_G8CH0 Analog input channel 0, group 8 CCU60_CCPOS2D Hall capture input 2 EVADC_G11CH12 Analog input channel 12, group 11 Y6 AN33/P40.5 I S / HighZ / VDDM Analog Input 33 SENT_SENT5A Receive input channel 5 EVADC_G8CH1 Analog input channel 1, group 8 CCU61_CCPOS0D Hall capture input 0 EVADC_G11CH13 Analog input channel 13, group 11 W10 AN34 I D / HighZ / VDDM Analog Input 34 EVADC_G8CH2 Analog input channel 2, group 8 EVADC_G11CH14 Analog input channel 14, group 11 Y7 AN35 I D / HighZ / VDDM Analog Input 35 EVADC_G8CH3 Analog input channel 3, group 8 EVADC_G11CH15 Analog input channel 15, group 11 V9 AN36/P40.6 I S / HighZ / VDDM Analog Input 36 SENT_SENT6A Receive input channel 6 EVADC_G8CH4 Analog input channel 4, group 8 CCU61_CCPOS1B Hall capture input 1 EDSADC_EDS1PA Positive analog input channel 1, pin A Table 2-22 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 153 V 1.2, 2021-03 W7 AN37/P40.7 I S / HighZ / VDDM Analog Input 37 SENT_SENT7A Receive input channel 7 EVADC_G8CH5 Analog input channel 5, group 8 CCU61_CCPOS1D Hall capture input 1 EDSADC_EDS1NA Negative analog input channel 1, pin A V10 AN38/P40.8 I S / HighZ / VDDM Analog Input 38 SENT_SENT8A Receive input channel 8 EVADC_G8CH6 Analog input channel 6, group 8 CCU61_CCPOS2B Hall capture input 2 EDSADC_EDS1PB Positive analog input channel 1, pin B W6 AN39/P40.9 I S / HighZ / VDDM Analog Input 39 SENT_SENT9A Receive input channel 9 EVADC_G8CH7 Analog input channel 7, group 8 CCU61_CCPOS2D Hall capture input 2 EDSADC_EDS1NB Negative analog input channel 1, pin B U10 AN40 I D / HighZ / VDDM Analog Input 40 EVADC_G8CH8 Analog input channel 8, group 8 EVADC_G4CH0 Analog input channel 0, group 4 U9 AN41 I D / HighZ / VDDM Analog Input 41 EVADC_G8CH9 Analog input channel 9, group 8 EVADC_G4CH1 Analog input channel 1, group 4 T10 AN42 I D / HighZ / VDDM Analog Input 42 EVADC_G8CH10 Analog input channel 10, group 8 EVADC_G4CH2 Analog input channel 2, group 4 T9 AN43 I D / HighZ / VDDM Analog Input 43 EVADC_G8CH11 Analog input channel 11, group 8 EVADC_G4CH3 Analog input channel 3, group 4 V6 AN44 I D / HighZ / VDDM Analog Input 44 EVADC_G8CH12 Analog input channel 12, group 8 EDSADC_EDS1PC Positive analog input channel 1, pin C V7 AN45 I D / HighZ / VDDM Analog Input 45 EVADC_G8CH13 Analog input channel 13, group 8 EDSADC_EDS1NC Negative analog input channel 1, pin C U6 AN46 I D / HighZ / VDDM Analog Input 46 EVADC_G8CH14 Analog input channel 14, group 8 EDSADC_EDS1PD Positive analog input channel 1, pin D Table 2-22 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 154 V 1.2, 2021-03 U7 AN47 I D / HighZ / VDDM Analog Input 47 EVADC_G8CH15 Analog input channel 15, group 8 EDSADC_EDS1ND Negative analog input channel 1, pin D AK7 AN48 I D / HighZ / VDDM Analog Input 48 EVADC_G5CH0 Analog input channel 0, group 5 AJ7 AN49 I D / HighZ / VDDM Analog Input 49 EVADC_G5CH1 Analog input channel 1, group 5 AJ6 AN50 I D / HighZ / VDDM Analog Input 50 EVADC_G5CH2 Analog input channel 2, group 5 EDSADC_EDS9PA Positive analog input channel 9, pin A AK6 AN51 I D / HighZ / VDDM Analog Input 51 EVADC_G5CH3 Analog input channel 3, group 5 EDSADC_EDS9NA Negative analog input channel 9, pin A AJ5 AN52 I D / HighZ / VDDM Analog Input 52 EVADC_G5CH4 Analog input channel 4, group 5 EDSADC_EDS6PA Positive analog input channel 6, pin A AK5 AN53 I D / HighZ / VDDM Analog Input 53 EVADC_G5CH5 Analog input channel 5, group 5 EDSADC_EDS6NA Negative analog input channel 6, pin A AJ4 AN54/P41.4 I S / HighZ / VDDM Analog Input 54 SENT_SENT20A Receive input channel 20 EVADC_G5CH6 Analog input channel 6, group 5 EDSADC_EDS6PB Positive analog input channel 6, pin B AK4 AN55/P41.5 I S / HighZ / VDDM Analog Input 55 SENT_SENT21A Receive input channel 21 EVADC_G5CH7 Analog input channel 7, group 5 EDSADC_EDS6NB Negative analog input channel 6, pin B AF1 AN56 I D / HighZ / VDDM Analog Input 56 EVADC_G6CH0 Analog input channel 0, group 6 AF2 AN57 I D / HighZ / VDDM Analog Input 57 EVADC_G6CH1 Analog input channel 1, group 6 AE2 AN58 I D / HighZ / VDDM Analog Input 58 EVADC_G6CH2 Analog input channel 2, group 6 AE1 AN59 I D / HighZ / VDDM Analog Input 59 EVADC_G6CH3 Analog input channel 3, group 6 AD1 AN60 I D / HighZ / VDDM Analog Input 60 EVADC_G6CH4 Analog input channel 4, group 6 EDSADC_EDS7PA Positive analog input channel 7, pin A Table 2-22 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 155 V 1.2, 2021-03 AD2 AN61 I D / HighZ / VDDM Analog Input 61 EVADC_G6CH5 Analog input channel 5, group 6 EDSADC_EDS7NA Negative analog input channel 7, pin A AC2 AN62/P41.6 I S / HighZ / VDDM Analog Input 62 SENT_SENT22A Receive input channel 22 EVADC_G6CH6 Analog input channel 6, group 6 EDSADC_EDS7PB Positive analog input channel 7, pin B AC1 AN63/P41.7 I S / HighZ / VDDM Analog Input 63 SENT_SENT23A Receive input channel 23 EVADC_G6CH7 Analog input channel 7, group 6 EDSADC_EDS7NB Negative analog input channel 7, pin B AB2 AN64/P41.8 I S / HighZ / VDDM Analog Input 64 SENT_SENT24A Receive input channel 24 EVADC_G7CH0 Analog input channel 0, group 7 AB1 AN65 I D / HighZ / VDDM Analog Input 65 EVADC_G7CH1 Analog input channel 1, group 7 AA2 AN66 I D / HighZ / VDDM Analog Input 66 EVADC_G7CH2 Analog input channel 2, group 7 AA1 AN67/P40.15 I S / HighZ / VDDM Analog Input 67 SENT_SENT15A Receive input channel 15 EVADC_G7CH3 Analog input channel 3, group 7 Y1 AN68/P41.0 I S / HighZ / VDDM Analog Input 68 SENT_SENT16A Receive input channel 16 EVADC_G7CH4 Analog input channel 4, group 7 EDSADC_EDS8PA Positive analog input channel 8, pin A Y2 AN69/P41.1 I S / HighZ / VDDM Analog Input 69 SENT_SENT17A Receive input channel 17 EVADC_G7CH5 Analog input channel 5, group 7 EDSADC_EDS8NA Negative analog input channel 8, pin A W1 AN70/P41.2 I S / HighZ / VDDM Analog Input 70 SENT_SENT18A Receive input channel 18 EVADC_G7CH6 Analog input channel 6, group 7 EDSADC_EDS9PB Positive analog input channel 9, pin B W2 AN71/P41.3 I S / HighZ / VDDM Analog Input 71 SENT_SENT19A Receive input channel 19 EVADC_G7CH7 Analog input channel 7, group 7 EDSADC_EDS9NB Negative analog input channel 9, pin B Table 2-22 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 156 V 1.2, 2021-03 Note: Port Pins P32.0 and P32.1 are bidirectional pads and are having the following two functionalities implemented: 1. In case the pins are used as standard GPIOs the functions defined in the pin configuration tables of P32.0 and P32.1 are available. 2. In case the pins are used as pre-drivers for extern al MOSFETs (internal DCDC usecase) P32.0 and P32.1 act as analog IOs named VGATE1N and VGATE1P. Table 2-23 System I/O Ball Symbol Ctrl. Buffer Type Function M21 ESR1 I/O FAST / PU1 / VEXT ESR1 Port Pin input - can be used to trigger a reset or an NMI ESR1: External System Request Reset 1. Default NMI function. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR1WKP I ESR1 pin input L21 ESR0 I/O FAST / OD / VEXT ESR0 Port Pin input - can be used to trigger a reset or an NMI ESR0: External System Request Reset 0. Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset. This is valid additionally after deactivation of PORST_N until the internal reset phase has finished. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR0WKP I ESR0 pin input AD22 VGATE1P O — DCDC P ch. MOSFET gate driver output P32.1 / External Pass Device gate control for EVRC AE22 VGATE1N O — DCDC N ch. MOSFET gate driver output P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC U25 XTAL1 I XTAL / VEXT XTAL pad1 XTAL1. Main Oscillator/PLL/Clock Generator Input. U24 XTAL2 O XTAL / VEXT XTAL pad2 XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT T24 TRST I FAST / PU2 / VEXT JTAG Module Reset/Enable Input P21 TCK I FAST / PD2 / VEXT JTAG Module Clock Input DAP0 I DAP: DAP0 Clock Input OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 157 V 1.2, 2021-03 R21 TMS I FAST / PD2 / VEXT JTAG Module State Machine Control Input DAP1 I/O DAP: DAP1 Data I/O M22 PORST I/O PORST / PD / VEXT PORST pin Power On Reset Input. Additional strong PD in case of power fail. Table 2-24 Supply Ball Symbol Ctrl. Buffer Type Function N19, V19, M18, W18, W13, V12, J21, K20, N12, M13 VDD I — Digital Core Power Supply (1.25V) AJ30, AH29, AD25, AC24, G8, F7, B3, A2, J29, J30, AH30, AK29, AK20, AJ11, AK11 VEXT I — External Power Supply (5V / 3.3V) J10 VFLEX I — Digital Power Supply for Flex Port Pads (5V / 3.3V) AE10, AJ9, AK9 VDDM I — ADC Analog Power Supply (5V / 3.3V) A29, B28, F24, G23 VDDP3 I — Flash Power Supply (3.3V) AK30, AJ29, AE25, AD24, AB22, AA21, K10, J9, G7, B2, A30, B30, B29, F25, G24, J22, K21, H30, H29, AJ10, AK10 VSS I — Digital Ground AE9, AJ8, AK8 VSSM I — Analog Ground for VDDM Table 2-23 System I/O (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 158 V 1.2, 2021-03 P19, U19, P18, R18, T18, U18, M15, M16, M17, N17, R17, T17, V17, W17, N16, P16, R16, T16, U16, V16, N15, P15, R15, T15, U15, V15, M14, N14, R14, T14, V14, W14, P13, R13, T13, U13, P12, U12, T19, W15, W16, R12, T12 VSS I — Digital Ground T25 VSS I — Oscillator Ground, VSS(OSC) AE11 VAREF1 I — Positive Analog Reference Voltage 1 AE12 VAGND1 I — Negative Analog Reference Voltage 1 AA6 VAREF2 I — Positive Analog Reference Voltage 2 AA7 VAGND2 I — Negative Analog Reference Voltage 2 Table 2-24 Supply (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 159 V 1.2, 2021-03 C30, D30, E30, F30, G30, W30, C29, D29, E29, F29, G29, A28, A27, B27, A26, B26, A25, A21, AJ20, B21, B20, A17, B17, A10, B10, A9, B9, A8, A4, B4, A3, AJ3, AK3, C2, D2, E2, H2, R2, AH2, AJ2, AK2, B1, C1, D1, E1, H1, J1, R1, T1, AH1, AJ1, B6, B14, B25, V1, V2, R19 NC I — Not connected. These pins are reserved for future extensions and shall not be connected externally AB9, F6, AE6, A1, AK1, V30, V29 NC1 I — Not connected. These pins are not connected on package level and will not be used for future extensions AA16 VEVRSB I — Standby Power Supply (5V / 3.3V) for the Standby SRAM V24 VDD I — Digital Power Supply for Oscillator (1.25V), VDD(OSC) V25 VEXT I — Digital Power Supply for Oscillator (shall be supplied with same level as used for VEXT), VEXT(OSC) AG1 VAREF3 I — Positive Analog Reference Voltage 3 AG2 VAGND3 I — Negative Analog Reference Voltage 3 Table 2-24 Supply (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 160 V 1.2, 2021-03

2.2 BGA292 Package Varian t Pin Configuration

Table 2-25 Port 00 Functions Ball Symbol Ctrl. Buffer Type Function G1 P00.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN4_10 Mux input channel 4 of TIM module 5 GTM_TIM3_IN0_1 Mux input channel 0 of TIM module 3 GTM_TIM2_IN0_1 Mux input channel 0 of TIM module 2 CCU61_CTRAPA Trap input capture CCU60_T12HRE External timer start 12 MSC0_INJ0 Injection signal from port GETH_MDIOA MDIO Input P00.0 O0 General-purpose output GTM_TOUT9 O1 GTM muxed output IOM_REF0_9 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output ASCLIN3_ATX O3 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 4 Reserved CAN10_TXD O5 CAN transmit output node 0 —O 6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 GETH_MDIO O MDIO Output OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 161 V 1.2, 2021-03 G2 P00.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN5_11 Mux input channel 5 of TIM module 5 GTM_TIM3_IN1_1 Mux input channel 1 of TIM module 3 GTM_TIM2_IN1_1 Mux input channel 1 of TIM module 2 CCU60_CC60INB T12 capture input 60 ASCLIN3_ARXE Receive input EDSADC_DSCIN5A Modulator clock input, channel 5 CAN10_RXDA CAN receive input node 0 PSI5_RX0A RXD inputs (receive data) channel 0 CCU61_CC60INA T12 capture input 60 SENT_SENT0B Receive input channel 0 EDSADC_DSCIN7B Modulator clock input, channel 7 EVADC_G9CH11 AI Analog input channel 11, group 9 EDSADC_EDS5NA Negative analog input channel 5, pin A P00.1 O0 General-purpose output GTM_TOUT10 O1 GTM muxed output IOM_REF0_10 Reference input 0 ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 3 Reserved EDSADC_DSCOUT5 O4 Modulator clock output EDSADC_DSCOUT7 O5 Modulator clock output SENT_SPC0 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-25 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 162 V 1.2, 2021-03 H1 P00.2 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM5_IN6_11 Mux input channel 6 of TIM module 5 GTM_TIM3_IN1_2 Mux input channel 1 of TIM module 3 GTM_TIM2_IN1_2 Mux input channel 1 of TIM module 2 EDSADC_DSDIN7B Digital datastream input, channel 7 EDSADC_DSDIN5A Digital datastream input, channel 5 SENT_SENT1B Receive input channel 1 EVADC_G9CH10 AI Analog input channel 10, group 9 EDSADC_EDS5PA Positive analog input channel 5, pin A P00.2 O0 General-purpose output GTM_TOUT11 O1 GTM muxed output IOM_REF0_11 Reference input 0 ASCLIN3_ASCLK O2 Shift clock output CAN21_TXD O3 CAN transmit output node 1 PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 QSPI3_SLSO4 O6 Master slave select output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 Table 2-25 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 163 V 1.2, 2021-03 H2 P00.3 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM5_IN7_10 Mux input channel 7 of TIM module 5 GTM_TIM3_IN2_1 Mux input channel 2 of TIM module 3 GTM_TIM2_IN2_1 Mux input channel 2 of TIM module 2 CCU60_CC61INB T12 capture input 61 EDSADC_DSCIN3A Modulator clock input, channel 3 EDSADC_ITR5F Trigger/Gate input, channel 5 PSI5_RX1A RXD inputs (receive data) channel 1 CAN03_RXDA CAN receive input node 3 CAN21_RXDA CAN receive input node 1 PSI5S_RXA RX data input SENT_SENT2B Receive input channel 2 CCU61_CC61INA T12 capture input 61 ASCLIN12_ARXA Receive input EVADC_G9CH9 AI Analog input channel 9, group 9 EDSADC_EDS5NB Negative analog input channel 5, pin B P00.3 O0 General-purpose output GTM_TOUT12 O1 GTM muxed output IOM_REF0_12 Reference input 0 ASCLIN3_ASLSO O2 Slave select signal output ASCLIN12_ATX O3 Transmit output EDSADC_DSCOUT3 O4 Modulator clock output —O 5 Reserved SENT_SPC2 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-25 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 164 V 1.2, 2021-03 J1 P00.4 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM6_IN4_1 Mux input channel 4 of TIM module 6 GTM_TIM3_IN3_1 Mux input channel 3 of TIM module 3 GTM_TIM2_IN3_1 Mux input channel 3 of TIM module 2 SCU_E_REQ2_2 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT3B Receive input channel 3 EDSADC_DSDIN3A Digital datastream input, channel 3 EDSADC_SGNA Carrier sign signal input ASCLIN10_ARXA Receive input GTM_DTMA5_0 CDTM5_DTM4 GTM_DTMT3_0 CDTM3_DTM0 EVADC_G9CH8 AI Analog input channel 8, group 9 EDSADC_EDS5PB Positive analog input channel 5, pin B P00.4 O0 General-purpose output GTM_TOUT13 O1 GTM muxed output IOM_REF0_13 Reference input 0 PSI5S_TX O2 TX data output CAN11_TXD O3 CAN transmit output node 1 PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 —O 5 Reserved SENT_SPC3 O6 Transmit output CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 Table 2-25 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 165 V 1.2, 2021-03 J2 P00.5 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN4_1 Mux input channel 4 of TIM module 3 GTM_TIM3_IN0_11 Mux input channel 0 of TIM module 3 GTM_TIM2_IN4_1 Mux input channel 4 of TIM module 2 CCU60_CC62INB T12 capture input 62 EDSADC_DSCIN2A Modulator clock input, channel 2 PSI5_RX2A RXD inputs (receive data) channel 2 CCU61_CC62INA T12 capture input 62 SENT_SENT4B Receive input channel 4 CAN11_RXDB CAN receive input node 1 ASCLIN12_ARXB Receive input GTM_DTMT1_1 CDTM1_DTM0 EVADC_G9CH7 AI Analog input channel 7, group 9 P00.5 O0 General-purpose output GTM_TOUT14 O1 GTM muxed output IOM_REF0_14 Reference input 0 EDSADC_CGPWMN O2 Negative carrier generator output QSPI3_SLSO3 O3 Master slave select output EDSADC_DSCOUT2 O4 Modulator clock output EVADC_FC0BFLOUT O5 Boundary flag output, FC channel 0 SENT_SPC4 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-25 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 166 V 1.2, 2021-03 J4 P00.6 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN5_1 Mux input channel 5 of TIM module 3 GTM_TIM3_IN1_14 Mux input channel 1 of TIM module 3 GTM_TIM2_IN5_1 Mux input channel 5 of TIM module 2 EDSADC_ITR4F Trigger/Gate input, channel 4 EDSADC_DSDIN2A Digital datastream input, channel 2 SENT_SENT5B Receive input channel 5 ASCLIN5_ARXA Receive input GTM_DTMT3_1 CDTM3_DTM0 EVADC_G9CH6 AI Analog input channel 6, group 9 P00.6 O0 General-purpose output GTM_TOUT15 O1 GTM muxed output IOM_REF0_15 Reference input 0 EDSADC_CGPWMP O2 Positive carrier generator output —O 3 Reserved PSI5_TX2 O4 TXD outputs (send data) IOM_REF1_15 Reference input 1 EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 SENT_SPC5 O6 Transmit output CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 Table 2-25 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 167 V 1.2, 2021-03 K1 P00.7 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN6_1 Mux input channel 6 of TIM module 3 GTM_TIM3_IN2_11 Mux input channel 2 of TIM module 3 GTM_TIM2_IN6_1 Mux input channel 6 of TIM module 2 CCU61_CC60INC T12 capture input 60 SENT_SENT6B Receive input channel 6 EDSADC_DSCIN4A Modulator clock input, channel 4 GPT120_T2INA Trigger/gate input of timer T2 CCU61_CCPOS0A Hall capture input 0 CCU60_T12HRB External timer start 12 GTM_DTMT0_2 CDTM0_DTM0 EVADC_G9CH5 AI Analog input channel 5, group 9 EDSADC_EDS4NA Negative analog input channel 4, pin A P00.7 O0 General-purpose output GTM_TOUT16 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output EVADC_FC2BFLOUT O3 Boundary flag output, FC channel 2 EDSADC_DSCOUT4 O4 Modulator clock output EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 SENT_SPC6 O6 Transmit output CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-25 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 168 V 1.2, 2021-03 K4 P00.8 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM3_IN7_1 Mux input channel 7 of TIM module 3 GTM_TIM3_IN3_11 Mux input channel 3 of TIM module 3 GTM_TIM2_IN7_1 Mux input channel 7 of TIM module 2 CCU61_CC61INC T12 capture input 61 SENT_SENT7B Receive input channel 7 EDSADC_DSDIN4A Digital datastream input, channel 4 GPT120_T2EUDA Count direction control input of timer T2 CCU61_CCPOS1A Hall capture input 1 CCU60_T13HRB External timer start 13 ASCLIN10_ARXB Receive input EVADC_G9CH4 AI Analog input channel 4, group 9 EDSADC_EDS4PA Positive analog input channel 4, pin A P00.8 O0 General-purpose output GTM_TOUT17 O1 GTM muxed output QSPI3_SLSO6 O2 Master slave select output ASCLIN10_ATX O3 Transmit output —O 4 Reserved EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 SENT_SPC7 O6 Transmit output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-25 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 169 V 1.2, 2021-03 K2 P00.9 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM4_IN0_7 Mux input channel 0 of TIM module 4 GTM_TIM1_IN0_1 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_1 Mux input channel 0 of TIM module 0 CCU61_CC62INC T12 capture input 62 SENT_SENT8B Receive input channel 8 CCU61_CCPOS2A Hall capture input 2 EDSADC_DSCIN1A Modulator clock input, channel 1 EDSADC_ITR3F Trigger/Gate input, channel 3 GPT120_T4EUDA Count direction control input of timer T4 CCU60_T13HRC External timer start 13 CCU60_T12HRC External timer start 12 ASCLIN13_ARXA Receive input EVADC_G9CH3 AI Analog input channel 3, group 9 EDSADC_EDS4NB Negative analog input channel 4, pin B P00.9 O0 General-purpose output GTM_TOUT18 O1 GTM muxed output QSPI3_SLSO7 O2 Master slave select output ASCLIN3_ARTS O3 Ready to send output EDSADC_DSCOUT1 O4 Modulator clock output ASCLIN4_ATX O5 Transmit output SENT_SPC8 O6 Transmit output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-25 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 170 V 1.2, 2021-03 K5 P00.10 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM4_IN1_11 Mux input channel 1 of TIM module 4 GTM_TIM1_IN1_1 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_1 Mux input channel 1 of TIM module 0 SENT_SENT9B Receive input channel 9 EDSADC_DSDIN1A Digital datastream input, channel 1 EVADC_G9CH2 AI Analog input channel 2, group 9 EDSADC_EDS4PB Positive analog input channel 4, pin B P00.10 O0 General-purpose output GTM_TOUT19 O1 GTM muxed output ASCLIN4_ASCLK O2 Shift clock output ASCLIN13_ATX O3 Transmit output —O 4 Reserved —O 5 Reserved SENT_SPC9 O6 Transmit output CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 L1 P00.11 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM4_IN2_11 Mux input channel 2 of TIM module 4 GTM_TIM1_IN2_1 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_1 Mux input channel 2 of TIM module 0 CCU60_CTRAPA Trap input capture EDSADC_DSCIN0A Modulator clock input, channel 0 CCU61_T12HRE External timer start 12 SENT_SENT10B Receive input channel 10 ASCLIN13_ARXB Receive input EVADC_G9CH1 AI Analog input channel 1, group 9 EVADC_FC3CH0 Analog input FC channel 3 P00.11 O0 General-purpose output GTM_TOUT20 O1 GTM muxed output ASCLIN4_ASLSO O2 Slave select signal output ASCLIN13_ATX O3 Transmit output EDSADC_DSCOUT0 O4 Modulator clock output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-25 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 171 V 1.2, 2021-03 L2 P00.12 I SLOW / PU1 / VEXT / ES1 General-purpose input GTM_TIM4_IN3_11 Mux input channel 3 of TIM module 4 GTM_TIM1_IN3_1 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_1 Mux input channel 3 of TIM module 0 ASCLIN3_ACTSA Clear to send input EDSADC_DSDIN0A Digital datastream input, channel 0 ASCLIN4_ARXA Receive input SENT_SENT11B Receive input channel 11 EVADC_G9CH0 AI Analog input channel 0, group 9 EVADC_FC2CH0 Analog input FC channel 2 P00.12 O0 General-purpose output GTM_TOUT21 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 Table 2-25 Port 00 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 172 V 1.2, 2021-03 Table 2-26 Port 01 Functions Ball Symbol Ctrl. Buffer Type Function G5 P01.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN5_2 Mux input channel 5 of TIM module 4 GTM_TIM2_IN0_14 Mux input channel 0 of TIM module 2 GTM_TIM0_IN5_8 Mux input channel 5 of TIM module 0 QSPI3_SLSIB Slave select input EDSADC_ITR7F Trigger/Gate input, channel 7 EVADC_G9CH14 AI Analog input channel 14, group 9 P01.3 O0 General-purpose output GTM_TOUT111 O1 GTM muxed output —O 2 Reserved —O 3 Reserved QSPI3_SLSO9 O4 Master slave select output CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 —O 6 Reserved —O 7 Reserved G4 P01.4 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN6_2 Mux input channel 6 of TIM module 4 GTM_TIM2_IN1_14 Mux input channel 1 of TIM module 2 GTM_TIM0_IN6_8 Mux input channel 6 of TIM module 0 CAN01_RXDC CAN receive input node 1 EDSADC_ITR7E Trigger/Gate input, channel 7 EVADC_G9CH13 AI Analog input channel 13, group 9 P01.4 O0 General-purpose output GTM_TOUT112 O1 GTM muxed output —O 2 Reserved ASCLIN9_ASLSO O3 Slave select signal output QSPI3_SLSO10 O4 Master slave select output —O 5 Reserved —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 173 V 1.2, 2021-03 H5 P01.5 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN3_2 Mux input channel 3 of TIM module 5 GTM_TIM2_IN3_7 Mux input channel 3 of TIM module 2 GTM_TIM2_IN2_7 Mux input channel 2 of TIM module 2 QSPI3_MRSTC Master SPI data input EDSADC_DSCIN8A Modulator clock input, channel 8 ASCLIN9_ARXA Receive input EVADC_G9CH12 AI Analog input channel 12, group 9 P01.5 O0 General-purpose output GTM_TOUT113 O1 GTM muxed output —O 2 Reserved —O 3 Reserved QSPI3_MRST O4 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 —O 5 Reserved EDSADC_DSCOUT8 O6 Modulator clock output —O 7 Reserved H4 P01.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN6_2 Mux input channel 6 of TIM module 5 GTM_TIM5_IN5_3 Mux input channel 5 of TIM module 5 GTM_TIM2_IN5_7 Mux input channel 5 of TIM module 2 QSPI3_MTSRC Slave SPI data input EDSADC_DSDIN8A Digital datastream input, channel 8 P01.6 O0 General-purpose output GTM_TOUT114 O1 GTM muxed output ASCLIN12_ATX O2 Transmit output ASCLIN9_ASCLK O3 Shift clock output QSPI3_MTSR O4 Master SPI data output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-26 Port 01 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 174 V 1.2, 2021-03 J5 P01.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN7_2 Mux input channel 7 of TIM module 5 GTM_TIM2_IN7_7 Mux input channel 7 of TIM module 2 QSPI3_SCLKC Slave SPI clock inputs EDSADC_ITR8F Trigger/Gate input, channel 8 ASCLIN9_ARXB Receive input P01.7 O0 General-purpose output GTM_TOUT115 O1 GTM muxed output —O 2 Reserved ASCLIN9_ATX O3 Transmit output QSPI3_SCLK O4 Master SPI clock output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-26 Port 01 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 175 V 1.2, 2021-03 Table 2-27 Port 02 Functions Ball Symbol Ctrl. Buffer Type Function B1 P02.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_2 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_2 Mux input channel 0 of TIM module 0 CCU61_CC60INB T12 capture input 60 ASCLIN2_ARXG Receive input CCU60_CC60INA T12 capture input 60 SCU_E_REQ3_2 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GTM_DTMA0_0 CDTM0_DTM4 P02.0 O0 General-purpose output GTM_TOUT0 O1 GTM muxed output IOM_REF0_0 Reference input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO1 O3 Master slave select output EDSADC_CGPWMN O4 Negative carrier generator output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 ERAY0_TXDA O6 Transmit Channel A CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 176 V 1.2, 2021-03 C2 P02.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_2 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_2 Mux input channel 1 of TIM module 0 ERAY0_RXDA2 Receive Channel A2 ASCLIN2_ARXB Receive input CAN00_RXDA CAN receive input node 0 SCU_E_REQ2_1 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P02.1 O0 General-purpose output GTM_TOUT1 O1 GTM muxed output IOM_REF0_1 Reference input 0 QSPI4_SLSO7 O2 Master slave select output QSPI3_SLSO2 O3 Master slave select output EDSADC_CGPWMP O4 Positive carrier generator output —O 5 Reserved —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 Table 2-27 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 177 V 1.2, 2021-03 C1 P02.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_2 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_2 Mux input channel 2 of TIM module 0 CCU61_CC61INB T12 capture input 61 CCU60_CC61INA T12 capture input 61 SENT_SENT14B Receive input channel 14 P02.2 O0 General-purpose output GTM_TOUT2 O1 GTM muxed output IOM_REF0_2 Reference input 0 ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI3_SLSO3 O3 Master slave select output PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ERAY0_TXDB O6 Transmit Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Table 2-27 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 178 V 1.2, 2021-03 D2 P02.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN3_2 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_2 Mux input channel 3 of TIM module 0 EDSADC_DSCIN5B Modulator clock input, channel 5 ERAY0_RXDB2 Receive Channel B2 CAN02_RXDB CAN receive input node 2 ASCLIN1_ARXG Receive input MSC1_SDI1 Upstream assynchronous input signal PSI5_RX0B RXD inputs (receive data) channel 0 SENT_SENT13B Receive input channel 13 P02.3 O0 General-purpose output GTM_TOUT3 O1 GTM muxed output IOM_REF0_3 Reference input 0 ASCLIN2_ASLSO O2 Slave select signal output QSPI3_SLSO4 O3 Master slave select output EDSADC_DSCOUT5 O4 Modulator clock output —O 5 Reserved —O 6 Reserved CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-27 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 179 V 1.2, 2021-03 D1 P02.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_1 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_1 Mux input channel 4 of TIM module 0 CCU61_CC62INB T12 capture input 62 EDSADC_DSDIN5B Digital datastream input, channel 5 QSPI3_SLSIA Slave select input CCU60_CC62INA T12 capture input 62 I2C0_SDAA Serial Data Input 0 CAN11_RXDA CAN receive input node 1 CAN0_ECTT1 External CAN time trigger input SENT_SENT12B Receive input channel 12 P02.4 O0 General-purpose output GTM_TOUT4 O1 GTM muxed output IOM_REF0_4 Reference input 0 ASCLIN2_ASCLK O2 Shift clock output QSPI3_SLSO0 O3 Master slave select output PSI5S_CLK O4 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. I2C0_SDA O5 Serial Data Output ERAY0_TXENA O6 Transmit Enable Channel A CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-27 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 180 V 1.2, 2021-03 E2 P02.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_1 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_1 Mux input channel 5 of TIM module 0 EDSADC_DSCIN4B Modulator clock input, channel 4 I2C0_SCLA Serial Clock Input 0 PSI5_RX1B RXD inputs (receive data) channel 1 PSI5S_RXB RX data input QSPI3_MRSTA Master SPI data input SENT_SENT3C Receive input channel 3 CAN0_ECTT2 External CAN time trigger input P02.5 O0 General-purpose output GTM_TOUT5 O1 GTM muxed output IOM_REF0_5 Reference input 0 CAN11_TXD O2 CAN transmit output node 1 QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 EDSADC_DSCOUT4 O4 Modulator clock output I2C0_SCL O5 Serial Clock Output ERAY0_TXENB O6 Transmit Enable Channel B CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 Table 2-27 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 181 V 1.2, 2021-03 E1 P02.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN0_10 Mux input channel 0 of TIM module 3 GTM_TIM1_IN6_1 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_1 Mux input channel 6 of TIM module 0 CCU60_CC60INC T12 capture input 60 SENT_SENT2C Receive input channel 2 EDSADC_DSDIN4B Digital datastream input, channel 4 EDSADC_ITR5E Trigger/Gate input, channel 5 GPT120_T3INA Trigger/gate input of core timer T3 CCU60_CCPOS0A Hall capture input 0 CCU61_T12HRB External timer start 12 QSPI3_MTSRA Slave SPI data input P02.6 O0 General-purpose output GTM_TOUT6 O1 GTM muxed output IOM_REF0_6 Reference input 0 PSI5S_TX O2 TX data output QSPI3_MTSR O3 Master SPI data output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX00 O5 Control of external analog multiplexer interface 0 —O 6 Reserved CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-27 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 182 V 1.2, 2021-03 F2 P02.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN1_10 Mux input channel 1 of TIM module 3 GTM_TIM1_IN7_1 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_1 Mux input channel 7 of TIM module 0 CCU60_CC61INC T12 capture input 61 SENT_SENT1C Receive input channel 1 EDSADC_DSCIN3B Modulator clock input, channel 3 EDSADC_ITR4E Trigger/Gate input, channel 4 GPT120_T3EUDA Count direction control input of core timer T3 PSI5_RX2B RXD inputs (receive data) channel 2 CCU60_CCPOS1A Hall capture input 1 QSPI3_SCLKA Slave SPI clock inputs CCU61_T13HRB External timer start 13 P02.7 O0 General-purpose output GTM_TOUT7 O1 GTM muxed output IOM_REF0_7 Reference input 0 —O 2 Reserved QSPI3_SCLK O3 Master SPI clock output EDSADC_DSCOUT3 O4 Modulator clock output EVADC_EMUX01 O5 Control of external analog multiplexer interface 0 SENT_SPC1 O6 Transmit output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Table 2-27 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 183 V 1.2, 2021-03 F1 P02.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN2_10 Mux input channel 2 of TIM module 3 GTM_TIM3_IN0_2 Mux input channel 0 of TIM module 3 GTM_TIM2_IN0_2 Mux input channel 0 of TIM module 2 CCU60_CC62INC T12 capture input 62 SENT_SENT0C Receive input channel 0 CCU60_CCPOS2A Hall capture input 2 EDSADC_DSDIN3B Digital datastream input, channel 3 EDSADC_ITR3E Trigger/Gate input, channel 3 GPT120_T4INA Trigger/gate input of timer T4 CCU61_T12HRC External timer start 12 CCU61_T13HRC External timer start 13 GTM_DTMA0_1 CDTM0_DTM4 P02.8 O0 General-purpose output GTM_TOUT8 O1 GTM muxed output IOM_REF0_8 Reference input 0 QSPI3_SLSO5 O2 Master slave select output ASCLIN8_ASCLK O3 Shift clock output PSI5_TX2 O4 TXD outputs (send data) IOM_REF1_15 Reference input 1 EVADC_EMUX02 O5 Control of external analog multiplexer interface 0 GETH_MDC O6 MDIO clock CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-27 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 184 V 1.2, 2021-03 E4 P02.9 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN2_2 Mux input channel 2 of TIM module 4 GTM_TIM3_IN3_10 Mux input channel 3 of TIM module 3 GTM_TIM0_IN2_10 Mux input channel 2 of TIM module 0 SENT_SENT20B Receive input channel 20 ASCLIN8_ARXA Receive input P02.9 O0 General-purpose output GTM_TOUT116 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 ASCLIN8_ATX O3 Transmit output —O 4 Reserved CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 —O 6 Reserved —O 7 Reserved F5 P02.10 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN3_2 Mux input channel 3 of TIM module 4 GTM_TIM3_IN4_11 Mux input channel 4 of TIM module 3 GTM_TIM0_IN3_10 Mux input channel 3 of TIM module 0 ASCLIN2_ARXC Receive input CAN01_RXDE CAN receive input node 1 SENT_SENT21B Receive input channel 21 ASCLIN8_ARXB Receive input P02.10 O0 General-purpose output GTM_TOUT117 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-27 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 185 V 1.2, 2021-03 F4 P02.11 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN4_3 Mux input channel 4 of TIM module 4 GTM_TIM3_IN5_12 Mux input channel 5 of TIM module 3 GTM_TIM0_IN7_7 Mux input channel 7 of TIM module 0 SENT_SENT22B Receive input channel 22 EVADC_G9CH15 AI Analog input channel 15, group 9 P02.11 O0 General-purpose output GTM_TOUT118 O1 GTM muxed output —O 2 Reserved ASCLIN8_ASLSO O3 Slave select signal output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-28 Port 10 Functions Ball Symbol Ctrl. Buffer Type Function A7 P10.0 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN0_12 Mux input channel 0 of TIM module 4 GTM_TIM1_IN4_2 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_2 Mux input channel 4 of TIM module 0 GPT120_T6EUDB Count direction control input of core timer T6 ASCLIN11_ARXA Receive input GETH_RXERC Receive Error MII GTM_DTMA5_2 CDTM5_DTM4 P10.0 O0 General-purpose output GTM_TOUT102 O1 GTM muxed output ASCLIN11_ATX O2 Transmit output QSPI1_SLSO10 O3 Master slave select output —O 4 Reserved —O 5 Reserved ASCLIN22_ATX O6 Transmit output —O 7 Reserved Table 2-27 Port 02 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 186 V 1.2, 2021-03 B7 P10.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN4_12 Mux input channel 4 of TIM module 4 GTM_TIM1_IN1_3 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_3 Mux input channel 1 of TIM module 0 GPT120_T5EUDB Count direction control input of timer T5 QSPI1_MRSTA Master SPI data input GTM_DTMT0_1 CDTM0_DTM0 P10.1 O0 General-purpose output GTM_TOUT103 O1 GTM muxed output QSPI1_MTSR O2 Master SPI data output QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 MSC0_EN1 O4 Chip Select EVADC_FC1BFLOUT O5 Boundary flag output, FC channel 1 —O 6 Reserved —O 7 Reserved A5 P10.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN5_12 Mux input channel 5 of TIM module 4 GTM_TIM1_IN2_3 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_3 Mux input channel 2 of TIM module 0 CAN02_RXDE CAN receive input node 2 MSC0_SDI1 Upstream assynchronous input signal QSPI1_SCLKA Slave SPI clock inputs GPT120_T6INB Trigger/gate input of core timer T6 SCU_E_REQ2_0 ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GTM_DTMT2_2 CDTM2_DTM0 P10.2 O0 General-purpose output GTM_TOUT104 O1 GTM muxed output IOM_MON2_9 Monitor input 2 —O 2 Reserved QSPI1_SCLK O3 Master SPI clock output MSC0_EN0 O4 Chip Select EVADC_FC3BFLOUT O5 Boundary flag output, FC channel 3 —O 6 Reserved —O 7 Reserved Table 2-28 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 187 V 1.2, 2021-03 A6 P10.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN6_10 Mux input channel 6 of TIM module 4 GTM_TIM1_IN3_3 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_3 Mux input channel 3 of TIM module 0 QSPI1_MTSRA Slave SPI data input SCU_E_REQ3_0 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T5INB Trigger/gate input of timer T5 P10.3 O0 General-purpose output GTM_TOUT105 O1 GTM muxed output IOM_MON2_10 Monitor input 2 —O 2 Reserved QSPI1_MTSR O3 Master SPI data output MSC0_EN0 O4 Chip Select —O 5 Reserved CAN02_TXD O6 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 —O 7 Reserved B6 P10.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN7_3 Mux input channel 7 of TIM module 4 GTM_TIM1_IN6_2 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_2 Mux input channel 6 of TIM module 0 QSPI1_MTSRC Slave SPI data input CCU60_CCPOS0C Hall capture input 0 GPT120_T3INB Trigger/gate input of core timer T3 ASCLIN11_ARXB Receive input ASCLIN22_ARXA Receive input P10.4 O0 General-purpose output GTM_TOUT106 O1 GTM muxed output IOM_MON2_11 Monitor input 2 ASCLIN22_ATX O2 Transmit output QSPI1_SLSO8 O3 Master slave select output QSPI1_MTSR O4 Master SPI data output MSC0_EN0 O5 Chip Select —O 6 Reserved —O 7 Reserved Table 2-28 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 188 V 1.2, 2021-03 B5 P10.5 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM4_IN3_13 Mux input channel 3 of TIM module 4 GTM_TIM1_IN2_4 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_4 Mux input channel 2 of TIM module 0 PMS_HWCFG4IN HWCFG4 pin input CAN20_RXDA CAN receive input node 0 MSC0_INJ1 Injection signal from port ASCLIN22_ARXB Receive input P10.5 O0 General-purpose output GTM_TOUT107 O1 GTM muxed output IOM_REF2_9 Reference input 2 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI3_SLSO8 O3 Master slave select output QSPI1_SLSO9 O4 Master slave select output GPT120_T6OUT O5 External output for overflow/underflow detection of core timer T6 ASCLIN2_ASLSO O6 Slave select signal output PSI5_TX3 O7 TXD outputs (send data) Table 2-28 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 189 V 1.2, 2021-03 A4 P10.6 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM4_IN2_13 Mux input channel 2 of TIM module 4 GTM_TIM1_IN3_4 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_4 Mux input channel 3 of TIM module 0 PSI5_RX3C RXD inputs (receive data) channel 3 ASCLIN2_ARXD Receive input QSPI3_MTSRB Slave SPI data input PMS_HWCFG5IN HWCFG5 pin input ASCLIN23_ARXA Receive input P10.6 O0 General-purpose output GTM_TOUT108 O1 GTM muxed output IOM_REF2_10 Reference input 2 ASCLIN2_ASCLK O2 Shift clock output QSPI3_MTSR O3 Master SPI data output GPT120_T3OUT O4 External output for overflow/underflow detection of core timer T3 CAN20_TXD O5 CAN transmit output node 0 QSPI1_MRST O6 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 —O 7 Reserved Table 2-28 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 190 V 1.2, 2021-03 A3 P10.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN0_3 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_3 Mux input channel 0 of TIM module 0 GPT120_T3EUDB Count direction control input of core timer T3 ASCLIN2_ACTSA Clear to send input QSPI3_MRSTB Master SPI data input SCU_E_REQ0_2 ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CCU60_CCPOS1C Hall capture input 1 ASCLIN23_ARXB Receive input P10.7 O0 General-purpose output GTM_TOUT109 O1 GTM muxed output IOM_REF2_11 Reference input 2 ASCLIN23_ATX O2 Transmit output QSPI3_MRST O3 Slave SPI data output IOM_MON2_3 Monitor input 2 IOM_REF2_3 Reference input 2 —O 4 Reserved CAN20_TXD O5 CAN transmit output node 0 CAN12_TXD O6 CAN transmit output node 2 —O 7 Reserved Table 2-28 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 191 V 1.2, 2021-03 B4 P10.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN0_13 Mux input channel 0 of TIM module 4 GTM_TIM1_IN5_2 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_2 Mux input channel 5 of TIM module 0 CAN12_RXDB CAN receive input node 2 GPT120_T4INB Trigger/gate input of timer T4 QSPI3_SCLKB Slave SPI clock inputs SCU_E_REQ1_2 ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the MSB) CCU60_CCPOS2C Hall capture input 2 CAN20_RXDB CAN receive input node 0 P10.8 O0 General-purpose output GTM_TOUT110 O1 GTM muxed output ASCLIN2_ARTS O2 Ready to send output QSPI3_SCLK O3 Master SPI clock output ASCLIN23_ATX O4 Transmit output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-29 Port 11 Functions Ball Symbol Ctrl. Buffer Type Function E10 P11.0 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN0_4 Mux input channel 0 of TIM module 4 GTM_TIM2_IN0_7 Mux input channel 0 of TIM module 2 ASCLIN3_ARXB Receive input GTM_DTMA2_1 CDTM2_DTM4 P11.0 O0 General-purpose output GTM_TOUT119 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 3 Reserved —O 4 Reserved CAN11_TXD O5 CAN transmit output node 1 GETH_TXD3 O6 Transmit Data —O 7 Reserved Table 2-28 Port 10 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 192 V 1.2, 2021-03 E9 P11.1 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN1_5 Mux input channel 1 of TIM module 4 GTM_TIM2_IN1_6 Mux input channel 1 of TIM module 2 P11.1 O0 General-purpose output GTM_TOUT120 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output ASCLIN3_ATX O3 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 4 Reserved CAN12_TXD O5 CAN transmit output node 2 GETH_TXD2 O6 Transmit Data —O 7 Reserved A10 P11.2 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN1_3 Mux input channel 1 of TIM module 3 GTM_TIM2_IN1_3 Mux input channel 1 of TIM module 2 P11.2 O0 General-purpose output GTM_TOUT95 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO5 O3 Master slave select output QSPI1_SLSO5 O4 Master slave select output MSC0_EN1 O5 Chip Select GETH_TXD1 O6 Transmit Data CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 Table 2-29 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 193 V 1.2, 2021-03 B10 P11.3 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN2_2 Mux input channel 2 of TIM module 3 GTM_TIM2_IN2_2 Mux input channel 2 of TIM module 2 MSC0_SDI3 Upstream assynchronous input signal QSPI1_MRSTB Master SPI data input P11.3 O0 General-purpose output GTM_TOUT96 O1 GTM muxed output —O 2 Reserved QSPI1_MRST O3 Slave SPI data output IOM_MON2_1 Monitor input 2 IOM_REF2_1 Reference input 2 ERAY0_TXDA O4 Transmit Channel A —O 5 Reserved GETH_TXD0 O6 Transmit Data CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 D10 P11.4 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN2_5 Mux input channel 2 of TIM module 4 GTM_TIM2_IN2_6 Mux input channel 2 of TIM module 2 GETH_RXCLKB Receive Clock MII P11.4 O0 General-purpose output GTM_TOUT121 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output —O 3 Reserved —O 4 Reserved CAN13_TXD O5 CAN transmit output node 3 GETH_TXER O6 Transmit Error MII GETH_TXCLK O7 Transmit Clock Output for RGMII Table 2-29 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 194 V 1.2, 2021-03 D8 P11.5 I SLOW / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN3_5 Mux input channel 3 of TIM module 4 GTM_TIM2_IN3_8 Mux input channel 3 of TIM module 2 GETH_TXCLKA Transmit Clock Input for MII GETH_GREFCLK Gigabit Reference Clock input for RGMII (125 MHz high precission) P11.5 O0 General-purpose output GTM_TOUT122 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved CAN20_TXD O5 CAN transmit output node 0 —O 6 Reserved —O 7 Reserved D9 P11.6 I RFAST / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN3_2 Mux input channel 3 of TIM module 3 GTM_TIM2_IN3_2 Mux input channel 3 of TIM module 2 QSPI1_SCLKB Slave SPI clock inputs P11.6 O0 General-purpose output GTM_TOUT97 O1 GTM muxed output ERAY0_TXENB O2 Transmit Enable Channel B QSPI1_SCLK O3 Master SPI clock output ERAY0_TXENA O4 Transmit Enable Channel A MSC0_FCLP O5 Shift-clock direct part of the differential signal GETH_TXEN O6 Transmit Enable MII and RMII GETH_TCTL Transmit Control for RGMII CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-29 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 195 V 1.2, 2021-03 E8 P11.7 I SLOW / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN4_5 Mux input channel 4 of TIM module 4 GTM_TIM2_IN4_7 Mux input channel 4 of TIM module 2 GETH_RXD3A Receive Data 3 MII and RGMII (RGMII can use RXD3A only) CAN11_RXDD CAN receive input node 1 P11.7 O0 General-purpose output GTM_TOUT123 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved E7 P11.8 I SLOW / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN5_5 Mux input channel 5 of TIM module 4 GTM_TIM2_IN5_8 Mux input channel 5 of TIM module 2 GETH_RXD2A Receive Data 2 MII and RGMII (RGMII can use RXD2A only) CAN12_RXDD CAN receive input node 2 P11.8 O0 General-purpose output GTM_TOUT124 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-29 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 196 V 1.2, 2021-03 A9 P11.9 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN4_2 Mux input channel 4 of TIM module 3 GTM_TIM2_IN4_2 Mux input channel 4 of TIM module 2 QSPI1_MTSRB Slave SPI data input ERAY0_RXDA1 Receive Channel A1 GETH_RXD1A Receive Data 1 MII, RMII and RGMII (RGMII can use RXD1A only) P11.9 O0 General-purpose output GTM_TOUT98 O1 GTM muxed output —O 2 Reserved QSPI1_MTSR O3 Master SPI data output —O 4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 Table 2-29 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 197 V 1.2, 2021-03 B9 P11.10 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN5_2 Mux input channel 5 of TIM module 3 GTM_TIM2_IN5_2 Mux input channel 5 of TIM module 2 GTM_TIM2_IN0_9 Mux input channel 0 of TIM module 2 CAN03_RXDD CAN receive input node 3 ERAY0_RXDB1 Receive Channel B1 ASCLIN1_ARXE Receive input SCU_E_REQ6_3 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) MSC0_SDI0 Upstream assynchronous input signal GETH_RXD0A Receive Data 0 MII, RMII and RGMII (RGMII can use RXD0A only) QSPI1_SLSIA Slave select input P11.10 O0 General-purpose output GTM_TOUT99 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO3 O3 Master slave select output QSPI1_SLSO3 O4 Master slave select output —O 5 Reserved —O 6 Reserved CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-29 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 198 V 1.2, 2021-03 A8 P11.11 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN6_2 Mux input channel 6 of TIM module 3 GTM_TIM3_IN0_14 Mux input channel 0 of TIM module 3 GTM_TIM2_IN6_2 Mux input channel 6 of TIM module 2 GETH_CRSDVA Carrier Sense / Data Valid combi-signal for RMII GETH_RXDVA Receive Data Valid MII GETH_CRSB Carrier Sense MII GETH_RCTLA Receive Control for RGMII P11.11 O0 General-purpose output GTM_TOUT100 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO4 O3 Master slave select output QSPI1_SLSO4 O4 Master slave select output MSC0_EN0 O5 Chip Select ERAY0_TXENB O6 Transmit Enable Channel B CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 B8 P11.12 I FAST / RGMII_In put / PU1 / VFLEX / ES General-purpose input GTM_TIM3_IN7_2 Mux input channel 7 of TIM module 3 GTM_TIM2_IN7_2 Mux input channel 7 of TIM module 2 GETH_REFCLKA Reference Clock input for RMII (50 MHz) GETH_TXCLKB Transmit Clock Input for MII GETH_RXCLKA Receive Clock MII P11.12 O0 General-purpose output GTM_TOUT101 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 GTM_CLK2 O3 CGM generated clock ERAY0_TXDB O4 Transmit Channel B CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CCU_EXTCLK1 O6 External Clock 1 CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-29 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 199 V 1.2, 2021-03 E6 P11.13 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN6_5 Mux input channel 6 of TIM module 4 GTM_TIM2_IN6_7 Mux input channel 6 of TIM module 2 GETH_RXERA Receive Error MII I2C1_SDAA Serial Data Input 0 CAN13_RXDD CAN receive input node 3 P11.13 O0 General-purpose output GTM_TOUT125 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved I2C1_SDA O6 Serial Data Output —O 7 Reserved D7 P11.14 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN7_4 Mux input channel 7 of TIM module 4 GTM_TIM2_IN7_8 Mux input channel 7 of TIM module 2 GETH_CRSDVB Carrier Sense / Data Valid combi-signal for RMII GETH_RXDVB Receive Data Valid MII GETH_CRSA Carrier Sense MII I2C1_SCLA Serial Clock Input 0 CAN20_RXDF CAN receive input node 0 P11.14 O0 General-purpose output GTM_TOUT126 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved I2C1_SCL O6 Serial Clock Output —O 7 Reserved Table 2-29 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 200 V 1.2, 2021-03 D6 P11.15 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN7_5 Mux input channel 7 of TIM module 4 GTM_TIM0_IN7_8 Mux input channel 7 of TIM module 0 GETH_COLA Collision MII P11.15 O0 General-purpose output GTM_TOUT127 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-30 Port 12 Functions Ball Symbol Ctrl. Buffer Type Function E12 P12.0 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN0_5 Mux input channel 0 of TIM module 4 GTM_TIM3_IN0_7 Mux input channel 0 of TIM module 3 CAN00_RXDC CAN receive input node 0 GETH_RXCLKC Receive Clock MII GTM_DTMA4_0 CDTM4_DTM4 P12.0 O0 General-purpose output GTM_TOUT128 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved GETH_MDC O6 MDIO clock —O 7 Reserved Table 2-29 Port 11 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 201 V 1.2, 2021-03 E11 P12.1 I SLOW / PU1 / VFLEX / ES General-purpose input GTM_TIM4_IN1_6 Mux input channel 1 of TIM module 4 GTM_TIM3_IN1_6 Mux input channel 1 of TIM module 3 GETH_MDIOC MDIO Input P12.1 O0 General-purpose output GTM_TOUT129 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved —O 7 Reserved GETH_MDIO O MDIO Output Table 2-31 Port 13 Functions Ball Symbol Ctrl. Buffer Type Function B12 P13.0 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM3_IN5_3 Mux input channel 5 of TIM module 3 GTM_TIM2_IN5_3 Mux input channel 5 of TIM module 2 ASCLIN10_ARXC Receive input ASCLIN21_ARXA Receive input P13.0 O0 General-purpose output GTM_TOUT91 O1 GTM muxed output ASCLIN10_ATX O2 Transmit output QSPI2_SCLKN O3 Master SPI clock output (LVDS N line) MSC0_EN1 O4 Chip Select MSC0_FCLN O5 Shift-clock inverted part of the differential signal —O 6 Reserved CAN10_TXD O7 CAN transmit output node 0 Table 2-30 Port 12 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 202 V 1.2, 2021-03 A12 P13.1 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM3_IN6_3 Mux input channel 6 of TIM module 3 GTM_TIM2_IN6_3 Mux input channel 6 of TIM module 2 I2C0_SCLB Serial Clock Input 1 CAN10_RXDD CAN receive input node 0 ASCLIN10_ARXD Receive input P13.1 O0 General-purpose output GTM_TOUT92 O1 GTM muxed output —O 2 Reserved QSPI2_SCLKP O3 Master SPI clock output (LVDS P line) —O 4 Reserved MSC0_FCLP O5 Shift-clock direct part of the differential signal I2C0_SCL O6 Serial Clock Output —O 7 Reserved B11 P13.2 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM3_IN7_3 Mux input channel 7 of TIM module 3 GTM_TIM2_IN7_3 Mux input channel 7 of TIM module 2 GPT120_CAPINA Trigger input to capture value of timer T5 into CAPREL register I2C0_SDAB Serial Data Input 1 P13.2 O0 General-purpose output GTM_TOUT93 O1 GTM muxed output ASCLIN10_ASCLK O2 Shift clock output QSPI2_MTSRN O3 Master SPI data output (LVDS N line) MSC0_FCLP O4 Shift-clock direct part of the differential signal MSC0_SON O5 Data output - inverted part of the differential signal I2C0_SDA O6 Serial Data Output ASCLIN21_ATX O7 Transmit output Table 2-31 Port 13 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 203 V 1.2, 2021-03 A11 P13.3 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM3_IN0_3 Mux input channel 0 of TIM module 3 GTM_TIM2_IN0_3 Mux input channel 0 of TIM module 2 ASCLIN21_ARXB Receive input P13.3 O0 General-purpose output GTM_TOUT94 O1 GTM muxed output ASCLIN10_ASLSO O2 Slave select signal output QSPI2_MTSRP O3 Master SPI data output (LVDS P line) —O 4 Reserved MSC0_SOP O5 Data output - direct part of the differential signal ASCLIN21_ATX O6 Transmit output —O 7 Reserved Table 2-32 Port 14 Functions Ball Symbol Ctrl. Buffer Type Function B16 P14.0 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN3_5 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_5 Mux input channel 3 of TIM module 0 SENT_SENT17D Receive input channel 17 P14.0 O0 General-purpose output GTM_TOUT80 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 ERAY0_TXDA O3 Transmit Channel A ERAY0_TXDB O4 Transmit Channel B CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 Table 2-31 Port 13 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 204 V 1.2, 2021-03 A15 P14.1 I FAST / PU1 / VEXT / ES2 General-purpose input GTM_TIM1_IN4_3 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_3 Mux input channel 4 of TIM module 0 ERAY0_RXDA3 Receive Channel A3 ASCLIN0_ARXA Receive input SENT_SENT18D Receive input channel 18 ERAY0_RXDB3 Receive Channel B3 CAN01_RXDB CAN receive input node 1 SCU_E_REQ3_1 ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the MSB) PMS_PINAWKP PINA ( P14.1) pin input P14.1 O0 General-purpose output GTM_TOUT81 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 E13 P14.2 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN5_3 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_3 Mux input channel 5 of TIM module 0 PMS_HWCFG2IN HWCFG2 pin input P14.2 O0 General-purpose output GTM_TOUT82 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO1 O3 Master slave select output —O 4 Reserved —O 5 Reserved ASCLIN2_ASCLK O6 Shift clock output —O 7 Reserved Table 2-32 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 205 V 1.2, 2021-03 B14 P14.3 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN6_3 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_3 Mux input channel 6 of TIM module 0 PMS_HWCFG3IN HWCFG3 pin input ASCLIN2_ARXA Receive input MSC0_SDI2 Upstream assynchronous input signal SCU_E_REQ1_0 ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P14.3 O0 General-purpose output GTM_TOUT83 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI2_SLSO3 O3 Master slave select output ASCLIN1_ASLSO O4 Slave select signal output ASCLIN3_ASLSO O5 Slave select signal output —O 6 Reserved —O 7 Reserved B15 P14.4 I SLOW / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN7_2 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_2 Mux input channel 7 of TIM module 0 PMS_HWCFG6IN HWCFG6 pin input GTM_DTMT0_0 CDTM0_DTM0 P14.4 O0 General-purpose output GTM_TOUT84 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved GETH_PPS O6 Pulse Per Second —O 7 Reserved Table 2-32 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 206 V 1.2, 2021-03 A14 P14.5 I FAST / PU2 / VEXT / ES General-purpose input GTM_TIM1_IN0_4 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_4 Mux input channel 0 of TIM module 0 PMS_HWCFG1IN HWCFG1 pin input GTM_DTMA2_0 CDTM2_DTM4 P14.5 O0 General-purpose output GTM_TOUT85 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved ERAY0_TXDB O6 Transmit Channel B ERAY1_TXDB O7 Transmit Channel B B13 P14.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_4 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_4 Mux input channel 1 of TIM module 0 P14.6 O0 General-purpose output GTM_TOUT86 O1 GTM muxed output —O 2 Reserved QSPI2_SLSO2 O3 Master slave select output CAN13_TXD O4 CAN transmit output node 3 —O 5 Reserved ERAY0_TXENB O6 Transmit Enable Channel B ERAY1_TXENB O7 Transmit Enable Channel B Table 2-32 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 207 V 1.2, 2021-03 D13 P14.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN7_10 Mux input channel 7 of TIM module 4 GTM_TIM1_IN0_5 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_5 Mux input channel 0 of TIM module 0 ERAY0_RXDB0 Receive Channel B0 ERAY1_RXDB0 Receive Channel B0 CAN10_RXDB CAN receive input node 0 CAN13_RXDA CAN receive input node 3 ASCLIN9_ARXC Receive input ASCLIN20_ARXA Receive input P14.7 O0 General-purpose output GTM_TOUT87 O1 GTM muxed output ASCLIN0_ARTS O2 Ready to send output QSPI2_SLSO4 O3 Master slave select output ASCLIN9_ATX O4 Transmit output —O 5 Reserved —O 6 Reserved ASCLIN20_ATX O7 Transmit output A13 P14.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN2_3 Mux input channel 2 of TIM module 3 GTM_TIM2_IN2_3 Mux input channel 2 of TIM module 2 ERAY0_RXDA0 Receive Channel A0 CAN02_RXDD CAN receive input node 2 ASCLIN1_ARXD Receive input ERAY1_RXDA0 Receive Channel A0 P14.8 O0 General-purpose output GTM_TOUT88 O1 GTM muxed output ASCLIN5_ASLSO O2 Slave select signal output ASCLIN7_ASLSO O3 Slave select signal output —O 4 Reserved —O 5 Reserved —O 6 Reserved ASCLIN20_ATX O7 Transmit output Table 2-32 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 208 V 1.2, 2021-03 D12 P14.9 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN3_3 Mux input channel 3 of TIM module 3 GTM_TIM2_IN3_3 Mux input channel 3 of TIM module 2 ASCLIN0_ACTSA Clear to send input QSPI2_MRSTFN Master SPI data input (LVDS N line) ASCLIN9_ARXD Receive input ASCLIN20_ARXB Receive input P14.9 O0 General-purpose output GTM_TOUT89 O1 GTM muxed output CAN23_TXD O2 CAN transmit output node 3 MSC0_EN1 O3 Chip Select CAN10_TXD O4 CAN transmit output node 0 ERAY0_TXENB O5 Transmit Enable Channel B ERAY0_TXENA O6 Transmit Enable Channel A ERAY1_TXENA O7 Transmit Enable Channel A D11 P14.10 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN4_3 Mux input channel 4 of TIM module 3 GTM_TIM2_IN4_3 Mux input channel 4 of TIM module 2 CAN23_RXDA CAN receive input node 3 QSPI2_MRSTFP Master SPI data input (LVDS P line) P14.10 O0 General-purpose output GTM_TOUT90 O1 GTM muxed output —O 2 Reserved MSC0_EN0 O3 Chip Select ASCLIN1_ATX O4 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ERAY0_TXDA O6 Transmit Channel A ERAY1_TXDA O7 Transmit Channel A Table 2-32 Port 14 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 209 V 1.2, 2021-03 Table 2-33 Port 15 Functions Ball Symbol Ctrl. Buffer Type Function B20 P15.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN3_4 Mux input channel 3 of TIM module 3 GTM_TIM2_IN3_4 Mux input channel 3 of TIM module 2 P15.0 O0 General-purpose output GTM_TOUT71 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO13 O3 Master slave select output —O 4 Reserved CAN02_TXD O5 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output —O 7 Reserved A18 P15.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN4_4 Mux input channel 4 of TIM module 3 GTM_TIM2_IN4_4 Mux input channel 4 of TIM module 2 CAN02_RXDA CAN receive input node 2 ASCLIN1_ARXA Receive input QSPI2_SLSIB Slave select input SCU_E_REQ7_2 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.1 O0 General-purpose output GTM_TOUT72 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_SLSO5 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 210 V 1.2, 2021-03 C19 P15.2 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN5_4 Mux input channel 5 of TIM module 3 GTM_TIM2_IN5_4 Mux input channel 5 of TIM module 2 QSPI2_SLSIA Slave select input SENT_SENT10D Receive input channel 10 QSPI2_MRSTE Master SPI data input P15.2 O0 General-purpose output GTM_TOUT73 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SLSO0 O3 Master slave select output —O 4 Reserved CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ASCLK O6 Shift clock output —O 7 Reserved B17 P15.3 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN6_4 Mux input channel 6 of TIM module 3 GTM_TIM2_IN6_4 Mux input channel 6 of TIM module 2 CAN01_RXDA CAN receive input node 1 ASCLIN0_ARXB Receive input QSPI2_SCLKA Slave SPI clock inputs P15.3 O0 General-purpose output GTM_TOUT74 O1 GTM muxed output ASCLIN0_ATX O2 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 QSPI2_SCLK O3 Master SPI clock output —O 4 Reserved MSC0_EN1 O5 Chip Select —O 6 Reserved —O 7 Reserved Table 2-33 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 211 V 1.2, 2021-03 A17 P15.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN7_4 Mux input channel 7 of TIM module 3 GTM_TIM2_IN7_4 Mux input channel 7 of TIM module 2 I2C0_SCLC Serial Clock Input 2 QSPI2_MRSTA Master SPI data input SCU_E_REQ0_0 ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT11D Receive input channel 11 P15.4 O0 General-purpose output GTM_TOUT75 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MRST O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 ASCLIN19_ATX O4 Transmit output —O 5 Reserved I2C0_SCL O6 Serial Clock Output CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 Table 2-33 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 212 V 1.2, 2021-03 E14 P15.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN0_4 Mux input channel 0 of TIM module 3 GTM_TIM2_IN0_4 Mux input channel 0 of TIM module 2 ASCLIN1_ARXB Receive input I2C0_SDAC Serial Data Input 2 QSPI2_MTSRA Slave SPI data input SCU_E_REQ4_3 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.5 O0 General-purpose output GTM_TOUT76 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI2_MTSR O3 Master SPI data output —O 4 Reserved MSC0_EN0 O5 Chip Select I2C0_SDA O6 Serial Data Output CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 A16 P15.6 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM2_IN2_14 Mux input channel 2 of TIM module 2 GTM_TIM1_IN0_6 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_6 Mux input channel 0 of TIM module 0 QSPI2_MTSRB Slave SPI data input ASCLIN19_ARXA Receive input P15.6 O0 General-purpose output GTM_TOUT77 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MTSR O3 Master SPI data output —O 4 Reserved QSPI2_SCLK O5 Master SPI clock output ASCLIN3_ASCLK O6 Shift clock output CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 Table 2-33 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 213 V 1.2, 2021-03 D15 P15.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN1_5 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_5 Mux input channel 1 of TIM module 0 ASCLIN3_ARXA Receive input QSPI2_MRSTB Master SPI data input ASCLIN19_ARXB Receive input P15.7 O0 General-purpose output GTM_TOUT78 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI2_MRST O3 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 ASCLIN19_ATX O4 Transmit output —O 5 Reserved —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 D14 P15.8 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN2_5 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_5 Mux input channel 2 of TIM module 0 QSPI2_SCLKB Slave SPI clock inputs SCU_E_REQ5_0 ERU Channel 5 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P15.8 O0 General-purpose output GTM_TOUT79 O1 GTM muxed output —O 2 Reserved QSPI2_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved ASCLIN3_ASCLK O6 Shift clock output CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-33 Port 15 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 214 V 1.2, 2021-03 Table 2-34 Port 20 Functions Ball Symbol Ctrl. Buffer Type Function H20 P20.0 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN6_7 Mux input channel 6 of TIM module 1 GTM_TIM1_IN4_9 Mux input channel 4 of TIM module 1 GTM_TIM0_IN6_7 Mux input channel 6 of TIM module 0 CAN03_RXDC CAN receive input node 3 CCU_PAD_SYSCLK Sysclk input CAN21_RXDC CAN receive input node 1 CBS_TGI0 Trigger input SCU_E_REQ6_0 ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the MSB) GPT120_T6EUDA Count direction control input of core timer T6 P20.0 O0 General-purpose output GTM_TOUT59 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output —O 4 Reserved HSCT0_SYSCLK_OUT O5 sys clock output —O 6 Reserved —O 7 Reserved CBS_TGO0 O Trigger output G19 P20.1 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN4_11 Mux input channel 4 of TIM module 4 GTM_TIM3_IN3_5 Mux input channel 3 of TIM module 3 GTM_TIM2_IN3_5 Mux input channel 3 of TIM module 2 CBS_TGI1 Trigger input GTM_DTMA1_1 CDTM1_DTM4 P20.1 O0 General-purpose output GTM_TOUT60 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved CBS_TGO1 O Trigger output OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 215 V 1.2, 2021-03 H19 P20.2 I S / PU / VEXT General-purpose input This pin is latched at power on reset release to enter test mode. TESTMODE Testmode Enable Input G20 P20.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN5_11 Mux input channel 5 of TIM module 4 GTM_TIM3_IN4_5 Mux input channel 4 of TIM module 3 GTM_TIM2_IN4_5 Mux input channel 4 of TIM module 2 ASCLIN3_ARXC Receive input GPT120_T6INA Trigger/gate input of core timer T6 P20.3 O0 General-purpose output GTM_TOUT61 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 QSPI0_SLSO9 O3 Master slave select output QSPI2_SLSO9 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CAN21_TXD O6 CAN transmit output node 1 —O 7 Reserved F17 P20.6 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN0_1 Mux input channel 0 of TIM module 6 GTM_TIM3_IN6_5 Mux input channel 6 of TIM module 3 GTM_TIM2_IN6_5 Mux input channel 6 of TIM module 2 CAN12_RXDA CAN receive input node 2 ASCLIN9_ARXE Receive input P20.6 O0 General-purpose output GTM_TOUT62 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output QSPI0_SLSO8 O3 Master slave select output QSPI2_SLSO8 O4 Master slave select output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-34 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 216 V 1.2, 2021-03 F19 P20.7 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN7_5 Mux input channel 7 of TIM module 3 GTM_TIM2_IN7_5 Mux input channel 7 of TIM module 2 GTM_TIM1_IN5_8 Mux input channel 5 of TIM module 1 GTM_TIM6_IN1_1 Mux input channel 1 of TIM module 6 CAN00_RXDB CAN receive input node 0 ASCLIN1_ACTSA Clear to send input ASCLIN9_ARXF Receive input P20.7 O0 General-purpose output GTM_TOUT63 O1 GTM muxed output ASCLIN9_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved CAN12_TXD O5 CAN transmit output node 2 —O 6 Reserved CCU61_COUT63 O7 T13 PWM channel 63 IOM_MON1_7 Monitor input 1 IOM_REF1_7 Reference input 1 F20 P20.8 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN2_1 Mux input channel 2 of TIM module 6 GTM_TIM1_IN7_3 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_3 Mux input channel 7 of TIM module 0 P20.8 O0 General-purpose output GTM_TOUT64 O1 GTM muxed output ASCLIN1_ASLSO O2 Slave select signal output QSPI0_SLSO0 O3 Master slave select output QSPI1_SLSO0 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-34 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 217 V 1.2, 2021-03 E17 P20.9 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN3_1 Mux input channel 3 of TIM module 6 GTM_TIM3_IN5_5 Mux input channel 5 of TIM module 3 GTM_TIM2_IN5_5 Mux input channel 5 of TIM module 2 CAN03_RXDE CAN receive input node 3 ASCLIN1_ARXC Receive input QSPI0_SLSIB Slave select input SCU_E_REQ7_0 ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the MSB) P20.9 O0 General-purpose output GTM_TOUT65 O1 GTM muxed output —O 2 Reserved QSPI0_SLSO1 O3 Master slave select output QSPI1_SLSO1 O4 Master slave select output —O 5 Reserved —O 6 Reserved CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 E19 P20.10 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN6_6 Mux input channel 6 of TIM module 3 GTM_TIM2_IN6_6 Mux input channel 6 of TIM module 2 P20.10 O0 General-purpose output GTM_TOUT66 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI0_SLSO6 O3 Master slave select output QSPI2_SLSO7 O4 Master slave select output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 ASCLIN1_ASCLK O6 Shift clock output CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-34 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 218 V 1.2, 2021-03 E20 P20.11 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN7_6 Mux input channel 7 of TIM module 3 GTM_TIM2_IN7_6 Mux input channel 7 of TIM module 2 QSPI0_SCLKA Slave SPI clock inputs P20.11 O0 General-purpose output GTM_TOUT67 O1 GTM muxed output —O 2 Reserved QSPI0_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 D19 P20.12 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN0_5 Mux input channel 0 of TIM module 3 GTM_TIM2_IN0_5 Mux input channel 0 of TIM module 2 QSPI0_MRSTA Master SPI data input IOM_PIN_13 GPIO pad input to FPC P20.12 O0 General-purpose output GTM_TOUT68 O1 GTM muxed output IOM_MON0_13 Monitor input 0 —O 2 Reserved QSPI0_MRST O3 Slave SPI data output IOM_MON2_0 Monitor input 2 IOM_REF2_0 Reference input 2 QSPI0_MTSR O4 Master SPI data output —O 5 Reserved —O 6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 Table 2-34 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 219 V 1.2, 2021-03 D20 P20.13 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN1_4 Mux input channel 1 of TIM module 3 GTM_TIM2_IN1_4 Mux input channel 1 of TIM module 2 QSPI0_SLSIA Slave select input IOM_PIN_14 GPIO pad input to FPC P20.13 O0 General-purpose output GTM_TOUT69 O1 GTM muxed output IOM_MON0_14 Monitor input 0 —O 2 Reserved QSPI0_SLSO2 O3 Master slave select output QSPI1_SLSO2 O4 Master slave select output QSPI0_SCLK O5 Master SPI clock output —O 6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 C20 P20.14 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN2_4 Mux input channel 2 of TIM module 3 GTM_TIM2_IN2_4 Mux input channel 2 of TIM module 2 QSPI0_MTSRA Slave SPI data input IOM_PIN_15 GPIO pad input to FPC P20.14 O0 General-purpose output GTM_TOUT70 O1 GTM muxed output IOM_MON0_15 Monitor input 0 —O 2 Reserved QSPI0_MTSR O3 Master SPI data output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-34 Port 20 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 220 V 1.2, 2021-03 Table 2-35 Port 21 Functions Ball Symbol Ctrl. Buffer Type Function K17 P21.0 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN0_11 Mux input channel 0 of TIM module 4 GTM_TIM3_IN4_6 Mux input channel 4 of TIM module 3 GTM_TIM2_IN4_6 Mux input channel 4 of TIM module 2 QSPI4_MRSTDN Master SPI data input (LVDS N line) DMU_FDEST Enter destructive debug mode ASCLIN11_ARXC Receive input ASCLIN17_ARXB Receive input P21.0 O0 General-purpose output GTM_TOUT51 O1 GTM muxed output ASCLIN11_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSM_HSM1 O Pin Output Value J17 P21.1 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM4_IN1_13 Mux input channel 1 of TIM module 4 GTM_TIM3_IN5_6 Mux input channel 5 of TIM module 3 GTM_TIM2_IN5_6 Mux input channel 5 of TIM module 2 QSPI4_MRSTDP Master SPI data input (LVDS P line) ASCLIN11_ARXD Receive input ASCLIN18_ARXA Receive input GTM_DTMA4_1 CDTM4_DTM4 P21.1 O0 General-purpose output GTM_TOUT52 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSM_HSM2 O Pin Output Value OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 221 V 1.2, 2021-03 K19 P21.2 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN4_11 Mux input channel 4 of TIM module 5 GTM_TIM1_IN0_7 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_7 Mux input channel 0 of TIM module 0 QSPI2_MRSTCN Master SPI data input (LVDS N line) SCU_EMGSTOP_POR T_B Emergency stop Port Pin B input request ASCLIN3_ARXGN Differential Receive input (low active) HSCT0_RXDN Rx data QSPI4_MRSTCN Master SPI data input (LVDS N line) ASCLIN11_ARXE Receive input GTM_DTMA1_0 CDTM1_DTM4 P21.2 O0 General-purpose output GTM_TOUT53 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved GETH_MDC O5 MDIO clock —O 6 Reserved —O 7 Reserved J19 P21.3 I LVDS_R X / FAST / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN5_12 Mux input channel 5 of TIM module 5 GTM_TIM1_IN1_6 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_6 Mux input channel 1 of TIM module 0 QSPI2_MRSTCP Master SPI data input (LVDS P line) ASCLIN3_ARXGP Differential Receive input (high active) GETH_MDIOD MDIO Input HSCT0_RXDP Rx data QSPI4_MRSTCP Master SPI data input (LVDS P line) P21.3 O0 General-purpose output GTM_TOUT54 O1 GTM muxed output ASCLIN11_ASCLK O2 Shift clock output ASCLIN18_ATX O3 Transmit output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved GETH_MDIO O MDIO Output Table 2-35 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 222 V 1.2, 2021-03 K20 P21.4 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM5_IN6_12 Mux input channel 6 of TIM module 5 GTM_TIM1_IN2_6 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_6 Mux input channel 2 of TIM module 0 ASCLIN18_ARXB Receive input P21.4 O0 General-purpose output GTM_TOUT55 O1 GTM muxed output ASCLIN11_ASLSO O2 Slave select signal output ASCLIN18_ATX O3 Transmit output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSCT0_TXDN O Tx data J20 P21.5 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM5_IN7_11 Mux input channel 7 of TIM module 5 GTM_TIM1_IN3_6 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_6 Mux input channel 3 of TIM module 0 ASCLIN11_ARXF Receive input P21.5 O0 General-purpose output GTM_TOUT56 O1 GTM muxed output ASCLIN3_ASCLK O2 Shift clock output ASCLIN11_ATX O3 Transmit output —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved HSCT0_TXDP O Tx data Table 2-35 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 223 V 1.2, 2021-03 H17 P21.6/TDI I FAST / PD / PU2 / VEXT / ES3 General-purpose input PD during Reset and in DAP/DAPE or JTAG mode. After Reset release and when not in DAP/DAPE or JTAG mode: PU. In Standby mode: HighZ. GTM_TIM4_IN2_12 Mux input channel 2 of TIM module 4 GTM_TIM1_IN4_8 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_8 Mux input channel 4 of TIM module 0 GPT120_T5EUDA Count direction control input of timer T5 ASCLIN3_ARXF Receive input CBS_TGI2 Trigger input TDI JTAG Module Data Input P21.6 O0 General-purpose output GTM_TOUT57 O1 GTM muxed output ASCLIN3_ASLSO O2 Slave select signal output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved GPT120_T3OUT O7 External output for overflow/underflow detection of core timer T3 CBS_TGO2 O Trigger output DAP3 I/O DAP: DAP3 Data I/O Table 2-35 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 224 V 1.2, 2021-03 H16 P21.7/TDO I FAST / PU2 / VEXT / ES4 General-purpose input GTM_TIM4_IN3_12 Mux input channel 3 of TIM module 4 GTM_TIM1_IN5_7 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_7 Mux input channel 5 of TIM module 0 GPT120_T5INA Trigger/gate input of timer T5 CBS_TGI3 Trigger input GETH_RXERB Receive Error MII P21.7 O0 General-purpose output GTM_TOUT58 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 ASCLIN3_ASCLK O3 Shift clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved GPT120_T6OUT O7 External output for overflow/underflow detection of core timer T6 CBS_TGO3 O Trigger output DAP2 I/O DAP: DAP2 Data I/O TDO O JTAG Module Data Output Table 2-36 Port 22 Functions Ball Symbol Ctrl. Buffer Type Function P20 P22.0 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN1_7 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_7 Mux input channel 1 of TIM module 0 QSPI4_MTSRB Slave SPI data input ASCLIN6_ARXE Receive input P22.0 O0 General-purpose output GTM_TOUT47 O1 GTM muxed output ASCLIN3_ATXN O2 Differential Transmit output (low active) QSPI4_MTSR O3 Master SPI data output QSPI4_SCLKN O4 Master SPI clock output (LVDS N line) MSC1_FCLN O5 Shift-clock inverted part of the differential signal —O 6 Reserved ASCLIN6_ATX O7 Transmit output Table 2-35 Port 21 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 225 V 1.2, 2021-03 P19 P22.1 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN0_8 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_8 Mux input channel 0 of TIM module 0 QSPI4_MRSTB Master SPI data input ASCLIN7_ARXE Receive input P22.1 O0 General-purpose output GTM_TOUT48 O1 GTM muxed output ASCLIN3_ATXP O2 Differential Transmit output (high active) QSPI4_MRST O3 Slave SPI data output IOM_MON2_4 Monitor input 2 IOM_REF2_4 Reference input 2 QSPI4_SCLKP O4 Master SPI clock output (LVDS P line) MSC1_FCLP O5 Shift-clock direct part of the differential signal —O 6 Reserved ASCLIN7_ATX O7 Transmit output R20 P22.2 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN3_7 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_7 Mux input channel 3 of TIM module 0 QSPI4_SLSIB Slave select input P22.2 O0 General-purpose output GTM_TOUT49 O1 GTM muxed output ASCLIN5_ATX O2 Transmit output QSPI4_SLSO3 O3 Master slave select output QSPI4_MTSRN O4 Master SPI data output (LVDS N line) MSC1_SON O5 Data output - inverted part of the differential signal —O 6 Reserved —O 7 Reserved Table 2-36 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 226 V 1.2, 2021-03 R19 P22.3 I LVDS_TX / FAST / PU1 / VEXT / ES6 General-purpose input GTM_TIM1_IN4_4 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_4 Mux input channel 4 of TIM module 0 QSPI4_SCLKB Slave SPI clock inputs ASCLIN5_ARXC Receive input P22.3 O0 General-purpose output GTM_TOUT50 O1 GTM muxed output —O 2 Reserved QSPI4_SCLK O3 Master SPI clock output QSPI4_MTSRP O4 Master SPI data output (LVDS P line) MSC1_SOP O5 Data output - direct part of the differential signal —O 6 Reserved —O 7 Reserved P16 P22.4 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN0_8 Mux input channel 0 of TIM module 3 ASCLIN7_ARXF Receive input GTM_DTMA3_0 CDTM3_DTM4 P22.4 O0 General-purpose output GTM_TOUT130 O1 GTM muxed output ASCLIN4_ASLSO O2 Slave select signal output —O 3 Reserved QSPI0_SLSO12 O4 Master slave select output —O 5 Reserved CAN13_TXD O6 CAN transmit output node 3 —O 7 Reserved P17 P22.5 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN1_7 Mux input channel 1 of TIM module 3 QSPI0_MTSRC Slave SPI data input CAN13_RXDC CAN receive input node 3 P22.5 O0 General-purpose output GTM_TOUT131 O1 GTM muxed output ASCLIN4_ATX O2 Transmit output —O 3 Reserved QSPI0_MTSR O4 Master SPI data output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-36 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 227 V 1.2, 2021-03 N16 P22.6 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN2_6 Mux input channel 2 of TIM module 3 GTM_TIM2_IN6_14 Mux input channel 6 of TIM module 2 QSPI0_MRSTC Master SPI data input ASCLIN4_ARXC Receive input P22.6 O0 General-purpose output GTM_TOUT132 O1 GTM muxed output —O 2 Reserved —O 3 Reserved QSPI0_MRST O4 Slave SPI data output IOM_MON2_0 Monitor input 2 IOM_REF2_0 Reference input 2 CAN21_TXD O5 CAN transmit output node 1 —O 6 Reserved —O 7 Reserved N17 P22.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM3_IN3_7 Mux input channel 3 of TIM module 3 QSPI0_SCLKC Slave SPI clock inputs CAN21_RXDF CAN receive input node 1 P22.7 O0 General-purpose output GTM_TOUT133 O1 GTM muxed output ASCLIN4_ASCLK O2 Shift clock output ASCLIN17_ATX O3 Transmit output QSPI0_SCLK O4 Master SPI clock output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-36 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 228 V 1.2, 2021-03 M16 P22.8 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN0_4 Mux input channel 0 of TIM module 5 GTM_TIM3_IN4_7 Mux input channel 4 of TIM module 3 QSPI0_SCLKB Slave SPI clock inputs P22.8 O0 General-purpose output GTM_TOUT134 O1 GTM muxed output ASCLIN5_ASCLK O2 Shift clock output —O 3 Reserved QSPI0_SCLK O4 Master SPI clock output CAN22_TXD O5 CAN transmit output node 2 —O 6 Reserved —O 7 Reserved M17 P22.9 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN1_10 Mux input channel 1 of TIM module 5 GTM_TIM3_IN5_7 Mux input channel 5 of TIM module 3 QSPI0_MRSTB Master SPI data input ASCLIN4_ARXD Receive input CAN22_RXDE CAN receive input node 2 GTM_DTMA3_1 CDTM3_DTM4 P22.9 O0 General-purpose output GTM_TOUT135 O1 GTM muxed output —O 2 Reserved —O 3 Reserved QSPI0_MRST O4 Slave SPI data output IOM_MON2_0 Monitor input 2 IOM_REF2_0 Reference input 2 —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-36 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 229 V 1.2, 2021-03 L16 P22.10 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN2_8 Mux input channel 2 of TIM module 5 GTM_TIM3_IN6_7 Mux input channel 6 of TIM module 3 QSPI0_MTSRB Slave SPI data input P22.10 O0 General-purpose output GTM_TOUT136 O1 GTM muxed output ASCLIN4_ATX O2 Transmit output —O 3 Reserved QSPI0_MTSR O4 Master SPI data output CAN23_TXD O5 CAN transmit output node 3 —O 6 Reserved —O 7 Reserved L17 P22.11 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN3_10 Mux input channel 3 of TIM module 5 GTM_TIM3_IN7_7 Mux input channel 7 of TIM module 3 CAN23_RXDE CAN receive input node 3 ASCLIN17_ARXA Receive input P22.11 O0 General-purpose output GTM_TOUT137 O1 GTM muxed output ASCLIN4_ASLSO O2 Slave select signal output ASCLIN17_ATX O3 Transmit output QSPI0_SLSO10 O4 Master slave select output —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-36 Port 22 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 230 V 1.2, 2021-03 Table 2-37 Port 23 Functions Ball Symbol Ctrl. Buffer Type Function V20 P23.0 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN7_1 Mux input channel 7 of TIM module 6 GTM_TIM1_IN5_4 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_4 Mux input channel 5 of TIM module 0 CAN10_RXDC CAN receive input node 0 P23.0 O0 General-purpose output GTM_TOUT41 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved U19 P23.1 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN6_1 Mux input channel 6 of TIM module 6 GTM_TIM1_IN6_4 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_4 Mux input channel 6 of TIM module 0 MSC1_SDI0 Upstream assynchronous input signal ASCLIN6_ARXF Receive input P23.1 O0 General-purpose output GTM_TOUT42 O1 GTM muxed output ASCLIN1_ARTS O2 Ready to send output QSPI4_SLSO6 O3 Master slave select output GTM_CLK0 O4 CGM generated clock CAN10_TXD O5 CAN transmit output node 0 CCU_EXTCLK0 O6 External Clock 0 ASCLIN6_ASCLK O7 Shift clock output OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 231 V 1.2, 2021-03 U20 P23.2 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN5_1 Mux input channel 5 of TIM module 6 GTM_TIM1_IN6_5 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_5 Mux input channel 6 of TIM module 0 ASCLIN7_ARXC Receive input P23.2 O0 General-purpose output GTM_TOUT43 O1 GTM muxed output —O 2 Reserved —O 3 Reserved CAN23_TXD O4 CAN transmit output node 3 CAN12_TXD O5 CAN transmit output node 2 —O 6 Reserved —O 7 Reserved T19 P23.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN4_2 Mux input channel 4 of TIM module 6 GTM_TIM1_IN7_4 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_4 Mux input channel 7 of TIM module 0 MSC1_INJ0 Injection signal from port ASCLIN6_ARXA Receive input CAN12_RXDC CAN receive input node 2 CAN23_RXDB CAN receive input node 3 P23.3 O0 General-purpose output GTM_TOUT44 O1 GTM muxed output ASCLIN7_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-37 Port 23 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 232 V 1.2, 2021-03 T20 P23.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN3_2 Mux input channel 3 of TIM module 6 GTM_TIM1_IN7_5 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_5 Mux input channel 7 of TIM module 0 P23.4 O0 General-purpose output GTM_TOUT45 O1 GTM muxed output ASCLIN6_ASLSO O2 Slave select signal output QSPI4_SLSO5 O3 Master slave select output —O 4 Reserved MSC1_EN0 O5 Chip Select —O 6 Reserved —O 7 Reserved T17 P23.5 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN2_2 Mux input channel 2 of TIM module 6 GTM_TIM1_IN2_7 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_7 Mux input channel 2 of TIM module 0 ASCLIN16_ARXA Receive input P23.5 O0 General-purpose output GTM_TOUT46 O1 GTM muxed output ASCLIN6_ATX O2 Transmit output QSPI4_SLSO4 O3 Master slave select output —O 4 Reserved MSC1_EN1 O5 Chip Select CAN22_TXD O6 CAN transmit output node 2 —O 7 Reserved R17 P23.6 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN1_2 Mux input channel 1 of TIM module 6 GTM_TIM4_IN2_7 Mux input channel 2 of TIM module 4 GTM_TIM1_IN2_10 Mux input channel 2 of TIM module 1 CAN22_RXDC CAN receive input node 2 P23.6 O0 General-purpose output GTM_TOUT138 O1 GTM muxed output ASCLIN16_ATX O2 Transmit output —O 3 Reserved QSPI0_SLSO11 O4 Master slave select output CAN11_TXD O5 CAN transmit output node 1 —O 6 Reserved —O 7 Reserved Table 2-37 Port 23 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 233 V 1.2, 2021-03 R16 P23.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM6_IN0_2 Mux input channel 0 of TIM module 6 GTM_TIM4_IN3_7 Mux input channel 3 of TIM module 4 GTM_TIM1_IN3_10 Mux input channel 3 of TIM module 1 CAN11_RXDC CAN receive input node 1 ASCLIN16_ARXB Receive input P23.7 O0 General-purpose output GTM_TOUT139 O1 GTM muxed output ASCLIN16_ATX O2 Transmit output —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-38 Port 32 Functions Ball Symbol Ctrl. Buffer Type Function Y17 P32.0 I SLOW / PU1 / VEXT / ES General-purpose input P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC GTM_TIM3_IN2_5 Mux input channel 2 of TIM module 3 GTM_TIM2_IN2_5 Mux input channel 2 of TIM module 2 P32.0 O0 General-purpose output GTM_TOUT36 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Table 2-37 Port 23 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 234 V 1.2, 2021-03 W17 P32.1 I SLOW / PU1 / VEXT / ES General-purpose input P32.1 / External Pass Device gate control for EVRC GTM_TIM3_IN3_15 Mux input channel 3 of TIM module 3 P32.1 O0 General-purpose output GTM_TOUT37 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved —O 7 Reserved Y18 P32.2 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN3_8 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_8 Mux input channel 3 of TIM module 0 CAN03_RXDB CAN receive input node 3 ASCLIN3_ARXD Receive input CAN21_RXDD CAN receive input node 1 P32.2 O0 General-purpose output GTM_TOUT38 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 3 Reserved —O 4 Reserved —O 5 Reserved PMS_DCDCSYNCO O6 DC-DC synchronization output —O 7 Reserved Table 2-38 Port 32 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 235 V 1.2, 2021-03 Y19 P32.3 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN4_5 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_5 Mux input channel 4 of TIM module 0 P32.3 O0 General-purpose output GTM_TOUT39 O1 GTM muxed output ASCLIN3_ATX O2 Transmit output IOM_MON2_15 Monitor input 2 IOM_REF2_15 Reference input 2 —O 3 Reserved ASCLIN3_ASCLK O4 Shift clock output CAN03_TXD O5 CAN transmit output node 3 IOM_MON2_8 Monitor input 2 IOM_REF2_8 Reference input 2 CAN21_TXD O6 CAN transmit output node 1 —O 7 Reserved W18 P32.4 I FAST / PU1 / VEXT / ES General-purpose input GTM_TIM1_IN5_5 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_5 Mux input channel 5 of TIM module 0 ASCLIN1_ACTSB Clear to send input MSC1_SDI2 Upstream assynchronous input signal ASCLIN15_ARXA Receive input P32.4 O0 General-purpose output GTM_TOUT40 O1 GTM muxed output PMS_DCDCSYNCO O2 DC-DC synchronization output —O 3 Reserved GTM_CLK1 O4 CGM generated clock MSC1_EN0 O5 Chip Select CCU_EXTCLK1 O6 External Clock 1 CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 Table 2-38 Port 32 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 236 V 1.2, 2021-03 T15 P32.5 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN5_9 Mux input channel 5 of TIM module 5 GTM_TIM4_IN1_14 Mux input channel 1 of TIM module 4 GTM_TIM3_IN5_8 Mux input channel 5 of TIM module 3 SENT_SENT10C Receive input channel 10 P32.5 O0 General-purpose output GTM_TOUT140 O1 GTM muxed output ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 —O 3 Reserved —O 4 Reserved —O 5 Reserved CAN02_TXD O6 CAN transmit output node 2 IOM_MON2_7 Monitor input 2 IOM_REF2_7 Reference input 2 —O 7 Reserved U15 P32.6 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN6_9 Mux input channel 6 of TIM module 5 GTM_TIM4_IN4_15 Mux input channel 4 of TIM module 4 GTM_TIM3_IN6_8 Mux input channel 6 of TIM module 3 CAN02_RXDC CAN receive input node 2 CBS_TGI4 Trigger input ASCLIN2_ARXF Receive input ASCLIN6_ARXC Receive input SENT_SENT11C Receive input channel 11 P32.6 O0 General-purpose output GTM_TOUT141 O1 GTM muxed output —O 2 Reserved —O 3 Reserved QSPI2_SLSO12 O4 Master slave select output CAN22_TXD O5 CAN transmit output node 2 —O 6 Reserved —O 7 Reserved CBS_TGO4 O Trigger output Table 2-38 Port 32 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 237 V 1.2, 2021-03 U16 P32.7 I SLOW / PU1 / VEXT / ES General-purpose input GTM_TIM5_IN7_8 Mux input channel 7 of TIM module 5 GTM_TIM4_IN0_15 Mux input channel 0 of TIM module 4 GTM_TIM3_IN7_8 Mux input channel 7 of TIM module 3 CBS_TGI5 Trigger input CAN22_RXDB CAN receive input node 2 SENT_SENT12C Receive input channel 12 ASCLIN15_ARXB Receive input P32.7 O0 General-purpose output GTM_TOUT142 O1 GTM muxed output ASCLIN6_ATX O2 Transmit output —O 3 Reserved ASCLIN15_ATX O4 Transmit output —O 5 Reserved —O 6 Reserved —O 7 Reserved CBS_TGO5 O Trigger output Table 2-38 Port 32 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 238 V 1.2, 2021-03 Table 2-39 Port 33 Functions Ball Symbol Ctrl. Buffer Type Function W10 P33.0 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN0_13 Mux input channel 0 of TIM module 3 GTM_TIM1_IN4_6 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_6 Mux input channel 4 of TIM module 0 EDSADC_ITR0E Trigger/Gate input, channel 0 SENT_SENT13C Receive input channel 13 IOM_PIN_0 GPIO pad input to FPC GTM_DTMT1_2 CDTM1_DTM0 EVADC_G10CH7 AI Analog input channel 7, group 10 P33.0 O0 General-purpose output GTM_TOUT22 O1 GTM muxed output IOM_MON0_0 Monitor input 0 IOM_GTM_0 GTM-provided inputs to EXOR combiner ASCLIN5_ATX O2 Transmit output —O 3 Reserved ASCLIN15_ATX O4 Transmit output —O 5 Reserved EVADC_FC2BFLOUT O6 Boundary flag output, FC channel 2 —O 7 Reserved OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 239 V 1.2, 2021-03 Y10 P33.1 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN1_15 Mux input channel 1 of TIM module 3 GTM_TIM1_IN5_6 Mux input channel 5 of TIM module 1 GTM_TIM0_IN5_6 Mux input channel 5 of TIM module 0 EDSADC_ITR1E Trigger/Gate input, channel 1 PSI5_RX0C RXD inputs (receive data) channel 0 EDSADC_DSCIN2B Modulator clock input, channel 2 SENT_SENT9C Receive input channel 9 ASCLIN8_ARXC Receive input IOM_PIN_1 GPIO pad input to FPC EVADC_G10CH6 AI Analog input channel 6, group 10 P33.1 O0 General-purpose output GTM_TOUT23 O1 GTM muxed output IOM_MON0_1 Monitor input 0 IOM_GTM_1 GTM-provided inputs to EXOR combiner ASCLIN3_ASLSO O2 Slave select signal output QSPI2_SCLK O3 Master SPI clock output EDSADC_DSCOUT2 O4 Modulator clock output EVADC_EMUX02 O5 Control of external analog multiplexer interface 0 —O 6 Reserved —O 7 Reserved Table 2-39 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 240 V 1.2, 2021-03 W11 P33.2 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN2_14 Mux input channel 2 of TIM module 3 GTM_TIM1_IN6_6 Mux input channel 6 of TIM module 1 GTM_TIM0_IN6_6 Mux input channel 6 of TIM module 0 EDSADC_ITR2E Trigger/Gate input, channel 2 SENT_SENT8C Receive input channel 8 EDSADC_DSDIN2B Digital datastream input, channel 2 IOM_PIN_2 GPIO pad input to FPC EVADC_G10CH5 AI Analog input channel 5, group 10 P33.2 O0 General-purpose output GTM_TOUT24 O1 GTM muxed output IOM_MON0_2 Monitor input 0 IOM_GTM_2 GTM-provided inputs to EXOR combiner ASCLIN3_ASCLK O2 Shift clock output QSPI2_SLSO10 O3 Master slave select output PSI5_TX0 O4 TXD outputs (send data) IOM_MON1_14 Monitor input 1 IOM_REF1_14 Reference input 1 EVADC_EMUX01 O5 Control of external analog multiplexer interface 0 EVADC_FC3BFLOUT O6 Boundary flag output, FC channel 3 ASCLIN14_ATX O7 Transmit output Table 2-39 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 241 V 1.2, 2021-03 Y11 P33.3 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN3_12 Mux input channel 3 of TIM module 3 GTM_TIM1_IN7_6 Mux input channel 7 of TIM module 1 GTM_TIM0_IN7_6 Mux input channel 7 of TIM module 0 PSI5_RX1C RXD inputs (receive data) channel 1 SENT_SENT7C Receive input channel 7 EDSADC_DSCIN1B Modulator clock input, channel 1 ASCLIN14_ARXA Receive input IOM_PIN_3 GPIO pad input to FPC EVADC_G10CH4 AI Analog input channel 4, group 10 P33.3 O0 General-purpose output GTM_TOUT25 O1 GTM muxed output IOM_MON0_3 Monitor input 0 IOM_GTM_3 GTM-provided inputs to EXOR combiner ASCLIN5_ASCLK O2 Shift clock output QSPI4_SLSO2 O3 Master slave select output EDSADC_DSCOUT1 O4 Modulator clock output EVADC_EMUX00 O5 Control of external analog multiplexer interface 0 —O 6 Reserved ASCLIN14_ATX O7 Transmit output Table 2-39 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 242 V 1.2, 2021-03 W12 P33.4 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM4_IN4_10 Mux input channel 4 of TIM module 4 GTM_TIM1_IN0_10 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_10 Mux input channel 0 of TIM module 0 EDSADC_ITR0F Trigger/Gate input, channel 0 SENT_SENT6C Receive input channel 6 EDSADC_DSDIN1B Digital datastream input, channel 1 CCU61_CTRAPC Trap input capture ASCLIN5_ARXB Receive input ASCLIN14_ARXB Receive input IOM_PIN_4 GPIO pad input to FPC GTM_DTMT2_0 CDTM2_DTM0 EVADC_G10CH3 AI Analog input channel 3, group 10 P33.4 O0 General-purpose output GTM_TOUT26 O1 GTM muxed output IOM_MON0_4 Monitor input 0 IOM_GTM_4 GTM-provided inputs to EXOR combiner ASCLIN2_ARTS O2 Ready to send output QSPI2_SLSO12 O3 Master slave select output PSI5_TX1 O4 TXD outputs (send data) IOM_MON1_15 Monitor input 1 EVADC_EMUX12 O5 Control of external analog multiplexer interface 1 EVADC_FC0BFLOUT O6 Boundary flag output, FC channel 0 CAN13_TXD O7 CAN transmit output node 3 Table 2-39 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 243 V 1.2, 2021-03 Y12 P33.5 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM4_IN5_10 Mux input channel 5 of TIM module 4 GTM_TIM1_IN1_8 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_8 Mux input channel 1 of TIM module 0 EDSADC_DSCIN0B Modulator clock input, channel 0 EDSADC_ITR1F Trigger/Gate input, channel 1 GPT120_T4EUDB Count direction control input of timer T4 PSI5S_RXC RX data input ASCLIN2_ACTSB Clear to send input CCU61_CCPOS2C Hall capture input 2 PSI5_RX2C RXD inputs (receive data) channel 2 SENT_SENT5C Receive input channel 5 CAN13_RXDB CAN receive input node 3 IOM_PIN_5 GPIO pad input to FPC EVADC_G10CH2 AI Analog input channel 2, group 10 P33.5 O0 General-purpose output GTM_TOUT27 O1 GTM muxed output IOM_MON0_5 Monitor input 0 IOM_GTM_5 GTM-provided inputs to EXOR combiner QSPI0_SLSO7 O2 Master slave select output QSPI1_SLSO7 O3 Master slave select output EDSADC_DSCOUT0 O4 Modulator clock output EVADC_EMUX11 O5 Control of external analog multiplexer interface 1 EVADC_FC2BFLOUT O6 Boundary flag output, FC channel 2 ASCLIN5_ASLSO O7 Slave select signal output Table 2-39 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 244 V 1.2, 2021-03 W13 P33.6 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN2_9 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_9 Mux input channel 2 of TIM module 0 EDSADC_ITR2F Trigger/Gate input, channel 2 GPT120_T2EUDB Count direction control input of timer T2 SENT_SENT4C Receive input channel 4 CCU61_CCPOS1C Hall capture input 1 EDSADC_DSDIN0B Digital datastream input, channel 0 ASCLIN8_ARXD Receive input IOM_PIN_6 GPIO pad input to FPC GTM_DTMT2_1 CDTM2_DTM0 EVADC_G10CH1 AI Analog input channel 1, group 10 P33.6 O0 General-purpose output GTM_TOUT28 O1 GTM muxed output IOM_MON0_6 Monitor input 0 IOM_GTM_6 GTM-provided inputs to EXOR combiner ASCLIN2_ASLSO O2 Slave select signal output QSPI2_SLSO11 O3 Master slave select output PSI5_TX2 O4 TXD outputs (send data) IOM_REF1_15 Reference input 1 EVADC_EMUX10 O5 Control of external analog multiplexer interface 1 EVADC_FC1BFLOUT O6 Boundary flag output, FC channel 1 PSI5S_TX O7 TX data output Table 2-39 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 245 V 1.2, 2021-03 Y13 P33.7 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN3_9 Mux input channel 3 of TIM module 1 GTM_TIM0_IN3_9 Mux input channel 3 of TIM module 0 CAN00_RXDE CAN receive input node 0 GPT120_T2INB Trigger/gate input of timer T2 CCU61_CCPOS0C Hall capture input 0 SCU_E_REQ4_0 ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the MSB) SENT_SENT14C Receive input channel 14 IOM_PIN_7 GPIO pad input to FPC EVADC_G10CH0 AI Analog input channel 0, group 10 P33.7 O0 General-purpose output GTM_TOUT29 O1 GTM muxed output IOM_MON0_7 Monitor input 0 IOM_GTM_7 GTM-provided inputs to EXOR combiner ASCLIN2_ASCLK O2 Shift clock output QSPI4_SLSO7 O3 Master slave select output ASCLIN8_ATX O4 Transmit output —O 5 Reserved EVADC_FC3BFLOUT O6 Boundary flag output, FC channel 3 —O 7 Reserved Table 2-39 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 246 V 1.2, 2021-03 W14 P33.8 I FAST / HighZ / VEVRSB General-purpose input GTM_TIM1_IN4_7 Mux input channel 4 of TIM module 1 GTM_TIM0_IN4_7 Mux input channel 4 of TIM module 0 ASCLIN2_ARXE Receive input SCU_EMGSTOP_POR T_A Emergency stop Port Pin A input request IOM_PIN_8 GPIO pad input to FPC P33.8 O0 General-purpose output GTM_TOUT30 O1 GTM muxed output IOM_MON0_8 Monitor input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI4_SLSO2 O3 Master slave select output —O 4 Reserved CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved CCU61_COUT62 O7 T12 PWM channel 62 IOM_MON1_13 Monitor input 1 IOM_REF1_8 Reference input 1 SMU_FSP0 O FSP[1..0] Output Signals - Generated by SMU_core Table 2-39 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 247 V 1.2, 2021-03 Y14 P33.9 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN1_9 Mux input channel 1 of TIM module 1 GTM_TIM0_IN1_9 Mux input channel 1 of TIM module 0 IOM_PIN_9 GPIO pad input to FPC P33.9 O0 General-purpose output GTM_TOUT31 O1 GTM muxed output IOM_MON0_9 Monitor input 0 ASCLIN2_ATX O2 Transmit output IOM_MON2_14 Monitor input 2 IOM_REF2_14 Reference input 2 QSPI4_SLSO1 O3 Master slave select output ASCLIN2_ASCLK O4 Shift clock output CAN01_TXD O5 CAN transmit output node 1 IOM_MON2_6 Monitor input 2 IOM_REF2_6 Reference input 2 ASCLIN0_ATX O6 Transmit output IOM_MON2_12 Monitor input 2 IOM_REF2_12 Reference input 2 CCU61_CC62 O7 T12 PWM channel 62 IOM_MON1_10 Monitor input 1 IOM_REF1_11 Reference input 1 Table 2-39 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 248 V 1.2, 2021-03 W15 P33.10 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM4_IN4_14 Mux input channel 4 of TIM module 4 GTM_TIM1_IN0_9 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_9 Mux input channel 0 of TIM module 0 QSPI4_SLSIA Slave select input CAN01_RXDD CAN receive input node 1 ASCLIN0_ARXD Receive input IOM_PIN_10 GPIO pad input to FPC P33.10 O0 General-purpose output GTM_TOUT32 O1 GTM muxed output IOM_MON0_10 Monitor input 0 QSPI1_SLSO6 O2 Master slave select output QSPI4_SLSO0 O3 Master slave select output ASCLIN1_ASLSO O4 Slave select signal output PSI5S_CLK O5 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. —O 6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 SMU_FSP1 O FSP[1..0] Output Signals - Generated by SMU_core Y15 P33.11 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN2_8 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_8 Mux input channel 2 of TIM module 0 QSPI4_SCLKA Slave SPI clock inputs IOM_PIN_11 GPIO pad input to FPC P33.11 O0 General-purpose output GTM_TOUT33 O1 GTM muxed output IOM_MON0_11 Monitor input 0 ASCLIN1_ASCLK O2 Shift clock output QSPI4_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved EDSADC_CGPWMN O6 Negative carrier generator output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-39 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 249 V 1.2, 2021-03 W16 P33.12 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN0_6 Mux input channel 0 of TIM module 3 GTM_TIM2_IN0_6 Mux input channel 0 of TIM module 2 QSPI4_MTSRA Slave SPI data input CAN00_RXDD CAN receive input node 0 PMS_PINBWKP PINB (P33.12) pin input IOM_PIN_12 GPIO pad input to FPC P33.12 O0 General-purpose output GTM_TOUT34 O1 GTM muxed output IOM_MON0_12 Monitor input 0 ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI4_MTSR O3 Master SPI data output ASCLIN1_ASCLK O4 Shift clock output CAN22_TXD O5 CAN transmit output node 2 EDSADC_CGPWMP O6 Positive carrier generator output CCU61_COUT60 O7 T12 PWM channel 60 IOM_MON1_11 Monitor input 1 IOM_REF1_10 Reference input 1 Table 2-39 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 250 V 1.2, 2021-03 Y16 P33.13 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM3_IN1_5 Mux input channel 1 of TIM module 3 GTM_TIM2_IN1_5 Mux input channel 1 of TIM module 2 ASCLIN1_ARXF Receive input EDSADC_SGNB Carrier sign signal input QSPI4_MRSTA Master SPI data input MSC1_INJ1 Injection signal from port CAN22_RXDA CAN receive input node 2 P33.13 O0 General-purpose output GTM_TOUT35 O1 GTM muxed output ASCLIN1_ATX O2 Transmit output IOM_MON2_13 Monitor input 2 IOM_REF2_13 Reference input 2 QSPI4_MRST O3 Slave SPI data output IOM_MON2_4 Monitor input 2 IOM_REF2_4 Reference input 2 QSPI2_SLSO6 O4 Master slave select output CAN00_TXD O5 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 —O 6 Reserved CCU61_CC60 O7 T12 PWM channel 60 IOM_MON1_8 Monitor input 1 IOM_REF1_13 Reference input 1 Table 2-39 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 251 V 1.2, 2021-03 T14 P33.14 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM5_IN0_8 Mux input channel 0 of TIM module 5 GTM_TIM4_IN5_14 Mux input channel 5 of TIM module 4 GTM_TIM2_IN0_8 Mux input channel 0 of TIM module 2 QSPI2_SCLKD Slave SPI clock inputs CBS_TGI6 Trigger input P33.14 O0 General-purpose output GTM_TOUT143 O1 GTM muxed output —O 2 Reserved QSPI2_SCLK O3 Master SPI clock output —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_CC62 O7 T12 PWM channel 62 IOM_MON1_0 Monitor input 1 IOM_REF1_4 Reference input 1 CBS_TGO6 O Trigger output U14 P33.15 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM5_IN1_9 Mux input channel 1 of TIM module 5 GTM_TIM4_IN6_12 Mux input channel 6 of TIM module 4 GTM_TIM2_IN1_7 Mux input channel 1 of TIM module 2 CBS_TGI7 Trigger input P33.15 O0 General-purpose output GTM_TOUT144 O1 GTM muxed output —O 2 Reserved QSPI2_SLSO11 O3 Master slave select output —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_COUT62 O7 T12 PWM channel 62 IOM_MON1_5 Monitor input 1 IOM_REF1_1 Reference input 1 CBS_TGO7 O Trigger output Table 2-39 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 252 V 1.2, 2021-03 Table 2-40 Port 34 Functions Ball Symbol Ctrl. Buffer Type Function U11 P34.1 I SLOW / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM5_IN3_9 Mux input channel 3 of TIM module 5 GTM_TIM3_IN4_12 Mux input channel 4 of TIM module 3 GTM_TIM2_IN3_9 Mux input channel 3 of TIM module 2 EVADC_G10CH11 AI Analog input channel 11, group 10 P34.1 O0 General-purpose output GTM_TOUT146 O1 GTM muxed output ASCLIN4_ATX O2 Transmit output —O 3 Reserved CAN00_TXD O4 CAN transmit output node 0 IOM_MON2_5 Monitor input 2 IOM_REF2_5 Reference input 2 CAN20_TXD O5 CAN transmit output node 0 —O 6 Reserved CCU60_COUT63 O7 T13 PWM channel 63 IOM_MON1_6 Monitor input 1 IOM_REF1_0 Reference input 1 T12 P34.2 I SLOW / PU1 / VEVRSB / ES General-purpose input GTM_TIM5_IN4_9 Mux input channel 4 of TIM module 5 GTM_TIM3_IN5_13 Mux input channel 5 of TIM module 3 GTM_TIM2_IN4_8 Mux input channel 4 of TIM module 2 ASCLIN4_ARXB Receive input CAN00_RXDG CAN receive input node 0 CAN20_RXDC CAN receive input node 0 EVADC_G10CH10 AI Analog input channel 10, group 10 P34.2 O0 General-purpose output GTM_TOUT147 O1 GTM muxed output —O 2 Reserved —O 3 Reserved —O 4 Reserved —O 5 Reserved —O 6 Reserved CCU60_CC60 O7 T12 PWM channel 60 IOM_MON1_2 Monitor input 1 IOM_REF1_6 Reference input 1 OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 253 V 1.2, 2021-03 U12 P34.3 I SLOW / PU1 / VEVRSB / ES General-purpose input GTM_TIM5_IN5_10 Mux input channel 5 of TIM module 5 GTM_TIM3_IN6_13 Mux input channel 6 of TIM module 3 GTM_TIM2_IN5_9 Mux input channel 5 of TIM module 2 EVADC_G10CH9 AI Analog input channel 9, group 10 P34.3 O0 General-purpose output GTM_TOUT148 O1 GTM muxed output ASCLIN4_ASCLK O2 Shift clock output —O 3 Reserved QSPI2_SLSO10 O4 Master slave select output —O 5 Reserved —O 6 Reserved CCU60_COUT60 O7 T12 PWM channel 60 IOM_MON1_3 Monitor input 1 IOM_REF1_3 Reference input 1 T13 P34.4 I SLOW / PU1 / VEVRSB / ES General-purpose input GTM_TIM5_IN6_10 Mux input channel 6 of TIM module 5 GTM_TIM3_IN7_12 Mux input channel 7 of TIM module 3 GTM_TIM2_IN6_8 Mux input channel 6 of TIM module 2 QSPI2_MRSTD Master SPI data input EVADC_G10CH8 AI Analog input channel 8, group 10 P34.4 O0 General-purpose output GTM_TOUT149 O1 GTM muxed output ASCLIN4_ASLSO O2 Slave select signal output —O 3 Reserved QSPI2_MRST O4 Slave SPI data output IOM_MON2_2 Monitor input 2 IOM_REF2_2 Reference input 2 —O 5 Reserved —O 6 Reserved CCU60_CC61 O7 T12 PWM channel 61 IOM_MON1_1 Monitor input 1 IOM_REF1_5 Reference input 1 Table 2-40 Port 34 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 254 V 1.2, 2021-03 U13 P34.5 I FAST / PU1 / VEVRSB / ES General-purpose input GTM_TIM5_IN7_9 Mux input channel 7 of TIM module 5 GTM_TIM4_IN7_12 Mux input channel 7 of TIM module 4 GTM_TIM2_IN7_9 Mux input channel 7 of TIM module 2 QSPI2_MTSRD Slave SPI data input ASCLIN8_ARXE Receive input P34.5 O0 General-purpose output GTM_TOUT150 O1 GTM muxed output ASCLIN8_ATX O2 Transmit output —O 3 Reserved QSPI2_MTSR O4 Master SPI data output —O 5 Reserved —O 6 Reserved CCU60_COUT61 O7 T12 PWM channel 61 IOM_MON1_4 Monitor input 1 IOM_REF1_2 Reference input 1 Table 2-41 Analog Inputs Ball Symbol Ctrl. Buffer Type Function T10 AN0 I D / HighZ / VDDM Analog Input 0 EVADC_G0CH0 Analog input channel 0, group 0 EDSADC_EDS3PA Positive analog input channel 3, pin A U10 AN1 I D / HighZ / VDDM Analog Input 1 EVADC_G0CH1 Analog input channel 1, group 0 EDSADC_EDS3NA Negative analog input channel 3, pin A W9 AN2 I D / HighZ / VDDM Analog Input 2 EVADC_G0CH2 Analog input channel 2, group 0 EDSADC_EDS0PA Positive analog input channel 0, pin A U9 AN3 I D / HighZ / VDDM Analog Input 3 EVADC_G0CH3 Analog input channel 3, group 0 EDSADC_EDS0NA Negative analog input channel 0, pin A T9 AN4 I D / HighZ / VDDM Analog Input 4 EVADC_G11CH0 Analog input channel 0, group 11 EVADC_G0CH4 Analog input channel 4, group 0 Y9 AN5 I D / HighZ / VDDM Analog Input 5 EVADC_G11CH1 Analog input channel 1, group 11 EVADC_G0CH5 Analog input channel 5, group 0 Table 2-40 Port 34 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 255 V 1.2, 2021-03 T8 AN6 I D / HighZ / VDDM Analog Input 6 EVADC_G11CH2 Analog input channel 2, group 11 EVADC_G0CH6 Analog input channel 6, group 0 U8 AN7 I D / HighZ / VDDM Analog Input 7 EVADC_G11CH3 Analog input channel 3, group 11 EVADC_G0CH7 Analog input channel 7, group 0 W8 AN8 I D / HighZ / VDDM Analog Input 8 EVADC_G11CH4 Analog input channel 4, group 11 EVADC_G1CH0 Analog input channel 0, group 1 U7 AN9 I D / HighZ / VDDM Analog Input 9 EVADC_G11CH5 Analog input channel 5, group 11 EVADC_G1CH1 Analog input channel 1, group 1 Y8 AN10 I D / HighZ / VDDM Analog Input 10 EVADC_G11CH6 Analog input channel 6, group 11 EVADC_G1CH2 Analog input channel 2, group 1 W7 AN11 I D / HighZ / VDDM Analog Input 11 EVADC_G11CH7 Analog input channel 7, group 11 EVADC_G1CH3 Analog input channel 3, group 1 T7 AN12 I D / HighZ / VDDM Analog Input 12 EVADC_G1CH4 Analog input channel 4, group 1 EDSADC_EDS0PB Positive analog input channel 0, pin B W6 AN13 I D / HighZ / VDDM Analog Input 13 EVADC_G1CH5 Analog input channel 5, group 1 EDSADC_EDS0NB Negative analog input channel 0, pin B U6 AN14 I D / HighZ / VDDM Analog Input 14 EVADC_G1CH6 Analog input channel 6, group 1 EDSADC_EDS3PB Positive analog input channel 3, pin B T6 AN15 I D / HighZ / VDDM Analog Input 15 EVADC_G1CH7 Analog input channel 7, group 1 EDSADC_EDS3NB Negative analog input channel 3, pin N W5 AN16 I D / HighZ / VDDM Analog Input 16 EVADC_G2CH0 Analog input channel 0, group 2 EVADC_FC0CH0 Analog input FC channel 0 U5 AN17/P40.10 I S / HighZ / VDDM Analog Input 17 SENT_SENT10A Receive input channel 10 EVADC_G2CH1 Analog input channel 1, group 2 EVADC_FC1CH0 Analog input FC channel 1 Table 2-41 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 256 V 1.2, 2021-03 W4 AN18/P40.11 I S / HighZ / VDDM Analog Input 18 SENT_SENT11A Receive input channel 11 EVADC_G11CH8 Analog input channel 8, group 11 EVADC_G2CH2 Analog input channel 2, group 2 W3 AN19/P40.12 I S / HighZ / VDDM Analog Input 19 SENT_SENT12A Receive input channel 12 EVADC_G11CH9 Analog input channel 9, group 11 EVADC_G2CH3 Analog input channel 3, group 2 Y3 AN20 I D / HighZ / VDDM Analog Input 20 EVADC_G2CH4 Analog input channel 4, group 2 EDSADC_EDS2PA Positive analog input channel 2, pin A Y2 AN21 I D / HighZ / VDDM Analog Input 21 EVADC_G2CH5 Analog input channel 5, group 2 EDSADC_EDS2NA Negative analog input channel 2, pin A T5 AN22 I D / HighZ / VDDM Analog Input 22 EVADC_G2CH6 Analog input channel 6, group 2 R5 AN23 I D / HighZ / VDDM Analog Input 23 EVADC_G2CH7 Analog input channel 7, group 2 W2 AN24/P40.0 I S / HighZ / VDDM Analog Input 24 SENT_SENT0A Receive input channel 0 EVADC_G3CH0 Analog input channel 0, group 3 CCU60_CCPOS0D Hall capture input 0 EDSADC_EDS2PB Positive analog input channel 2, pin B W1 AN25/P40.1 I S / HighZ / VDDM Analog Input 25 SENT_SENT1A Receive input channel 1 EVADC_G3CH1 Analog input channel 1, group 3 CCU60_CCPOS1B Hall capture input 1 EDSADC_EDS2NB Negative analog input channel 2, pin B V2 AN26/P40.2 I S / HighZ / VDDM Analog Input 26 SENT_SENT2A Receive input channel 2 EVADC_G3CH2 Analog input channel 2, group 3 CCU60_CCPOS1D Hall capture input 1 EVADC_G11CH10 Analog input channel 10, group 11 V1 AN27/P40.3 I S / HighZ / VDDM Analog Input 27 SENT_SENT3A Receive input channel 3 EVADC_G3CH3 Analog input channel 3, group 3 CCU60_CCPOS2B Hall capture input 2 EVADC_G11CH11 Analog input channel 11, group 11 Table 2-41 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 257 V 1.2, 2021-03 U2 AN28/P40.13 I S / HighZ / VDDM Analog Input 28 SENT_SENT13A Receive input channel 13 EVADC_G3CH4 Analog input channel 4, group 3 EVADC_G4CH4 Analog input channel 4, group 4 U1 AN29/P40.14 I S / HighZ / VDDM Analog Input 29 SENT_SENT14A Receive input channel 14 EVADC_G3CH5 Analog input channel 5, group 3 EVADC_G4CH5 Analog input channel 5, group 4 T4 AN30 I D / HighZ / VDDM Analog Input 30 EVADC_G3CH6 Analog input channel 6, group 3 EVADC_G4CH6 Analog input channel 6, group 4 R4 AN31 I D / HighZ / VDDM Analog Input 31 EVADC_G3CH7 Analog input channel 7, group 3 EVADC_G4CH7 Analog input channel 7, group 4 P4 AN32/P40.4 I S / HighZ / VDDM Analog Input 32 SENT_SENT4A Receive input channel 4 EVADC_G8CH0 Analog input channel 0, group 8 CCU60_CCPOS2D Hall capture input 2 EVADC_G11CH12 Analog input channel 12, group 11 R1 AN33/P40.5 I S / HighZ / VDDM Analog Input 33 SENT_SENT5A Receive input channel 5 EVADC_G8CH1 Analog input channel 1, group 8 CCU61_CCPOS0D Hall capture input 0 EVADC_G11CH13 Analog input channel 13, group 11 P5 AN34 I D / HighZ / VDDM Analog Input 34 EVADC_G8CH2 Analog input channel 2, group 8 EVADC_G11CH14 Analog input channel 14, group 11 R2 AN35 I D / HighZ / VDDM Analog Input 35 EVADC_G8CH3 Analog input channel 3, group 8 EVADC_G11CH15 Analog input channel 15, group 11 N4 AN36/P40.6 I S / HighZ / VDDM Analog Input 36 SENT_SENT6A Receive input channel 6 EVADC_G8CH4 Analog input channel 4, group 8 CCU61_CCPOS1B Hall capture input 1 EDSADC_EDS1PA Positive analog input channel 1, pin A Table 2-41 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 258 V 1.2, 2021-03 P2 AN37/P40.7 I S / HighZ / VDDM Analog Input 37 SENT_SENT7A Receive input channel 7 EVADC_G8CH5 Analog input channel 5, group 8 CCU61_CCPOS1D Hall capture input 1 EDSADC_EDS1NA Negative analog input channel 1, pin A N5 AN38/P40.8 I S / HighZ / VDDM Analog Input 38 SENT_SENT8A Receive input channel 8 EVADC_G8CH6 Analog input channel 6, group 8 CCU61_CCPOS2B Hall capture input 2 EDSADC_EDS1PB Positive analog input channel 1, pin B P1 AN39/P40.9 I S / HighZ / VDDM Analog Input 39 SENT_SENT9A Receive input channel 9 EVADC_G8CH7 Analog input channel 7, group 8 CCU61_CCPOS2D Hall capture input 2 EDSADC_EDS1NB Negative analog input channel 1, pin B M5 AN40 I D / HighZ / VDDM Analog Input 40 EVADC_G8CH8 Analog input channel 8, group 8 EVADC_G4CH0 Analog input channel 0, group 4 M4 AN41 I D / HighZ / VDDM Analog Input 41 EVADC_G8CH9 Analog input channel 9, group 8 EVADC_G4CH1 Analog input channel 1, group 4 L5 AN42 I D / HighZ / VDDM Analog Input 42 EVADC_G8CH10 Analog input channel 10, group 8 EVADC_G4CH2 Analog input channel 2, group 4 L4 AN43 I D / HighZ / VDDM Analog Input 43 EVADC_G8CH11 Analog input channel 11, group 8 EVADC_G4CH3 Analog input channel 3, group 4 N1 AN44 I D / HighZ / VDDM Analog Input 44 EVADC_G8CH12 Analog input channel 12, group 8 EDSADC_EDS1PC Positive analog input channel 1, pin C N2 AN45 I D / HighZ / VDDM Analog Input 45 EVADC_G8CH13 Analog input channel 13, group 8 EDSADC_EDS1NC Negative analog input channel 1, pin C M1 AN46 I D / HighZ / VDDM Analog Input 46 EVADC_G8CH14 Analog input channel 14, group 8 EDSADC_EDS1PD Positive analog input channel 1, pin D Table 2-41 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 259 V 1.2, 2021-03 Note: Port Pins P32.0 and P32.1 are bidirectional pads and are having the following two functionalities implemented: 3. In case the pins are used as standard GPIOs the functions defined in the pin configuration tables of P32.0 and P32.1 are available. 4. In case the pins are used as pre-drivers for extern al MOSFETs (internal DCDC usecase) P32.0 and P32.1 act as analog IOs named VGATE1N and VGATE1P. M2 AN47 I D / HighZ / VDDM Analog Input 47 EVADC_G8CH15 Analog input channel 15, group 8 EDSADC_EDS1ND Negative analog input channel 1, pin D Table 2-42 System I/O Ball Symbol Ctrl. Buffer Type Function G16 ESR1 I/O FAST / PU1 / VEXT ESR1 Port Pin input - can be used to trigger a reset or an NMI ESR1: External System Request Reset 1. Default NMI function. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR1WKP I ESR1 pin input F16 ESR0 I/O FAST / OD / VEXT ESR0 Port Pin input - can be used to trigger a reset or an NMI ESR0: External System Request Reset 0. Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset. This is valid additionally after deactivation of PORST_N until the internal reset phase has finished. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin PMS_ESR0WKP I ESR0 pin input W17 VGATE1P O — DCDC P ch. MOSFET gate driver output P32.1 / External Pass Device gate control for EVRC Y17 VGATE1N O — DCDC N ch. MOSFET gate driver output P32.0 / SMPS mode: analog output. External Pass Device gate control for EVRC M20 XTAL1 I XTAL / VEXT XTAL pad1 XTAL1. Main Oscillator/PLL/Clock Generator Input. M19 XTAL2 O XTAL / VEXT XTAL pad2 XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT Table 2-41 Analog Inputs (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 260 V 1.2, 2021-03 L19 TRST I FAST / PU2 / VEXT JTAG Module Reset/Enable Input J16 TCK I FAST / PD2 / VEXT JTAG Module Clock Input DAP0 I DAP: DAP0 Clock Input K16 TMS I FAST / PD2 / VEXT JTAG Module State Machine Control Input DAP1 I/O DAP: DAP1 Data I/O G17 PORST I/O PORST / PD / VEXT PORST pin Power On Reset Input. Additional strong PD in case of power fail. Table 2-43 Supply Ball Symbol Ctrl. Buffer Type Function P8, P13, N7, N14, E15, H14, D16, G13, G8, H7 VDD I — Digital Core Power Supply (1.25V) A2, B3, V19, W20 VEXT I — External Power Supply (5V / 3.3V) D5 VFLEX I — Digital Power Supply for Flex Port Pads (5V / 3.3V) Y5 VDDM I — ADC Analog Power Supply (5V / 3.3V) B18, A19 VDDP3 I — Flash Power Supply (3.3V) B2, D4, E5, T16, U17, W19, Y20, E16, D17, B19, A20 VSS I — Digital Ground Y4 VSSM I — Analog Ground for VDDM Table 2-42 System I/O (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions BGA292 Package Variant Pin Configuration Data Sheet 261 V 1.2, 2021-03 P9, P12, N9, N10, N11, N12, M7, M8, M10, M11, M13, M14, L8, L9, L10, L11, L12, L13, K8, K9, K10, K11, K12, K13, J7, J8, J10, J11, J13, J14, H9, H10, H11, H12, G9, G10, G11, G12, L14, P10, P11, K7, L7 VSS I — Digital Ground L20 VSS I — Oscillator Ground, VSS(OSC) Y6 VAREF1 I — Positive Analog Reference Voltage 1 Y7 VAGND1 I — Negative Analog Reference Voltage 1 T1 VAREF2 I — Positive Analog Reference Voltage 2 T2 VAGND2 I — Negative Analog Reference Voltage 2 K14 NC I — Not connected. These pins are reserved for future extensions and shall not be connected externally A1, Y1, U4 NC1 I — Not connected. These pins are not connected on package level and will not be used for future extensions T11 VEVRSB I — Standby Power Supply (5V / 3.3V) for the Standby SRAM N19 VDD I — Digital Power Supply for Oscillator (1.25V), VDD(OSC) N20 VEXT I — Digital Power Supply for Oscillator (shall be supplied with same level as used for VEXT), VEXT(OSC) Table 2-43 Supply (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 262 V 1.2, 2021-03

2.3 Sequence of Pads in Pad Frame

Number Pad Name Pad Type X Y Comment 1E S R 1 FAST / PU1 / VEXT 263799 179145 ESR1 Port Pin input - can be used to trigger a reset or an NMI ESR1: External System Request Reset 1. Default NMI function. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin 2E S R 0 FAST / OD / VEXT 357795 179145 ESR0 Port Pin input - can be used to trigger a reset or an NMI ESR0: External System Request Reset 0. Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset. This is valid additionally after deactivation of PORST_N until the internal reset phase has finished. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. PMS_EVRWUP: EVR Wakepup Pin 3 P20.9 FAST / PU1 / VEXT / ES 409293 348147 General-purpose I/O 4 P20.14 FAST / PU1 / VEXT / ES 456291 179145 General-purpose I/O 5 P15.0 FAST / PU1 / VEXT / ES 503289 348147 General-purpose I/O 6 P15.2 FAST / PU1 / VEXT / ES 550287 179145 General-purpose I/O 7 P15.4 FAST / PU1 / VEXT / ES 597285 348147 General-purpose I/O OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 263 V 1.2, 2021-03 8 P15.1 FAST / PU1 / VEXT / ES 644283 179145 General-purpose I/O 9 P15.3 FAST / PU1 / VEXT / ES 691281 348147 General-purpose I/O 10 P14.0 FAST / PU1 / VEXT / ES2 738279 179145 General-purpose I/O

11 VDDP3 Vx 785277 348147 Supply Voltage

12 P15.10 FAST / PU1 / VEXT / ES6 832275 179145 General-purpose I/O 13 P15.11 FAST / PU1 / VEXT / ES6 926271 179145 General-purpose I/O

14 VDD Vx 973269 348147 Supply Voltage

15 VSS Vx 1048869 179145 Supply Voltage

16 P15.12 FAST / PU1 / VEXT / ES6 1124469 348147 General-purpose I/O 17 P15.6 FAST / PU1 / VEXT / ES 1171467 179145 General-purpose I/O 18 P15.13 FAST / PU1 / VEXT / ES6 1218465 348147 General-purpose I/O 19 P15.7 FAST / PU1 / VEXT / ES 1265463 179145 General-purpose I/O 20 P15.14 FAST / PU1 / VEXT / ES 1312461 348147 General-purpose I/O

21 VEXT Vx 1359459 179145 Supply Voltage

22 P15.15 FAST / PU1 / VEXT / ES 1406457 348147 General-purpose I/O

23 VSS Vx 1453455 179145 Supply Voltage

24 P14.4 SLOW / PU2 / VEXT / ES 1500453 348147 General-purpose I/O 25 P15.8 FAST / PU1 / VEXT / ES 1547451 179145 General-purpose I/O 26 P14.1 FAST / PU1 / VEXT / ES2 1594449 348147 General-purpose I/O 27 P14.3 SLOW / PU2 / VEXT / ES 1641447 179145 General-purpose I/O 28 P14.5 FAST / PU2 / VEXT / ES 1688445 348147 General-purpose I/O 29 P15.5 FAST / PU1 / VEXT / ES 1735443 179145 General-purpose I/O 30 P14.11 SLOW / PU1 / VEXT / ES 1782441 348147 General-purpose I/O

31 VSS Vx 1858041 179145 Supply Voltage

Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 264 V 1.2, 2021-03 32 P14.12 SLOW / PU1 / VEXT / ES 1933641 348147 General-purpose I/O

33 VDD Vx 2009241 179145 Supply Voltage

34 P14.13 FAST / PU1 / VEXT / ES 2084841 348147 General-purpose I/O 35 P14.7 SLOW / PU1 / VEXT / ES 2131839 179145 General-purpose I/O 36 P14.15 SLOW / PU1 / VEXT / ES 2178837 348147 General-purpose I/O 37 P14.6 FAST / PU1 / VEXT / ES 2225835 179145 General-purpose I/O

38 VEXT Vx 2272833 348147 Supply Voltage

39 P14.9 LVDS_RX / FAST / PU1 / VEXT / ES 2347884 179145 General-purpose I/O 40 P14.10 LVDS_RX / FAST / PU1 / VEXT / ES 2441880 179145 General-purpose I/O 41 P14.8 SLOW / PU1 / VEXT / ES 2516931 348147 General-purpose I/O 42 P14.2 SLOW / PU2 / VEXT / ES 2563929 179145 General-purpose I/O 43 P13.0 LVDS_TX / FAST / PU1 / VEXT / ES6 2675430 348147 General-purpose I/O 44 P13.1 LVDS_TX / FAST / PU1 / VEXT / ES6 2769426 348147 General-purpose I/O

45 VDD Vx 2880927 348147 Supply Voltage

46 VSS Vx 2936925 179145 Supply Voltage

47 P13.2 LVDS_TX / FAST / PU1 / VEXT / ES6 3048426 348147 General-purpose I/O 48 P13.3 LVDS_TX / FAST / PU1 / VEXT / ES6 3142422 348147 General-purpose I/O

49 VDD Vx 3253923 179145 Supply Voltage

50 P13.9 FAST / PU1 / VEXT / ES 3300921 348147 General-purpose I/O

51 VSS Vx 3347919 179145 Supply Voltage

52 P13.4 LVDS_TX / FAST / PU1 / VEXT / ES6 3459420 348147 General-purpose I/O Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 265 V 1.2, 2021-03 53 P13.5 LVDS_TX / FAST / PU1 / VEXT / ES6 3553416 348147 General-purpose I/O 54 P13.6 LVDS_TX / FAST / PU1 / VEXT / ES6 3729420 348147 General-purpose I/O 55 P13.7 LVDS_TX / FAST / PU1 / VEXT / ES6 3823416 348147 General-purpose I/O

56 VDD Vx 3934917 348147 Supply Voltage

57 VSS Vx 3981915 179145 Supply Voltage

58 P13.10 SLOW / PU1 / VEXT / ES 4085973 348147 General-purpose I/O

59 VSS Vx 4132971 179145 Supply Voltage

60 P13.12 SLOW / PU1 / VEXT / ES 4179969 348147 General-purpose I/O

61 VEXT Vx 4226967 179145 Supply Voltage

62 VDDP3 Vx 4408965 348147 Supply Voltage

63 P13.13 SLOW / PU1 / VEXT / ES 4455963 179145 General-purpose I/O

64 VDDP3 Vx 4502961 348147 Supply Voltage

65 P13.14 SLOW / PU1 / VEXT / ES 4549959 179145 General-purpose I/O

66 VDDP3 Vx 4596957 348147 Supply Voltage

67 P13.11 SLOW / PU1 / VEXT / ES 4643955 179145 General-purpose I/O 68 P13.15 SLOW / PU1 / VEXT / ES 4690953 348147 General-purpose I/O 69 P14.14 FAST / PU1 / VEXT / ES 4737951 179145 General-purpose I/O 70 P12.0 SLOW / PU1 / VFLEX / ES 4832019 179145 General-purpose I/O 71 P12.1 SLOW / PU1 / VFLEX / ES 4879017 348147 General-purpose I/O 72 P11.0 RFAST / PU1 / VFLEX / ES 4983021 348147 General-purpose I/O

73 VFLEX Vx 5030019 179145 Supply Voltage

74 P11.1 RFAST / PU1 / VFLEX / ES 5105223 348147 General-purpose I/O

75 VSS Vx 5152221 179145 Supply Voltage

76 P11.2 RFAST / PU1 / VFLEX / ES 5227425 348147 General-purpose I/O Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 266 V 1.2, 2021-03

77 VDD Vx 5274423 179145 Supply Voltage

78 P11.4 RFAST / PU1 / VFLEX / ES 5390127 348147 General-purpose I/O

79 VSS Vx 5477625 179145 Supply Voltage

80 P11.3 RFAST / PU1 / VFLEX / ES 5552829 348147 General-purpose I/O

81 VFLEX Vx 5599827 179145 Supply Voltage

82 P11.6 RFAST / PU1 / VFLEX / ES 5675031 348147 General-purpose I/O

83 VSS Vx 5722029 179145 Supply Voltage

84 P11.5 SLOW / RGMII_Input / PU1 / VFLEX / ES 5769027 348147 General-purpose I/O 85 P11.7 SLOW / RGMII_Input / PU1 / VFLEX / ES 5821407 179145 General-purpose I/O 86 P11.9 FAST / RGMII_Input / PU1 / VFLEX / ES 5872005 348147 General-purpose I/O

87 VFLEX Vx 5922603 179145 Supply Voltage

88 P11.8 SLOW / RGMII_Input / PU1 / VFLEX / ES 5969601 348147 General-purpose I/O 89 P11.10 FAST / RGMII_Input / PU1 / VFLEX / ES 6020199 179145 General-purpose I/O 90 P11.11 FAST / RGMII_Input / PU1 / VFLEX / ES 6070797 348147 General-purpose I/O

91 VSS Vx 6121395 179145 Supply Voltage

92 P11.12 FAST / RGMII_Input / PU1 / VFLEX / ES 6168393 348147 General-purpose I/O 93 P11.14 SLOW / PU1 / VFLEX / ES 6276357 348147 General-purpose I/O 94 P11.13 SLOW / PU1 / VFLEX / ES 6323355 179145 General-purpose I/O Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 267 V 1.2, 2021-03 95 P11.15 SLOW / PU1 / VFLEX / ES 6370353 348147 General-purpose I/O

96 VDD Vx 6444567 179145 Supply Voltage

97 VSS Vx 6538563 179145 Supply Voltage

98 P10.0 SLOW / PU1 / VEXT / ES 6614163 348147 General-purpose I/O

99 VDD Vx 6689763 179145 Supply Voltage

100 P10.3 FAST / PU1 / VEXT / ES 6765363 348147 General-purpose I/O

101 VSS Vx 6840963 179145 Supply Voltage

102 P10.1 FAST / PU1 / VEXT / ES 6916563 348147 General-purpose I/O

103 VEXT Vx 6972561 179145 Supply Voltage

104 P10.9 SLOW / PU1 / VEXT / ES 7089147 348147 General-purpose I/O

105 VSS Vx 7176645 179145 Supply Voltage

106 P10.11 SLOW / PU1 / VEXT / ES 7306641 179145 General-purpose I/O 107 P10.4 FAST / PU1 / VEXT / ES 7391295 263799 General-purpose I/O 108 P10.10 SLOW / PU1 / VEXT / ES 7391295 357795 General-purpose I/O 109 P10.15 SLOW / PU1 / VEXT / ES 7222293 451791 General-purpose I/O 110 P10.13 SLOW / PU1 / VEXT / ES 7391295 545787 General-purpose I/O 111 P10.2 FAST / PU1 / VEXT / ES 7222293 639783 General-purpose I/O 112 P10.14 SLOW / PU1 / VEXT / ES 7391295 733779 General-purpose I/O 113 P10.6 SLOW / PU2 / VEXT / ES 7222293 795888 General-purpose I/O 114 P10.5 SLOW / PU2 / VEXT / ES 7391295 842886 General-purpose I/O 115 P10.8 SLOW / PU1 / VEXT / ES 7391295 936882 General-purpose I/O 116 P10.7 SLOW / PU1 / VEXT / ES 7222293 983880 General-purpose I/O 117 P02.0 FAST / PU1 / VEXT / ES 7391295 1030878 General-purpose I/O 118 P02.2 FAST / PU1 / VEXT / ES 7222293 1077876 General-purpose I/O Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 268 V 1.2, 2021-03 119 P02.1 SLOW / PU1 / VEXT / ES 7391295 1124874 General-purpose I/O 120 P02.5 FAST / PU1 / VEXT / ES 7222293 1171872 General-purpose I/O 121 P02.3 SLOW / PU1 / VEXT / ES 7391295 1218870 General-purpose I/O 122 P02.13 SLOW / PU1 / VEXT / ES 7222293 1265868 General-purpose I/O 123 P02.11 SLOW / PU1 / VEXT / ES 7391295 1312866 General-purpose I/O 124 P02.12 SLOW / PU1 / VEXT / ES 7222293 1359864 General-purpose I/O 125 P02.4 FAST / PU1 / VEXT / ES 7391295 1406862 General-purpose I/O 126 P02.15 FAST / PU1 / VEXT / ES 7222293 1453860 General-purpose I/O

127 VDD Vx 7391295 1529460 Supply Voltage

128 VSS Vx 7391295 1623456 Supply Voltage

129 P02.14 SLOW / PU1 / VEXT / ES 7222293 1699056 General-purpose I/O 130 P02.6 FAST / PU1 / VEXT / ES 7391295 1746054 General-purpose I/O 131 P01.0 SLOW / PU1 / VEXT / ES 7222293 1793052 General-purpose I/O 132 P02.7 FAST / PU1 / VEXT / ES 7391295 1840050 General-purpose I/O 133 P01.1 SLOW / PU1 / VEXT / ES 7222293 1887048 General-purpose I/O 134 P02.8 SLOW / PU1 / VEXT / ES 7391295 1934046 General-purpose I/O 135 P01.2 SLOW / PU1 / VEXT / ES 7222293 1981044 General-purpose I/O 136 P02.9 SLOW / PU1 / VEXT / ES 7391295 2028042 General-purpose I/O 137 P01.8 SLOW / PU1 / VEXT / ES 7222293 2075040 General-purpose I/O

138 VEXT Vx 7391295 2122038 Supply Voltage

139 P01.9 SLOW / PU1 / VEXT / ES 7222293 2169036 General-purpose I/O

140 VSS Vx 7391295 2216034 Supply Voltage

141 P01.11 SLOW / PU1 / VEXT / ES 7222293 2263032 General-purpose I/O Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 269 V 1.2, 2021-03 142 P02.10 SLOW / PU1 / VEXT / ES 7391295 2310030 General-purpose I/O 143 P01.10 SLOW / PU1 / VEXT / ES 7222293 2357028 General-purpose I/O

144 VSS Vx 7391295 2432628 Supply Voltage

145 VDD Vx 7391295 2526624 Supply Voltage

146 P00.0 FAST / PU1 / VEXT / ES 7391295 2620620 General-purpose I/O 147 P01.13 FAST / PU1 / VEXT / ES 7222293 2667618 General-purpose I/O 148 P01.4 SLOW / PU1 / VEXT / ES 7391295 2714616 General-purpose I/O 149 P01.12 FAST / PU1 / VEXT / ES 7222293 2761614 General-purpose I/O 150 P01.3 SLOW / PU1 / VEXT / ES 7391295 2808612 General-purpose I/O 151 P01.15 SLOW / PU1 / VEXT / ES 7222293 2855610 General-purpose I/O 152 P01.6 FAST / PU1 / VEXT / ES 7391295 2902608 General-purpose I/O 153 P01.14 FAST / PU1 / VEXT / ES 7222293 2949606 General-purpose I/O 154 P01.5 SLOW / PU1 / VEXT / ES 7391295 2996604 General-purpose I/O 155 P00.15 FAST / PU1 / VEXT / ES 7222293 3043602 General-purpose I/O 156 P01.7 FAST / PU1 / VEXT / ES 7391295 3090600 General-purpose I/O 157 P00.13 FAST / PU1 / VEXT / ES 7222293 3137598 General-purpose I/O

158 RESERVED Vx 7391295 3184596 PBIST_OFFMust be bonded

159 RESERVED Vx 7391295 3278592 OTPMust be bonded to VSS

160 P00.14 SLOW / PU1 / VEXT / ES 7222293 3325590 General-purpose I/O

161 VSS Vx 7391295 3401190 Supply Voltage

162 VDD Vx 7391295 3495186 Supply Voltage

164 P00.1 SLOW / PU1 / VEXT / ES 7222293 3572226 General-purpose I/O 165 P00.2 SLOW / PU1 / VEXT / ES1 7391295 3619224 General-purpose I/O Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 270 V 1.2, 2021-03 166 P00.3 SLOW / PU1 / VEXT / ES1 7222293 3666222 General-purpose I/O 167 P00.4 SLOW / PU1 / VEXT / ES1 7391295 3713220 General-purpose I/O 168 P00.5 SLOW / PU1 / VEXT / ES1 7222293 3760218 General-purpose I/O

169 VSS Vx 7391295 3807216 Supply Voltage

170 P00.6 SLOW / PU1 / VEXT / ES1 7222293 3854214 General-purpose I/O

171 VEXT Vx 7391295 3901212 Supply Voltage

172 P00.7 SLOW / PU1 / VEXT / ES1 7222293 3948210 General-purpose I/O 173 P00.8 SLOW / PU1 / VEXT / ES1 7391295 3995208 General-purpose I/O 174 P00.9 SLOW / PU1 / VEXT / ES1 7222293 4042206 General-purpose I/O 175 P00.10 SLOW / PU1 / VEXT / ES1 7391295 4089204 General-purpose I/O 176 P00.11 SLOW / PU1 / VEXT / ES1 7222293 4136202 General-purpose I/O 177 P00.12 SLOW / PU1 / VEXT / ES1 7391295 4183200 General-purpose I/O

179 AN47 D / HighZ /

7222293 4257414 Analog Input 47

180 AN46 D / HighZ /

7391295 4304412 Analog Input 46

181 AN45 D / HighZ /

7222293 4351410 Analog Input 45

182 AN44 D / HighZ /

7391295 4398408 Analog Input 44

183 VDDM Vx 7222293 4445406 Supply Voltage

184 VSSM Vx 7391295 4492404 Supply Voltage

185 VAREF5 Vx 7222293 4539402 Supply Voltage

186 VAREF4 Vx 7391295 4586400 Supply Voltage

187 VAGND5 Vx 7222293 4633398 Supply Voltage

188 VAGND4 Vx 7391295 4680396 Supply Voltage

189 AN43 D / HighZ /

7222293 4727394 Analog Input 43

190 AN42 D / HighZ /

7391295 4774392 Analog Input 42

191 AN41 D / HighZ /

7222293 4821390 Analog Input 41 Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 271 V 1.2, 2021-03

192 VSSM Vx 7391295 4868388 Supply Voltage

193 VDDM Vx 7222293 4915386 Supply Voltage

194 AN40 D / HighZ /

7391295 4962384 Analog Input 40 195 AN39/P40.9 S / HighZ / VDDM 7222293 5009382 Analog Input 39

196 VSSM Vx 7391295 5056380 Supply Voltage

197 AN38/P40.8 S / HighZ / VDDM 7222293 5103378 Analog Input 38

198 VDDM Vx 7391295 5150376 Supply Voltage

199 AN37/P40.7 S / HighZ / VDDM 7222293 5197374 Analog Input 37 200 AN36/P40.6 S / HighZ / VDDM 7391295 5244372 Analog Input 36

201 AN35 D / HighZ /

7222293 5291370 Analog Input 35

202 AN34 D / HighZ /

7391295 5338368 Analog Input 34 203 AN33/P40.5 S / HighZ / VDDM 7222293 5385366 Analog Input 33 204 AN32/P40.4 S / HighZ / VDDM 7391295 5432364 Analog Input 32

205 VAREF3 Vx 7222293 5479362 Supply Voltage

206 VAREF2 Vx 7391295 5526360 Supply Voltage

207 VAGND3 Vx 7222293 5573358 Supply Voltage

208 VAGND2 Vx 7391295 5620356 Supply Voltage

209 AN71/P41.3 S / HighZ / VDDM 7222293 5667354 Analog Input 71 210 AN70/P41.2 S / HighZ / VDDM 7391295 5714352 Analog Input 70 211 AN69/P41.1 S / HighZ / VDDM 7222293 5761350 Analog Input 69 212 AN68/P41.0 S / HighZ / VDDM 7391295 5808348 Analog Input 68 213 AN67/P40.15 S / HighZ / VDDM 7222293 5855346 Analog Input 67

214 AN66 D / HighZ /

7391295 5902344 Analog Input 66

215 AN65 D / HighZ /

7222293 5949342 Analog Input 65 216 AN64/P41.8 S / HighZ / VDDM 7391295 5996340 Analog Input 64 Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 272 V 1.2, 2021-03

217 VDDM Vx 7222293 6043338 Supply Voltage

218 VSSM Vx 7391295 6090336 Supply Voltage

219 AN63/P41.7 S / HighZ / VDDM 7222293 6137334 Analog Input 63 220 AN62/P41.6 S / HighZ / VDDM 7391295 6184332 Analog Input 62

221 AN61 D / HighZ /

7222293 6231330 Analog Input 61

222 AN60 D / HighZ /

7391295 6278328 Analog Input 60

223 AN59 D / HighZ /

7222293 6325326 Analog Input 59

224 AN58 D / HighZ /

7391295 6372324 Analog Input 58

225 AN57 D / HighZ /

7222293 6419322 Analog Input 57

226 AN56 D / HighZ /

7391295 6466320 Analog Input 56 227 AN55/P41.5 S / HighZ / VDDM 7222293 6513318 Analog Input 55 228 AN54/P41.4 S / HighZ / VDDM 7391295 6560316 Analog Input 54

229 AN53 D / HighZ /

7222293 6607314 Analog Input 53

230 AN52 D / HighZ /

7391295 6654312 Analog Input 52

231 AN51 D / HighZ /

7222293 6701310 Analog Input 51

232 AN50 D / HighZ /

7391295 6748308 Analog Input 50

233 AN49 D / HighZ /

7222293 6795306 Analog Input 49

234 AN48 D / HighZ /

7391295 6842304 Analog Input 48

235 AN31 D / HighZ /

7391295 6936300 Analog Input 31

236 AN30 D / HighZ /

7302141 7058295 Analog Input 30 237 AN29/P40.14 S / HighZ / VDDM 7208145 7058295 Analog Input 29 238 AN28/P40.13 S / HighZ / VDDM 7161147 6889293 Analog Input 28 Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 273 V 1.2, 2021-03 239 AN27/P40.3 S / HighZ / VDDM 7114149 7058295 Analog Input 27 240 AN26/P40.2 S / HighZ / VDDM 7067151 6889293 Analog Input 26 241 AN25/P40.1 S / HighZ / VDDM 7020153 7058295 Analog Input 25 242 AN24/P40.0 S / HighZ / VDDM 6973155 6889293 Analog Input 24

243 AN23 D / HighZ /

6926157 7058295 Analog Input 23

244 AN22 D / HighZ /

6879159 6889293 Analog Input 22

245 AN21 D / HighZ /

6832161 7058295 Analog Input 21

246 AN20 D / HighZ /

6785163 6889293 Analog Input 20 247 AN19/P40.12 S / HighZ / VDDM 6738165 7058295 Analog Input 19 248 AN18/P40.11 S / HighZ / VDDM 6691167 6889293 Analog Input 18 249 AN17/P40.10 S / HighZ / VDDM 6644169 7058295 Analog Input 17

250 AN16 D / HighZ /

6597171 6889293 Analog Input 16

251 AN15 D / HighZ /

6550173 7058295 Analog Input 15

252 VAGND1 Vx 6503175 6889293 Supply Voltage

253 VAGND0 Vx 6456177 7058295 Supply Voltage

254 VAREF1 Vx 6409179 6889293 Supply Voltage

255 VAREF0 Vx 6362181 7058295 Supply Voltage

256 AN14 D / HighZ /

6315183 6889293 Analog Input 14

257 AN13 D / HighZ /

6268185 7058295 Analog Input 13

258 VDDM Vx 6221187 6889293 Supply Voltage

259 VSSM Vx 6174189 7058295 Supply Voltage

260 AN12 D / HighZ /

6127191 6889293 Analog Input 12

261 VSSM Vx 6080193 7058295 Supply Voltage

262 VDDM Vx 6033195 6889293 Supply Voltage

263 AN11 D / HighZ /

5986197 7058295 Analog Input 11 Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 274 V 1.2, 2021-03

264 AN10 D / HighZ /

5939199 6889293 Analog Input 10

265 AN9 D / HighZ /

5892201 7058295 Analog Input 9

266 AN8 D / HighZ /

5845203 6889293 Analog Input 8

267 AN7 D / HighZ /

5798205 7058295 Analog Input 7

268 AN6 D / HighZ /

5751207 6889293 Analog Input 6

269 AN5 D / HighZ /

5704209 7058295 Analog Input 5

270 AN4 D / HighZ /

5657211 6889293 Analog Input 4

271 AN3 D / HighZ /

5610213 7058295 Analog Input 3

272 AN2 D / HighZ /

5563215 6889293 Analog Input 2

273 AN1 D / HighZ /

5516217 7058295 Analog Input 1

274 AN0 D / HighZ /

5469219 6889293 Analog Input 0

276 VSS Vx 5386005 7058295 Supply Voltage

277 VDD Vx 5310405 6889293 Supply Voltage

278 VDD Vx 5234805 7058295 Supply Voltage

279 VSS Vx 5140809 7058295 Supply Voltage

280 VEXT Vx 4961709 6889293 Supply Voltage

281 P32.1 SLOW / PU1 / VEXT / ES 4914711 7058295 General-purpose I/O 282 VGATE1P Vx 4867713 6889293 DCDC P ch. MOSFET gate driver output

283 VSS Vx 4802715 7058295 Supply Voltage

284 VGATE1N Vx 4737717 6889293 DCDC N ch. MOSFET gate driver output 285 P32.0 SLOW / PU1 / VEXT / ES 4690719 7058295 General-purpose I/O

286 VEVRSB Vx 4607505 6889293 Supply Voltage

287 VEVRSB Vx 4560507 7058295 Supply Voltage

288 P33.1 SLOW / PU1 / VEVRSB / ES5 4513509 6889293 General-purpose I/O

289 VSS Vx 4466511 7058295 Supply Voltage

Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 275 V 1.2, 2021-03

290 VSS — 4354515 7058295 Supply Voltage

291 VDD — 4307517 6889293 Supply Voltage

292 P33.0 SLOW / PU1 / VEVRSB / ES5 4260519 7058295 General-purpose I/O 293 P33.3 SLOW / PU1 / VEVRSB / ES5 4213521 6889293 General-purpose I/O 294 P33.2 SLOW / PU1 / VEVRSB / ES5 4166523 7058295 General-purpose I/O 295 P33.5 SLOW / PU1 / VEVRSB / ES5 4119525 6889293 General-purpose I/O

296 VSS Vx 4016925 7058295 Supply Voltage

297 VDD Vx 3969927 6889293 Supply Voltage

298 P34.1 SLOW / PU1 / VEVRSB / ES5 3922929 7058295 General-purpose I/O 299 P33.4 SLOW / PU1 / VEVRSB / ES5 3875931 6889293 General-purpose I/O 300 P34.3 SLOW / PU1 / VEVRSB / ES 3828933 7058295 General-purpose I/O 301 P33.7 SLOW / PU1 / VEVRSB / ES5 3781935 6889293 General-purpose I/O 302 P34.2 SLOW / PU1 / VEVRSB / ES 3734937 7058295 General-purpose I/O 303 P33.6 SLOW / PU1 / VEVRSB / ES5 3687939 6889293 General-purpose I/O 304 P34.5 FAST / PU1 / VEVRSB / ES 3640941 7058295 General-purpose I/O 305 P33.9 SLOW / PU1 / VEVRSB / ES5 3593943 6889293 General-purpose I/O

306 VEVRSB Vx 3546945 7058295 Supply Voltage

307 P33.8 FAST / HighZ / VEVRSB 3499947 6889293 General-purpose I/O 308 P34.4 SLOW / PU1 / VEVRSB / ES 3452949 7058295 General-purpose I/O Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 276 V 1.2, 2021-03 309 P33.11 FAST / PU1 / VEVRSB / ES5 3405951 6889293 General-purpose I/O

310 VSS Vx 3303153 7058295 Supply Voltage

311 VDD Vx 3256155 6889293 Supply Voltage

312 VSS Vx 3209157 7058295 Supply Voltage

313 P33.10 FAST / PU1 / VEVRSB / ES5 3162159 6889293 General-purpose I/O 314 P33.15 SLOW / PU1 / VEVRSB / ES5 3115161 7058295 General-purpose I/O 315 P33.13 FAST / PU1 / VEVRSB / ES5 3068163 6889293 General-purpose I/O 316 P33.14 FAST / PU1 / VEVRSB / ES5 3021165 7058295 General-purpose I/O 317 P33.12 FAST / PU1 / VEVRSB / ES5 2974167 6889293 General-purpose I/O

318 VDD — 2890953 7058295 Supply Voltage

319 VSS — 2796957 7058295 Supply Voltage

320 P32.2 SLOW / PU1 / VEXT / ES 2721357 6889293 General-purpose I/O 321 P32.5 SLOW / PU1 / VEXT / ES 2674359 7058295 General-purpose I/O 322 P32.4 FAST / PU1 / VEXT / ES 2627361 6889293 General-purpose I/O

323 VSS Vx 2580363 7058295 Supply Voltage

324 VEXT Vx 2533365 6889293 Supply Voltage

325 P32.3 SLOW / PU1 / VEXT / ES 2486367 7058295 General-purpose I/O 326 P32.7 SLOW / PU1 / VEXT / ES 2439369 6889293 General-purpose I/O

327 VSS Vx 2363769 7058295 Supply Voltage

328 P32.6 SLOW / PU1 / VEXT / ES 2288169 6889293 General-purpose I/O

329 VDD Vx 2212569 7058295 Supply Voltage

330 P31.1 FAST / PU1 / VEXT / ES 2136969 6889293 General-purpose I/O 331 P31.0 FAST / PU1 / VEXT / ES 2089971 7058295 General-purpose I/O Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 277 V 1.2, 2021-03 332 P31.3 FAST / PU1 / VEXT / ES 2042973 6889293 General-purpose I/O 333 P31.2 FAST / PU1 / VEXT / ES 1995975 7058295 General-purpose I/O 334 P31.4 FAST / PU1 / VEXT / ES 1948977 6889293 General-purpose I/O 335 P31.5 FAST / PU1 / VEXT / ES 1901979 7058295 General-purpose I/O 336 P31.6 FAST / PU1 / VEXT / ES 1854981 6889293 General-purpose I/O 337 P31.7 FAST / PU1 / VEXT / ES 1807983 7058295 General-purpose I/O 338 P31.8 FAST / PU1 / VEXT / ES 1760985 6889293 General-purpose I/O 339 P31.10 FAST / PU1 / VEXT / ES 1713987 7058295 General-purpose I/O 340 P31.9 FAST / PU1 / VEXT / ES 1666989 6889293 General-purpose I/O 341 P31.12 FAST / PU1 / VEXT / ES 1619991 7058295 General-purpose I/O 342 P31.11 FAST / PU1 / VEXT / ES 1572993 6889293 General-purpose I/O 343 P31.14 FAST / PU1 / VEXT / ES 1525995 7058295 General-purpose I/O 344 P31.13 FAST / PU1 / VEXT / ES 1478997 6889293 General-purpose I/O

345 VDD Vx 1403397 7058295 Supply Voltage

346 VSS Vx 1309401 7058295 Supply Voltage

347 P31.15 FAST / PU1 / VEXT / ES 1233801 6889293 General-purpose I/O 348 P30.2 FAST / PU1 / VEXT / ES 1186803 7058295 General-purpose I/O 349 P30.0 FAST / PU1 / VEXT / ES 1139805 6889293 General-purpose I/O

350 VSS Vx 1092807 7058295 Supply Voltage

351 P30.1 FAST / PU1 / VEXT / ES 1045809 6889293 General-purpose I/O

352 VEXT Vx 998811 7058295 Supply Voltage

353 P30.3 FAST / PU1 / VEXT / ES 951813 6889293 General-purpose I/O 354 P30.5 FAST / PU1 / VEXT / ES 904815 7058295 General-purpose I/O Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 278 V 1.2, 2021-03 355 P30.4 FAST / PU1 / VEXT / ES 857817 6889293 General-purpose I/O 356 P30.8 FAST / PU1 / VEXT / ES 810819 7058295 General-purpose I/O

357 VDD Vx 763821 6889293 Supply Voltage

358 VSS Vx 716823 7058295 Supply Voltage

359 VDD Vx 614223 6889293 Supply Voltage

360 VSS Vx 538623 7058295 Supply Voltage

361 P30.6 FAST / PU1 / VEXT / ES 463023 6889293 General-purpose I/O 362 P30.9 FAST / PU1 / VEXT / ES 357795 7058295 General-purpose I/O 363 P30.7 FAST / PU1 / VEXT / ES 263799 7058295 General-purpose I/O 369 P30.10 FAST / PU1 / VEXT / ES 179145 6973641 General-purpose I/O 370 P30.11 FAST / PU1 / VEXT / ES 179145 6879645 General-purpose I/O 371 P30.14 FAST / PU1 / VEXT / ES 348147 6828147 General-purpose I/O 372 P30.15 FAST / PU1 / VEXT / ES 179145 6781149 General-purpose I/O 373 P30.13 FAST / PU1 / VEXT / ES 348147 6734151 General-purpose I/O 374 P30.12 FAST / PU1 / VEXT / ES 179145 6687153 General-purpose I/O 375 P26.0 SLOW / PU1 / VEXT / ES 348147 6640155 General-purpose I/O 376 P25.0 FAST / PU1 / VEXT / ES 179145 6593157 General-purpose I/O 377 P23.0 SLOW / PU1 / VEXT / ES 348147 6546159 General-purpose I/O 378 P23.1 FAST / PU1 / VEXT / ES 179145 6499161 General-purpose I/O 379 P23.2 SLOW / PU1 / VEXT / ES 348147 6443163 General-purpose I/O 380 P25.2 FAST / PU1 / VEXT / ES 179145 6396165 General-purpose I/O 381 P23.3 SLOW / PU1 / VEXT / ES 348147 6349167 General-purpose I/O 382 P25.1 FAST / PU1 / VEXT / ES 179145 6302169 General-purpose I/O Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 279 V 1.2, 2021-03

383 VEXT Vx 348147 6255171 Supply Voltage

384 P25.4 FAST / PU1 / VEXT / ES 179145 6208173 General-purpose I/O

385 VSS Vx 348147 6161175 Supply Voltage

386 P23.5 FAST / PU1 / VEXT / ES 179145 6114177 General-purpose I/O 387 P23.6 SLOW / PU1 / VEXT / ES 348147 6067179 General-purpose I/O 388 P23.7 SLOW / PU1 / VEXT / ES 179145 6020181 General-purpose I/O 389 P25.3 FAST / PU1 / VEXT / ES 348147 5973183 General-purpose I/O 390 P22.4 SLOW / PU1 / VEXT / ES 179145 5926185 General-purpose I/O 391 P25.7 FAST / PU1 / VEXT / ES 348147 5879187 General-purpose I/O 392 P25.5 FAST / PU1 / VEXT / ES 179145 5832189 General-purpose I/O 393 P25.8 FAST / PU1 / VEXT / ES 348147 5785191 General-purpose I/O 394 P25.9 FAST / PU1 / VEXT / ES 179145 5738193 General-purpose I/O 395 P25.10 FAST / PU1 / VEXT / ES 348147 5691195 General-purpose I/O 396 P22.5 SLOW / PU1 / VEXT / ES 179145 5644197 General-purpose I/O 397 P25.11 FAST / PU1 / VEXT / ES 348147 5588199 General-purpose I/O

398 VSS Vx 179145 5512599 Supply Voltage

399 VDD Vx 348147 5436999 Supply Voltage

400 P25.12 FAST / PU1 / VEXT / ES 179145 5390001 General-purpose I/O 401 P23.4 FAST / PU1 / VEXT / ES 348147 5343003 General-purpose I/O 402 P25.14 FAST / PU1 / VEXT / ES 179145 5296005 General-purpose I/O 403 P25.13 FAST / PU1 / VEXT / ES 348147 5249007 General-purpose I/O 404 P25.15 FAST / PU1 / VEXT / ES 179145 5202009 General-purpose I/O 405 P25.6 FAST / PU1 / VEXT / ES 348147 5155011 General-purpose I/O Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 280 V 1.2, 2021-03 406 P24.1 FAST / PU1 / VEXT / ES 179145 5108013 General-purpose I/O 407 P24.0 FAST / PU1 / VEXT / ES 348147 5061015 General-purpose I/O 408 P24.3 FAST / PU1 / VEXT / ES 179145 5014017 General-purpose I/O 409 P24.2 FAST / PU1 / VEXT / ES 348147 4967019 General-purpose I/O 410 P24.5 FAST / PU1 / VEXT / ES 179145 4920021 General-purpose I/O 411 P24.4 FAST / PU1 / VEXT / ES 348147 4873023 General-purpose I/O

412 VEXT Vx 179145 4826025 Supply Voltage

413 VSS Vx 348147 4779027 Supply Voltage

414 P22.7 SLOW / PU1 / VEXT / ES 179145 4732029 General-purpose I/O 415 P24.9 FAST / PU1 / VEXT / ES 348147 4685031 General-purpose I/O 416 P22.6 SLOW / PU1 / VEXT / ES 179145 4638033 General-purpose I/O 417 P24.8 FAST / PU1 / VEXT / ES 348147 4591035 General-purpose I/O 418 P22.8 SLOW / PU1 / VEXT / ES 179145 4544037 General-purpose I/O 419 P22.2 LVDS_TX / FAST / PU1 / VEXT / ES6 348147 4432536 General-purpose I/O 420 P22.3 LVDS_TX / FAST / PU1 / VEXT / ES6 348147 4338540 General-purpose I/O

421 VDD Vx 179145 4227039 Supply Voltage

422 P22.0 LVDS_TX / FAST / PU1 / VEXT / ES6 348147 4115538 General-purpose I/O 423 P22.1 LVDS_TX / FAST / PU1 / VEXT / ES6 348147 4021542 General-purpose I/O

424 VSS Vx 179145 3910041 Supply Voltage

425 P24.6 FAST / PU1 / VEXT / ES 348147 3834441 General-purpose I/O 426 P24.7 FAST / PU1 / VEXT / ES 179145 3787443 General-purpose I/O Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 281 V 1.2, 2021-03 427 P24.11 FAST / PU1 / VEXT / ES 348147 3740445 General-purpose I/O

428 VSS Vx 179145 3664845 Supply Voltage

429 VDD Vx 348147 3570849 Supply Voltage

430 P24.10 FAST / PU1 / VEXT / ES 179145 3495249 General-purpose I/O

432 VDD Vx 348147 3406041 Supply Voltage

433 VSS Vx 179145 3359043 Supply Voltage

434 XTAL1 XTAL / VEXT 1 79145 3199392 XTAL pad1

XTAL1. Main Oscillator/PLL/Clock Generator Input.

435 XTAL2 XTAL / VEXT 1 79145 3105396 XTAL pad2

XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT

436 VSS — 179145 2945745 Supply Voltage

437 VEXT Vx 348147 2898747 Supply Voltage

439 P24.13 FAST / PU1 / VEXT / ES 348147 2764233 General-purpose I/O 440 P22.11 SLOW / PU1 / VEXT / ES 179145 2717235 General-purpose I/O 441 P24.12 FAST / PU1 / VEXT / ES 348147 2670237 General-purpose I/O 442 P22.10 SLOW / PU1 / VEXT / ES 179145 2623239 General-purpose I/O 443 P24.15 FAST / PU1 / VEXT / ES 348147 2576241 General-purpose I/O 444 P22.9 SLOW / PU1 / VEXT / ES 179145 2529243 General-purpose I/O 445 P24.14 FAST / PU1 / VEXT / ES 348147 2482245 General-purpose I/O

446 TRST FAST / PU2 /

179145 2435247 JTAG Module Reset/Enable Input 447 P21.0 LVDS_RX / FAST / PU1 / VEXT / ES 348147 2360196 General-purpose I/O 448 P21.1 LVDS_RX / FAST / PU1 / VEXT / ES 348147 2266200 General-purpose I/O

449 VDD Vx 179145 2191149 Supply Voltage

Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 282 V 1.2, 2021-03 450 P21.2 LVDS_RX / FAST / PU1 / VEXT / ES 348147 2116098 General-purpose I/O 451 P21.3 LVDS_RX / FAST / PU1 / VEXT / ES 348147 2022102 General-purpose I/O

452 VSS Vx 179145 1947051 Supply Voltage

453 P21.4 LVDS_TX / FAST / PU1 / VEXT / ES6 348147 1835550 General-purpose I/O 454 P21.5 LVDS_TX / FAST / PU1 / VEXT / ES6 348147 1741554 General-purpose I/O

455 VDD Vx 348147 1630053 Supply Voltage

456 VSS Vx 179145 1554453 Supply Voltage

457 VSS Vx 348147 1460457 Supply Voltage

458 VEXT Vx 179145 1413459 Supply Voltage

459 P20.0 FAST / PU1 / VEXT / ES 348147 1366461 General-purpose I/O

460 TCK FAST / PD2 /

179145 1319463 JTAG Module Clock Input 461 P20.2 S / PU / VEXT 348147 1272465 General-purpose I/O This pin is latched at power on reset release to enter test mode.

462 TMS FAST / PD2 /

179145 1225467 JTAG Module State Machine Control Input 463 P20.3 SLOW / PU1 / VEXT / ES 348147 1178469 General-purpose I/O 464 P21.7/TDO FAST / PU2 / VEXT / ES4 179145 1131471 General-purpose I/O 465 P20.1 SLOW / PU1 / VEXT / ES 348147 1084473 General-purpose I/O

466 VEXT Vx 179145 1037475 Supply Voltage

467 P20.8 FAST / PU1 / VEXT / ES 348147 990477 General-purpose I/O

468 VSS Vx 179145 943479 Supply Voltage

469 P20.7 FAST / PU1 / VEXT / ES 348147 896481 General-purpose I/O

470 VDD Vx 179145 820881 Supply Voltage

471 P20.11 FAST / PU1 / VEXT / ES 348147 745281 General-purpose I/O Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Sequence of Pads in Pad Frame Data Sheet 283 V 1.2, 2021-03 Whenever in table of section 3 ’Electrical Specification’ the term ‘neighbor pads’ is used, the detailed definition is provided by Figure 2-44. This statement is also valid for next/nearest neighbor pads. In order to find out who is affecting operation on a target pad (interfering) a number of active close-neighbor pads (ACNP) has to be defined. Finding close-neighbor pads. The Pad Ring has four edges: bottom, left, top, right. Each edge is limited, i.e. it has two ends. Each pad has two direct (first) neighbors unless it is located at the end of the edge. In that case it only has one neighbor. Similarly, each pad has two indirect (second) neighbo rs unless it or its first neighbor is located at the end of the edge. These first and second neighbors we will colle ctively call Close-Neighbor pads. Therefore each pad has 2 to 4 close-neighbor pads. Finding close-neighbors can be done with the following sequence: 1.) Choose a target pad and lookup its “X” and “Y” coordinates in table Figure 2-44. 2.) Find first and second neighbors by calculating “X” and “Y” distance from the selected pad. Figure 2-44 is sorted by “Y” coordinate, which might help locate the 4 close-neighbor candidates (if the pad is near the edge, it might end up with less than 4 close-neighbors). Defining active pads: Pad is active if it is currently in use and if it doesn’t have “Vxx” in the name. Figuring out number of active close-neighbor pads follow next rules: - If the first neighbor is active, then we count it and also ch eck if second neighbor (on the same side of selected pad) is active. - If the first neighbor is not active, then we do not check the second on the same side. 472 P21.6/TDI FAST / PD / PU2 / VEXT / ES3 179145 698283 General-purpose I/O PD during Reset and in DAP/DAPE or JTAG mode. After Reset release and when not in DAP/DAPE or JTAG mode: PU. In Standby mode: HighZ. 473 P20.10 FAST / PU1 / VEXT / ES 348147 651285 General-purpose I/O

474 VSS Vx 179145 575685 Supply Voltage

475 P20.13 FAST / PU1 / VEXT / ES 348147 500085 General-purpose I/O

476 PORST PORST / PD /

Power On Reset Input. Additional strong PD in case of power fail. 477 P20.12 FAST / PU1 / VEXT / ES 179145 357795 General-purpose I/O 478 P20.6 SLOW / PU1 / VEXT / ES 179145 263799 General-purpose I/O Table 2-44 Pad List (cont’d) Number Pad Name Pad Type X Y Comment OPEN MARKET VERSION

Pin Definition and Functions Legend Data Sheet 284 V 1.2, 2021-03

2.4 Legend

Column “Ctrl.”: I = Input (for GPIO port lines with IOCR bit field Selection PCx = 0XXXB) O = Output (for GPIO port lines the ´O´ represents in most cases the port HWOUT function) O0 = Output with IOCR bit field selection PCx = 1X000B O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1) O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2) O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3) O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4) O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5) O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6) O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7) Column “Buffer Type”: RFAST = Pad class RFAST (5V/3.3V) FAST = Pad class FAST (5V/3.3V) SLOW = Pad class SLOW (5V/3.3V) LVDS_TX = Pad class LVDS Transmit LVDS_RX = Pad class LVDS Receive S = Pad class S (Analog Input overlayed with General Purpose Input) D = Pad class D (Analog Input) Porst = Porst input Pad XTAL1 = XTAL1 input Pad XTAL2 = XTAL2 input Pad PU = with pull-up device connected during reset (PORST = 0) PU1 = with pull-up device connected during reset (PORST = 0)1) PU2 = with pull-up device connected during startup and reset, HighZ in Standby mode PD = with pull-down device connected during reset (PORST = 0) PD1 = with pull-down device connected during reset (PORST = 0)1) PD2 = with pull-down device connected during startup and reset, HighZ in Standby mode OD = open drain during reset (PORST = 0) ES = Supports Emergency Stop ES1 = ES. ES can be overruled by VADC, control via P00_PCSR ES2 = ES. ES can be overruled by DXCPL - DAP over CAN physical layer, No overruling for DXCM - Debug over CAN message ES3 = ES. ES can be overruled by JTAG mode if this pin is used as TDI ES4 = ES. ES can be overruled by JTAG or Three Pin DAP mode 1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG6 (P14.4). Pls. see also chapter PMS, HWCFG[6]. OPEN MARKET VERSION

Pin Definition and Functions Legend Data Sheet 285 V 1.2, 2021-03 ES5 = ES. ES can be overruled by the Standby Controller - SCR - if implemented. Overruling can be disabled via the control register P33_PCSR and P34_PCSR ES6 = ES. On LVDS TX pads the ES affects the pads only in CMOS mode, not in LVDS mode. Thus, only when LPCRx.TX_EN selects the CMOS Mode, the output is switched off in the ES event OPEN MARKET VERSION

Electrical Specification Parameter Interpretation Data Sheet 286 V 1.2, 2021-03

3 Electrical Specification

3.1 Parameter Interpretation

The parameters listed in this section partly represent the characteristics of the TC38x and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column “Symbol”:

• CC Such parameters indicate Controller Characteristics which are a distinctive feature of the TC38x and must be regarded for a system design.
• SR Such parameters indicate System Requirements which must be provided by the microcontroller system in which the TC38x designed in. OPEN MARKET VERSION

Electrical Specification Absolute Maximum Ratings Data Sheet 287 V 1.2, 2021-03

3.2 Absolute Maximum Ratings

Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the de vice at these or any ot her conditions above those indicated in the Operational Conditions of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 3-1 Absolute Maximum Ratings Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Storage Temperature TST SR -65 - 150 °C upto 65h @ TJ = 150°C Voltage at VDD power supply pins with respect to VSS 1) 2) 1) Valid for cumulated for up to 2.8h and pulse forms followed a power supply switch on phase, where the rise and fall times are related to the system capacities and coils. 2) Due to EVRC output voltage osc illation during switch off phase VDD can drop down to -0.72V. For VDD an input level down to -0.72V during switch off phase will not cause any damage or reliability problem. VDD SR - - 1.65 V upto 2.8h - - 1.45 V upto 72h Voltage at VDDP3 power supply pins with respect to VSS VDDP3 SR - - 4.43 V Voltage at VDDM, VEXT, VFLEX and VEVRSB power supply pins with respect to VSS VDDM SR - - 6.75 V upto 2.8h - - 5.6 V upto 72h Voltage on all analog and class S input pins with respect to VSS 3) Voltages below VINmin have no Impact to the device reliability as Long as the times and currents defined in section Pin Reliability in Overload for the affected pad(s) are not violated. VIN SR -0.7 - 6.75 V Voltage on all other input pins with respect to VSS 3) VIN SR -0.7 - 6.75 V Input current on any pin during overload condition 4) 5) 4) This parameter is an Absolute Maximum Rating. Exposure to Absolute Maximum Ratings for extended periods of time may damage the device. 5) The specified min. and max. values represent the current limits, which have to be maintained, in case of a short circuit condition on the output of any Fast, RFast, Slow and Class S pad, not being used during operation. This covers also output currents due to switching in operation for CL=200pF. IIN SR -10 - 10 mA Absolute maximum sum of all input circuit currents during overload condition. 4) ΣIIN SR -100 - 100 mA OPEN MARKET VERSION

Electrical Specification Pin Reliability in Overload Data Sheet 288 V 1.2, 2021-03

3.3 Pin Reliability in Overload

When receiving signals from highe r voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own IO power supplies specification. The following table defines overload conditions that will not cause any negative reliability impact if all the following conditions are met:

• allowed time interval (defined in Note column) for overload co ndition is not exceeded. If no time limit is defined the allowed time includes both ‘Operation Lifetime hours’ and ‘Inactive Lifetime hours’. The number of hours in Table 3-68 and Table 3-69 are examples only and the applicable numbers are defined by the customer profiles accepted by Infineon.
• Operating Conditions are met for – pad supply levels – temperature If a pin current is out of the Operating Conditions but within the overload par ameters, then the parameters functionality of this pin as sta ted in the Operating Conditions can no longer be guaranteed. Operation is still possible in most cases but with relaxed parameters. Table 3-2 Overload Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Input current on any digital pin during overload condition IIN -5 - 5 mA except LVDS pins -15 1) - 1 5 1) mA except LVDS pins; limited to max. 20 pulses with 1ms pulse length Input current on LVDS pin during overload condition IINLVDS -3 - 3 mA Input current on analog input pin during overload condition IINANA -3 - 3 mA -5 - 5 mA limited to 60h over lifetime Absolute sum of all analog input currents for analog inputs during overload condition IINSA -20 - 20 mA Absolute maximum sum of all input circuit currents during overload condition (digital and analog combined) ΣIINS -100 - 100 mA Signal voltage over/undershoot at GPIOs VOUS VSS - 2 - VEXT/FLEX + 2 V limited to 60h over lifetime; Valid for non LVDS and analoge pads Sum of all inactive device pin currents IIDS -100 - 100 mA Static pin output current IOUT CC - - 2.5 mA 100% duty cycle; output driver = medium - - 5 mA 100% duty cycle; output driver = strong OPEN MARKET VERSION

Electrical Specification Pin Reliability in Overload Data Sheet 289 V 1.2, 2021-03 Overload coupling factor for digital inputs, negative KOVDN CC - - 3*10 -4 Overload injected on GPIO non LVDS pad and affecting neighbor fast pads; -5mA < IIN < 0mA --2 * 1 0 -3 Overload injected on GPIO non LVDS pad and affecting neighbor slow pads VGASTE1N and VGATE1P; -5mA < IIN < 0mA --1 * 1 0 -4 Overload injected on GPIO non LVDS pad and affecting neighbor slow pads; -5mA < IIN < 0mA - - 0.8 Overload injected on LVDS RX pad and affecting neighbor LVDS pads - - 0.5 Overload injected on LVDS TX pad and affecting neighbor LVDS pads Overload coupling factor for digital inputs, positive KOVDP CC - - 1.5*10 -3 Overload injected on GPIO non LVDS pad and affecting neighbor GPIO non LVDS pads - - 1 Overload injected on LVDS RX pad and affecting neighbor LVDS pads --5 * 1 0 -3 Overload injected on LVDS TX pad and affecting neighbor LVDS pads Overload coupling factor for analog inputs, negative 2) KOVAN CC - - 1*10 -4 Analog inputs overlaid with slow pads or pull down diagnostics; - 5mA < IIN < 0mA --1 * 1 0 -5 else; -5mA < IIN < 0mA Table 3-2 Overload Parameters (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Pin Reliability in Overload Data Sheet 290 V 1.2, 2021-03 Overload coupling factor for analog inputs, positive 2) KOVAP CC - - 2*10 -4 Analoge inputs overlaid with slow pads or pull down diagnostics; 0mA < IIN < 5mA --2 * 1 0 -5 else; 0mA < IIN < 5mA 1) Reduced VADC / DSADC result accu racy and / or GPIO input levels (VIL and VIH) can differ from specified parameters. 2) Overload coupling on analog inputs is caused by parasitic effects between pads, input multiplexers and surrounding structures. The given parameters have been verified for all permutations of channels. Also watch multiple connections of a pin to several channels. Table 3-2 Overload Parameters (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Operating Conditions Data Sheet 291 V 1.2, 2021-03

3.4 Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the TC38x. All parameters specified in the following tables refer t o these operating conditions, unless otherwise noticed. Digital supply voltages applied to the TC38x must be static regulated voltages. All parameters specified in the following tables refer to these operating conditions (see table below), unless otherwise noticed in the Note / Test Condition column. Table 3-3 Operating Conditions Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. SRI frequency fSRI SR - - 300 MHz CPU Frequency (All CPUs) fCPUx SR - - 300 MHz PLL0 output frequency fPLL0 SR 20 - 300 MHz SPB frequency fSPB SR - - 100 MHz FSI2 frequency fFSI2 SR - - 300 MHz FSI frequency fFSI SR 20 - 100 MHz GTM frequency fGTM SR - - 200 MHz STM frequency fSTM SR - - 100 MHz ERAY frequency fERAY SR - 80 - MHz VADC frequency fADC SR - - 160 MHz ASCLIN Operating Frequency fASCLINx SR - - 200 MHz CAN frequency fCAN SR - - 80 MHz I2C frequency fI2C SR - - 100 MHz Operating MSC Frequency fMSC SR - - 200 MHz PLL1 output frequency from PER PLL fPLL1 SR 20 - 320 MHz PLL2 output frequency from PER PLL fPLL2 SR 20 - 200 MHz QSPI Frequency fQSPI SR - - 200 MHz ADAS clock frequency fADAS CC 200 - 300 MHz MCANH frequency fMCANH CC - - 100 MHz GETH frequency fGETH CC 100 - 150 MHz Ambient Temperature TA SR -40 - 125 °C valid for all SAK products -40 - 150 °C valid for all SAL products with package -40 - 170 °C valid for all SAL products without package OPEN MARKET VERSION

Electrical Specification Operating Conditions Data Sheet 292 V 1.2, 2021-03 Junction Temperature TJ SR -40 - 150 °C valid for all SAK products -40 - 170 °C valid for all SAL products Core Supply Voltage VDD SR 1.125 1) 1 . 2 5 1 . 3 7 5 2) V ADC analog supply voltage VDDM SR 2.97 5.0 5.5 3) V Digital external supply voltage for pads and EVR VEXT SR 4.5 5.0 5.5 3) V Nominal 5V Pad / Port Pin supply range. 5V pad parameters are valid. 2.97 3.3 3.63 V Nominal 3.3V Pad / Port Pin supply range with VDDP3 supplied externally and EVR33 inactive. 3.3V pad parameters are valid. 3.6 - 4.5 V Flash configured in cranking mode; Flash read operation with reduced performance. EVR33 active in low voltage mode. 3.3V pad parameters are valid. 2.97 - 3.6 V Incase EVR33 is active, Flash configured in sleep mode and execution switched to RAM. 3.3V pad parameters are valid. Digital supply voltage for Flex port VFLEX SR 2.97 - 4.0 V 3.3V pad parameters are valid 4.5 5.0 5.5 3) V 5V pad parameters are valid Digital supply voltage for Flash VDDP3 SR 2.97 3.3 3.63 4) V 2.6 - 3.63 V Flash configured in cranking mode; Flash read operation with reduced performance. Digital ground voltage VSS SR 0 - - V Analog ground voltage for VDDM VSSM CC -0.1 0 0.1 V Table 3-3 Operating Conditions (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Operating Conditions Data Sheet 293 V 1.2, 2021-03 Limitation of Supply Voltage over Time The maximum operation voltage for VEXT/FLEX/DDM supply rails is limited over the complete lifetime. The following voltage profile is an example. Application specific voltage profiles need to be aligned and approved by Infineon Technologies for the fulfillment of quality and reliability targets. The maximum operation voltage for VDD supply rails is limited over the complete lifetime. The following voltage profile is an example. Application specific voltage profiles need to be aligned and approved by Infineon Technologies for the fulfillment of quality and reliability targets. Digital external supply voltage for EVR and during Standby mode VEVRSB SR 2.97 5) - 5.5 V Voltage to ensure defined pad states VDDPPA CC 1.3 6) - - V 1) For VDD 1.08V ≤ VDD < 1.125V operation is still possible but with relaxed parameters. 2) Voltage overshoot to 1.69V i s permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and leakage is increased. 3) Voltage overshoot to 6.5V is p ermissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and leakage is increased. 4) Voltage overshoot to 4.29V i s permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and leakage is increased. 5) VEVRSB supply voltage can drop down upto 2.6V during Standby mode. It is required to have a capictor of 100nF on VEVRSB supply pin. 6) HWCFG[6] pin is latched and pu ll-up or tristate is activated at Port pins when VEXT has reached this level. Table 3-4 Example Voltage Profile VEXT/FLEX/DDM= Duration [h] 5.4 V < VEXT/FLEX/DDM ≤ 5.5 V ≤ 5% of lifetime 5.15 V < VEXT/FLEX/DDM ≤ 5.4 V ≤ 15% of lifetime 4.85 V < VEXT/FLEX/DDM ≤ 5.15 V ≤ 60% of lifetime 4.6 V < VEXT/FLEX/DDM ≤ 4.85 V ≤ 15% of lifetime 4.5 V < VEXT/FLEX/DDM ≤ 4.6 V ≤ 5% of lifetime Table 3-5 Example Voltage Profile VDD= Duration [h] 1.325 V < VDD ≤ 1.375 V ≤ 5% of lifetime 1.275 V < VDD ≤ 1.325 V ≤ 15% of lifetime 1.225 V < VDD ≤ 1.275 V ≤ 60% of lifetime 1.175 V < VDD ≤ 1.225 V ≤ 15% of lifetime 1.125 V < VDD ≤ 1.175V ≤ 5% of lifetime Table 3-3 Operating Conditions (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 294 V 1.2, 2021-03 3.5 5 V / 3.3 V switchable Pads Pad classes slow GPIO and fast GP I O s u p p o r t b o t h A u t o m o t i v e L e ve l ( A L ) o r T T L l e v e l ( T T L ) o p e r a t i o n . Parameters are defined for AL operation and degrade in TTL operation. Table 3-6 PORST Pad Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. PORST pad Output current IPORST CC 13 - - mA VEXT = 2.97V; VPORST = 0.9V Spike filter always blocked pulse duration tSF1 CC - - 80 ns Spike filter pass-through blocked pulse duration tSF2 CC 260 - - ns without additional PORST Digtial Filter active (PORSTDF = 0). Input hysteresis 1) 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. HYS CC 0.055 * VEXT - - V non of the neighbor pads are used as output;TTL (degraded, used for CIF) Pull-down current 2) 2) Values for Pull-down resist or is defined via parameter RMDD in table VADC 5V. IPDL CC - - |130| µA VIH; TTL (degraded, used for CIF) |15| - - µA VIL; TTL (degraded, used for CIF) Input leakage current IOZ CC -450 - 450 nA TJ≤150°C ; (0.1 * VEXT) < VIN < (0.9 * VEXT) -500 - 500 nA TJ≤150°C ;else -900 - 900 nA TJ≤170°C ; (0.1 * VEXT) < VIN < (0.9 * VEXT) -950 - 950 nA TJ≤170°C ; else Input high voltage level VIH SR 1.4 - - V TTL (degraded, used for CIF); VEXT = 2.97V 2.0 - - V TTL; VEXT = 4.5V Input low voltage level VIL SR - - 0.5 V TTL (degraded, used for CIF); VEXT = 2.97V - - 0.8 V TTL; VEXT = 4.5V Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 295 V 1.2, 2021-03 Table 3-7 Fast 5V GPIO Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. On-Resistance of pad output RDSON CC 125 225 320 Ohm medium driver; IOH / OL = 2mA 31 55 80 Ohm strong driver; IOH / OL = 8mA Rise / Fall time 1) 2) tRF CC 1.6 - 3.2 ns CL = 25pF; driver = strong sharp edge; from 0.2 * VEXT/FLEX/EVRSB to 0.8 * VEXT/FLEX/EVRSB 4+0.55*CL 4 + 0 . 7 5 *CL 12+1.0*CL ns driver = medium; CL≤200pF 1.0+0.18* CL 2.5+0.27* CL 5.0+0.35* CL ns driver = strong edge = medium; CL≤200pF 0.5+0.08* CL 0.5+0.11* CL 1.0+0.17* CL ns driver = strong edge = sharp ; CL≤200pF Asymmetry of sending tTX_ASYM CC -1 - 1 ns valid for all data rates excluding clock tolerance Input frequency fIN CC - - 160 MHz Input hysteresis 3) HYS CC 0.09 * VEXT/FLEX/E VRSB - - V non of the neighbor pads are used as output; AL 0.075 * VEXT/FLEX/E VRSB - - V non of the neighbor pads are used as output; TTL 75 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL Pull-up current 4) IPUH CC |30| - - µA VIH; AL or TTL - - |130| µA VIL; AL or TTL Pull-down current 5) IPDL CC - - |130| µA VIH; AL or TTL |30| - - µA VIL; AL |28| - - µA VIL; TTL OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 296 V 1.2, 2021-03 Input leakage current IOZ CC -1100 - 1100 nA TJ ≤ 150°C ; (0.1 * VEXT/FLEX/EVRSB) < VIN < (0.9 * VEXT/FLEX/EVRSB) -2500 - 2500 nA TJ ≤ 150°C ; (0.1 * VEXT/FLEX) < VIN < (0.9 * VEXT/FLEX) ; LVDS_TX / Fast pad type -6000 - 6000 nA TJ ≤ 150°C ; LVDS_RX / Fast pad type ; else -3200 - 3200 nA TJ ≤ 150°C ; LVDS_TX / Fast pad type ; else -1500 - 1500 nA TJ ≤ 150°C ; else -2000 - 2000 nA TJ ≤ 170°C ; (0.1 * VEXT/FLEX/EVRSB) < VIN < (0.9 * VEXT/FLEX/EVRSB) -4000 - 4000 nA TJ ≤ 170°C ; (0.1 * VEXT/FLEX) < VIN < (0.9 * VEXT/FLEX) ; LVDS_TX / Fast pad type -13500 - 13500 nA TJ ≤ 170°C ; LVDS_RX / Fast pad type ; else -5100 - 5100 nA TJ ≤ 170°C ; LVDS_TX / Fast pad type ; else -2500 - 2500 nA TJ ≤ 170°C ; else Input high voltage level VIH SR 0.7 * VEXT/FLEX/E VRSB --V A L 2.0 - - V TTL Input low voltage level VIL SR - - 0.44 * VEXT/FLEX/E VRSB VA L - - 0.8 V TTL Input low threshold variation VILD SR -50 - 50 mV max. variation of 1ms; VEXT/FLEX/EVRSB = constant; AL Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET CC - - 100 ns 1) In the formulas the value of CL needs to be entered in pF to obtain results in ns. 2) Rise / fall times are defined 10% - 90% of pad supply voltage . Table 3-7 Fast 5V GPIO (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 297 V 1.2, 2021-03 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 5) Values for Pull-down resist or is defined via parameter RMDD in table VADC 5V. Table 3-8 Fast 3.3V GPIO Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. On-Resistance of pad output RDSON CC 125 225 320 Ohm medium driver; IOH / OL = 2mA 31 55 80 Ohm strong driver; IOH / OL = 8mA Rise / Fall time 1) 2) tRF CC 1.6 - 4.5 ns CL = 25pF; driver = strong sharp edge; from 0.2 * VEXT/FLEX/EVRSB to 0.8 * VEXT/FLEX/EVRSB --5 n s CL = 25pF; driver = strong sharp edge; from 0.8V to 2.0V (RMII) CL 10+1.25* CL ns driver = medium; CL≤200pF 1.5+0.18* CL 1.5+0.28* CL 8+0.4*CL ns driver = strong edge = medium; CL≤200pF 0.75+0.08 *CL 0.75+0.11 *CL 2.5+0.21* CL ns driver = strong edge = sharp ; CL≤200pF Asymmetry of sending tTX_ASYM CC -1 - 1 ns valid for all data rates excluding clock tolerance Input frequency fIN CC - - 160 MHz Input hysteresis 3) HYS CC 0.055 * VEXT/FLEX/E VRSB - - V non of the neighbor pads are used as output; AL 0.09 * VEXT/FLEX/E VRSB - - V non of the neighbor pads are used as output; TTL 0.055 * VEXT/FLEX/E VRSB - - V non of the neighbor pads are used as output;TTL (degraded, used for CIF) 125 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 298 V 1.2, 2021-03 Pull-up current 4) IPUH CC |17| - - µA VIH; AL and TTL (degraded, used for CIF) |11| - - µA VIH; TTL - - |80| µA VIL; AL and TTL and TTL (degraded, used for CIF) Pull-down current 5) IPDL CC - - |105| µA VIH; AL and TTL (degraded, used for CIF) - - |115| µA VIH; TTL |19| - - µA VIL; AL and TTL |15| - - µA VIL; TTL (degraded, used for CIF) Input leakage current IOZ CC -1100 - 1100 nA TJ ≤ 150°C ; (0.1 * VEXT/FLEX/EVRSB) < VIN < (0.9 * VEXT/FLEX/EVRSB) -2500 - 2500 nA TJ ≤ 150°C ; (0.1 * VEXT/FLEX) < VIN < (0.9 * VEXT/FLEX) ; LVDS_TX / Fast pad type -6000 - 6000 nA TJ ≤ 150°C ; LVDS_RX / Fast pad type ; else -3200 - 3200 nA TJ ≤ 150°C ; LVDS_TX / Fast pad type ; else -1500 - 1500 nA TJ ≤ 150°C ; else -2000 - 2000 nA TJ ≤ 170°C ; (0.1 * VEXT/FLEX/EVRSB) < VIN < (0.9 * VEXT/FLEX/EVRSB) -4000 - 4000 nA TJ ≤ 170°C ; (0.1 * VEXT/FLEX) < VIN < (0.9 * VEXT/FLEX) ; LVDS_TX / Fast pad type -13500 - 13500 nA TJ ≤ 170°C ; LVDS_RX / Fast pad type ; else -5100 - 5100 nA TJ ≤ 170°C ; LVDS_TX / Fast pad type ; else -2500 - 2500 nA TJ ≤ 170°C ; else Table 3-8 Fast 3.3V GPIO (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 299 V 1.2, 2021-03 Input high voltage level VIH SR 0.7 * VEXT/FLEX/E VRSB --V A L 2.0 - - V TTL 1.4 - - V TTL (degraded, used for CIF) Input low voltage level VIL SR - - 0.42 * VEXT/FLEX/E VRSB VA L - - 0.8 V TTL - - 0.5 V TTL (degraded, used for CIF) Input low/high voltage level VILH SR 1.0 - 1.9 V RGMII; no hysteresis available Input low threshold variation VILD SR -33 - 33 mV max. variation of 1ms; VEXT/FLEX/EVRSB = constant; AL Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET CC - - 100 ns 1) In the formulas the value of CL needs to be entered in pF to obtain results in ns. 2) Rise / fall times are defined 10% - 90% of pad supply voltage . 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 5) Values for Pull-down resist or is defined via parameter RMDD in table VADC 5V. Table 3-9 Slow 5V GPIO Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. On-Resistance of pad output RDSON CC 125 225 320 Ohm medium driver; IOH / OL = 2mA Rise / Fall time 1) 2) tRF CC 4+0.55* CL 4 + 0 . 7 5 *CL 12+1*CL ns driver = medium edge = medium ; CL≤200pF 1.5+0.25* CL 2.5+0.40* CL 7+0.55*CL ns driver = medium edge = sharp ; CL≤200pF Asymmetry of sending tTX_ASYM CC -1 - 1 ns valid for all data rates excluding clock tolerance Input frequency fIN CC - - 160 MHz Table 3-8 Fast 3.3V GPIO (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 300 V 1.2, 2021-03 Input hysteresis 3) HYS CC 0.09 * VEXT/FLEX/E VRSB - - V non of the neighbor pads are used as output; AL 0.075 * VEXT/FLEX/E VRSB - - V non of the neighbor pads are used as output; TTL 75 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL Pull-up current 4) IPUH CC |30| - - µA VIH;AL or TTL; exept VGATE1P; except VGATE1N and TJ > 150°C - - |130| µA VIL; AL or TTL; exept VGATE1P; except VGATE1N and TJ > 150°C Pull-down current 5) IPDL CC - - |130| µA VIH; AL or TTL |30| - - µA VIL; AL |28| - - µA VIL; TTL Input leakage current IOZ CC -300 - 300 nA TJ ≤ 150°C; (0.1 * VEXT/FLEX/EVRSB) < VIN < (0.9 * VEXT/FLEX/EVRSB) -400 - 400 nA TJ ≤ 150°C; else -600 - 600 nA TJ ≤ 170°C; (0.1 * VEXT/FLEX/EVRSB) < VIN < (0.9 * VEXT/FLEX/EVRSB) -750 - 750 nA TJ ≤ 170°C; else -18000 - 18000 nA P32.0 and P32.1;TJ≤150°C -38000 - 38000 nA P32.0 and P32.1;TJ≤170°C Input high voltage level VIH SR 0.7 * VEXT/FLEX/E VRSB --V A L 2.0 - - V TTL Input low voltage level VIL SR - - 0.44 * VEXT/FLEX/E VRSB VA L - - 0.8 V TTL Table 3-9 Slow 5V GPIO (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 301 V 1.2, 2021-03 Input low threshold variation VILD SR -50 - 50 mV max. variation of 1ms; VEXT/FLEX/EVRSB = constant; AL Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET CC - - 100 ns 1) In the formulas the value of CL needs to be entered in pF to obtain results in ns. 2) Rise / fall times are defined 10% - 90% of pad supply voltage . 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 5) Values for Pull-down resist or is defined via parameter RMDD in table VADC 5V. Table 3-10 Slow 3.3V GPIO Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. On-Resistance of pad output RDSON CC 125 225 320 Ohm medium driver; IOH / OL = 2mA Rise / Fall time 1) 2) tRF CC 2+0.57* CL 5.5+0.75* CL 10+1.25* CL ns driver = medium edge = medium ; CL≤200pF CL 5+0.70*CL ns driver = medium edge = sharp ; CL≤200pF Asymmetry of sending tTX_ASYM CC -1 - 1 ns valid for all data rates excluding clock tolerance Input frequency fIN CC - - 160 MHz Input hysteresis 3) HYS CC 0.055 * VEXT/FLEX/E VRSB - - V non of the neighbor pads are used as output; AL 0.09 * VEXT/FLEX/E VRSB - - V non of the neighbor pads are used as output; TTL 0.055 * VEXT/FLEX/E VRSB - - V non of the neighbor pads are used as output;TTL (degraded, used for CIF) 125 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL Table 3-9 Slow 5V GPIO (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 302 V 1.2, 2021-03 Pull-up current 4) IPUH CC |17| - - µA VIH; AL and TTL (degraded, used for CIF); exept VGATE1P; except VGATE1N and TJ > 150°C |11| - - µA VIH; TTL; exept VGATE1P; except VGATE1N and TJ > 150°C - - |80| µA VIL; AL and TTL and TTL (degraded, used for CIF); exept VGATE1P; except VGATE1N and TJ > 150°C Pull-down current 5) IPDL CC - - |105| µA VIH; AL and TTL (degraded, used for CIF) - - |115| µA VIH; TTL |19| - - µA VIL; AL and TTL |15| - - µA VIL; TTL (degraded, used for CIF) Input leakage current IOZ CC -300 - 300 nA TJ ≤ 150°C; (0.1 * VEXT/FLEX/EVRSB) < VIN < (0.9 * VEXT/FLEX/EVRSB) -400 - 400 nA TJ ≤ 150°C; else -600 - 600 nA TJ ≤ 170°C; (0.1 * VEXT/FLEX/EVRSB) < VIN < (0.9 * VEXT/FLEX/EVRSB) -750 - 750 nA TJ ≤ 170°C; else -18000 - 18000 nA P32.0 and P32.1;TJ≤150°C -38000 - 38000 nA P32.0 and P32.1;TJ≤170°C Input high voltage level VIH SR 0.7 * VEXT/FLEX/E VRSB --V A L 2.0 - - V TTL 1.4 - - V TTL (degraded, used for CIF) Table 3-10 Slow 3.3V GPIO (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 303 V 1.2, 2021-03 Input low voltage level VIL SR - - 0.42 * VEXT/FLEX/E VRSB VA L - - 0.8 V TTL - - 0.5 V TTL (degraded, used for CIF) Input low/high voltage level VILH SR 1.0 - 1.9 V RGMII; no hysteresis available Input low threshold variation VILD SR -33 - 33 mV max. variation of 1ms; VEXT/FLEX/EVRSB = constant; AL Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET CC - - 100 ns 1) In the formulas the value of CL needs to be entered in pF to obtain results in ns. 2) Rise / fall times are defined 10% - 90% of pad supply voltage . 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 5) Values for Pull-down resist or is defined via parameter RMDD in table VADC 5V. Table 3-11 RFast 5V GPIO Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. On-Resistance of pad output RDSON CC 125 225 320 Ohm medium driver; IOH / OL = 2mA 31 55 80 Ohm strong driver; IOH / OL = 8mA Rise / Fall time 1) 2) tRF CC 1.6 - 3.2 ns CL = 25pF; driver = strong sharp edge; from 0.2 * VFLEX to 0.8 * VFLEX 4+0.55*CL 4 + 0 . 7 5 *CL 12+1.0*CL ns driver = medium; CL≤200pF 1.0+0.18* CL 2.5+0.27* CL 5.0+0.35* CL ns driver = strong edge = medium; CL≤200pF 0.5+0.08* CL 0.5+0.11* CL 1.0+0.17* CL ns driver = strong edge = sharp ; CL≤200pF Asymmetry of sending tTX_ASYM CC -0.5 - 0.5 ns valid for all data rates excluding clock tolerance Table 3-10 Slow 3.3V GPIO (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 304 V 1.2, 2021-03 Input frequency fIN CC - - 160 MHz Input hysteresis 3) HYS CC 0.09 * VFLEX - - V non of the neighbor pads are used as output; AL 0.075 * VFLEX - - V non of the neighbor pads are used as output; TTL 75 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL Pull-up current 4) IPUH CC |30| - - µA VIH; AL or TTL - - |130| µA VIL; AL or TTL Pull-down current 5) IPDL CC - - |130| µA VIH; AL or TTL |30| - - µA VIL; AL |28| - - µA VIL; TTL Input leakage current IOZ CC -1700 - 1700 nA TJ ≤ 150°C ; (0.1 * VFLEX) < VIN < (0.9 * VFLEX) -2100 - 2100 nA TJ ≤ 150°C ; else -3000 - 3000 nA TJ ≤ 170°C ; (0.1 * VFLEX) < VIN < (0.9 * VFLEX) -4000 - 4000 nA TJ ≤ 170°C ; else Input high voltage level VIH SR 0.7 * VFLEX - - V A L 2.0 - - V TTL Input low voltage level VIL SR - - 0.44 * VFLEX VA L - - 0.8 V TTL Input low threshold variation VILD SR -50 - 50 mV max. variation of 1ms; VFLEX = constant; AL Pin capacitance CIO CC - 2 3.5 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET CC - - 100 ns 1) In the formulas the value of CL needs to be entered in pF to obtain results in ns. 2) Rise / fall times are defined 10% - 90% of pad supply voltage . 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. Table 3-11 RFast 5V GPIO (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 305 V 1.2, 2021-03 5) Values for Pull-down resist or is defined via parameter RMDD in table VADC 5V. Table 3-12 RFast 3.3V pad Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. On-Resistance of pad output RDSON CC 8 20 30 Ohm Driver = RGMII; IOH / OL = 8mA 125 225 320 Ohm medium driver; IOH / OL = 2mA 31 55 80 Ohm strong driver; IOH / OL = 8mA Input Duty Cycle fD SR 47.5 50 52.5 Rise / Fall time 1) 2) tRF CC 1.6 - 4.5 ns CL = 25pF; driver = strong sharp edge; from 0.2 * VFLEX to 0.8 * VFLEX --5 n s CL = 25pF; driver = strong sharp edge; from 0.8V to 2.0V (RMII) - - 1 ns Driver = RGMII; from 20%V to 80%V; CL=15pF CL 10+1.25* CL ns driver = medium; CL≤200pF 1.5+0.18* CL 1.5+0.28* CL 8+0.4*CL ns driver = strong edge = medium; CL≤200pF 0.75+0.08 *CL 0.75+0.11 *CL 2.5+0.21* CL ns driver = strong edge = sharp ; CL≤200pF Asymmetry of sending tTX_ASYM CC -0.4 - 0.4 ns valid for all data rates excluding clock tolerance Input frequency fIN CC - - 160 MHz OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 306 V 1.2, 2021-03 Input hysteresis 3) HYS CC 0.055 * VFLEX - - V non of the neighbor pads are used as output; AL 0.09 * VFLEX - - V non of the neighbor pads are used as output; TTL 0.055 * VFLEX - - V non of the neighbor pads are used as output;TTL (degraded, used for CIF) 125 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL Pull-up current 4) IPUH CC |17| - - µA VIH; AL and TTL (degraded, used for CIF) |11| - - µA VIH; TTL - - |80| µA VIL; AL and TTL and TTL (degraded, used for CIF) Pull-down current 5) IPDL CC - - |105| µA VIH; AL and TTL (degraded, used for CIF) - - |115| µA VIH; TTL |19| - - µA VIL; AL and TTL |15| - - µA VIL; TTL (degraded, used for CIF) Input leakage current IOZ CC -1700 - 1700 nA TJ ≤ 150°C ; (0.1 * VFLEX) < VIN < (0.9 * VFLEX) -2100 - 2100 nA TJ ≤ 150°C ; else -3000 - 3000 nA TJ ≤ 170°C ; (0.1 * VFLEX) < VIN < (0.9 * VFLEX) -4000 - 4000 nA TJ ≤ 170°C ; else Input high voltage level VIH SR 0.7 * VFLEX - - V A L 2.0 - - V TTL 1.4 - - V TTL (degraded, used for CIF) Table 3-12 RFast 3.3V pad (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 307 V 1.2, 2021-03 Input low voltage level VIL SR - - 0.42 * VFLEX VA L - - 0.8 V TTL - - 0.5 V TTL (degraded, used for CIF) Input low threshold variation VILD SR -33 - 33 mV max. variation of 1ms; VFLEX = constant; AL Pin capacitance CIO CC - 2 3.5 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET CC - - 100 ns 1) In the formulas the value of CL needs to be entered in pF to obtain results in ns. 2) Rise / fall times are defined 10% - 90% of pad supply voltage . 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 5) Values for Pull-down resist or is defined via parameter RMDD in table VADC 5V. Table 3-13 Class S 5V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Input frequency fIN CC - - 160 MHz Input hysteresis 1) HYS CC 0.09 * VDDM - - V non of the neighbor pads are used as output; AL 0.075 * VDDM - - V non of the neighbor pads are used as output; TTL 75 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL Pull-up current 2) IPUH CC |30| - - µA VIH; AL or TTL - - |130| µA VIL; AL or TTL Pull-down current 3) IPDL CC - - |130| µA VIH; AL or TTL |30| - - µA VIL; AL |28| - - µA VIL; TTL Table 3-12 RFast 3.3V pad (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 308 V 1.2, 2021-03 Input leakage current IOZ CC -150 - 150 nA TJ ≤ 150°C; else -300 - 300 nA TJ ≤ 150°C; PDD option available, or AltRef option available and EDSADC channel connected, or two EDSADC channels connected -300 - 300 nA TJ ≤ 170°C; else -600 - 600 nA TJ ≤ 170°C; PDD option available, or AltRef option available and EDSADC channel connected, or two EDSADC channels connected Input high voltage level VIH SR 0.7 * VDDM - - V A L 2.0 - - V TTL Input low voltage level VIL SR - - 0.44 * VDDM VA L - - 0.8 V TTL Input low threshold variation VILD SR -50 - 50 mV max. variation of 1ms; VDDM = constant; AL Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET CC - - 100 ns 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 2) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 3) Values for Pull-down resist or is defined via parameter RMDD in table VADC 5V. Table 3-14 Class S 3.3V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Input frequency fIN CC - - 160 MHz Table 3-13 Class S 5V (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 309 V 1.2, 2021-03 Input hysteresis 1) HYS CC 0.055 * VDDM - - V non of the neighbor pads are used as output; AL 0.09 * VDDM - - V non of the neighbor pads are used as output; TTL 0.065 * VDDM - - V non of the neighbor pads are used as output; TTL (degraded used for CIF) 125 - - mV two of the neighbor pads are used as output with driver=strong and edge=sharp; AL Pull-up current 2) IPUH CC |17| - - µA VIH; AL and TTL (degraded, used for CIF) |11| - - µA VIH; TTL - - |80| µA VIL Pull-down current 3) IPDL CC - - |105| µA VIH; AL and TTL (degraded, used for CIF) - - |115| µA VIH; TTL |19| - - µA VIL; AL and TTL |15| - - µA VIL; TTL (degraded, used for CIF) Input leakage current IOZ CC -150 - 150 nA TJ ≤ 150°C; else -300 - 300 nA TJ ≤ 150°C; PDD option available, or AltRef option available and EDSADC channel connected -300 - 300 nA TJ ≤ 170°C; else -600 - 600 nA TJ ≤ 170°C; PDD option available Input high voltage level VIH SR 0.7 * VDDM - - V A L 2.0 - - V TTL 1.4 - - V TTL (degraded, used for CIF) Table 3-14 Class S 3.3V (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 310 V 1.2, 2021-03 Input low voltage level VIL SR - - 0.42 * VDDM VA L - - 0.8 V TTL - - 0.5 V TTL (degraded, used for CIF) Input low threshold variation VILD SR -33 - 33 mV max. variation of 1ms; VDDM = constant; AL Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added Pad set-up time to get an software update of the configuration active tSET CC - - 100 ns 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 2) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V. 3) Values for Pull-down resist or is defined via parameter RMDD in table VADC 5V. Table 3-15 Class D Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Input leakage current IOZ CC -150 - 150 nA TJ ≤ 150°C; else -300 1) 1) For AN11 100 nA need to be added. -3 0 0 1) nA TJ ≤ 150°C; PDD option available, or AltRef option available and EDSADC channel connected, or two EDSADC channels connected -300 - 300 nA TJ ≤ 170°C; else -600 2) 2) For AN11 200 nA need to be added. -6 0 0 2) nA TJ ≤ 170°C; PDD option available, or AltRef option available and EDSADC channel connected, or two EDSADC channels connected Pin capacitance CIO CC - 2 3 pF in addition 2.5pF from package to be added Table 3-14 Class S 3.3V (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 311 V 1.2, 2021-03 Table 3-16 ADC Reference Pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Input leakage current for VAREF IOZ2 CC -2 1) 1) Limit is valid for VAREF2 pin. -2 1) µA TJ ≤ 150°C; VAREF < VDDM; for EVADC; valid for BGA292 -7 1) -7 1) µA TJ ≤ 150°C; VAREF ≤ VDDM+50mV; for EVADC; valid for BGA292 -4 1) -4 1) µA TJ ≤ 170°C; VAREF < VDDM; for EVADC; valid for BGA292 -14 1) -1 4 1) µA TJ ≤ 170°C; VAREF ≤ VDDM+50mV; for EVADC; valid for BGA292 -1 2) 2) Limit is valid for VAREF 2 and VAREF3 pins each. -1 2) µA TJ ≤ 150°C; VAREF < VDDM; for EVADC; valid for BGA516 -2 2) -2 2) µA TJ ≤ 170°C; VAREF < VDDM; for EVADC; valid for BGA516 -3.5 2) -3 . 5 2) µA TJ ≤ 150°C; VAREF ≤ VDDM+50mV; for EVADC; valid for BGA516 -7 2) -7 2) µA TJ ≤ 170°C; VAREF ≤ VDDM+50mV; for EVADC; valid for BGA516 -2 3) 3) Limit is valid for VAREF1 pin. -2 3) µA TJ ≤ 150°C; VAREF < VDDM; for EDSADC -4 3) -4 3) µA TJ ≤ 170°C; VAREF < VDDM; for EDSADC -6 3) -6 3) µA TJ ≤ 150°C; VAREF ≤ VDDM+50mV; for EDSADC -12 3) -1 2 3) µA TJ ≤ 170°C; VAREF ≤ VDDM+50mV; for EDSADC OPEN MARKET VERSION

Electrical Specification 5 V / 3.3 V switchable Pads Data Sheet 312 V 1.2, 2021-03 Table 3-17 Driver Mode Selection for Slow Pads PDx.2 PDx.1 PDx.0 Port Functionality Driver Setting X X 0 Speed grade 1 medium sharp edge (sm) X X 1 Speed grade 2 medium medium edge (m) Table 3-18 Driver Mode Selection for Fast Pads PDx.2 PDx.1 PDx.0 Port Functionality Driver Setting X 0 0 Speed grade 1 Strong sharp edge (ss) X 0 1 Speed grade 2 Strong medium edge (sm) X 1 0 Speed grade 3 medium (m) X 1 1 Speed grade 4 Reserved, do not use this combination Table 3-19 Driver Mode Selection for RFast Pads PDx.2 PDx.1 PDx.0 Port Functionality Driver Setting X 0 0 Speed grade 1 Strong sharp edge (ss) X 0 1 Speed grade 2 Strong medium edge (sm) X 1 0 Speed grade 3 medium (m) X 1 1 Speed grade 4 RGMII function active OPEN MARKET VERSION

Electrical Specification High performance LVDS Pads Data Sheet 313 V 1.2, 2021-03

3.6 High performance LVDS Pads

This LVDS pad type is used for the high speed chip to chip communication interface of the new TC38x. It compose out of a LVDS pad and a fast pad. CL = 2.5 pF for all LVDS parameters. Table 3-20 LVDS - IEEE standard LVDS general purpose link (GPL) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Output impedance R0 CC 40 - 140 Ohm Vcm = 1.0 V and 1.4 V Rise time (20% - 80%) trise20 CC - - 0.75 1) n s ZL = 100 Ohm ±20% @2pF external load Fall time (20% - 80%) tfall20 CC - - 0.75 2) n s ZL = 100 Ohm ±20% @2pF external load Output differential voltage 3) VOD CC 240 - 330 mV RT = 100 Ohm ±1%; LPCRx.VDIFFADJ=00 280 - 370 mV RT = 100 Ohm ±1%; LPCRx.VDIFFADJ=01 320 - 410 mV RT = 100 Ohm ±1%; LPCRx.VDIFFADJ=10 380 - 500 mV RT = 100 Ohm ± 1%; LPCRx.VDIFFADJ=11; Multi slave operation Output voltage high VOH CC - - 1475 mV RT = 100 Ohm +/- 1% VDIFFADJ=00 and 01 - - 1500 mV RT = 100 Ohm ± 1% VDIFFADJ=10 and 11 Output voltage low VOL CC 925 - - mV RT = 100 Ohm ± 1% VDIFFADJ=00 and 01 900 - - mV RT = 100 Ohm +/- 1% VDIFFADJ=10 and 11 Output offset (Common mode) voltage VOS CC 1125 - 1275 mV RT = 100 Ohm ± 1% Input voltage range VI SR 0 - 1600 mV Driver ground potential difference < 925 mV; RT = 100 Ohm ±10% 0 - 2400 mV Driver ground potential difference < 925 mV; RT = 100 Ohm ±20% Input differential threshold Vidth SR -100 - 100 mV Driver ground potential difference < 900 mV; VDIFFADJ=10 and 11 -100 - 100 mV Driver ground potential difference < 925 mV; VDIFFADJ=00 and 01 OPEN MARKET VERSION

Electrical Specification High performance LVDS Pads Data Sheet 314 V 1.2, 2021-03 Note: Driver ground potential difference is defined as driver-receiver potentital difference, that can result in a voltage shift when comparing driver output voltage level and receiver input voltage level of a transmitted signal. Note: RT in table ‘LVDS - IEEE standard LVDS general purpose Link (GPL)’ is as termination resistor of the receiver according to figure 3-5 in IEEE Std 1596.3-1996 and is represent in Figure 3-1 either by Rin or by RT=100Ohm but not both. If RT is mentioned in column Note / Test Condition always the internal resistor Rin in Figure 3-1 is the selected one. default after start-up = CMOS function Receiver differential input impedance Rin CC 80 - 120 Ohm VI ≤ 2400 mV Output differential voltage Sleep Mode 4) VODSM CC -5 - 20 mV RT = 100 Ohm ± 20%; LPCRx.VDIFFADJ=xx Delta output impedance dR0 SR - - 10 % Vcm = 1.0 V and 1.4 V Change in VOS between 0 and dVOS CC - - 25 mV RT = 100 Ohm ±1% Change in Vod between 0 and 1 dVod CC - - 25 mV RT = 100 Ohm ±1% Pad set-up time tSET_LVDS CC -1 0 1 3 µ s Duty cycle tduty CC 45 - 55 % 1) trise20 = 0.75ns + (CL - 2)[pF]*20ps. CL defines the external load. 2) tfall20 = 0.75ns + (CL - 2)[pF]*20ps. CL defines the external load. 3) Potential violations of the IE EE Std 1596.3 are intended for the new multislave support feature. To be compliant to IEEE Std 1596.3 LPCRx.VDIFFADJ has to be configured to 01. 4) Common Mode voltage of Tx is maintained. Table 3-20 LVDS - IEEE standard LVDS general purpose link (GPL) (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification High performance LVDS Pads Data Sheet 315 V 1.2, 2021-03 Figure 3-1 LVDS pad Input model Ctotal=3.5pF LVDS_Input_Pad_Model.vsd Htotal=5nH LVDS IN P N RT=100Ohm Ctotal=3.5pF Rin Cext=2pF Cext=2pF Htotal=5nH OPEN MARKET VERSION

Electrical Specification VADC Parameters Data Sheet 316 V 1.2, 2021-03

3.7 VADC Parameters

The accuracy of the converter results depends on the reference voltage range. The parameters in the table below are valid for a reference voltage range of ( VAREF - VAGND) >= 4.5 V. If the reference voltage range is below 4.5 V Noise on supply voltage VDDM influences the conversion. The accuracy (error) parameters are defined for a supply voltage ripple of below 20 mVpp up to 10 MHz (below 5 mVpp above 10M H z ) . Digital functions overlapping analog inputs influence accuracy. The total unadjusted error (TUE) is defined without noise. The overall deviation depends on TUE and ENRMS (depending on the noise distribution). Example: For a noise distribution of 4 sigma and ENRMS = 1.0 the additional peak-peak noise error is ±(4 × 1.0) = 8 LSB12. Fast compare operations are executed with 10-bit values. The noise reduction feature improv es the result by adding addit ional conversion steps. The conversion times, therefore, increase accordingly (4 × tADCI + 3 × tADC for each of 1, 3, or 7 steps). Table 3-21 VADC 5V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. EVADC IVR output voltage VDDK CC 1.15 - 1.35 V Measured at low temperature. Deviation of IVR output voltage VDDK dVDDK CC -2 - 2 % Based on device- specific value Analog reference voltage 1) VAREF SR 4.5 5.0 VDDM + 0.05 V 4.5 V ≤ VDDM ≤ 5.5 V 2.97 3.3 VDDM + 0.05 V2 . 9 7 V ≤ VDDM < 4.5 V Analog reference ground VAGND SR VSSM VSSM VSSM V VSSM and VAGND are connected together Analog input voltage range VAIN SR VAGND - VAREF V VAIN is limited by the respective pad supply voltage; see pin configuration (buffer type) Converter reference clock fADCI SR 16 40 53.33 MHz 4.5 V ≤ VDDM ≤ 5.5 V 16 20 26.67 MHz 2.97 V ≤ VDDM < 4.5 V Total Unadjusted Error 2) 3) TUE CC -4 - 4 LSB 12-bit resolution for primary/secondary groups, 10-bit resolution for fast compare channels INL Error 2) EAINL CC -3 - 3 LSB DNL error 2)4) EADNL CC -1 - 3 LSB Gain Error 2) EAGAIN CC -3.5 - 3.5 LSB Offset Error 2)3) EAOFF CC -4 - 4 LSB OPEN MARKET VERSION

Electrical Specification VADC Parameters Data Sheet 317 V 1.2, 2021-03 RMS Noise 2)5) 6) ENRMS CC - 0.5 0.8 LSB Noise reduction level 3 - 0.5 1.0 LSB Standard conversion Reference input charge consumption per conversion (from VAREF) 7) 8) 9) QCONV CC - - 20 pC VAIN = 0 V (worst case), precharging disabled --1 0 p C VAIN = 0 V (worst case), precharging enabled, VDDM - 5% < VAREF < VDDM + 50 mV Switched capacitance of an analog input CAINS CC - 2.5 3.4 pF Input buffer disabled Analog input charge consumption 10) QAINS CC - - 3.5 pC Primary groups and fast compare channels; VAIN = VAREF; VDDM = 5.0 V; input buffer enabled; TJ ≤ 150°C - - 3.8 pC Primary groups and fast compare channels; VAIN = VAREF; VDDM = 5.0 V; input buffer enabled; TJ > 150°C - - 4.4 pC Secondary groups; VAIN = VAREF; VDDM = 5.0 V; input buffer enabled; TJ ≤ 150 °C - - 4.8 pC Secondary groups; VAIN = VAREF; VDDM = 5.0 V; input buffer enabled; TJ > 150°C Table 3-21 VADC 5V (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification VADC Parameters Data Sheet 318 V 1.2, 2021-03 Sampling time tS SR 100 - - ns Primary group or fast compare channel, 4.5 V ≤ VDDM ≤ 5.5 V; input buffer disabled 300 - - ns Primary group or fast compare channel, 4.5 V ≤ VDDM ≤ 5.5 V; input buffer enabled 500 - - ns Secondary group, 4.5 V ≤ VDDM ≤ 5.5 V; input buffer disabled 700 - - ns Secondary group, 4.5 V ≤ VDDM ≤ 5.5 V; input buffer enabled 200 - - ns Primary Group or fast compare channel, 2.97 V ≤ VDDM < 4.5 V; input buffer disabled 400 - - ns Primary group or fast compare channel, 2.97 V ≤ VDDM < 4.5 V; input buffer enabled 1000 - - ns Secondary group, 2.97 V ≤ VDDM < 4.5 V; input buffer disabled 1200 - - ns Secondary group, 2.97 V ≤ VDDM < 4.5 V; input buffer enabled Sampling time for calibration tSCAL SR 50 - - ns 4.5 V ≤ VDDM ≤ 5.5 V 100 - - ns 2.97 V ≤ VDDM < 4.5 V Input buffer switch-on time tBUF CC - 0.4 1 µs Wakeup time tWU CC - 0.1 0.2 µs Fast standby mode - 1.6 3 µs Slow standby mode Broken wire detection delay against VAREF tBWR CC - 100 - cycles Result above 80% of full scale range, analog input buffer disabled Broken wire detection delay against VAGND tBWG CC - 100 - cycles Result below 10% of full scale range, analog input buffer disabled Converter diagnostics unit resistance 11) RCSD CC 45 - 75 kOhm Converter diagnostics voltage accuracy dVCSD CC -10 - 10 % Percentage refers to VDDM Table 3-21 VADC 5V (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification VADC Parameters Data Sheet 319 V 1.2, 2021-03 Figure 3-2 Equivalent Circuitry for Analog Inputs Resistance of the multiplexer diagnostics pull-up device RMDU CC 30 - 42 kOhm 0 V ≤ VIN ≤ 0.9* VDDM, Automotive Levels 56 - 78 kOhm 0 V ≤ VIN ≤ 0.9* VDDM, TTL Levels Resistance of the multiplexer diagnostics pull-down device RMDD CC 43 - 58 kOhm 0.1* VDDM ≤ VIN ≤ VDDM, Automotive level 18 - 25 kOhm 0.1* VDDM ≤ VIN ≤ VDDM, TTL level Resistance of the pull-down test device RPDD CC - - 0.3 kOhm Measured at pad input voltage VIN = VDDM / 2. 1) These limits apply t o the standard reference input as well as to the alternate reference input. 2) Parameter depends on reference voltage range and supply ripple, see introduction. Resulting worst case combined error is arithmetic combination of TUE and ENRMS. Tests are done with postcalibration disabled, after completing the startup calibration. 3) Analog inputs mapped to pads of the type SLOW influence accuracy. The values for this parameter increase by 3 LSB12. 4) Monotonic characteristic, no missing codes when calibrated. 5) Parameter EN RMS refers to a 1 sigma distribution. 6) Analog inputs mapped to pads of the type SLOW the RMS noise (ENRMS) can be up to 2 LSB 12 (soft switching for DC/DC enabled). 7) For reduced reference voltages VAREF < 3.375V, the consumed charge QCONV is reduced by the factor of k2 = VAREF [V] 8) Maximum charge increases by 15 pC when BWD (Broken Wire Detection) is active. 9) Fast compare channels only cons ume 1/3 of the charge for a primary/secondary group. 10) For analog inputs with overlaid digital GPIOs or with PDD function this value increases by 1 pC. 11) Use a sample time of at least 1.1 µs to enable proper settling of the test voltage. Table 3-21 VADC 5V (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification DSADC Parameters Data Sheet 320 V 1.2, 2021-03

3.8 DSADC Parameters

The DSADC parameters are valid only for voltage range 4.5 V <= VDDM <= 5.5 V. These parameters describe the product properties and do not inc lude external circuitry. The values are valid for junction temperatures TJ <= 150°C if not defined explicitly. Calibration is specified for gain factors 1 and 2, calibrated values refer to these settings. The signal-noise ratio (SNR) is specified for differential inpu ts. For single ended operation the resulting signal- noise ratio is reduced by 6 dB. For quasi-differential mode (i.e. using VCM) it is reduced by 6 dB for gain = 1 and by 3 dB for gain= 2. Table 3-22 DSADC 5V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Common mode voltage bias resistance RBIAS CC 105 130 155 kOhm On-chip variation ≤ ±2.5%. Positive reference voltage VAREF SR 4.5 - VDDM + 0.05 V Reference ground voltage VAGND SR VSSM - VSSM V VSSM and VAGND are connected together Reference load current IREF CC - 10 12 µA Per modulator - - 14 µA Per modulator, TJ>150°C Common mode voltage accuracy 1) dVCM CC -100 - 100 mV Deviation from selected voltage Analog input voltage range VDSIN SR VSSM - 2 * VDDM V Differential; VDSxP - VDSxN VSSM - VDDM V Single ended Input current 2) IRMS CC 7 10 13 µA Exact value (±1%) available in UCB; valid for gain = 1 and fMOD =

26.7 MHz

Gain error 3) 4) EDGAIN CC -0.2 5) ± 0 . 1 5) 0.2 5) % TJ≤150°C; Target, calibrated, VAREF constant after calibration; fMOD =

26.67 MHz

• ±0.25 - % TJ>150°C; VAREF constant after calibration; fMOD =

-1 - 1 % Calibrated once; fMOD = -2.5 - 2.5 % Uncalibrated; fMOD =

Electrical Specification DSADC Parameters Data Sheet 321 V 1.2, 2021-03 DC offset error 3) EDOFF CC -5 5) -5 5) mV Calibrated; fMOD = -10 - 10 mV Calibrated once; fMOD = -30 - 30 mV Uncalibrated; fMOD = differential input signals 2)6) 7) SNR CC 80 - - dB TJ≤150°C; fPB = 30 kHz; fMOD = 26.67 MHz 78 - - dB TJ≤150°C; fPB = 50 kHz; fMOD = 26.67 MHz 74 - - dB TJ≤150°C; fPB = 100 kHz; fMOD = 26.67 MHz Signal-Noise Ratio degradation DSNR CC - - 3 dB TJ>150°C; Resulting Signal-Noise Ratio value is SNR - DSNR Spurious-free dynamic range 3) SFDR CC 60 - - dB fMOD = 26.67 MHz Output sampling rate fD CC 3.906 - 300 kHz 16 MHz / 4096, without integrator Pass band fPB CC 1.302 - 100 kHz Output data rate: fD = fPB * 3; without integrator 1.302 - 10 kHz Output data rate: fD = fPB * 6; without integrator Pass band ripple dfPB CC -0.08 - 0.08 dB FIR filters enabled 60 - - dB 2.5 fD ... OSR/2 fD DC compensation factor DCF CC -3 - - dB 10 -5 fD, offset compensation filter enabled (FCFGMx.OCEN = 001B) Modulator settling time tMSET CC - - 20 µs After switching on, voltage regulator already running 1) On pins with overlaid GPIO func tion the max. limit increases by up to 25 mV due to leakage current for TJ > 150°C. 2) For detailed information, refer to the User Manual chapter. 3) This parameter is valid w ithin the defined range of fMOD. 4) Gain mismatch error between t he different EDSADC channels is within ±0.5% if they have the same calibration strategy Table 3-22 DSADC 5V (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification DSADC Parameters Data Sheet 322 V 1.2, 2021-03 5) Recalibration needed in case of a temperature change >20ºC 6) These values are valid for an analog gain factor of 1. Subtract 3 dB for each higher gain factor. 7) For single ended input signals and gain1, the SNR is reduced by 6 dB. OPEN MARKET VERSION

Electrical Specification MHz Oscillator Data Sheet 323 V 1.2, 2021-03

3.9 MHz Oscillator

OSC_XTAL is used as accurate and exact clock source. OSC_XTAL supports 16 MHz to 40 MHz crystals external outside of the device. Support of ceramic resonators is also provided. Table 3-23 OSC_XTAL Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Input current at XTAL1 IIX1 CC -70 - 70 µA VIN>0V ; VIN<VEXT Oscillator frequency fOSC SR 4 - 40 MHz Direct Input Mode selected, if shaper is not bypassed 16 - 40 MHz External Crystal Mode selected Oscillator start-up time tOSCS CC - - 3 1) 1) tOSCS is defined from the moment when the Oscillator Mode is set to External Crystal Mode until the oscillations reach an amplitude at XTAL1 of 0.3 * VEXT. This value depends on the frequency of the used external crystal. For faster crystal frequencies this value decrease. ms 20MHz ≤ fOSC and 8pF load capacitance Input voltage at XTAL1 2) 2) For Supply ( VEXT < 5.3V VIX) min could be down to -0.9V. For XTAL1 an input level down to -0.9V will not cause a damage or a reliability problem operating with an external crystal. VIX SR -0.7 - VEXT + 0.5 V If shaper is not bypassed Input amplitude (peak to peak) at XTAL1 VPPX SR 0.3* VEXT - VEXT + 1.0 V If shaper is not bypassed; fOSC > 25MHz 0.35*VEXT - VEXT + 1.0 V If shaper is not bypassed; fOSC ≤ 25MHz Internal load capacitor CL0 CC 1.30 1.40 1.55 pF enabled via bit OSCCON.CAP0EN Internal load capacitor CL1 CC 3.05 3.35 3.70 pF enabled via bit OSCCON.CAP1EN Internal load capacitor CL2 CC 7.85 8.70 9.55 pF enabled via bit OSCCON.CAP2EN Internal load capacitor CL3 CC 12.05 13.35 14.65 pF enabled via bit OSCCON.CAP3EN Internal load stray capacitor between XTAL1 and XTAL2 CXINTS CC 1.15 1.20 1.25 pF Internal load stray capacitor between XTAL1 and ground CXTAL1 CC - 2.5 4 pF Duty cycle at XTAL1 3) DCX1 SR 35 - 65 % VXTAL1 = 0.5*VPPX Slew rate at XTAL1 3) SRXTAL1 SR 0.3 - - V/ns Maximum 30% difference between rising and falling slew rate OPEN MARKET VERSION

Electrical Specification MHz Oscillator Data Sheet 324 V 1.2, 2021-03 Note: It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits specified by the crystal or ceramic resonator supplier. 3) Square wave input signal for XTAL1. OPEN MARKET VERSION

Electrical Specification Back-up Clock Data Sheet 325 V 1.2, 2021-03

3.10 Back-up Clock

The back-up clock provides an alternative clock source. Table 3-24 Back-up Clock Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Back-up clock accuracy before trimming fBACKUT CC 70 100 130 MHz VEXT≥2.97V Back-up clock accuracy after trimming 1) 1) A short term trimming providing the accuracy required by LIN communication is possible by periodic trimming every 2 ms for temperature and voltage drifts up to temperatures of 125 celcius fBACKT CC 98 100 102 MHz VEXT≥2.97V Standby clock fSB CC 25 70 110 kHz VEXT≥2.97V OPEN MARKET VERSION

Electrical Specification Temperature Sensor Data Sheet 326 V 1.2, 2021-03

3.11 Temperature Sensor

Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Measurement time for each conversion 1) 1) After warm reset tM is not restarted and is measured from last conversion. tM CC - - 2.7 ms Measured from cold power-on reset release Calibration reference accuracy TCALACC CC -1 - 1 °C calibration points @ TJ=-40°C and TJ=127°C Accuracy over temperature range TNL CC -2 - 2 °C TCALACC has to be added in addition DTS temperature range TSR SR -40 - 170 °C Table 3-26 DTS Core Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Measurement time for each conversion 1) 1) After warm reset tM is not restarted and is measured from last conversion. tM CC - - 2.7 ms Measured from cold power-on reset release Temperature difference between on chip temperature sensors ΔT CC -3 - 3 °C Calibration reference accuracy TCALACC CC -2 - 2 °C calibration points @ TJ=-40°C and TJ=127°C Accuracy over temperature range TNL CC -2 - 2 °C TCALACC has to be added in addition DTS temperature range TSR SR -40 - 170 °C OPEN MARKET VERSION

Electrical Specification Power Supply Current Data Sheet 327 V 1.2, 2021-03

3.12 Power Supply Current

The total power supply current defined below consists of leakage and switching components. Application relevant values are typically lower than those given in the following table and depend on the customer's system operating conditions (e.g. thermal connection or used application configurations). The operating conditions for the parameters in the following table are: The real (realistic) power pattern defines the following conditions:

• TJ = 150 °C
• fSRI = fCPUx =3 0 0M H z
• fGTM = 200 MHz
• fSPB = fSTM = fBAUD1 = fBAUD2 = fASCLINx =1 0 0 M H z
• VDD =1 . 2 7 5V
• VDDP3/FLEX =3 . 3 6 6V
• VEXT / EVRSB = VDDM =5 . 1V
• all cores are active inclu ding two lockstep cores
• the following periphe rals are inactive: HSM, HSCT, Ethernet, PSI5, I2C, FCE, and MTU Table 3-27 Current Consumption Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. ∑ Sum of IDD core and peripheral supply currents (incl. IDDPORST+ ∑ IDDCx0+ ∑ IDDCxx+ IDDGTM+IDDSB) IDDRAIL CC - - 1100 mA max power pattern - - 840 mA real power pattern IDD core current during active power-on reset (PORST pin held low). Leakage current of core domain. 1) IDDPORST CC - - 160 mA VDD = 1.275V; TJ=125°C - - 290 mA VDD = 1.275V; TJ=150°C - - 350 mA VDD = 1.275V; TJ=160°C - - 380 mA VDD = 1.275V; TJ=165°C ∑ Sum of IDDP3 3.3 V supply currents IDDP3RAIL CC - - 50 mA max power pattern incl. Flash read current and Dflash programming current. --4 0 2) mA real power pattern incl. Flash read current and Dflash programming current. ∑ Sum of external IEXT supply currents (incl. IEXTFLEX+IEVRSB+IEXTLVDS) IEXTRAIL CC - - 56 mA max power pattern - - 50 mA real power pattern OPEN MARKET VERSION

Electrical Specification Power Supply Current Data Sheet 328 V 1.2, 2021-03 IEXT and IFLEX supply current IEXTFLEX CC - - 18 3) mA real power pattern with port activity absent; PORST output inactive. IEVRSB supply current 1) IEVRSB CC - - 8 mA real power pattern; PMS/EVR module current considered without SCR and Standby RAM during RUN mode. ∑ Sum of external IDDM supply currents (incl. IDDMEVADC+IDDMEDSADC) IDDM CC - - 48 mA real power pattern; sum of currents of EDSADC and EVADC modules ∑ Sum of all currents (incl. IEXTRAIL+IDDMRAIL+IDDx3RAIL+IDD) IDDTOT CC - - 978 mA real power pattern; TJ=150°C ∑ Sum of all currents with DC- DC EVRC regulator active 4) IDDTOTDC3 CC - - 580 mA real power pattern; EVRC reset settings with 72% efficiency; VEXT = 3.3V; TJ=150°C ∑ Sum of all currents with DC- DC EVRC regulator active 4) IDDTOTDC5 CC - - 440 mA real power pattern; EVRC reset settings with 72% efficiency; VEXT = 5V; TJ=150°C ∑ Sum of all currents (SLEEP mode) 1) ISLEEP CC - - 27 mA All CPUs in idle, All peripherals in sleep, fSRI/SPB = 1 MHz via LPDIV divider; TJ = 25°C ∑ Sum of all currents (STANDBY mode) drawn at VEVRSB supply pin 5) ISTANDBY CC - - 130 6) µA 32 kB Standby RAM block active. SCR inactive. Power to remaining domains switched off. TJ = 25°C; VEVRSB = 5V Maximum power dissipation 7) PD SR - - 2400 mW max power pattern - - 1700 mW real power pattern 1) Limits are defined for real power pattern ( VDD=1.275V). For max power pattern limit has to be multiplied by the factor 1.22. 2) Realistic Pflash read pattern with 50% Pflash bandwidth utlilization and a code mix of 50% 0s and 50% 1s. A common decoupling capacitor of atleast 100nF for (VDDP3) is used. Continuous Dflash programming in burst mode with 3.3 V supply and realistic Pflash read access in parallel. Erase currents of the corresponding flash modules are less than the respective programming currents at VDDP3 pin. Programming and erasing flash may generate transient current spikes of up to 45 mA / 20 ns which are handled by the decoupling and buffer capacitors. This parameter is relevant for external power supply dimensioning and not for thermal considerations. 3) The current consumption inclu des only minimal port activity. Table 3-27 Current Consumption (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Power Supply Current Data Sheet 329 V 1.2, 2021-03 4) The total current drawn from e xternal regulator is estimated with 72% EVRC SMPS regulator efficiency. IDDTOTDCx is calculated from IDDTOT using the scaled core current [(IDD x VDD)/(VinxEfficiency)] and constitutes all other rail currents and IDDM. 5) The same current limits apply also for the other power pattern. 6) ∑ Sum of all currents during RUN mode at VEVRSB supply pin is less than (IEVRSB + 4 mA Standby RAM current + ISCRSB if SCR active). ∑ It is recommended to have atleast 100 nF decoupling capacitor at this pin. 32kB of Standby SRAM contributes less than 10uA to ISTANDBY current. 7) The values are only valid if all supplies are applied from external and do not contain the power losses of EVR33 and EVRC. Table 3-28 Module Current Consumption Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. IDDP3 supply current for programming of a Pflash or Dflash bank 1) IDDP3PROG CC - - 25 mA Pflash 3.3V programming current adder when using external 3.3V supply. --9 2) mA Pflash 3.3V programming current adder when using external 5V supply. IEXT supply current added by LVDS pads in LVDS mode 1) IEXTLVDS CC - - 9 mA real power pattern; 6 pairs of LVDS pins active with receive function - - 24 mA real power pattern; 6 pairs of LVDS pins active with transmit function OPEN MARKET VERSION

Electrical Specification Power Supply Current Data Sheet 330 V 1.2, 2021-03 ∑ Sum of external IDDM supply currents (incl. IDDMEVADC+IDDMEDSADC) IDDM CC - - 32 mA real power pattern; current for EDSADC modules only and EVADC modules are inactive; 8 EDSADC channels active continuously. --4 5 3) mA max power pattern; current for EDSADC modules only and EVADC modules are inactive; all EDSADC channels active continuously. - - 16 mA real power pattern; current for EVADC modules only and EDSADC modules are inactive; 12 EVADC modules active. --2 0 4) mA max power pattern; current for EVADC modules only and EDSADC modules are inactive; all EVADC modules active. IDDP3 supply current for erasing of a Pflash or Dflash bank IDDP3ERASE CC - - 25 mA Pflash 3.3V erasing current adder when using external 3.3V supply. SCR 8-bit Standby Controller current incl. PMS in STANDBY Mode drawn at VEVRSB supply pin ISCRSB CC - - 7 5) mA SCR power pattern incl. PMS current consumption with fback clock active; fSYS_SCR = 20MHz; TJ=150°C - 0.150 - mA SCR power pattern incl. PMS current consumption with fback inactive; fSYS_SCR = 70kHz; TJ=25°C SCR 8-bit Standby Controller CPU in IDLE mode 6) ISCRIDLE CC - - 3.5 mA real power pattern. CPU set into idle mode. 1) The same current limits apply also for the other power pattern. 2) During Pflash programming at 5V , additional 3 mA is drawn at VEXT supply rail. 3) A single DS channel in stance consumes 4 mA. Table 3-28 Module Current Consumption (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Power Supply Current Data Sheet 331 V 1.2, 2021-03 3.12.1 Calculating the 1.25 V Current Consumption The current consumption of the 1.25 V rail is composed of two parts:

• Static curren t consumption
• Dynamic current consumption 4) A single VADC unit consumes 1.3 mA. 5) If SCR ADCOMP is activated, an additional 0.6 mA adder is to be considered. 6) Limits are defined for real power pattern ( VDD=1.275V). For max power pattern limit has to be multiplied by the factor 1.22. Table 3-29 Module Core Current Consumption Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. IDD core current of CPUx main core with CPUx lockstep core inactive IDDCx0 CC - - 70 mA max power pattern; IPC=1.2 - - 45 mA real power pattern; IPC=0.6 IDD core current of CPUx main core with CPUx lockstep core active IDDCxx CC - - IDDCx0 + mA max power pattern; IPC=1.2 -- IDDCx0 + mA real power pattern; IPC=0.6 IDD core current added by GTM IDDGTM CC - - 125 mA max power pattern - - 100 mA real power pattern; TIMx, TOMx, ATOMx , MCSx active. 3 clusters at 200 MHz. - - 50 mA TIMx, TOMx active at 100MHz. ATOMx , MCSx, DPLL inactive. 2 clusters at 100 MHz. IDD core current added by HSM IDDHSM CC - - 20 1) 1) The current consumption inclu des basic HSM activity incl. AES module. mA max power pattern; HSM running at 100MHz. IDD core dynamic current added by LBIST IDDLBIST CC - - 80 2) 2) LBIST is executed either durin g start-up phase or can be triggered by application software. Secondary voltage monitors are inactive during the LBIST execution time (tLBIST). During the start-up phase externally supplied VDD voltage has to be equal or greater than 1.2V (VDD nominal - 4%) for static accuracy. If VDD is supplied internally by EVRC, EVRC takes care not to violate the VDD 1.2V static under voltage limit. mA LBIST Configuration A; 1.2V ≤ VDD IDD core dynamic current added by MBIST IDDMBIST CC - - 200 mA fMBIST = 300MHz; tMBIST < 6ms. MTU Ganging procedure for SRAM test and initialization; VDD = 1.375V. OPEN MARKET VERSION

Electrical Specification Power Supply Infrastructure and Supply Start-up Data Sheet 332 V 1.2, 2021-03 The static current consumption is related to the device tempera ture TJ and the dynamic current consumption depends on the configured clocking frequencies and the software application executed. These two parts need to be added in order to get the rail current consumption. (3.1) (3.2) Equation (3.1) defines the typical static current consumption and Equation (3.2) defines the maximum static current consumption. Both functions are valid for VDD =1 . 2 7 5V .

3.13 Power Supply Infrastru cture and Supply Start-up

Electrical Specification Power Supply Infrastructure and Supply Start-up Data Sheet 333 V 1.2, 2021-03

3.13.1 Supply Ramp-up a nd Ramp-down Behavior

Start-up slew rates for supply rails shall comply to SR (see Table 3-33 Supply Ramp).

3.13.1.1 Single S upply mode (a)

Figure 3-3 Single Supply mode (a) - VEXT (5 V) single supply VEXT = 5 V single supply mode. VDD and VDDP3 are generated internally by the EVRC and EVR33 internal regulators. VEXT (externally supplied) EVRC & EVR33 Ramp-up Phase 0 V 5.0 V VRST5 Firmware ExecutionBasic Supply & Clock Infrastructure User Code Execution 0 V 1.25 V VDD (internally generated by EVRC) VRSTC Primary Reset Threshold 5.5 V 4.5 V 1.375 V Power Ramp-down phase fCPU0 =100MH z default on firmware exit Startup_Diag_2 v 0.3 0 V 3.30 V 3.63 V VRST33 VDDP3 (internally generated by EVR33) Primary Reset Threshold PORST (output driven by PMS) PORST (input driven by external regulator) VLVDRST5 tBP (incl. tEVRstartup) tEVRstartup (incl. tSTR) PORST output deasserted when VDD, VDDP3 and VEXT voltage above respective primary reset thresholds EVR33 is started with a delay after VLVDRST5 level is reached at VEXT & VLVDRSTC level is reached at VDDPD PORST input deasserted by external regulator when all input voltages have reached their minimum operational level EVR33_tSTR EVRC_tSTR Primary cold PORST Reset T hreshold LVD Reset release HWCFG[1,2] latch VDDPPA LVD Reset Threshold HWCFG[6] latch OPEN MARKET VERSION

Electrical Specification Power Supply Infrastructure and Supply Start-up Data Sheet 334 V 1.2, 2021-03

• The rate at which current is dr awn from the external regulator (dIEXT /dt) is limited during the basic infrastructure and EVRx regulator start-up phase (T0 up to T2) to a maximum of 100 mA with 100 us settling time. Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent the specification.
• Furthermore it is also ensured that the current drawn from the regulator (dIDD/dt) is limited during the Firmware start-up phase (T3 up to T4) to a maximum of 100 mA with 100 us settling time.
• PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
• PORST (input) active means that t he reset is held active by external agents by pulling the PORST pin low. It is recommended to keep the PORST (input) asserted until the external supply is above the respective primary reset threshold.
• PORST (output) active means that µ C asserts the reset internally and drives the PORST pin low thus propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the basic supply and clock infrastructure is available. During reset release at T3, the load jump of up to 150 mA (dIDD) is expected.
• The power sequence as shown in Figure 3-3 is enumerated below – T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are available as the external supply ramps up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are available as the external supply ramps up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the HWCFG[2:1,6] pins. These events are initiated after LVD reset release at T1. LVD reset is released the both input voltages VEXT and VEVRSB are above VLVDRST5 and VLVDRSTSB levels correspondingly. Internal pre-regulator VDDPD output voltage is above VLVDRSTC level. – T2 refers to the point in time where consequently a soft start of EVRC and EVR33 regulators are initiated. PORST (input) does not have any affect on EVR33 or EVRC output and regulators continue to generate the respective voltages though PORST is asserted and the device is in reset state. The generated voltage follows a soft ramp-up over the tSTR (datasheet parameter) time to avoid overshoots. – T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5, VRST33 and VRSTC supply voltage levels. EVRC and EVR33 regulators have ramped up. PORST (output) is de-asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU. Firmware execution is initiated. The time between T1 and T3 is documented as tEVRstartup (datasheet parameter). – T4 refers to the point in time when Firmware execution is comp leted and User code execution starts with CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet parameter). – T5 refers to the point in time during the ramp-down phase when at least one of the externally provided or generated supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset thresholds. OPEN MARKET VERSION

Electrical Specification Power Supply Infrastructure and Supply Start-up Data Sheet 335 V 1.2, 2021-03

3.13.1.2 Single S upply mode (e)

Figure 3-4 Single Supply mode (e) - (VEXT & VDDP3) 3.3 V single supply VEXT = VDDP3 = 3.3 V single supply mode. VDD is generated internally by the EVRC regulator.

• The rate at which current is drawn from the external regulator (dIEXT /dt) is limited in the Start-up phase to a maximum of 100 mA with 100 us settling time. Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent the specification.
• PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
• PORST (input) active means that t he reset is held active by external agents by pulling the PORST pin low. It is recommended to keep the PORST (input) asserted until the external supply is above the respective primary reset threshold.
• PORST (output) active means that µ C asserts the reset internally and drives the PORST pin low thus propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the EVRC Ramp-up Phase 0 4 Firmware ExecutionBasic Supply & Clock Infrastructure User Code Execution 0 V 1.25 V VDD (internally generated by EVRC) VRSTC Primary Reset Threshold 1.375 V Power Ramp-down phase fCPU0 =100MHz default on firmware exit Startup_Diag_4 v 0.3 POR ST (output driven by PMS) PORST (input driven by external regulator) 0 V 3.30 V 3.63 V VRST5/ VRST33 VEXT/VDDP3 (exter nally supplied) VLVDRST5 tBP (incl. tEVRstartup) tEVRstartup (incl. tSTR) PORST output deasserted when VDD, VDDP3 and VEXT voltage above respective primary reset thresholds EVRC is started with a delay after VLVDRST5 level is reached at VEXT & VLVDRSTC level is reached at VDDPD PORST input deasserted by external regulator when all input voltages have reached their minimum operational level EVRC_tSTR Primary cold PORST Reset T hreshold LVD Reset release HWCFG[1,2] latch VDDPPA LVD Reset Threshold HWCFG[6] latch OPEN MARKET VERSION

Electrical Specification Power Supply Infrastructure and Supply Start-up Data Sheet 336 V 1.2, 2021-03 basic supply and clock infrastructure is available. During reset release at T3, the load jump of upto 150 mA (dIDD) is expected.

• The power sequence as shown in Figure 3-4 is enumerated below – T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are available as the external supply ramps up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are available as the external supply ramps up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the HWCFG[2:1,6] pins. These events are initiated after LVD reset release at T1. LVD reset is released the both input voltages VEXT and VEVRSB are above VLVDRST5 and VLVDRSTSB levels correspondingly. Internal pre-regulator VDDPD output voltage is above VLVDRSTC level. – T2 refers to the point in time where consequently a soft start of EVRC regulator is initiated. PORST (input) does not have any affect on EVRC output and regulators continue to generate the respective voltages though PORST is asserted and the device is in reset state. The generated voltage follows a soft ramp-up over the tSTR (datasheet parameter) time to avoid overshoots. – T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5, VRST33 and VRSTC supply voltage levels. EVRC regulator has ramped up. PORST (output) is de- asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU. Firmware execution is initiated. The time between T1 and T3 is documented as tEVRstartup (datasheet parameter). – T4 refers to the point in time when Firmware execution is comp leted and User code execution starts with CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet parameter). – T5 refers to the point in time during the ramp-down phase when at least one of the externally provided or generated supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset thresholds. OPEN MARKET VERSION

Electrical Specification Power Supply Infrastructure and Supply Start-up Data Sheet 337 V 1.2, 2021-03

3.13.1.3 External Supply mode (d)

Figure 3-5 External Supply mode (d) - VEXT and VDD externally supplied VEXT = 5 V and VDD supplies are externally supplied. 3.3V is generated internally by the EVR33 regulator.

• External supplies VEXT and VDD may ramp-up or ramp-down indepe ndent of each other with regards to start, rise and fall time(s). Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent the specification. It is expected that during start-up, VEXT ramps up before VDD rail. If VDD voltage VEXT (externally supplied) EVR33 Ramp-up Phase PORST (output driven by PMS) 0 V 5.0 V VRST5 Primary cold PORST Reset T hreshold Firmware ExecutionBasic Supply & Clock Infrastructure PORST (input driven by external regulator) User Code Execution 0 V 1.25 V VDD (externally supplied) VRSTC Primary Reset Threshold 5.5 V 4.5 V 1.375 V Power Ramp-down phase fCPU0 =100MH z defaul t on firmware exit Startup_Diag_1 v 0.3 0 V 3.30 V 3.63 V VRST33 VDDP3 (internally generated by EVR33) Primary Reset Threshold LVD Reset release HWCFG[1,2] latch VLVDRST5 tBP (incl. tEVRstartup) tEVRstartup (incl. tSTR) PORST output deasserted when VDD, VDDP3 and VEXT voltage above respective primary reset thresholds EVR33 is started with a delay after VLVDRST5 level is reached at VEXT & VLVDRSTC level is reached at VDDPD PORST input deasserted by external regulator when all input voltages have reached their minimum operational level EVR33_tSTR VDDPPA LVD Reset Threshold HWCFG[6] latch OPEN MARKET VERSION

Electrical Specification Power Supply Infrastructure and Supply Start-up Data Sheet 338 V 1.2, 2021-03 rail is ramped up before VEXT; VDD supply overshoots during start-up shall be limited within the operational voltage range.

• The rate at which current is drawn from the external regulator (dIEXT /dt or dIDD /dt) is limited in the Start-up phase to a maximum of 100 mA with 100 us settling time.
• PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
• PORST (input) active means that t he reset is held active by external agents by pulling the PORST pin low. It is recommended to keep the PORST (input) asserted until all the external supplies are above their primary reset thresholds.
• PORST (output) active means that µ C asserts the reset internally and drives the PORST pin low thus propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the basic supply and clock infrastructure is available. During reset release at T3, the load jump of upto 150 mA (dIDD) is expected.
• The power sequence as shown in Figure 3-5 is enumerated below – T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are available as the external supply ramps up. The bandgap and internal clock sources are started. The supply mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are available as the external supply ramps up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the HWCFG[2:1,6] pins. These events are initiated after LVD reset release at T1. LVD reset is released the both input voltages VEXT and VEVRSB are above VLVDRST5 and VLVDRSTSB levels correspondingly. Internal pre-regulator VDDPD output voltage is above VLVDRSTC level. – T2 refers to the point in time where consequently a soft start of EVR33 regulator is initiated. PORST (input) does not have any affect on EVR33 output and regulators continue to generate the respective voltages though PORST is asserted and the device is in reset state. The generated voltage follows a soft ramp-up over the tSTR (datasheet parameter) time to avoid overshoots. – T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5, VRST33 and VRSTC supply voltage levels. EVR33 regulators has ramped up. PORST (output) is de- asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU. Firmware execution is initiated. The time between T1 and T3 is documented as tEVRstartup (datasheet parameter). – T4 refers to the point in time when Firmware execution is comp leted and User code execution starts with CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet parameter). – T5 refers to the point in time during the ramp-down phase when at least one of the externally provided or generated supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset thresholds. OPEN MARKET VERSION

Electrical Specification Power Supply Infrastructure and Supply Start-up Data Sheet 339 V 1.2, 2021-03

3.13.1.4 External Supply mode (h)

Figure 3-6 External Supply mode (h) - VEXT, VDDP3 & VDD externally supplied All supplies, namely VEXT, VDDP3& VDD are externally supplied.

• External supplies VEXT, VDDP3 & VDD may ramp-up or ramp-down independent of each other with regards to start, rise and fall time(s). Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent the specification. It is expected that during start-up, VEXT ramps up before VDDP3 and VDD rails. If smaller voltage rails are ramped up before VEXT; VDD and VDDP3 supply overshoots during start-up shall be limited within the operational voltage ranges of the respective rails. VEXT (externally supplied) 0 V 5.0 V VRST5 Firmware ExecutionBasic Supply & Clock Infrastructure User Code Execution 0 V 1.25 V VDD (externally supplied) VRSTC Primary Reset Threshold 5.5 V 4.5 V 1.375 V Power Ramp-down phase fCPU0 =100MHz default on firmware exit Startup_Diag_3 v 0.4 0 V 3.30 V 3.63 V VRST33 VDDP3 (externally supplied) Primary Reset Threshold PORST (input driven by external regulator) PORST (output driven by PMS) tPOA time to ensure adequate time between reset releases VLVDRST5 tBP PORST output deasserted when VDD, VDDP3 and VEXT voltage above respective primary reset thresholds Primary cold PORST Reset Threshold LVD Reset release HWCFG[1,2] latch VDDPPA LVD Reset Threshold HWCFG[6] latch OPEN MARKET VERSION

Electrical Specification Power Supply Infrastructure and Supply Start-up Data Sheet 340 V 1.2, 2021-03

• The rate at which current is drawn from the external regulator (dIEXT /dt, dIDD /dt or dIDDP3 /dt) is limited in the Start-up phase to a maximum of 100 mA with 100 us settling time.
• PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
• PORST (input) active means that t he reset is held active by external agents by pulling the PORST pin low. It is recommended to keep the PORST (input) asserted until all the external supplies are above their primary reset thresholds.
• PORST (output) active means that µ C asserts the reset internally and drives the PORST pin low thus propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the basic supply and clock infrastructure is available. During reset release at T3, the load jump of upto 150 mA (dIDD) is expected.
• The power sequence as shown in Figure 3-6 is enumerated below – T1 up to T3 refers to the period in time when basic supply and clock infrastructure components are available as the external supply ramps up. The bandgap and internal clock sources are started. The supply mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are available as the external supply ramps up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the HWCFG[2:1,6] pins. These events are initiated after LVD reset release at T1. LVD reset is released the both input voltages VEXT and VEVRSB are above VLVDRST5 and VLVDRSTSB levels correspondingly. Internal pre-regulator VDDPD output voltage is above VLVDRSTC level. – T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5, VRST33 and VRSTC supply voltage levels. PORST (output) is de-asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU. Firmware execution is initiated. – T4 refers to the point in time when Firmware execution is comp leted and User code execution starts with CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet parameter). – T5 refers to the point in time during the ramp-down phase when at least one of the externally provided supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset thresholds. OPEN MARKET VERSION

Electrical Specification Reset Timing Data Sheet 341 V 1.2, 2021-03

3.14 Reset Timing

Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Application Reset Boot Time tB CC - - 400 µs operating with max. frequencies, with valid BMI header System Reset Boot Time tBS CC - - 1.1 ms RAM initialization and HSM boot time are not included, with valid BMI header Cold Power on Reset Boot Time tBP CC - - 3.1 ms dVEXT/dT=1V/ms. VEXT>VLVDRST5. Boot time after Cold PORST including EVR ramp-up and Firmware execution time; RAM initialization and HSM boot time are not included. - - 1.6 ms Firmware execution time after PORST release without EVR ramp-up; RAM initialization and HSM boot time is not included Minimum cold PORST reset hold time in case of power fail event issued by EVR primary monitors tEVRPOR CC 10 2) - - µ s PMS Infrastructure, EVRC and EVR33 overall start-up time till cold PORST reset release tEVRstartup CC --1 m s dV/dT=1V/ms. EVRC and EVR33 active Minimum PORST active hold time externally after power supplies are stable at operating levels after start-up tPOA SR 1 3) - - m s Configurable PORST digital filter delay in addition to analog pad filter delay tPORSTDF CC 600 - 1200 ns Warm Reset Sequencing Delay tWARMRSTSEQ CC - - 180 µs HWCFG pins hold time from ESR0 rising edge tHDH CC 16 / fSPB - - n s OPEN MARKET VERSION

Electrical Specification Reset Timing Data Sheet 342 V 1.2, 2021-03 HWCFG pins setup time to ESR0 rising edge tHDS CC 0 - - ns Ports inactive after ESR0 reset active tPI CC 8000/ fBAC KT - 18000/ fBA CKT s Ports inactive after PORST reset active tPIP CC - - 150 ns Hold time from PORST rising edge tPOH SR 150 - - ns Setup time to PORST rising edge tPOS SR 0 - - ns Warm PORST reset boot time tBWP CC - - 1.3 ms without RAM initalization LBIST execution time extending the boot time tLBIST CC - - 6 ms LBIST Configuration A; 1.2V ≤ VDD SCR reset boot time tSCR CC - - 5 µs User Mode 0 - - 16 µs User Mode 1 - 13.3 - µs WDT double bit ECC, soft reset Minimum external supplies hold time after warm reset assertion tSUPHOLD CC - - 250 µs external supplies are VEVRSB, VEXT, VFLEX, VDDM, VDDP3 and VDD 1) RAM initialization add 500µs in addition. 2) Cold PORST reset is driven b y uC and maintained in an extended voltage range between VDDPPA limit and absolute maximum rating VEXT/VEVRSB voltage limits. 3) The reset release on supply ra mp-up or supply restoration is delayed by a voltage hysteresis of 1.5% (default value) above the undervoltage reset limit implemented on VEXT, VDDP3 and VDD rails. This mechanism helps to avoid multiple consecutive cold PORST events during slow supply ramp-ups owing to voltage drop/current jumps when reset is released. Table 3-30 Reset (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Reset Timing Data Sheet 343 V 1.2, 2021-03 Figure 3-7 Power, Pad and Reset Timing reset_beh_aurix VDDP PORST Pads Pad- state undefined VDD VDDPPA VDDPPA Pad- state undefined VDDPR Programmed Z / HTristate Z / pullup H tPOA tPOA HWCFG ESR 0 tPI P Z / H Cold Warm tHDH TESTMODE tPOS tPOH tPOS tPOHTRST t PI Programmed Programmed tPI power -on config tHDA tHDH config tHDA tHDH config OPEN MARKET VERSION

Electrical Specification PMS Data Sheet 344 V 1.2, 2021-03

3.15 PMS

Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Input voltage range VIN SR 3.60 1) - 5.50 V Normal RUN mode 2.97 2) - 5.50 V Low voltage cranking mode Output voltage operational range including load/line regulation and aging 3) VOUT CC 2.97 3.3 3.63 V Normal RUN mode 2.60 3.3 3.63 V Low voltage cranking mode; IDDP3=50mA Output VDDx3 static voltage accuracy after trimming and aging without dynamic load/line regulation. VOUTT CC 3.225 3.3 3.375 V Normal RUN mode 2.78 3.3 3.375 V Low voltage cranking mode; IDDP3=50mA Output buffer capacitance on VOUT COUT SR 1.45 2.2 3 µF Output buffer capacitor ESR COUTESR SR - - 100 4) mOhm f > 0.5MHz; f < 10MHz Maximum output current of the regulator IMAX CC 60 5) - - mA Normal RUN mode Startup time tSTR CC - 500 1000 µs Normal RUN mode External VIN supply ramp 6) dVin/dt SR - 1 - V/ms Ripple on Output Voltage Δ VOUTTC CC - - 33 mV VEXT ≥ 2.97V ; VEXT ≤ 5.5V ; IOUTTC ≥ 10mA ; IOUTTC ≤ 60mA; ΔVOUTTC = (peak to peak ripple / 2) Load step response 7) dVout/dIout CC -165 - - mV Normal RUN mode; dI=10 to 60mA; dt=20ns; Tsettle=20us - - 165 mV Normal RUN mode; dI=60 to 10mA; dt=20ns; Tsettle=20us -180 - - mV Low voltage cranking mode; dI=10 to 50 mA; dt=20ns; Tsettle=20us - - 180 mV Low voltage cranking mode; dI=50 to 10mA; dt=20ns; Tsettle=20us OPEN MARKET VERSION

Electrical Specification PMS Data Sheet 345 V 1.2, 2021-03 Line step response dVout/dVin CC --4 0 m V dVin/dT=1V/ms; dV= 3.6 to 5V; IMAX=60mA; ΔVOUTTC is included -40 - - mV dVin/dT=1V/ms; dV= 5 to 3.6V; IMAX=60mA; ΔVOUTTC is included - - 280 mV dVin/dT=50V/ms; dV= 3.6 to 5V; IMAX=60mA -165 - - mV dVin/dT=50V/ms; dV= 5 to 3.6V; IMAX=60mA 1) A maximum pass device dropout voltage of 300mV is included in the minimum input voltage to ensure optimal pass device performance during normal operation. 2) VEXT Input voltage drop up to 2 .97V leading to VDDP3 output voltage drop upto 2.6V can be tolerated if Flash is switched before to low performance mode. 3) No external inductive load permissible if EVR33 is used. 4) It is also recommended that the resistance of the supply trace from the pin to the EVR output capacitor is less than 100 mOhm. An additional decoupling capacitor of 100nF shall be located close to the pin before Cout. 5) IMAX is limited to 40 mA incase of Low voltage mode (cranking case) with on chip pass devices. In case EVR33 is not used, Injection current into 3.3V VDDP3 supply rail with active sink on 5V VEXT rail should be limited to 500 mA if during power sequencing 3.3V is supplied before 5V by external regulator. 6) EVR is robust against residual voltage ramp-up starting between 0 - 2.97 V. A VEXT voltage ramp range between 0.5V/min upto 120V/ms is covered in robustness validation. The generated voltage itself follows a soft ramp-up over the tSTR time to avoid overshoots. 7) Settling time is defined until output voltage is within +-1% of the mean(VOUTT) of the individual device. Table 3-32 Supply Monitors Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Primary Undervoltage Reset threshold for VDDP3 before trimming 1) VRST33 CC - - 3.00 V by reset release before EVR trimming on supply ramp-up Primary undervoltage reset threshold for VDD before trimming VRSTC CC - - 1.138 V by reset release before trimming on supply ramp-up including 2 LSB voltage Hysteresis VEXT primary undervoltage monitor accuracy after trimming VEXTPRIUV CC 2.86 2.92 2.97 V VEXT = Undervoltage cold PORST Primary Monitor Threshold VDDP3 primary undervoltage monitor accuracy after trimming VDDP3PRIUV CC 2.86 3) 2.90 2.97 V VDDP3 = Undervoltage cold PORST Primary Monitor Threshold VDD primary undervoltage monitor accuracy after trimming VDDPRIUV CC 1.08 3) 1.105 1.125 V VDD = Undervoltage cold PORST Primary Monitor Threshold Table 3-31 EVR33 LDO (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification PMS Data Sheet 346 V 1.2, 2021-03 EVR primary monitor measurement latency for a new supply value tPRIUV CC - - 300 ns The supply ramp / line jump slope is limited to 50V/ms for VEXT, VDDP3 and VDD rails. VEXT, VDDM & VEVRSB secondary supply monitor accuracy after trimming 4) 5) VEXTMON CC 3.2 3.3 3.4 V SWDxxVAL, VDDMxxVAL & SBxxVAL monitoring threshold=3.3V=90h(O V,UV). EVRMONFILT.SWDFI L=1. 4.5 4.6 4.7 V SWDxxVAL, VDDMxxVAL & SBxxVAL monitoring threshold=4.6V=C8h(U V)/C9h(OV). EVRMONFILT.SWDFI L=1 5.3 5.4 5.5 V SWDxxVAL, VDDMxxVAL & SBxxVAL monitoring threshold=5.4V=EAh(U V)/ECh(OV). EVRMONFILT.SWDFI L=1 4.9 5.0 5.1 V SWDxxVAL, VDDMxxVAL & SBxxVAL monitoring threshold=5V=D9h(UV) /DAh(OV). EVRMONFILT.SWDFI L=1 Table 3-32 Supply Monitors (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification PMS Data Sheet 347 V 1.2, 2021-03 VDDP3 secondary supply monitor accuracy after trimming 5) VDDP3MON CC 2.97 3.035 3.1 V EVR33xxVAL monitoring threshold=3.035V=CBh (UV)/CCh(OV). EVRMONFILT.EVR33 FIL = 3. 3.235 3.30 3.365 V EVR33xxVAL monitoring threshold=3.3V=DDh( OV,UV). EVRMONFILT.EVR33 FIL = 3. 3.5 3.565 3.63 V EVR33xxVAL monitoring threshold=3.565V=EEh (UV)/EFh(OV). EVRMONFILT.EVR33 FIL = 3. VDD & VDDPD secondary supply monitor accuracy after trimming VDDMON CC 1.125 1.15 1.175 V EVRCxxVAL & PRExxVAL monitoring threshold=1.15V=C7h( UV)/C8h(OV). EVRMONFILT.EVRCFI L = 1. 1.225 1.25 1.275 V EVRCxxVAL & PRExxVAL monitoring threshold=1.25V=D9h( OV,UV). EVRMONFILT.EVRCFI L = 1. 1.325 1.35 1.375 V EVRCxxVAL & PRExxVAL monitoring threshold=1.35V=EAh( UV)/EBh(OV). EVRMONFILT.EVRCFI L = 1. VEXT LVD Primary undervoltage reset Monitor threshold VLVDRST5 CC 2.3 - 2.72 V Power-down 2.4 - 2.75 V Power-up VEVRSB LVD Primary undervoltage reset Monitor threshold VLVDRSTSB CC 2.18 - 2.47 V Power-down 2.21 - 2.5 V Power-up VEXT and VEVRSB PBIST primary overvoltage Monitor threshold VPBIST5 CC 5.63 - - V Table 3-32 Supply Monitors (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification PMS Data Sheet 348 V 1.2, 2021-03

• Up to 1000000 power-cycles, matc hing the limits defined in the table ’Supply Ramp’ are allowed for TC38x, without any restriction to reliability. Primary undervoltage reset threshold for VEXT before trimming VRST5 CC - - 3.0 V by last cold PORST release on supply ramp-up including voltage hysteresis. EVR secondary monitor measurement latency for all 6 supply rails tMON CC - - 3.2 µs HPOSC and SHPBG bandgap trimmed. Filter inactive. 1) The reset release on supply ram p-up is delayed by a time duration 20-40 us after reaching undervoltage reset threshold and by a voltage hysteresis of 1.5% above the undervoltage reset limit. These mechanisms serve as hysteresis to avoid multiple consecutive cold PORST events during slow supply ramp-ups owing to voltage drop/current jumps when reset is released. The reset limit of 2,97V at pin is for the case with 3.3V generated internally from EVR33. In case the 3.3V supply is provided externally, the bondwire drop will cause a reset at a higher voltage of 3.0V at the VDDP3 pin. 2) The monitor tolerances constit ute the inherent variation of the band gap and ADC over process, voltage and temperature operational ranges. The VxxPRIUV parameters are device individually tested in production with +-1% tolerance about the VxxPRIUV limits. All voltages are measured on pins. 3) VRSTxx parameters are relevant only for the first cold PORST release. Later the reset levels are trimmed by the Firmware and reflected as VxxPRIUV parameters before device is used with full performance. The cold PORST is released with a voltage hysteresis on all the primary monitors to avoid consecutive PORST toggling behavior. 4) In case the application is using 3.3V single supply (Single Supply mode (e), i.e. VEXT and VDDP3 are shorted together), it is recommended to use secondary supply monitoring on channel VDDP3, because of the better accuracy of parameter VDDP3MON. 5) To monitor voltage level not p rovided in conditions the values for OV and UV thresholds can be generated by a linear interpolation or extrapolation based on the given points. Table 3-33 Supply Ramp Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. External VEXT & VEVRSB supply ramp-up and ramp-down slope 1) 2) 3) 1) The device is robust against residual voltage ramp-up starting between 0 - 2.97 V for VEXT, VEVRSB, VDDP3 and VDDM and 0-1 V for VDD. A voltage ramp range between 0.5V/min upto 120V/ms is covered in robustness validation. 2) Also valid in case EVR33 or EVRC is used. The generated voltage itself follows a soft ramp-up over the tSTR time to avoid overshoots. 3) The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent the specification. dVEXT/dt SR 8.3E-6 1 100 V/ms External VDDP3 supply ramp-up and ramp-down slope 1)3) dVDDP3/dt SR 8.3E-6 1 100 V/ms External VDD supply ramp-up and ramp-down slope 1)3) dVDD/dt SR 8.3E-6 1 100 V/ms External VDDM supply ramp-up and ramp-down slope 1)3) dVDDM/dt SR 8.3E-6 1 100 V/ms Table 3-32 Supply Monitors (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification PMS Data Sheet 349 V 1.2, 2021-03 Table 3-34 EVRC SMPS Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Input VEXT Voltage range VIN SR 2.97 - 5.5 V Start-up VEXT voltage > 2.6 V SMPS regulator output voltage range including load/line regulation and aging VDDDC CC 1.125 - 1.375 V VEXT ≥ 2.97V ; VEXT ≤ 5.5V ; IDDDC ≥ 1mA ; IDDDC ≤ 1.5A ; untrimmed SMPS regulator static voltage output accuracy after trimming without dynamic load/line regulation. VDDDCT CC 1.225 1.25 1.275 V VEXT ≥ 2.97V ; VEXT ≤ 5.5V ; IDDDC ≥ 1mA ; IDDDC ≤ 1.5A Programmable switching frequency fDCDC SR 1.6 1.82 2.0 MHz Start-up frequency switches from 500 KHz in open loop operation to 1.82 MHz in closed loop Operation. - 0.8 - MHz Start-up frequency switches from 500 KHz in open loop operation to 1.82 MHz in closed loop Operation. 0.8 MHz to be set in SW. Startup time tSTRDC CC - - 900 µs SMPS Start-up Mode. It is is defined beween VEXTPRIUV reset threshold till PORST release, on condition that all other PORST requirements were released before. ISTART < 700mA. Switching frequency modulation spread ΔfDCSPR CC - 1.8% - MHz Maximum ripple at IMAX Δ VDDDC CC - - 16 mV VEXT ≥ 2.97V ; VEXT ≤ 5.5V ; IDDDC ≥ 300mA ; IDDDC ≤ 1.5A ; ΔVDDDC = (Peak to Peak ripple / 2) No load current consumption of SMPS regulator IDCNL CC - 15 19 mA fDCDC=1.82MHz; IDDDC=ISLEEP; VEXT >

2.97 V; TJ=25°C

-5 -m A L P M m o d e ; IDDDC=ISLEEP; VEXT >

Electrical Specification PMS Data Sheet 350 V 1.2, 2021-03 SMPS regulator load transient response dVDDDCT / dlOUT CC -50 - 87 mV dI < -450mA ; IDDDC=500-1500mA; tr=0.1us; tf=0.1us; VDDDC=1.25V; Tsettle=100 us -100 - 145 mV dI < -700mA ; IDDDC=750-1500mA; tr=0.1us; tf=0.1us; VDDDC=1.25V; Tsettle=100 us -26 - 26 mV dI < 100mA ; IDDDC=50- 1500mA; tr=0.1us; tf=0.1us; VDDDC=1.25V; Tsettle=20us; Maximum output current IMAX CC 100 - - mA LPM mode. Typical current in LPM Mode = ISLEEP 1.5 - - A limited by thermal constraints and component choice SMPS regulator line transient response dVDDDCT / dVIN CC -75 - 75 mV dV/dT=120V/ms; dV < 2.97 - 5.5V ; IDDDC=50- 1500mA; -12.5 - 12.5 mV dV/dT=1V/ms; dV < 2.97 - 5.5V ; IDDDC=50- 1500mA; SMPS regulator efficiency nDC CC - 80 - % VIN=3.3V; IDDDC=1500mA; fDCDC=1.82MHz -7 5 -% VIN=5V; IDDDC=1500mA; fDCDC=1.82MHz Input Synchronisation frequency fDCDCSYNC SR 1.6 1.82 2.0 MHz Table 3-35 EVRC SMPS External components Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. External output capacitor value COUT SR 20.8 32 43.2 µF IDDDC=1.5A; fDDDC = 0.8MHz 15.4 22 29.7 µF IDDDC=1.5A; fDDDC = 1.82MHz Table 3-34 EVRC SMPS (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification PMS Data Sheet 351 V 1.2, 2021-03 External output capacitor ESR COUT_ESR SR - - 50 mOhm f≥0.5MHz ; f≤10MHz - - 100 Ohm f=10Hz External input capacitor value 1) CIN SR 6.5 10 13.5 µF IDDDC=1.5A External input capacitor ESR CIN_ESR SR - - 50 mOhm f≥0.5MHz ; f≤10MHz - - 100 Ohm f=100Hz External inductor value LDC SR 3.29 4.7 6.11 fDCDC=0.8MHz 2.31 3.3 4.29 µH fDCDC=1.82MHz External inductor DCR LDC_DCR SR - - 0.2 Ohm P + N-channel MOSFET logic level VLL SR - - 2.5 V P + N-channel MOSFET drain source breakdown voltage |VBR_DS| SR +7 - - V NMOS - VGS = 0. --- 7 V P M O S - VGS = 0. P + N-channel MOSFET drain source ON-state resistance RON SR - 150 - mOhm IDDDC=1.5A; |VGS|=2.5V ; TA=25°C P + N-channel MOSFET Gate Charge QG SR - - 8 nC IDDDC=1.5A; NMOS- |VGS|=5V; 1.5A pulsed drain current -8 - - nC IDDDC=1.5A; PMOS- |VGS|=5V; 1.5A pulsed drain current External Inductor Saturation Current Margin ΔISAT SR 400 - - mA The saturation current of the coil must be larger than IDDDC + ΔISAT P + N-channel MOSFET Gate threshold voltage VGSTH SR - 1 - V NMOS -- 1 -V P M O S N-channel MOSFET reverse diode forward voltage VRDN SR - 0.8 - V 1) Capacitor min-max range represent typical +-35% tolerance including DC bias effect. The trace resistance from the capacitor to the supply or ground rail should be limited to 25 mOhm. Table 3-35 EVRC SMPS External components (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification System Phase Locked Loop (SYS_PLL) Data Sheet 352 V 1.2, 2021-03

3.16 System Phase Locked Loop (SYS_PLL)

Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the maximum driver and sharp edge. Note: The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz. These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes. Table 3-36 PLL System Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. DCO Input frequency range fREF CC 10 - 40 MHz Modulation Amplitude MA CC 0 - 2 % Peak Period jitter DP CC -200 - 200 ps without modulation (PLL output frequency) Peak Accumulated Jitter DPP CC -5 - 5 ns without modulation Total long term jitter JTOT CC - - 11.5 ns including modulation; MA 1.25%; fREF 20MHz System frequency deviation fSYSD CC - - 0.01 % with active modulation DCO frequency range fDCO CC 400 - 800 MHz PLL lock-in time tL CC 4 - 100 µs OPEN MARKET VERSION

Electrical Specification Peripheral Phase Locked Loop (PER_PLL) Data Sheet 353 V 1.2, 2021-03

3.17 Peripheral Phase Locked Loop (PER_PLL)

Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the maximum driver and sharp edge. Note: The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz. These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes. Table 3-37 PLL Peripheral Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Peak Accumulated jitter at SYSCLK pin DPP CC -1000 - 1000 ps Peak only Peak accumulated jitter DPPI CC -700 - 700 ps Peak only RMS Accumulated jitter DRMS CC -100 - 100 ps measured over 1 µs; fREF = 20 MHz and fDCO = 640 MHz or fREF = 25 MHz and fDCO = 800 MHz Peak Period jitter DP CC -200 - 200 ps fDCO = 640 MHz or fDCO = 800 MHz

640 MHz

800 MHz

DCO frequency range fDCO CC 400 - 800 MHz DCO input frequency range fREF CC 10 - 40 MHz PLL lock-in time tL CC 4 - 100 µs OPEN MARKET VERSION

Electrical Specification AC Specifications Data Sheet 354 V 1.2, 2021-03

3.18 AC Specifications

All AC parameters are specified for the complete operating range defined in Chapter 3.4 unless otherwise noted in column Note / Test Condition. Unless otherwise noted in the figures the timings are defined with the following guidelines: Figure 3-8 Definition of rise / fall times Figure 3-9 Time Reference Point Definition 10% 90% 10% 90% VSS VEXT/FLEX /V DDP 3 tr rise_fall tf timing _reference VEXT/FLEX /VDDP3 Timing Reference Points VEXT /FLEX /V DDP 3 VSS VEXT/FLEX /V DDP 3 OPEN MARKET VERSION

Electrical Specification JTAG Parameters Data Sheet 355 V 1.2, 2021-03

3.19 JTAG Parameters

The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000. Figure 3-10 Test Clock Timing (TCK) Table 3-38 JTAG Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. TCK clock period t1 SR 50 - - ns TCK high time t2 SR 10 - - ns TCK low time t3 SR 10 - - ns TCK clock rise time t4 SR - - 4 ns TCK clock fall time t5 SR - - 4 ns TDI/TMS setup to TCK rising edge t6 SR 6.0 - - ns TDI/TMS hold after TCK rising edge t7 SR 6.0 - - ns TDO valid after TCK falling edge (propagation delay) t8 CC 3.0 - - ns CL≤20pF --2 5 n s CL≤50pF TDO hold after TCK falling edge t18 CC 2 - - ns TDO high impedance to valid from TCK falling edge t9 CC - - 25 ns CL≤50pF TDO valid output to high impedance from TCK falling edge t10 CC - - 25 ns CL≤50pF MC_JTAG_TCK

0.9 VEXT

0.5 VEXT

0.1 VEXT

Electrical Specification JTAG Parameters Data Sheet 356 V 1.2, 2021-03 Figure 3-11 JTAG Timing t6 t7 t6 t7 t9 t8 t10 TCK TMS TDI TDO MC_JTAG t18 OPEN MARKET VERSION

Electrical Specification DAP Parameters Data Sheet 357 V 1.2, 2021-03

3.20 DAP Parameters

The following parameters are applicable for communication through the DAP debug interface. Table 3-39 DAP Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. DAP0 clock rise time t14 SR - - 1 ns f=160MHz - - 4 ns f=40MHz - - 2 ns f=80MHz DAP0 clock fall time t15 SR - - 1 ns f=160MHz - - 4 ns f=40MHz - - 2 ns f=80MHz DAP1 setup to DAP0 rising edge t16 SR 4 - - ns 5 - - ns f=40MHz DAP1 hold after DAP0 rising edge t17 SR 2 - - ns DAP1 valid per DAP0 clock period t19 CC 4 - - ns CL=20pF ; f=160MHz 8 - - ns CL=20pF ; f=80MHz 10 - - ns CL=50pF ; f=40MHz DAP0 high time t12 SR 2 - - ns DAP0 low time t13 SR 2 - - ns DAP0 clock period t11 SR 6.25 - - ns Table 3-40 SCR DAP Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. DAP0 clock rise time t14 SR - - 8 ns f=20MHz DAP0 clock fall time t15 SR - - 8 ns f=20MHz DAP1 setup to DAP0 rising edge t16 SR 10 - - ns DAP1 hold after DAP0 rising edge t17 SR 10 - - ns DAP1 valid per DAP0 clock period t19 CC 30 - - ns CL=20pF ; f=20MHz DAP0 high time t12 SR 15 - - ns DAP0 low time t13 SR 15 - - ns DAP0 clock period t11 SR 50 - - ns OPEN MARKET VERSION

Electrical Specification DAP Parameters Data Sheet 358 V 1.2, 2021-03 Figure 3-12 DAP Timing Note: The DAP1 and DAP2 device to host timing is individual for both pins. There is no guaranteed max. signal skew. DAP11),2) (Device to Host) (Host to Device) 1) The DAP1 and DAP2 device to host timing is individual for both pins. There is no guaranteed max. signal skew. 2) No explicit setup and hold times are given for DAP1 for the direction Device to Host. Only t11 and t19 are guaranteed and the tool may set the sample point freely. OPEN MARKET VERSION

Electrical Specification ASCLIN SPI Master Timing Data Sheet 359 V 1.2, 2021-03

3.21 ASCLIN SPI Master Timing

This section defines the timings for the ASCLIN in the TC38x. Note: Pad asymmetry is already included in the following timings. Table 3-41 Master Mode strong sharp (ss) output pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. ASCLKO clock period t50 CC 20 - - ns CL=25pF Deviation from ideal duty cycle t500 CC -2 - 2 ns CL=25pF MTSR delay from ASCLKO shifting edge t51 CC -3.5 - 3.5 ns CL=25pF ASLSOn delay from the first ASCLKO edge t510 CC -3 - 3.5 ns CL=25pF MRST setup to ASCLKO latching edge t52 SR 25 - - ns CL=25pF MRST hold from ASCLKO latching edge t53 SR -2 - - ns CL=25pF Table 3-42 Master Mode strong medium (sm) output pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. ASCLKO clock period t50 CC 50 - - ns CL=50pF Deviation from ideal duty cycle t500 CC -5 - 5 ns CL=50pF MTSR delay from ASCLKO shifting edge t51 CC -7 - 7 ns CL=50pF ASLSOn delay from the first ASCLKO edge t510 CC -7 - 7 ns CL=50pF MRST setup to ASCLKO latching edge t52 SR 35 - - ns CL=50pF MRST hold from ASCLKO latching edge t53 SR -5 - - ns CL=50pF Table 3-43 Master Mode medium (m) output pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. ASCLKO clock period t50 CC 160 - - ns CL=50pF Deviation from ideal duty cycle t500 CC -10 - 10 ns CL=50pF MTSR delay from ASCLKO shifting edge t51 CC -20 - 20 ns CL=50pF ASLSOn delay from the first ASCLKO edge t510 CC -20 - 20 ns CL=50pF OPEN MARKET VERSION

Electrical Specification ASCLIN SPI Master Timing Data Sheet 360 V 1.2, 2021-03 Figure 3-13 ASCLIN SPI Master Timing MRST setup to ASCLKO latching edge t52 SR 80 - - ns CL=50pF MRST hold from ASCLKO latching edge t53 SR -15 - - ns CL=50pF Table 3-43 Master Mode medium (m) output pads (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. ASCLIN_TmgMM.vsd ASCLKO MTSR t51 t51 MRST t53 Data valid ASLSO t510 t50 t500 t52 Data valid OPEN MARKET VERSION

Electrical Specification QSPI Timings, Master and Slave Mode Data Sheet 361 V 1.2, 2021-03

3.22 QSPI Timings, Master and Slave Mode

This section defines the timings for the QSPI in the TC38x. It is assumed that SCLKO, MTSR, and SLSO pads have the same pad settings: Note: Pad asymmetry is already included in the following timings. Table 3-44 Master Mode Timing, LVDS output pads for data and clock Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. SCLKO clock period t50 CC 20 1) 1) The load ( CL=25pF) defined in the condition list is a load definition for the single end signal SLSO and does not intend to add an additional load inside the differential signal lines. For single end signals the load definition defines the max length of the signal on the PCB layout. For the LVDS pads the IEEE Std 1596.3-1996 load definitions apply. - - ns CL=25pF Deviation from the ideal duty cycle t500 CC -1 1) -1 1) ns CL=25pF MTSR delay from SCLKO shifting edge t51 CC -3 1) -4 1) ns CL=25pF SLSOn deviation from the ideal programmed position t510 CC -4 1) -5 . 5 1) ns CL=25pF, driver strength ss -10 1) -1 0 1) ns CL=25pF, driver strength sm -30 1) -3 0 1) ns CL=25pF, driver strength m MRST setup to SCLK latching edge t52 SR 18 1) - - ns CL=25pF; valid for LVDS Input pads of QSPI2 only 19.5 1) - - ns CL=25pF; valid for LVDS Input pads of QSPI4 only MRST hold from SCLK latching edge t53 SR -1 1) - - ns CL=25pF; valid for LVDS Input pads only Table 3-45 Master Mode Strong Sharp (ss) output pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. SCLKO clock period t50 CC 50 - - ns CL=25pF Deviation from the ideal duty cycle t500 CC -2 - 2 ns CL=25pF MTSR delay from SCLKO shifting edge t51 CC -4 - 5 ns CL=25pF SLSOn deviation from the ideal programmed position t510 CC -4 - 5 ns CL=25pF MRST setup to SCLK latching edge t52 SR 25 1) 2) - - ns CL=25pF MRST hold from SCLK latching edge t53 SR -2 1)2) - - ns CL=25pF OPEN MARKET VERSION

Electrical Specification QSPI Timings, Master and Slave Mode Data Sheet 362 V 1.2, 2021-03 1) For compensation of the avera ge on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 2) The setup and hold times are va lid for both settings of the input pads thresholds: TTL and AL. Table 3-46 Master Mode Strong Medium (sm) output pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. SCLKO clock period t50 CC 50 - - ns CL=50pF Deviation from the ideal duty cycle t500 CC -5 - 5 ns CL=50pF MTSR delay from SCLKO shifting edge t51 CC -7 - 7 ns CL=50pF SLSOn deviation from the ideal programmed position t510 CC -7 - 7 ns CL=50pF MRST setup to SCLK latching edge t52 SR 35 1) 2) 1) For compensation of the avera ge on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 2) The setup and hold times are va lid for both settings of the input pads thresholds: TTL and AL. - - ns CL=50pF MRST hold from SCLK latching edge t53 SR -5 1)2) - - ns CL=50pF Table 3-47 Master Mode Medium (m) output pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. SCLKO clock period t50 CC 160 - - ns CL=50pF Deviation from the ideal duty cycle t500 CC -10 - 10 ns CL=50pF MTSR delay from SCLKO shifting edge t51 CC -20 - 20 ns CL=50pF SLSOn deviation from the ideal programmed position t510 CC -20 - 20 ns CL=50pF MRST setup to SCLK latching edge t52 SR 80 1) 2) 1) For compensation of the avera ge on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 2) The setup and hold times are va lid for both settings of the input pads thresholds: TTL and AL. - - ns CL=50pF MRST hold from SCLK latching edge t53 SR -15 1)2) - - ns CL=50pF -13 1)2) - - ns CL=50pF; SCR SSC Table 3-48 Slave mode timing Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. SCLK clock period t54 SR 4 x TMAX - - n s SCLK duty cycle t55/t54 SR 40 - 60 % OPEN MARKET VERSION

Electrical Specification QSPI Timings, Master and Slave Mode Data Sheet 363 V 1.2, 2021-03 Figure 3-14 Master Mode Timing MTSR setup to SCLK latching edge t56 SR 6 - - ns Input Level AL 6 - - ns Input Level TTL MTSR hold from SCLK latching edge t57 SR 4 - - ns Input Level AL 6 - - ns Input Level TTL SLSI setup to first SCLK shift edge t58 SR 4 - - ns Input Level AL 6 - - ns Input Level TTL SLSI hold from last SCLK latching edge t59 SR 3 - - ns Input Level AL 6 - - ns Input Level TTL MRST delay from SCLK shift edge t60 CC 5 - 35 ns driver = strong edge = medium ; CL=50pF 2 - 24 ns driver = strong edge = sharp ; CL=50pF 15 - 80 ns medium driver ; CL=50pF 14 - - ns medium driver ; CL=50pF; SCR SSC Table 3-48 Slave mode timing (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. QSPI_TmgMM.vsd SCLK1)2) MTSR1) t51 MRST1) t53 Data valid SLSOn2) 1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0, ECON.B=0 (no sampling point delay). 2) t510 is the deviation from the ideal position configured with the leading delay, BACON.LPRE and BACON.LEAD > 0. t50 t500 t52 Data valid SAMPLING POINT t510

0.5 VEXT/FLEX

Electrical Specification QSPI Timings, Master and Slave Mode Data Sheet 364 V 1.2, 2021-03 Figure 3-15 Slave Mode Timing QSPI_TmgSM.vsd SCLKI1) t55 MTSR1) t57 Data valid t56 SLSI 1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0. t54 t55 t59 Last latching SCLK edge First latching SCLK edge t57 Data valid t56 MRST1) t60 First shift SCLK edge t60 t61 t58

Electrical Specification MSC Timing 5 V Operation Data Sheet 365 V 1.2, 2021-03

3.23 MSC Timing 5 V Operation

The following section defines the timings. Note: Pad asymmetry is already included in the following timings. Note: Load for LVDS pads are defined as differential loads in the following timings. Table 3-49 LVDS clock/data (LVDS pads in LVDS mode) valid for 5V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. FCLPx clock period t40 CC 2 * TA 1) 2) 1) TA depends on the clock source selected for baud rate generation in the ABRA block of the MSC. 2) The capacitive load on the LVDS pins is differential, the cap acitive load on the CMOS pins is single ended. 3) The load ( CL=50pF) defined in the condition list is a load definition for the single end signal EN and does not intend to add an additional load inside the differential signal lines. For single end signals the load definition defines the max length of the signal on the PCB layout. For the LVDS pads the IEEE Std 1596.3-1996 load definitions apply. --n s L V D S ; CL=50pF Deviation from ideal duty cycle t400 CC -1 3) -1 3) ns LVDS; 0 < CL < 50pF SOPx output delay t44 CC -3 3) -3 3) ns CL=50pF ENx output delay t45 CC -4 3) -5 3) ns ss; CL=50pF; ABRA block bypassed -4 3) -4 3) ns ss; CL=50pF; ABRA block used -2 3) -1 0 3) ns sm; CL=50pF -30 3) -3 0 3) ns m; CL=50pF Table 3-50 Strong sharp (ss) driver for clock/data valid for 5V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. FCLPx clock period t40 CC 2 * TA - - ns CL=50pF Deviation from ideal duty cycle t400 CC -2 - 2 ns CL=50pF SOPx output delay t44 CC -4 - 3.5 ns CL=50pF ENx output delay t45 CC -4 - 3.5 ns CL=50pF Table 3-51 Strong medium (sm) driver for clock/data valid for 5V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. FCLPx clock period t40 CC 2 * TA - - ns CL=50pF Deviation from ideal duty cycle t400 CC -5 - 5 ns CL=50pF SOPx output delay t44 CC -7 - 7 ns CL=50pF ENx output delay t45 CC -7 - 7 ns CL=50pF OPEN MARKET VERSION

Electrical Specification MSC Timing 5 V Operation Data Sheet 366 V 1.2, 2021-03 Figure 3-16 MSC Interface Timing Note: The SOP data signal is sampled with the falling edge of FCLP in the target device. Table 3-52 Medium (m) driver for clock/data valid for 5V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. FCLPx clock period t40 CC 2 * TA - - ns CL=50pF Deviation from ideal duty cycle t400 CC -10 - 10 ns CL=50pF SOPx output delay t44 CC -20 - 20 ns CL=50pF ENx output delay t45 CC -20 - 20 ns CL=50pF Table 3-53 Upstream Interface Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. SDI bit time t46 SR 8 * tMSC - - n s SDI rise time t48 SR - - 200 ns SDI fall time t49 SR - - 200 ns MSC_Timing_A.vsd t44 t44 t40 SOP FCLP SDI t46 t48

0.1 VEXT/FLEX

0.9 VEXT/FLEX

Electrical Specification Ethernet Interface (ETH) Characteristics Data Sheet 367 V 1.2, 2021-03

3.24 Ethernet Interface (ETH) Characteristics

3.24.1 ETH Measurement Reference Points

Figure 3-17 ETH Measurement Reference Points ETH_Testpoints.vsd ETH Clock 1.4 V 1.4 V 2.0 V 0.8 V 2.0 V 0.8 V tR tF ETH I/O OPEN MARKET VERSION

Electrical Specification Ethernet Interface (ETH) Characteristics Data Sheet 368 V 1.2, 2021-03

3.24.2 ETH Management Signal Pa rameters (ETH_MDC, ETH_MDIO)

Figure 3-18 ETH Management Signal Timing Table 3-54 ETH Management Signal Parameters valid for 3.3V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. ETH_MDC period t1 CC 400 - - ns CL=25pF ETH_MDC high time t2 CC 160 - - ns CL=25pF ETH_MDC low time t3 CC 160 - - ns CL=25pF ETH_MDIO setup time (output) t4 CC 10 - - ns CL=25pF ETH_MDIO hold time (output) t5 CC 10 - - ns CL=25pF ETH_MDIO data valid (input) t6 SR 0 - 300 ns CL=25pF ETH_Timing-Mgmt.vsd ETH_MDC ETH_MDIO (output ) Valid Data Valid Data ETH_MDIO (input ) ETH_MDC ETH_MDIO sourced by controller : ETH_MDIO sourced by PHY: ETH_MDC t3 t2 OPEN MARKET VERSION

Electrical Specification Ethernet Interface (ETH) Characteristics Data Sheet 369 V 1.2, 2021-03

3.24.3 ETH MII Parameters

In the following, the parameters of the MII (Media Independent Interface) are described. Figure 3-19 ETH MII Signal Timing Table 3-55 ETH MII Signal Timing Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Clock period t7 SR - 40 - ns CL=25pF ; baudrate=100Mbps - 400 - ns CL=25pF ; baudrate=10Mbps Clock high time t8 SR 14 - 26 ns CL=25pF ; baudrate=100Mbps 140 1) 1) Defined by 35% of clock period. -2 6 0 2) 2) Defined by 65% of clock period. ns CL=25pF ; baudrate=10Mbps Clock low time t9 SR 14 - 26 ns CL=25pF ; baudrate=100Mbps 140 1) -2 6 0 2) ns CL=25pF ; baudrate=10Mbps Input setup time t10 SR 10 - - ns CL=25pF Input hold time t11 SR 10 - - ns CL=25pF Output valid time t12 CC 0 - 25 ns CL=25pF ETH_Timing-MII.vsd ETH _MII_RX_CLK ETH_MII_TXD [3:0] ETH_MII_TXEN ETH_MII_RXD[3:0] ETH_MII_RX_DV ETH_MII_RX_ER ETH_MII_TX_CLK t11 Valid Data t10 Valid Data t12 (sourced by controller ) (sourced by PHY ) t9 t8 ETH _MII_RX_CLK ETH_MII_TX_CLK OPEN MARKET VERSION

Electrical Specification Ethernet Interface (ETH) Characteristics Data Sheet 370 V 1.2, 2021-03

3.24.4 ETH RMII Parameters

In the following, the parameters of the RMII (Reduced Media Independent Interface) are described. Figure 3-20 ETH RMII Signal Timing Table 3-56 ETH RMII Signal Timing Parameters valid for 3.3V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. ETH_RMII_REF_CL clock period t13 SR - 20 - ns 50ppm ; CL=25pF ETH_RMII_REF_CL clock high time t14 SR 7 1) 1) Defined by 35% of clock period. -1 3 2) 2) Defined by 65% of clock period. ns CL=25pF ETH_RMII_REF_CL clock low time t15 SR 7 1) -1 3 2) ns CL=25pF ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV; setup time 3) 3) For ETHRXD and ETHCRSDV signa ls this parameter is a SR. t16 CC 4 - - ns CL=25pF ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV; hold time 3) t17 CC 2 - - ns CL=25pF ETH_Timing-RMII.vsd ETH _RMII_REF _CL t17 Valid Data t16 t13 t15 t14 ETH _RMII_REF _CL ETHTXEN , ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV, ETHRXER OPEN MARKET VERSION

Electrical Specification Ethernet Interface (ETH) Characteristics Data Sheet 371 V 1.2, 2021-03

3.24.5 ETH RGMII Parameters

In the following, the parameters of the RGMII are described. Figure 3-21 ETH RGMII TX Signal Timing (Delay on Destination (DoD)) Figure 3-22 ETH RGMII RX Signal Timing (Delay on Source (DoS)) Table 3-57 ETH RGMII Signal Timing Parameters valid for 3.3V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. TX Clock period t19 CC 36 40 44 ns 100Mbps 360 400 440 ns 10Mbps 7.2 8 8.8 ns Gigabit Data to Clock Output skew t20 CC -500 0 500 ps Data to Clock input skew (at receiver) t21 SR 1 1.8 2.6 ns SKEWCTL.RXCFG = 0; SKEWCTL.TXCFG = Clock duty cycle tduty CC 40 50 60 % 10/100Mbps 45 50 55 % Gigabit GREFCLK duty cycle tduty_in SR 45 - 55 % GREFCLK Input accuracy ACC SR -0.005 - 0.005 % OPEN MARKET VERSION

Electrical Specification E-Ray Parameters Data Sheet 372 V 1.2, 2021-03

3.25 E-Ray Parameters

The timings of this section are valid for the strong driver and sharp edge settings of the output drivers with CL = 25 pF. Table 3-58 Transmit Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Rise time of TxEN tdCCTxENRise2 5 CC --9 n s CL=25pF Fall time of TxEN tdCCTxENFall25 CC --9 n s CL=25pF Sum of rise and fall time tdCCTxRise25+d CCTxFall25 CC - - 9 ns 20% - 80% ; CL=25pF Sum of delay between TP1_FF and TP1_CC and delays derived from TP1_FFi, rising edge of TxEN tdCCTxEN01 CC --2 5 n s Sum of delay between TP1_FF and TP1_CC and delays derived from TP1_FFi, falling edge of TxEN tdCCTxEN10 CC --2 5 n s Asymmetry of sending ttx_asym CC -2.45 - 2.45 ns CL=25pF Sum of delay between TP1_FF and TP1_CC and delays derived from TP1_FFi, rising edge of TxD tdCCTxD01 CC - - 25 ns Sum of delay between TP1_FF and TP1_CC and delays derived from TP1_FFi, falling edge of TxD tdCCTxD10 CC - - 25 ns TxD signal sum of rise and fall time at TP1_BD ttxd_sum CC - - 9 ns Table 3-59 Receive Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Acceptance of asymmetry at receiving part tdCCTxAsymAcc ept25 SR -30.5 - 43.0 ns CL=25pF Acceptance of asymmetry at receiving part tdCCTxAsymAcc ept15 SR -31.5 - 44.0 ns CL=15pF Threshold for detecting logical high TuCCLogic1 SR 35 - 70 % Threshold for detecting logical low TuCCLogic0 SR 30 - 65 % OPEN MARKET VERSION

Electrical Specification E-Ray Parameters Data Sheet 373 V 1.2, 2021-03 Sum of delay between TP4_CC and TP4_FF and delays derived from TP4_FFi, rising edge of RxD tdCCRxD01 CC - - 10 ns Sum of delay between TP4_CC and TP4_FF and delays derived from TP4_FFi, falling edge of RxD tdCCRxD10 CC - - 10 ns Table 3-59 Receive Parameters (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification HSCT Parameters Data Sheet 374 V 1.2, 2021-03

3.26 HSCT Parameters

Table 3-60 HSCT - Rx parasitics and loads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Capacitance total budget Ctotal CC - 3.5 5 pF Total Budget for complete receiver including silicon, package, pins and bond wire Parasitic inductance budget Htotal CC - 5 - nH Table 3-61 HSCT - Rx/Tx setup timing Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. RX o/p duty cycle DCrx CC 40 - 60 % Disable time of the LVDS pad tLVDSDIS CC - - 20 ns Enable time of the LVDS pad tLVDSEN CC - - 400 ns Wakeup time from Sleep Mode tSWU CC - - 250 ns Maximum length of a wake-up glitch that does not wake-up the receiver tWUP CC - - 0.2 ns Bias startup time tbias CC - 5 10 µs Bias distributor waking up from power down and provide stable Bias. RX startup time trxi CC - - 600 ns Wake-up RX from power down. TX startup time ttx CC - - 280 ns Wake-up TX from power down. OPEN MARKET VERSION

Electrical Specification Inter-IC (I2C) Interface Timing Data Sheet 375 V 1.2, 2021-03

3.27 Inter-IC (I2 C) Interface Timing

This section defines the timings for I2C in the TC38x. All I2C timing parameter are SR for Master Mode and CC for Slave Mode. Table 3-62 I2C Standard Mode Timing Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Fall time of both SDA and SCL t1 - - 300 ns Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Capacitive load for each bus line Cb SR - - 400 pF Bus free time between a STOP and ATART condition t10 4.7 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Rise time of both SDA and SCL t2 - - 1000 ns Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Data hold time t3 0 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Data set-up time t4 250 - - ns Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Low period of SCL clock t5 4.7 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line High period of SCL clock t6 4 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Hold time for the (repeated) START condition t7 4 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line OPEN MARKET VERSION

Electrical Specification Inter-IC (I2C) Interface Timing Data Sheet 376 V 1.2, 2021-03 Set-up time for (repeated) START condition t8 4.7 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Set-up time for STOP condition t9 4 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Table 3-63 I2C Fast Mode Timing Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Fall time of both SDA and SCL t1 20+0.1* Cb - 300 ns Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Capacitive load for each bus line Cb SR - - 400 pF Bus free time between a STOP and ATART condition t10 1.3 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Rise time of both SDA and SCL t2 20+0.1* Cb - 300 ns Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Data hold time t3 0 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Data set-up time t4 100 - - ns Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Low period of SCL clock t5 1.3 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line High period of SCL clock t6 0.6 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Table 3-62 I2C Standard Mode Timing (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Inter-IC (I2C) Interface Timing Data Sheet 377 V 1.2, 2021-03 Hold time for the (repeated) START condition t7 0.6 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Set-up time for (repeated) START condition t8 0.6 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Set-up time for STOP condition t9 0.6 - - µs Measured with a pull- up resistor of 4.7 kohms at each of the SCL and SDA line Table 3-64 I2C High Speed Mode Timing Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Capacitive load for each bus line Cb SR - - 400 pF Fall time of SCL t11 10 1) 1) Values are defined for Cb = 100pF, for the Timing of Cb = 400pF see the I2C Standard. -4 0 1) ns bus line lo ad of 100pF Fall time of SDA t12 10 1) -8 0 1) ns bus line lo ad of 100pF Rise time of SCL t13 10 1) -4 0 1) ns bus line lo ad of 100pF Rise time of SDA t14 10 1) -8 0 1) ns bus line lo ad of 100pF Data hold time t3 0 1) -7 0 1) ns bus line lo ad of 100pF Data set-up time t4 10 1) - - ns bus line lo ad of 100pF Low period of SCL clock t5 160 1) - - ns bus line lo ad of 100pF High period of SCL clock t6 60 1) - - ns bus line lo ad of 100pF Hold time for the (repeated) START condition t7 160 1) - - ns bus line lo ad of 100pF Set-up time for (repeated) START condition t8 160 1) - - ns bus line lo ad of 100pF Set-up time for STOP condition t9 160 1) - - ns bus line lo ad of 100pF Table 3-63 I2C Fast Mode Timing (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Inter-IC (I2C) Interface Timing Data Sheet 378 V 1.2, 2021-03 Figure 3-23 I2C Standard and Fast Mode Timing SCL SDA SCL SDA t1 t2 t1 t2 t10 t9t7t8 PSSr S 70% 30% 9th clock 9th clock OPEN MARKET VERSION

Electrical Specification FSP Parameters Data Sheet 379 V 1.2, 2021-03

3.28 FSP Parameters

Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Skew between FSP0 and FSP1 tFSPSKEW CC -8 - 9 ns CL=50pF, driver strength m -5 - 6 ns CL=50pF, driver strength sm -4 - 5 ns CL=50pF, driver strength ss OPEN MARKET VERSION

Electrical Specification Flash Target Parameters Data Sheet 380 V 1.2, 2021-03

3.29 Flash Target Parameters

Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Program Flash Erase Time per logical sector 1) tERP CC - - 0.5 s cycle count < 1000 Program Flash Erase Time per Multi-Sector Command 1) tMERP CC - - 0.5 s For consecutive logical sectors in a physical sector with total range ≤ 512 kByte; cycle count < 1000 Program Flash program time per page in 5 V mode 1) tPRP5 CC - - 80 µs 32 Byte Program Flash program time per page in 3.3 V mode 1) tPRP3 CC - - 115 µs 32 Byte Program Flash program time per burst in 5 V mode 1) tPRPB5 CC - - 220 µs 256 Byte Program Flash program time per burst in 3.3 V mode 1) tPRPB3 CC - - 530 µs 256 Byte Program Flash program time for

1 MByte with burst programming

in 3.3 V mode excluding communication 1) tPRPB3_1MB CC - - 2.2 s Derived value for documentation purpose Program Flash program time for communication 1) tPRPB5_1MB CC - - 1 s Derived value for documentation purpose Program Flash program time for complete PFlash with burst programming in 5 V mode excluding communication 1) tPRPB5_PF CC - - 10 s Derived value for documentation purpose Write Page Once adder 1) tADD CC - - 20 µs Adder to Program Time when using Write Page Once Program Flash suspend to read latency 1) tSPNDP CC - - 120 µs For Write Burst, Verify Erased and for multi- (logical) sector erase commands Data Flash Erase Disturb Limit (single ended sensing mode) NDFD CC - - 50 cycles Data Flash Erase Disturb Limit (complement sensing mode) NDFDC CC - - 500 cycles UCB Erase Disturb Limit NUCBD CC - - 500 cycles OPEN MARKET VERSION

Electrical Specification Flash Target Parameters Data Sheet 381 V 1.2, 2021-03 Program time data flash per page 1)2) tPRD CC - - 75 µs 8 Byte Complete Device Flash Erase Time PFlash and DFlash 1)3) 4) 5) tER_Dev CC - 6.7 11.5 s Valid for less than 1000 cycles, w/o UCB. Derived value for documentation purpose. Data Flash program time per burst 1)2) tPRDB CC - - 140 µs 32 Byte Data Flash suspend to read latency 1) tSPNDD CC - - 120 µs Wait time after margin change tFL_MarginDel CC --2 µ s Program Flash Endurance per Logical Sector NE_P CC - - 1000 cycles Replace logical sector command shall be used if a sector fails during erase or program Number of erase operations per physical sector in program flash NERP CC - - 16000 cycles Program Flash Retention Time, Sector tRET CC 20 - - years Max. 1000 erase/program cycles UCB Retention Time tRTU CC 20 - - years Max. 100 erase/program cycles per UCB, max 500 erase/program cycles for all UCBs together Data Flash access delay tDF CC - - 100 ns see RFLASH of DMU register HF_DWAIT Data Flash ECC Delay tDFECC CC - - 20 ns see RECC of DMU register HF_DWAIT Program Flash access delay tPF CC - - 30 ns see RFLASH of DMU register HF_PWAIT Program Flash ECC delay tPFECC CC - - 10 ns see RECC and CECC of DMU register HF_PWAIT Number of erase operations on DF0 over lifetime (complement sensing mode) 6) NERD0C CC - - 4000000 cycles Number of erase operations on DF0 over lifetime (single ended sensing mode) 7) NERD0S CC - - 750000 cycles Table 3-66 Flash (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Flash Target Parameters Data Sheet 382 V 1.2, 2021-03 Number of erase operations on DF1 over lifetime (complement sensing mode) 6) NERD1C CC - - 2000000 cycles Number of erase operations on DF1 over lifetime (single ended sensing mode) 7) NERD1S CC - - 500000 cycles Data Flash Endurance per EEPROMx sector (complement sensing mode) 8) NE_EEP10C CC - - 500000 cycles Max. data retention time 10 years DataFlash Endurance per EEPROMx sector (single ended sensing mode) 8) NE_EEP10S CC - - 125000 cycles Retent ion time and Tj according below example temperature profile - - 125000 cycles max data retention time 20y, Tj=110°C - - 125000 cycles max data retention time 8.2y, Tj=125°C Data Flash Endurance per HSMx sector (complement sensing mode) 8) NE_HSMC CC - - 250000 cycles Max. data retention time 10 years Data Flash Endurance per HSMx sector (single ended sensing mode) 8) NE_HSMS CC - - 125000 cycles Ret ention time and Tj according below example temperature profile - - 125000 cycles max data retention time 20y, Tj=110°C - - 125000 cycles max data retention time 8.2y, Tj=125°C Junction temperature limit for PFlash program/erase operations TJPFlash SR - - 150 °C Data Flash Erase Time per Sector 1)3)5) tERD1 CC - - 0.5 s Max. 1000 erase/program cycles Data Flash Erase Time per Sector 1)3)5) tERDM CC - - 1.5 s Max allowed cycles, see NE_EEP10 and NE_HSM parameters DataFlash Adder on Erase Time per 32kByte erase size when using complement sensing mode 1) tER_ADDC32C CC - - 50 ms Adder per 32 kByte on erase time; applicable only when using complement mode Table 3-66 Flash (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Flash Target Parameters Data Sheet 383 V 1.2, 2021-03 Data Flash Erase Time per Multi-Sector Command 1)3)5) tMERD1 CC - - 0.5 s Max 1000 erase/program cycles; For consecutive logical sectors ≤ 256KBytes Data Flash Erase Time per Multi-Sector Command 1)3)5) tMERDM CC - - 1.5 s Max allowed cycles, see NE_EEP10x and NE_HSMx Parameters; For consecutive logical sectors ≤ 256 kByte Program Flash Access Delay at reduced VDDP3 voltage supply during cranking tPF_low_VDDP3 CC - - 60 ns see register DMU_HF_PWAIT.CFL ASH Data Flash Erase Verify time per page (Complement Sensing) 2) tVER_PAGE_DC CC - - 10 µs Time per 8 Byte page for Verify Erased Page command Data Flash Erase Verify time per page (Single Ended Sensing) 1) tVER_PAGE_DS CC - - 10 µs Time per 8 Byte page for Verify Erased Page command Program Flash Erase Verify time per page 1) tVER_PAGE_P CC - - 10 µs Time per 32 Byte page for Verify Erased Page command Data Flash Erase Verify time per sector (Complement Sensing) 1) tVER_SEC_DC CC - - 200 µs Time per 2 KB sector for Verify Erased Logical Sector Range command Data Flash Erase Verify time per sector (Single Ended Sensing) 1) tVER_SEC_DS CC - - 360 µs Time per 4 KB sector for Verify Erased Logical Sector Range command Program Flash Erase Verify time per sector 1) tVER_SEC_P CC - - 360 µs Time per 16KB sector for Verify Erased Logical Sector Range command Data Flash Erase Verify time per wordline (Complement Sensing) tVER_WL_DC CC --3 0 µ s Data Flash Erase Verify time per wordline (Single Ended Sensing) 1) tVER_WL_DS CC --5 0 µ s Program Flash Erase Verify time per wordline 1) tVER_WL_P CC --3 0 µ s 1) Only vaild for fFSI = 100MHz. 2) Time is not dependent on program mode (5V or 3.3V). Table 3-66 Flash (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. OPEN MARKET VERSION

Electrical Specification Flash Target Parameters Data Sheet 384 V 1.2, 2021-03 3) Under out-of-spec conditions (e.g. over-cycling) or in case of activation of WL oriented defects, the duration of erase processes may be increased by up to 50%. 4) Using 512 kByte / 256 kByte eras e commands (PFlash / DFlash). 5) If the DataFlash is operated in Complement Sensing Mode the erase time is increased by erase_size / 32kByte x tER_ADDC32C 6) Allows segmentation of address able memory into 8 logical sectors; round robin cycling must still be done to consider erase disturb limit NDFD. 7) Allows segmentation of address able memory into 6 logical sectors; round robin cycling must still be done to consider erase disturb limit NDFD. 8) Only valid when a r obust EEPROM emulation algorithm is used. For more details see the Users Manual. OPEN MARKET VERSION

Electrical Specification Quality Declarations Data Sheet 385 V 1.2, 2021-03

3.30 Quality Declarations

Example Temperature Profile The following temperature profile is an example. Operation Lifetime plus Inactive time defines a 20 years period. Application specific temperature profiles need to be aligned an d approved by Infineon Technologies for the fulfillment of quality and reliability targets. Table 3-67 Quality Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Moisture Sensitivity Level MSL CC - - 3 Conforming to Jedec J- STD--020C for 240C ESD susceptibility according to Charged Device Model (CDM) VCDM SR - - 500 1) 1) Pads of the AGBT interface are limited to a maximum value of 250V. V for all other balls/pins; conforming to JESD22- C101-C - - 750 V for corner balls/pins; conforming to JESD22- C101-C ESD susceptibility according to Human Body Model (HBM) VHBM SR - - 2000 2) 2) Pads of the AGBT interface are limited to a maximum value of 1000V. V Conforming to JESD22-A114-B ESD susceptibility of the LVDS pins according to Human Body Model (HBM) VHBM1 SR - - 2000 V Operation Lifetime tOP CC - - 24500 hour see below temperature profile as an example Table 3-68 Example Operation Lifetime Temperature Profile TJ= Duration [h] Comment ≤ 170°C ≤ 30 ≤ 160°C ≤ 120 ≤ 150°C ≤ 220 ≤ 140°C ≤ 350 ≤ 130°C ≤ 780 ≤ 120°C ≤ 1600 ≤ 110°C ≤ 3000 ≤ 100°C ≤ 7000 ≤ 90°C ≤ 8000 ≤ 80°C ≤ 2400 ≤ 70°C ≤ 1000 ≤ 24500 total time OPEN MARKET VERSION

Electrical Specification Quality Declarations Data Sheet 386 V 1.2, 2021-03 Table 3-69 Example Inactive Lifetime Temperature Profile TJ= Duration [h] Comment ≤ 55°C ≤ 150700 OPEN MARKET VERSION

Electrical Specification Package Outline Data Sheet 387 V 1.2, 2021-03

3.31 Package Outline

Figure 3-24 Package Outlines FBGA-516 Figure 3-25 Package Outlines LFBGA-292 You can find all of our packages, sorts of packing and others i n our Infineon Internet Page “Products”: http://www.infineon.com/products. OPEN MARKET VERSION

Electrical Specification Package Outline Data Sheet 388 V 1.2, 2021-03

3.31.1 Package Parameters

Table 3-70 Package Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Thermal resistance (junction to ambient) 1) 1) The top and bottom thermal resistances between the case and t he ambient (RTH_CTA, RTH_CBA) are to be combined with the thermal resistances between the junction and the case given above (RTH_JCT, RTH_JCB), in order to calculate the total thermal resistance between the junction and the ambient (RTH_JA). The thermal resistances between the case and the ambient (RTH_CTA, RTH_CBA) depend on the external system (PCB, case) characteristics and are under user responsibility. The junction temperature can be calculated using the following equation: TJ = TA + RTH_JA * PD, where the RTH_JA is the total thermal resistance between the junction and the ambient. Thermal resistances as measured by the 'cold plate method' (MIL SPEC-883 Method 1012.1). RTH_JA CC --1 4 K / W F B G A 5 1 6 - - 17 K/W LFBGA292 Thermal resistance (junction to case bottom) 1) RTH_JCB CC - - 3 K/W FBGA516 - - 4 K/W LFBGA292 Thermal resistance (junction to case top) 1) RTH_JCT CC - - 5 K/W FBGA516 - - 5 K/W LFBGA292 OPEN MARKET VERSION

History Changes from Version 0.4 to Version 0.6 Data Sheet 389 V 1.2, 2021-03

4 History

Version 0.4 is the first version of this document. 4.1 Changes from Versi on 0.4 to Version 0.6

• Update table Platform Feature Overview
• Changes in Pin Definition and Functions – Add pad type RFAST to Legend – Corrected ball assigmant to NC and NC1 – P32.0 replece name from EVR13 to EVRC – P32.1 replece name from EVR13 to EVRC – Add Function description f or GTM_TIM_INxx Symbols – Change numbering for GTM_TIM_INxx Symbols – Update Function description for CAN signals – Add missing Function description for EVADC – Add missing Function description for EDSADC – Add Function description for GTM_DTMxx Symbols – Update Function description for SCU_E_REQ signals – Change Symbol for SCU_E_REQ signals – Update Function description for SCU_PD_HWCFGx signals – remove PLL_WRAPPER_ANA_0_PAD_SYSCLK – Switch CBS_TGyz from inverted to non inverted – Add CCUEXTCLK0 – Add EDSADC_EDS9NB to AN70 – Add EDSADC_EDS9NB to AN71 – Add PMS_DCDCSYNCO to P32.4 – Add DAP3 to P21.6 – Remove SDMMC_DS from P15.2 – ADD TDI to P21.6 – Add DAPE1 to P21.6 – Add DAP2 to P21.7 – ADD TDO to P21.7 – Remove DAP Function description from P21.7 Input – Add EVADC_G5CH2 to AN50 – Add EDSADC_EDS9PB to AN70 – Add EDSADC_EDS9NB to AN71
• Changes in table 'Overload Parameters' of Overload – Change note of KOVDN from ''Overload injected on GPIO non LVDS pad and affecting neighbor slow pads; -2mA < IIN < 0mA'' to ''Overload injected on GPIO non LVDS pad and affecting neighbor slow pads; -5mA < IIN < 0mA'' – Change max value of KOVDN from '6*10-4' to '1*10-4' – Change max value of KOVDN from '1.7*10-3' to '3*10-4' OPEN MARKET VERSION

History Changes from Version 0.4 to Version 0.6 Data Sheet 390 V 1.2, 2021-03 – Change note of KOVDN from ''Overload injected on LVDS pad and affecting neighbor LVDS pads'' to ''Overload injected on LVDS TX pad and affecting neighbor LVDS pads'' – Change max value of KOVDN from '0.3' to '0.5' – Change note of KOVDP from 'Overload injected on LVDS pad and affecting neighbor LVDS pads' to 'Overload injected on LVDS TX pad and affecting neighbor LVDS pads' – Change max value of KOVDP from 5*10-4 to 5*10-3 – Change max value of KOVDP from '1*10-5' to '1.5*10-3' – Change max value of KOVAN from 1*10-4 to 1*10-5 – Change note of KOVAN from 'Analog Inputs overlaid with class slow pads or pull down diagnostics; -1mA < IIN < 0mA' to 'Analog Inputs overlaid with class slow pads or pull down diagnostics; -5mA < IIN < 0mA' – Change max value of KOVAN from 1*10-3 to 1*10-4 – Change note of KOVAP from '1*10-5' to '2*10-5' – Change note of KOVAP from '1*10-4' to '2*10-4' – Add parameter IOUT

• Operating Conditions – Change note of VDDM from 'Lower voltage range' to '' – Change note of VEVRSB from 'VEVRSB is bonded together with VEXT supply pin in smaller LQFP packages.' to ''
• Changes in table 'Fast 5V GPIO' of Standard Pads – Change note of HYS from '0.1 * VEXT/FLEX V' to '0.09 * VEXT/FLEX V' – Change note of HYS from '0.09 * VEXT/FLEX V' to '0.075 * VEXT/FLEX V' – Change min value of RDSON from 140 Ohm to 125 Ohm – Change typ value of RDSON from 200 Ohm to 225 Ohm – Change note of RDSON from '260 Ohm' to '320 Ohm' – Change note of RDSON from '35 Ohm' to '31 Ohm' – Change note of RDSON from '50 Ohm' to '55 Ohm' – Change note of RDSON from '65 Ohm' to '80 Ohm' – Change note of tRF from ''CL = 25pF; driver = strong sharp edge'' to ''CL = 25pF; driver = strong sharp edge; from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX'' – Change note of tRF from '2.8 ns' to '3.2 ns' – Change min value of tRF from 0.5+0.075*CL ns to 0.5+0.08*CL ns – Change max value of tRF from 0.5+0.15*CL ns to 1.0+0.17*CL ns – Change note of tRF from '2.5+0.18*CL ns' to '1.0+0.18*CL ns' – Change note of tRF from '2.5+0.35*CL ns' to '5.0+0.35*CL ns' – Change max value of tRF from 4+0.95*CL ns to 12+1.0*CL ns – Change note of IOZ from '-3900 nA' to '-5000 nA' – Change min value of IOZ from -3600 nA to -5000 nA – Change min value of IOZ from -6700 nA to -9000 nA – Change max value of IOZ from 3900 nA to 5000 nA – Change max value of IOZ from 3600 nA to 5000 nA – Change note of IOZ from '6700 nA' to '9000 nA' – Change note of tRF from 'CL = 25pF; driver = strong sharp edge' to 'CL = 25pF; driver = strong sharp edge; from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX' OPEN MARKET VERSION

History Changes from Version 0.4 to Version 0.6 Data Sheet 391 V 1.2, 2021-03 – Change note of fIND from '' to 'AL and TTL' – Change note of fOUTD from '' to 'medium driver' – Change note of IPDL from 'VIL; AL or TTL' to 'VIL; AL'

• Changes in table 'Fast 3. 3V GPIO' of Standard Pads – Change note of HYS from '0.065 * VEXT/FLEX V' to '0.055 * VEXT/FLEX V' – Change min value of HYS from 0.1 * VEXT/FLEX V to 0.09 * VEXT/FLEX V – Change note of HYS from '0.07 * VEXT/FLEX V' to '0.055 * VEXT/FLEX V' – Change min value of RDSON from 140 Ohm to 125 Ohm – Change note of RDSON from '200 Ohm' to '225 Ohm' – Change note of RDSON from '300 Ohm' to '320 Ohm' – Change note of RDSON from '35 Ohm' to '31 Ohm' – Change typ value of RDSON from 50 Ohm to 55 Ohm – Change max value of RDSON from 77 Ohm to 80 Ohm – Change note of tRF from ''CL = 25pF; driver = strong sharp edge'' to ''CL = 25pF; driver = strong sharp edge; from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX'' – Change note of tRF from '2 ns' to '1.6 ns' – Change min value of tRF from 4+0.57*CL ns to 2+0.57*CL ns – Change max value of tRF from 0.75+0.15*CL ns to 2.5+0.21*CL ns – Change max value of tRF from 1.5+0.38*CL ns to 8+0.4*CL ns – Change note of tRF from '7+1.1*CL ns' to '10+1.25*CL ns' – Change min value of IPUH from |19| µA to |17| µA – Change min value of IPUH from |9| µA to |11| µA – Change min value of IPDL from |18| µA to |15| µA – Change min value of IOZ from -4100 nA to -5000 nA – Change min value of IOZ from -3600 nA to -5000 nA – Change min value of IOZ from -6700 nA to -9000 nA – Change max value of IOZ from 4100 nA to 5000 nA – Change note of IOZ from '3600 nA' to '5000 nA' – Change max value of IOZ from 6700 nA to 9000 nA – Change note of tRF from 'CL = 25pF; driver = strong sharp edge' to 'CL = 25pF; driver = strong sharp edge; from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX' – Change note of fOUTD from '' to 'medium driver'
• Changes in table 'Slow 5V GPIO' of Standard Pads – Change min value of HYS from 0.1 * VEXT/FLEX V to 0.09 * VEXT/FLEX V – Change min value of HYS from 0.09 * VEXT/FLEX V to 0.075 * VEXT/FLEX V – Change min value of RDSON from 140 Ohm to 125 Ohm – Change typ value of RDSON from 200 Ohm to 225 Ohm – Change max value of RDSON from 260 Ohm to 320 Ohm – Change note of tRF from '4+0.95*CL ns' to '12+1*CL ns' – Change note of tRF from '3.5+0.55*CL ns' to '7+0.55*CL ns' – Change note of IPUH from 'VIH; AL or TTL' to 'VIH; AL or TTL; exept VGATE1P and TJ > 150°C' – Change note of IPUH from 'VIL; AL or TTL' to 'VIL; AL or TTL; exept VGATE1P and TJ > 150°C' OPEN MARKET VERSION

History Changes from Version 0.4 to Version 0.6 Data Sheet 392 V 1.2, 2021-03 – Change note of IPDL from 'VIL; AL or TTL' to 'VIL; AL'

• Changes in table 'Slow 3. 3V GPIO' of Standard Pads – Change min value of HYS from 0.1 * VEXT/FLEX V to 0.09 * VEXT/FLEX V – Change min value of HYS from 0.065 * VEXT/FLEX V to 0.055 * VEXT/FLEX V – Change min value of HYS from 0.07 * VEXT/FLEX V to 0.055 * VEXT/FLEX V – Change note of RDSON from '140 Ohm' to '125 Ohm' – Change typ value of RDSON from 200 Ohm to 225 Ohm – Change max value of RDSON from 300 Ohm to 320 Ohm – Change note of tRF from '4+0.57*CL ns' to '2+0.57*CL ns' – Change note of tRF from '7+1.1*CL ns' to '10+1.25*CL ns' – Change note of IPUH from 'VIH; AL and TTL (degraded, used for CIF)' to 'VIH; AL and TTL (degraded, used for CIF); exept VGATE1P and TJ > 150°C' – Change min value of IPUH from |19| µA to |17| µA – Change note of IPUH from ''VIH; TTL'' to ''VIH; TTL; exept VGATE1P and TJ > 150°C'' – Change note of IPUH from '|9| µA' to '|11| µA' – Change min value of IPDL from |18| µA to |15| µA – Change note of IPUH from 'VIL; AL and TTL and TTL (degraded, used for CIF)' to 'VIL; AL and TTL and TTL (degraded, used for CIF); exept VGATE1P and TJ > 150°C' – Change note of fOUTD from '' to 'medium driver'
• Changes in table 'PORST Pad' of Standard Pads – Change note of HYS from 'non of the neighbor pads are used as output; TTL' to 'non of the neighbor pads are used as output;TTL (degraded, used for CIF)' – Change min value of HYS from 0.1 * VEXT/FLEX V to 0.055 * VEXT/FLEX V – Change note of IPDL from '|18| µA' to '|15| µA' – Change note of HYS from 'two of the neighbor pads are used as output with driver=strong and edge=sharp; TTL' to 'two of the neighbor pads are used as output with driver=strong and edge=sharp; TTL (degraded, used for CIF)'
• Changes in table 'Class S 5V' of Standard Pads – Change min value of HYS from 0.1 * VEXT/FLEX V to 0.09 * VEXT/FLEX V – Change min value of HYS from 0.09 * VEXT/FLEX V to 0.075 * VEXT/FLEX V – Change note of IPDL from 'VIL; AL or TTL' to 'VIL; AL'
• Changes in table 'RFast 3 .3V pad' of Standard Pads – Change min value of HYS from 0.065 * VEXT/FLEX V to 0.055 * VEXT/FLEX V – Change min value of HYS from 0.1 * VEXT/FLEX V to 0.09 * VEXT/FLEX V – Change min value of HYS from 0.07 * VEXT/FLEX V to 0.055 * VEXT/FLEX V – Change min value of RDSON from 140 Ohm to 125 Ohm – Change typ value of RDSON from 200 Ohm to 225 Ohm – Change note of RDSON from '300 Ohm' to '320 Ohm' – Change note of RDSON from '35 Ohm' to '31 Ohm' – Change typ value of RDSON from 50 Ohm to 55 Ohm – Change max value of RDSON from 77 Ohm to 80 Ohm – Change note of RDSON from '10 Ohm' to '8 Ohm' OPEN MARKET VERSION

History Changes from Version 0.4 to Version 0.6 Data Sheet 393 V 1.2, 2021-03 – Change note of tRF from 'CL = 25pF; driver = strong sharp edge' to 'CL = 25pF; driver = strong sharp edge; from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX' – Change min value of tRF from 2 ns to 1.6 ns – Change min value of tRF from 4+0.57*CL ns to 2+0.57*CL ns – Change note of tRF from '0.75+0.15*CL ns' to '2.5+0.21*CL ns' – Change max value of tRF from 1.5+0.38*CL ns to 8+0.4*CL ns – Change max value of tRF from 7+1.1*CL ns to 10+1.25*CL ns – Change min value of IPUH from |19| µA to |17| µA – Change note of IPUH from '|9| µA' to '|11| µA' – Change min value of IPDL from |18| µA to |15| µA – Change note of tRF from 'CL = 25pF; driver = strong sharp edge' to 'CL = 25pF; driver = strong sharp edge; from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX' – Change note of fOUTD from '' to 'medium driver'

• Changes in table 'RFast 5V GPIO' of Standard Pads – Change min value of HYS from 0.1 * VEXT/FLEX V to 0.09 * VEXT/FLEX V – Change note of HYS from '0.09 * VEXT/FLEX V' to '0.075 * VEXT/FLEX V' – Change min value of RDSON from 140 Ohm to 125 Ohm – Change max value of RDSON from 260 Ohm to 320 Ohm – Change typ value of RDSON from 200 Ohm to 225 Ohm – Change note of RDSON from '35 Ohm' to '31 Ohm' – Change max value of RDSON from 65 Ohm to 80 Ohm – Change note of RDSON from '50 Ohm' to '55 Ohm' – Change note of tRF from '2.5+0.18*CL ns' to '1.0+0.18*CL ns' – Change note of tRF from ''CL = 25pF; driver = strong sharp edge'' to ''CL = 25pF; driver = strong sharp edge; from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX'' – Change note of tRF from '2.8 ns' to '3.2 ns' – Change min value of tRF from 0.5+0.075*CL ns to 0.5+0.08*CL ns – Change note of tRF from '0.5+0.15*CL ns' to '1.0+0.17*CL ns' – Change max value of tRF from 4+0.95*CL ns to 12+1.0*CL ns – Change note of tRF from '2.5+0.35*CL ns' to '5.0+0.35*CL ns' – Change note of tRF from 'CL = 25pF; driver = strong sharp edge' to 'CL = 25pF; driver = strong sharp edge; from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX' – Change note of fIND from '' to 'AL and TTL' – Change note of fOUTD from '' to 'medium driver' – Change note of IPDL from 'VIL; AL or TTL' to 'VIL; AL'
• Changes in table 'Class D' of Standard Pads – Update footnote of Standard Pads to 'For AN11 200 nA need to be added.' – Change note of IOZ from 'TJ ≤ 150°C; PDD option available, or AltRef option available and EDSADC channel connected' to 'TJ ≤ 150°C; PDD option available, or AltRef option available and EDSADC channel connected, or two EDSADC channels connected'
• Changes in table 'LVDS - IEEE st andard LVDS general purpose link (GPL)' of LVDS Pads – Change max value of trise20 from 0.5 ns to 0.75 ns – Change max value of tfall20 from 0.5 ns to 0.75 ns OPEN MARKET VERSION

History Changes from Version 0.4 to Version 0.6 Data Sheet 394 V 1.2, 2021-03 – Change max value of VOD from 450 mV to 500 mV – Change min value of VOD from 360 mV to 380 mV

• VADC 5V – Change note of dVCSD from '-20 %' to '-10 %' – Change note of dVCSD from '20 %' to '10 %' – Change note of fADCI from 'Upper voltage range' to '4.5V ≤ VDDM ≤ 5.5V' – Change note of tSCAL from 'Upper voltage range' to '4.5V ≤ VDDM ≤ 5.5V' – Change note of fADCI from 'Lower voltage range' to '2.97V ≤ VDDM < 4.5V' – Change note of tS from 'Primary group or fast compare channel, upper voltage range; input buffer disabled' to 'Primary group or fast compare channel, 4.5V ≤ VDDM ≤ 5.5V; input buffer disabled' – Change note of tSCAL from 'Lower voltage range' to '2.97V ≤ VDDM < 4.5V' – Change note of tS from 'Primary group or fast compare channel, upper voltage range; input buffer enabled' to 'Primary group or fast compare channel, 4.5V ≤ VDDM ≤ 5.5V; input buffer enabled' – Change note of tS from 'Secondary group, upper voltage range; input buffer disabled' to 'Secondary group, 4.5V ≤ VDDM ≤ 5.5V; input buffer disabled' – Change note of tS from 'Secondary group, upper voltage range; input buffer enabled' to 'Secondary group, 4.5V ≤ VDDM ≤ 5.5V; input buffer enabled' – Change note of tS from 'Primary Group or fast compare channel, lower voltage range; input buffer disabled' to 'Primary Group or fast compare channel, 2.97V ≤ VDDM < 4.5V; input buffer disabled' – Change note of tS from 'Primary group or fast compare channel, lower voltage range; input buffer enabled' to 'Primary group or fast compare channel, 2.97V ≤ VDDM < 4.5V; input buffer enabled' – Change note of tS from 'Secondary group, lower voltage range; input buffer disabled' to 'Secondary group, 2.97V ≤ VDDM < 4.5V; input buffer disabled' – Change note of tS from 'Secondary group, lower voltage range; input buffer enabled' to 'Secondary group, 2.97V ≤ VDDM < 4.5V; input buffer enabled'
• DSADC 5V – Update wording in front of table DSADC 5V – Change note of DCF from '10-5 fD, offset compensation filter enabled (FCFGMx.OEN = 001B)' to '10-5 fD, offset compensation filter enabled (FCFGMx.OCEN = 001B)'
• O S C _ X T A L – Add parameter CXTAL1 – Change typ value of CL1 from 2.35 pF to 3.35 pF
• Changes in table 'DTS PMS' of DTS – Change max value of tM from 2.6 ms to 2.7 ms
• A d d t a b l e ' D T S C o r e '
• Current Consumption – Update footnote of Current Consumption to 'A single DS channel instance consumes 4 mA.' – Change note of IDDRAIL from '800 mA' to '840 mA' – Change note of IDDRAIL from '920 mA' to '1100 mA' – Change note of IDDRAIL from '960 mA' to '1100 mA' – Change note of IDDRAIL from '1020 mA' to '1100 mA' – Change note of IDDRAIL from '1110 mA' to '1100 mA' – Change note of IDDRAIL from '1099 mA' to '1100 mA' OPEN MARKET VERSION

History Changes from Version 0.4 to Version 0.6 Data Sheet 395 V 1.2, 2021-03

• Changes in table 'Module Core Cur rent Consumption' of Current Consumption – Change name of Module Core Current Consumption from Module Core Current Concumption to Module Core Current Consumption – Change max value of IDDCx0 from 40 mA to 45 mA – Change note of IDDCx0 from 'real power pattern' to 'real power pattern; IPC=0.6' – Change note of IDDCx0 from '60 mA' to '70 mA' – Change note of IDDCx0 from ''max power pattern'' to ''max power pattern; IPC=1.2'' – Change max value of IDDCxx from IDDCx0 + 60 mA to IDDCx0 + 50 mA – Change note of IDDCxx from 'max power pattern' to 'max power pattern; IPC=1.2' – Change max value of IDDGTM from 60 mA to 100 mA – Change note of IDDGTM from 'real power pattern; TIMx, TOMx, ATOMx , MCSx active. 5 clusters at 200 MHz.' to 'real power pattern; TIMx, TOMx, ATOMx , MCSx active. 3 clusters at 200 MHz.' – Change max value of IDDGTM from 88 mA to 120 mA – Change note of IDDMBIST from '100 mA' to '200 mA' – Change note of IDDCxx from 'real power pattern' to 'real power pattern; IPC=0.6' – Change max value of IDDGTM from 20 mA to 50 mA – Change note of IDDGTM from 'TIMx, TOMx active at 100MHz. ATOMx , MCSx, DPLL inactive.' to 'TIMx, TOMx active at 100MHz. ATOMx , MCSx, DPLL inactive. 2 clusters at 100 MHz.' – Change max value of IEXTRAIL from 58 mA to 50 mA – Change max value of IEXTRAIL from t.b.d mA to 56 mA – Change max value of IEXTFLEX from 30 mA to 18 mA
• Changes in table 'Module Current Consumption' of Current Consu mption – Change max value of IEXTLVDS from t.b.d mA to 20 mA – Change note of ISCRSB from '4 mA' to '6.5 mA' – Change note of ISCRSB from ''SCR 8-bit Standby Controller in STANDBY Mode drawn at VEVRSB supply pin'' to ''SCR 8-bit Standby Controller current incl. PMS in STANDBY Mode drawn at VEVRSB supply pin'' – Change note of ISCRSB from ''Additional SCR 8-bit Standby Controller current in STANDBY Mode drawn at VEVRSB supply pin'' to ''SCR 8-bit Standby Controller current incl. PMS in STANDBY Mode drawn at VEVRSB supply pin'' – Change note of ISCRSB from ''SCR 8-bit Standby Controller current in STANDBY Mode incl. PMS current drawn at VEVRSB supply pin'' to ''SCR 8-bit Standby Controller current incl. PMS in STANDBY Mode drawn at VEVRSB supply pin'' – Change note of ISCRSB from ''SCR power pattern; fSYS_SCR = 20MHz; TJ=150°C'' to ''SCR power pattern incl. PMS current consumption with fback clock active; fSYS_SCR = 20MHz; TJ=150°C'' – Change typ value of ISCRSB from 0.025 mA to 0.190 mA – Change note of ISCRSB from 'real power pattern; fSYS_SCR = 70kHz; TJ=25°C' to 'SCR power pattern incl. PMS current consumption with fback inactive; fSYS_SCR = 70kHz; TJ=25°C' – Change note of ISCRSB from ''SCR 8-bit Standby Controller in STANDBY Mode drawn at VEVRSB supply pin'' to ''SCR 8-bit Standby Controller current incl. PMS in STANDBY Mode drawn at VEVRSB supply pin'' – Change note of IDDM from '66 mA' to '32 mA' – Change note of IDDM from ''real power pattern ; current for EDSADC module only; 11 EDSADC channels active.'' to ''real power pattern; current for EDSADC modules only and EVADC modules are inactive; 8 EDSADC channels active continuously.'' – Change note of IDDM from '60 mA' to '45 mA' OPEN MARKET VERSION

History Changes from Version 0.4 to Version 0.6 Data Sheet 396 V 1.2, 2021-03 – Change note of IDDM from ''max power pattern; All EDSADC channels active 100% time.'' to ''max power pattern; current for EDSADC modules only and EVADC modules are inactive; all EDSADC channels active continuously.'' – Change note of IDDM from 'real pattern;12 EVADC modules active' to 'real power pattern; current for EVADC modules only and EDSADC modules are inactive; 12 EVADC modules active.' – Change max value of IDDM from 21 mA to 20 mA – Change note of IDDM from 'max power pattern; All EVADC modules are active 100% time' to 'max power pattern; current for EVADC modules only and EDSADC modules are inactive; all EVADC modules active.' – Change max value of IDDM from 56 mA to 48 mA – Change max value of ISLEEP from 10 mA to 25 mA – Change max value of IDDTOT from 924 mA to 978 mA – Change max value of PD from t.b.d. mW to 1700 mW – Change max value of PD from t.b.d. mW to 2400 mW – Change note of IDDTOTDC5 from 't.b.d mA' to '440 mA' – Change note of IDDTOTDC5 from ''real power pattern; VEXT = 5V; TJ=150°C'' to ''real power pattern; EVRC reset settings with 72% efficiency; VEXT = 5V; TJ=150°C'' – Change description of IDDTOTDC5 from '∑ Sum of all currents with DC-DC EVR13 regulator active' to '∑ Sum of all currents with DC-DC EVRC regulator active' – Change max value of IDDTOTDC3 from t.b.d. mA to 580 mA – Change note of IDDTOTDC3 from 'real power pattern; VEXT = 3.3V; TJ=150°C' to 'real power pattern; EVRC reset settings with 72% efficiency; VEXT = 3.3V; TJ=150°C' – Change description of IDDTOTDC3 from '∑ Sum of all currents with DC-DC EVR13 regulator active' to '∑ Sum of all currents with DC-DC EVRC regulator active' – Change max value of IEVRSB from 4 mA to 8 mA – Change note of IDDPORST from '430 mA' to '490 mA'

• Reset – Change min value of tPOH from 100 ns to 150 ns – Change note of tBP from 'dV/dT=1V/ms. including EVR ramp-up and Firmware execution time; RAM initialization and HSM boot time is not included' to 'dVEXT/dT=1V/ms. VEXT>VLVDRST5. Boot time after Cold PORST including EVR ramp-up and Firmware execution time; RAM initialization and HSM boot time are not included.' – Change note of tB from 'operating with max. frequencies' to 'operating with max. frequencies, with valid BMI header' – Change note of tBS from '' to 'RAM initialization and HSM boot time are not included, with valid BMI header' – Change note of tBP from 'Firmware execution time; without EVR ramp-up; RAM initialization and HSM boot time is not included' to 'Firmware execution time after warm PORST without EVR ramp-up; RAM initialization and HSM boot time is not included' – Change type of tPOA from CC to SR – Change description of tPOA from 'Minimum PORST active hold time externally after power supplies are stable at operating levels' to 'Minimum PORST active hold time externally after power supplies are stable at operating levels after start-up'
• PMS/EVR33 LDO – Change min value of COUT from 0.65 µF to 1.45 µF – Change note of COUT from '1.35 µF' to '3 µF' – Change note of COUT from '1 µF' to '2.2 µF' OPEN MARKET VERSION

History Changes from Version 0.4 to Version 0.6 Data Sheet 397 V 1.2, 2021-03 – Change min value of dVout/dIout from -100 mV to -180 mV – Change max value of dVout/dIout from 100 mV to 180 mV – Change note of IMAX from '100 mA' to '60 mA' – Change note of dVout/dVin from 'dVin/dT=50V/ms; dV= 5 to 3.6V' to 'dVin/dT=50V/ms; dV= 5 to 3.6V; IMAX=60mA' – Change note of dVout/dVin from 'dVin/dT=50V/ms; dV= 3.6 to 5V' to 'dVin/dT=50V/ms; dV= 3.6 to 5V; IMAX=60mA'

• PMS/Supply Monitors – Change note of VLVDRST5 from '2.7 V' to '2.75 V' – Change note of VLVDRST5 from '2.67 V' to '2.72 V'
• PMS/Supply Ramp – Change description of SR_V_EXT from 'External VEXT & VEVRSB supply ramp' to 'External VEXT & VEVRSB supply ramp-up and ramp-down slope' – Change description of SR_V_DDP3 from 'External VDDP3 supply ramp' to 'External VDDP3 supply ramp-up and ramp-down slope' – Change description of SR_V_DD from 'External VDD supply ramp' to 'External VDD supply ramp-up and ramp-down slope' – Change description of SR_V_DDM from 'External VDDM supply ramp' to 'External VDDM supply ramp-up and ramp-down slope'
• Changes in table 'EVRC SMPS' of PMS/EVRC SMPS – Change name of EVRC SMPS from EVR13 SMPS to EVRC SMPS
• Changes in table 'EVRC SMPS Exte rnal components' of PMS/EVRC SMPS – Change name of EVRC SMPS External components from EVR13 SMPS External components to EVRC SMPS External components
• Changes in section JTAG Parameters – Update figure Test Clock Timing (TCK)
• Changes in section DAP Parameters – Combine figures Test Clock Timing (DAP0), DAP Timing Host to D evice, and DAP Timing Device to Host (DAP1 and DAP2 pins) into single figure DAP Timing –A d d t14 for condition F=40MHz –A d d t15 for condition F=40MHz –A d d t16 for condition F=40MHz
• Changes in table 'Master Mode str ong sharp (ss) output pads' of ASCLIN – Change min value of t51 from -3 ns to -3.5 ns – Change max value of t51 from 3 ns to 3.5 ns – Change max value of t510 from 3 ns to 3.5 ns
• Changes in table 'Master Mode T iming, LVDS output pads for data and clock' of QSPI – Change note of t51 from '3 ns' to '4 ns' – Change note of t52 from '17 ns' to '18 ns'
• Changes in table 'Strong sharp ( ss) driver for clock/data valid for 5V' of MSC – Change min value of t45 from -3 ns to -4 ns – Change note of t44 from '-3 ns' to '-4 ns'
• Changes in table 'ETH RGMII Si gnal Timing Parameters valid for 3.3V' of Ethernet OPEN MARKET VERSION

History Changes from Version 0.6 to Version 0.7 Data Sheet 398 V 1.2, 2021-03 – Add parameter t21

• Changes in table 'ETH RMII Sig nal Timing Parameters valid for 3.3V' of Ethernet – Change description of t16 from 'ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV, ETHRXER; setup time' to 'ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV; setup time' – Change description of t17 from 'ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV, ETHRXER; hold time' to 'ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV; hold time'
• Changes in table 'HSCT - Rx/T x setup timing' of LVDS Pads – Change max value of ttx from 250 ns to 280 ns
• F l a s h – Change note of tER_Dev from ''Derived value for documentation purpose'' to ''Valid for less than 1000 cycles, w/o UCB. Derived value for documentation purpose.'' – Change note of tER_Dev from '17.8 s' to '11.5 s' – Change max value of tPRPB5_PF from 16 s to 10 s
• Package Parameters – Update table Thermal Characteristics of the Package – Change package type from PG-LFBGA-516-9 to PG-LBGA-516-1 – Change package type from PG-LFBGA-292-9 to PG-LFBGA-292-11 4.2 Changes from Versi on 0.6 to Version 0.7
• Changed step description from “AA” to “AB”
• Update of Data Flash to 512 KB in “Platform Feature Overview”
• Update AGBT to “no” in Platfo rm feature overview table
• “BBB frequency” from table “Operating Conditions
• Update Ctrl. for Pin ESR0
• Update Ctrl. for Pin ESR1
• Absolute Maximum Ratings – Change description of VDDM from 'Voltage at VDDM, VEXT and VFLEX power supply pins with respect to VSS' to 'Voltage at VDDM, VEXT, VFLEX and VEVRSB power supply pins with respect to VSS'
• Changes in table 'Overload Parameters' of Overload – Change note of IIN from 'except LVDS pins' to 'except LVDS pins; limited to max. Operation Livetime hours' – Change note of IINLVDS from '' to 'limited to max. Operation Livetime hours' – Change note of IID from 'All power supply voltages VDDx = 0' to 'All power supply voltages VDDx = 0; limited to max. Inactive Livetime hours' – Change note of IOUT from '100% duty cycle; output driver = strong' to '100% duty cycle; output driver = strong; limited to max. Operation Livetime hours' – Change of “Pin Reliabilit y in Overload” praeamble
• Changes in table 'Slow 3. 3V GPIO' of Standard Pads – Change note of VIL from '0.44 * VEXT/FLEX V' to '0.42 * VEXT/FLEX V' – Change note of IPUH from 'VIH; AL and TTL (degraded, used for CIF); exept VGATE1P and TJ > 150°C' to 'VIH; AL and TTL (degraded, used for CIF); exept VGATE1P; except VGATE1N and TJ > 150°C' OPEN MARKET VERSION

History Changes from Version 0.6 to Version 0.7 Data Sheet 399 V 1.2, 2021-03 – Change note of IPUH from 'VIL; AL and TTL and TTL (degraded, used for CIF); exept VGATE1P and TJ > 150°C' to 'VIL; AL and TTL and TTL (degraded, used for CIF); exept VGATE1P; except VGATE1N and TJ > 150°C' – Change note of IPUH from 'VIH; TTL; exept VGATE1P and TJ > 150°C' to 'VIH; TTL; exept VGATE1P; except VGATE1N and TJ > 150°C' – Change description of tSET from 'Pad set-up time' to 'Pad set-up time to get an software update of the configuration active' – Change min value of IOZ from -200 nA to -300 nA – Change max value of IOZ from 200 nA to 300 nA – Change min value of IOZ from -250 nA to -400 nA – Change max value of IOZ from 250 nA to 400 nA – Change min value of IOZ from -300 nA to -600 nA – Change max value of IOZ from 300 nA to 600 nA – Change min value of IOZ from -500 nA to -750 nA – Change max value of IOZ from 500 nA to 750 nA – Change min value of IOZ from -350 nA to -300 nA – Change max value of IOZ from 350 nA to 300 nA – Change min value of IOZ from -550 nA to -400 nA – Change max value of IOZ from 550 nA to 400 nA – Change min value of IOZ from -700 nA to -600 nA – Change max value of IOZ from 700 nA to 600 nA – Change min value of IOZ from -1100 nA to -750 nA – Change max value of IOZ from 1100 nA to 750 nA – Change max value of IOZ from 11000 nA to 18000 nA – Change note of IOZ from '-11000 nA' to '-18000 nA' – Change max value of IOZ from 22000 nA to 38000 nA – Change min value of IOZ from -22000 nA to -38000 nA

• Changes in table 'RFast 3 .3V pad' of Standard Pads – Change note of VIL from '0.44 * VEXT/FLEX V' to '0.42 * VEXT/FLEX V' – Change description of tSET from 'Pad set-up time' to 'Pad set-up time to get an software update of the configuration active'
• Changes in table 'Fast 3. 3V GPIO' of Standard Pads – Change note of VIL from '0.44 * VEXT/FLEX V' to '0.42 * VEXT/FLEX V' – Change note of IOZ from '-750 nA' to '-1100 nA' – Change note of IOZ from '750 nA' to '1100 nA' – Change min value of IOZ from -5000 nA to -6000 nA – Change note of IOZ from '5000 nA' to '6000 nA' – Change min value of IOZ from -1300 nA to -2000 nA – Change max value of IOZ from 1300 nA to 2000 nA – Change min value of IOZ from -2000 nA to -2500 nA – Change note of IOZ from '2000 nA' to '2500 nA' – Change max value of IOZ from 9000 nA to 13500 nA – Change min value of IOZ from -9000 nA to -13500 nA OPEN MARKET VERSION

History Changes from Version 0.6 to Version 0.7 Data Sheet 400 V 1.2, 2021-03 – Change note of IOZ from '-2300 nA' to '-1100 nA' – Change min value of IOZ from -5000 nA to -2000 nA – Change note of IOZ from '2300 nA' to '1100 nA' – Change max value of IOZ from 5000 nA to 2000 nA – Change description of tSET from 'Pad set-up time' to 'Pad set-up time to get an software update of the configuration active'

• Changes in table 'Fast 5V GPIO' of Standard Pads – Change max value of IOZ from 750 nA to 1100 nA – Change min value of IOZ from -750 nA to -1100 nA – Change min value of IOZ from -5000 nA to -6000 nA – Change max value of IOZ from 5000 nA to 6000 nA – Change note of IOZ from '-1300 nA' to '-2000 nA' – Change max value of IOZ from 1300 nA to 2000 nA – Change min value of IOZ from -2000 nA to -2500 nA – Change max value of IOZ from 2000 nA to 2500 nA – Change note of IOZ from '9000 nA' to '13500 nA' – Change min value of IOZ from -9000 nA to -13500 nA – Change note of IOZ from '-2300 nA' to '-1100 nA' – Change note of IOZ from '-5000 nA' to '-2000 nA' – Change max value of IOZ from 2300 nA to 1100 nA – Change max value of IOZ from 5000 nA to 2000 nA – Change description of tSET from 'Pad set-up time' to 'Pad set-up time to get an software update of the configuration active'
• Changes in table 'Slow 5V GPIO' of Standard Pads – Change note of IOZ from '-250 nA' to '-400 nA' – Change max value of IOZ from 250 nA to 400 nA – Change min value of IOZ from -350 nA to -600 nA – Change max value of IOZ from 350 nA to 600 nA – Change note of IOZ from '500 nA' to '750 nA' – Change note of IOZ from '-500 nA' to '-750 nA' – Change min value of IOZ from -200 nA to -300 nA – Change max value of IOZ from 200 nA to 300 nA – Change note of IPUH from 'VIH; AL or TTL; exept VGATE1P and TJ > 150°C' to 'VIH;AL or TTL; exept VGATE1P; except VGATE1N and TJ > 150°C' – Change note of IPUH from 'VIL; AL or TTL; exept VGATE1P and TJ > 150°C' to 'VIL; AL or TTL; exept VGATE1P; except VGATE1N and TJ > 150°C' – Change description of tSET from 'Pad set-up time' to 'Pad set-up time to get an software update of the configuration active' – Change min value of IOZ from -350 nA to -300 nA – Change max value of IOZ from 350 nA to 300 nA – Change min value of IOZ from -550 nA to -400 nA – Change note of IOZ from '550 nA' to '400 nA' – Change min value of IOZ from -700 nA to -600 nA OPEN MARKET VERSION

History Changes from Version 0.6 to Version 0.7 Data Sheet 401 V 1.2, 2021-03 – Change max value of IOZ from 700 nA to 600 nA – Change min value of IOZ from -1100 nA to -750 nA – Change max value of IOZ from 1100 nA to 750 nA – Change max value of IOZ from 11000 nA to 18000 nA – Change min value of IOZ from -11000 nA to -18000 nA – Change note of IOZ from '22000 nA' to '38000 nA' – Change min value of IOZ from -22000 nA to -38000 nA

• Changes in table 'Class S 5V' of Standard Pads – Change description of tSET from 'Pad set-up time' to 'Pad set-up time to get an software update of the configuration active' – Change min value of IOZ from -350 nA to -300 nA – Change note of IOZ from '350 nA' to '300 nA' – Change min value of IOZ from -700 nA to -600 nA – Change max value of IOZ from 700 nA to 600 nA
• Changes in table 'Class D' of Standard Pads – Change min value of IOZ from -350 nA to -300 nA – Change max value of IOZ from 350 nA to 300 nA – Change min value of IOZ from -700 nA to -600 nA – Change max value of IOZ from 700 nA to 600 nA
• Changes in table 'RFast 5V GPIO' of Standard Pads – Change description of tSET from 'Pad set-up time' to 'Pad set-up time to get an software update of the configuration active'
• Changes in table 'LVDS - IEEE st andard LVDS general purpose link (GPL)' of LVDS Pads – Add parameter tSET_LVDS – Change note of Rin from '1600 mV < VI ≤ 2000 mV' to 'VI ≤ 2000 mV'
• VADC 5V – Add parameter dVDDK – Change note of VDDK from '' to 'Measured at low temperature.' – Change note of tSCAL from '4.5V ≤ VDDM ≤ 5.5V' to '4.5 V ≤ VDDM ≤ 5.5 V' – Change note of fADCI from '4.5V ≤ VDDM ≤ 5.5V' to '4.5 V ≤ VDDM ≤ 5.5 V' – Change note of RPDD from '' to 'Measured at pad input voltage VIN = VDDM / 2.' – Change note of tSCAL from '2.97V ≤ VDDM < 4.5V' to '2.97 V ≤ VDDM < 4.5 V' – Change note of tS from 'Primary group or fast compare channel, 4.5V ≤ VDDM ≤ 5.5V; input buffer disabled' to 'Primary group or fast compare channel, 4.5 V ≤ VDDM ≤ 5.5 V; input buffer disabled' – Change note of fADCI from '2.97V ≤ VDDM < 4.5V' to '2.97 V ≤ VDDM < 4.5 V' – Change note of tS from 'Primary group or fast compare channel, 4.5V ≤ VDDM ≤ 5.5V; input buffer enabled' to 'Primary group or fast compare channel, 4.5 V ≤ VDDM ≤ 5.5 V; input buffer enabled' – Change note of tS from 'Secondary group, 4.5V ≤ VDDM ≤ 5.5V; input buffer disabled' to 'Secondary group, 4.5 V ≤ VDDM ≤ 5.5 V; input buffer disabled' – Change note of tS from 'Secondary group, 4.5V ≤ VDDM ≤ 5.5V; input buffer enabled' to 'Secondary group, 4.5 V ≤ VDDM ≤ 5.5 V; input buffer enabled' – Change note of tS from 'Primary Group or fast compare channel, 2.97V ≤ VDDM < 4.5V; input buffer disabled' to 'Primary Group or fast compare channel, 2.97 V ≤ VDDM < 4.5 V; input buffer disabled' OPEN MARKET VERSION

History Changes from Version 0.6 to Version 0.7 Data Sheet 402 V 1.2, 2021-03 – Change note of tS from 'Primary group or fast compare channel, 2.97V ≤ VDDM < 4.5V; input buffer enabled' to 'Primary group or fast compare channel, 2.97 V ≤ VDDM < 4.5 V; input buffer enabled' – Change note of tS from 'Secondary group, 2.97V ≤ VDDM < 4.5V; input buffer disabled' to 'Secondary group, 2.97 V ≤ VDDM < 4.5 V; input buffer disabled' – Change note of tS from 'Secondary group, 2.97V ≤ VDDM < 4.5V; input buffer enabled' to 'Secondary group, 2.97 V ≤ VDDM < 4.5 V; input buffer enabled' – Change of “VADC Parameters” praeamble

• DSADC 5V – Add parameter RBIAS – Change type of IREF from SR to CC
• Changes in table 'DTS Core' of DTS – Add parameter ΔT
• Current Consumption – Change max value of IDDP3RAIL from '60 mA' to '50 mA'
• Changes in table 'Module Current Consumption' of Current Consu mption – Change max value of IDDP3ERASE from 20 mA to 25 mA – Add parameter IDDP3ERASE – Change description of IDDP3ERASE from 'Current adder for' to 'IDDP3 supply current for erasing of a Pflash or Dflash bank' – Change typ value of ISCRSB from 0.190 mA to 0.150 mA – Change max value of IDDP3PROG from '8 mA' to '9 mA' – Change max value of IDDP3PROG from '20 mA' to '25 mA' – Change max value of ISCRSB from '6.5 mA' to '7 mA' – Change max value of ISCRIDLE from '1 mA' to '3.5 mA' – Change max value of IDDPORST from ''real power pattern; TJ=125°C'' to ''VDD = 1.275V; TJ=125°C'' – Change max value of IDDPORST from '190 mA' to '185 mA' – Change max value of ISLEEP from 25 mA to 27 mA
• Changes in table 'Module Core Cur rent Consumption' of Current Consumption – Change max value of IDDGTM from 120 mA to 125 mA – Change note of IDDPORST from 'real power pattern; TJ=150°C' to 'VDD = 1.275V; TJ=150°C' – Change max value of IDDPORST from 340 mA to 320 mA – Change note of IDDPORST from 'real power pattern; TJ=160°C' to 'VDD = 1.275V; TJ=160°C' – Change max value of IDDPORST from 450 mA to 400 mA – Change note of IDDPORST from ''real power pattern; TJ=165°C'' to ''VDD = 1.275V; TJ=165°C'' – Change note of IDDPORST from '490 mA' to '430 mA'
• Reset – Change max value of tBS from 1 ms to 1.05 ms – Change note of tBP from 'Firmware execution time after warm PORST without EVR ramp-up; RAM initialization and HSM boot time is not included' to 'Firmware execution time after PORST release without EVR ramp-up; RAM initialization and HSM boot time is not included' – Change description of tBP from 'Power on Reset Boot Time' to 'Cold Power on Reset Boot Time' – Change note of tLBIST from 'PATTERNS=0x00040, FREQU=5, SPLITSH=4' to 'LBIST Configuration A' – Removed parameter tLBIST with note 'PATTERNS=0x00280, FREQU=5, SPLITSH=4' OPEN MARKET VERSION

History Changes from Version 0.6 to Version 0.7 Data Sheet 403 V 1.2, 2021-03

• PMS/EVR33 LDO – Change note of dVout/dVin from ''dVin/dT=1V/ms; dV= 3.6 to 5V'' to ''dVin/dT=1V/ms; dV= 3.6 to 5V; ΔVOUTTC is included'' – Change note of dVout/dVin from '20 mV' to '40 mV' – Change min value of dVout/dVin from -20 mV to -40 mV – Change note of dVout/dVin from 'dVin/dT=1V/ms; dV= 5 to 3.6V' to 'dVin/dT=1V/ms; dV= 5 to 3.6V; ΔVOUTTC is included' – Add parameter dVOUTTC – Change note of tSTR from '' to 'Normal RUN mode'
• PMS/Supply Monitors – Change max value of VRSTC from 1.135 V to 1.138 V
• Changes in table 'EVRC SMPS' of PMS/EVRC SMPS – Change max value of Δ VDDDC from 12 mV to 16 mV
• PLL Peripheral – Add parameter JABS25 – Change note of DP from 'fDCO = 640 MHz' to 'fDCO = 640 MHz or fDCO = 800 MHz' – Change note of DRMS from 'measured over 1 µs; fREF = 20 MHz; fDCO = 640 MHz' to 'measured over 1 µs; fREF = 20 MHz and fDCO = 640 MHz or fREF = 25 MHz and fDCO = 800 MHz'
• F l a s h – Change note of NE_HSMS from 'Max. data retention time 10 years' to 'max data retention time 20y, Tj=85°C' – Change note of NE_EEP10S from 'Max. data retention time 10 years' to 'max data retention time 20y, Tj=85°C' – Add parameter NE_EEP10S – Change max value of NE_EEP10S to 125000 cycles – Add parameter NE_EEP10S – Change max value of NE_EEP10S to 125000 cycles – Add parameter NE_EEP10S – Change max value of NE_EEP10S to 70000 cycles – Add parameter NE_HSMS – Change max value of NE_HSMS to 125000 cycles – Add parameter NE_HSMS – Change max value of NE_HSMS to 125000 cycles – Add parameter NE_HSMS – Change max value of NE_HSMS to 70000 cycles – Add inactive time to Table 3-75 “Example Temperature Profile”
• Package Parameters – Update table layout for table 3-67 – Change max value of RTH_JA from 14,8 K/W to 17 K/W – Change max value of RTH_J A from 12 K/W to 14 K/W – Change name of RTH_JA from Thermal resistance (junction to ambient) to RTH_JA – Change description of RTH_JA from '' to 'Thermal resistance (junction to ambient)' – Change max value of RTH_JCT from 4.5 K/W to 3 K/W – Change max value of RTH_JCT from 4.7 K/W to 3 K/W OPEN MARKET VERSION

History Changes from Version 0.7 to Version 0.71 Data Sheet 404 V 1.2, 2021-03 – Change max value of RTH_JCB from 2.8 K/W to 2 K/W – Change description of RTH_JCB from '' to 'Thermal resistance (junction to case bottom)' – Change note of RTH_JCB fro m '3.5 K/W' to '2 K/W' 4.3 Changes from Versi on 0.7 to Version 0.71

• P i n n i n g – Corrected descriptions of HSCT pins – Corrected descriptions of CCU_PAD_SYSCLK pin
• Summary of Features – Included RGMII in the Ethernet description
• Platform featu re overview – Corrected number of SDMMC modules from ‘1’ to ‘0’ – Corrected the value of MCDS from “yes” to “no” – Corrected number of QSPI modules from ‘6’ to ‘5’
• Corrected ‘LVDSH’ to ‘LVDS’ in Section ‘High performance LVDS Pads’
• Changes in table "Absolute Maximum Ratings" – Change value of Parameter "VDDM" – Change value of Parameter "VIN"
• Change preamble of Section "Overload"
• Changes in table "Overload Param eters" of Section "Overload" – Change condition of Parameter "IIN" – Change condition of Parameter "IINLVDS" – Change condition of Parameter "IOUT" – Change condition of Parameter "IINANA" – Delete Parameter "IID"
• Changes in table "PORST Pad" of Section "Switchable Pads" – Change refer ence voltage of Parameters and values from "VEXT/FLEX" to “VEXT”
• Changes in table "Class S" of Section "Switchable Pads" – Change refer ence voltage of Parameters and values from "VEXT/FLEX" to “VDDM”
• Changes in table "RFast 3.3V pad" of Section "Switchable Pads" – Change refer ence voltage of Parameters and values from "VEXT/FLEX" to “VFLEX”
• Changes in table "RFast 5V pad" of Section "Switchable Pads" – Change refer ence voltage of Parameters and values from "VEXT/FLEX" to “VFLEX”
• Changes in table "Fast 3.3V pad " of Section "Switchable Pads" – Change refer ence voltage of Parameters and values from "VEXT/FLEX" to “VEXT/FLEX/EVRSB”
• Changes in table "Fast 5V pad" of Section "Switchable Pads" – Change refer ence voltage of Parameters and values from "VEXT/FLEX" to “VEXT/FLEX/EVRSB”
• Changes in table "Slow 3.3V pad " of Section "Switchable Pads" – Change refer ence voltage of Parameters and values from "VEXT/FLEX" to “VEXT/FLEX/EVRSB”
• Changes in table "Slow 5V pad" of Section "Switchable Pads" – Change refer ence voltage of Parameters and values from "VEXT/FLEX" to “VEXT/FLEX/EVRSB” OPEN MARKET VERSION

History Changes from Version 0.7 to Version 0.71 Data Sheet 405 V 1.2, 2021-03

• Changes in table "VADC 5V" – Add footnote to Parameter "QCON" – Update picture ‘Equivalent Circuitry for Analog Inputs’
• Changes in table "DSADC 5V" – Change value of Parameter "EDGAIN" – Change value of Parameter "EDOFF" – Add footnote to Parameter "EDOFF" – Change value of Parameter "IREF" – Change value of Parameter "IRMS" – Add footnote to Parameter "IRMS" – Add footnote to Parameter "SNR" – Add footnote to Parameter "SFDR"
• Changes in table "Current Consumption" – Change Parameter description of "IDDRAIL" – Change condition of Parameter "ISTANDBY" – Change value of Parameter "ISTANDBY" – Change footnote of Parameter "ISTANDBY"
• Changes in table "Module Core Cu rrent Consumption" of Section "Current Consumption" – Change condition of Parameter "IDDLBIST" – Change value of Parameter "IDDLBIST" – Add footnote to Parameter "IDDLBIST" – Add footnote to Parameter “ISCRSB” – Change condition of Parameter "IDDMBIST"
• Added section "Calculating the 1.25V Current Consumption"
• Changes in table "Reset" – Change value of Parameter "tB" – Change value of Parameter "tBS" – Add footnote to Parameter "tEVRPOR" – Change value of Parameter "tBWP" – Change condition of Parameter "tLBIST" – Change Parameter de scription of "tLBIST"
• Changes in table "EVR33 LDO" – Change condition of Parameter "dVout/dIout" – Change condition of Parameter "Vout/dVin" – Change footnote of Parameter "IMAX"
• Changes in table "Supply Monitors" – Change condition of Parameter "tMON" – Change condition of Parameter"VDDMON" – Change condition of Parameter "VDDP3MON" – Change condition of Parameter "VEXTMON" – Add footnote to P arameter "VEXTMON" – Change condition of Parameter "VRST5" OPEN MARKET VERSION

History Changes from Version 0.71 to Version 1.0 Data Sheet 406 V 1.2, 2021-03

• Changes in table "Flash" – Change condition of Parameter "NE_EEP10S" – Remove condition of Parameter "NE_EEP10S" – Change condition of Parameter "NE_HSMS" – Remove condition of Parameter "NE_HSMS"
• Changes in table "Quality Parame ters" of Section "Quality Declarations" – Change Parameter description of "VHBM1"
• Add Section "TC380 Carrier Tape"
• O S C _ X T A L – Removed parameter VILBX – Removed parameter VIHBX
• Changes in table "Back-up Clock" – Update footnote of Parameters “fBACKT"
• Changes in table "PLL Peripheral" – Add Parameters “DPP" – Add Parameters “DPPI"
• Changes in table "Receive Param eters" of “E-ray Parameters” – Update Parameters description of “tdCCRxD01" 4.4 Changes from Versi on 0.71 to Version 1.0
• Changes in chapter “Summary of Features” – Changed LMU Memory size from 128 Kbyte to 256 Kbyte
• P i n n i n g – Corrected descriptions of Column “Buffer Type”: PU2
• Changes in chapter Ele ctrical Specification – Corrected/ added wording in sub-chapter 3.1 “Parameter Interpr etation” – Added naming for temperature va lue, table 3-66, Example Operation Lifetime Profile – Changed naming for sub-chapter 3.16, from Phase Locked Loop (P LL) to System Phase Locked Loop (SYS_PLL) – corrected temperature in “S ummary of Features” section
• Changes in Absolute Maximum Table – Add footnote 2) to VDD
• Changes in Operating Conditions Table – Add footnote 1) to VDD
• Changes in table 'PORST Pad' of Standard Pads – Change min value of HYS from 0.055 * VEXT/FLEX V to 0.055 * VEXT V – Change note of IOZ from 'TJ≤150°C ; (0.1 * VEXT/FLEX) < VIN < (0.9 * VEXT/FLEX)' to 'TJ≤150°C ; (0.1 * VEXT) < VIN < (0.9 * VEXT)' – Changed footnote 1) from 10% to 90% VEXT/FLEX 10% to 90% pad supply voltage – Add footnote 2) to IPDL OPEN MARKET VERSION

History Changes from Version 0.71 to Version 1.0 Data Sheet 407 V 1.2, 2021-03 – Add parameter VIH for condition TTL, VEXT – Add parameter VIL for condition TTL, VEXT

• Changes in table 'Fast 5V GPIO' of Standard Pads – Change min value of VIH from 0.7 * VEXT/FLEX V to 0.7 * VEXT/FLEX/EVRSB V – Change note of VIL from '0.44 * VEXT/FLEX V' to '0.44 * VEXT/FLEX/EVRSB V' – Change note of VILD from 'max. variation of 1ms; VDDM = constant; AL' to 'max. variation of 1ms; VEXT/FLEX/EVRSB = constant; AL' – Combined equal values of IOZ in single line – Add footnote 4) to IPUH – Add footnote 5) to IPDL
• Changes in table 'Fast 3. 3V GPIO' of Standard Pads – Change min value of VIH from 0.7 * VEXT/FLEX V to 0.7 * VEXT/FLEX/EVRSB V – Change note of VIL from '0.42 * VEXT/FLEX V' to '0.42 * VEXT/FLEX/EVRSB V' – Change note of VILD from 'max. variation of 1ms; VDDM = constant; AL' to 'max. variation of 1ms; VEXT/FLEX/EVRSB = constant; AL' – Combined equal values of IOZ in single line – Add footnote 4) to IPUH – Add footnote 5) to IPDL
• Changes in table 'Slow 5V GPIO' of Standard Pads – Change min value of VIH from 0.7 * VEXT/FLEX V to 0.7 * VEXT/FLEX/EVRSB V – Change note of VIL from '0.44 * VEXT/FLEX V' to '0.44 * VEXT/FLEX/EVRSB V' – Change note of VILD from 'max. variation of 1ms; VDDM = constant; AL' to 'max. variation of 1ms; VEXT/FLEX/EVRSB = constant; AL' – Combined equal values of IOZ in single line – Add footnote 4) to IPUH – Add footnote 5) to IPDL
• Changes in table 'Slow 3. 3V GPIO' of Standard Pads – Change min value of VIH from 0.7 * VEXT/FLEX V to 0.7 * VEXT/FLEX/EVRSB V – Change note of VIL from '0.42 * VEXT/FLEX V' to '0.42 * VEXT/FLEX/EVRSB V' – Change note of VILD from 'max. variation of 1ms; VDDM = constant; AL' to 'max. variation of 1ms; VEXT/FLEX/EVRSB = constant; AL' – Combined equal values of IOZ in single line – Add footnote 4) to IPUH – Add footnote 5) to IPDL
• Changes in table 'RFast 5V GPIO' of Standard Pads – Change min value of HYS from 0.09 * VEXT/FLEX V to 0.09 * VFLEX V – Change note of HYS from '0.075 * VEXT/FLEX V' to '0.075 * VFLEX V' – Change min value of VIH from 0.7 * VEXT/FLEX V to 0.7 * VFLEX V – Change note of VIL from '0.44 * VEXT/FLEX V' to '0.44 * VFLEX V' – Change note of tRF from 'CL = 25pF; driver = strong sharp edge; from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX' to 'CL = 25pF; driver = strong sharp edge; from 0.2 * VFLEX to 0.8 * VFLEX' – Change note of IOZ from 'TJ ≤ 170°C ; (0.1 * VEXT/FLEX) < VIN < (0.9 * VEXT/FLEX)' to 'TJ ≤ 170°C ; (0.1 * VFLEX) < VIN < (0.9 * VFLEX)' OPEN MARKET VERSION

History Changes from Version 0.71 to Version 1.0 Data Sheet 408 V 1.2, 2021-03 – Change note of IOZ from 'TJ ≤ 150°C ; (0.1 * VEXT/FLEX) < VIN < (0.9 * VEXT/FLEX)' to 'TJ ≤ 150°C ; (0.1 * VFLEX) < VIN < (0.9 * VFLEX)' – Change note of VILD from 'max. variation of 1ms; VDDM = constant; AL' to 'max. variation of 1ms; VFLEX = constant; AL' – Add footnote 4) to IPUH – Add footnote 5) to IPDL

• Changes in table 'RFast 3 .3V pad' of Standard Pads – Change min value of HYS from 0.055 * VEXT/FLEX V to 0.055 * VFLEX V – Change min value of HYS from 0.09 * VEXT/FLEX V to 0.09 * VFLEX V – Change min value of HYS from 0.055 * VEXT/FLEX V to 0.055 * VFLEX V – Change note of VIH from '0.7 * VEXT/FLEX V' to '0.7 * VFLEX V' – Change note of VIL from '0.42 * VEXT/FLEX V' to '0.42 * VFLEX V' – Change note of tRF from 'CL = 25pF; driver = strong sharp edge; from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX' to 'CL = 25pF; driver = strong sharp edge; from 0.2 * VFLEX to 0.8 * VFLEX' – Change note of IOZ from 'TJ ≤ 170°C ; (0.1 * VEXT/FLEX) < VIN < (0.9 * VEXT/FLEX)' to 'TJ ≤ 170°C ; (0.1 * VFLEX) < VIN < (0.9 * VFLEX)' – Change note of VILD from 'max. variation of 1ms; VDDM = constant; AL' to 'max. variation of 1ms; VFLEX = constant; AL' – Add footnote 4) to IPUH – Add footnote 5) to IPDL
• Changes in table 'Class S 5V' of Standard Pads – Change min value of HYS from 0.09 * VEXT/FLEX V to 0.09 * VDDM V – Change min value of HYS from 0.075 * VEXT/FLEX V to 0.075 * VDDM V – Change min value of VIH from 0.7 * VEXT/FLEX V to 0.7 * VDDM V – Change note of VIL from '0.44 * VEXT/FLEX V' to '0.44 * VDDM V' – Add footnote 2) to IPUH – Add footnote 3) to IPDL
• Add table 'Class S 3.3V' of Standard Pads
• Changes in table 'ADC Refer ence Pads' of Standard Pads – Change note of IOZ2 from 'TJ ≤ 150°C; VAREF ≤ VDDM+50mV; used for EVADC' to 'TJ ≤ 150°C; VAREF ≤ VDDM+50mV; for EVADC; valid for BGA516 and Bare Die' – Change note of IOZ2 from 'TJ ≤ 150°C; VAREF < VDDM; used for EDSADC' to 'TJ ≤ 150°C; VAREF < VDDM; for EDSADC' – Change note of IOZ2 from 'TJ ≤ 150°C; VAREF ≤ VDDM+50mV; used for EDSADC' to 'TJ ≤ 150°C; VAREF ≤ VDDM+50mV; for EDSADC' – Change value of IOZ2 from 'TJ ≤ 150°C; VAREF < VDDM; used for EVADC' to 'TJ ≤ 150°C; VAREF < VDDM; for EVADC; valid for BGA516 and Bare Die' – Change note of IOZ2 from 'TJ ≤ 170°C; VAREF < VDDM; used for EDSADC' to 'TJ ≤ 170°C; VAREF < VDDM; for EDSADC' – Change note of IOZ2 from 'TJ ≤ 170°C; VAREF ≤ VDDM+50mV; used for EDSADC' to 'TJ ≤ 170°C; VAREF ≤ VDDM+50mV; for EDSADC' – Change note of IOZ2 from 'TJ ≤ 170°C; VAREF ≤ VDDM+50mV; used for EVADC' to 'TJ ≤ 170°C; VAREF ≤ VDDM+50mV; for EVADC; valid for BGA516 and Bare Die' OPEN MARKET VERSION

History Changes from Version 0.71 to Version 1.0 Data Sheet 409 V 1.2, 2021-03 – Change note of IOZ2 from 'TJ ≤ 170°C; VAREF < VDDM; used for EVADC' to 'TJ ≤ 170°C; VAREF < VDDM; for EVADC; valid for BGA516 and Bare Die' – Added values for IOZ2 – Add footnote 1) – Add footnote 2) – Add footnote 3)

• LVDS - IEEE standa rd LVDS general purpose link (GPL) – Added footnote 1) for max. value trise20 – Added footnote 2) for max. value tfall20 – Changed footnote number 1) for VOD to footnote number 3) – Changed footnote number 2) for VODSM to footnote number 4) – Changed marking in figure 'LVDS Input model' from 'LVDSH IN' to 'LVDS IN'
• VADC 5V – Change note of VAREF from '' to '4.5 V ≤ VDDM ≤ 5.5 V' – Change min value of VAREF from VDDMnom * 0.9 V to 4.5 V – Add min value of VAREF – Add typ value of VAREF – Add max value of VAREF – Add note of VAREF to '2.97 V ≤ VDDM ≤ 4.5 V' – Add footnote 1)
• DSADC 5V – Change min value of VAREF from VDDMnom * 0.9 V to 4.5 V – Add max value of IREF at high temperature
• O S C _ X T A L – Add parameter for DCx1 – Add parameter for JABSX1 – Add parameter for SRXTAL1 – Add footnote 3)
• Back-up Clock – Change min value of fSB from 30 kHz to 25 kHz – Change note of IfBACKT from 'A short term trimming providing the accuracy required by LIN communication is possible by periodic trimming every 2 ms for temperature and voltage drifts ' to 'A short term trimming providing the accuracy required by LIN communication is possible by periodic trimming every 2 ms for temperature and voltage drifts up to temperatures of 125 celcius'
• D T S – Change note of TNL from ‘’ to ‘TCALACC has to be added in addition’
• Power Supply Current – Changes in conditions from 'four lockstep cores' to 'two locks tep cores'
• Current Consumption – Change max value of IDDPORST from '185 mA' to '160 mA' – Change max value of IDDPORST from '320 mA' to '290 mA' – Change max value of IDDPORST from '400 mA' to '350 mA' OPEN MARKET VERSION

History Changes from Version 0.71 to Version 1.0 Data Sheet 410 V 1.2, 2021-03 – Change max value of IDDPORST from '430 mA' to '380 mA' – Changed footnote 3)

• Module Current Consumption – Add parameter of IEXTLVDS for receive
• Module Core Current Consumption – Changed footnote 1)
• Changes in chapter “Calculating the 1.25 V Current Consumption” – Changes in formula (3.2)
• Changes in chapter “Supply Ramp-up and Ramp-down Behavior” – Changed Figure and tex tual description for figure “Single Supply Mode (a) - VEXT (5 V) single supply” – Changed Figure and textual description for figure “Single Supp ly Mode (e) - (VEXT & VDDP3) 3.3 V single supply” – Changed Figure and tex tual description for figure “Single Supply Mode (d) - VEXT and VDD externally supplied” – Changed Figure and tex tual description for figure “Single Supply Mode (h) - VEXT, VDDP3 and VDD externally supplied”
• Reset Timing – Add parameter tWARMRSTSEQ
• PMS/Supply Monitors – Changed min value of VEXTMON from '3.235 V to 3.2 V', and max value from '3.365 V' to '3.4 V' – Added footnote 5) for VDDMON
• EVRC SMPS – Added typ. value of '0.8 MHz' and note for fDCDC – Added values for LDC for 'fDCDC = 0.8 MHz'
• Add chapter FSP Parameters
• PLL System – Deleted values for fMV for 'Modulation variation frequency'
• Table 'Master Mode Timing' – Added footnote 1)
• Table 'LVDS clock/data' – Added footnote 3)
• F l a s h – Add parameter for NDFDC – Add parameter for NUCBD – Add parameter tVER_PAGE_DC – Change description of tVER_PAGE_DC from 'Data Flash Erase Verify time per page' to 'Data Flash Erase Verify time per page (Complement Sensing)' – Change name of tVER_PAGE_DS from tVER_PAGE_D to tVER_PAGE_DS – Change description of tVER_PAGE_DS from 'Data Flash Erase Verify time per page' to 'Data Flash Erase Verify time per page (Single Ended Sensing)' – Change note of tRTU from ’Max. 100 erase/program cycles per UCB, max 400 erase/program cycles for all UCBs together’ to ‘Max. 100 erase/program cycles per UCB, max 500 erase/program cycles for all UCBs together’ OPEN MARKET VERSION

History Changes from Version 1.0 to Version 1.1 Data Sheet 411 V 1.2, 2021-03

• Package Parameters – Change max value of RTH_JCT from 3 K/W to 5 K/W for LFBGA292 – Change max value of RTH_JCT from 3 K/W to 5 K/W for LFBGA516
• TC380 Carrier Tape – Added disclaimer for TC380 – Changed X and Y values for 'TC380 Chip Dimensions' – Changed figure for 'Carrier Tape Dimensions' – Added accuracy value for 'TC380 Chip Dimensions'
• Summary of Features – Removed ASIL value from table 'Platform Feature Overview' 4.5 Changes from Versi on 1.0 to Version 1.1
• Changes in table “Platform Feature Overview” - changed package types
• Changes on title page and c hapter heads – AD/AE-Step”
• Changes in table “Platform Feature Overview” – package naming spelling of LFBGA-516-1 and LFBGA-292-11
• Change in table “Platf orm Feature Overview” – spelling of “HSPDM”
• Chapter “Bare Die Variant Pin Configuration of TC38x” - added information concerning “neighbor pads” after table “Pad List”
• Changes in chapter “Legend” – Added information concerning I/O-Spirit file version – Changed refering IO_Spirit_file version – Changed explanation fo r PD2 = with pull-down device connected during startup and reset, HighZ in Standby mode
• Changes in table “Absol ute Maximum Ratings” – Changed description for para meter “Absolute maximum sum” – Added footnote 5)
• Changes in table 'Slow 5V GPIO' of Standard Pads – Changed conditions of parameter IOZ – Changed value of parameter VIL
• Changes in table “Slow 3. 3V GPIO” of Standard Pads – Changed conditions of parameter IOZ
• Changes in table “RFast 3 .3V pad” of Standard Pads – Deleted parameter for fIND
• Changes in table “LVDS - IEEE s tandard LVDS general purpose link (GPL)” of LVDS Pads – Changed value of parameter VI – Changed condition of parameter Vidth – Added values for parameter Vidth – Changed condition of parameter Rin – Added notes/ hints to table foo tnotes for “Driver ground potential difference” and for parameter “RT”
• Changes in table “VADC 5V” – Added condition for parameter VAIN OPEN MARKET VERSION

History Changes from Version 1.1 to Version 1.2 Data Sheet 412 V 1.2, 2021-03

• Changes in table “DSADC 5V” – Added value for parameter IRMS – Changed footnotes of parameter EDGAIN – Changed footnotes of parameter EDOFF – Added footnote 4) for parameter EDGAIN
• Changes in table “OSC_XTAL” – Changed footnote 1) for parameter tOSCS
• Changes in table “Current Consumption” – Deleted footnote 1) for parameter IEXTFLEX – Changed value in footnote 1) – Changed explanation in footnote 6)
• Changes in table “Modul e Current Consumption” – Changed values of parameter IEXTLVDS – Changed conditions of parameter IEXTLVDS – Changed value in footnote 6)
• Changes in table “Reset” – Changed values of parameter tSCR
• Changes in table “Supply Ramp” – Added note “power-cycles” to supply ramp table
• Changes in table “EVRC SMPS” – Changed symbol for parameter “∆ fDCSPR”
• Changes in table “PLL System” – Changed value for parameter fREF
• Changes in table “ETH RGMII Parameters” – Added figures for ETH RG MII TX and RX signals
• Changes in table “Quality Parameters” – Changed value for parameter VHBM1
• Changes in chapter “Package Outline” - changed package types
• Changes in sub-chapter “TC380 Carrier Tape” – Changed number of figure “Carrier Tape Dimensions” 4.6 Changes from Versi on 1.1 to Version 1.2
• Changes in chapter “Revision History” – Chronology completed
• Changes in chapter “Summary of Features” – Changed wording for “DFLASH” – Added description for “AEC-Q100” – Added description for “ ISO 26262 Safety Element” – Added description for Data Flas h in table “Platform Feature Overview” – Changed figure for GTM clusters i n table “Platform Feature Overview” OPEN MARKET VERSION

History Changes from Version 1.1 to Version 1.2 Data Sheet 413 V 1.2, 2021-03 – Changed figures for GTM/CDTM/DTM modules in table “Platform Fe ature Overview” – Changed package type in tabl e “Platform Feature Overview”

• Changes in chapter “Pin Definition and Functions” – Changed EDSADC function descrip tion for Port 00 in “BGA-516 Package Variant” tables – Changed EDSADC function descrip tion for Port 01 in “BGA-516 Package Variant” tables – Changed EDSADC function descrip tion for Port 02 in “BGA-516 Package Variant” tables – Changed PSI5S function description for Port 02 in “BGA-516 Pac kage Variant” tables – Deleted PMS parameter for Port 02 in “BGA-516 Package Variant” tables – Deleted SCU parameter at Port 1 0 in “BGA-516 Package Variant” tables – Added PMS parameter at Port 10 in “BGA-516 Package Variant” ta bles “BGA-516 Package Variant” tables – Changed function description for GETH at Port 11 in “BGA-516 Package Variant” tables – Changed function description for GTM at Port 11 in “BGA-516 Package Variant” tables – Deleted parameter for SCU at Po rt 14 in “BGA-516 Package Variant” tables – Added parameter for PMS at Port 14 in “BGA-516 Package Variant ” tables – Changed function description for GTM at Port 14 in “BGA-516 Package Variant” tables – Changed function description for HSCT0 at Port 20 in “BGA-516 Package Variant” tables – Changed function description for GTM at Port 20 in “BGA-516 Package Variant” tables – Added function description for D MU at Port 21 in “BGA-516 Package Variant” tables – Changed function description for HSCT0 at Port 21 in “BGA-516 Package Variant” tables – Changed function description for GTM at Port 23 in “BGA-516 Package Variant” tables – Changed EDSADC function descrip tion for Port 33 in “BGA-516 Package Variant” tables – Changed function description for GTM at Port 33 in “BGA-516 Package Variant” tables – Changed PSI5S function description for Port 33 in “BGA-516 Pac kage Variant” tables – Added notes to table “System I/O ” for “BGA-516 Package Variant” – Changed “Ctrl.” information fo r balls M21, L21 in “System I/O” table for “BGA-516 Package Variant” – Changed function description fo r ball M22 in “System I/O” table for “BGA-516 Package Variant” – Changed “Ctrl.” information fo r balls M22 in “System I/O” table for “BGA-516 Package Variant” – Changed function descriptions fo r EDSADC at Port 00 in “BGA-292 Package Variant” tables – Changed function descriptions fo r EDSADC at Port 01 in “BGA-292 Package Variant” tables – Changed function descriptions fo r EDSADC at Port 02 in “BGA-292 Package Variant” tables – Changed function descriptions fo r PSI5S at Port 02 in “BGA-292 Package Variant” tables – Changed GTM input channel at Por t 02 in “BGA-292 Package Variant” tables – Deleted parameter for PMS at Po rt 02 in “BGA-292 Package Variant” tables – Deleted parameter for SCU at Po rt 10 in “BGA-292 Package Variant” tables – Added parameter for PMS at Port 10 in “BGA-292 Package Variant ” tables “BGA-292 Package Variant” tables – Changed function description for GETH at Port 11 in “BGA-292 Package Variant” tables OPEN MARKET VERSION

History Changes from Version 1.1 to Version 1.2 Data Sheet 414 V 1.2, 2021-03 – Changed GTM input channel at Por t 11 in “BGA-292 Package Variant” tables – Deleted parameter for SCU at Po rt 14 in “BGA-292 Package Variant” tables – Added parameter for PMS at Port 14 in “BGA-292 Package Variant ” tables – Changed GTM input channel at Por t 14 in “BGA-292 Package Variant” tables – Added function description for D MU at Port 21 in “BGA-292 Package Variant” tables – Changed function description for HSCT0 at Port 21 in “BGA-292 Package Variant” tables – Changed GTM input channel at Por t 23 in “BGA-292 Package Variant” tables – Changed function descriptions fo r EDSADC at Port 33 in “BGA-292 Package Variant” tables – Changed GTM input channel at Por t 33 in “BGA-292 Package Variant” tables – Changed PSI5S function description for Port 33 in “BGA-292 Pac kage Variant” tables – Added notes to table “System I/O ” for “BGA-292 Package Variant” – Changed “Ctrl.” information for balls G16, F16, G17 in “System I/O” table for “BGA-292 Package Variant” – Changed function description fo r ball G17 in “System I/O” table for “BGA-292 Package Variant” – Changed sub-chapter title from “Bare Die Variant Pin Configuration of TC38x” to “Sequence of Pads in Pad Frame” – Changed comments for pad name V DDP3 (62, 64) in Pad List of “Sequence of Pads in Pad Frame” “Sequence of Pads in Pad Frame” – Changed comments for pads 158, 159 in Pad List of “Sequence of Pads in Pad Frame” – Changed pad names for pads 198, 2 17, 218, 352, 383 in Pad List of “Sequence of Pads in Pad Frame” – Changed/ revised footnote for table Pad List of “Sequence of P ads in Pad Frame”

• Changes in chapter “Legend” – Changed version number of “TC38xpd_IO_Spirit” file
• Changes in chapter “El ectrical Specification” – Typos corrected in footnotes for sub-chapter “Absolute Maximum Ratings” – Typo corrected for parameter IINSA in table “Overload Parameters” of sub-chapter “Pin Reliability in Overload” – Changed values for parameter GE TH frequency in table “Operating Conditions” – Changed note for parameter tTX_ASYM in table “Fast 5V GPIO” of sub-chapter “5V/3.3V switchable Pads” – Changed note for parameter tTX_ASYM in table “Fast 3.3V GPIO” of sub-chapter “5V/3.3V switchable Pads” – Changed note for parameter tTX_ASYM in table “Slow 5V GPIO” of sub-chapter “5V/3.3V switchable Pads” – Changed note for parameter tTX_ASYM in table “Slow 3.3V GPIO” of sub-chapter “5V/3.3V switchable Pads” – Changed note for parameter tTX_ASYM in table “RFast 5V GPIO” of sub-chapter “5V/3.3V switchable Pads” – Changed note for parameter tTX_ASYM in table “RFast 3.3V pad” of sub-chapter “5V/3.3V switchable Pads” – Changed notes for parameter IOZ2 in table “ADC Reference Pads” of sub-chapter “5V/3.3V switchable Pads” – Typos corrected in fo otnote 3) for table “LVDS – IEEE standard LVDS general purpose link (GPL)” in sub- chapter “High performance LVDS Pads” – Added footnote content for tab le “LVDS – IEEE standard LVDS general purpose link (GPL)” in sub-chapter “High performance LVDS Pads” OPEN MARKET VERSION

History Changes from Version 1.1 to Version 1.2 Data Sheet 415 V 1.2, 2021-03 – Typo corrected for parameter dVCSD in table “VADC 5V” in sub-chapter “VADC Parameters” – Changed footnote 7) of table “ VADC 5V” in sub-chapter “VADC Parameters” – Changed figure “Equivalent Circuitry for Analog Inputs” in sub -chapter “VADC Parameters” – Changed footnotes 3) and 6) for table "VADC 5V" in sub-chapter "VADC Parameters" – Changed value of parameter IRMS in table “DSADC 5V” in sub-chapter “DSADC Parameters” – Changed footnote 4) in sub-c hapter “DSADC Parameters” – Changed spelling in f ootnote 2) in sub-chapter “MHz Oscillator” – Changed spelling in initial text for sub-chapter “Power Supply Current” – Changed footnote 2) for table “Current Consumption” in sub-cha pter “Power Supply Current” – Added footnote 7) for table “Cu rrent Consumption” in sub-chapter “Power Supply Current” – Typos corrected in sub-chapter “Calculating the 1.25V Current Consumption” – Added sentence to sub-chapter “Supply Ramp-up and Ramp-down Be havior” – Changed/added value for parameter tPI in table “Reset” for sub-chapter “Reset Timing” – Changed figure “DAP Timing” in s ub-chapter “DAP Parameters” – Changed values (from Min . to Typ.) for parameter t7 in table “ETH MII Signal Timing Parameters” for sub- chapter “ETH MII Parameters” – Changed symbols for parameters t13, t14, t15 in table “ETH RMII Signal Timing Parameters valid for 3.3V” in sub-chapter “ETH RMII Parameters” – Changed value (from Min. to Typ.) for parameter t13 in table “ETH RMII Signal Timing Parameters valid for 3.3V” in sub-chapter “ETH RMII Parameters” – Added footnote 3) for table “ETH RMII Signal Timing Parameters valid for 3.3V” in sub-chapter “ETH RMII Parameters” – Changed figure title to “Package Outlines FBGA-516” in sub-cha pter “Package Outline” – Changed notes in table “Package Parameters” to “FBGA” for sub- chapter “Package Parameters” – Deleted sub-chapter “TC380 Carrier Tape” OPEN MARKET VERSION

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