TC35661SBG-551 TOSHIBA | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 2.1 Pin Functions
- 2.2 System Configuration Example
Datasheet sections
©2017 TOSHIBA Corporation 2017-01-05 1 TC35661SBG-551 Bluetooth® IC ROM Profile Series Rev. 1.0 The Bluetooth® word mark and logos are registered trademarks owned by Bluetooth SIG, Inc. ARM is a registered trademark of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved.
This data sheet consists of two parts describing the firmware and the hardware. The chapter of the firmware describes the functions of the firmware built in the ROM of the IC. The chapter of the hardware describes the functions of the hardware. Some functions are not supported by the firmware depending on ROM versions. Please refer to the chapter of the firmware for details.
Bluetooth® IC ROM Profile Series SPP+GATT Rev 1.01
- General Description 1.1. Product Concept TC35661 is the 1-chip CMOS IC for Bluetooth® communication, which includes an RF analog part and a Baseband digital part. Each supported function depends on ROM version. TC35661-551 is TC35661 with ROM version 551. It supports both SPP (Serial Port Profile) and GATT (Bluetooth® Low Energy). 1.2. Features SPP (Serial Port Profile) and GATT (Generic Attribute Profile) UART as Host CPU Interface Baud rate from 2400 bps to 3.25 Mbps (Default 115200 bps) 4- wire EEPROM control I 2C interface API for General Purpose I/O (GPIO) control 19 ports (with pull-up and pull-down resistors) API for Wake-up Interface Wake-up input Wake-up status output Host wake-up output API for Low power mode Sleep function Wake up by UART command Wake up by GPIO0 input Selectable source of the sleep clock 32.768 kHz (External input or Clock divided from 26 MHz) Synchronization signal output For LED blinking function Figure 1-1 Diagram of Bluetooth® Stack in TC35661-551 Physical Layer HCI SDP GAP L2CAP RFCOMM GAP SMP ATT GATT Service Database API BR function LE function BR/EDR Baseband LE Link Layer SPP
1.3. Bluetooth® Support Feature List Table 1-1 Support Feature List Items Description Status Bluetooth® Core Version 4.2 Power Class 2 Basic Rate (BR) Supported Bluetooth® low energy (LE) Supported High Speed (HS) Not Supported Bluetooth® (BR/EDR) Sniff Supported Park/Hold Not Supported BR- 3slot packet Supported BR- 5slot packet Supported EDR Not Supported Extended Inquiry Response Supported Interlaced Inquiry/Page Scan Supported Read RSSI Supported Secure Simple Pairing Supported Power Control Supported Enhanced Power Control Supported AFH Supported SCO/eSCO Not Supported CQDDR Not Supported Sniff subrating Supported SPP Supported (Initiator and Acceptor) SPP UUID Assignment Supported Multi Profile / Multi point connection Not supported
Bluetooth® (LE) Central Not Supported Peripheral Supported ConnectionUpdate Supported Random Address Supported WhiteList Supported LE Legacy Pairing Supported LE Secure Connection (V4.2) Supported GATT-Client Supported GATT-Server Supported Broadcaster (Advertising) Supported Observer (Scan) Not Supported MAX MTU size 160 bytes Read RSSI Supported Multi point connection Not Supported Scatternet (V4.1) Not Supported LE Encryption Supported Connection parameters Request Procedure (V4.1) Not Supported Extended Reject Indication (V4.1) N ot Supported Slave-initiated Feature Exchange (V4.1) Not Supported LE Ping(V4.1) Not Supported LE Data Packet Length Extension (V4.2) Not Supported LL Privacy(V4.2) Not Supported Extended Scanner Filter Policies (V4.2) Not Supported Low Duty cycle Directed Advertising (V4.1) Not Supported LE L2CAP Connection Oriented Channel (V4.1) Not Supported 32-bit UUID support in LE (V4.1) Supported Bluetooth® Dual mode BR Page/Inquiry scan and LE Advertising simultaneously Supported SPP+GATT connection establishment simultaneously Not Supported Interface UART Baudrate 115200 bps (default). Selected by command. UART Protocol UART Transport Layer (Core4.2 Transport Layer Part A) USB Not Supported PCM Not Supported WIFI Co-Ex Not Supported
- Pin Function
2.1 Pin Functions
Table 2-1 shows an attribute and the state of input or output at operation for each pin, and the function description. Table 2-1 Pin Functions Pin name Pin No. Attribute Condition Functional description VDD category Direction Type Default configuration General purpose I/O port GPIO0 C7 DVDDA IN/OUT Pull-up/Pull-down Schmitt trigger 1, 2, and 4 mA IN (Neither pull-up nor pull-down resistor) General purpose I/O pin 0 (Wake-Up Input) After the pin configuration done by the UART command, this pin is able to operate as Wake-Up input pin. If not used for this function, this pin needs to be pulled down by 100 kΩ. GPIO1 A4 DVDDA IN/OUT Pull-up/Pull-down Schmitt trigger 1, 2, and 4 mA OUT General Purpose I/O pin 1 (Wake-up Status Output) After the boot-up, this pin is assigned to the Wake-up Status output pin automatically. L output: Active mode H output: Sleep mode If not used for this function, this pin needs to be kept open. GPIO2 H8 DVDDB IN/OUT Pull-up/Pull-down Schmitt trigger 1, 2, and 4 mA IN (Pull-up) General Purpose I/O pin 2 (LED Blinking Output) After the pin configuration done by the UART command, this pin is able to operate as LED Blinking output pin. If not used for this function, this pin needs to be kept open. GPIO3 G8 DVDDB IN/OUT Pull-up/Pull-down Schmitt trigger 1, 2, and 4 mA IN (Pull-up) General Purpose I/O pin 3 (LED Blinking Output) After the pin configuration done by the UART command, this pin is able to operate as LED Blinking output pin. If not used for this function, this pin needs to be kept open. GPIO4 G7 DVDDB IN/OUT Pull-up/Pull-down Schmitt trigger 1, 2, and 4 mA IN (Pull-up) General Purpose I/O pin 4 (Request Wake-Up output for Host CPU) After the pin configuration done by the UART command, this pin is able to operate as Request Wake-up output port for Host CPU. If not used for this function, this pin needs to be kept open.
Pin name Pin No. Attribute Condition Functional description VDD category Direction Type Default configuration GPIO5 G6 DVDDB IN/OUT Pull-up/Pull-down Schmitt trigger 1, 2, and 4 mA IN (Pull-up) General Purpose I/O pin 5 After the pin configuration done by the UART command, this pin is able to operate as a general-purpose input and output port. If not used for this function, this pin needs to be kept open. GPIO6 E7 DVDDA IN/OUT Pull-up/Pull-down Schmitt trigger 1, 2, and 4 mA OUT General Purpose I/O pin 6 (UART-TX port) After the boot-up, this pin is assigned to the UART-TX output pin automatically. GPIO7 F8 DVDDA IN/OUT Pull-up/Pull-down Schmitt trigger 1, 2, and 4 mA IN (Neither pull-up nor pull-down resistor) General Purpose I/O pin 7 (UART-RX port) After the boot-up, this pin is assigned to the UART-RX input pin automatically. GPIO8 F7 DVDDA IN/OUT Pull-up/Pull-down Schmitt trigger 1, 2, and 4 mA OUT General Purpose I/O pin 8 (UART-RTSX port) After the boot-up, this pin is assigned to the UART -RTSX (Request to send) output pin automatically. GPIO9 D7 DVDDA IN/OUT Pull-up/Pull-down Schmitt trigger 1, 2, and 4 mA IN (Neither pull-up nor pull-down resistor) General Purpose I/O pin 9 (UART-CTSX port) After the boot-up this pin is assigned to the UART -CTSX (Clear to send) input pin automatically. GPIO10 B2 DVDDA IN/OUT Pull-up/Pull-down Schmitt trigger 1, 2, and 4 mA IN (Pull-up) General Purpose I/O pin 10 After the pin configuration done by the UART command, this pin is able to operate as a general-purpose input and output port. If not used for this function, this pin needs to be kept open. GPIO11 A2 DVDDA IN/OUT Pull-up/Pull-down Schmitt trigger 1, 2, and 4 mA IN (Pull-up) General Purpose I/O pin 11 After the pin configuration done by the UART command, this pin is able to operate as a general-purpose input and output port. If not used for this function, this pin needs to be kept open. GPIO12 C6 DVDDA IN/OUT Pull-up/Pull-down Schmitt trigger 1, 2, and 4 mA IN (Pull-up) General Purpose I/O pin 12 After the pin configuration done by the UART command, this pin is able to operate as a general-purpose input and output port. If not used for this function, this pin needs to be kept open.
Pin name Pin No. Attribute Condition Functional description VDD category Direction Type Default configuration GPIO13 D8 DVDDA IN/OUT Pull-up/Pull-down Schmitt trigger 1, 2, and 4 mA IN (Pull-up) General Purpose I/O pin 13 After the pin configuration done by the UART command, this pin is able to operate as a general-purpose input and output port. If not used for this function, this pin needs to be kept open. GPIO14 B6 DVDDA IN/OUT Pull-up/Pull-down Schmitt trigger 1, 2, and 4 mA IN (Pull-up) General Purpose I/O pin 14 (I 2C SCL port) After the pin configuration done by the UART command, this pin changes to SCL signal pin for the serial memory interface. I2C can be selected for the serial memory interface. If not used for this function, this pin needs to be kept open. GPIO15 B5 DVDDA IN/OUT Pull-up/Pull-down Schmitt trigger 1, 2, and 4 mA IN (Pull-up) General Purpose I/O pin 15 (I2C SDA port) After the pin configuration done by the UART command, this pin changes to SDA signal pin for the serial memory interface. I 2C can be selected for the serial memory interface. If not used for this function, this pin needs to be kept open. GPIO16 A5 DVDDA IN/OUT Pull-up/Pull-down Schmitt trigger 1, 2, and 4 mA IN (Pull-up) General Purpose I/O pin 16 After the pin configuration done by the UART command, this pin is able to operate as a general-purpose input and output port. If not used for this function, this pin needs to be kept open. GPIO17 A3 DVDDA IN/OUT Pull-up/Pull-down Schmitt trigger 1, 2, and 4 mA IN (Pull-up) General Purpose I/O pin 17 After the pin configuration done by the UART command, this pin is able to operate as a general-purpose input and output port. If not used for this function, this pin needs to be kept open. GPIO18 B4 DVDDA IN/OUT Pull-up/Pull-down Schmitt trigger 1, 2, and 4 mA IN (Pull-up) General Purpose I/O pin 18 After the pin configuration done by the UART command, this pin is able to operate as a general-purpose input and output port. If not used for this function, this pin needs to be kept open.
2.2 System Configuration Example
This Figure 2-1 shows an example of system configuration. Figure 2-1 TC35661-551 System Configuration Example TC35661-551 Filter
26 MHz
(Option) RFIO H2 XOIN D1 XOOUT D2 RESETX D5 CLKREQ CLKREQ C8 32.768 kHz E8 SLEEPCLK GPIO0 JTAG I/F TRSTX B3 TCK TMS TDI TDO TRTCK GPIO2 GPIO3 GPIO4 GPIO5 GPIO6/UART-TX GPIO7/UART-RX GPIO8/UART-RTSX GPIO9/UART-CTSX GPIO14/SCL B6 GPIO15/SDA GPIO16 GPIO17 GPIO18 GPIO10 GPIO11 GPIO12 GPIO13 GPIO1 A4 Wake-up input Status output LEDout1 Request Wake-up USBDP USBDM DVDD33USB GND
Bluetooth® IC ROM Profile Series Rev 1.00
- General Description 1.1. Product Concept TC35661 is a 1-chip CMOS IC for Bluetooth® communication. Each supported function depends on ROM version. Please see the firmware data sheet. 1.2. Features Each supported function depends on ROM version. Please see the firmware data sheet. Compliant with Bluetooth® specification B uilt-in Bluetooth® baseband digital core Built-in Bluetooth® RF analog core Built-in PLL for multi-clock input Built-in ARM7TDMI-STM core On-chip Program Mask-ROM for Bluetooth® communication On-chip Work memory (RAM) for Bluetooth® Baseband procedure Supports patch program loader function Supports a CODEC for audio communication CVSD (Continuous Variable Slope Delta Modulation) CODEC PCM (Pulse Code Modulation) CODEC Connectable Serial Flash ROM/ EEPROM at external serial memory interface Serial Flash ROM interface (SPI) EEPROM interface (I2C/SPI) Host Interface (set for the product test.) UART interface: Baud rate from 2400 bps to 4.33 Mbps Voice/Audio CODEC Digital Interface (1-ch) Supports I2S (The Inter-IC Sound Bus) interface L eft-justified interface S upports PCM (Pulse Code Modulation) digital interface General Purpose I/O (GPIO) with pull-up and pull-down resistors (MAX: 19 ports) Wake-up Interface Wake-up input function and remote wake-up output function Wi-Fi co-existence interface (2-wire, 3-wire and 4-wire) Test Interface JTAG Interface (ICE Interface) Supports OSC (Crystal oscillator: 26 MHz) Supports an external clock input Built-in oscillation circuit for an external crystal oscillator Supports a sleep clock Built-in divider for the reference operation clock Supports an external clock input Built-in sleep function Power Supply: Single 1.8 or 3.3 V Package TC35661SBG: P-TFBGA64-0505-0.50 [64 balls, 5x5 mm, 0.5 mm pitch, and 1.2 mm height]
1.3. Ordering Information The product whose ending of the product number (the added code) is different has different specifications. Ending of Product Number (Added Code) Weight (Typ.) (ELA 0.052 g (ELC 0.049 g Others 0.049 g Example of product name TC 35661 SBG - 551 (EL) XXX - XXX X XXX ADD Code (EL): Embossed Tape ROM Number ROM551: Bluetooth® V4.2, SPP+GATT with LE secure connection. Package SBG: BGA64 (5x5 mm, 0.5 mm pitch and 1.2 mm height)
- Pin Function 2.1. Pin Assignment Figure 2-1 Pin Assignment (Top view) LVSS33 LDOOUT12A USBDM CLKREQ GPIO13 SLEEPCLK GPIO3 GPIO2 CVDD USBDP GPIO0 GPIO9 GPIO6 GPIO8 GPIO4 DVDDB DVDDA GPIO14 GPIO12 TCK CDVSS CDVSS GPIO5 CVDD LVDD33D LVDD33A CDVSS CDVSS RESETX TDI GPIO15 GPIO16 GPIO1 DVDD33USB GPIO18 LVSS33 GPIO17 TRTCK TMODE1 TRTESTA AVSS12ADC TRTESTC AVSSSG RFIO XOOUT VPGM GPIO10 GPIO11 DVDDA TMS TMODE0 XOIN AVDD12X AVDD12SYN AVDD12SG AVSSSG A8 B8 C8 D8 E8 F8 G8 H8 A7 B7 C7 D7 E7 F7 G7 H7 A6 B6 C6 D6 E6 F6 G6 H6 A5 B5 C5 D5 E5 F5 G5 H5 A4 B4 C4 D4 E4 F4 G4 H4 A3 B3 C3 D3 E3 F3 G3 H3 A2 B2 C2 D2 E2 F2 G2 H2 A1 B1 C1 D1 E1 F1 G1 H1 GPIO7 TRTESTB TRTESTD TDO TRSTX AVDD33PA AVSS12X AVSS12SYN
2.2. Pin Functions Table 2-1 shows an attribute of each pin, input or output state at operation, and function of each pin. Each supported function depends on ROM version. Please see the firmware data sheet. The power supply pins are shown in Table 2-2. Table 2-1 Pin Functions Pin name Pin No. Attribute Condition Functional description VDD category Direction Type During BT communication During a reset After a reset release Reset interface RESETX D5 DVDDA IN Schmitt trigger IN IN IN Hardware reset input pin Low level indicates the reset. Clock interface XOIN D1 AVDD12X IN OSC IN IN IN Reference clock input pin Crystal oscillator or TCXO input pin. The clock frequency is 26 MHz. The clock frequency uncertainty should be +/- 20 ppm or less. A feedback resistor is built in between XOIN pin and XOOUT pin. A resistor and a capacitor suitable for the used crystal oscillator should be externally connected. The clock is used as the internal reference clock. XOOUT D2 AVDD12X OUT OSC OUT OUT OUT Reference clock feedback output pin Crystal oscillator output pin. A feedback resistor is built in between XOIN pin and XOOUT pin. A resistor and a capacitor suitable for the used crystal oscillator should be externally connected. The clock is used as the internal reference clock. If using TCXO for a reference clock, this pin needs to be kept open. CLKREQ C8 DVDDA OUT 2 mA OUT OUT OUT Reference clock (26 MHz) request pin Reference clock request signal. By using this signal to control ON/OFF of an external clock, lower power consumption of the hardware system is achieved. A high level indicates a request for the clock supply. If SLEEPCLK is not used and only X’tal is used, or during a reset, this pin always outputs High. When the clock supply is not necessary, this pin outputs Low. When not using this pin, this pin needs to be kept open. SLEEPCLK E8 DVDDA IN Schmitt trigger IN IN IN Sleep clock input pin This pin is a clock input for low power consumption operation. The clock frequency should be 32.768 kHz. Frequency uncertainty of the sleep clock should be less than or equal to +/-250 ppm. When not using this pin, this pin needs to be pulled down by 100 kΩ.
No. Attribute Condition Functional description VDD category Direction Type During BT communication During a reset After a reset release RF interface RFIO H2 AVDD12SG IN/OUT Analog IN/OUT GND GND RF I/O pin Chapter 6 shows the external connection example of the circuit which matches this pin to 50 Ω. Refer to the connection example, confirm operations in customer’s environment, and adjust the components constant. The pattern before and behind the matching circuit should wire with the 50 Ω transmission line as much as possible, and should not interfere with the power supply line. Don’t connect DC voltage directly to this pin. General purpose I/O port GPIO0 C7 DVDDA IN/OUT Pull-up/ Pull-down Schmitt trigger 1, 2, and 4 mA IN/OUT No-pull-up No-pull-up General purpose I/O pin 0 During a reset GPIO0 is set as an input whose built-in pull-up resistor is disabled. After the reset release, the data direction and the built-in pull-up resistor are set by using the internal software. When not using this pin, this pin needs to be pulled down by 100 kΩ. Each supported function depends on ROM version. Please see the firmware data sheet. GPIO1 A4 DVDDA/DVDDB IN/OUT Pull-up/ Pull-down Schmitt trigger 1, 2, and 4 mA IN/OUT Pull-up Pull-up General Purpose I/O pin 1 to 18 During a reset the GPIO pin is set as an input whose built-in pull-up resistor is enabled. After the reset release, the data direction and the built-in pull-up resistor are set by using the internal software. When not using this pin, this pin needs to be kept open. Pin function of each GPIO pin is assigned to UART interface, the codec digital interface, the serial memory interface, and so on by the firmware mounted on ROM or the commands from the external host mounted on that firmware. Please see the firmware data sheet. GPIO2 H8 GPIO3 G8 GPIO4 G7 GPIO5 G6 GPIO6 E7 GPIO7 F8 GPIO8 F7 GPIO9 D7 GPIO10 B2 GPIO11 A2 GPIO12 C6 GPIO13 D8 GPIO14 B6 GPIO15 B5 GPIO16 A5 GPIO17 A3 GPIO18 B4
No. Attribute Condition Functional description VDD category Direction Type During BT communication During a reset After a reset release IC test interface TMODE0 C1 DVDDA IN Schmitt trigger IN IN IN Test mode setting pins These pins are used to test a product in Toshiba. TMODE0 and TMODE1 pins need to be connected to GND. TMODE1 D3 TRTESTA E3 LVDD33A IN/OUT Analog IN IN IN Analog test pins These pins are used for analog inputs or outputs at the test of a product. These pins are used to test a product in Toshiba. TRTESTA, TRTESTB, TRTESTC and TRTESTD pins have to be connected to GND. TRTESTB E4 TRTESTC G3 TRTESTD F4 USBDP B7 DVDD33USB IN/OUT Differential IN/OUT Hi-Z Hi-Z Test pin This pin has to be connected to GND. USBDM B8 DVDD33USB IN/OUT Differential IN/OUT Hi-Z Hi-Z Test pin This pin has to be connected to GND. JTAG interface TRSTX B3 DVDDA IN Schmitt trigger Pull-down Pull-down Pull-down JTAG reset input pin This pin is a reset input for test or debugging. During a reset the TRSTX is set as an input whose built-in pull-down resistor is enabled. Low level indicates JTAG reset. High level indicates JTAG operation. This pin needs to be kept open (not connected) or to be pulled down if not used for JTAG. TCK D6 DVDDA IN Schmitt trigger Pull-up Pull-up Pull-up JTAG clock input pin This pin is a clock input for test or debugging. This pin needs to be kept open (unconnected) or to be pulled up if not used for JTAG. TMS B1 DVDDA IN Schmitt trigger Pull-up Pull-up Pull-up JTAG mode selection input pin This pin is a serial signal input of the mode selection for test or debugging. This pin needs to be kept open (unconnected) or to be pulled up if not used for JTAG. TDI C5 DVDDA IN Schmitt trigger Pull-up Pull-up Pull-up JTAG data input pin This pin is a serial data input for test or debugging. This pin is for a chip boundary test and firmware development. This pin needs to be kept open (unconnected) or to be pulled up if not used for JTAG. TDO C4 DVDDA TristateOUT 4 mA Hi-Z Hi-Z Hi-Z JTAG data output pin This pin is a serial data output for test or debugging. This pin needs to be kept open (unconnected) if not used for JTAG. TRTCK C3 DVDDA OUT 4 mA OUT OUT OUT ICE return clock output pin Wait control signal to JTAG clock when using ICE. This pin is used for firmware development using ICE. This pin needs to be kept open (unconnected) if not used for JTAG.
2.2.1. Power Supply Pins Table 2-2 shows an attribute of each pin and the supply voltage for each pin at operation. Table 2-2 Power supply pins Pin name Pin No. Attribute Condition Functional description Type VDD/GND Normal Exceptional VDD/ GND VPGM C2 Digital VDD/GND GND 3.3 V Test pin for IC manufacturing VPGM shall be connected to GND directly. DVDDA A1 Digital VDD 3.3 V Power supply pin for GPIOm pins (m = 0, 1, and 6 to 18)
3.3 V needs to be supplied to all DVDDA pins because two
DVDDA pins, A1 and A6 are connected internally in the IC. DVDDB H7 Digital VDD 3.3 V Power supply pin for GPIOn pins (n = 2 to 5) 3.3 V needs to be supplied to DVDDB pin. DVDD33USB A8 Digital VDD/GND GND Test pin (for power supply) This pin needs to be connected to GND in normal operation. CVDD A7 Digital VDD 1.2 V Power supply pin for the IC core LDO output voltage (1.2 V) is supplied to the digital circuit in the IC. A capacitor of at least 0.8 μF or more in the operating temperature range needs to be connected to this pin as the load of LDO. All CVDD pins, A7 and H6 are connected internally in the IC. CDVSS E5 Digital GND GND GND pin for the digital core logic and I/O interface All CDVSS pins need to be connected to GND. AVDD12X E1 Analog VDD 1.2 V Power supply pin for the crystal oscillator interface LDO output voltage (1.2 V) is supplied to the digital circuit in the IC. A capacitor of 0.8 μF or more needs to be connected in the operating temperature range as the load of the LDO. AVDD12SYN F1 Analog VDD 1.2 V Power supply pin for RFPLL This pin needs to be connected to LDOOUT12A. AVDD12SG G1 Analog VDD 1.2 V Power supply pin for LNA/ Receiver MIX (RxMIX)/ ADC/ DAC/ Low pass filter (LPF)/ PAcontrol/ BasebandPLL This pin needs to be connected to LDOOUT12A. AVDD33PA G2 Analog VDD 3.3 V Power supply pin for PA 3.3 V needs to be supplied to AVDD33PA pin. AVSS12X E2 Analog GND GND GND pin for the crystal oscillator interface AVSS12X pin needs to be connected to GND. AVSS12SYN F2 Analog GND GND GND pin for RFPLL AVSS12SYN pin needs to be connected to GND. AVSS12ADC F3 Analog GND GND GND pin for ADC/ DAC/ LPF/ BasebandPLL AVSS12ADC pin needs to be connected to GND. AVSSSG H1 Analog GND GND GND pin for LNA/ RxMIX/ PAcontrol/ PA All AVSSSG pins need to be connected to GND. LVDD33D H5 LDO IN VDD 3.3 V Power supply pin for LDO-type regulator for the digital core 3.3 V needs to be supplied to LVDD33D pin. LVDD33A G5 LDO IN VDD 3.3 V Power supply pin for LDO-type regulator for the analog core 3.3 V needs to be supplied to LVDD33A pin. LVSS33 D4 LDO GND GND GND GND pin for LDO-type regulators for the analog core and the digital core All LVSS33 pins need to be connected to GND.
No. Attribute Condition Functional description Type VDD/GND Normal Exceptional LDOOUT12A H4 LDO OUT OUT OUT Voltage output pin of LDO-type regulator for the analog core LDOOUT12A pin needs to be connected to both AVDD12SYN pin and AVDD12SG pin. A capacitor of 0.8 μF or more needs to be connected in the operating temperature range as the load of the LDO.
4.2.3. Frame Format TC35661 supporting format is as follows. Number of data bits: 8 bits Parity bit: no parity Stop bit: 1 stop bit Flow control: RTSX/CTSX Figure 4-6 shows UART data frame. Figure 4-6 UART data frame 4.2.4. Flow Control Function TC35661 UART interface uses flow control function by hardware signals, Transmit flow control (CTSX) and Receive flow control (RTSX). Figure 4-4 shows the signal input and output directions. Figure 4-6 shows the signal polarities. CTSX input signal is used for UART transmitting. Low input indicates the completion of the preparation for the other party to receive data and TC35661 does UART transmitting if there is data for transmission. In case of High level input, TC35661 stops transmitting in the units of the UART frame. RTSX output signal is used for UART receiving. Low output indicates data transmission request to UART transmission side device of the other party. TC35661 outputs Low level from RTSX when it can receive data, and it prepares to receive data. When it becomes Busy where data reception is disabled, it outputs High level and stops UART transmitting in the units of the UART frame. Response time of UART transmitting and receiving for the flow control signal depends on the baud rate and the frame internal process status. It is from 1 frame to 4 frames. UART Transmit data UART Transmit flow control
1 LSB 2 3 4 5 6 MSB
Start bit Stop bit OverSampling (×12 to17) /bit 1 2 3 4 5 6 7 8 9 10
4.2.5. UART Baud Rate Setting TC35661 UART interface has a programmable baud rate setting function. The UART baud rate can be set using the over-sampling number and the dividing ratio according to the following equation. The baud rate generating clock frequency is 39 MHz. The over-sampling number is set to an integer that ranges from 12 to 17. The dividing ratio is set to an integer that ranges from 1 to 65,535. RatioDividingNumberSamplingOver FrequencyClockGeneratingRateBaudBaudRateUART ×−= Table 4-1 shows examples of the target baud rates supported by TC35661. If the other target baud rate is necessary, please contact our representative. Table 4-1 UART Baud rate setting Target baud rate [bps] Actual baud rate [bps] Baud rate generating clock frequency [MHz] Over-sampling number Dividing ratio Deviation [%] 115,200 116,071 39 12 28 +0.7564 921,600 928,571 39 14 3 +0.7564 2,764,800 2,785,714 39 14 1 +0.7564 4.2.6. Error Detection Function TC35661 UART interface has 3 kinds of error detection functions. Receiver timeout error Receiver overrun error Receiver frame error Receiver timeout error judges as an error if the interval between reception frames counted by TC35661 internal timer is equal to or greater than a predetermined time Receiver overrun error judges as an error if UART reception frame buffer in TC35661 overflows. When data transfer is done according to the flow control in Section 4.2.4, the overflow does not occur. Receiver frame error judges as an error if a frame unit is not recognized. If “0” is detected as Stop bit field after Start bit detection, it is considered that the frame organization fails.
4.3.4. Programmable Polarity Changing The audio CODEC digital interface can program the change of the polarity of the sampling edge and the polarity of the frame synchronization signal, respectively. Data transmitting and receiving timings can be configured as shown in Figure 4-16. Edge polarity can be settings of two types. A: transmission timing @ falling edge, reception sampling @ rising edge B: transmission timing @ rising edge, reception sampling @ falling edge (default) Figure 4-16 Transmission and reception sampling edges DAC digital output ADC digital input Bit clock Frame synchronization Master mode (A) Master mode (B) Slave mode (A) Slave mode (B) Transmission timing Reception timing Transmission timing Reception timing DAC digital output ADC digital input Bit clock Frame synchronization
Table 4-2 shows examples of the bit clock frequency which can be generated. Table 4-2 Examples of the generated bit clock frequency Frame synch frequency [kHz] Number of Bit clock [FS] Bit clock frequency switching Bit clock frequency for a short cycle time [kHz] Bit clock frequency for a long cycle time [kHz] 8 50 No 400 — 52 416 — 100 800 — 130 1040 — 250 2000 — 8 Yes 64.20 63.88 16 128.71 127.45 32 257.43 254.90 64 520.00 500.00 128 1040 1000.00 16 50 No 800 — 130 2080 — 250 4000 — 32 Yes 509.80 514.85 64 1040 1000.00 128 2080 2000.00
Figure 4-24 Connection example for two serial Flash-ROM’s with SPI interface Note: Some connections may need pull-up resistors on the data lines. TC35661 Chip select [1:0] Serial clock output Write data output Read data input Serial Flash-ROM Serial Flash-ROM
4.4.3. Selection of External Pull-up Resistor Value for I2C Bus Interface The external pull-up resistor value needs to be selected by the following equations in case of I2C bus interface. Its maximum value is defined by the equation (1) in which tr is a rise time of the serial clock and data, and Cb is I2C bus capacity. Its minimum value is defined by the equation (2) in which Vdd is a supply voltage for TC35661, Vol_max is the maximum value of the low level output voltage, and Iol is the low level output current. Please select the value of the pull-up resistor in the range of the minimum value and the maximum value. b r C t ×= 8473 . 0Rext_max (1) ol ol dd I V V max_ ext_minR −= (2) TC35661 supports I2C bus standard mode (100 kHz or less) and I2C bus fast mode (400 kHz or less). The rise time tr is 1000 ns for the standard mode and it is 300 ns for the fast mode. Cb value depends on a PCB and implementation on the board. Table 4-3 and Table 4-4 show examples when I2C bus capacity is 20 pF. Table 4-3 External pull-up resistor value for I2C standard mode (Cb = 20 pF) I2C bus frequency 100 kHz or less tr [ns] 1000 Cb [pF] 20 Vol_max [V] 0.3 0.4 0.4 Iol [mA] 1 2 4 1 2 4 1 2 4 Rext_max [kΩ] 59.01 Table 4-4 External pull-up resistor value for I2C fast mode (Cb = 20 pF) I2C bus frequency 400 kHz or less tr [ns] 300 Cb [pF] 20 Vol_max [V] 0.3 0.4 0.4 Iol [mA] 1 2 4 1 2 4 1 2 4 Rext_max [kΩ] 17.70
- Electrical Characteristics 5.1. Absolute Maximum Ratings The absolute maximum ratings of a semiconductor device are a set of specified parameter values, which must not be exceeded during operation, even for an instant. If any of these ratings would be exceeded during operation, the device electrical characteristics may be irreparably altered, and the reliability and lifetime of the device can no longer be guaranteed. Moreover, these operations with exceeded ratings may cause break-down, damage and/or degradation to any other equipment. Applications using the device should be designed such that each absolute maximum rating will never be exceeded in any operating conditions. Table 5-1 Absolute Maximum Ratings (CDVSS = AVSS* = LVSS33 = 0 V) Item Symbol (Power supply category) Rating Unit Min Max Power supply DVDD* -0.3 +3.9 V LVDD33* -0.3 +3.9 V AVDD12* -0.3 +1.8 V AVDD33PA -0.3 +3.9 V CVDD -0.3 +1.8 V Input voltage VIN (DVDDA) -0.3 DVDDA + 0.3 V VIN (DVDDB) -0.3 DVDDB + 0.3 V VIN (AVDD12X) -0.3 AVDD12X + 0.3 V GPIO* -0.3 DVDD* + 0.3 V XOIN -0.3 AVDD12X + 0.3 V Other IO pins -0.3 DVDDA + 0.3 V Output voltage VOUT (DVDDA) -0.3 DVDDA + 0.3 V VOUT (DVDDB) -0.3 DVDDB + 0.3 V VOUT (AVDD12X) -0.3 AVDD12X + 0.3 V VOUT (LDOOUT12A) -0.3 CVDD + 0.3 V GPIO* -0.3 DVDD* + 0.3 V XOOUT -0.3 AVDD12X + 0.3 V Other IO pins -0.3 DVDDA + 0.3 V Input current IIN (DVDD*) -10 +10 mA Input power RFIO (AVDD12SG) — +6 dBm Storage temperature — -40 +125 °C Note: AVSS *: AVSS12X, AVSS12SYN, AVSS12ADC and AVSSSG. DVDD *: DVDDA and DVDDB. LVDD33 *: LVDD33D and LVDD33A. AVDD12 *: AVDD12X, AVDD12SYN and AVDD12SG. GPIO*: GPIO0 to GPIO18.
5.2. Operation Condition The recommended operation conditions are the conditions where this product can operate normally with enough good quality. Malfunction may occur when every condition is not kept at operation. Please keep all operation conditions when application equipment using this product is designed. Table 5-2 Operating condition (CDVSS = AVSS * = LVSS33 = 0 V) Item Symbol Rating Unit Min Typ. Max Power supply DVDDA DVDDB LVDD33* AVDD33PA (Note1) 1.7 2.7 1.8 or 3.3 1.9 3.6 V AVDD12SG AVDD12SYN AVDD12X — 1.2 — V CVDD — 1.2 — V Operating Temperature (Note2) Ta -40 +25 +85 °C Note1: Please refer to different appropriate documents for the recommended connection examples of each power pin. CVDD is generated by a built-in regulator and supplied internally. Please connect a bypass capacitor to CVDD pin. AVDD12X is generated by a built-in regulator and supplied internally. Please connect a bypass capacitor to AVDD12X pin. AVDD12SYN and AVDD12SG are supplied by LDOOUT12A. LDOOUT12A cannot be used for a power supply to another device because it is a 1.2-V output from a built-in regulator. Please supply the same voltage level at LVDD33* and DVDDA. Please use less noise power supply voltage. Note2: This item is the design value. Note3: AVSS *: AVSS12X, AVSS12SYN, AVSS12ADC and AVSSSG. LVDD33 *: LVDD33D and LVDD33A.
5.3. DC Characteristics 5.3.1. Current consumption The current consumption is shown in Table 5-3. The values in the table are operating average current consumption values with the recommended connections of the power supply pins in the ambient temperature of 25°C. Some items in the table are not measured values at the design value. Table 5-3 Current consumption (CDVSS = LVSS33 = AVSS* = 0 V) Item Symbol Condition Measured pin (Note2) Rating Unit Supply voltage Note Min Typ. Max Average current consumed by LVDD33D digital part IDDDIG 3.3 V or 1.8 V — LVDD33D — 6.5 — mA Average current consumed by X’tal OSC digital part IDDANA 3.3 V or 1.8 V — LVDD33A — 2.0 — Average current consumed by analog part during RX IDDDRX 3.3 V or 1.8 V — LVDD33A — 54 — Average current consumed by analog part during TX IDDDTX 3.3 V or 1.8 V — LVDD33A — 24 — 3.3 V or 1.8 V — A VDD33PA — 30 — Average current consumed by IO part (Not1) IDDDIOA 3.3 V or 1.8 V — DVDDA — 0.40 — IDDDIOB 3.3 V or 1.8 V — DVDDB — 0.16 — Current consumed during SLEEPCLK, no clock input to XOIN IDDPDIG 3.3 V or 1.8 V LVDD33D — 0.028 — IDDPANA 3.3 V or 1.8 V LVDD33A — 0.000 — IDDP33PA 3.3 V or 1.8 V AVDD33PA — 0.001 — IDDPIO (Note1) 3.3 V or 1.8 V DVDD* — — — Stand-by current consumed during reset operation, no clock input to XOIN and no SLEEPCLK IDDPDIG 3.3 V or 1.8 V LVDD33D — 0.37 — IDDPANA 3.3 V or 1.8 V LVDD33A — 2.0 — IDDP33PA 3.3 V or 1.8 V AVDD33PA — 0.020 — IDDPIO (Note1) 3.3 V or 1.8 V DVDD* — — — Note1: Average current consumed by IO part changes depending on the buffer settings. Note2: Each measured pin is an LDO output pin in Table 2-2. Note3: AVSS *: AVSS12X, AVSS12SYN, AVSS12ADC and AVSSSG. DVDD *: DVDDA and DVDDB.
The DC characteristics of each pin are shown in Table 5-4. The table shows the values in the ambient temperature of 25°C. Some items in the table are not measured values at the design value. Table 5-4 DC characteristics (CDVSS = LVSS33 = AVSS* = 0 V) Item Symbol Condition Pin (Note1) Rating Unit Interface voltage Others Min Typ. Max High level input voltage VIH
3.3 V LVCMOS level
0.8 x DVDD* — — V 1.8 V 0.8 x DVDD* — — Low level input voltage VIL 3.3 V LVCMOS level input DVDDA and DVDDB categories — — 0.2 x DVDD* 1.8 V — — 0.2 x DVDD* High level input current IIH DVDD* Interface voltage Pull-down Off DVDDA and DVDDB categories - 10 — 10 μA Pull-down On 10 — 200 Low level input current IIL Pull-up Off - 10 — 10 Pull-up On - 200 — - 10 High level output voltage VOH 3.3 V IOH = 1 mA DVDDA and DVDDB categories DVDD* - 0.6 — — V IOH = 2 mA DVDD* - 0.6 — — IOH = 4 mA DVDD* - 0.6 — — 1.8 V IOH = 1 mA DVDD* - 0.3 — — IOH = 2 mA DVDD* - 0.3 — — IOH = 4 mA DVDD* - 0.3 — — Low level output voltage VOL 3.3 V IOL = 1 mA DVDDA and DVDDB categories — — 0.4 V IOL = 2 mA — — 0.4 IOL = 4 mA — — 0.4 1.8 V IOL = 1 mA — — 0.3 IOL = 2 mA — — 0.3 IOL = 4 mA — — 0.3 External reference clock input level (Note2) VCLK 1.2 V AC coupling XOIN 0.7 1.0 1.2 Vpp External 32 kHz reference clock high level input V Sleep CLK H 3.3 V — SLEEPCLK 0.8 x DVDDA — DVDDA+ 0.2 V External 32 kHz reference clock low level input V Sleep CLK L 3.3 V — SLEEPCLK — — 0.2 x DVDDA V Note1: About each pin category, see Table 2-2. Note2: In case of using an external clock, not use of a crystal oscillator. These are the design values. Note3: AVSS *: AVSS12X, AVSS12SYN, AVSS12ADC and AVSSSG. DVDD *: DVDDA and DVDDB.
5.4. Internal Regulator Characteristics Table 5-5 Internal regulator characteristics Item Symbol Pin Rating Unit Min Typ. Max Input Voltage Range Vin LVDD33* 2.7 3.3 3.6 V 1.7 1.8 1.9 V Output Voltage Vout1 LDOOUT12A — 1.2 — V Vout2 AVDD12X — 1.2 — V Vout3 CVDD — 1.2 — V Note: LVDD33 *: LVDD33D and LVDD33A
5.5. RF Characteristics The following conditions are applied unless special notations are described: Ta = 25°C DVDDA=DVDDB = LVDD33A =LVDD33D = 3.3 V f = 2441 MHz (RF channel = 39 channel) fx’tal = 26 MHz (tolerance: +/-2 ppm or less) PAOUT1 = +1.0 dBm Measurement points: Measuring pins of Toshiba's evaluation board. 5.5.1. Basic Rate The RF reception characteristics and the RF transmission characteristics in Basic Rate are shown in Table 5-6 and Table 5-7, respectively. Some items in the tables are not measured values at the design value. Table 5-6 RF reception characteristics (Basic rate) Item Symbol Conditions Rating Unit Min Typ. Max Sensitivity Sense1 Bit error rate (BER): 0.1 % or less f = 2402 MHz, 2441 MHz, and 2480 MHz — - 91.0 — dBm Max Input level maxRange1 — -20 - 10 — dBm C/I Performance (Note1) CI_Co — — 9 — dB CI + 1 MHz — — - 4.5 — dB CI – 1 MHz — — - 2.8 — dB CI + 2 MHz — — - 36 — dB CI – 2 MHz — — - 34 — dB CI + 3 MHz — — - 28 — dB CI – 3 MHz — — - 43 — dB CI + 4 MHz — — - 40 — dB CI + 5 MHz or greater — — - 45 — dB CI – 4 MHz or less — — - 45 — dB Intermodulation IM |f1-f2| = 5 MHz -39 - 26 — dBm Out of band blocking (Note1) OBB1 fTX = fRX = 2460 MHz, and 30 to 2000 MHz -10 0 — dBm OBB2 fTX = fRX = 2460 MHz, and 2 to 2.4 GHz -27 — — dBm OBB3 fTX = fRX = 2460 MHz, and 2.498 to 3 GHz -27 — — dBm OBB4 fTX = fRX = 2460 MHz, and 3 to 12.75 GHz -10 0 — d Bm Note1: For blocking and C/I performance characteristics, the relaxation defined in the Bluetooth SIG specification is maybe applied. Note2: Conditions are conformed to the specification of Bluetooth SIG Inc.
Table 5-7 RF transmission characteristics (Basic rate) Item Symbol Conditions Rating Unit Min Typ. Max TX Output level PAOUT1 f = 2402 MHz, 2441 MHz, and 2480 MHz — 1 .0 — dBm Frequency range Frange — 2400 — 2483.5 MHz 20 dB Band Width 20 dBBW — — 915 1000 kHz Frequency deviation1 Dev1(TX) — 140 162 175 kHz Frequency deviation2 Dev2(TX) — 115 132 — kHz Frequency deviation ratio Deviation(TX) Δf2ave/ Δf1avg 0.8 0.93 — — Initial carrier Frequency Tolerance ICFT — -75 - 4.7 75 kHz Frequency drift1 DH1 Fdrift1 DH1 packet -25 2.5 25 kHz Frequency drift2 DH5 Fdrift2 DH5 packet -40 2.5 40 kHz Frequency drift rate Fdrift rate — -20 6.7 20 kHz/ 50 μs Adjacent channel power IBsp1 Frequency offset = 2 MHz — - 47 - 20 dBm IBsp2 Frequency offset = 3 MHz or greater — - 52 - 40 Note: Conditions are conformed to the specification of Bluetooth SIG Inc.
5.5.2. Bluetooth® Low Energy Each supported function depends on ROM version. Please see the firmware data sheet. The RF reception characteristics and the RF transmission characteristics in Bluetooth® Low Energy are shown in Table 5-8 and Table 5-9, respectively. Some items in the tables are not measured values at the design value. Table 5-8 RF reception characteristics (Bluetooth® Low Energy) Item Symbol Condition Rating Unit Min Typ. Max Sensitivity Sense_4 f = 2402 MHz, 2426 MHz, 2440 MHz, and 2480 MHz PER = 30.8 % or less — - 95.0 — dBm Max Input level maxRange_4 PER = 30.8 % or less -10 — — dBm PER Report Integrity PERReport_4 — 50.0 — 65.4 % C/I performance (Note1) dB CI + 1 MHz_4 — — 3 — CI + 5 MHz or greater_4 — — - 42 — CI – 3 MHz or less_4 — — - 42 — Intermodulation IM_4 |f1-f2| = 5 MHz -50 - 25 — dBm Blocking Performance (Note1) OBB1_4 30 to 2000 MHz -30 0 — dBm OBB2_4 2003 to 2399 MHz -35 — — OBB3_4 2484 to 2997 MHz -35 — — OBB4_4 3.0 to 12.75 GHz -30 0 — Note1: For blocking and C/I performance characteristics, the relaxation defined in the Bluetooth SIG specification is maybe applied. Note2: Conditions are conformed to the specification of Bluetooth SIG Inc.
Table 5-9 R F transmission characteristics (Bluetooth® Low Energy) Item Symbol Condition Rating Unit Min Typ. Max TX Output level PAOUT_4 — — 1 .0 — dBm PDiff_4 Differential between average and peak — 0.5 — dB Carrier Frequency Offset and Drift Carrier freq. offset Cfreqoffset_4 fn ; n = 0,1,2,...,k -150 0 150 kHz Drift Fdrift1_4 f0 - fn ; n = 2,3,4...,k - 50 4.6 50 Drift rate Fdrift rate_4 f1 - f0 , fn - f(n - 5) Modulation Characteristics Δf1avg Dev1_4 Δf1avg 225 247 275 kHz Δf2max Dev2_4 Δf2max 185 218 — Δf2avg/Δf 1avg Devratio_4 Δf2avg/Δf1avg 80 96 — % In-band Emission |M-N|=2 IBE2_4 2 MHz offset — - 47 - 20 dBm |M-N|≥3 IBE3_4 ≥ 3 MHz offset — - 53 - 30 Note: Conditions are conformed to the specification of Bluetooth SIG Inc.
5.6. AC Characteristics 5.6.1. UART Interface Table 5-10 UART Interface AC characteristics Symbol Item Min Typ. Max Unit tCLDTDLY Transmission Data ON from CTSX Low level 96 — — ns tCHDTDLY Transmission Data OFF from CTSX High level — — 2 byte tTXDIV Transmission Data Tolerance (Note) - 0.756 — +0.756 % tRLDTDLY Received Data ON from RTSX Low level 0 — — ns tRHDTDLY Received Data OFF from RTSX High level — — 8 byte tRXDIV Received Data Acceptable Tolerance Note: This is the tolerance of the internal baud rate for each item. UART- CTSX (GPIO9) UART-TX (GPIO6) tCLDTDLY START BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 STOP tCHDTDLY tTXDIV UART- RTSX (GPIO8) UART-RX (GPIO7) tRLDTDLY START BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 STOP tRHDTDLY tRXDIV Figure 5-1 UART Interface Timing Diagram
5.6.2. I 2C Interface 5.6.2.1. Normal Mode Table 5-11 I 2C Interface Normal mode AC Characteristics Symbol Item Min Typ. Max Unit tDATS Data set-up time 250 — — ns tDATH Data hold time 300 — — ns tDATVD Data validity period — — 3450 ns tACKVD ACK validity period — — 3450 ns tSTAS Restart condition set-up time 4700 — — ns tSTAH Restart condition hold time 4000 — — ns tSTOS Stop condition set-up time 4000 — — ns tBUF Bus open period from Stop condition to Start condition 4700 — — ns tr Rise time — — 1000 ns tf Fall time — — 300 ns tHIGH Serial clock period of High 4000 — — ns tLOW Serial clock period of Low 4700 — — ns Cb Bus load capacitance — — 400 pF 70% 30% 70% tf tLOW tHIGH tDATVDtDATH tDATS 1/fSCL 70% 30% 70% 30% tACKVD tSTOS tBUF tSTAH S Sr P S 1st clock tr tf tr 2nd clock 3rd clock 9th clock 9th clock SDA (GPIO15) SCL (GPIO14) S : START condition Sr : Repeated START Condition P : STOP condition tSTAHtSTAS SCL (GPIO14) SDA (GPIO15) Figure 5-2 I 2C Interface Normal mode Timing diagram
5.6.2.2. Fast mode Table 5-12 I 2C Interface Fast mode AC Characteristics Symbol Item Min Typ. Max Unit tDATS Data set-up time 100 — — ns tDATH Data hold time 300 — — ns tDATVD Data validity period — — 900 ns tACKVD ACK validity period — — 900 ns tSTAS Restart condition set-up time 600 — — ns tSTAH Restart condition hold time 600 — — ns tSTOS Stop condition set-up time 600 — — ns tBUF Bus open period from Stop condition to Start condition 1300 — — ns tr Rise time 20 + 0.1 Cb — 300 ns tf Fall time 20 + 0.1 Cb — 300 ns tSP Spike pulse width that can be removed 0 — 50 ns tHIGH Serial clock period of High 600 — — ns tLOW Serial clock period of Low 1300 — — ns Cb Bus load capacitance — — 400 pF 70% 30% 70% tf tLOW tHIGH tDATVDtDATH tDATS 1/fSCL 70% 30% 70% 30% tSP tACKVD tSTOS tBUF tSTAH S Sr P S 1st clock tr tf tr 2nd clock 3rd clock 9th clock 9th clock SDA (GPIO15) SCL (GPIO14) S : START condition Sr : Repeated START Condition P : STOP condition tSTAHtSTAS SDA (GPIO15) SCL (GPIO14) Figure 5-3 I 2C Interface Fast mode Timing diagram
- System Configuration Example 6.1. System Configuration Example Each supported function depends on ROM version. Please see the firmware data sheet. 6.2. Application Circuit Example The application circuits shown in this document are provided for reference purpose only. Especially, thorough evaluation is required on the phase of mass production design. Toshiba dose not grant the use of any industrial property rights with these examples of application circuits. TC35661 DVDDA_1 DVDDA_2 DVDDB LVDD33D LVSS33_1 LVDD33A N.M 0Ω H5 AVDD33PA LVSS33_2 10pF 1000pF AGND 0.22µH 0.22µH DVDD33 CDVSS_1 CDVSS_2 CDVSS_3 CDVSS_4 GND 0.1µF 10µF DVDD33USB AGND LDOOUT12A AVDD12SYN AVDD12SG 18pF 0.1µF AGND AGND AGND GND 1µF AVDD12X 0.1µF AGND AGND 1µF AVSS12ADC AVSS12SYN AVSSSG_1 AVSSSG_2 AVSS12X AGND CVDD_1 GND GND CVDD_2 0.1µF 1µF VPGM AGND RFIO H21.0nH AGND 3pF AGND 2pF 1 4 2 3 5 AGNDAGND100kΩ 1.5pF 5.1nH FeedFixing AGND AGND AGND Antenna RF connector SAW Filter OUT IN AGND GND XOIN XOOUT 15pF 15pF AGND AGND AGNDTRSTX TCK TMS TDI TDO TRTCK GPIO6 GPIO7 GPIO8 GPIO9 RESETX GPIO0 USBDP USBDM GPIO15 GPIO14 GPIO16 X’tal GPIO17 GPIO18 GPIO10 GPIO11 GPIO12 GPIO13 CLKREQ C8 TMODE0 TMODE1 TRTESTA TRTESTB TRTESTC TRTESTD EEPROM SDA SCL WP VCC GND 10kΩ 10kΩ GND AGND GND VDD33 GND 0.1μF GPIO1 SLEEPCLK UARTTX UARTRX RTS CTS RESETX GPIO0 GPIO1 SLEEPCLK GPIO10 GPIO11 GPIO12 GPIO13 GPIO16 GPIO17 GPIO5 GPIO4 GPIO3 GPIO5 GPIO4 GPIO3 GPIO2 GPIO2 10µF Figure 6-1 Application Circuit Example
- Package 7.1. TC35661SBG Package Outline Unit: mm Figure 7-1 P ackage outline (P-TFBGA64-0505-0.50) Note: This figure is for explanation. For the dimensions and the others that are not listed in the figure, please contact our representative.
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