TC35080P | DigiCamel IC Datasheet

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TC35080P TOSHIBA | Alldatasheet

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TC35080P CMOS A/D CONVERTER TOSHIBA (LOGIC/MEMORY) (10-Bit Serial I/O A/D Converter ) 1. GENERAL DESCRIPTION ‘The TC35080P is a high precision, high speed monolithic CMOS 10-bit Successive Approximation A/D Converter with separate serial input and output. This device has a clock input (IOCK) which shifts serial data in (write mode) and out (read mode), a data output enable (DOE) which controls output timing and a Successive Approximation Register Status (SARS) output. These permit easy interfacing to other devices. ‘The frequency of the built in A/D conversion DIP20 ~ P - 300A clock is determined by the values of an external RC Network connected to the CKI and CKO terminals. For the user desires, an external clock may be connected to the CKI terminal. Ga K] Vpo Aino Bl fg CKi 2. FEATURES an G fg CKO High accuracy : 1LSB TYP. Anz Gl fq DI CiHigh speed conversion : 11ps @ £CKI=2.0MHz Ans GI fg DOE | O Single power supply :5.0V10% Ane & fy 1OCK O Serial YO Ans kg DO O Built-in 8-channel Analog multiplexer Ane & fy SARS © Latched 3-state output an Gl Fa Vrer O Built-in A/D Oscillator vss FI Ano i

0 Zero or full scale adjustment free i

(TOP VIEW)

APPLICATIONS

Ci Industrial Control Instruments O Electrical Wiring Apparatus * 1:Successive Approximation Register 672 een TE

——— TOSHIBA (LOGIC/NEMORY) ange npan 3. SYSTEM DESCRIPTION -cs JOCK -SARS oO 9 9 0 °

4 Bit Shift Register

Control & Timing sta | set | cH2 | cH1 | cHo cko © Logic — i Vacr © i Capacitor Array/Resistor Ladder | © AINo ia & 0 Aint Acno © Decoder 8-ch © Aine L f \\/ Analog O AIn3 Comp. © Aina Successive Approximation Multi ae ; -plexer INS Register O AInNé WW O AIN7 merepen Output TOBit shift Register Contro! Cy Co Output Buffer Logte <~—O Vpop Boe <~—o Vss 673 ee

PIN DESCRIPTION [pre [omar [ neem] {Chip Select} -cs | Atthe falling edge of -CS, the device is set ready for conversion. When -CSis “H", the device is reset and all outputs go to high impedance state. [| 2} Ano [Analog Input] [“ON CHANNEL] CH2 [CHT CHO ] Se One ofaoto Auy7 Analog input channels, [—Aua_—} EP FE [ST Tana] selected according tothe decoding of the [ag tw t [6 | Ama | Channel Select Bits (CHO, CH1, and CH2) [Ains tie i [Awa pup a ee bees to theo ests Tne Full range of Et — te es er @ input signed voltage is from Agnoto [awe Ps ee VSS = OV eS Agno defines the zero level of Ain. ee Vrer defines the full scale of Ain. [Successive Approximation Register Status ] -SARS — SARS is the signed output terminal which indicates the internal status of A/D converter (during conversion or after conversion that allows data to be read). Output data is sent out in series [VO Clock] 1OcK Clock input terminal for the input ( read mode ) or output (write mode ) of serial data. a Timing control for conversion data output. [ Data Input}

7 For starting the conversion a start bit (“L”Level) and channel select bit (from

CH2 to CHO in order) are to be applied. ee = Clock output terminal for A/D conversion. Poe festeman | Clock input terminal for A/D conversion. { System Power Supply] pe fo ee 674 eee

TOSHIBA (LOGIC/MEMORY) - nnn TC35080P 5. FUNCTIONAL DESCRIPTION

5.1 TIMING CHART

(1) WRITE/ READ OPERATION OF SERIAL DATA ee UU UU $k PRCECLD a Co) Cr Gl Sa, OP Teeter _ poe . exsrrosion S! i — sans [74 al | ns 0 t 0 High imp. i = goccoconog™ High ip. 008="t" i H 1s 2od_3ed 4th Sth 6th 7th Sth 9th 10th oo jp eX e0000 0 Gnu: — i {iw and Sed 4th Sth Gh Mh Bh Sh toh a SEL= TL": LSB FIRST (2) CONVERSIONOPERATION —S@”vETOnTime ees ee <2 pinata | omaelis A oo oie T seat} Sampling Time pi Comparing Time { st Date oes wate i Conversion Time TSamp.= Sou +0 Temp. =13eRiea aS Mock 675 a

C/MEMORY) OSHIBA (LOGT

5.2 SYSTEM INITIALIZATION

When —CS set high, all circuits except the output latch circuit are reset and all outputs are set to the high impedance state. ‘When the power is switched ON or a wrong operation occurs, set —CS high to initialize the internal circuits.

53 AD CONVERSION

‘When —CS goes low and after writing the serial data from DI, conversion begins. After a certain period for conversion, the conversion data is output in series from DO as determined by the output data format ( SEL bit from DI ) and output control enable ( DOE ). This completes one conversion cycle.During this period, —CS must be held low. @® Write Mode After —CS goes low, output data format ( SEL ) and channel select ( CH2,CH1,CHO ) are written into the 4 Bit shift resister in order followed by the start bit( STA=“L” ). This is written on the raising edge of IOCK. ® Conversion Mode (TC = Tsamp + Tcomp ) After completing the write of serial data, the sampling cycle (Tsamp=8/fCKI+ a ) status in the internal circuits, as well as sampling of the selected input voltage level. After the sampling cycle, the comparison cycle ( Teomp=13fcxi+ a) stars and the analog input level is converted a ten bit digital data stream. @® Read Mode After the conversion cycle, the start bit(STA=“L” ), the 10-bit conversion data stream and the stop bit (STP=“H” ) are output in that order synchronously with the falling edge of IOCK from DO according to output data format ( SEL ) and output control (DOE ). @ Output Data Format SEL= “L” :10-bit conversion data is output from LSB TO MSB. SEL=“H” :10-bit conversion data is output from MSB TO LSB. @ Output Control DOE=“L”: SAR status output ( —SARS ) goes low during conversion mode (Tc ) and when the conversion is just completed, it goes high, then the conversion data stream output status. DOE=“H” —“L” : At the start of conversion, DOE is high, -SARS goes low at the end of the conversion, and conversion data is allowed reading. If DOE is set low, and —SARS goes high on | the falling edge of IOCK ,the output of conversion data begins. | @ Serial Conversion | —CS is set high ( 100ns MIN ) once every conversion cycle. This resets the internal circuitry for | the next conversion. i 676 | a

RY) OGIC/MENO!

5.4 CLOCK

Separate clocks are provided for A/D conversion ( CKI,CKO ) and serial data read/write functions (OCK). ‘The clock for A/D conversion is composed of an oscillation circuit which uses an external resistor and capacitor. If desired an external clock may be used on the CKI pin, © CKI Pe al cKO 677 rr

TOSHIBA ¢ LOGIC/MENORY ) 6. ELECTRICAL CHARACTERISTICS

6.1 MAXIMUM RATINGS

fnnuecorene | ww [ama PowerDsspwion [ro | 300+ aw | songeTenpetieterae | Tw [Seo | e_| 6.2 RECOMMENDED OPERATING CONDITIONS (Vsg = 0.0V) [cvanacrense [sewoor] conomons [ vane [ rrr. [ wax | on | faomrvorage | veo [ps | se fs Dv ference vonage | Var [aawaev [| 90 | voo | voo [| v_ fares cnavonase | Aono [vnr=sav [oo | oo | oo |v fr=Acnovorose | _[voo=sovsiex| 20 | voo | voo | _v_| oer __ fee pecenewe oe f= en Le ocr [voo=savev0% [soot [= [20 | wie | Peemcnare [ic femesnsoe ox =F = loowatarterpenwre | too [voo-sovzeu| -«@ | - | = |< | | 678

T¢35080P TOSHIBA (LOGIC/NEMORY) 6.4 SWITCHING CHARACTERISTICS ( Vpp = 5.0 + 10% Vs = 0.0V,Ta = 25°C ) [cranacrensnc —[srsox] conornons [wn | we, [ax | var | Output Rise/Fall Time ‘tTLH CL =50pF DO, - SARS tTHL P Propagation Delay Time tPLH = DO, -SARS tPHL ema 3-State Output Enable Time tezH CL=S0pF DO, - SARS ‘tezu RL=1KQ 3-State Output Disable Time teyz | CL=50pF DO, - SARS ‘teLz RL=1KQ famonrawan - [wn | i - | fmt = | [ent fowrarme —[ = [= | - | foupucancane | cour [psweowon | - fw | - Lo | 680 a

TOSHIBA (LOGIC/MEMORY) 6.4.1. SWITCHING CHARACTERISTICS TEST WAVE FORMS lock 60% 50% S0%0 IV ts te 50% * | “ roe KC ct 50% tezH teLH tpHz 90% - SARS 50% som tpzL AS tet, tpHL es) 50% DO (Pull Up) 5 50% i DO ,-SARS 90% 90% ee 10% 10% KI, 1OCK 50% 50% tw CKI tw lOCK trHe | tT 681

TC35080P ————=_ TOSHIBA (LOGIC/MEMORY ) 6.4.2 3-STATE OUTPUT TEST CIRCUIT Vop Voo Re tpLZ, tpzL TC35080P o ‘tpnz, tpzH ot ‘pl ‘pi

65 SYSTEM CHARACTERISTICS (Ta = ~ 40 to 85°C)

poem | ners ety = = a fcxi=2.0MHz [= [eae [ais [| [coneriontine | te [eanzowee | - | | - |» | 682 a

Product Information

TC35080P specifications and overview.

Summary

10-BIT SERIAL I/O A/D CONVERTER

Description

10-BIT SERIAL I/O A/D CONVERTER

Source title TC35080P Datasheet(PDF) - Toshiba Semiconductor

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