TC1724

TC1724 INFINEON | Alldatasheet

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V1.2 2014-06 Microcontrollers 32-Bit Microcontroller TC1724 32-Bit Single-Chip Microcontroller

81726 Munich, Germany

© 2014 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

V1.2 2014-06 Microcontrollers 32-Bit Microcontroller TC1724 32-Bit Single-Chip Microcontroller

Data Sheet I-1 V1.2, 2014-06 TC1724 Table of Contents Table of Contents

Data Sheet I-2 V1.2, 2014-06 TC1724 Table of Contents

Data Sheet 1-1 V1.2, 2014-06

1 Summary of Features

The SAK-TC1724F-192F133HL / SAK-TC1724F-192F133HR has the following features:

• High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) – 133 MHz operation at full temperature range
• 32-bit Peripheral Control Processor with single cycle instruction (PCP2) – 8 Kbyte Parameter Memory (PRAM) – 24 Kbyte Code Memory (CMEM) – 133 MHz operation at full temperature range
• Multiple on-chip memories – 1.5 Mbyte Program Flash Me mory (PFLASH) with ECC – 64 Kbyte Data Flash Memory (DFL ASH) usable for EEPROM emulation – 120 Kbyte Data Memory (LDRAM) – Instruction Cache: up to 8Kbyte (ICACHE, configurable) – 24 Kbyte Code Scratchpad Memory (SPRAM) – Data Cache: up to 4 Kbyt e (DCACHE, configurable) – 8 Kbyte Overlay Memory (OVRAM) – 16 Kbyte BootROM (BROM)
• 16-Channel DMA Controller
• Sophisticated interru pt system with 2 × 255 hardware priority arbitration levels serviced by CPU or PCP2
• High performing on-chip bus structure – 64-bit Local Memory Buses between CPU, Flash and Data Memory – 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units – One bus bridge (LFI Bridge)
• Versatile On-chip Peripheral Units – Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection – Four High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction – One serial Micro Second Bus interface (MSC) for serial port expansion to external power devices – One High-Speed Micro Link interface (MLI) for serial inter-processor communication – One MultiCAN Module with 3 CAN nodes and 64 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer – One FlexRay TM module with 2 channels (E-Ray).

Data Sheet 1-2 V1.2, 2014-06 – One General Purpose Timer Array Module (GPTA) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management – Two Capture/Compare Unit 6 (CAPCOM6) kernels – Two General Purpose Timer (GPT12) modules

• 28 analog input lines for ADC – 2 independent kernels (ADC0 and ADC1) – Analog supply voltage range from 3.3 V to 5 V (single supply) – Broken wire detection
• 2 different FADC input channels – channels with impedance control and overlaid with ADC1 inputs – Extreme fast conversion, 21 cycles of fFADC clock – 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter)
• 95 digital general purpose I/O lines (GPIO)
• Digital I/O ports with 3.3 V capability
• On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
• Dedicated Emulation Device chip available (TC1724ED) – multi-core debugging, real time tracing, and calibration – four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
• Power Management System
• Clock Generation Unit with PLL

Data Sheet 1-3 V1.2, 2014-06 The SAK-TC1724N-192F133HR has the following features:

• High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) – 133 MHz operation at full temperature range
• 32-bit Peripheral Control Processor with single cycle instruction (PCP2) – 8 Kbyte Parameter Memory (PRAM) – 24 Kbyte Code Memory (CMEM) – 133 MHz operation at full temperature range
• Multiple on-chip memories – 1.5 Mbyte Program Flash Me mory (PFLASH) with ECC – 64 Kbyte Data Flash Memory (DFL ASH) usable for EEPROM emulation – 120 Kbyte Data Memory (LDRAM) – Instruction Cache: up to 8Kbyte (ICACHE, configurable) – 24 Kbyte Code Scratchpad Memory (SPRAM) – Data Cache: up to 4 Kbyt e (DCACHE, configurable) – 8 Kbyte Overlay Memory (OVRAM) – 16 Kbyte BootROM (BROM)
• 16-Channel DMA Controller
• Sophisticated interru pt system with 2 × 255 hardware priority arbitration levels serviced by CPU or PCP2
• High performing on-chip bus structure – 64-bit Local Memory Buses between CPU, Flash and Data Memory – 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units – One bus bridge (LFI Bridge)
• Versatile On-chip Peripheral Units – Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection – Four High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction – One serial Micro Second Bus interface (MSC) for serial port expansion to external power devices – One High-Speed Micro Link interface (MLI) for serial inter-processor communication – One MultiCAN Module with 3 CAN nodes and 64 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer – One General Purpose Timer Array Module (GPTA) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management – Two Capture/Compare Unit 6 (CAPCOM6) kernels

Data Sheet 1-4 V1.2, 2014-06 – Two General Purpose Timer (GPT12) modules

• 28 analog input lines for ADC – 2 independent kernels (ADC0 and ADC1) – Analog supply voltage range from 3.3 V to 5 V (single supply)
• 2 different FADC input channels – channels with impedance control and overlaid with ADC1 inputs – Extreme fast conversion, 21 cycles of fFADC clock – 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter)
• 95 digital general purpose I/O lines (GPIO)
• Digital I/O ports with 3.3 V capability
• On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
• Dedicated Emulation Device chip available (TC1724ED) – multi-core debugging, real time tracing, and calibration – four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
• Power Management System
• Clock Generation Unit with PLL

Data Sheet 1-5 V1.2, 2014-06 The SAK-TC1724N-192F80HL / SAK-TC1724N-192F80HR has the following features:

• High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) – 80 MHz operation at full temperature range
• 32-bit Peripheral Control Processor with single cycle instruction (PCP2) – 8 Kbyte Parameter Memory (PRAM) – 24 Kbyte Code Memory (CMEM) – 80 MHz operation at full temperature range
• Multiple on-chip memories – 1.5 Mbyte Program Flash Me mory (PFLASH) with ECC – 64 Kbyte Data Flash Memory (DFL ASH) usable for EEPROM emulation – 120 Kbyte Data Memory (LDRAM) – Instruction Cache: up to 8Kbyte (ICACHE, configurable) – 24 Kbyte Code Scratchpad Memory (SPRAM) – Data Cache: up to 4 Kbyt e (DCACHE, configurable) – 8 Kbyte Overlay Memory (OVRAM) – 16 Kbyte BootROM (BROM)
• 16-Channel DMA Controller
• Sophisticated interru pt system with 2 × 255 hardware priority arbitration levels serviced by CPU or PCP2
• High performing on-chip bus structure – 64-bit Local Memory Buses between CPU, Flash and Data Memory – 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units – One bus bridge (LFI Bridge)
• Versatile On-chip Peripheral Units – Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection – Four High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction – One serial Micro Second Bus interface (MSC) for serial port expansion to external power devices – One High-Speed Micro Link interface (MLI) for serial inter-processor communication – One MultiCAN Module with 3 CAN nodes and 64 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer – One General Purpose Timer Array Module (GPTA) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management – Two Capture/Compare Unit 6 (CAPCOM6) kernels

Data Sheet 1-6 V1.2, 2014-06 – Two General Purpose Timer (GPT12) modules

• 28 analog input lines for ADC – 2 independent kernels (ADC0 and ADC1) – Analog supply voltage range from 3.3 V to 5 V (single supply)
• 2 different FADC input channels – channels with impedance control and overlaid with ADC1 inputs – Extreme fast conversion, 21 cycles of fFADC clock – 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter)
• 95 digital general purpose I/O lines (GPIO)
• Digital I/O ports with 3.3 V capability
• On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
• Dedicated Emulation Device chip available (TC1724ED) – multi-core debugging, real time tracing, and calibration – four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
• Power Management System
• Clock Generation Unit with PLL

Data Sheet 1-7 V1.2, 2014-06

Ordering Information

The ordering code for Infineon microcontro llers provides an exact reference to the required product. This ordering code identifies:

• The derivative itself, i.e. its function set, the temperature range, and the supply voltage
• The package and the type of delivery. For the available ordering codes for the TC1724 please refer to the “Product Catalog Microcontrollers”, which summarizes all available microcontroller variants. This document describes the de rivatives of the device.The Table 1 enumerates these derivatives and summarizes the differences. Table 1 TC1724 Derivative Synopsis Derivative Ambient Temperatur e Range (T CPU/PCP Freq. Flash Size ERAY Wire Bond Material SAK-TC1724F-192F133HL -40 oC to +125oC 133 MHz 1.5 MB Yes Au SAK-TC1724F-192F133HR1) 1) This derivative has the same features as the S AK-TC1724F-192F133HL, except the wire-bonding material. -40oC to +125oC 133 MHz 1.5 MB Yes Cu SAK-TC1724N-192F133HR -40 oC to +125oC 133 MHz 1.5 MB No Cu SAK-TC1724N-192F80HL -40 oC to +125oC 80 MHz 1.5 MB No Au SAK-TC1724N-192F80HR2) 2) This derivative has the same features as the SAK-TC1724N-192F80HL, except the wire-bonding material. -40oC to +125oC 80 MHz 1.5 MB No Cu

System Overview of the TC1724 Data Sheet 2-1 V1.2, 2014-06

2 System Overview of the TC1724

The TC1724 combines three powerful technologies within one silicon die, achieving new levels of power, speed, and economy for embedded applications:

• Reduced Instruction Set Computing (RISC) processor architecture
• Digital Signal Processing (DSP) operations and addressing modes
• On-chip memories and peripherals DSP operations and addressing modes prov ide the computational power necessary to efficiently analyze complex real-world signals. The RISC load/store architecture provides high computational bandwidth with low system cost. On-chip memory and peripherals are designed to support even the most demanding high-bandwidth real-time embedded control-systems tasks. Additional high-level features of the TC1724 include:
• Efficient memory organization: instru ction and data scratch memories, caches
• Serial communication interfaces – flexible synchronous and asynchronous modes
• Peripheral Control Processor – standalon e data operations and interrupt servicing
• DMA Controller – DMA operations and interrupt servicing
• General-purpose timers
• High-performance on-chip buses
• On-chip debugging and emulation facilities
• Flexible interconnections to external components
• Flexible power-management The TC1724 is a high-performance microcontroller with TriCore CPU, program and data memories, buses, bus arbitration, an interrupt controller, a peripheral control processor and a DMA controller and several on-chip peripherals. The TC1724 is designed to meet the needs of the most demanding embedded control systems applications where the competing issues of price/performance, real-time responsiveness, computational power, data bandwidth, and power consumption are key design elements. The TC1724 offers several versatile on-chip per ipheral units such as serial controllers, timer units, CAPCOM6 and Analog-to-Digital converters. Within the TC1724, all these peripheral units are connected to the TriCore CPU/system via the Flexible Peripheral Interconnect (FPI) Bus and the Local Memory Bus (LMB). Several I/O lines on the TC1724 ports are reserved for these peripher al units to communicate with the external world.

System Overview of the TC1724 Data Sheet 2-2 V1.2, 2014-06

2.1 Block Diagrams

Figure 1 shows the block diagram of th e SAK-TC1724F-192F133HL / SAK-TC1724F- 192F133HR. Figure 1 SAK-TC1724F-192F133HL / SAK-TC1724F-192F133HR Block Diagram E-Ray (2 channels) OCDS L1 Debug Interface MLI0 MemCheck TriCore CPU TC1.3.1 133MHz PMI Interrupt System FPI-Bus Interface

8 KB PRAM

24 KB CMEM

(SPB) SBCU LFI Bridge SMIF DMI CPS LBCU PMU MultiCAN (3 Nodes,

64 MO)

Ext. Request Unit 1,5 MB PFlash

64 KB Dflash

16 KB BROM

8 KB OVRAM

M M/S

16 KB SPRAM

8 KB ICACHE

(Configurable)

116 KB LDRAM

4 KB DCACHE

(Configurable) FPU PLL E-RAY PLL fE-Ray fCP U Abbreviations : ICACHE: Instruction Cache DCACHE Data Cache SPRAM: Scratch-Pad RAM LDRAM: Local Data RAM OVRAM: Overlay RAM BROM: Boot ROM PFlash: Program Flash DFlash: Data Flash PRAM: Parameter RAM in PCP CMEM: Code RAM in PCP V0.8 DMA 16 channels SSC2 Local Memory Bus (LMB) CAPCOM (CCU 60, CCU 61) GPT12 (GPT 120) GPT12 (GPT 121) GPTA 0 FCE SSC3 JTAG/DAP SSC0 BMU FADC (3.3V max, 2 differential channels ) ADC0 (5 V max , 16 channels ) ADC1 (5 V max , 24 channels ) Ext. ADC Supply 1.3V, 3.3V Int. Supply EVR Embedded Voltage Regulator 5V, 3.3V Optional Ext . Supply Single -source Ext. Supply

System Overview of the TC1724 Data Sheet 2-3 V1.2, 2014-06 Figure 2 shows the block diagram of the SAK-TC1724N-192F133HR. Figure 2 SAK-TC1724N-192F133HR Block Diagram OCDS L1 Debug Interface MLI0 MemCheck TriCore CPU TC 1.3.1 133MHz PMI Interrupt System FPI-Bus Interface (SPB) SBCU LFI Bridge SMIF DMI CPS LBCU PMU MultiCAN (3 Nodes, Ext. Request Unit 1,5 MB PFlash M M/S (Configurable) (Configurable) FPU PLL fCPU Abbreviations : ICACHE: Instruction Cache DCACHE Data Cache SPRAM: Scratch-Pad RAM LDRAM: Local Data RAM OVRAM: Overlay RAM BROM: Boot ROM PFlash: Program Flash DFlash: Data Flash PRAM: Parameter RAM in PCP CMEM: Code RAM in PCP V0.8 DMA 16 channels SSC2 Local Memory Bus (LMB) CAPCOM (CCU60, CCU61) GPT12 (GPT 120 ) GPT12 (GPT 121 ) GPTA 0 FCE SSC3 JTAG/DAP SSC0 BMU FADC (3.3V max, 2 differential channels ) ADC0 (5 V max , 16 channels ) ADC1 (5 V max , 24 channels ) Ext. ADC Supply 1.3V, 3.3V Int. Supply EVR Embedded Voltage Regulator 5V, 3.3V Optional Ext. Supply Single -source Ext. Supply

System Overview of the TC1724 Data Sheet 2-4 V1.2, 2014-06 Figure 3 shows the block diagram of the SAK-TC1724N-192F80HL / SAK-TC1724N- 192F80HR. Figure 3 SAK-TC1724N-192F80HL / SAK-TC1724N-192F80HR Block Diagram OCDS L1 Debug Interface MLI0 MemCheck TriCore CPU TC 1.3.1 80MHz PMI Interrupt System FPI-Bus Interface (SPB) SBCU LFI Bridge SMIF DMI CPS LBCU PMU MultiCAN (3 Nodes, Ext. Request Unit 1,5 MB PFlash M M/S (Configurable) (Configurable) FPU PLL fCPU Abbreviations : ICACHE: Instruction Cache DCACHE Data Cache SPRAM: Scratch-Pad RAM LDRAM: Local Data RAM OVRAM: Overlay RAM BROM: Boot ROM PFlash: Program Flash DFlash: Data Flash PRAM: Parameter RAM in PCP CMEM: Code RAM in PCP V0.8 DMA 16 channels SSC2 Local Memory Bus (LMB) CAPCOM (CCU60, CCU61) GPT12 (GPT 120 ) GPT12 (GPT 121 ) GPTA0 FCE SSC3 JTAG/DAP SSC0 BMU FADC (3.3V max, 2 differential channels ) ADC0 (5 V max , 16 channels ) ADC1 (5 V max , 24 channels ) Ext. ADC Supply 1.3V, 3.3V Int. Supply EVR Embedded Voltage Regulator 5V, 3.3V Optional Ext . Supply Single -source Ext. Supply

System Overview of the TC1724 Data Sheet 2-5 V1.2, 2014-06 Figure 4 shows the block diagram of the SAK-TC1724F-192F80HR. Figure 4 SAK-TC1724F-192F80HR Block Diagram OCDS L1 Debug Interface MLI0 MemCheck TriCore CPU TC 1.3.1

80 MHz

(SPB) SBCU LFI Bridge SMIF DMI CPS LBCU PMU MultiCAN (3 Nodes, Ext. Request Unit 1,5 MB PFlash M M/S (Configurable) (Configurable) FPU PLL fCP U Abbreviations : ICACHE: Instruction Cache DCACHE Data Cache SPRAM: Scratch-Pad RAM LDRAM: Local Data RAM OVRAM: Overlay RAM BROM: Boot ROM PFlash: Program Flash DFlash: Data Flash PRAM: Parameter RAM in PCP CMEM: Code RAM in PCP V0.8 DMA 16 channels SSC2 Local Memory Bus (LMB) CAPCOM (CCU60, CCU61) GPT12 (GPT 120 ) GPT12 (GPT 121 ) GPTA 0 FCE SSC3 JTAG/DAP SSC0 BMU FADC (3.3V max, 2 differential channels ) ADC0 (5 V max , 16 channels ) ADC1 (5 V max , 24 channels ) Ext. ADC Supply 1.3V, 3.3V Int. Supply EVR Embedded Voltage Regulator 5V, 3.3V Optional Ext . Supply Single -source Ext. Supply E-Ray (2 channels) PLL E-RAY fE-Ray

Data Sheet 3-1 V1.2, 2014-06

3 Pinning

Figure 5 shows the logic symbol for TC1724 Figure 5 TC1724 Logic Symbol TESTMODE ESR 0 PORST Digital Circuitry Power Supply General Control AN [16:0], AN19, AN23, AN25, AN[39:32] Analog Inputs VDDM VSSM VAREF0 VAGND0 Analog Power Supply TC1724_LogSym_144 Alternate Functions Oscillator GPTA, SCU , E-RAY , MSC0, CCU6 GPTA, SSC 0/1, MSC0, MLI0, CCU6, GPT12 GPTA, ASC 0/1, SSC 0/1, SCU, CAN, MSC0 GPTA, SCU , CCU6, GPT12 GPTA, E-RAY1), SSC 0/2, CAN, CCU6, GPT12, SCU, ADC1 TC172 4 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 8 CCU6, GPT12, SSC3, GPTA XTAL2 XTAL1 VSS VDDP VDD ESR 1 TRST TCK / DAP0 TMS / DAP1 OCDS / JTAG Control SCU, GPTA , SSC 1, OCDS, CCU6, GPT12 Port 9 GPTA, CCU6, CAN, OCDS/JTAG VPDG 1EVR Pass Device Gate Port 11 Overlaid digital /analog inputs Port 12 Overlaid digital /analog inputs 1)Onl y avai l abl e for SAK-TC1724 F-192 F133 HL , SAK- TC1724 F-192 F133 HR

Data Sheet 3-2 V1.2, 2014-06 Figure 6 TC1724 Pinning for PG-LQFP-144-17 package Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) Pin Symbol Ctrl. Type Function Port 0 TC1724_QFP144 100 101 102 103 104 105 106 107 108109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 143 144 133 134 135 136 137 138 140 141 142 139 TC1724 AN39/DIG19/P12.3 AN38/DIG18/P12.2 AN36/DIG16/P12.0 AN37/DIG17/P12.1 REQ7/CC62/CC62INA/B/CAPINA/B/SLSO20/OUT40/IN40/P5.0 SLSO21/OUT41/IN41/P5.1 COUT62/SLSO22/OUT42/IN42/P5.2 SLSI2A/SLSO24/OUT44/IN44/P5.4 SLSO23/OUT43/IN43/P5.3 MRST2A/OUT45/IN45/P5.5 MTSR2A/OUT46/IN46/P5.6 SCLK2A/OUT47/IN47/P5.7 CC61/CC61INA/B/OUT6/TXDA1 1)/P5.8 OUT7/RXDCAN0/TXDB1 1)/P5.9 COUT61/OUT8/TXENA 1)/P5.10 COUT63/OUT9/TXENB 1)/P5.11 CCPOS0A/T12HRB/T3INA/B/AD1EMUX0/SLSO07/OUT19/P5.12 CCPOS1A/T13HRB/T3EUDA/B/OUT20/AD1EMUX1/P5.13 CCPOS2A/T12HRC/T13HRC/T4INA/B/OUT36/AD1EMUX2/RXDA1 1)/P5.14 TXDCAN0/OUT37/RXDB1 1)/P5.15 VDD CC60INC/CC60/OUT87/P9.7 COUT60/OUT88/P9.8 RXDCAN2/OUT80/P9.0 TXDCAN2/OUT81/P9.1 VDDP 1) V DD AN33 AN32 AN7 AN25/DIG9/P11.9 AN23/DIG7/P11.7 AN34 AN35 VPDG CC62/CC62INA/B/TCLK0/OUT32/IN32/P2.0 CCPOS0A/T12HRB/T2INA/B/SLSO13/SLSO03/OUT33/TREADY0A/IN33/P2.1 CC61/CC61INA/B/TVALID0A/OUT34/IN34/P2.2 T12HRC/T13HRC/CCPOS2A/T4EUDA/B/TDATA0/OUT35/IN35/P2.3 COUT63/OUT36/RCLK0A/IN36/P2.4 CC60/CC60INA/B/RREADY0A/OUT37/IN37/P2.5 COUT62/OUT38/RVALID0A/IN38/P2.6 COUT60/OUT39/RDATA0A/IN39/P2.7 AN14 AN15 AN16/DIG0/P11.0 AN19/DIG3/P11.3 V DD VDDP CC62INC/CC62/OUT102/P8.7 COUT61/OUT101/P8.6 SLSO32/OUT100/CC60/CC60INC/P8.5 VSSM AN13 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN8 AN9 AN10 AN11 AN12 V AGND0 VAREF0 VDDM T13HRB/CCPOS1A/T2EUDA/B/EXTCLK1/OUT54/OUT30/IN54/IN30/P4.2 P1.1/IN17/OUT17/OUT73/T13HRE/CTRAPB P1.11/IN27/IN51/SCLK1B/OUT27/OUT51/CCPOS0C/T2INA/B P1.3/IN19/OUT19/OUT75/COUT63 P1.4/IN20/EMGSTOP/OUT20/OUT76/COUT61 VSS P3.2/SCLK0/OUT86 P3.3/MRST0/OUT87 P3.4/MTSR0/OUT88 P3.5/SLSO00/SLSO10/SLSOANDO0 P3.6/SLSO01/SLSO11/SLSOANDO1 P3.8/SLSO06/TXD1/OUT90/REQ14 P1.9/IN25/IN49/MRST1B/OUT25/OUT49/CCPOS1C/T2EUDA/B VDD VDDP VSS P4.3/IN31/IN55/OUT31/OUT55/EXTCLK0/T12HRE/CTRAPA P1.10/IN26/IN50/OUT26/OUT50/SLSO17 XTAL1 XTAL2 TMS/DAP1 TCK/DAP0 TESTMODEP8.4/OUT99/COUT62/SLSO31 P8.3/SLSI3/CC61INC/CC61/OUT51/SLSO30 P8.13/OUT4/COUT60 P3.7/SLSO02/SLSO12/SLSI0/OUT89 P1.15/BRKIN/BRKOUT TRST P9.5/TDI/BRKIN/BRKOUT P1.0/REQ15/IN16/OUT16/OUT72/T3OUT/BRKIN/BRKOUT PORST ESR1 ESR0 P1.8/IN24/IN48/MTSR1B/OUT24/OUT48/CCPOS2C/T4EUDA/B P9.6/TDO/BRKIN/BRKOUT 1) This pin is used as standby power supply in emulation device. P8.0/SCLK3/CCPOS0C/T3INA/B/OUT48 P8.2/MTSR3/CCPOS2C/T4INA/B/OUT50 P8.1/MRST3/CCPOS1C/T3EUDA/B/OUT49 VDD VDDP P0.0/IN0/HWCFG0/OUT0/OUT56/CC60/CC60INA/B P0.1/IN1/HWCFG1/OUT1/OUT57/SDI1/COUT60 P0.2/IN2/HWCFG2/OUT2/OUT58 P0.3/IN3/HWCFG3/OUT3/OUT59 P0.4/IN4/HWCFG4/OUT4/OUT60/EVTO0 P0.5/IN5/HWCFG5/OUT5/OUT61/EVTO1 P0.6/IN6/REQ2/HWCFG6/OUT6/OUT62/EVTO2 P0.7/IN7/REQ3/HWCFG7/OUT7/OUT63/EVTO3 P0.12/IN12/OUT12/TXENA /OUT68/CTRAPB/T13HRE P0.13/IN13/OUT13/TXENB /OUT69 P0.14/IN14/REQ4/OUT14/OUT70/CC61INC/CC61 P0.15/IN15/REQ5/OUT15/OUT71/COUT61 P2.8/SLSO04/SLSO14/EN00 P2.9/SLSO05/SLSO15/EN01 P2.10/MRST1A P2.11/SCLK1A/FCLP0B P2.12/MTSR1A/SOP0B P2.13/SLSI11/SDI0/CTRAPA/T12HRE/SLSO16/T6OUT P3.0/OUT84/RXD0A/REQ6 P3.1/TXD0/OUT85 P3.9/RXD1A/OUT91 P3.10/REQ0/OUT92 P3.11/REQ1/OUT93 P3.12/RXDCAN0/RXD0B/OUT94 P3.13/TXDCAN0/TXD0/OUT95 P3.14/RXDCAN1/RXD1B/OUT96/SDI2 P3.15/TXDCAN1/TXD1/OUT97 P9.4/CC62INC/CC62/OUT84 P9.3/OUT83/COUT62 P9.2/COUT63/OUT82 1) Only available for SAK-TC1724F-192F133HL, SAK-TC1724F-192F133HR

Data Sheet 3-3 V1.2, 2014-06 121 P0.0 I/O0 A1/ PU Port 0 General Purpose I/O Line 0 IN0 I GPTA0 Input 0 CCU60 I CC60INA CCU61 I CC60INB HWCFG0 I Hardware Configuration Input 0 OUT0 O1 GPTA0 Output 0 OUT56 O2 GPTA0 Output 56 CCU60 O3 CC60 122 P0.1 I/O0 A1/ PU Port 0 General Purpose I/O Line 1 IN1 I GPTA0 Input 1 SDI1 I MSC0 Serial Data Input 1 HWCFG1 I Hardware Configuration Input 1 OUT1 O1 GPTA0 Output 1 OUT57 O2 GPTA0 Output 57 CCU60 O3 COUT60 123 P0.2 I/O0 A1/ PU Port 0 General Purpose I/O Line 2 IN2 I GPTA0 Input 2 HWCFG2 I Hardware Configuration Input 2 OUT2 O1 GPTA0 Output 2 OUT58 O2 GPTA0 Output 58 Reserved O3 - 124 P0.3 I/O0 A1+/ PU Port 0 General Purpose I/O Line 3 IN3 I GPTA0 Input 3 HWCFG3 I Hardware Configuration Input 3 OUT3 O1 GPTA0 Output 3 OUT59 O2 GPTA0 Output 59 Reserved O3 - Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-4 V1.2, 2014-06 134 P0.4 I/O0 A1/ PD Port 0 General Purpose I/O Line 4 IN4 I GPTA0 Input 4 HWCFG4 I Hardware Configuration Input 4 OUT4 O1 GPTA0 Output 4 OUT60 O2 GPTA0 Output 60 EVTO0 O3 MCDS event output 0 135 P0.5 I/O0 A1/ PD Port 0 General Purpose I/O Line 5 IN5 I GPTA0 Input 5 HWCFG5 I Hardware Configuration Input 5 OUT5 O1 GPTA0 Output 5 OUT61 O2 GPTA0 Output 61 EVTO1 O3 MCDS event output 1 141 P0.6 I/O0 A1/ PU Port 0 General Purpose I/O Line 6 IN6 I GPTA0 Input 6 HWCFG6 I Hardware Configuration Input 6 REQ2 I External Request Input 2 OUT6 O1 GPTA0 Output 6 OUT62 O2 GPTA0 Output 62 EVTO2 O3 MCDS event output 2 142 P0.7 I/O0 A1/ PU Port 0 General Purpose I/O Line 7 IN7 I GPTA0 Input 7 HWCFG7 I Hardware Configuration Input 7 REQ3 I External Request Input 3 OUT7 O1 GPTA0 Output 7 OUT63 O2 GPTA0 Output 63 EVTO3 O3 MCDS event output 3 Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-5 V1.2, 2014-06 136 P0.12 I/O0 A2/ PU Port 0 General Purpose I/O Line 12 IN12 I GPTA0 Input 12 CCU60 I CTRAPB CCU61 I T13HRE OUT12 O1 GPTA0 Output 12 OUT68 O2 GPTA0 Output 68 TXENA O3 E-Ray Channel A transmit Data Output enable1) 137 P0.13 I/O0 A2/ PU Port 0 General Purpose I/O Line 13 IN13 I GPTA0 Input 13 OUT13 O1 GPTA0 Output 13 OUT69 O2 GPTA0 Output 69 TXENB O3 E-Ray Channel B transmit Data Output enable1) 143 P0.14 I/O0 A1+/ PU Port 0 General Purpose I/O Line 14 IN14 I GPTA0 Input 14 REQ4 I External Request Input 4 CCU61 I CC61INC OUT14 O1 GPTA0 Output 14 OUT70 O2 GPTA0 Output 70 CCU60 O3 CC61 144 P0.15 I/O0 A1+/ PU Port 0 General Purpose I/O Line 15 IN15 I GPTA0 Input 15 REQ5 I External Request Input 5 OUT15 O1 GPTA0 Output 15 OUT71 O2 GPTA0 Output 71 CCU60 O3 COUT61 Port 1 Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-6 V1.2, 2014-06 92 P1.0 I/O0 A2/ PU Port 1 General Purpose I/O Line 0 REQ15 I External Request Input 15 IN16 I GPTA0 Input 16 BRKIN I Break Input OUT16 O1 GPTA0 Output 16 OUT72 O2 GPTA0 Output 72 GPT120 O3 T3OUT BRKOUT O Break Output (controlled by OCDS module) 95 P1.1 I/O0 A1/ PU Port 1 General Purpose I/O Line 1 IN17 I GPTA0 Input 17 CCU60 I T13HRE CCU61 I CTRAPB OUT17 O1 GPTA0 Output 17 OUT73 O2 GPTA0 Output 73 Reserved O3 - 78 P1.3 I/O0 A1/ PU Port 1 General Purpose I/O Line 3 IN19 I GPTA0 Input 19 OUT19 O1 GPTA0 Output 19 OUT75 O2 GPTA0 Output 75 CCU61 O3 COUT63 79 P1.4 I/O0 A1/ PU Port 1 General Purpose I/O Line 4 IN20 I GPTA0 Input 20 EMGSTOP I Emergency Stop Input OUT20 O1 GPTA0 Output 20 OUT76 O2 GPTA0 Output 76 CCU61 O3 COUT61 Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-7 V1.2, 2014-06 74 P1.8 I/O0 A1+/ PU Port 1 General Purpose I/O Line 8 IN24 I GPTA0 Input 24 IN48 I GPTA0 Input 48 MTSR1B I SSC1 Slave Receive Input B (Slave Mode) CCU61 I CCPOS2C GPT120 I T4EUDB GPT121 I T4EUDA OUT24 O1 GPTA0 Output 24 OUT48 O2 GPTA0 Output 48 MTSR1B O3 SSC1 Master Transmit Output B (Master Mode) 75 P1.9 I/O0 A1+/ PU Port 1 General Purpose I/O Line 9 IN25 I GPTA0 Input 25 IN49 I GPTA0 Input 49 MRST1B I SSC1 Master Receive Input B (Master Mode) CCU61 I CCPOS1C GPT120 I T2EUDB GPT121 I T2EUDA OUT25 O1 GPTA0 Output 25 OUT49 O2 GPTA0 Output 49 MRST1B O3 SSC1 Slave Transmit Output B (Slave Mode) 76 P1.10 I/O0 A1+/ PU Port 1 General Purpose I/O Line 10 IN26 I GPTA0 Input 26 IN50 I GPTA0 Input 50 OUT26 O1 GPTA0 Output 26 OUT50 O2 GPTA0 Output 50 SLSO17 O3 SSC1 Slave Select Output 7 Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-8 V1.2, 2014-06 77 P1.11 I/O0 A1+/ PU Port 1 General Purpose I/O Line 11 IN27 I GPTA0 Input 27 IN51 I GPTA0 Input 51 SCLK1B I SSC1 Clock Input B CCU61 I CCPOS0C GPT120 I T2INB GPT121 I T2INA OUT27 O1 GPTA0 Output 27 OUT51 O2 GPTA0 Output 51 SCLK1B O3 SSC1 Clock Output B 93 P1.15 I/O0 A2/ PU Port 1 General Purpose I/O Line 15 BRKIN I Break Input Reserved O1 - Reserved O2 - Reserved O3 - BRKOUT O Break Output (controlled by OCDS module) Port 2 61 P2.0 I/O0 A2/ PU Port 2 General Purpose I/O Line 0 IN32 I GPTA0 Input 32 CCU60 I CC62INB CCU61 I CC62INA OUT32 O1 GPTA0 Output 32 TCLK0 O2 MLI0 Transmitter Clock Output 0 CCU61 O3 CC62 Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-9 V1.2, 2014-06 62 P2.1 I/O0 A2/ PU Port 2 General Purpose I/O Line 1 IN33 I GPTA0 Input 33 TREADY0A I MLI0 Transmitter Ready Input A CCU61 I CCPOS0A CCU60 I T12HRB GPT120 I T2INA GPT121 I T2INB OUT33 O1 GPTA0 Output 33 SLSO03 O2 SSC0 Slave Select Output Line 3 SLSO13 O3 SSC1 Slave Select Output Line 3 63 P2.2 I/O0 A2/ PU Port 2 General Purpose I/O Line 2 IN34 I GPTA0 Input 34 CCU60 I CC61INB CCU61 I CC61INA OUT34 O1 GPTA0 Output 34 TVALID0A O2 MLI0 Transmitter Valid Output CCU61 O3 CC61 64 P2.3 I/O0 A2/ PU Port 2 General Purpose I/O Line 3 IN35 I GPTA0 Input 35 CCU60 I T12HRC CCU60 I T13HRC CCU61 I CCPOS2A GPT120 I T4EUDA GPT121 I T4EUDB OUT35 O1 GPTA0 Output 35 TDATA0 O2 MLI0 Transmitter Data Output Reserved O3 - Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-10 V1.2, 2014-06 65 P2.4 I/O0 A2/ PU Port 2 General Purpose I/O Line 4 IN36 I GPTA0 Input 36 RCLK0A I MLI Receiver Clock Input A OUT36 O1 GPTA0 Output 36 CCU61 O2 COUT63 Reserved O3 - 66 P2.5 I/O0 A2/ PU Port 2 General Purpose I/O Line 5 IN37 I GPTA0 Input 37 CCU60 I CC60INB CCU61 I CC60INA OUT37 O1 GPTA0 Output 37 RREADY0A O2 MLI0 Receiver Ready Output A CCU61 O3 CC60 67 P2.6 I/O0 A2/ PU Port 2 General Purpose I/O Line 6 IN38 I GPTA0 Input 38 RVALID0A I MLI Receiver Valid Input A Reserved I - OUT38 O1 GPTA0 Output 38 CCU61 O2 COUT62 Reserved O3 - 68 P2.7 I/O0 A2/ PU Port 2 General Purpose I/O Line 7 RDATA0A I MLI Receiver Data Input A IN39 I GPTA0 Input 39 OUT39 O1 GPTA0 Output 39 CCU61 O2 COUT60 Reserved O3 - 132 P2.8 I/O0 A2/ PU Port 2 General Purpose I/O Line 8 SLSO04 O1 SSC0 Slave Select Output 4 SLSO14 O2 SSC1 Slave Select Output 4 EN00 O3 MSC0 Enable Output 0 Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-11 V1.2, 2014-06 128 P2.9 I/O0 A2/ PU Port 2 General Purpose I/O Line 9 SLSO05 O1 SSC0 Slave Select Output 5 SLSO15 O2 SSC1 Slave Select Output 5 EN01 O3 MSC0 Enable Output 1 129 P2.10 I/O0 A1+/ PU Port 2 General Purpose I/O Line 10 MRST1A I SSC1 Master Receive Input A MRST1A O1 SSC1 Slave Transmit Output Reserved O2 - Reserved O3 - 130 P2.11 I/O0 A1+/ PU Port 2 General Purpose I/O Line 11 SCLK1A I SSC1 Clock Input A SCLK1A O1 SSC1 Clock Output A Reserved O2 - FCLP0B O3 MSC0 Clock Output Positive B 131 P2.12 I/O0 A1+/ PU Port 2 General Purpose I/O Line 12 MTSR1A I SSC1 Slave Receive Input A MTSR1A O1 SSC1 Master Transmit Output A Reserved O2 - SOP0B O3 MSC0 Serial Data Output Positive B 133 P2.13 I/O0 A1+/ PU Port 2 General Purpose I/O Line 13 SLSI11 I SSC1 Slave Select Input 1 SDI0 I MSC0 Serial Data Input 0 CCU60 I CTRAPA CCU61 I T12HRE Reserved O1 - SLSO16 O2 SSC1 Slave Select Output 6 GPT120 O3 T6OUT Port 3 Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-12 V1.2, 2014-06 112 P3.0 I/O0 A1+/ PU Port 3 General Purpose I/O Line 0 RXD0A I ASC0 Receiver Input A (Async. & Sync. Mode) REQ6 I External Request Input 6 RXD0A O1 ASC0 Output (Sync. Mode) Reserved O2 - OUT84 O3 GPTA0 Output 84 111 P3.1 I/O0 A1+/ PU Port 3 General Purpose I/O Line 1 TXD0 O1 ASC0 Output Reserved O2 - OUT85 O3 GPTA0 Output 85 105 P3.2 I/O0 A1+/ PU Port 3 General Purpose I/O Line 2 SCLK0 I SSC0 Clock Input (Slave Mode) SCLK0 O1 SSC0 Clock Output (Master Mode) Reserved O2 - OUT86 O3 GPTA0 Output 86 106 P3.3 I/O0 A1+/ PU Port 3 General Purpose I/O Line 3 MRST0 I SSC0 Master Receive Input (Master Mode) MRST0 O1 SSC0 Slave Transmit Output (Slave Mode) Reserved O2 - OUT87 O3 GPTA0 Output 87 108 P3.4 I/O0 A2/ PU Port 3 General Purpose I/O Line 4 MTSR0 I SSC0 Slave Receive Input (Slave Mode) MTSR0 O1 SSC0 Master Transmit Output (Master Mode) Reserved O2 - OUT88 O3 GPTA0 Output 88 102 P3.5 I/O0 A1+/ PU Port 3 General Purpose I/O Line 5 SLSO00 O1 SSC0 Slave Select Output 0 SLSO10 O2 SSC1 Slave Select Output 0 SLSOANDO0 O3 SSC0 AND SSC1 Slave Select Output 0 Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-13 V1.2, 2014-06 103 P3.6 I/O0 A1+/ PU Port 3 General Purpose I/O Line 6 SLSO01 O1 SSC0 Slave Select Output 1 SLSO11 O2 SSC1 Slave Select Output 1 SLSOANDO1 O3 SSC0 AND SSC1 Slave Select Output 1 107 P3.7 I/O0 A2/ PU Port 3 General Purpose I/O Line 7 SLSI0 I SSC0 Slave Select Input 1 SLSO02 O1 SSC0 Slave Select Output 2 SLSO12 O2 SSC1 Slave Select Output 2 OUT89 O3 GPTA0 Output 89 104 P3.8 I/O0 A2/ PU Port 3 General Purpose I/O Line 8 REQ14 I External Request Input 14 SLSO06 O1 SSC0 Slave Select Output 6 TXD1 O2 ASC1 Transmit Output OUT90 O3 GPTA0 Output 90 114 P3.9 I/O0 A1/ PU Port 3 General Purpose I/O Line 9 RXD1A I ASC1 Receiver Input A RXD1A O1 ASC1 Receiver Output A (Synchronous Mode) Reserved O2 - OUT91 O3 GPTA0 Output 91 113 P3.10 I/O0 A1/ PU Port 3 General Purpose I/O Line 10 REQ0 I External Request Input 0 Reserved O1 - Reserved O2 - OUT92 O3 GPTA0 Output 92 120 P3.11 I/O0 A1/ PU Port 3 General Purpose I/O Line 11 REQ1 I External Request Input 1 Reserved O1 - Reserved O2 - OUT93 O3 GPTA0 Output 93 Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-14 V1.2, 2014-06 119 P3.12 I/O0 A1/ PU Port 3 General Purpose I/O Line 12 RXDCAN0 I CAN Node 0 Receiver Input RXD0B I ASC0 Receiver Input B RXD0B O1 ASC0 Receiver Output B (Synchronous Mode) Reserved O2 - OUT94 O3 GPTA0 Output 94 118 P3.13 I/O0 A2/ PU Port 3 General Purpose I/O Line 13 TXDCAN0 O1 CAN Node 0 Transmitter Output TXD0 O2 ASC0 Transmit Output OUT95 O3 GPTA0 Output 95 110 P3.14 I/O0 A1/ PU Port 3 General Purpose I/O Line 14 RXDCAN1 I CAN Node 1 Receiver Input RXD1B I ASC1 Receiver Input B SDI2 I MSC0 Serial Data Input 2 RXD1B O1 ASC1 Receiver Output B (Synchronous Mode) Reserved O2 - OUT96 O3 GPTA0 Output 96 109 P3.15 I/O0 A2/ PU Port 3 General Purpose I/O Line 15 TXDCAN1 O1 CAN Node 1 Transmitter Output TXD1 O2 ASC1 Transmit Output OUT97 O3 GPTA0 Output 97 Port 4 Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-15 V1.2, 2014-06 72 P4.2 I/O0 A2/ PU Port 4 General Purpose I/O Line 2 IN30 I GPTA0 Input 30 IN54 I GPTA0 Input 54 CCU60 I T13HRB CCU61 I CCPOS1A GPT120 I T2EUDA GPT121 I T2EUDB OUT30 O1 GPTA0 Output 30 OUT54 O2 GPTA0 Output 54 EXTCLK1 O3 External Clock 1 Output 73 P4.3 I/O0 A2/ PU Port 4 General Purpose I/O Line 3 IN31 I GPTA0 Input 31 IN55 I GPTA0 Input 55 CCU60 I T12HRE CCU61 I CTRAPA OUT31 O1 GPTA0 Output 31 OUT55 O2 GPTA0 Output 55 EXTCLK0 O3 External Clock 0 Output Port 5 1 P5.0 I/O0 A1+/ PU Port 5 General Purpose I/O Line 0 REQ7 I External Request Input 7 IN40 I GPTA0 Input 40 CCU60 I CC62INA CCU61 I CC62INB GPT120 I CAPINB GPT121 I CAPINA OUT40 O1 GPTA0 Output 40 CCU60 O2 CC62 SLSO20 O3 SSC2 Slave Select Output 0 Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-16 V1.2, 2014-06 2 P5.1 I/O0 A1+/ PU Port 5 General Purpose I/O Line 1 IN41 I GPTA0 Input 41 OUT41 O1 GPTA0 Output 41 Reserved O2 - SLSO21 O3 SSC2 Slave Select Output 1 3 P5.2 I/O0 A1+/ PU Port 5 General Purpose I/O Line 2 IN42 I GPTA0 Input 42 OUT42 O1 GPTA0 Output 42 CCU60 O2 COUT62 SLSO22 O3 SSC2 Slave Select Output 2 4 P5.3 I/O0 A1+/ PU Port 5 General Purpose I/O Line 3 IN43 I GPTA0 Input 43 OUT43 O1 GPTA0 Output 43 Reserved O2 - SLSO23 O3 SSC2 Slave Select Output 3 7 P5.4 I/O0 A1+/ PU Port 5 General Purpose I/O Line 4 IN44 I GPTA0 Input 44 SLSI2A I SSC2 Slave Select Input A OUT44 O1 GPTA0 Output 44 Reserved O2 - SLSO24 O3 SSC2 Slave Select Output 4 8 P5.5 I/O0 A1+/ PU Port 5 General Purpose I/O Line 5 IN45 I GPTA0 Input 45 MRST2A I SSC2 Master Receive Input A (Master Mode) OUT45 O1 GPTA0 Output 45 Reserved O2 - MRST2 O3 SSC2 Slave Transmit Output (Slave Mode) Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-17 V1.2, 2014-06 9 P5.6 I/O0 A1+/ PU Port 5 General Purpose I/O Line 6 IN46 I GPTA0 Input 46 MTSR2A I SSC2 Slave Receive Input (Slave Mode) OUT46 O1 GPTA0 Output 46 Reserved O2 - MTSR2 O3 SSC2 Master Transmit Output (Master Mode) 10 P5.7 I/O0 A1+/ PU Port 5 General Purpose I/O Line 7 IN47 I GPTA0 Input 47 SCLK2A I SSC2 Clock Input A (Slave Mode) OUT47 O1 GPTA0 Output 47 Reserved O2 - SCLK2 O3 SSC2 Clock Output (Master Mode) 15 P5.8 I/O0 A2/ PU Port 5 General Purpose I/O Line 8 CCU60 I CC61INA CCU61 I CC61INB OUT6 O1 GPTA0 Output 6 TXDA1 O2 E-Ray Channel A transmit Data Output1) CCU60 O3 CC61 16 P5.9 I/O0 A2/ PU Port 5 General Purpose I/O Line 9 RXDCAN0 I CAN Node 0 Receiver Input OUT7 O1 GPTA0 Output 7 TXDB1 O2 E-Ray Channel B transmit Data Output1) Reserved O3 - 17 P5.10 I/O0 A2/ PU Port 5 General Purpose I/O Line 10 OUT8 O1 GPTA0 Output 8 TXENA O2 E-Ray Channel A transmit Data Output enable1) CCU60 O3 COUT61 Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-18 V1.2, 2014-06 18 P5.11 I/O0 A2/ PU Port 5 General Purpose I/O Line 11 OUT9 O1 GPTA0 Output 9 TXENB O2 E-Ray Channel B transmit Data Output enable1) CCU60 O3 COUT63 19 P5.12 I/O0 A1+/ PU Port 5 General Purpose I/O Line 12 CCU60 I CCPOS0A CCU61 I T12HRB GPT120 I T3INA GPT121 I T3INB OUT19 O1 GPTA0 Output 19 SLSO07 O2 SSC0 Slave Select Output 7 AD1EMUX0 O3 ADC1 External Multiplexer Control Output 0 20 P5.13 I/O0 A1+/ PU Port 5 General Purpose I/O Line 13 CCU60 I CCPOS1A CCU61 I T13HRB GPT120 I T3EUDA GPT121 I T3EUDB OUT20 O1 GPTA0 Output 20 Reserved O2 - AD1EMUX1 O3 ADC1 External Multiplexer Control Output 1 21 P5.14 I/O0 A1+/ PU Port 5 General Purpose I/O Line 14 RXDA1 I E-Ray Channel A Receive Data Input 11) CCU60 I CCPOS2A CCU61 I T12HRC CCU61 I T13HRC GPT120 I T4INA GPT121 I T4INB OUT36 O1 GPTA0 Output 36 Reserved O2 - AD1EMUX2 O3 ADC1 External Multiplexer Control Output 2 Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-19 V1.2, 2014-06 11 P5.15 I/O0 A1+/ PU Port 5 General Purpose I/O Line 15 RXDB1 I E-Ray Channel B Receive Data Input 11) OUT37 O1 GPTA0 Output 37 Reserved O2 - TXDCAN0 O3 CAN Node 0 Transmitter Output Port 8 117 P8.0 I/O0 A2/ PU Port 8 General Purpose I/O Line 0 SCLK3 I SSC3 Clock Input (Slave Mode) CCU60 I CCPOS0C GPT120 I T3INB GPT121 I T3INA Reserved O1 - OUT48 O2 GPTA0 Output 48 SCLK3 O3 SSC3 Clock Output (Master Mode) 116 P8.1 I/O0 A2/ PU Port 8 General Purpose I/O Line 1 MRST3 I SSC3 Master Receive Input (Master Mode) CCU60 I CCPOS1C GPT120 I T3EUDB GPT121 I T3EUDA Reserved O1 - OUT49 O2 GPTA0 Output 49 MRST3 O3 SSC3 Slave Transmit Output (Slave Mode) 115 P8.2 I/O0 A2/ PU Port 8 General Purpose I/O Line 2 MTSR3 I SSC3 Slave Receive Input (Slave Mode) CCU60 I CCPOS2C GPT120 I T4INB GPT121 I T4INA Reserved O1 - OUT50 O2 GPTA0 Output 50 MTSR3 O3 SSC3 Master Transmit Output (Master Mode) Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-20 V1.2, 2014-06 100 P8.3 I/O0 A2/ PU Port 8 General Purpose I/O Line 3 SLSI3 I SSC3 Slave Select Input B CCU60 I CC61INC CCU61 O1 CC61 OUT51 O2 GPTA0 Output 51 SLSO30 O3 SSC3 Slave Select Output 0 99 P8.4 I/O0 A2/ PU Port 8 General Purpose I/O Line 4 OUT99 O1 GPTA0 Output 99 CCU61 O2 COUT62 SLSO31 O3 SSC3 Slave Select Output 1 69 P8.5 I/O0 A2/ PU Port 8 General Purpose I/O Line 5 CCU60 I CC60INC OUT100 O1 GPTA0 Output 100 CCU61 O2 CC60 SLSO32 O3 SSC3 Slave Select Output 2 70 P8.6 I/O0 A2/ PU Port 8 General Purpose I/O Line 6 OUT101 O1 GPTA0 Output 101 Reserved O2 - CCU61 O3 COUT61 71 P8.7 I/O0 A2/ PU Port 8 General Purpose I/O Line 7 CCU60 I CC62INC OUT102 O1 GPTA0 Output 102 Reserved O2 - CCU61 O3 CC62 101 P8.13 I/O0 A2/ PU Port 8 General Purpose I/O Line 13 OUT4 O1 GPTA0 Output 4 Reserved O2 - CCU61 O3 COUT60 Port 9 Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-21 V1.2, 2014-06 5 P9.0 I/O0 A1/ PU Port 9 General Purpose I/O Line 0 RXDCAN2 I CAN Node 2 Receiver Input Reserved O1 - OUT80 O2 GPTA0 Output 80 Reserved O3 - 6 P9.1 I/O0 A2/ PU Port 9 General Purpose I/O Line 1 TXDCAN2 O1 CAN Node 2 Transmitter Output OUT81 O2 GPTA0 Output 81 Reserved O3 - 140 P9.2 I/O0 A1/ PU Port 9 General Purpose I/O Line 2 Reserved O1 - OUT82 O2 GPTA0 Output 82 CCU60 O3 COUT63 139 P9.3 I/O0 A1/ PU Port 9 General Purpose I/O Line 3 Reserved O1 - OUT83 O2 GPTA0 Output 83 CCU60 O3 COUT62 138 P9.4 I/O0 A1/ PU Port 9 General Purpose I/O Line 4 CCU61 I CC62INC Reserved O1 - OUT84 O2 GPTA0 Output 84 CCU60 O3 CC62 87 P9.5 I/O0 A2/ PU Port 9 General Purpose I/O Line 5 TDI I JTAG Serial Data Input BRKIN I OCDS Break Input Reserved O1 - Reserved O2 - Reserved O3 - BRKOUT O OCDS Break Output (controlled by OCDS module) Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-22 V1.2, 2014-06 89 P9.6 I/O0 A2/ PU Port 9 General Purpose I/O Line 6 TDO I JTAG Serial Data Output BRKIN I OCDS Break Input Reserved O1 - Reserved O2 - Reserved O3 - BRKOUT O OCDS Break Output (controlled by OCDS module) TDO O JTAG Serial Data Output (controlled by OCDS module) 13 P9.7 I/O0 A1/ PU Port 9 General Purpose I/O Line 7 CCU61 I CC60INC Reserved O1 - OUT87 O2 GPTA0 Output 87 CCU60 O3 CC60 14 P9.8 I/O0 A1/ PU Port 9 General Purpose I/O Line 7 Reserved O1 - OUT88 O2 GPTA0 Output 88 CCU60 O3 COUT60 Port 11 38 P11.0 I D / S Port 11 General Purpose I/O Line 02) Dig0 I Digital Input 0 AN16 I Analog Input : ADC1.CH0 3) 37 P11.3 I D / S Port 11 General Purpose I/O Line 32) Dig3 I Digital Input 3 AN19 I Analog Input : ADC1.CH3 3) 36 P11.7 I D / S Port 11 General Purpose I/O Line 72) Dig7 I Digital Input 7 AN23 I Analog Input : ADC1.CH7 3) Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-23 V1.2, 2014-06 35 P11.9 I D / S Port 11 General Purpose I/O Line 92) Dig9 I Digital Input 9 AN25 I Analog Input : ADC1.CH9 3) Port 12 29 P12.0 I D / S Port 12 General Purpose I/O Line 02) Dig16 I Digital Input 16 AN36 I Analog Input : ADC1.CH20 3) 28 P12.1 I D / S Port 12 General Purpose I/O Line 12) Dig17 I Digital Input 17 AN37 I Analog Input : ADC1.CH21 3) 27 P12.2 I D / S Port 12 General Purpose I/O Line 22) Dig18 I Digital Input 18 AN38 I Analog Input : ADC1.CH22 3) 26 P12.3 I D / S Port 12 General Purpose I/O Line 32) Dig19 I Digital Input 19 AN39 I Analog Input : ADC1.CH23 3) Analog Input Port 57 AN0 I D Analog Input 0: ADC0.CH0 3) 56 AN1 I D Analog Input 1: ADC0.CH1 3) 55 AN2 I D Analog Input 2: ADC0.CH2 3) 54 AN3 I D Analog Input 3: ADC0.CH3 3) 53 AN4 I D Analog Input 4: ADC0.CH4 3) 52 AN5 I D Analog Input 5: ADC0.CH5 3) 51 AN6 I D Analog Input 6: ADC0.CH6 3) 34 AN7 I D Analog Input 7: ADC0.CH7 3) 50 AN8 I D Analog Input 8: ADC0.CH8 3) 49 AN9 I D Analog Input 9: ADC0.CH9 3) 48 AN10 I D Analog Input 10: ADC0.CH10 3) 47 AN11 I D Analog Input 11: ADC0.CH11 3) 46 AN12 I D Analog Input 12: ADC0.CH12 3) Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-24 V1.2, 2014-06 45 AN13 I D Analog Input 13: ADC0.CH13 3) 40 AN14 I D Analog Input 14: ADC0.CH14 3) 39 AN15 I D Analog Input 15: ADC0.CH15 3) 38 AN16 I D / S Analog Input 16: ADC1.CH0, Dig0 3) 37 AN19 I D / S Analog Input 19: ADC1.CH3, Dig3 3) 36 AN23 I D / S Analog Input 23: ADC1.CH7, Dig7 3) 35 AN25 I D / S Analog Input 25: ADC1.CH9, Dig9 3)

33 AN32 I D Analog Input 32: FADC_FADIN0P 4)

32 AN33 I D Analog Input 33: FADC_FADIN0N 4)

31 AN34 I D Analog Input 34: FADC_FADIN1P 4)

30 AN35 I D Analog Input 35: FADC_FADIN1N 4)

29 AN36 I D / S Analog Input 36: ADC1.CH20, Dig16 3) 28 AN37 I D / S Analog Input 37: ADC1.CH21, Dig17 3) 27 AN38 I D / S Analog Input 37: ADC1.CH22, Dig18 3) 26 AN39 I D / S Analog Input 37: ADC1.CH23, Dig19 3) 44 VDDM -- ADC Analog Part Power Supply (3.3V - 5V)

43 VSSM -- ADC Analog Part Ground

42 VAREF0 -- ADC0 and ADC1 Reference Voltage

41 VAGND0 -- ADC Reference Ground

12, 235), 58, 84, 125 VDD -- Digital Core Power Supply (1.3V) 22, 59, 85, 126 VDDP -- Port Power Supply (3.3V) Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-25 V1.2, 2014-06 24, 60, 127 V5 -- EVR Power Supply (5V)

25 VPDG -- EVR Pass Device Gate

If this pin is connected to ground, the internal pass devices are used and the external pass device bypassed. 80, VSS -- Digital Ground

81 XTAL1 I Main Oscillator Input

82 XTAL2 O Main Oscillator Output

88 TMS I A2/

JTAG State Machine Control Input DAP1 I/O Device Access Port Line 1

90 TRST I A1/

91 TCK I A1/

DAP0 I Device Access Port Line 0

94 TESTMODE I I/PU Test Mode Select Input

96 ESR1 I/O A2/

External System Request Reset Input 1

97 PORST I I/PU Power On Reset

98 ESR0 I/O A2 External System Request Reset Input 0

Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset. 1) Only applicable for SAK-TC1724F -192F133HL, SAK-TC1724F-192F133HR. 2) Analog input overlayed with digital input functionality. The related port logic is used to configure the input as either analog input (default after reset) or digital input. The related port logic supports only the port input features as the connected pads are input only pads. 3) IOZ1 valid for this pin is the parameter with overlayed = No in the ADC parameter table. 4) IOZ1 valid for this pin is the parameter with overlayed = Yes in the ADC parameter table. 5) For the emulation device (ED), this pin is bonded to VDD SB (ED Stand By RAM supply). In the production devide device, this pin is bonded to a VDD pad. Table 3-1 Pin Definitions and Functions ( PG-LQFP-144-17 package) (cont’d) Pin Symbol Ctrl. Type Function

Data Sheet 3-26 V1.2, 2014-06 Legend for Table 3-1 Column “Ctrl.”: I = Input (for GPIO port lines with IOCR bit field selection PCx = 0XXXB) O = Output O0 = Output with IOCR bit field selection PCx = 1X00B O1 = Output with IOCR bit field selection PCx = 1X01B (ALT1) O2 = Output with IOCR bit field selection PCx = 1X10B(ALT2) O3 = Output with IOCR bit field selection PCx = 1X11(ALT3) Column “Type”: A1 = Pad class A1 (LVTTL) A1+ = Pad class A1+ (LVTTL) A2 = Pad class A2 (LVTTL) D = Pad class D (ADC) I = Pad class I (LVTTL) S = Pad class D (ADC) / Pad class S (Digital) PU = with pull-up device connected during reset (PORST = 0) PD = with pull-down device connected during reset (PORST = 0) TR = tri-state during reset (PORST = 0)

Data Sheet 4-1 V1.2, 2014-06

4 Identification Registers

The Identification Registers uniquely identify the device. Table 2 SAK-TC1724F-192F133HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 H F000 0408H AB CBS_JTAGID 101D 0083 H F000 0464H AB SCU_MANID 0000 1820 H F000 0644H AB SCU_CHIPID 0300 A601 H F000 0640H AB SCU_RTID 0000 0001 H F000 0648H AB Table 3 SAK-TC1724F-192F133HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 H F000 0408H AB CBS_JTAGID 101D 0083 H F000 0464H AB SCU_MANID 0000 1820 H F000 0644H AB SCU_CHIPID 8300 A601 H F000 0640H AB SCU_RTID 0000 0001 H F000 0648H AB Table 4 SAK-TC1724F-192F133HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 H F000 0408H AC CBS_JTAGID 101D 0083 H F000 0464H AC SCU_MANID 0000 1820 H F000 0644H AC SCU_CHIPID 8300 A601 H F000 0640H AC SCU_RTID 0000 0002 H F000 0648H AC Table 5 SAK-TC1724N-192F133HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 H F000 0408H AC CBS_JTAGID 101D 0083 H F000 0464H AC SCU_MANID 0000 1820 H F000 0644H AC

Data Sheet 4-2 V1.2, 2014-06 SCU_CHIPID 8300 9B01 H F000 0640H AC SCU_RTID 0000 0002 H F000 0648H AC Table 6 SAK-TC1724N-192F80HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 H F000 0408H AB CBS_JTAGID 101D 0083 H F000 0464H AB SCU_MANID 0000 1820 H F000 0644H AB SCU_CHIPID 1300 9B01 H F000 0640H AB SCU_RTID 0000 0001 H F000 0648H AB Table 7 SAK-TC1724N-192F80HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 H F000 0408H AB CBS_JTAGID 101D 0083 H F000 0464H AB SCU_MANID 0000 1820 H F000 0644H AB SCU_CHIPID 9300 9B01 H F000 0640H AB SCU_RTID 0000 0001 H F000 0648H AB Table 8 SAK-TC1724N-192F80HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 H F000 0408H AC CBS_JTAGID 101D 0083 H F000 0464H AC SCU_MANID 0000 1820 H F000 0644H AC SCU_CHIPID 9300 9B01 H F000 0640H AC SCU_RTID 0000 0002 H F000 0648H AC Table 5 SAK-TC1724N-192F133HR Identification Registers (cont’d) Short Name Value Address Stepping

Data Sheet 5-1 V1.2, 2014-06

5 Electrical Parameters

This specification provides all electrical parameters of the TC1724.

5.1 General Parameters

5.1.1 Parameter Interpretation

The parameters listed in this section partly represent the characteristics of the TC1724 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column “Symbol”:

• CC Such parameters indicate Controller Characteristics which are a distinctive feature of the TC1724 and must be regarded for a system design.
• SR Such parameters indicate System Requirements which must provided by the microcontroller system in which the TC1724 designed in.

Data Sheet 5-2 V1.2, 2014-06

5.1.2 Pad Driver and Pad Classes Summary

This section gives an overview on the different pad driver classes and its basic characteristics. More details (mainly DC parameters) are defined in the Section 5.2.1. Table 9 Pad Driver and Pad Classes Overview Class Power Supply Type Sub Class Speed Grade Load Leakage 1) 150°C 1) Two values are given: for TJ = 150 °C and a 50% higher value for TJ = 160 °C. Termination A 3.3 V LVTTL I/O, LVTTL outputs (e.g. GPIO)

6 MHz 100 pF 500 nA No

(e.g. serial I/Os) MHz 50 pF 1 μAS e r i e s termination recommended (e.g. serial I/Os) MHz 50 pF 3 μAS e r i e s termination recommended DE 5V A D C – – – – I 3.3 V LVTTL (input only) –– – –

Data Sheet 5-3 V1.2, 2014-06

5.1.3 Absolute Maximum Ratings

Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any ot her conditions above those indicated in the operational sections of this specificat ion is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 10 Absolute Maximum Rating Parameters Parameter Symbol Values Unit Note / Test Con dition Min. Typ. Max. Storage temperature TST SR -65 – 160 °C– Voltage at 1.3 V power supply pins with respect to VSS VDD SR – – 2.0 V – Voltage at 3.3 V power supply pins with respect to VSS VDDP SR ––4 . 3 3 V– Voltage at 5 V power supply pins with respect to VSS VDDM SR – – 7.0 V – Voltage on any Class A input pin and dedicated input pins with respect to VSS VIN SR -0.6 – VDDP + 0.5 or max. 4.33 V Whatever is lower Voltage on any Class D analog input pin with respect to VAGND VAIN VAREFx SR -0.6 – 7.0 V – Voltage on any shared Class D analog input pin with respect to VSSAF, if the FADC is switched through to the pin. VAINF SR -0.6 – 7.0 V – Input current on any pin during overload condition IIN -10 – +10 mA Absolute maximum sum of all input circuit currents for one port group during overload condition1) IIN -75 – +75 mA Absolute maximum sum of all input circuit currents during overload condition Σ IIN – – |200| mA

Data Sheet 5-4 V1.2, 2014-06 1) The port groups are defined in Table 15.

Data Sheet 5-5 V1.2, 2014-06

5.1.4 Pin Reliability in Overload

When receiving signals from higher voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own IO power supplies specification. Table 11 defines overload conditions that will not cause any negative reliability impact if all the following conditions are met:

• full operation life-time (24000 h) is not exceeded
• Operating Conditions are met for – pad supply levels ( VDDP or VDDM) – temperature If a pin current is out of the Operating Conditions but within the overload parameters, then the parameters functionality of this pin as stated in the Operating Conditions can no longer be guaranteed. Operat ion is still possible in mo st cases but with relaxed parameters. Note: An overload condition on one or more pins does not require a reset. Note: FADC input pins count as analog pin as they are overlayed with an ADC pins. Table 11 Overload Parameters Parameter Symbol Values Unit Note / Test Con dition Min. Typ. Max. Input current on any digital pin during overload condition IIN -5 – +5 mA Absolute sum of all input circuit currents for one port group during overload condition 1) The port groups are defined in Table 15. IING -70 – +70 mA Input current on analog pins IINANA -3 – +3 mA Absolute sum of all analog input currents for analog inputs of a single ADC during overload condition IINSAS -15 – +15 mA Absolute sum of all input circuit currents during overload condition Σ IINS -100 – 100 mA

Data Sheet 5-6 V1.2, 2014-06 Note: A series resistor at the pin to limit the current to the maximum permitted overload current is sufficient to handle failure situations like short to battery without having any negative reliability impact on the operational life-time. Table 12 PN-Junction Characteris itics for positive Overload Pad Type IIN =3m A IIN =5m A A1 / A1+ UIN = VDDP +0 . 6V UIN = VDDP +0 . 7V A2 UIN = VDDP +0 . 5V UIN = VDDP +0 . 6V D / S UIN = VDDM +0 . 6V - Table 13 PN-Junction Characterisitics for negative Overload Pad Type IIN =- 3m A IIN =- 5m A A1 / A1+ UIN = VSS -0 . 6V UIN = VSS -0 . 7V A2 UIN = VSS -0 . 5V UIN = VSS -0 . 6V D / S UIN = VSSM -0 . 6V -

Data Sheet 5-7 V1.2, 2014-06

5.1.5 Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct operation and reliability of t he TC1724. All parameters specif ied in the following tables refer to these operating conditions, unless otherwise noticed. Digital supply voltages applied to the TC 1724 from external must be static regulated voltages which allow a typical voltage swing of ± 5 %. All parameters specified in the following tables refer to these operating conditions (Table 14), unless otherwise noticed in the Note / Test Condition column. Table 14 Operating Conditions Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ Max. Overload coupling factor for analog inputs, negative KOVAN CC −− 0.0001 IOV≥ -2 mA; IOV≤ 0 mA; analog pad= 5.0 V Overload coupling factor for analog inputs, positive KOVAP CC −− 0.00001 IOV≥ 0m A ; IOV≤ 3 mA; analog pad= 5.0 V CPU Frequency fCPU SR −− 133 MHz SAK-TC1724F- 192F133HL; SAK-TC1724F- 192F133HR; SAK-TC1724N- 192F133HR −− 80 MHz SAK-TC1724N- 192F80HL; SAK-TC1724N- 192F80HR

Data Sheet 5-8 V1.2, 2014-06 FPI Frequency fFPI SR −− 110 MHz SAK-TC1724F- 192F133HL; SAK-TC1724F- 192F133HR; SAK-TC1724N- 192F133HR −− 80 MHz SAK-TC1724N- 192F80HL; SAK-TC1724N- 192F80HR LMB Frequency fLMB SR −− 133 MHz SAK-TC1724F- 192F133HL; SAK-TC1724F- 192F133HR; SAK-TC1724N- 192F133HR −− 80 MHz SAK-TC1724N- 192F80HL; SAK-TC1724N- 192F80HR PCP Frequency fPCP SR −− 133 MHz SAK-TC1724F- 192F133HL; SAK-TC1724F- 192F133HR; SAK-TC1724N- 192F133HR −− 80 MHz SAK-TC1724N- 192F80HL; SAK-TC1724N- 192F80HR Inactive device pin current IID SR -1 − 1m A All power supply voltages V DDx = 0 Short circuit current of digital outputs1) ISC SR -5 − 5m A Table 14 Operating Conditions Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ Max.

Data Sheet 5-9 V1.2, 2014-06 Absolute sum of short circuit currents of the device ΣISC_D CC −− 100 mA Absolute sum of short circuit currents per pin group Σ ISC_PG CC −− 70 mA Ambient Temperature TA SR -40 − 125 °C Junction temperature TJ SR -40 − 160 °C Core Supply Voltage VDD SR 1.17 1.3 1.43 2) V Only required if externally supplied5) ADC analog supply voltage VDDM SR 2.97 5.0 5.5 3) V EVR supply voltage V5 SR 4.00 5.0 5.5 V 5.0V single supply 2.97 3.3 3.63 V 3.3V single supply Digital supply voltage for IO pads VDDP SR 2.97 3.3 3.63 4) V Only required if externally supplied5) VDDP voltage to ensure defined pad states VDDPPA CC 0.65 −− V Digital ground voltage VSS SR 0 −− V Analog ground voltage for VDDM VSSM SR -0.1 0 0.1 V 1) Applicable for digital outputs. 2) Voltage overshoot to 1.7V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 μs and the cumulated sum of the pulses does not exceed 1 h. 3) Voltage overshoot to 6.5V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 μs and the cumulated sum of the pulses does not exceed 1 h. 4) Voltage overshoot to 4.0V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 μs and the cumulated sum of the pulses does not exceed 1 h. 5) No external inductive load permissable if EVR is used. 6) This parameter is valid under the assumption the PORST signal is constantly at low level during the power- up/power-down of VDDP. Table 14 Operating Conditions Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ Max.

Data Sheet 5-10 V1.2, 2014-06 Table 15 Pin Groups for Overload / Short-Circuit Current Sum Parameter Group Pins P8.[2:0], P9.[4:2]

Data Sheet 5-11 V1.2, 2014-06

5.2 DC Parameters

5.2.1 Input/Output Pins

Table 16 Standard_Pads Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Pin capacitance (digital inputs/outputs) CIO CC −− 10 pF TA=2 5° C ; f=1M H z Pull-down current | IPDL| CC −− 150 μA Vi≥ 0.6 x VDDP V 10 −−μ A Vi≥ 0.36 x VDDP V Pull-Up current | IPUH| CC 10 −−μ A Vi≤ 0.6 x VDDP V −− 100 μA Vi≤ 0.36 x VDDP V Spike filter always blocked pulse duration tSF1 CC −− 10 ns only PORST pin Spike filter pass-through pulse duration tSF2 CC 120 −− ns only PORST pin Table 17 Standard_Pads Class_A1 Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Input Hysteresis for pads of all A classes1) HYSA CC 0.1 x VDDP −− V Input Leakage Current Class A1 IOZA1 CC -500 − 500 nA Vi≤ VDDP V; Vi≥ 0V ; -40°C ≤ TJ ≤ 150°C -750 − 750 nA Vi≤ VDDP V; Vi≥ 0V ; 150°C < TJ ≤ 160°C Ratio Vil/Vih, A1 pads VILA1 / VIHA1 CC 0.6 −−

Data Sheet 5-12 V1.2, 2014-06 On-Resistance of the class A1 pad, weak driver RDSONW CC − 450 600 Ohm IOH>- 0 . 5m A ; P_MOS − 210 340 Ohm IOL<0 . 5m A ; N_MOS On-Resistance of the class A1 pad, medium driver RDSONM CC −− 155 Ohm IOH>- 2m A ; P_MOS −− 110 Ohm IOL<2m A ; N_MOS Fall time,pad type A1 tFA1 CC −− 150 ns CL= 20 pF; pin out driver= weak −− 50 ns CL= 50 pF; pin out driver= medium −− 140 ns CL= 150 pF; pin out driver= medium −− 550 ns CL= 150 pF; pin out driver= weak −− 18000 ns CL= 20000 pF; pin out driver= medium −− 65000 ns CL= 20000 pF; pin out driver= weak Rise time, pad type A1 tRA1 CC −− 150 ns CL= 20 pF; pin out driver= weak −− 50 ns CL= 50 pF; pin out driver= medium −− 140 ns CL= 150 pF; pin out driver= medium −− 550 ns CL= 150 pF; pin out driver= weak −− 18000 ns CL= 20000 pF; pin out driver= medium −− 65000 ns CL= 20000 pF; pin out driver= weak Table 17 Standard_Pads Class_A1 (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Data Sheet 5-13 V1.2, 2014-06 Input high voltage, class A1 pads VIHA1 SR 0.6 x VDDP − min(VD DP + 0.3, 3.6) V Input low voltage, class A1 pads VILA1 SR -0.3 − 0.36 x VDDP V Output voltage high, class A1 pads VOHA1 CC VDDP - 0.4 −− V IOH≥ -1.4 mA; pin out driver= medium 2.4 −− V IOH≥ -2 mA; pin out driver= medium VDDP - 0.4 −− V IOH≥ -400 μA; pin out driver= weak 2.4 −− V IOH≥ -500 μA; pin out driver= weak Output voltage low, class A1 pads VOLA1 CC −− 0.4 V IOL≤ 2 mA; pin out driver= medium −− 0.4 V IOL≤ 500 μA; pin out driver= weak 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be guaranteed that it suppresses switching due to external system noise. Table 18 Standard_Pads Class_A1+ Parameter Symbo l Values Unit Note / Test ConditionMin. Typ Max. Input Hysteresis for A1+ pads 1) HYSA1 + CC 0.1 x VDDP −− V Input Leakage Current Class A1+ IOZA1+ CC -1000 − 1000 nA Table 17 Standard_Pads Class_A1 (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Data Sheet 5-14 V1.2, 2014-06 On-Resistance of the class A1+ pad, weak driver RDSONW CC − 450 600 Ohm IOH>- 0 . 5m A ; P_MOS − 210 340 Ohm IOL<0 . 5m A ; N_MOS On-Resistance of the class A1+ pad, medium driver RDSONM CC −− 155 Ohm IOH>- 2m A ; P_MOS −− 110 Ohm IOL<2m A ; N_MOS On-Resistance of the class A1+ pad, strong driver RDSON1+ CC −− 110 Ohm IOH>- 2m A ; P_MOS −− 80 Ohm IOL<2m A ; N_MOS Fall time, pad type A1+ tFA1+ C C −− 150 ns CL= 20 pF; pin out driver= weak −− 28 ns CL=5 0p F ; edge= slow; pin out driver= strong −− 16 ns CL=5 0p F ; edge= soft ; pin out driver= strong −− 50 ns CL= 50 pF; pin out driver= medium −− 140 ns CL= 150 pF; pin out driver= medium −− 550 ns CL= 150 pF; pin out driver= weak −− 18000 ns CL= 20000 pF; pin out driver= medium −− 65000 ns CL= 20000 pF; pin out driver= weak Table 18 Standard_Pads Class_A1+ (cont’d) Parameter Symbo l Values Unit Note / Test ConditionMin. Typ Max.

Data Sheet 5-15 V1.2, 2014-06 Rise time, pad type A1+ tRA1+ C C −− 150 ns CL= 20 pF; pin out driver= weak −− 28 ns CL=5 0p F ; edge= slow ; pin out driver= strong −− 16 ns CL=5 0p F ; edge= soft ; pin out driver= strong −− 50 ns CL= 50 pF; pin out driver= medium −− 140 ns CL= 150 pF; pin out driver= medium −− 550 ns CL= 150 pF; pin out driver= weak −− 18000 ns CL= 20000 pF; pin out driver= medium −− 65000 ns CL= 20000 pF; pin out driver= weak Input high voltage, Class A1+ pads VIHA1+ SR 0.6 x VDDP − min(VD DP + 0.3, 3.6) V Input low voltage, Class A1+ pads VILA1+ SR -0.3 − 0.36 x VDDP V Ratio Vil/Vih, A1+ pads VILA1+ / VIHA1+ CC 0.6 −− Table 18 Standard_Pads Class_A1+ (cont’d) Parameter Symbo l Values Unit Note / Test ConditionMin. Typ Max.

Data Sheet 5-16 V1.2, 2014-06 Output voltage high, class A1+ pads VOHA1+ CC VDDP - 0.4 −− V IOH≥ -1.4 mA; pin out driver= medium VDDP - 0.4 −− V IOH≥ -1.4 mA; pin out driver= strong 2.4 −− V IOH≥ -2 mA; pin out driver= medium 2.4 −− V IOH≥ -2 mA; pin out driver= strong VDDP - 0.4 −− V IOH≥ -400 μA; pin out driver= weak 2.4 −− V IOH≥ -500 μA; pin out driver= weak Output voltage low, class A1+ pads VOLA1+ CC −− 0.4 V IOL≤ 2 mA; pin out driver= medium −− 0.4 V IOL≤ 2 mA; pin out driver= strong −− 0.4 V IOL≤ 500 μA; pin out driver= weak 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be guaranteed that it suppresses switching due to external system noise. Table 19 Standard_Pads Class_A2 Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Input Hysteresis for A2 pads 1) HYSA2 CC 0.1 x VDDP −− V Table 18 Standard_Pads Class_A1+ (cont’d) Parameter Symbo l Values Unit Note / Test ConditionMin. Typ Max.

Data Sheet 5-17 V1.2, 2014-06 Input Leakage current Class A2 IOZA2 CC -6000 − 6000 nA Vi< VDDP / 2 - 1 V; Vi> VDDP / 2 + 1 V; Vi≥ 0V ; Vi≤ VDDP V -3000 − 3000 nA Vi> VDDP / 2 - 1 V; Vi< VDDP / 2 + 1 V Ratio Vil/Vih, A2 pads VILA2 / VIHA2 CC 0.6 −− On-Resistance of the class A2 pad, weak driver RDSONW CC − 450 600 Ohm IOH>- 0 . 5m A ; P_MOS − 210 340 Ohm IOL<0 . 5m A ; N_MOS On-Resistance of the class A2 pad, medium driver RDSONM CC −− 155 Ohm IOH>- 2m A ; P_MOS −− 110 Ohm IOL<2m A ; N_MOS On-Resistance of the class A2 pad, strong driver RDSON2 CC −− 42 Ohm IOH>- 2m A ; P_MOS −− 22 Ohm IOL<2m A ; N_MOS Table 19 Standard_Pads Class_A2 (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Data Sheet 5-18 V1.2, 2014-06 Fall time, pad type A2 tFA2 CC −− 150 ns CL=2 0p F ; pin out driver= weak −− 7n s CL=5 0p F ; edge= medium ; pin out driver= strong −− 10 ns CL=5 0p F ; edge= medium- minus ; pin out driver= strong −− 3.7 ns CL=5 0p F ; edge= sharp ; pin out driver= strong −− 5n s CL=5 0p F ; edge= sharp- minus ; pin out driver= strong −− 16 ns CL=5 0p F ; edge= soft ; pin out driver= strong −− 50 ns CL= 50 pF; pin out driver= medium −− 7.5 ns CL=1 0 0p F ; edge= sharp ; pin out driver= strong −− 140 ns CL=1 5 0p F ; pin out driver= medium Table 19 Standard_Pads Class_A2 (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Data Sheet 5-19 V1.2, 2014-06 −− 550 ns CL= 150 pF; pin out driver= weak −− 18000 ns CL= 20000 pF; pin out driver= medium −− 65000 ns CL= 20000 pF; pin out driver= weak Rise time, pad type A2 tRA2 CC −− 150 ns CL= 20 pF; pin out driver= weak −− 7.0 ns CL=5 0p F ; edge= medium ; pin out driver= strong −− 10 ns CL=5 0p F ; edge= medium- minus ; pin out driver= strong −− 3.7 ns CL=5 0p F ; edge= sharp ; pin out driver= strong −− 5n s CL=5 0p F ; edge= sharp- minus ; pin out driver= strong −− 16 ns CL=5 0p F ; edge= soft ; pin out driver= strong −− 50 ns CL= 50 pF; pin out driver= medium −− 7.5 ns CL=1 0 0p F ; edge= sharp ; pin out driver= strong −− 140 ns CL= 150 pF; pin out driver= medium Table 19 Standard_Pads Class_A2 (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Data Sheet 5-20 V1.2, 2014-06 −− 550 ns CL= 150 pF; pin out driver= weak −− 18000 ns CL= 20000 pF; pin out driver= medium −− 65000 ns CL= 20000 pF; pin out driver= weak Input high voltage, class A2 pads VIHA2 SR 0.6 x VDDP − min(VDDP + 0.3, 3.6) V Input low voltage, Class A2 pads VILA2 SR -0.3 − 0.36 x VDDP V Output voltage high, class A2 pads VOHA2 CC VDDP - 0.4 −− V IOH≥ -1.4 mA; pin out driver= medium VDDP - 0.4 −− V IOH≥ -1.4 mA; pin out driver= strong 2.4 −− V IOH≥ -2 mA; pin out driver= medium 2.4 −− V IOH≥ -2 mA; pin out driver= strong VDDP - 0.4 −− V IOH≥ -400 μA; pin out driver= weak 2.4 −− V IOH≥ -500 μA; pin out driver= weak Output voltage low, class A2 pads VOLA2 CC −− 0.4 V IOL≤ 2 mA; pin out driver= medium −− 0.4 V IOL≤ 2 mA; pin out driver= strong −− 0.4 V IOL≤ 500 μA; pin out driver= weak 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be guaranteed that it suppresses switching due to external system noise. Table 19 Standard_Pads Class_A2 (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Data Sheet 5-21 V1.2, 2014-06 Class S pad parameters are only valid for VDDM = 4.75 V to 5.25 V. Table 20 Standard_Pads Class_I Parameter Symbol Values Unit Note / Test Condit ion Min. Typ. Max. Input Hysteresis Class I1) 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be guaranteed that it suppresses switching due to external system noise. HYSI CC 0.1 x VDDP −− V Input Leakage Current IOZI CC -1000 − 1000 nA -40°C ≤ TJ ≤ 150°C -1500 − 1500 nA 150°C < TJ ≤ 160°C Ratio between low and high input threshold VILI / VIHI CC 0.6 −− Input high voltage, class I pins VIHI SR 0.6 x VDDP − min(VD DP + 0.3, 3.6) V Input low voltage, Class I pads VILI SR -0.3 − 0.36 x VDDP V Table 21 Standard_Pads Class_S Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Input Hysteresis for class S pads1) HYSS CC 0.3 −− V Input leakage current IOZS CC −300 − 300 nA Input voltage high VIHS CC −− 3.6 V

Data Sheet 5-22 V1.2, 2014-06 Input voltage low VILS CC 1.9 −− V VILS Delta 2) VILSD CC -50 − 50 mV Maximum input low state treshold variation over 1ms VDDP =c o n s t a nt) 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be guaranteed that it suppresses switching due to external system noise. 2) V ILSD is implemented to ensure J2716 specification. It can’t be guaranteed that it suppresses switching due to external noise. Table 21 Standard_Pads Class_S (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Data Sheet 5-23 V1.2, 2014-06

5.2.2 Analog to Digital Converters (ADCx)

ADC parameter in Table 22 are valid for VDD = 1.235 V to 1.365 V; VDDM = 4.75 V to 5.25 V; TJ =1 5 0 ° C . Table 22 5V ADC Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Switched capacitance at the analog voltage inputs CAINSW CC − 92 0 p F Total capacitance of an analog input CAINTOT CC − 20 30 pF Switched capacitance at the positive reference voltage input2)3) CAREFSW CC − 15 30 pF Total capacitance of the voltage reference inputs2) CAREFTOT CC − 20 40 pF Differential Non-Linearity Error4)5)6)7) EADNL CC -3 − 3 LSB ADC resolution= 12- bit 8) 9) Gain Error4)5)6)7) EAGAIN CC -3.5 − 3.5 LSB ADC resolution= 12- bit 8) 9) Integral Non- Linearity 4)5)6)7) EAINL CC -3 − 3 LSB ADC resolution= 12- bit8) 9) Offset Error4)5)6)7) EAOFF CC -4 − 4 LSB ADC resolution= 12- bit 8) 9)

Data Sheet 5-24 V1.2, 2014-06 Converter clock fADC SR 4− 110 MHz SAK-TC1724F- 192F133HL; SAK-TC1724F- 192F133HR; SAK-TC1724N- 192F133HR 4− 80 MHz SAK-TC1724N- 192F80HL; SAK-TC1724N- 192F80HR Internal ADC clock fADCI CC 1 − 20 MHz 10) Charge consumption per conversion QCONV CC 70 85 11) 100 pC charge needs to be provided via VAREF0 Table 22 5V ADC Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Data Sheet 5-25 V1.2, 2014-06 Input leakage at analog inputs12) IOZ1 CC -100 − 500 nA Vi≥ 0.97 x VDDM V; Vi≤ VDDM V; overlayed= No -100 − 600 nA Vi≥ 0.97 x VDDM V; Vi≤ VDDM V; overlayed= Yes -500 − 100 nA Vi≥ 0V ; Vi≤ 0.03 x VDDM V; overlayed= No -600 − 100 nA Vi≤ 0.03 x VDDM V; Vi≥ 0V ; overlayed= Yes -100 − 200 nA Vi> 0.03 x VDDM V; Vi< 0.97 x VDDM V; overlayed= No -100 − 300 nA Vi> 0.03 x VDDM V; Vi< 0.97 x VDDM V; overlayed= Yes Input leakage current at Varef0 IOZ2 CC -2 − 2 μA VAREF0≥ 0V; VAREF0≤ VDDM V Input leakage current at Vagnd0 IOZ3 CC -2 − 2 μA VAGND0≥ 0V; VAGND0≤ VDDM V ON resistance of the transmission gates in the analog voltage path RAIN CC − 900 1500 Ohm Table 22 5V ADC Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Data Sheet 5-26 V1.2, 2014-06 ON resistance for the ADC test (pull down for AIN7) RAIN7T CC 180 550 900 Ohm Test feature available only for odd AINx pins Resistance of the reference voltage input path RAREF CC − 500 1000 Ohm 500 Ohm increased if AIN[1:0] used as reference input Broken wire detection delay against VAGND tBWG CC −− 50 13) Broken wire detection delay against VAREF tBWR CC −− 50 14) Sample time tS CC 2 − 257 TADCI Calibration time after bit ADC_GLOBCFG.SUCAL is set tCAL CC −− 4352 cycles Total Unadjusted Error5)6)15) TUE CC -4 − 416) LSB ADC resolution= 12- bit Wakeup time from analog powerdown, fast mode tAWAF CC −− 5 μs Wakeup time from analog powerdown, slow mode tAWAS CC −− 10 μs Analog reference ground2) VAGND0 SR VSSM - 0.05 − VAREF0 VDDM/2 V Analog input voltage VAIN SR VAGND0 − VAREF0 V Analog reference voltage2) VAREF0 SR VAGND0 VDDM/2 − VDDM + 0.0517) 18) V Analog reference voltage range5)6)2) VAREF0 - VAGND0 SR VDDM/2 − VDDM + 0.05 V Table 22 5V ADC Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Data Sheet 5-27 V1.2, 2014-06 1) The sampling capacity of the conv ersion C-network is pre-charged to VAREF/2 before the sampling moment. Because of the parasitic elements the voltage measured at AINx can deviate from VAREF/2. 2) Applies to AINx, when used as auxiliary reference input. 3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead smaller capacitances are successively switched to the reference voltage. 4) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error. 5) If the analog reference voltage range is below VDDM but still in the defined range of VDDM / 2 and VDDM is used, then the ADC converter errors increase. If the refe rence voltage is reduced by the factor k (k<1), TUE,DNL,INL,Gain, and Offset errors increase also by the factor 1/k. 6) If a reduced analog reference voltage between 1V and VDDM / 2 is used, then there are additonal decrease in the ADC speed and accuracy. 7) If the analog reference voltage is > VDDM, then the ADC converter errors increase. 8) For 10-bit conversions the error value must be multiplied with a factor 0.25. 9) For 8-bit conversions the error value must be multiplied with a factor 0.0625. 10) If the alternate reference is used or fADCI is more than 16 MHz, the accuracy of the ADC may decrease. 11) For a conversion time of 1 µs a rms value of 85µA result for IAREF0. 12) The leakage current definition is a continous function, as shown in figure ADCx Analoge Input Leakage. The numerical values defined determine the characteristic points of the given countinuous linear approximation - they do not define step function. 13) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 250μs. Results below 10% (199H). 14) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 10 μs. This function is influenced by leakage current, in particular at high temperature.Results above 60% (999H). 15) Measured without noise. 16) For 10-bit conversion the TUE is ±2LSB; for 8-bit conversion the TUE is ±1LSB 17) A running conversion may become inexact in case of violating the normal conditions (voltage overshoot). 18) If the reference voltage VAREF increase or the VDDM decrease, so that VAREF = (VDDM + 0.05V to VDDM + 0.07V), then the accuracy of the ADC decrease by 4LSB12.

Data Sheet 5-28 V1.2, 2014-06 ADC parameter in Table 23 are valid for VDD = 1.235 V to 1.365 V; VDDM = 3.135 V to 3.465 V; TJ = 150°C. Table 23 3.3V ADC Parameters Parameter Symbo l Values Unit Note / Test ConditionMin. Typ. Max. Switched capacitance at the analog voltage inputs CAINSW CC − 92 0 p F Total capacitance of an analog input CAINTOT CC − 20 30 pF Switched capacitance at the positive reference voltage input2)3) CAREFS W CC − 15 30 pF Total capacitance of the voltage reference inputs2) CAREFTO T CC − 20 40 pF Differential Non-Linearity Error4)5)6)7) EADNL CC -4 − 4 LSB ADC resolution= 12- bit 8) 9) Gain Error4)5)6)7) EAGAIN CC -3.5 − 3.5 LSB ADC resolution= 12- bit 8) 9) Integral Non- Linearity 4)5)6)7) EAINL CC -4 − 4 LSB ADC resolution= 12- bit8) 9) Offset Error4)5)6)7) EAOFF CC -4 − 4 LSB ADC resolution= 12- bit 8) 9) Converter clock fADC SR 4− 110 MHz SAK-TC1724F- 192F133HL; SAK-TC1724F- 192F133HR; SAK-TC1724N- 192F133HR 4− 80 MHz SAK-TC1724N- 192F80HL; SAK-TC1724N- 192F80HR

Data Sheet 5-29 V1.2, 2014-06 Internal ADC clock fADCI CC 1 − 20 MHz 10) Charge consumption per conversion11) QCONV CC −− 70 pC charge needs to be provided via VAREF0 Input leakage at analog inputs12) IOZ1 C C -100 − 500 nA Vi≥ 0.97 x VDDM V; Vi≤ VDDM V; overlayed= No -100 − 600 nA Vi≥ 0.97 x VDDM V; Vi≤ VDDM V; overlayed= Yes -500 − 100 nA Vi≥ 0V ; Vi≤ 0.03 x VDDM V; overlayed= No -600 − 100 nA Vi≤ 0.03 x VDDM V; Vi≥ 0V ; overlayed= Yes -100 − 200 nA Vi>0 . 0 3 x VDDM V; Vi<0 . 9 7 x VDDM V; overlayed= No -100 − 300 nA Vi>0 . 0 3 x VDDM V; Vi<0 . 9 7 x VDDM V; overlayed= Yes Input leakage current at Varef IOZ2 CC -2 − 2 μA VAREF0≤ VDDM V Input leakage current at Vagnd IOZ3 CC -2 − 2 μA VAGND0≤ VDDM V Table 23 3.3V ADC Parameters (cont’d) Parameter Symbo l Values Unit Note / Test ConditionMin. Typ. Max.

Data Sheet 5-30 V1.2, 2014-06 ON resistance of the transmission gates in the analog voltage path RAIN C C − 3500 9000 Ohm ON resistance for the ADC test (pull down for AIN7) RAIN7T CC 180 800 1800 Ohm Test feature available only for odd AINx pins Resistance of the reference voltage input path RAREF CC − 1700 3000 Ohm 500 Ohm increased if AIN[1:0] used as reference input Broken wire detection delay against VAGND tBWG CC −− 50 13) Broken wire detection delay against VAREF tBWR CC −− 50 14) Sample time tS CC 2 − 257 TADCI Calibration time after bit ADC_GLOBCFG.SUCAL is set tCAL CC −− 4352 cycles Total Unadjusted Error5)6)15) TUE CC -4.5 − 4.516) LSB ADC resolution= 12- bit Analog reference ground2) VAGND0 SR VSSM - 0.05 − VAREF0 VDDM/2 V Analog input voltage VAIN SR VAGND0 − VAREF0 V Analog reference voltage2) VAREF0 SR VAGND0 VDDM/2 − VDDM + 0.0517) 18) V Analog reference voltage range5)6)2) VAREF0 - VAGND0 SR VDDM/2 − VDDM + 0.05 V 1) The sampling capacity of the conversion C-network is pre-charged to VAREF/2 before the sampling moment. Because of the parasitic elements the voltage measured at AINx can deviate from VAREF/2. Table 23 3.3V ADC Parameters (cont’d) Parameter Symbo l Values Unit Note / Test ConditionMin. Typ. Max.

Data Sheet 5-31 V1.2, 2014-06 2) Applies to AINx, when used as auxiliary reference input. 3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead smaller capacitances are successively switched to the reference voltage. 4) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error. 5) If the analog reference voltage range is below VDDM but still in the defined range of VDDM / 2 and VDDM is used, then the ADC converter errors increase. If the refe rence voltage is reduced by the factor k (k<1), TUE,DNL,INL,Gain, and Offset errors increase also by the factor 1/k. 6) If a reduced analog reference voltage between 1V and VDDM / 2 is used, then there are additonal decrease in the ADC speed and accuracy. 7) If the analog reference voltage is > VDDM, then the ADC converter errors increase. 8) For 10-bit conversions the error value must be multiplied with a factor 0.25. 9) For 8-bit conversions the error value must be multiplied with a factor 0.0625. 10) If the alternate reference is used, or fADCI is more than 16 MHz, or STC is lower than 8, the accuracy of the ADC may decrease. 11) QCONV is calculated as QCONV = CAREF*VAREF. The Qconv can be calculated according to this formula. 12) The leakage current definition is a continous functi on,as shown in figure ADCx Analoge Input Leakage. The numerical values defined determine th e characteristic points of the gi ven countinuous linear approximation - they do not define step function. 13) The broken wire detection delay against VAGND is measured in numbers of cons ecutive precharge cycles at a conversion rate of not more than 250μs. Results below 10% (199H). 14) The broken wire detection delay against VAREF is measured in numbers of cons ecutive precharge cycles at a conversion rate of not more than 10 μs. This function is influenced by leakage current, in particular at high temperature.Results above 60% (999H). 15) Measured without noise. 16) For 10-bit conversion the TUE is ±2LSB; for 8-bit conversion the TUE is ±1LSB 17) A running conversion may become inexact in case of violating the normal conditions (voltage overshoot). 18) If the reference voltage VAREF increase or the VDDM decrease, so that VAREF = (VDDM + 0.05V to VDDM + 0.07V), then the accuracy of the ADC decrease by 4LSB12. Table 24 Conversion Time (Operating Conditions apply) Parameter Symbol Values Unit Note Conversion time with post-calibration tC CC 2 × TADC +( 4+S T C+n ) × TADCI μs n = 8, 10, 12 for n - bit conversion TADC =1/ fFPI TADCI =1/ fADCIConversion time without post-calibration 2 × TADC +( 2+S T C+n ) × TADCI

Data Sheet 5-32 V1.2, 2014-06 Figure 7 ADCx Input Circuits Reference Voltage Input Circuitry Analog Input Circuitry Analog_InpRefDiag REXT =VAIN CEXT RAIN, On CAINTOT - CAINSW CAINSW ANx VAREF RAREF, On CAREFTOT - CAREFSW CAREFSW VAGNDx VAREFx RAIN7TVAGNDx

Data Sheet 5-33 V1.2, 2014-06 Figure 8 ADCx Analog Inputs Leakage VIN[VDDM%]200nA 500nA 3% 100%97% Ioz1 100nA -500nA -100nA VIN[VDDM%]300nA 600nA 3% 100%97% Ioz1 100nA -600nA -100nA Single ADC Input Overlayed ADC/FADC Input

Data Sheet 5-34 V1.2, 2014-06

5.2.3 Fast Analog to Digital Converter (FADC)

FADC parameter are valid for VDDM = 4.75 V to 5.25 V;TJ = 150°C. Table 25 FADC Parameters with VDDM = 5V Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. DNL error EFDNL CC -1 − 1L S B VIN mode= differential Gain = 1, 2 -1 − 1L S B VIN mode= single ended Gain = 1, 2 -2 − 2L S B VIN mode= differential Gain = 4, 8 TJ = 150°C 1) -2.5 − 2.5 LSB VIN mode= differential Gain = 4, 8 TJ = 160°C 1) -2 − 2L S B VIN mode= single ended Gain = 4, 8 TJ = 150°C 1) -2.5 − 2.5 LSB VIN mode= single ended Gain = 4, 8 TJ = 160°C 1)

Data Sheet 5-35 V1.2, 2014-06 GRADient error EFGRAD CC -5 − 5% VIN mode= differential ; Gain< 4 -5 − 5% VIN mode= single ended ; Gain< 4 -5.5 − 5% VIN mode= differential ; Gain= 4 -5.5 − 5% VIN mode= single ended ; Gain= 4 -6 − 6% VIN mode= differential ; Gain= 8 -6 − 6% VIN mode= single ended ; Gain= 8 INL error EFINL CC -4 − 4L S B VIN mode= differential -4 − 4L S B VIN mode= single ended Table 25 FADC Parameters with VDDM = 5V (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Data Sheet 5-36 V1.2, 2014-06 Offset error EFOFF CC -90 − 90 mV VIN mode= differential ; Calibration= No -90 − 90 mV VIN mode= single ended ; Calibration= No -20 − 20 mV VIN mode= differential ; Calibration= Yes 2)3) -20 − 20 mV VIN mode= single ended ; Calibration= Yes 2)3) Error of common mode voltage VFAREFI/2 EFREFI CC -80 − 80 mV Channel amplifier cutoff frequency fCOFF CC 2 −− MHz Converter clock fFADC SR 4− 110 MHz SAK-TC1724F- 192F133HL; SAK-TC1724F- 192F133HR; SAK-TC1724N- 192F133HR 4− 80 MHz SAK-TC1724N- 192F80HL; SAK-TC1724N- 192F80HR Conversion time tC CC −− 21 1 / fFADC For 10-bit conversion Input resistance of the analog voltage path (Rn, Rp) RFAIN CC 100 − 200 kOh m Table 25 FADC Parameters with VDDM = 5V (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Data Sheet 5-37 V1.2, 2014-06 The calibration procedure should run after each power-up, when all power supply voltages and the reference voltage have stabilized. Settling time of a channel amplifier after changing ENN or ENP tSET CC −− 5 μs Analog input voltage range4) VAINF SR VSSM − VDDP V Wakeup time from analog powerdown, fast mode tFWAF CC −− 5 μs Wakeup time from analog powerdown, slow mode tFWAS CC −− 10 μs Analog reference ground VFAGNDI CC −0− V Internally generated Analog reference voltage VFAREFI CC −3 . 3 − 5)6) V Internally generated 1) No missing codes. 2) Calibration should be preformed at each power-up. In case of a continous operation, it should be performed minimium once per week. 3) The offser error voltage drifts over the whole temperature range maximum +-3LSB. 4) The accuracy values is valid between 5% and 90%of VAINF 5) Voltage overshoot to 4V is permissible, provided the pulse duration is less than 100 μs and the cumulated sum of the pulses does not exceed 1 h. 6) A running conversion may become inexact in case of violating the nomal operating conditions (voltage overshoots). Table 25 FADC Parameters with VDDM = 5V (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Data Sheet 5-38 V1.2, 2014-06 Figure 9 FADC Input Circuits FADC_InpRefDiag RN FAINxN FAINxP VSSM FADC Analog Input Stage RP VFAREF/2 VFAREF (from IVR) FADC Reference Voltage Input Circuitry VFAGND VFAREF IFAREF

Data Sheet 5-39 V1.2, 2014-06

5.2.4 Oscillator Pins

Note: It is strongly recomm ended to measure the oscill ation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits specified by the crystal or ceramic resonator supplier. Table 26 OSC_XTAL Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Input current at XTAL1 IIX1 CC -25 − 25 μA VIN>0V ; VIN<VDDP Input frequency fOSC SR 4 − 40 MHz Direct Input Mode selected 8 − 25 MHz External Crystal Mode selected Oscillator start-up time1) 1) tOSCS is defined from the moment when VDDP = 3.13V until the oscillations reach an amplitude at XTAL1 of 0.3 * VDDP. The external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended and specified by crystral suppliers. tOSCS CC −− 10 ms Input high voltage at XTAL12) 2) If the XTAL1 pin is driven by a crystal, re aching a minimum amplitude (peak-to-peak) of 0.3 * VDDP is necessary. VIHX SR 0.7 x VDDP − VDDP + 0.5 V Input low voltage at XTAL1 VILX SR -0.5 − 0.3 x VDDP V Input hysteresis for XTAL1 pad3) 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be guaranteed that it suppresses switching due to external system noise. HYSAX CC −− 200 mV

Data Sheet 5-40 V1.2, 2014-06

5.2.5 Power Supply Current

The total power supply current defined below consists of leakage and switching component. Application relevant values are typically lower than those given in the following two tables and depend on the customer's system operatin g conditions (e.g. thermal connection or used application configurations). The operating conditions for the parameters in the following table are: VDD=1.365 V, VDDP=3.47 V, VDDM=5.1 V, fLMB=133 / 80 MHz, TJ=160 °C The realisic power pattern defines the following conditions:

• TJ=150 °C
• fLMB = fPCP = fCPU =1 3 3/8 0M H z
• fFPI = 66.5 / 80 MHz
• VDD =1 . 3 2 6V
• VDDP =3 . 3 6 6V
• VDDM =5 . 1V The max power pattern defines the following conditions: TJ=160 °C
• fLMB = fPCP = fCPU =1 3 3/8 0M H z
• fFPI = 66.5 / 80MHz
• VDD =1 . 3 7V
• VDDP =3 . 4 7V
• VDDM =5 . 2 5V

Data Sheet 5-41 V1.2, 2014-06 Table 27 Power Supply Parameters Parameter Symbol Values Unit Note / Test Condition Min Typ. Max. Core active mode supply current1) IDD CC −− 310 mA power pattern= max ; SAK-TC1724F-192F133HL SAK-TC1724F-192F133HR SAK-TC1724N-192F133HR −− 212 mA power pattern= realistic ; SAK-TC1724F-192F133HL SAK-TC1724F-192F133HR SAK-TC1724N-192F133HR 248 mA power pattern= max ; SAK-TC1724N-192F80HL SAK-TC1724N-192F80HR 160 mA power pattern= realistic ; SAK-TC1724N-192F80HL SAK-TC1724N-192F80HR IDD current at PORST Low IDD_PORST CC −− 110 mA PORST pad output current IDDPORST CC 13 −− mA Sum of all 1.3 V supply currents IDDSUM CC −− 212 mA power pattern= realistic; SAK-TC1724F-192F133HL SAK-TC1724F-192F133HR SAK-TC1724N-192F133HR −− 160 mA power pattern= realistic ; SAK-TC1724N-192F80HL SAK-TC1724N-192F80HR SAK-TC1724F-192F80HR IDDP current at PORST Low IDDP_PORS T CC −− 6m A

Data Sheet 5-42 V1.2, 2014-06 IDDP current no pad activity2) IDDP CC −− IDDP_ PORST + 83 mA including flash read current −− IDDP_ PORST + 62 mA including flash programming current 3) −− IDDP_ PORST 914) mA including flash erase verify current 3) ADC 5V power supply current IDDM CC −− 32 mA EVR Supply current IV5 CC −− 375 mA power pattern= max; mode = 5V only with ext. pass device; SAK-TC1724F-192F133HL SAK-TC1724F-192F133HR −− 370 mA power pattern= max; mode = 5V only with ext. pass device SAK-TC1724N-192F133HR −− 280 mA power pattern= real; mode = 5V only with ext. pass device; SAK-TC1724F-192F133HL SAK-TC1724F-192F133HR −− 275 mA power pattern= real; mode = 5V only with ext. pass device; SAK-TC1724N-192F133HL SAK-TC1724N-192F133HR Table 27 Power Supply Parameters (cont’d) Parameter Symbol Values Unit Note / Test Condition Min Typ. Max.

Data Sheet 5-43 V1.2, 2014-06 EVR Supply current IV5 CC −− 310 mA power pattern= max; mode = 5V only without ext. pass device; SAK-TC1724N-192F80HL SAK-TC1724N-192F80HR −− 235 mA power pattern= real; mode = 5V only without ext. pass device; SAK-TC1724N-192F80HL SAK-TC1724N-192F80HR Maximum power dissipation PD CC −− 902 mW power pattern= max; mode = all external; SAK-TC1724F-192F133HL SAK-TC1724F-192F133HR SAK-TC1724N-192F133HR −− 744 mW power pattern= realistic mode = all external; SAK-TC1724F-192F133HL SAK-TC1724F-192F133HR SAK-TC1724N-192F133HR Table 27 Power Supply Parameters (cont’d) Parameter Symbol Values Unit Note / Test Condition Min Typ. Max.

Data Sheet 5-44 V1.2, 2014-06 Maximum power dissipation PD CC −− 1970 mW power pattern= max; mode = 5V only with ext. pass device; SAK-TC1724F-192F133HL SAK-TC1724F-192F133HR −− 1950 mW power pattern= max; mode = 5V only with ext. pass device; SAK-TC1724N-192F133HR −− 1428 mW power pattern= realistic mode = 5V only with ext. pass device; SAK-TC1724F-192F133HL SAK-TC1724F-192F133HR −− 1403 mW power pattern= realistic mode = 5V only with ext. pass device; SAK-TC1724N-192F133HR Maximum power dissipation PD CC −− 810 mW power pattern= max; mode = all external; SAK-TC1724N-192F80HL SAK-TC1724N-192F80HR −− 669 mW power pattern= realistic; mode = all external; SAK-TC1724N-192F80HL SAK-TC1724N-192F80HR Table 27 Power Supply Parameters (cont’d) Parameter Symbol Values Unit Note / Test Condition Min Typ. Max.

Data Sheet 5-45 V1.2, 2014-06 5.2.5.1 Calculating the 1.3 V Current Consumption The current consumption of the 1.3 V rail compose out of two parts:

• Static current consumption
• Dynamic current consumption The static current consumption is related to the device temperature TJ and the dynamic current consumption depends of the configured clocking frequencies and the software application executed. These two parts needs to be added in order to get the rail current consumption. (1) (2) Maximum power dissipation PD CC −− 1628 mW power pattern= max; mode = 5V only without ext. pass device; SAK-TC1724N-192F80HL SAK-TC1724N-192F80HR −− 1200 mW power pattern= realistic mode = 5V only without ext. pass device; SAK-TC1724N-192F80HL SAK-TC1724N-192F80HR 1) Infineon Power Loop: CPU and PCP running, all peripherals active. The power consumption of each customer application will most probably be lower than this value, but must be evaluated separately. 2) For operations including the D-Flash the required cu rrent is always lower than the current for non-DFlash operations. 3) Relevant for the power supply dimensi oning, not for thermal considerations. 4) In case of erase of Program Flash PF, internal flash array loading effects may generate transient current spikes of up to 15 mA for maximum 5 ms per flash module. Table 27 Power Supply Parameters (cont’d) Parameter Symbol Values Unit Note / Test Condition Min Typ. Max. I0 06 7 4mA I0 39 mA

Data Sheet 5-46 V1.2, 2014-06 Function 1 defines the typical static curren t consumption and Function 2 defines the maximum static current consumption. Both functions are valid for VDD =1 . 3 2 6V . For the dynamic current consumption using the application pattern and fLMB = fPCP =2* fFPI the function 4 applies: (3) For the dynamic current consumption using the application pattern and fLMB = fPCP = fFPI the function 5 applies: (4) and this finally results in (5) IDym 07 6 mA IDym 09 mA IDD I0 IDYM+=

Data Sheet 5-47 V1.2, 2014-06

5.3 AC Parameters

All AC parameters are defined with maximum driver strength unless otherwise stated.

5.3.1 Testing Waveforms

Figure 10 Rise/Fall Time Parameters Figure 11 Testing Waveform, Output Delay Figure 12 Testing Waveform, Output High Impedance 10% 90% 10% 90% VSS VDDP tR rise_fall tF mct 04881_a.vsd VDDE / 2 Test Points VDDE / 2 VSS VDDP MCT04880_new VLoad + 0.1 V VOH - 0.1 VTiming Reference PointsVLoad - 0.1 V VOL - 0.1 V

Data Sheet 5-48 V1.2, 2014-06

5.3.2 Power Sequencing 5V Supply Only

Figure 13 5 V / 3.3 V / 1.3 V Power-Up/Down Sequence The events for the above points in the power-up/down sequence

• A :external supplied voltage reaches operating level
• B: external supplied and internal generated voltages reaches operating levels
• C: internal generated voltage drops below operating level
• D: internal generated voltage resumes operating level
• E: external supplied voltage leaves operating level P0.4 and P0.5 should be kept at the selected se tting of '0' or '1' until external supplied voltage has reached its operating level. The following list of rules applies to the power-up/down sequence:
• All ground pins V SS must be externally connected to one single star point in the system. Regarding the DC current component, all ground pins are internally directly connected.
• The latch-up risk is minimized if the I/O currents are limited to: – 20 mA for one pin group – AND 100 mA for the completed device I/Os Power-Up_EVR_1.vsd 1.3V t V t 4.0V 5.5V PORST (input) PORST (output) A B C DE 3.3V 3.63V 2.97 1.43V 1.17V

Data Sheet 5-49 V1.2, 2014-06 – AND additionally before power-up / after power-down: 1 mA for one pin in inactive mode (0 V on all power supplies)

• The PORST signal may be deactivated after all VDD5, and VAREF0 power-supplies and the oscillator have reached stable op eration, within the normal operating conditions.
• At normal power down the PORST signal should be activated within the normal operating range, and then the power supp lies may be switched off. Care must be taken that all Flash write or delete sequences have been completed.
• In case of a power-loss at any power-supply, all power supplies must be powered- down, conforming at the same time to the rule number 2.
• Although not necessary, it is additionally recommended that all power supplies are powered-up/down together in a controlled way, as tight to each other as possible.
• Additionally, regarding the ADC reference voltage VAREF0: – VAREF0 must power-up at the same time or later then VDDM, and – VAREF0 must power-down either earlier or at latest to satisfy the condition VAREF0 < VDDM + 0.5 V. This is required in order to prevent discharge of VAREF0 filter capacitance through th e ESD diodes through the VDDM power supply. In case of discharging the reference capacitance through the ESD diodes, the current must be lower than 5 mA.

Data Sheet 5-50 V1.2, 2014-06 5.3.3 Power Sequencing 3.3V Supply Only Figure 14 3.3 V / 1.3 V Power-Up/Down Sequence The events for the above points in the power-up/down sequence

• A :external supplied voltage reaches operating level
• B: external supplied and internal generated voltages reaches operating levels
• C: internal generated voltage drops below operating level
• D: internal generated voltage resumes operating level
• E: external supplied voltage leaves operating level P0.4 and P0.5 should be kept at the selected se tting of '0' or '1' until external supplied voltage has reached its operating level. The following list of rules applies to the power-up/down sequence:
• All ground pins V SS must be externally connected to one single star point in the system. Regarding the DC current component, all ground pins are internally directly connected.
• The latch-up risk is minimized if the I/O currents are limited to: – 20 mA for one pin group – AND 100 mA for the completed device I/Os Power-Up_EVR_2.vsd 1.3V 3.3V t V t 2.97V 3.63V PORST (input) PORST (output) A B C DE 1.43V 1.17V

Data Sheet 5-51 V1.2, 2014-06 – AND additionally before power-up / after power-down: 1 mA for one pin in inactive mode (0 V on all power supplies)

• The PORST signal may be deactivated after all VDD3.3, and VAREF0 power- supplies and the oscillator have reac hed stable operation, within the normal operating conditions.
• At normal power down the PORST signal should be activated within the normal operating range, and then the power supp lies may be switched off. Care must be taken that all Flash write or delete sequences have been completed.
• In case of a power-loss at any power-supply, all power supplies must be powered- down, conforming at the same time to the rule number 2.
• Although not necessary, it is additionally recommended that all power supplies are powered-up/down together in a controlled way, as tight to each other as possible.
• Additionally, regarding the ADC reference voltage VAREF0: – VAREF0 must power-up at the same time or later then VDDM, and – VAREF0 must power-down either earlier or at latest to satisfy the condition VAREF0 < VDDM + 0.5 V. This is required in order to prevent discharge of VAREF0 filter capacitance through th e ESD diodes through the VDDM power supply. In case of discharging the reference capacitance through the ESD diodes, the current must be lower than 5 mA.

Data Sheet 5-52 V1.2, 2014-06

5.3.4 Power Sequencing all Voltages supplied from External

Figure 15 5 V / 3.3 V / 1.3 V Power-Up/Down Sequence P0.4 and P0.5 should be kept at the selected setting until external supplied voltage has reached its operating level. The following list of rules applies to the power-up/down sequence:

• All ground pins V SS must be externally connected to one single star point in the system. Regarding the DC current component, all ground pins are internally directly connected.
• At any moment in time to avoid increased latch-up risk, each power supply must be higher then any lower_power_supply - 0.5 V, or: VDD5 > VDDP - 0.5 V; VDD5 > VDD - 0.5 V;VDDP > VDD - 0.5 V, see Figure 15. – The latch-up risk is minimized if the I/O currents are limited to: – 20 mA for one pin group – AND 100 mA for the completed device I/Os – AND additionally before power-up / after power-down: 1 mA for one pin in inactive mode (0 V on all power supplies) Power-Up 10.v 1.3V 3.3V V PORST 0.5V0.5V 0.5V VDDP VAREF power down power fail 3.63V 2.97V 1.17V 1.43V 4.5V 5.5V

Data Sheet 5-53 V1.2, 2014-06

• During power-up and power-down, the volt age difference between the power supply pins of the same voltage (3.3 V, 1.3 V, and 5 V) with different names, that are internally connected via diodes, must be lower than 100 mV. On the other hand, all power supply pins with the same name (for example all VDDP), are internally directly connected. It is recommended that the power pins of the same voltage are driven by a single power supply.
• The PORST signal may be deactivated after all VDD5, VDDP, VDD, and VAREF0 power-supplies and the oscillator have reached stable operation, within the normal operating conditions.
• At normal power down the PORST signal should be activated within the normal operating range, and then the power supp lies may be switched off. Care must be taken that all Flash write or delete sequences have been completed.
• At power fail the PORST signal must be ac tivated at latest when any 3.3 V or 1.3 V power supply voltage falls 10% below the no minal level. If, under these conditions, the PORST is activated during a Flash write, only the memory row that was the target of the write at the moment of the power loss will contain unreliable content. In order to ensure clean power-down behavior, t he PORST signal should be activated as close as possible to the normal operating voltage range.
• In case of a power-loss at any power-supply, all power supplies must be powered- down, conforming at the same time to the rules number 2 and 4.
• Although not necessary, it is additionally recommended that all power supplies are powered-up/down together in a controlled way, as tight to each other as possible.
• Additionally, regarding the ADC reference voltage VAREF0: – VAREF0 must power-up at the same time or later then VDDM, and – VAREF0 must power-down either earlier or at latest to satisfy the condition VAREF0 < VDDM + 0.5 V. This is required in order to prevent discharge of VAREF0 filter capacitance through th e ESD diodes through the VDDM power supply. In case of discharging the reference capacitance through the ESD diodes, the current must be lower than 5 mA.

Data Sheet 5-54 V1.2, 2014-06

5.3.5 Power, Pad and Reset Timing

Table 28 Reset Timings Parameters Parameter Symbo l Values Uni t Note / Test Condition Min. Typ. Max. Application Reset Boot Time1)2) tB CC 150 − 810 μs SAK-TC1724F-192F133HL SAK-TC1724F-192F133HR SAK-TC1724N-192F133HR 150 − 1140 μs SAK-TC1724N-192F80HL SAK-TC1724N-192F80HR Power on Reset Boot Time3)4) tBP CC −− 2.5 ms EVR Startup time from Supply ramp-up till PORST release tEVR CC − 860 1100 μs HWCFG pins hold time from ESR0 rising edge tHDH SR 16 / fFPI −− ns HWCFG pins setup time to ESR0 rising edge tHDS CC 0 −− ns Ports inactive after ESR0 reset active tPI CC −− 8/fFPI ns Ports inactive after PORST reset active5) tPIP CC −− 150 ns Minimum PORST active time after power supplies are stable at operating levels tPOA CC 4.5 −− ms 6)

Data Sheet 5-55 V1.2, 2014-06 TESTMODE /T R ST hold time from PORST rising edge tPOH SR 100 −− ns PORST rise time tPOR SR −− 50 ms TESTMODE /T R ST setup time to PORST rising edge tPOS SR 0 −− ns Application Reset inactive after PORST deassertion tPOR_APP SR −− 40 7) μs 1) The duration of the boot time is defined between the rising edge of the internal application reset and the clock cycle when the first user instruction has entered the CPU pipeline and its processing starts. 2) The given time includes the time of the inte rnal reset extension for a configured value of SCU_RSTCNTCON.RELSA = 0x05BE. 3) The duration of the boot time is defined between the rising edge of the PORST and the clock cycle when the first user instruction has entered the CPU pipeline and its processing starts. 4) The given time includes the internal reset extension time for the System and Application Reset which is visible through ESR0. 5) This parameter includes the delay of the analog spike filter in the PORST pad. 6) This parameter represents the additional time required to ensure that external crystal is stable and operational at PORST. 7) Application Reset is assumed not to be extended from external, otherwise the time extends by the time the Application Reset is extended. Table 28 Reset Timings Parameters (cont’d) Parameter Symbo l Values Uni t Note / Test Condition Min. Typ. Max.

Data Sheet 5-56 V1.2, 2014-06 Figure 16 Power, Pad and Reset Timing As programmed Pads Pad‐state undefined VDD VDDPPA VDDPPA thd t POA TRST ESR0 PORST tPOH HWCFG tHDH t PIP tPI Tri‐state or pull device active thd tPOH tHDH t PIP tPIt PIP tPI tPI tHDH tPI VDD ‐12%tBP VDDP tEVR ‐10%

Data Sheet 5-57 V1.2, 2014-06

5.3.6 EVR Parameter

Table 29 Pass device detector Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Pull-up current at VDPG IPU_VDPG SR 0.7 − 2.0 mA VDD5≥ 4.5V; VDD5≤ 5.5V Input low voltage VIL SR 0 − 1.5 V Table 30 EVR Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Output Capacitance on VDDP COUT33 CC − 6.8 − µF ILOAD > 310 mA; ESR < 50mΩ; with external pass device, additional decoupling capacitor on each supply pin, SAK-TC1724F-192F133HL SAK-TC1724F-192F133HR SAK-TC1724N-192F133HR − 2.2 − µF ILOAD ≤ 310 mA; ESR < 50mΩ; with internal pass device, additional decoupling capacitor on each supply pin, SAK-TC1724N-192F80HL SAK-TC1724N-192F80HR

Data Sheet 5-58 V1.2, 2014-06 Output Capacitance on VDD COUT13 CC − 6.8 − µF ILOAD < 250 mA; ESR < 50mΩ; additional decoupling capacitor on each supply pin, SAK-TC1724F-192F133HL SAK-TC1724F-192F133HR SAK-TC1724N-192F133HR − 4.7 − µF ILOAD < 250 mA; ESR < 50mΩ; additional decoupling capacitor on each supply pin, SAK-TC1724N-192F80HL SAK-TC1724N-192F80HR Input Capacitance on CIN5 CC − 6.8 − µF depending on ext. regulator SAK-TC1724F-192F133HL SAK-TC1724F-192F133HR SAK-TC1724N-192F133HR − 4.7 − µF depending on ext. regulator SAK-TC1724N-192F80HL SAK-TC1724N-192F80HR Undervoltage Reset threshold for external supply VRST5 CC −− 2.97 V 3.3V single supply −− 4.5 V 5.0 single supply Output accuracy of EVR33 after trimming VOUT33 CC 1 mA≤ IOUT ≤310mA Dynamic Load Regulation of EVR33 ∆VLOREG 33 CC 225 − +225 mV dI / dt = 150mA /10 ns Dynamic Line Regulation of EVR33 ∆VLIREG 33 CC -25 − +25 mV dV5 / dt = 1V / ms 1 … 310mA, 4.5V … 5.5V Table 30 EVR Parameters (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max.

Data Sheet 5-59 V1.2, 2014-06 Undervoltage Reset threshold for EVR33 VRST33 CC −− 2.97 V Current drawn from EVR33 for external devices with internal pass devices. EXI33 SR −− 30 mA No inductive loads allowed. Decoupling capacitor > 330 nF Output accuracy of EVR13 after trimming VOUT13 CC -30 − +30 mV 2.97V ≤ VIN ≤ 3.63V; 1 mA≤ IOUT ≤250mA Dynamic Load Regulation of EVR13 ∆VLOREG 13 CC 100 − +100 mV 5.0V/3.3V single supply, dI / dt = 150mA /10 ns Dynamic Line Regulation of EVR13 VLIREG 13 CC -10 − +10 mV 5.0V/3.3V single supply, dV5 / dt=1V / ms 1 … 250mA, 2.97V … 3.63V Undervoltage Reset threshold for EVR13 VRST13 CC −− 1.17 V Current drawn from EVR13 for external devices EXI13 SR −− 10 mA No inductive loads allowed. Decoupling capacitor > 100 nF Supply ramp-up SR SR −− 50 V/ms Table 30 EVR Parameters (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max.

Data Sheet 5-60 V1.2, 2014-06

5.3.7 Phase Locked Loop (PLL)

Phase Locked Loop Operation When PLL operation is enabled and configured, the PLL clock fVCO (and with it the LMB- Bus clock fLMB) is constantly adjusted to the sele cted frequency. The PLL is constantly adjusting its output frequency to correspond to the input frequency (from crystal or clock source), resulting in an accumulated jitter t hat is limited. This means that the relative deviation for periods of more than one clock cycle is lower than for a single clock cycle. This is especially important for bus cycles using wait states and for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible. Two formulas are defined for the (absolute) approximate maximum value of jitter Dm in [ns] dependent on the K2 - factor, the LMB clock frequency fLMB in [MHz], and the number m of consecutive fLMB clock periods. (6) (7) Table 31 PLL_SysClk Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Accumulated Jitter DP CC -7 − 7n s PLL base frequency fPLLBASE CC 50 200 320 MHz VCO input frequency fREF CC 8 − 16 MHz VCO frequency range fVCO CC 400 − 720 MHz PLL lock-in time tL CC 14 − 200 μsN > 3 2 14 − 400 μsN ≤ 32 for K2 100 ≤() and m fLMB MHz[]() 2⁄≤() Dmn s[] 740 K2 fLMB MHz[]× 05, fLMB MHz[] 1–× ⎛⎞×= else Dmn s[] 740 K2 fLMB MHz[]×

Data Sheet 5-61 V1.2, 2014-06 With rising number m of clock cycles the maximum jitter increases linearly up to a value of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum accumulated jitter remains at a constant valu e. Further, a lower LMB-Bus clock frequency fLMB results in a higher absolute maximum jitter value. Note: The specified PLL jitter values are va lid if the capacitive load per pin does not exceed CL = 20 pF with the maximum driver and sharp edge. Oscillator Watchdog (OSC_WDT) The expected input frequency is selected via the bit field SCU_OSCCON.OSCVAL. The OSC_WDT checks for too low frequencies and for too high frequencies. The frequency that is monitored is fOSCREF which is derived for fOSC. (8) The divider value SCU_OSCCON.OSCVAL has to be selected in a way that fOSCREF is 2.5 MHz. Note: fOSCREF has to be within the range of 2 MHz to 3 MHz and should be as close as possible to 2.5 MHz. The monitored frequency is too low if it is below 1.25 MHz and too high if it is above 7.5 MHz. This leads to the following two conditions:

• T o o l o w : fOSC <1 . 2 5M H z× (SCU_OSCCON.OSCVAL+1)
• Too high: fOSC >7 . 5M H z× (SCU_OSCCON.OSCVAL+1) Note: The accuracy is 30% for these boundaries. f OSCREF f OSC

Data Sheet 5-62 V1.2, 2014-06

5.3.8 ERAY Phase Locked Loop (ERAY_PLL)

Note: The specified PLL jitter values are va lid if the capacitive load per pin does not exceed CL = 20 pF with the maximum driver and sharp edge. Table 32 PLL_ERAY Parameters Parameter Symbol Values Unit Note / Test Con dition Min. Typ. Max. Accumulated jitter at SYSCLK pin DPP CC -0.8 − 0.8 ns Accumulated_Jitter DP CC -0.5 − 0.5 ns PLL Base Frequency of the ERAY PLL fPLLBASE_ERAY CC 50 250 360 MHz VCO input frequency of the ERAY PLL fREF CC 20 − 40 MHz VCO frequency range of the ERAY PLL fVCO_ERAY CC 450 − 500 MHz PLL lock-in time tL CC 5.6 − 200 μs

Data Sheet 5-63 V1.2, 2014-06

5.3.9 JTAG Interface Timing

The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 33 JTAG Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. TCK clock period t1 SR 25 −− ns TCK high time t2 SR 10 −− ns TCK low time t3 SR 10 −− ns TCK clock rise time t4 SR −− 4n s TCK clock fall time t5 SR −− 4n s TDI/TMS setup to TCK rising edge t6 SR 6.0 −− ns TDI/TMS hold after TCK rising edge t7 SR 6.0 −− ns TDO valid after TCK falling edge1) 1) The falling edge on TCK is used to generate the TDO timing. t8 CC 3.0 −− ns CL= 20 pF −− 13 ns CL=50 pF TDO high impedance to valid from TCK falling edge2) 2) The setup time for TDO is given implicitly by the TCK cycle time. t9 CC −− 14 ns CL=5 0p F TDO valid output to high impedance from TCK falling edge t10 CC −− 13.5 ns CL= 50 pF TDO hold after TCK falling edge t18 CC 2 −− ns

Data Sheet 5-64 V1.2, 2014-06 Figure 17 Test Clock Timing (TCK) Figure 18 JTAG Timing MC_JTAG _TCK

0.9 VDDP

0.5 VDDP

0.1 VDDP

MC_JTAG t18

Data Sheet 5-65 V1.2, 2014-06

5.3.10 DAP Interface Timing

The following parameters are applicable for communication through the DAP debug interface. Note: These parameters are not subject to production test but verified by design and/or characterization. Figure 19 Test Clock Timing (DAP0) Table 34 DAP Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. DAP0 clock period1) 1) See the DAP chapter for clock rate restrictions in the Active::IDLE protocol state. tTCK SR 12.5 −− ns DAP0 high time t12 SR 4 −− ns DAP0 low time1) t13 SR 4 −− ns DAP0 clock rise time t14 SR −− 2n s DAP0 clock fall time t15 SR −− 2n s DAP1 setup to DAP0 rising edge t16 SR 6.0 −− ns DAP1 hold after DAP0 rising edge t17 SR 6.0 −− ns DAP1 valid per DAP0 clock period2) 2) The Host has to find a suitable sampling point by analyzing the sync telegram response. t19 CC 8 −− ns CL=2 0p F ; f=8 0M H z 10 −− ns CL=5 0p F ; f=4 0M H z MC_DAP0

Data Sheet 5-67 V1.2, 2014-06

5.3.11 Peripheral Timings

Note: Peripheral timings are not subjected to production test. They are verified by design / characterization.

5.3.11.1 Micro Link Interface (MLI) Timing

Figure 22 MLI Interface Timing t27 t25 t26 t16 t17 t15t15 MLI_Tmg_2.vsd TDATAx TVALIDx TCLKx RDATAx RVALIDx RCLKx TREADYx RREADYx t10 t13 t11 t12 t14 t20 t27 MLI Transmitter Timing MLI Receiver Timing t23 t21 t22 t24

Data Sheet 5-68 V1.2, 2014-06 Note: The generation of RREADYx is in the input clock domain of the receiver. The reception of TREADYx is asynchronous to TCLKx. The MLI parameters are valid for CL = 50 pF, strong driver medium edge. Table 35 MLI Receiver Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. RCLK clock period t20 SR 1 / fFPI −− ns RCLK high time1)2) 1) The following formula is valid: t21 + t22 = t20. 2) Min and Max values for this parameter can be derived from the typ. value by considering the other receiver timing parameters. t21 SR − 0.5 x t20 − ns RCLK low time1)2) t22 SR − 0.5 x t20 − ns RCLK rise time3) 3) The RCLK max. input rise/fall times are best case para meters for fFPImax. For reduction of EMI, slower input signal rise/fall times can be used for longer RCLK clock periods. t23 SR −− 4n s RCLK fall time3) t24 SR −− 4n s RDATA/RVALID setup time before RCLK falling edge t25 SR 4.2 −− ns RDATA/RVALID hold time after RCLK falling edge t26 SR 2.2 −− ns RREADY output delay time t27 SR 0 − 16 ns Table 36 MLI Transmitter Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. TCLK clock period t10 CC 2 x 1 / fFPI −− ns TCLK high time1)2) t11 CC 0.45 x t10 0.5 x t10 0.55 x t10 ns TCLK low time1)2) t12 CC 0.45 x t10 0.5 x t10 0.55 x t10 ns

Data Sheet 5-69 V1.2, 2014-06

5.3.11.2 Micro Second Channel (MSC) Interface Timing

The MSC parameters are valid for CL =5 0p F . TCLK rise time t13 CC −− 0.3 x t10 3) ns TCLK fall time t14 CC −− 0.3 x t10 3) ns TDATA/TVALID output delay time t15 CC -3 − 4.4 ns TREADY setup time before TCLK rising edge t16 SR 18 −− ns TREADY hold time after TCLK rising edge t17 SR -2 −− ns 1) The following formula is valid: t11 + t12 = t10. 2) The min./max. TCLK low/high times t11/t12 include the PL L jitter of fSYS. Fractional divider settings must be regarded additionally to t11 / t12. 3) For high-speed MLI interface, strong driver sharp or medium edge selection (class A2 pad) is recommended for TCLK. Table 37 MSC Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. FCLP clock period1)2) t40 CC 2 x TMSC −− ns Table 36 MLI Transmitter (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Data Sheet 5-70 V1.2, 2014-06 Figure 23 MSC Interface Timing SOP4)/ENx outputs delay from FCLP4) rising edge t45 CC -5 − 5 ns ENx with strong driver and sharp (minus ) edge; CMOS mode -2 − 10 ns ENx with strong driver and medium (minus) edge 0 − 21 ns ENx with strong driver and soft edge SDI bit time t46 CC 8 x TMSC −− ns SDI rise time t48 SR −− 200 ns SDI fall time t49 SR −− 200 ns 1) FCLP signal rise/fall times are only defined by the pad rise/fall times. 2) FCLP signal high and low can be minimum 1 / TMSC 3) TMSC = TSYS = 1 / fSYS. 4) SOP / FCLP either propagated by CMOS strong driver and non soft edge. Table 37 MSC Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. MSC_Tmg_1.vsd t45 t45 t40

Data Sheet 5-71 V1.2, 2014-06 Note: The data at SOP should be sampled with the falling edge of FCLP in the target device.

Data Sheet 5-72 V1.2, 2014-06

5.3.11.3 SSC Master/Slave Mode Timing

The SSC parameters are valid for CL = 50 pF, strong driver medium edge. Table 38 Parameters Parameter Symbol Values Unit Note / Test Conditi on Min. Typ. Max. SCLK clock period1)2)3) 1) SCLK signal rise/fall times are the same as the rise/fall times of the pad. 2) SCLK signal high and low times can be minimum 1xT. 3) Tmin = TSYS = 1/fSYS. t50 CC 2 x 1 / fFPI −− ns MTSR/SLSOx delay from SCLK rising edge t51 CC 0 − 8n s MRST setup to SCLK latching edge3) t52 SR 16.5 −− ns MRST hold from SCLK latching edge3) t53 SR 0 −− ns SCLK input clock period1)3) t54 SR 4 x 1 / fFPI −− ns SCLK input clock duty cycle t55_t54 SR 45 − 55 % MTSR setup to SCLK latching edge3)4) 4) Fractional divider switched off, internal baud rate generation used. t56 SR 1 / fFPI + 1 −− ns MTSR hold from SCLK latching edge t57 SR 1 / fFPI + 5 −− ns SLSI setup to first SCLK latching edge t58 SR 1 / fFPI + 5 −− ns SLSI hold from last SCLK latching edge5) t59 SR 7 −− ns MRST delay from SCLK shift edge t60 CC 0 − 16.5 ns SLSI to valid data on MRST t61 CC −− 16.5 ns

Data Sheet 5-73 V1.2, 2014-06 Figure 24 Master Mode Timing 5) For CON.PH=1 slave select must not be removed before the following shifting edge. This mean, that what ever is configured (shifting / latching first), SLSI must not be de-actived before the last trailing edge from the pair of shifting / latching edges. SSC_TmgMM SCLK1)2) MTSR1) t51 t51 MRST1) t53 Data valid t52 SLSOn2) t51 1) This timing is based on the following setup: CON.PH = CON.PO = 0. 2) The transition at SLSOn is based on the following setup: SSOTC.TRAIL = 0 and the first SCLK high pulse is in the first one of a transmission. t50

Data Sheet 5-74 V1.2, 2014-06 Figure 25 Slave Mode Timing SSC_TmgSM SCLK1) t55 MTSR1) t57 Data valid t56 SLSI t58 1) This timing is based on the following setup: CON.PH = CON.PO = 0. t54 t55 t59 Last latching SCLK edge First latching SCLK edge t57 Data valid t56 MRST1) t60 First shift SCLK edge t60 t61

Data Sheet 5-75 V1.2, 2014-06

5.3.11.4 ERAY Interface Timing

The timings of this section are valid for the strong driver and either sharp edge or medium edge settings of the output drivers with CL = 25 pF. The ERAY interface is onl y available for the SAK-TC 1724F-192F133HL and SAK- TC1724F-192F133HR . Table 39 ERAY Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Time span from last BSS to FES without the influence of quartz tolerancies (d10Bit_TX)1) 1) This includes the PLL_ERAY accumulated jitter. t60 CC 997.75 − 1002.25 ns TxD data valid from fsample flip flop txd_reg TxDA, TxDB (dTxAsym) 2)3) 2) Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers. Quarz tolerance and PLL_ERAY accumulated jitter are not included. 3) E-Ray TxD output drivers have an asymmetry of rising and falling edges of | tFA2 - tRA2| ≤ 1 ns. t61-t62 CC −− 1.5 ns Asymmetrical delay of rising and falling edge (TxDA, TxDB) Time span between last BSS and FES without influence of quartz tolerancies (d10Bit_RX) 1)4)5) 4) Limits of 966ns and 1046.1ns correspond to (30%, 70%) * VDDP FlexRay standard input thresholds. For input thresholds of this product, a correction of - 0.5 ns and +0.1 ns has to be applied. t63 SR 966 − 1046.1 ns RxD capture by fsample (RxDA/RxDB sampling flip-flop) (dRxAsym)5) t64-t65 CC −− 3.0 ns Asymmetrical delay of rising and falling edge (RxDA, RxDB) TxD data delay from sampling flip-flop dTxdly CC −− 10.0 ns Px_PDRz.PDy =0 0 0B −− 15.0 ns Px_PDRz.PDy =0 0 1B RxD capture delay by sampling flip-flop dRxdly CC −− 10.0 ns

Data Sheet 5-76 V1.2, 2014-06 Figure 26 ERAY Timing 5) Valid for output slopes of the bus driver of dRxSlope 5ns, 20% * VDDP to 80% * VDDP, according to the FlexRay Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming signal have to satisfy the following inequality: -1.6ns ≤ |tFA2 - tRA2| ≤ 1.3ns. TXD t60

0.7 VDD

0.3 VDD

(Byte Start Sequence) Last CRC Byte FES (Frame End Sequence) ERAY_TIMING RXD t63 (Byte Start Sequence) Last CRC Byte FES (Frame End Sequence)

0.9 VDD

0.1 VDD

Data Sheet 5-77 V1.2, 2014-06

5.4 Package and Reliability

5.4.1 Package Parameters

Table 40 Thermal Characteristics of the Package Device Package R ΘJCT 1) The top and bottom thermal resistances between the case and the ambient ( RTCAT, RTCAB) are to be combined with the thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate the total thermal resistance between the junction and the ambient ( RTJA). The thermal resistances between the case and the ambient (RTCAT, RTCAB) depend on the external system (PCB, case) characteristics, and are under user responsibility. The junction temperature can be calculated using the following equation: TJ = TA + RTJA × PD, where the RTJA is the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA can be obtained from the upper four partial thermal resistances. RΘJC B1) RΘJCL Unit Note TC1724 PG-LQFP-144-17 9.0 0.4 28.1 K/W

Data Sheet 5-78 V1.2, 2014-06

5.4.2 Package Outline

Figure 27 Package Outlines PG-LQFP-144-17 You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products.

5.4.3 Flash Memory Parameters

The data retention time of the TC1724’s Flash memory depends on the number of times the Flash memory has been erased and programmed. Table 41 Exposed pad Dimensions Ex 7.5 mm Ey 7.5 mm

Data Sheet 5-79 V1.2, 2014-06 Table 42 FLASH32 Parameters Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max. Data Flash Erase Time per Sector tERD CC −− 31) s Program Flash Erase Time per 256 KByte Sector tERP CC −− 5s Program time data flash per page2) tPRD CC −− 5.3 ms without reprogramming −− 15.9 ms with two reprogramming cycles Program time program flash per page tPRP CC −− 5.3 ms without reprogramming −− 10.6 ms with one reprogramming cycle Data Flash Endurance NE CC 60000 −− cycles Min. data retention 5 years Erase suspend delay tFL_ErSusp CC −− 15 ms Wait time after margin change tFL_MarginDel SR 10 −− μ s Program Flash Retention Time, Physical Sector5)6) tRET CC 20 −− years Max. 1000 erase/ program cycles Program Flash Retention Time, Logical Sector 5)6) tRETL CC 20 −− years Max. 100 erase/ program cycles UCB Retention Time5)6) tRTU CC 20 −− years Max. 4 erase/ program cycles per UCB Wake-Up time2) tWU CC −− 270 μs

Data Sheet 5-80 V1.2, 2014-06

5.4.4 Quality Declarations

1) In case of wordline oriented defects (see robust EEPROM emulation in the User's Manual) this erase time can increase by up to 100%. 2) In case the Program Verify feature detects weak bi ts, these bits will be programmed up to twice more. Each reprogramming takes additional 5 ms. 3) In case the Program Verify f eature detects weak bits , these bits will be programmed once more. The reprogramming takes additional 5 ms. 4) Only valid when a robust EEPROM emulation algorith m is used. For more details see the User´s Manual. 5) Storage and inactive time included. 6) At average weighted junction temperature Tj = 100°C, or the retention time at average weighted temperature of Tj = 110°C is minimum 10 years, or the retention time at average weighted temperature of Tj = 150°C is minimum 0.7 years. Table 43 Quality Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Operation Lifetime1) 1) This lifetime refers only to the time when the device is powered on. tOP – – 24000 hours – 2) ESD susceptibility according to Human Body Model (HBM) VHBM – – 2000 V Conforming to JESD22-A114-B ESD susceptibility according to Charged Device Model (CDM) VCDM – – 500 V Conforming to JESD22-C101-C Moisture Sensitivity Level MSL – – 3 – Conforming to Jedec J-STD-020C for 240°C Table 42 FLASH32 Parameters (cont’d) Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.

Data Sheet 5-81 V1.2, 2014-06

5.5 Revision History

Changes from V0.3 to V0.4D1

• Operating Conditions – Added footnote 3 and 4 – Updated KOVAN and KOVAP max values – Added fCPU, fLMB, fPCP, fFPImax for SAK-TC1724F-1 92F133HL, SAK-TC1724F- 192F133HR, SAK-TC1724N-192F80HR, SAK-TC1724N-128F80HR. – Updated limits for VDD, VDDM, VDDP. – Added IIN, ΣIIN – Updated ΣISC_PG
• Standard Pad Class A1 – Changed RDSON1 to RDSONM, added new condition “PMOS” for 140ohms, added a new condition for “NMOS” with a max value of 100ohms – Added RDSONW – Changed min value of VIHA1 to 0.6 x VDDP – Changed min value of VILA1 / VIHA1 to 0.6
• Standard Pad Class A1+ – Added HYSA1+ – Added VILA1+ / VIHA1+ – Added RDSONW, RDSONM – RDSON1+, added new condition “PMOS” for 85ohms, added a new condition for “NMOS” with a max value of 70ohms – Changed min value of VIHA1+ to 0.6 x VDDP – Deleted -2000nA to 2000nA limits for IOZA1+
• Standard Pad Class A2 – Added HYSA2 – Added RDSONW, RDSONM – RDSON2, added new condition “PMOS” for 25ohms, added a new condition for “NMOS” with a max value of 20ohms – tFA2, added max 18000ns for CL=20000pF; pinout driver=medium, 65000ns for CL=20000pF;pinout driver=weak – tRA2, removed 140ns for CL=150pF;pinout driver=weak – tRA2, added 550ns for CL=150pF,pinout driver=weak, 18000ns for CL=20000pF, pinout driver=medium, 65000ns for CL=20000pF, pinoutdriver=weak
• Standard Pad Class F – Added HYSF 2) For worst-case temperature profile equivalent to: 1200 hours at Tj = 125...160oC 3600 hours at Tj = 110...125oC 7200 hours at Tj = 100...110oC 11000 hours at Tj = 25...110oC 1000 hours at Tj = -40...25oC

Data Sheet 5-82 V1.2, 2014-06 – Changed min value of VIHF to 0.6 x VDDP – Added min value of VILF / VIHF as 0.6 – Added RDSONW, RDSONM – Deleted note for tFF, tRF

• Standard Pad Class I – Changed min value of VIHI to 0.6 x VDDP – Changed min value of VILI / VIHI as 0.6
• LVDS Pads – Removed input hysteresis F, HYSF – Added note “Parallel termination 100 Ohm +-1%” for tFL, tRL, tSET_LVDS
• Standard Pad Class S – Changed max value of VIHS to 3.6 – Changed min value of VILS to 2.1 – Added input leakage current, IOZS
• ADC parameters – Changed typ value of CAINSW to 9pF – Changed typ value of CAINTOT to 20pF – Updated notes for EADNL,EAGAIN,TUE,EAINL,EAOFF – Changed fADCI to max 20MHz – Added fADC of 110MHz where ffpimax=110MHz – Added fADC of 80MHz where ffpimax=80MHz – Updated fADC min of 4MHz – Added sample time, tS, 2 to 255 tADCI – Added calibration time after reset, tCAL max 4352 cycles – Included footnote for TUE for 10-bit and 8-bit conversion – Removed IAIN7T (covered by RAIN7T ) – Removed IAREF, added QCONV – Updated notes for IOZ2 and IOZ3 – Updated typ value of 900Ohm for RAIN
• FADC parameters – Updated note for EFGRAD – Updated note for EFOFF – Added fFADC of 110MHz where ffpimax=110MHz – Added fFADC of 80MHz where ffpimax=80MHz – Added conversion time, tC – Added analog input voltage range,V AINF
• OSC XTAL parameters – Added fOSC – Changed max value of VIHX to VDDP+0.5V – Changed min value of VILX to -0.5V – Added typ values for internal load capacitors, CL0 to CL3, 2.5pF, 2.5pF, 4pF, 6.5pF – Added HYSAX
• Power Supply parameters

Data Sheet 5-83 V1.2, 2014-06 – Updated IDDP, IDDM, IDDP_FP – Added IDD for fCPU=80MHz for max and realistic patterns – Updated PD values for max and real patterns, all external, fCPU=133MHz – Added text to of fCPU=133MHz to the note for the PD parameter. – Added PD for fCPU=80Mhz for max and realistic patterns for both all external mode and 5V only with ext.pass device mode – Current consumption for LVDS pad pairs is updated for all LVDS pads in total – Deleted the redundant IDDP – Updated IDDP_FP, IDDP_PORST, IDD_PORST – Deleted RTHJA parameter

• Power Sequencing – Added Power Sequencing for 3.3V Supply Only section
• Power, Pad and Reset Timing parameters – Removed redundant note for tHDH, tHDS – Added text from note “TESTMO DE/TRST” to the name of tPOH and tPOS, deleted note
• EVR Parameters – Added IPU_VDPG, VIH and VIL parameters in Pass Device Detector Table – Added EVR Parameter Table
• PLL SYSCLK parameters – Changed max value for fVCO – Added min value of 50us for tL – Included formula 1 and 2 – Removed note for peak-to-peak noise on pad supply voltage
• PLL ERAY parameters – Changed typ value to 250MHz for fPLLBASE – Added min value of 50us for tL – Removed note for peak-to-peak noise on pad supply voltage
• JTAG Interface parameters – Changed to ‘=’ signs in the notes for t8, t9 and t10
• DAP parameters
• Peripheral Timings – Removed note for Peripheral Timings “Peripheral timing parameters are not subject to production test. They are verified by design/characterization.”
• MLI Timing – Added text for MLI para meters valid for CL=25pF
• MLI Receiver parameters – Changed fSYS to 110MHz in footnote 3
• MLI Tranmitt er parameters – Changed t13, TCLK rise time and t14, TCLK fall time to 0.3 x t10
• MSC parameters – Added text for MSC para meters valid for CL=25pF – Added limits for different pad drive strength of t45

Data Sheet 5-84 V1.2, 2014-06

• parameters – Changed min value of t t52 to 16.5ns
• ERAY parameters – Changed min value of t60 – Changed max value of t61-t62 – Changed min and max values of t63 – Changed max value of t64-t65 – Added dTxdly, dRxdly – Updated ERAY timing figure
• Flash32 parameters – Updated tPRD, tPRP – Changed min value of WSDF to 50ns x fLMB – Updated footnote 3
• Package parameters – Added RTHJCT, RTHJCB, RTHJCL for LQFP144
• Package outline – Added package outline for LQFP176 Changes from V0.5 to V0.6
• Added max limit for VRST5 for 5.0V single supply
• Removed note above MLI Transmitter table
• Updated conditions for tFL and tRL for LVDS pad parameters
• Updated limits for RDSONW and RDSONM for Class A1 pads
• Updated limits for RDSONW and RDSONM and RDSON1+ for Class A1+ pads
• Updated limits for RDSONW and RDSONM and RDSON2 for Class A2 pads
• Updated limits for RDSONW and RDSONM for Class F pads
• Added footnote 7 to ADC table
• Updated QCONVof ADC table
• Updated conditions to tL of PLL Sysclk
• Changed t19 of DAP from SR to CC
• Removed condition for V5
• Added FADC input circuit
• Updated max limit for VAGND0 and min limit for VAREF0
• tBWG and tBWR are added to ADC table
• Updated description of tCAL
• Added a placeholder for RAIN, RAIN7T, RAREF, tS, fADCI, EADNL, EAINL, EAGAIN, EAOFF, TUE at a separate ADC table for VDDM=3.3V
• Added a placeholder for tAWAF, tAWAS to both ADC tables for VDDM=5V and VDDM=3.3V
• Added a placeholder for tFWAF, tFWAS to FADC table for VDDM=5V, VDDM=3.3V
• Removed limits of gain=8 for EFGRAD
• Added VFAREFI and VFAGNDI parameters
• Updated limit of tSF2 to min 120ns
• Typo in Note for IV5 at 80MHz is corrected.

Data Sheet 5-85 V1.2, 2014-06

• Updated max limit of ΣIIN.
• Added IIN.
• Added Pin Reliability in Overload subchapter.
• Removed sentence “Exposure to conditions within the maximum ratings will not affect device reliability.” Replaced with the Pin Reliability in Overload subchapter.
• Added definition of driver strength settings, updated footnote 4 for ERAY Interface Timing
• Updated max limits of Flash parameters tPRD, tPRP
• Updated representation of IDDP
• Updated limits of IDD_PORST to max 110mA
• Updated limits of IDDP_PORST to max 6mA
• Updated limits of IDD for real pattern, fCPU=133MHz, to max 212mA
• Added new parameter IDDSUM
• Updated max limit of IDDM to 32mA
• Updated TC1724 IV5 for max and real patterns, with and without ERAY, fCPU=133MHz
• Updated TC1724 IV5 for max pattern, fCPU=80MHz
• Updated PD for real pattern, fCPU=133MHz, all external supplies.
• Updated TC1724 PD for max and real patterns, with and without ERAY, fCPU=133MHz, 5V only with external pass device.
• Updated TC1724 PD for max and real patterns, fCPU=80MHz, 5V only without external pass device.
• Updated limit for RDSON2 of A2 pad, P_MOS
• Removed VIH for Pass Device Detector
• Updated limits for VIL of Pass Device Detector
• Updated limits and test conditions for ∆VLOREG33 and ∆VLIREG33
• Updated test condition for 5.0V single supply ∆VLOREG13
• Updated limits and test condition for 5.0V single supply ∆VLIREG13
• Corrected typ and max limits for COUT33 and COUT13
• Added limit and test condition for 3.3V single supply ∆VLOREG13 and ∆VLIREG13
• Application reset boot time limits are updated
• Added min limit for IOZS
• Added a new parameter VILSD
• Updated limits for tBP, STT
• Removed typical text from load of Peripheral Timing sections.
• Limits for EFGRAD with Gain=4 is changed to TBD
• Min limit for VDDM is changed to TBD
• Added EFREFI
• Added a placeholder for RFAIN, EFDNL, EFINL, EFGRAD, EFOFF at a separate ADC table for VDDM=3.3V
• Added max and typ limits for RRAIN for VDDM=3.3V
• Updated limits of PD for real pattern, fCPU=80MHz, to max 669mW
• Added new variant SAK-TC1724F-192F80HR
• Updated text for Note column of NE

Data Sheet 5-86 V1.2, 2014-06

• Corrected typo for Class D pads in PN-Juncti on Characteristics for positive/negative overload tables
• Updated limits of IDD for max pattern, fCPU=133MHz, to max 310mA
• Updated limits of IDD for max pattern, fCPU=80MHz, to max 248mA
• Updated limits of PD for max pattern, fCPU=133MHz, to max 902mA
• Updated limits of IDD for max pattern, fCPU=80MHz, to max 810mA
• Corrected typo for COUT13
• Updated load jump current for COUT33 and COUT13 for fCPU=80MHz
• Changed min to typ value for CIN5 Changes from V0.6 to V0.7
• Name of package is updated Changes from V0.7 to V0.8
• Absolute maximum rating section for is updated for VDDP, VIN, VAIN, VAREF0, VAINF
• A footnote is added to tERD
• A note is added, updated pad supply levels in Pin Reliability in Overload section
• Updated min limit for t17 of MLI
• Added a footnote to IDDP
• Included text to power sequencing sections for setting of P0.4 and P0.5.
• Added limits for EFDNLfor Gain= 4, 8
• Changed STT to tEVR, updated Power, Pad and Reset Timing figure
• Changed min limit of tL for PLL_ERAY timing
• Changed min limit of tL for PLL_Sysclk timing
• Removed IPU_VDPG for VDD5≥2.97V, VDD5£3.63V
• Updated limit and test condition for COUT33, COUT13
• Updated limit for CIN5
• Updated limit and test condition for ∆VLOREG33
• Removed PSRR33, PSRR13
• Updated test condition for ∆VLOREG13
• Updated limit and test condition for ∆VLIREG13
• Updated min limit for MSC t45, strong sharp setting, CMOS mode
• Added ∆VOUT33, ∆VOUT13 parameters
• Updated first sentence for Chapter 5.3
• Added text for MLI and SSC parameters for validity of strong driver medium edge only
• Updated description for t52 and t53
• Changed SSC parameters from CC to SR for t56, t57, t58, and t59
• Changed min to max limit for EVR Supply ramp-up parameter
• Updated min limit for IPU_VDPG Changes from V0.8 to V1.0
• Added limits for EFGRAD for Gain= 4, 8
• Added limits for EFREFI

Data Sheet 5-87 V1.2, 2014-06

• Updated VFAGNDI, VFAREFI, changed from SR to CC
• A footnote is added for VFAREFI
• Updated limit for COUT13
• Updated limit for CIN5
• Added min limit for V5
• Updated limits for fADCI, tBWG, tBWR , tAWAF, tAWAS, tFWAF, , tFWAS
• Updated limits for ADC table, VDDM=3.3V, fADCI, tBWG, tBWR , tAWAF, tAWAS, tFWAF, , tFWAS, RAIN7T, EADNL, EAGAIN, EAINL, , EAOFF, TUE , QCONV
• Corrected typo in test condition for RDSON
• Removed footnote 2 from ΣISC_D
• Added footnote 3 to VDDM
• Corrected typo for Class F in Table 14 and Table 15
• Updated max limit for ADC parameter tS
• Added footnote 2 for t9 of JTAG parameter
• Changed t26, t27 from CC to SR
• Updated max limit for ADC parameter VAIN
• Added footnote 5 to t59
• Added tPOR_APP parameter of Reset Timing parameters
• Updated max limit fo r ERAY parameter t60 Changes from V1.0 to V1.1
• Updated limits for ADC table, VDDM=3.3V, fADCI, t BWG, tBWR , tAWAF, tAWAS, RAIN7T, EADNL, EAGAIN, EAINL , EAOFF, TUE , QCONV
• Added new marking options for TC1724
• Updated description for tCAL
• Added a footnote to QCONV Changes from V1.1 to V1.2
• change t48 from 100ns to 200ns in table 29
• change t49 from 100ns to 200ns in table 29
• extend KOVAN conditon from IOV≤ 0m A ; IOV≥ -1 mA to IOV≤ 0m A ; IOV≥ -2 mA
• clearify leakage definition for A1 and I pads for 150°C < TJ ≤ 160°C
• change VILS from 2.1V to 1.9V in table 25
• change t56 from 1 / fFPI to 1 / fFPI + 1 in table 30
• change RAIN from 4500 Ohm to 9000 Ohm in table 15
• remove the following product options: – SAK-TC1724N-192F133HL – SAK-TC1724F-128F133HL – SAK-TC1724F-128F133HR – SAK-TC1724N-128F133HL – SAK-TC1724N-128F133HR – SAK-TC1724N-128F80HL – SAK-TC1724N-128F80HR – SAK-TC1724N-192F133HL

Data Sheet 5-88 V1.2, 2014-06 – SAK-TC1724F-128F80HR

• shift the product SAK-TC1724 N-192F133HR from step AB to AC
• add for products SAK-TC1724F-192F133HR and SAK-TC1724N-192F80HR step AC

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