TC1232 TELCOM | Alldatasheet

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Technical content

5-19TELCOM SEMICONDUCTOR, INC. PRELIMINARY INFORMATION TC1232

FEATURES

n Debounced Manual Reset Input for External Override MICROPROCESSOR MONITOR

APPLICATIONS

n Critical µP Power Monitoring FUNCTIONAL BLOCK DIAGRAM VCC TC1232 5%/10% TOLERANCE SELECTTOL DEBOUNCE WATCHDOG TIMEBASE SELECT PB RST TD GND REF WATCHDOG TIMER RESET GENERATOR RST RST ST

ORDERING INFORMATION

Part No. Package Temp. Range TC1232COA 8-Pin SOIC 0 °C to +70°C TC1232COE 16-Pin SOIC (Wide) 0 °C to +70°C TC1232CPA 8-Pin PDIP 0 °C to +70°C TC1232EOA 8-Pin SOIC – 40 °C to +85°C TC1232EOE 16-Pin SOIC (Wide) – 40 °C to +85°C TC1232EPA 8-Pin PDIP – 40 °C to +85°C TC1232-4 11/6/96 GENERAL DESCRIPTION The TC1232 is a fully-integrated processor supervisor. It provides three important functions to safeguard processor sanity: precision power on/off reset control, watchdog timer and external reset override. On power-up, the TC1232 holds the processor in the reset state for a minimum of 250msec after V CC is within tolerance to ensure a stable system start-up. Microprocessor sanity is monitored by the on-board watchdog circuit. The microprocessor must provide a peri- odic low-going signal on the ST input. Should the processor fail to supply this signal within the selected time-out period (150msec, 600msec or 1200msec), an out-of-control pro- cessor is indicated and the TC1232 issues a processor reset as a result. The outputs of the TC1232 are immediately driven active when the PB input is brought low by an external push- button switch or other electronic signal. When connected to a push-button switch, the TC1232 provides contact debounce. The TC1232 is packaged in a space-saving 8-pin plastic DIP or SOIC package and requires no external components.

5-20 TELCOM SEMICONDUCTOR, INC. TC1232 MICROPROCESSOR MONITOR ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin (With Respect to GND) – 0.3V to +5.8V Operating Temperature Range: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS: TA = TMIN to TMAX; VCC = +4.5V to 5.5V, unless otherwise specified. Symbol Parameter Test Conditions Min Typ Max Unit VCC Supply Voltage 4.5 5.0 5.5 V VIH ST and PB RST 2.0 — V CC +0.3 V Input High Level Note 1 VIL ST and PB RST – 0.3 — +0.8 V Input Low Level IL Input Leakage ST, TOL – 1.0 — +1.0 µA IOH Output Current RST V OH = 2.4V – 1.0 –12 — mA IOL Current RST, RST V OL = 0.4V 2.0 10 — mA ICC Operating Current Note 2 — 50 200 µA VCCTP VCC 5% Trip Point (Note 3) TOL = GND 4.50 4.62 4.74 V VCCTP VCC 10% Trip Point (Note 3) TOL = V CC 4.25 4.37 4.49 V AC ELECTRICAL CHARACTERISTICS: TA = TMIN to TMAX; VCC = +5V to +10%, unless otherwise specified. Symbol Parameters Test Conditions Min Typ Max Units tPB PB RST (Note 5) Figure 3 20 — — msec tPBD PB RST Delay Figure 3 1 4 20 msec tRST Reset Active Time 250 610 1000 msec tST ST Pulse Width Figure 4 75 — — nsec tTD ST Time-out Period Figure 4 TD Pin = 0V 62.5 150 250 msec TD Pin = Open 250 600 1000 msec TD Pin = VCC 500 1200 2000 msec tF VCC Fall Time (Note 4) Figure 5 10 — — µsec CAPACITANCE (Note 4): TA = +25°C Symbol Parameters Test Conditions Min Typ Max Units C IN Input Capacitance ST, TOL — — 5 pF C OUT Output Capacitance RST, RST ——7 p F

5-21TELCOM SEMICONDUCTOR, INC. AC ELECTRICAL CHARACTERISTICS: (Cont. ) TA = TMIN to TMAX ; VCC = +5V to +10%, unless otherwise specified. Symbol Parameter Test Conditions Min Typ Max Units tR VCC Rise Time (Note 4) Figure 6 0 — — µsec tRPD VCC Detect to RST High Figure 7, V CC Falling — — 100 nsec and RST Low tRPU VCC Detect to RST High Figure 8, V CC Rising 250 610 1000 msec and RST Open (Note 6) PIN DESCRIPTION Pin No. Pin No. Pin No. (8-Pin PDIP) (8-Pin SOIC) (16-Pin SOIC) Symbol Description 1 1 2 PB RST Push-button Reset Input. A debounced active-low input that ignores pulses less than 1msec in duration and is guaranteed to recognize inputs of 20msec or greater. 2 2 4 TD Time Delay Set. The watchdog time-out select input (t TD = 150msec for TD = 0V, tTD = 600msec for TD = open, tTD = 1.2sec for TD = VCC ). 3 3 6 TOL Tolerance Input. Connect to GND for 5% tolerance or to V CC for 10% tolerance. 4 4 8 GND Ground. 5 5 9 RST Reset Output (Active High) - goes active: 1. If V CC falls below the selected reset voltage threshold 2. If PB RST is forced low 3. If ST is not strobed within the minimum time-out period 4. During power-up 6 6 11 RST Reset Output (Active Low, Open Drain) - see RST. 7 7 13 ST Strobe Input. Input for watchdog timer. 881 5 V CC The +5V Power-Supply Input. 1, 3, 5, 7, 10, NC No Internal Connection. 12, 14, 16 NOTES: 1. PB RST is internally pulled up to VCC with an internal impedance of typically 40kΩ . 2. Measured with outputs open. 3. All voltages referenced to GND. 4. Guaranteed by design. 5. PB RST must be held low for a minimum of 20msec to guarantee a reset. 6. t R = 5µsec. 1 8 2 7 3 6 4 5 TC1232CPA TC1232EPA RST RST GND TOL TD PB RST RST ST VCC RST ST RSTGND TOL TD PB RST RST ST VCC PB RST TC1232COA TC1232EOA V NC TD NC NC TOL GND NC NC NC TC1232COE TC1232EOE NC CC NC 16-Pin SOIC Wide8-Pin PDIP 8-Pin SOIC PIN CONFIGURATION S TC1232 MICROPROCESSOR MONITOR

5-24 TELCOM SEMICONDUCTOR, INC. Figure 8. VCC Detect Reset Output Delay (Power-Up)Figure 7. VCC Detect Reset Output Delay (Power-Down)