TC1163

TC1163 INFINEON | Alldatasheet

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Data Sheet, V1.0, Apr. 2008 Microcontrollers TC1163/TC1164 32-Bit Single-Chip Microcontroller TriCore

81726 München, Germany

© Infineon Technologies AG 2008. All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non- infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Data Sheet, V1.0, Apr. 2008 Microcontrollers TC1163/TC1164 32-Bit Single-Chip Microcontroller TriCore

Data Sheet V1.0, 2008-04 Trademarks TriCore® is a trademark of Infineon Technologies AG. TC1163/TC1164 Data Sheet Revision History: V1.0, 2008-04 Previous Version: V0.3 2007-03 Page Subjects (major chang es since last revision) 7 VSSOSC3 is deleted from the TC1163/TC1164 Logic Symbol. 8, 10 TDATA0 of Pin 17, TCLK0 of Pin 20, TCLK0 of Pin 74 and TDATA0 of Pin 77 are updated in the Pinning Diagram and Pin Definition and Functions Table. 53 Transmit DMA request in Block Diagram of ASC Interfaces is updated. 55 Alternate output functions in block diagram of SSC interfaces are updated. 61 Programmable baud rate of the MLI is updated. 62 TDATA0 and TCLK0 of the block diagram of MLI interfaces are updated. 74 The description for WDT double reset detection is updated. 111 The power sequencing details is updated. 122 MLI timing, maximum operating frequency limit is extended, t31 is added. 126 Thermal resistance junction leads is updated. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com

Table of ContentsPreliminary Data Sheet 1 V1.0, 2008-04 Table of Contents

Table of ContentsPreliminary Data Sheet 2 V1.0, 2008-04

Summary of FeaturesPreliminary Data Sheet 3 V1.0, 2008-04

1 Summary of Features

The TC1163/TC1164 has the following features:

• High-performance 32-bit super-scaler TriCore v1.3 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) – 80 MHz operation at full temperature range
• Peripheral Control Processor wit h single cycle instruction (PCP2) – 8 Kbyte Parameter Memory (PRAM) – 12 Kbyte Code Memory (CMEM)
• Multiple on-chip memories – 40 Kbyte Local Data Memory (SRAM) – 8 Kbyte Overlay Memory – 8 Kbyte Scratch-Pad RAM (SPRAM) – 8 Kbyte Instruction Cache (ICACHE) – 1024 Kbyte Program Flash (for inst ruction code and constant data) – 16 Kbyte Data Flash (e.g. 2 Kbyte EEPROM emulation) – 16 Kbyte Boot ROM
• 8-channel DMA Controller
• Fast-response interrupt system with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2
• High-performance on-chip bus structure – 64-bit Local Memory Bu s (LMB) to Flash memory – System Peripheral Bus (SPB) for interconnections of functional units
• Versatile on-chip Peripheral Units – Two Asynchronous/Synchronous Seri al Channels (ASC s) with baudrate generator, parity, framing and overrun error detection – Two High Speed Synchronous Serial Channels (SSCs) with programmable data length and shift direction – One Micro Second Bus (MSC) interface for serial port expansion to external power devices – One high-speed Micro Link Interface (MLI) for serial inter-processor communication – One MultiCAN Module with two CAN n odes and 64 free assignable message objects for high efficien cy data handling via FIFO buffering and gateway data transfer 1) Not applicable to TC1163

Summary of FeaturesPreliminary Data Sheet 4 V1.0, 2008-04 – One General Purpose Timer Array Module (G PTA) with a powerful set of digital signal filtering and ti mer functionality to real ize autonomous and complex Input/Output management – One 16-channel Analog -to-Digital Converter unit (ADC) with selectable 8-bit, 10- bit, or 12-bit, supporting 32 input channels – One 2-channel Fast Analog -to-Digital Converter unit (FADC) with concatenated comb filters for hardware data reducti on: supporting 10-bit resolution, with minimum conversion time of 262.5ns

• 32 analog input lines for ADC and FADC
• 81 digital general purpose I/O lines
• Digital I/O ports with 3.3 V capability
• On-chip debug support for OCDS Level 1 and 2 (CPU, PCP, DMA)
• Power Management System
• Clock Generation Unit with PLL
• Core supply vo ltage of 1.5 V
• I/O voltage of 3.3 V
• Full Industrial and Multi-Market te mperature range: -40° to +85°C
• PG-LQFP-176-2 package

Summary of FeaturesPreliminary Data Sheet 5 V1.0, 2008-04

Ordering Information

The ordering code for Infin eon microcontrollers provides an exact refe rence to the required product. This ordering code identifies:

• The derivative itself, i.e. its function set, the temper ature range, and the supply voltage
• The package and the type of delivery For the available ordering c odes for the TC1163/TC 1164, please refer to the “Product Catalog Microcontrollers” that summarizes all available microcontroller variants. This document describes the derivatives of the device.The Table 1-1 enumerates these derivatives and summarizes the differences. Table 1-1 TC1163/TC1164 Derivative Synopsis Derivative Ambient Temperature Range SAF-TC1163-128F80HL T A = -40oC to +85oC SAF-TC1164-128F80HL T A = -40oC to +85oC

General Device InformationPreliminary Data Sheet 6 V1.0, 2008-04

2 General Device Information

Chapter 2 provides the general information for the TC1163/TC1164.

2.1 Block Diagram

Figure 2-1 shows the TC1163/TC1164 block diagram. Figure 2-1 TC1163/TC1164 Block Diagram DMA 8 ch. BI0

8 KB PRAM

12 KB CMEM

System Peripheral Bus (SPB) Ports SBCU TC1163/TC1164 Block Diagram Multi CAN (2 Nodes,

64 Buffer)

Ext. Request Unit LBCU LFI Bridge OCDS Debug Interface/JT AG Abbreviations: ICACHE: Instruction Cache SPRAM: Scratch-Pad RAM LDRAM: Local Data RAM OVRAM: Overlay RAM BROM: Boot ROM PFlash: Program Flash DFlash: Data Flash PRAM: Parameter Memory in PCP CMEM: Code Memory in PCP MLI0 TriCore (TC1.3M) PMI

8 KB SPRAM

8 KB ICACHE

40 KB LDRAM

16 KB BROM

1024 KB Pflash

16 KB DFlash

8 KB OVRAM

2 ch. ADC0 32 ch. An al o g In pu t Assignment SSC1 SSC0 DMA Bus PLL SCU PLL F PI-Bus Interface Local Memory Bus (LMB) BI1 SMIF MSC0 1) Not applicable to TC1163

General Device InformationPreliminary Data Sheet 7 V1.0, 2008-04

2.2 Logic Symbol

Figure 2-2 shows the TC1163/TC1164 logic symbol. Figure 2-2 TC1163/TC1164 Logic Symbol FCLN0 FCLP 0A TESTMODE BYPASS NMI HDRST PORST VSS MSC0 Control Digital Circuitry Power Supply General Control SOP0A SON0 VDD VDDP AN[35:0]ADC Analog Inputs VDDM VSSM VDDMF VSSMF VDDAF VSSAF VAREF0 VAGND0 VFAREF VFAGND VDDFL3 ADC/FADC Analog Power Supply TC 1163 /TC 1164 Logic Sym bol Port 0 16-bit Alternate Functions BRKOUT XTAL1 XTAL2 Oscillator TDI TCK TRST Port 1 15-bit Port 2 14-bit Port 3 16-bit Port 4 4-bit GPTA, SCU GPTA, SSC1, ADC SSC0/1, MLI0, GPTA, MSC0 ASC0/1, SSC0/1, SCU, CAN TDO OCDS / JTAG Control GPTA, SCU TMS BRKIN TRCLK Port 5 16-bit GPTA, OCDS L 2, MLI0 TC1163/ TC1164 1) Alternate functions for CAN module is not applicable for TC 1163. VDDOSC3 VDDOSC VSSOSC

General Device InformationPreliminary Data Sheet 8 V1.0, 2008-04

2.3 Pin Configuration

Figure 2-3 shows the TC1163/TC1164 pin configuration. Figure 2-3 TC1163/TC1164 Pinnin g for PG-LQFP-176-2 Package 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 P0.0/IN0/SWCFG0/OUT0/OUT56 P0.1/IN1/SWCFG1/OUT1/OUT57 P0.2/IN2/SWCFG2/OUT2/OUT58 P0.3/IN3/SWCFG3/OUT3/OUT59 P0.4/IN4/SWCFG4/OUT4/OUT60 P0.5/IN5/SWCFG5/OUT5/OUT61 P0.6/IN6/SWCFG6/REQ2/OUT6/OUT62 P0.7/IN7/SWCFG7/REQ3/OUT7/OUT63 P0.8/IN8/SWCFG8/OUT8/OUT64 P0.9/IN9/SWCFG9/OUT9/OUT65 P0.10/IN10/SWCFG10/OUT10/OUT66 P0.11/IN11/SWCFG11/OUT11/OUT67 P0.12/IN12/SWCFG12/OUT12/OUT68 P0.13/IN13/SWCFG13/OUT13/OUT69 P0.14/IN14/SWCFG14/REQ4/OUT14/OUT70 P0.15/IN15/SWCFG15/REQ5/OUT15/OUT71 P1.0/IN16/OUT16/OUT72 P1.1/IN17/OUT17/OUT73 P1.2/IN18/OUT18/OUT74 P1.3/IN19/OUT19/OUT75 P1.4/IN20/EMG_IN/OUT20/OUT76 P1.5/IN21/OUT21/OUT77 P1.6/IN22/OUT22/OUT78 P1.7/IN23/OUT23/OUT79 P1.8/IN24/IN48/MTSR1B/OUT24/OUT48 P1.9/IN25/IN49/MRST1B/OUT25/OUT49 P1.10/IN26/IN50/OUT26/OUT50/SLSO17 P1.11/IN27/IN51/SCLK1B/OUT27/OUT51 AD0EMUX0/P1.12 AD0EMUX1/P1.13 AD0EMUX2/P1.14 TCLK0/OUT32/IN32/P2.0 SLSO13/SLSO03/OUT33/TREADY0A/IN33/P2.1 TVALID0A/OUT34/IN34/P2.2 TDATA0/OUT35/IN35/P2.3 OUT36/RCLK0A/IN36/P2.4 RREADY0A/OUT37/IN37/P2.5 OUT38/RVALID0A/IN38/P2.6 OUT39/RDATA0A/IN39/P2.7 P2.8/SLSO04/SLSO14/EN00 P2.9/SLSO05/SLSO15/EN01 P2.10/MRST1A P2.11/SCLK1A/FCLP0B P2.12/MTSR1A/SOP0B P2.13/SLSI1/SDI0 P3.0/RXD0A P3.1/TXD0A P3.2/SCLK0 P3.3/MRST0 P3.4/MTSR0 P3.5/SLSO00/SLSO10/SLSO00&SLSO10 P3.6/SLSO01/SLSO11/SLSO01&SLSO11 P3.7/SLSI0/SLSO02/SLSO12 P3.8/SLSO06/TXD1A P3.9/RXD1A P3.10/REQ0 P3.11/REQ1 P3.12/RXDCAN01)/RXD0B P3.13/TXDCAN01)/TXD0B P3.14/RXDCAN11)/RXD1B P3.15/TXDCAN11)/TXD1B OUT52/OUT28/HWCFG0/IN52/IN28/P4.0 OUT53/OUT29/HWCFG1/IN53/IN29/P4.1 OUT54/OUT30/HWCFG2/IN54/IN30/P4.2 P4.3/IN31/IN55/OUT31/OUT55/SYSCLK OCDSDBG0/OUT40/IN40/P5.0 OCDSDBG1/OUT41/IN41/P5.1 OCDSDBG2/OUT42/IN42/P5.2 OCDSDBG4/OUT44/IN44/P5.4 OCDSDBG3/OUT43/IN43/P5.3 OCDSDBG5/OUT45/IN45/P5.5 OCDSDBG6/OUT46/IN46/P5.6 OCDSDBG7/OUT47/IN47/P5.7 OCDSDBG8/RDATA0B/P5.8 OCDSDBG9/RVALID0B/P5.9 OCDSDBG10/RREADY0B/P5.10 OCDSDBG11/RCLK0B/P5.11 OCDSDBG12/TDATA0/P5.12 OCDSDBG13/TVALID0B/P5.13 OCDSDBG14/TREADY0B/P5.14 OCDSDBG15/TCLK0/P5.15 FCLP0A FCLN0 SOP0A SON0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN8 AN7 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AN35 TRST TCK TDI TDO TMS BRKIN BRKOUT NMI HDRST PORST BYPASS TESTMODE XTAL1 XTAL2 VDD VDDP VSS N.C. N.C. TRCLK TC1163/TC1164 VDD VDDP VSS VDDMF VSSMF VDDAF VSSAF VFAREF VFAGND VDDM VSSM VAREF0 VAGND0 VDD VDDP VSS VDD VDDP VSS VSS VDD VDDP VSS VDDOSC VDDOSC3 VSSOSC VDDFL3 VDDP VSS VDD VDDP VSS VDD VDDP VSS TC1163/TC1164 Pinning 1) Not applicable to TC1163

General Device InformationPreliminary Data Sheet 9 V1.0, 2008-04

2.4 Pad Driver and Input Classes Overview

The TC1163/TC1164 provides different types and classes of input and output lines. For understanding of the abbreviations in Table 2-2 starting at the next page, Table 2-1 gives an overview on the pad type and class types. Table 2-1 Pad Driver and Input Classes Overview Class Power Supply Type Sub Class Speed Grade Termination A 3.3V LVTTL I/O, LVTTL outputs (e.g. GPIO)

6 MHz No

(e.g. serial I/Os)

40 MHz Series termination

(e.g. BRKIN, BRKOUT)

80 MHz/ Yes, series

(e.g.Trace Clock)

80 MHz Yes, series

C 3.3V LVDS – 50 MHz Parallel termination D Analog input –– –

General Device InformationPreliminary Data Sheet 10 V1.0, 2008-04

2.5 Pin Definitions and Functions

Table 2-2 shows the TC1163/TC1164 pin definitions and functions. Table 2-2 Pin Definiti ons and Functions Symbol Pins I/O Pad Driver Class Power Supply Functions Parallel Ports P0 I/O A1 VDDP Port 0 Port 0 is a 16-bit bi-directional general- purpose I/O port which can be alternatively used for GPTA I/O lines or external trigger inputs. P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 145 146 147 148 166 167 173 174 149 150 151 152 168 169 175 176 IN0 / OUT0 / IN1 / OUT1 / IN2 / OUT2 / IN3 / OUT3 / IN4 / OUT4 / IN5 / OUT5 / IN6 / OUT6 / REQ2 IN7 / OUT7 / REQ3 IN8 / OUT8 / IN9 / OUT9 / IN10 / OUT10 / IN11 / OUT11 / IN12 / OUT12 / IN13 / OUT13 / IN14 / OUT14 / REQ4 IN15 / OUT15 / REQ5 OUT56 line of GPTA OUT57 line of GPTA OUT58 line of GPTA OUT59 line of GPTA OUT60 line of GPTA OUT61 line of GPTA OUT62 line of GPTA External trigger input 2 OUT63 line of GPTA External trigger input 3 OUT64 line of GPTA OUT65 line of GPTA OUT66 line of GPTA OUT67 line of GPTA OUT68 line of GPTA OUT69 line of GPTA OUT70 line of GPTA External trigger input 4 OUT71 line of GPTA External trigger input 5 In addition, the state of the port pins are latched into the software configuration input register SCU_SCLIR at the rising edge of HDRST . Therefore, Port 0 pins can be used for operating mode selections by software.

General Device InformationPreliminary Data Sheet 11 V1.0, 2008-04 P1 I/O VDDP Port 1 Port 1 is a 15-bit bi-directional general purpose I/O port which can be alternatively used for GPTA I/O lines, SSC1 and ADC0 interface. P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P1.8 P1.9 P1.10 P1.11 P1.12 P1.13 P1.14 107 108 109 110 IN16 / OUT16 / IN17 / OUT17 / IN18 / OUT18 / IN19 / OUT19 / IN20 / OUT20 / IN21 / OUT21 / IN22 / OUT22 / IN23 / OUT23 / IN24 / OUT24 / MTSR1B IN25 / OUT25 / MRST1B IN26 / OUT26 / SLSO17 IN27 / OUT27 / SCLK1B AD0EMUX0 AD0EMUX1 AD0EMUX2 OUT72 line of GPTA OUT73 line of GPTA OUT74 line of GPTA OUT75 line of GPTA OUT76 line of GPTA OUT77 line of GPTA OUT78 line of GPTA OUT79 line of GPTA IN48 / OUT48 line of GPTA SSC1 master transmit output / slave rec. input B IN49 / OUT49 line of GPTA SSC1 master receive input / slave transmit output B IN50 / OUT50 line of GPTA SSC1 slave select output 7 IN51 / OUT51 line of GPTA SSC1 clock input / output B ADC0 external multiplexer control output 0 ADC0 external multiplexer control output 1 ADC0 external multiplexer control output 2 In addition, P1.4 also serves as emergency shut-off input for certain I/O lines (e.g. GPTA related outputs). Table 2-2 Pin Definiti ons and Functions (cont’d) Symbol Pins I/O Pad Driver Class Power Supply Functions

General Device InformationPreliminary Data Sheet 12 V1.0, 2008-04 P2 I/O VDDP Port 2 Port 2 is a 14-bit bi-directional general- purpose I/O port which can be alternatively used for GPTA I/O, and interface for MLI0, MSC0 or SSC0/1. P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 TCLK0 IN32 / OUT32 TREADY0A IN33 / OUT33 SLSO03 SLSO13 TVALID0A IN34 / OUT34 TDATA0 IN35 / OUT35 RCLK0A IN36 / OUT36 RREADY0A IN37 / OUT37 RVALID0A IN38 / OUT38 RDATA0A IN39 / OUT39 MLI0 transmit channel clock output A line of GPTA MLI0 transmit channel ready input A line of GPTA SSC0 slave select output 3 SSC1 slave select output 3 MLI0 transmit channel valid output A line of GPTA MLI0 transmit channel data output A line of GPTA MLI0 receive channel clock input A line of GPTA MLI0 receive channel ready output A line of GPTA MLI0 receive channel valid input A line of GPTA MLI0 receive channel data input A line of GPTA Table 2-2 Pin Definiti ons and Functions (cont’d) Symbol Pins I/O Pad Driver Class Power Supply Functions

General Device InformationPreliminary Data Sheet 13 V1.0, 2008-04 P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 164 160 161 162 163 165 SLSO04 SLSO14 EN00 SLSO05 SLSO15 EN01 MRST1A SCLK1A FCLP0B MTSR1A SOP0B SLSI1 SDI0 SSC0 Slave Select output 4 SSC1 Slave Select output 4 MSC0 enable output 0 SSC0 Slave Select output 5 SSC1 Slave Select output 5 MSC0 enable output 1 SSC1 master receive input / slave transmit output A SSC1 clock input/output A MSC0 clock output B SSC1 master transmit out / slave receive input A MSC0 serial data output B SSC1 slave select input MSC0 serial data input Table 2-2 Pin Definiti ons and Functions (cont’d) Symbol Pins I/O Pad Driver Class Power Supply Functions

General Device InformationPreliminary Data Sheet 14 V1.0, 2008-04 P3 I/O VDDP Port 3 Port 3 is a 16-bit bi-directional general- purpose I/O port which can be alternatively used for ASC0/1, SSC0/1 and CAN lines. P3.0 P3.1 136 135 RXD0A TXD0A ASC0 receiver inp./outp. A ASC0 transmitter output A This pin is sampled at the rising edge of PORST. If this pin and the BYPASS input pin are both active, then oscillator bypass mode is entered. P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.14 P3.15 129 130 132 126 127 131 128 138 137 144 143 142 134 133 SCLK0 MRST0 MTSR0 SLSO00 SLSO10 SLSO01 SLSO11 SLSI0 SLSO02 SLSO12 SLSO06 TXD1A RXD1A REQ0 REQ1 RXDCAN0 RXD0B TXDCAN01) TXD0B RXDCAN1 RXD1B TXDCAN11) TXD1B SSC0 clock input/output SSC0 master receive input/ slave transmit output SSC0 master transmit output/slave receive input SSC0 slave select output 0 SSC1 slave select output 0 SSC0 slave select output 1 SSC1 slave select output 12) SSC0 slave select input SSC0 slave select output 2 SSC1 slave select output 2 SSC0 slave select output 6 ASC1 transmitter output A ASC1 receiver inp./outp. A External trigger input 0 External trigger input 1 CAN node 0 receiver input ASC0 receiver inp./outp. B CAN node 0 transm. output ASC0 transmitter output B CAN node 1 receiver input ASC1 receiver inp./outp. B CAN node 1 transm. output ASC1 transmitter output B Table 2-2 Pin Definiti ons and Functions (cont’d) Symbol Pins I/O Pad Driver Class Power Supply Functions

General Device InformationPreliminary Data Sheet 15 V1.0, 2008-04 P4 I/O VDDP Port 4 / Hardware Configuration Inputs P4.[3:0] HWCFG[3:0] Boot m ode and boot location inputs; inputs are latched with the rising edge of HDRST. During normal operation, Port 4 pins may be used as alternate functions for GPTA or system clock output. P4.0 P4.1 P4.2 P4.3 IN28 / OUT28 / IN29 / OUT29 / IN30 / OUT30 / IN31 / OUT31 / SYSCLK IN52 / OUT52 line of GPTA IN53 / OUT53 line of GPTA IN54 / OUT54 line of GPTA IN55 / OUT55 line of GPTA System Clock Output Table 2-2 Pin Definiti ons and Functions (cont’d) Symbol Pins I/O Pad Driver Class Power Supply Functions

General Device InformationPreliminary Data Sheet 16 V1.0, 2008-04 P5 I/O A2 VDDP Port 5 Port 5 is a 16-bit bi-directional general- purpose I/O port. In emulation, it is used as a trace port for OCDS Level 2 debug lines. In normal operation, it is used for GPTA I/O or the MLI0 interface. P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 OCDSDBG0 IN40 / OUT40 OCDSDBG1 IN41 / OUT41 OCDSDBG2 IN42 / OUT42 OCDSDBG3 IN43 / OUT43 OCDSDBG4 IN44 / OUT44 OCDSDBG5 IN45 / OUT45 OCDSDBG6 IN46 / OUT46 OCDSDBG7 IN47 / OUT47 OCDS L2 Debug Line 0 (Pipeline Status Sig. PS0) line of GPTA OCDS L2 Debug Line 1 (Pipeline Status Sig. PS1) line of GPTA OCDS L2 Debug Line 2 (Pipeline Status Sig. PS2) line of GPTA OCDS L2 Debug Line 3 (Pipeline Status Sig. PS3) line of GPTA OCDS L2 Debug Line 4 (Pipeline Status Sig. PS4) line of GPTA OCDS L2 Debug Line 5 (Break Qualification Line BRK0) line of GPTA OCDS L2 Debug Line 6 (Break Qualification Line BRK1) line of GPTA OCDS L2 Debug Line 7 (Break Qualification Line BRK2) line of GPTA Table 2-2 Pin Definiti ons and Functions (cont’d) Symbol Pins I/O Pad Driver Class Power Supply Functions

General Device InformationPreliminary Data Sheet 17 V1.0, 2008-04 P5.8 P5.9 P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 OCDSDBG8 RDATA0B OCDSDBG9 RVALID0B OCDSDBG10 RREADY0B OCDSDBG11 RCLK0B OCDSDBG12 TDATA0 OCDSDBG13 TVALID0B OCDSDBG14 TREADY0B OCDSDBG15 TCLK0 OCDS L2 Debug Line 8 (Indirect PC Addr. PC0) MLI0 receive channel data input B OCDS L2 Debug Line 9 (Indirect PC Addr. PC1) MLI0 receive channel valid input B OCDS L2 Debug Line 10 (Indirect PC Addr. PC2) MLI0 receive channel ready output B OCDS L2 Debug Line 11 (Indirect PC Addr. PC3) MLI0 receive channel clock input B OCDS L2 Debug Line 12 (Indirect PC Addr. PC04) MLI0 transmit channel data output B OCDS L2 Debug Line 13 (Indirect PC Addr. PC05) MLI0 transmit channel valid output B OCDS L2 Debug Line 14 (Indirect PC Address PC6) MLI0 transmit channel ready input B OCDS L2 Debug Line 15 (Indirect PC Address PC7) MLI0 transmit channel clock output B Table 2-2 Pin Definiti ons and Functions (cont’d) Symbol Pins I/O Pad Driver Class Power Supply Functions

General Device InformationPreliminary Data Sheet 18 V1.0, 2008-04 MSC0 Outputs FCLP0A FCLN0 SOP0A SON0 157 156 159 158 O O O O C VDDP LVDS MSC Clock and Data Outputs4) MSC0 Differential Driver Clock Output Positive A MSC0 Differential Driver Clock Output Negative MSC0 Differential Driver Serial Data Output Positive A MSC0 Differential Driver Serial Data Output Negative Table 2-2 Pin Definiti ons and Functions (cont’d) Symbol Pins I/O Pad Driver Class Power Supply Functions

General Device InformationPreliminary Data Sheet 19 V1.0, 2008-04 Analog Inputs AN[35:0] AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 ID – Analog Input Port The Analog Input Port provides altogether 36 analog input lines to ADC0 and FADC. AN[31:0]: ADC0 analog inputs [31:0] AN[35:32]: FADC analog differential inputs Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5 Analog input 6 Analog input 7 Analog input 8 Analog input 9 Analog input 10 Analog input 11 Analog input 12 Analog input 13 Analog input 14 Analog input 15 Analog input 16 Analog input 17 Analog input 18 Analog input 19 Analog input 20 Analog input 21 Analog input 22 Analog input 23 Analog input 24 Analog input 25 Analog input 26 Analog input 27 Analog input 28 Analog input 29 Analog input 30 Table 2-2 Pin Definiti ons and Functions (cont’d) Symbol Pins I/O Pad Driver Class Power Supply Functions

General Device InformationPreliminary Data Sheet 20 V1.0, 2008-04 AN31 AN32 AN33 AN34 AN35 I D – Analog input 31 Analog input 32 Analog input 33 Analog input 34 Analog input 35 System I/O TRST

114 I A2 3) VDDP JTAG Module Reset/Enable Input

TCK 115 I A2 3) VDDP JTAG Module Clock Input TDI 111 I A1 3) VDDP JTAG Module Serial Data Input TDO 113 O A2 VDDP JTAG Module Serial Data Output TMS 112 I A2 3) VDDP JTAG Module State Machine Control Input BRKIN 117 I/O A3 VDDP OCDS Break Input (Alternate Output)4)5) BRK OUT

116 I/O A3 VDDP OCDS Break Output (Alternate Input)4)5)

TRCLK 9O A 4 VDDP Trace Clock for OCDS_L2 Lines4) NMI 120 I A2 6)7) VDDP Non-Maskable Interrupt Input HDRST 122 I/O A2 8) VDDP Hardware Reset Input / Reset Indication Output PORST

121 I A2 6)7) VDDP Power-on Reset Input

BYPASS 119 I A1 3) VDDP PLL Clock Bypass Select Input This input has to be held stable during power- on resets. With BYPASS = 1, the spike filters in the HDRST, PORST and NMI inputs are switched off. TEST MODE

118 I A2 6)10) VDDP Test Mode Select Input

For normal operation of the TC1163/TC1164, this pin should be connected to high level. XTAL1 XTAL2 102 103 I O n.a. VDDOSC Oscillator/PLL/Clock Generator Input/Output Pins Table 2-2 Pin Definiti ons and Functions (cont’d) Symbol Pins I/O Pad Driver Class Power Supply Functions

General Device InformationPreliminary Data Sheet 21 V1.0, 2008-04 N.C. 21, –– – Not Connected These pins are reserved for future extension and must not be connected externally. Power Supplies VDDM 54 – – – ADC Analog Part Power Supply (3.3 V) VSSM 53 – – – ADC Analog Part Ground for VDDM VDDMF 24 – – – FADC Analog Part Power Supply (3.3 V) VSSMF 25 – – – FADC Analog Part Ground for VDDMF VDDAF 23 – – – FADC Analog Part Logic Power Supply (1.5 V) VSSAF 22 – – – FADC Analog Part Logic Ground for VDDAF VAREF0 52 – – – ADC Reference Voltage VAGND0 51 – – – ADC Reference Ground VFAREF 26 – – – FADC Reference Voltage VFAGND 27 – – – FADC Reference Ground VDDOSC 105 – – – Main Oscillator and PLL Power Supply (1.5 V) VDDOSC3 106 – – – Main Oscillator Power Supply (3.3 V) VSSOSC 104 – – – Main Oscillator and PLL Ground VDDFL3 141 – – – Power Supply for Flash (3.3 V) VDD 10, 68, 84, 99, 123, 153, 170 –– – Core Power Supply (1.5 V) Table 2-2 Pin Definiti ons and Functions (cont’d) Symbol Pins I/O Pad Driver Class Power Supply Functions

General Device InformationPreliminary Data Sheet 22 V1.0, 2008-04 VDDP 11, 69, 83, 100, 124, 154, 171, 139 –– – Port Power Supply (3.3 V) VSS 12, 70, 85, 101, 125, 155, 172, 140, –– – Ground 1) Not applicable to TC1163 2) The logical AND function of the two slave select outputs is available as a third alternate output function. 3) These pads are I/O pads with input only function. Its input characteristics are identical with the input characteristics as defined for class A pads. 4) In case of a power-fail condition (one or more pow er supply voltages drop below the specified voltage range), an undefined output driving level may occur at these pins. 5) Programmed by software as either break input or break output. 6) These pads are input only pads with input characteristics. 7) Input only pads with input spike filter. 8) Open drain pad with input spike filter. 9) The dual input reset system of TC1163/TC1164 assumes that the PORST reset pin is used for power on reset only. 10) Input only pads without input spike filter. Table 2-2 Pin Definiti ons and Functions (cont’d) Symbol Pins I/O Pad Driver Class Power Supply Functions

General Device InformationPreliminary Data Sheet 23 V1.0, 2008-04 Table 2-3 List of Pull-up/Pull-do wn Reset Behavior of the Pins Pins PORST =0 P O R S T =1 All GPIOs, TDI, TMS, TDO Pull-up HDRST Drive-low Pull-up BYPASS Pull-up High-impedance TRST, TCK High-impedance Pull-down TRCLK High-impedance BRKIN, BRKOUT, TESTMODE Pull-up NMI, PORST Pull-down

Functional DescriptionPreliminary Data Sheet 24 V1.0, 2008-04

3 Functional Description

Chapter 3 provides an overview of the TC1163/TC1164 functional description.

3.1 System Architecture and On-Chip Bus Systems

The TC1163/TC1164 has two independent on-chip buse s (see also TC1163/TC1164 block diagram on Page 2-6):

• Local Memory Bus (LMB)
• System Periphe ral Bus (SPB) The LMB Bus connects the CPU local resources for data and instruction fetch. The Local Memory Bus interconnects t he memory units and functiona l units, such as CPU and PMU. The main target of the LMB bus is to support device s with fast response times, optimized for speed. This al lows the DMI and PMI fast access to local memory and reduces load on the FPI bus. The Tricore system itself is located on LMB bus. The Local Memory Bus is a syn chronous, pipelined, split bu s with variable block size transfer support. It supports 8- , 16-, 32- and 64-bit singl e transactions and variable length 64-bit block transfers. The SPB Bus is mainly governed by the PCP and is accessible to the CPU via the LMB Bus bridge. The System Peripheral Bus (SPB Bus) in TC1163/TC1164 is an on-chip FPI Bus. The FPI Bus interconnects the functional units of the TC1163/TC1164, such as the DMA and on-chip peripher al components. The FPI Bus is designed to be quick to be acquired by on-chip functional units, and quick to transfer data. The low setup overhead of the FPI Bus access protocol guarantees fast FPI Bus acquisition, which is required for time-critical applications.The FPI Bus is desi gned to sustain high tr ansfer rates. For example, a peak transfer rate of up to 320 Mbyte/s can be achieved with a 80 MHz bus clock and 32-bit data bus. Multiple data transfers per bus arbitration cycle allow the FPI Bus to operate at close to its peak bandwidth. Both the LMB Bus and the SPB Bus runs at full CPU speed. The maximum CPU speed is 80 MHz. Additionally, two simplified bus interfaces ar e connected to and controlled by the DMA Controller:
• D M A B u s
• SMIF Interface

Functional DescriptionPreliminary Data Sheet 25 V1.0, 2008-04

3.2 On-Chip Memories

As shown in the TC1163/TC1164 block diagram on Page 2-6, some of the TC1163/TC1164 units provide on-chip memories that ar e used as program or data memory.

• Program memory in PMU – 16 Kbyte Boot ROM (BROM) – 1024 Kbyte Program Flash (PFlash)
• Program memory in PMI – 8 Kbyte Scratch-Pad RAM (SPRAM) – 8 Kbyte Instruction Cache (ICACHE)
• Data memory in PMU – 16 Kbyte Data Flash (DFlash) – 8 Kbyte Overlay RAM (OVRAM)
• Data memory in DMI – 40 Kbyte Local Data RAM (LDRAM)
• Memory of PCP2 – 12 Kbyte Code Memory (CMEM) wi th parity error protection – 8 Kbyte Parameter RAM (PRAM) wi th parity error protection
• On-chip SRAM with par ity error protection Features of Program Flash
• 1024 Kbyte on-chip program Flash memory
• Usable for instruction code or constant data storage
• 256-byte program interface – 256 bytes are programmed into PF LASH page in one step/command
• 256-bit read interface – Transfer from PFLASH to CPU/PMI by four 64-bit single cycle burst transfers
• Dynamic correction of single-b it errors during read access
• Detection of double-bit errors
• Fixed sector architecture – Eight 16 Kbyte, one 12 8 Kbyte, one 256 Kbyte and one 512 Kbyte sectors – Each sector separately erasable – Each sector separately write-protectable
• Configurable read protecti on for complete PFLASH wit h sophisticated read access supervision, combined with write protection for complete PFLASH (protection against “Trojan horse” software)
• Configurable write pr otection for each sector – Each sector separately write-protectable – With capability to be re-programmed – With capability to be lo cked forever (OTP)
• Password mechanism for temporary disabling of write and read protection
• On-chip generation of programming voltage

Functional DescriptionPreliminary Data Sheet 26 V1.0, 2008-04

• JEDEC-standard based command sequences for PFLASH control – Write state machine controls programming and erase operations – Status and error reporting by status flags and interrupt
• Margin check for detection of problematic PFLASH bits Features of Data Flash
• 16 Kbyte on-chip data Flash memory , organized in two 8 Kbyte banks
• Usable for data storage wit h EEPROM functionality
• 128 Byte of pr ogram interface – 128 bytes are programmed into one DFLASH page by one step/command
• 64-bit read interface (no burst transfers)
• Dynamic correction of single-b it errors during read access
• Detection of double-bit errors
• Fixed sector architecture – Two 8 Kbyte banks/sectors – Each sector separately erasable
• Configurable read protecti on (combined with write protection) for complete DFLASH together with PFLASH read protection
• Password mechanism for temporary disabling of write and read protection
• Erasing/programm ing of one bank possible while reading data from the other bank
• Programming of one ban k while erasing the other bank possible
• On-chip generation of programming voltage
• JEDEC-standard based command sequences for DFLASH control – Write state machine controls programming and erase operations – Status and error reporting by status flags and interrupt
• Margin check for detection of problematic DFLASH bits

Functional DescriptionPreliminary Data Sheet 27 V1.0, 2008-04

3.3 Memory Maps

This chapter gives an overview of the TC1163/TC1164 memory map and describes the address locations and access possibilities for the units, memories, and reserved areas as “seen” from different on-chip buses’ (SPB and LMB) point of view.

3.3.1 Architectural Address Map

Table 3-1 shows the overall architectural address map as defined for the TriCore and as implemented in TC1163/TC1164. Table 3-1 TC1163/TC1164 Ar chitectural Address Map Seg- ment Contents Size Description 0-7 Global 8 x 256 Mbyte Reserved (MMU space); cached

8 Global

256 Mbyte Reserved (246 Mbyte); PMU, Boot ROM;

9 Global

256 Mbyte FPI space; cached

10 Global

256 Mbyte Reserved (246 Mbyt e), PMU, Boot ROM; non-

11 Global

256 Mbyte FPI space; non-cached

12 Local LMB

256 Mbyte Reserved; bottom 4 Mbyte visible from FPI bus

in segment 14; cached

13 DMI 64 Mbyte Local Data Memory RAM; non-cached

PMI 64 Mbyte Local Code Memory RAM; non-cached EXT_PER 96 Mbyte Reserved; non-cached EXT_EMU 16 Mbyte Reserved; non-cached BOOTROM 16 Mbyte B oot ROM space, Boot ROM mirror; non-cached

Functional DescriptionPreliminary Data Sheet 28 V1.0, 2008-04

14 EXTPER 128 Mbyte Reserved;

non-speculative; non-cached; no execution CPU[0 ..15] image region 16 x 8 Mbyte Non-speculative; non-cached; no execution

15 LMB_PER

INT_PER 256 Mbyte CSFRs of CPUs[0 ..15]; LMB & FPI Peripheral Space; non-speculative; non-cached; no execution Table 3-1 TC1163/TC1164 Ar chitectural Address Map (cont’d) Seg- ment Contents Size Description

Functional DescriptionPreliminary Data Sheet 29 V1.0, 2008-04

3.3.2 How to Read the Address Maps

The bus-specific address maps describe how the different bus master devices react on accesses to on-chip me mories and modules, and which address ranges are valid or invalid for the corresponding buses. The FPI Bus address map shows the system add resses from the point of view of the SPB master agents. SPB master agents are PCP2 and OCDS, and DMA. The LMB address map shows the system addresses from the point of view of the LMB master agents. LMB master agents are PMI and DMI. Table 3-2 defines the acronyms and other term s that are used in the address maps (Table 3-3 to Table 3-5). Table 3-2 Definition of Acronyms and Terms Term Description …BE Means “Bus error” generation. …BET Means “Bus error & trap” generation. SPBBE A bus access is terminated with a bus error on the SPB. SPBBET A bus access is term inated with a bus error on the SPB and a DSE trap (read access) or DAE trap (write access). LMBBE A bus access is terminated with a bus error on the LMB. LMBBET A bus access is terminated with a bus error on the LMB and a DSE trap (read access) or DAE trap (write access). access A bus access is a llowed and is executed. ignore A bus access is ignored and is not executed. No bus error is generated. trap A DSE trap (read access) or DAE trap (write access) is generated.

32 Only 32-bit word bus access es are permitted to that

register/address range. nE A bus access generates no bus error, although the bus access points to an undefined address or address range. This is valid e.g. for CPU accesses (MTCR/MFCR) to undefined addresses in the CSFR range.

Functional DescriptionPreliminary Data Sheet 30 V1.0, 2008-04

3.3.3 Contents of the Segments

This section summarizes the contents of the segments. Segments 0-7 These segments are reserved segments in the TC1163/TC1164. Segment 8 From the SPB point of view (PCP, DMA and Cerberus), this memory segment allows accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM). From the CPU point of view (PMI and DMI), this memo ry segment allows cached accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM). Segment 9 This memory segment is reserved in the TC1163/TC1164. Segment 10 From the SPB point of view (PCP, DMA and Cerberus), this memory segment allows accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM). From the CPU point of view (PMI and DMI) , this memory segment allows non-cached accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM). Segment 11 This memory segment is reserved in the TC1163/TC1164. Segment 12 From the SPB point of view (PCP, DMA, and Cerberus), this memory segment is reserved in the TC1163/TC1164. From the CPU point of view (PMI and DMI), this memo ry segment allows cached accesses to the PMU memory, OVRAM. Segment 13 From the SPB point of view (PCP, DMA and Cerberus), this memory segment is reserved in the TC1163/TC1164. From the CPU point of view (PMI and DMI) , this memory segment allows non-cached accesses to the PMI scratch-pad RAM, r ead access to the boot ROM and test ROM (BROM and TROM) and the DMI memories (LDRAM).

Functional DescriptionPreliminary Data Sheet 31 V1.0, 2008-04 Segment 14 From the SPB point of view (PCP, DMA and Cerberus), this memory segment allows accesses to the PMU Overlay memory (OVR AM), the DMI Local Data RAM (LDRAM), and the PMI scratch-pad RAM (SPRAM). From the CPU point of view (PMI and DMI), this memory segment is reserved in the TC1163/TC1164. Segment 15 From the SPB point of view (PCP, DMA and Cerberus), this memory segment allows accesses to all SFRs and CSFRs, the PCP memories, and the MLI transfer windows. From the CPU point of view (PMI and DMI), this memory segment allows accesses to all SFRs and CSFRs, the PCP memories, and the MLI transfer windows.

Functional DescriptionPreliminary Data Sheet 32 V1.0, 2008-04

3.3.4 Address Map of the FPI Bus System

Table 3-3 and Table 3-4 shows the address maps of the FPI Bus System.

3.3.4.1 Segments 0 to 14

Table 3-3 shows the address maps of segments 0 to 14 as it is seen from the SPB bus masters PCP, DMA and OCDS. Table 3-3 SPB Address Map of Segment 0 to 14 Seg- ment Address Range Size Description Access Type Read Write 0-7 0000 0000 H - 0000 0007H 8 byte Reserved (virtual address space) MPN trap MPN trap 0000 0008H - 7FFF FFFFH 8 × 256 Mbyte SPBBE SPBBE

Functional DescriptionPreliminary Data Sheet 33 V1.0, 2008-04 8 8000 0000 H - 800F FFFFH

1 Mbyte Program Flash (PFLASH) access access 1)

≈ 0.5 Mbyte Reserved access 2) access1)2) 8017 8000H - 807F FFFFH

6.5 Mbyte Reserved LMBBE &

Reserved LMBBE & SPBBE LMBBE 8FE0 0000 H - 8FE0 1FFFH

8 Kbyte Data Flash (DFLASH)

access access 1) 8FE0 2000H - 8FE0 3FFFH

8 Kbyte Reserved access 2) access1)2)

48 Kbyte Reserved LMBBE &

access access 1) 8FE1 2000H - 8FE1 3FFFH

1 Mbyte Reserved LMBBE &

16 Kbyte Boot ROM (BROM) access

Table 3-3 SPB Address Map of Segment 0 to 14 (cont’d) Seg- ment Address Range Size Description Access Type Read Write

Functional DescriptionPreliminary Data Sheet 34 V1.0, 2008-04

10 A000 0000 H -

≈ 0.5 Mbyte Reserved access 2) access1)2) A017 8000H - A07F FFFFH Reserved LMBBE & SPBBE LMBBE AFE0 0000 H - AFE0 1FFFH access access 1) AFE0 2000H - AFE0 3FFFH access access 1) AFE1 2000H - AFE1 3FFFH

11 B000 0000 H -

12 C000 0000

8 Kbyte Overlay memory

(OVRAM) SPBBE SPBBE C000 2000H - CFFF FFFFH ≈ 256 Mbyte Reserved SPBBE SPBBE Table 3-3 SPB Address Map of Segment 0 to 14 (cont’d) Seg- ment Address Range Size Description Access Type Read Write

Functional DescriptionPreliminary Data Sheet 35 V1.0, 2008-04

13 D000 0000 H -

40 Kbyte DMI Local Data RAM

(LDRAM) SPBBE SPBBE D000 A000H - D3FF FFFFH ≈ 64 Mbyte Reserved SPBBE SPBBE D400 0000H - D400 1FFFH

8 Kbyte PMI Scratch-Pad RAM

(SPRAM) SPBBE SPBBE D400 2000H - D7FF FFFFH ≈ 64 Mbyte Reserved SPBBE SPBBE D800 0000H - DEFF FFFFH 112 Mbyte Reserved SPBBE SPBBE DF00 0000 H - DFFF FFEFH ≈ 16 Mbyte Reserved (for Boot Rom) SPBBE SPBBE DFFF FFF0H - DFFF FFFFH 16 byte microROM SPBBE SPBBE Table 3-3 SPB Address Map of Segment 0 to 14 (cont’d) Seg- ment Address Range Size Description Access Type Read Write

Functional DescriptionPreliminary Data Sheet 36 V1.0, 2008-04

14 E000 0000 H -

128 MB Reserved LMBBE LMBBE

(OVRAM) access access E800 2000H - E83F FFFFH ≈ 4 Mbyte Reserved LMBBE LMBBE E840 0000H - E840 9FFFH (LDRAM) access access E840 A000H - E840 DFFFH

16 Kbyte Reserved access 2) access2)

≈ 1 Mbyte Reserved LMBBE LMBBE E850 0000H - E850 1FFFH (SPRAM) access access E850 2000H - E850 3FFFH

8 Kbyte Reserved access 2) access2)

≈ 1 Mbyte Reserved LMBBE LMBBE E860 C000H - EFFF FFFFH ≈ 122 Mbyte Reserved LMBBE LMBBE

15 F000 0000 H -

1) Only applicable when writing Flash command sequences. 2) Read and write accesses to this address range will not generate any traps. Table 3-3 SPB Address Map of Segment 0 to 14 (cont’d) Seg- ment Address Range Size Description Access Type Read Write

Functional DescriptionPreliminary Data Sheet 37 V1.0, 2008-04

3.3.4.2 Segment 15

Table 3-4 shows the address map of segment 15 as seen fr om the SPB bus masters PCP, DMA and OCDS. Please note that access in Table 3-4 means only that an access to an address within the defined address range is not automatically incorrect or ignored. If an access is really addressing a correct address, it can be found in the detailed tables in the TC116x User’s Manual, Register Overview’s chapter. Table 3-4 SPB Address Map of Segment 15 Unit Address Range Size Access Type Read Write System Control Unit (SCU) and Watchdog Timer (WDT) F000 0000H - F000 00FFH 256 byte access access System Peripheral Bus Control Unit (SBCU) F000 0100 H - F000 01FFH 256 byte access access System Timer (STM) F000 0200 H - F000 02FFH 256 byte access access Reserved F000 0300 H - F000 03FFH – SPBBE SPBBE On-Chip Debug Support (Cerberus) F000 0400 H - F000 04FFH 256 byte access access Reserved F000 0500 H - F000 07FFH – SPBBE SPBBE MicroSecond Bus Controller 0 (MSC0) F000 0800H - F000 08FFH 256 byte access access Reserved F000 0900 H - F000 09FFH – SPBBE SPBBE Async./Sync. Serial Interface 0 (ASC0) F000 0A00H - F000 0AFFH 256 byte access access Async./Sync. Serial Interface 1 (ASC1) F000 0B00 H - F000 0BFFH 256 byte access access Port 0 F000 0C00 H - F000 0CFFH 256 byte access access Port 1 F000 0D00 H - F000 0DFFH 256 byte access access Port 2 F000 0E00 H - F000 0EFFH 256 byte access access

Functional DescriptionPreliminary Data Sheet 38 V1.0, 2008-04 Port 3 F000 0F00 H - F000 0FFFH 256 byte access access Port 4 F000 1000 H - F000 10FFH 256 byte access access Port 5 F000 1100 H - F000 11FFH 256 byte access access Reserved F000 1200 H - F000 12FFH – SPBBE SPBBE Reserved F000 1300 H - F000 13FFH – SPBBE SPBBE Reserved F000 1400 H - F000 14FFH – SPBBE SPBBE Reserved F000 1500 H - F000 15FFH – SPBBE SPBBE Reserved F000 1600 H - F000 16FFH – SPBBE SPBBE Reserved F000 1700 H - F000 17FFH – SPBBE SPBBE General Purpose Timer Array 0 (GPTA0) F000 1800H - F000 1FFFH 8 × 256 byte access access Reserved F000 2000 H - F000 27FFH – SPBBE SPBBE Reserved F000 2800 H - F000 2FFFH – SPBBE SPBBE Reserved F000 3000 H - F000 3BFFH – SPBBE SPBBE Direct Memory Access Controller (DMA) F000 3C00H - F000 3EFFH 3 × 256 byte access access Reserved F000 3F00 H - F000 3FFFH – SPBBE SPBBE MultiCAN Controller (CAN) F000 4000 H - F000 5FFFH

8 Kbyte access 1) access1)

Table 3-4 SPB Address Map of Segment 15 (cont’d) Unit Address Range Size Access Type Read Write

Functional DescriptionPreliminary Data Sheet 39 V1.0, 2008-04 Reserved F000 6000 H - F003 FFFFH – SPBBE SPBBE Reserved F004 0000 H - F004 3EFFH – SPBBE SPBBE PCP Registers F004 3F00 H - F004 3FFFH 256 byte access access Reserved F004 4000 H - F004 FFFFH – SPBBE SPBBE PCP Data Memory (PRAM) F005 0000 H - F005 1FFFH

8 Kbyte nE, 32 nE, 32

– SPBBE SPBBE PCP Code Memory (PCODE) F006 0000 H - F006 2FFFH Kbyte nE, 32 nE, 32 Reserved F006 3000 H - F007 FFFFH – SPBBE SPBBE Reserved F008 0000 H - F00F FFFFH – SPBBE SPBBE Reserved F010 0000 H - F010 00FFH – SPBBE SPBBE Synchronous Serial Interface 0 (SSC0) F010 0100H - F010 01FFH 256 byte access access Synchronous Serial Interface 1 (SSC1) F010 0200 H - F010 02FFH 256 byte access access Fast Analog-to-Digital Converter (FADC) F010 0300 H - F010 03FFH 256 byte access access Analog-to-Digital Converter 0 (ADC0) F010 0400 H - F010 05FFH 2 × 256 byte access access Reserved F010 0600 H - F010 07FFH – SPBBE SPBBE Reserved F010 0800 H - F010 9FFFH – SPBBE SPBBE Table 3-4 SPB Address Map of Segment 15 (cont’d) Unit Address Range Size Access Type Read Write

Functional DescriptionPreliminary Data Sheet 40 V1.0, 2008-04 Reserved F010 A000 H - F010 BFFFH – SPBBE SPBBE Micro Link Interface 0 (MLI0) F010 C000 H - F010 C0FFH 256 byte access access Reserved F010 C100 H - F010 C1FFH 256 byte access 2) access2) Memory Checker (MCHK) F010 C200 H - F010 C2FFH 256 byte access access Reserved F010 C300 H - F01D FFFFH – SPBBE SPBBE MLI0 Small Transfer Windows F01E 0000 H - F01E 7FFFH 4 × 8 Kbyte access access Reserved F01E 8000 H - F01E FFFFH 4 × 8 Kbyte access2) access2) Reserved F01F 0000 H - F01F FFFFH – SPBBE SPBBE MLI0 Large Transfer Windows F020 0000 H - F023FFFFH 4 × 64 Kbyte access access Reserved F024 0000 H - F027 FFFFH 4 × 64 Kbyte access2) access2) Reserved F028 0000 H - F7E0 FEFFH – SPBBE SPBBE CPU CPU Slave Interface Registers (CPS) F7E0 FF00H - F7E0 FFFFH 256 byte access access CPU Core SFRs & GPRs F7E1 0000 H - F7E1 FFFFH Kbyte access access Reserved F7E2 0000 H - F7FF FFFFH – SPBBE SPBBE Reserved F800 0000 H - F800 03FFH – SPBBE SPBBE Reserved F800 0400 H - F800 04FFH – LMBBE & SPBBE LMBBE Table 3-4 SPB Address Map of Segment 15 (cont’d) Unit Address Range Size Access Type Read Write

Functional DescriptionPreliminary Data Sheet 41 V1.0, 2008-04 Program Memory Unit (PMU) F800 0500 H - F800 05FFH 256 byte access access Reserved F800 0600 H - F800 0FFFH – LMBBE & SPBBE LMBBE Flash Register F800 1000 H - F800 23FFH

5 Kbyte access access

– LMBBE & SPBBE LMBBE Reserved F801 0100 H - F801 01FFH – LMBBE & SPBBE LMBBE Reserved F801 0200 H - F87F F9FFH – LMBBE & SPBBE LMBBE Reserved F87F FA00 H - F87F FAFFH – LMBBE & SPBBE LMBBE Reserved F87F FB00 H - F87F FBFFH – LMBBE & SPBBE LMBBE CPU DMI Registers F87F FC00 H - F87F FCFFH 256 byte access access PMI Registers F87F FD00 H - F87F FDFFH 256 byte access access Local Memory Bus Control Unit (LBCU) F87F FE00 H - F87F FEFFH 256 byte access access LFI Bridge F87F FF00 H - F87F FFFFH 256 byte access access Reserved F880 0000 H - FFFF FFFFH – LMBBE & SPBBE LMBBE 1) For TC1163, read and write accesses to this address range will not generate any traps. 2) Read and write accesses to this address range will not generate any traps. Table 3-4 SPB Address Map of Segment 15 (cont’d) Unit Address Range Size Access Type Read Write

Functional DescriptionPreliminary Data Sheet 42 V1.0, 2008-04

3.3.5 Address Map of the Local Memory Bus (LMB)

Table 3-5 shows the address map as seen from the LMB bus masters (PMI and DMI). Table 3-5 LMB Address Map Seg- ment Address Range Size Description Action Read Write 0-71) 0000 0000H - 0000 0007H 8 byte Reserved (virtual address space) MPN trap MPN trap 0000 0008H - 7FFF FFFFH 8 × 256 Mbyte SPBBET SPBBE 81) 8000 0000H - 800F FFFFH

1 Mbyte Program Flash (PFLASH) access access 2)

≈ 0.5 Mbyte Reserved access 3) access2)3) 8017 8000H - 807F FFFFH

6.5 Mbyte Reserved LMBBET LMBBET

access access 2) 8FE0 2000H - 8FE0 3FFFH

8 Kbyte Reserved access 3) access2)3)

48 Kbyte Reserved LMBBET LMBBET

access access 2) 8FE1 2000H - 8FE1 3FFFH

1 Mbyte Reserved LMBBET LMBBET

256 Kbyte Reserved

624 Kbyte Reserved

Functional DescriptionPreliminary Data Sheet 43 V1.0, 2008-04 91) 9000 0000H - 9FFF FFFFH 256 Mbyte Reserved SPBBET SPBBE 4) A000 0000H - A00F FFFFH ≈ 0.5 Mbyte Reserved access 3) access2)3) A017 8000H - A07F FFFFH access access 2) AFE0 2000H - AFE0 3FFFH access access 2) AFE1 2000H - AFE1 3FFFH 114) B000 0000H - BFFF FFFFH 256 Mbyte Reserved SPBBET SPBBE Table 3-5 LMB Address Map (cont’d) Seg- ment Address Range Size Description Action Read Write

Functional DescriptionPreliminary Data Sheet 44 V1.0, 2008-04 121) C000 0000H - C000 1FFFH (OVRAM) access access C000 2000H - CFFF FFFFH 256 Mbyte Reserved LMBBET LMBBET 4) D000 0000H - D000 9FFFH (LDRAM) access SPBBE access SPBBE D000 A000H - D000 DFFFH

16 Kbyte Reserved access

SPBBE5) access SPBBE D000 E000H - D3FF FFFFH

64 Mbyte Reserved LMBBET LMBBET

(SPRAM) access access D400 2000H - D400 3FFFH

8 Kbyte Reserved access 3) access3)

≈ 64 Mbyte Reserved LMBBET LMBBET D800 0000H - DEFF FFFFH 112 Mbyte Reserved DF00 0000 H - DFFF FFEFH

16 Mbyte Reserved (for Boot Rom)

144) E000 0000H - E7FF FFFFH 128 Mbyte Reserved LMBBET LMBBET E800 0000 H - EFFF FFFFH 128 Mbyte Reserved LMBBET LMBBET Table 3-5 LMB Address Map (cont’d) Seg- ment Address Range Size Description Action Read Write

Functional DescriptionPreliminary Data Sheet 45 V1.0, 2008-04 address map (see Table 3-5) Reserved areas give an bus error. SPBBET SPBBE F800 0000 H - F800 03FFH

1 Kbyte Reserved LMBBET LMBBET

256 byte Reserved LMBBET LMBBET F800 0500H - F800 05FFH 256 byte Program Memory Unit (PMU) access access F800 0600H - F800 0FFFH ≈ 2 Kbyte Reserved LMBBET LMBBET F800 1000H - F800 23FFH

5 Kbyte Flash Registers access access

≈ 8 Mbyte Reserved LMBBET LMBBET F87F FC00H - F87F FCFFH 256 byte Data Memory Interface Unit access access F87F FD00H - F87F FDFFH 256 byte Program Memory Interface Unit access access F87F FE00H - F87F FEFFH 256 byte LBCU register space access access F87F FF00H - F87F FFFFH 256 byte LFI Bus Bridge access access F880 0000H - FFFF FFFFH ≈ 119 Mbyte Reserved LMBBET LMBBET 1) Cached area 2) Only applicable when writing Flash command sequences 3) Read and write accesses to this address range will not generate any traps. 4) Non-cached area 5) If accessible, read and write accesses to this address range will not generate any traps. Table 3-5 LMB Address Map (cont’d) Seg- ment Address Range Size Description Action Read Write

Functional DescriptionPreliminary Data Sheet 46 V1.0, 2008-04

3.4 Memory Protection System

The TC1163/TC1164 memory protection system specifie s the addressable range and read/write permissions of memory segments available to the current executing task. The memory protection system controls the position and range of addressable segments in memory. It also controls the types of read and write opera tions allowed within addressable memory segments. Any illegal memory access is detected by the memory protection hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the error. Thus, the memory protection system protects critical system functions against both software and hardware errors. The memory protection hardware can also generate signals to the Debug Unit to facilitate tracing illegal memory accesses. There are two Memory Protection Register Sets in the TC11 63/TC1164, numbered 0 and 1, which specify memory protection ranges and permissions for code and data. The PSW.PRS bit field determines which of these is the set currently in use by the CPU. As the TC1163/TC1164 uses a Harvard-style memory architecture, each Memory Protection Register Set is broken down into a Data Protection Register Set and a Code Protection Register Set. Ea ch Data Protection Register Set can spec ify up to four address ranges to receive a particular protection modes. Each Code Protection Register Set can specify up to two address ranges to receive a particular protection modes. Each Data Protection Register Sets and Code Protection Register Sets determines the range and protection modes for a separate memory area. Each set contains a pair of registers which determine th e address range (the Data Segment Protection Registers and Code Segment Protection Registers) and one register (Data Protection Mode Register) which determines th e memory access modes that applies to the specified range.

3.5 Peripheral Control Processor

The Peripheral Control Processor (PCP2) in the TC1163/T C1164 performs tasks that would normally be performed by the combination of a DMA controller and its supporting CPU interrupt service routines in a trad itional computer system . It could easily be considered as the host processor’s first line of defence as an interrupt-handling engine. The PCP can unload the CPU from having to service time-critical interrupts. This provides many benefits, including:

• Avoiding large interrupt-driv en task context-switching latencies in the host processor
• Reducing the cost of interrupts in terms of processor register and memory overhead
• Improving the responsiveness of interrupt se rvice routines to data-capture and data- transfer operations
• Easing the implementation of multitasking operating systems The PCP2 has an architecture that efficiently supports DMA-type transactions to and from arbitrary devices and memory addresses within the TC1163/TC1164 and also has reasonable stand-alone computational capabilities.

Functional DescriptionPreliminary Data Sheet 47 V1.0, 2008-04 The PCP2 in the TC1163/TC1164 contains an impr oved version of the TC1775’s PCP with the following enhancements:

• Optimized context switching
• Support for ne sted interrupts
• Enhanced instruction set
• Enhanced instructio n execution speed
• Enhanced interrupt queueing The PCP2 is made up of several modular blocks as follows (see Figure 3-1):
• PCP Processor Core
• Code Memory (CMEM)
• Parameter Memory (PRAM)
• PCP Interrupt Control Unit (PICU)
• PCP Service Request Nodes (PSRN)
• System bus interface to the Flexib le Peripheral Interface (FPI Bus) Figure 3-1 PCP2 Block Diagram MCB06135 PCP Processor Core PCP Service Req. Nodes PSRNs PCP Interrupt Control Unit PICU Parameter Memory PRAM Code Memory CMEM FPI-Interface PCP Interrupt Arbitration Bus CPU Interrupt Arbitration Bus FPI Bus

Functional DescriptionPreliminary Data Sheet 48 V1.0, 2008-04 Table 3-6 PCP2 Instruction Set Overview Instruction Group Description DMA primitives Efficient DM A channel implementation Load/Store Transfer data between PRAM or FPI memory and the general purpose registers, as well as move or exchange values between registers Arithmetic Add, subtract , compare and complement Divide/Multiply Divide and multiply Logical And, Or, Exclusive Or, Negate Shift Shift right or left, rotate right or left, prioritize Bit Manipulation Set, clear, insert and test bits Flow Control Jump conditionally, jump long, exit Miscellaneous No operation, Debug

Functional DescriptionPreliminary Data Sheet 49 V1.0, 2008-04

3.6 DMA Controller and Memory Checker

The DMA Controller of the TC1163/TC1164 transfers data from data source locations to data destination locations without intervention of the CPU or other on-chip devices. One data move operation is co ntrolled by one DM A channel. Eight DMA channels are provided in one DMA Sub-Bloc k. The Bus Switch provides the connection of the DMA Sub-Block to the two FPI Bus interfaces and an MLI bus interface. In the TC1163/TC1164, the FPI Bus interfaces are connected to the Syst em Peripheral Bus and the DMA Bus. The third specific bus in terface provides a connection to Micro Link Interface modules (two MLI modules in the TC1163/TC1164) a nd other DMA-related devices (Memory Checker module in the TC1163/TC1164). Clock control, address decoding, DMA request wiring, and DMA interrupt service re quest control are implementation-specific and managed outside the DMA controller kernel. Figure 3-2 shows the implementation details and interconnections of the DMA module. Figure 3-2 DMA Contro ller Block Diagram Interrupt Request Nodes TC1163/TC1164 DMA Block Diagram Clock Control fDMA SR[15:0] DMA Controller Arbiter/ Switch Control Bus Switch FPI Bus Interfac e 0 FPI Bus Interfac e 1 ML I In te rface System Periphera Bus DMA Bus DMA Requests of On-chip Periph. Units Address Decoder DMA Interrupt Control CH0n_OUT DMA Channels 00-07 DMA Sub-Block 0 Request Selection/ Arbitration Transaction Control Unit Memory Checker MLI0

Functional DescriptionPreliminary Data Sheet 50 V1.0, 2008-04

Features

• 8 independent DMA channels – 8 DMA channels in the DMA Sub-Block – Up to 8 selectable reque st inputs per DMA channel – 2-level programmable priority of DMA channels within the DMA Sub-Block – Software and hard ware DMA request – Hardware requests by selected on-c hip peripherals and external inputs
• Programmable priority of the DMA Sub-Blocks on the bus interfaces
• Buffer capability for move actions on the buses (at least 1 move per bus is buffered).
• Individually programm able operation modes for each DMA channel – Single Mode: stops and disables DMA channel after a predefined number of DMA transfers – Continuous Mode: DMA channel remain s enabled after a predefined number of DMA transfers; DMA transaction can be repeated. – Programmable address modification
• Full 32-bit addressing capab ility of each DMA channel – 4 Gbyte address range – Support of circular buffer addressing mode
• Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit
• Micro Link bus interface support
• Register set for each DMA channel – Source and destination address register – Channel control and status register – Transfer count register
• Flexible interrupt g eneration (the service request node logic for the MLI channels is also implemented in the DMA module)
• All buses connected to the DMA module must work at the same frequency.
• Read/write requests of the System Bus si de to the peripherals on DMA Bus are bridged to the DMA Bus (only the DMA is the master on the DMA bus), allowing easy access to these peripherals by PCP and CPU Memory Checker The Memory Checker Module (MCHK) makes it possible to check the data consistency of memories. Any SPB bus master may access the memory checker. It is preferable the DMA does it as described her eafter. It uses DMA 8-bit, 16-bit, or 32-bit moves to read from the selected address ar ea and to write t he value read in a me mory checker input register. With each write ope ration to the memory checker input register, a polynomial checksum calculation is trigger ed and the result of the ca lculation is stored in the memory checker result register. The memory checker uses the standard Ethernet polynomial, which is given by: G 32 = x32+ x26+ x23+ x22+ x16+ x12+ x11+ x10+ x8+ x7+ x5+ x4+ x2+ x +1

Functional DescriptionPreliminary Data Sheet 51 V1.0, 2008-04 Note: Although the polynomial a bove is used for generation, the generation algorithm differs from the one that is used by the Ethernet protocol.

3.7 Interrupt System

The TC1163/TC1164 inte rrupt system provides a flexib le and time-efficient means of processing interrupts. An interrupt request can be serviced either by the CPU or by the Peripheral Control Processo r (PCP). These units are ca lled “Service Providers”. Interrupt requests are called “Service Requests” rather than “Interrupt Requests” in this document because they can be serviced by either Service Providers. Each peripheral in the TC1163/TC1164 can generate service requests. Additionally, the Bus Control Units, the Debug Unit, the PC P, and even the CPU itself can generate service requests to either of the two Service Providers. As shown in Figure 3-3, each TC1163/TC1164 unit that can generate service requests is connected to one or mult iple Service Request Nodes (SRN). Each SRN contains a Service Request Control Register mod_SRCx, where “mod” is the identifier of the service requesting unit and “x” an optional index. Two arbitration buses connect the SRNs with two Interrupt Control Units, which handle interrupt arbitration among competing interrupt service requests, as follows:

• The Interrupt Control Unit (ICU) arbi trates service reque sts for the CPU and administers the CPU Interrupt Arbitration Bus.
• The Peripheral Interrupt Cont rol Unit (PICU) arbitrates service requests for the PCP and administers the PCP Interrupt Arbitration Bus. The PCP can make service reque sts directly to itself (via the PICU), or it can make service requests to the CPU. The Debug Unit can generate service requests to the PCP or the CPU. The CPU can make service requests directly to itself (via the ICU), or it can make service requests to the PCP. The CPU Service Request Nodes are activated through software. Depending on the selected system clock frequency fSYS, the number of fSYS clock cycles per arbitration cycle must be selected as follows:
• fSYS < 60 MHz: ICR.CONECYC = 1 and PCP_ICR.CONECYC = 1
• fSYS > 60 MHz: ICR.CONECYC = 0 and PCP_ICR.CONECYC = 0

Functional DescriptionPreliminary Data Sheet 52 V1.0, 2008-04 Figure 3-3 Block Diagra m of the TC1163/TC1164 Interrupt System PCP Interrupt Control Unit PICU Service Req. Nodes Service Req. Nodes Service Requestors CPU Interrupt Control Unit Service Req. Nodes Interrupt Service Providers

4 SRNs4MLI0

3 SRNs3SSC0

3 SRNsSSC1

4 SRNs4ASC0

4 SRNsASC1

6 SRNsMultiCAN 1)

4 SRNsADC0

2 SRNsFADC

38 SRNs38GPTA0

5 SRNs

2 SRNs

Int. Ack. CCPN Int. Req. PIPN CPU CCPN Int. Ack. Software and Breakpoint Interrupts ICU

2 SRNs2MSC0

1 SRN

4 SRNs

Ext. Int STM FPU Flash Service Requestors LBCU SBCU Cerberus DMA Int. Req. PIPN DMA Bus TC1163/TC1164 Interrupt System 1) MultiCAN module and the 6 SRNs are not applicable to TC1163.

Functional DescriptionPreliminary Data Sheet 53 V1.0, 2008-04

3.8 Asynchronous/Synchronous Se rial Interfaces (ASC0, ASC1)

Figure 3-4 shows a global view of the functiona l blocks and interf aces of the two Asynchronous/Synchronous Serial Interfaces, ASC0 and ASC1. Figure 3-4 Block Diagram of the ASC Interfaces The ASC provides serial communication between th e TC1163/TC1164 and other microcontrollers, microprocessors, or external peripherals. The ASC supports full-duplex asynch ronous communicat ion and half-duplex synchronous communication. In Synchronous Mode, data is transmitted or received synchronous to a shift clock that is gener ated by the ASC intern ally. In Asynchronous Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be MCB06211c ASC0 Module (Kernel) Port 3 Control ASC1 Module (Kernel) P3.12 / RXD0B P3.13 / TXD0B P3.0 / RXD0A P3.1 / TXD0A P3.14 / RXD1B P3.15 / TXD1B P3.9 / RXD1A P3.8 / TXD1A RXD_I1 RXD_O RXD_I0 TXD_O RXD_I1 RXD_O RXD_I0 TXD_O Interrupt Control EIR TBIR TIR RIR Clock Control Address Decoder Interrupt Control fASC EIR TBIR TIR RIR To DMA ASC0_RDR ASC0_TDR To DMA ASC1_RDR ASC1_TDR

Functional DescriptionPreliminary Data Sheet 54 V1.0, 2008-04 selected. Parity, framing, and overrun error detection are provided to increase the reliability of data transfers. Transmission and reception of data is double-buffered. For multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator provides the ASC with a separate serial clock signal, which can be accurately adjusted by a prescaler implemented as fractional divider.

• Full-duplex asynchronous operating modes – 8-bit or 9-bit data frames, LSB first – Parity-bit generation/checking – One or two stop bits – Baud rate from 5.0 Mbit/s to 1.19 bit/s (@ 80 MHz module clock) – Multiprocessor mode for automatic address/data byte detection – Loop-back capability
• Half-duplex 8-bit synch ronous operating mode – Baud rate from 10.0 Mbit/s to 813.8 bit/s (@ 80 MHz module clock)
• Double-buffered transmitter/receiver
• Interrupt generation – On a transmit buffer empty condition – On a transmit last bi t of a frame condition – On a receive buffer full condition – On an error condition (frame, parity, overrun error)

Functional DescriptionPreliminary Data Sheet 55 V1.0, 2008-04

3.9 High-Speed Synchronous Serial Interfaces (SSC0 and SSC1)

Figure 3-5 shows a global view of the functional blocks and interfaces of the two high- speed Synchronous Serial Interfaces, SSC0 and SSC1. Figure 3-5 Block Diagra m of the SSC Interfaces Clock Control Address Decoder Interrupt Control fSSC0 SSC 0_TDR EIR TIR RIR Port 3 Control SSC0 Module (Kernel ) MRSTB MTSR Master SLSI1 SLSO[2:0] MRSTA MTSRB MRST MTSRA SCLKB SCLK SCLKA Slave Slave Master Slave Master fCLC 0 SLSI[7:2]1) Enable1) M/S Select 1 ) These lines are not connected Clock Control Address Decoder Interrupt Control fSSC1 SSC 1_TDR EIR TIR RIR Port 2 Control SSC1 Module (Kernel ) Master fCLC 1 SLSO[5:3] SLSO7 SLSO[5:3] SLSO6 MRSTB MTSR Master SLSI1 MRSTA MTSRB MRST MTSRASCLKB SCLK SCLKA Slave Slave Master Slave SLSI[7:2] SLSO[2:0] Port 1 Control SLSO7 SLSO6 1) SSC 0_RDR SSC 1_RDRTo DMA To DMA Enable M/S Select MCB06225_c P3.7 /SLSO02 / SLSO12 P3.3 /MRST0 P3.4 /MTSR0 P3.2 /SCLK0 P3.7 /SLSI0 P3.5 /SLSO00 / SLSO10 / SLSO00 AND SLSO10 P1.10 /SLSO17 P2.8 /SLSO04 / SLSO14 P2.9 /SLSO05 / SLSO15 P2.10 /MRST1A P2.12 /MTSR1A P2.11 /SCLK1A P2.13 /SLSI1 P3.8 /SLSO06 P2.1 /SLSO03 / SLSO13 P1.9 /MRST1B P1.11 /SCLK1B P1.8 /MTSR1B P3.6 /SLSO01 / SLSO11 / SLSO01 AND SLSO11

Functional DescriptionPreliminary Data Sheet 56 V1.0, 2008-04 The SSC supports full-duplex and half-duplex serial synchronous communication up to 40.0 MBaud (@ 80 MHz module clock). The serial clock signal can be generated by the SSC itself (Master Mode) or can be received from an external master (Slave Mode). Data width, shift directi on, clock polarity and phase are programmable. This allows communication with SPI-com patible devices. Transmission and reception of data is double-buffered. A shift clock generator provides the SSC with a separ ate serial clock signal. Seven slave select inputs are av ailable for Slave Mode operation. Eight programmable slave select outputs (chip selects) are supported in Master Mode.

• Master and Slave Mode operation – Full-duplex or ha lf-duplex operation – Automatic pad control possible
• Flexible data format – Programmable number of data bits: 2 to 16 bits – Programmable shift directi on: LSB or MSB shift first – Programmable clock polarity: Idle low or idle high state for the shift clock – Programmable clock/data phase: Data shift with leading or trailing edge of the shift clock
• Baud rate generation from 40.0 Mbit/s to 610.36 bit/s (@ 80 MHz module clock)
• Interrupt generation – On a transmitter empty condition – On a receiver full condition – On an error condition (receive, p hase, baud rate, transmit error)
• Flexible SSC pin configuration
• Seven slave select inputs SLSI[7:1] in Slave Mode
• Eight programmable slave select outputs SLSO[7:0] in Master Mode – Automatic SLSO generation with programmable timing – Programmable active level and enable control

Functional DescriptionPreliminary Data Sheet 57 V1.0, 2008-04

3.10 Micro Second Bus Interface (MSC0)

The MSC interface provides a serial communication link typically used to connect power switches or other pe ripheral devices. The serial co mmunication link includes a fast synchronous downstream channel and a slow asynchronous upstream channel. Figure 3-6 shows a global view of the MSC interface signals. Figure 3-6 Block Diagram of the MSC Interface The downstream and upstream channels of the MSC module communicate with the external world via nine I/O lines. Eight output lines are required for the serial communication of the downstream channel (clock, data, and enable signals). One out of eight input lines SDI[7:0] is used as serial data input signal for the upstream channel. The source of the serial data to be transmitted by the downstream channel can be MSC register contents or data that is provided at the ALTINL/ALTINH input lines. These input lines are typically connected to other on-chip peripheral units (for example with a timer unit like the GPTA). An emergency stop input signal makes it possible to set bits of the serial data stream to dedicated values in emergency cases. MSC0 Module (Kernel) MCA0625 5 Port 2 Control P2.13 / SDI0 EN0 SOP SON0SON SOP0A P2.9 / EN01 P2.8 / EN00 FCLN0FCLN FCLP0AFCLP EN1 P2.11 / FCLP0B P2.12 / SOP0B Upstream Channel Downstream Channel Clock Control Address Decoder Interrupt Control SR[1:0] EMGSTOPMSC ALTINL[15:0] ALTINH[15:0] To DMA SR[3:2] (from GPTA) (from SCU) fMSC0 fCLC0 SR15 (from CAN) SDI[0]1) 1) SDI[7:1] are connected to high level C C C C

Functional DescriptionPreliminary Data Sheet 58 V1.0, 2008-04 Clock control, address decoding, and inte rrupt service request control are managed outside the MSC module kernel. Service request outputs are able to trigger an interrupt or a DMA request.

• Fast synchronous serial inte rface to connect power switch es in particular, or other peripheral devices via serial buses
• High-speed synchronous serial tr ansmission on downstream channel – Serial output clock frequency: fFCL = fMSC/2 – Fractional clock divider for precis e frequency control of serial clock fMSC – Command, data, and passive frame types – Start of serial frame: Software-cont rolled, timer-controlled, or free-running – Programmable upstream data fr ame length (16 or 12 bits) – Transmission with or without SEL bit – Flexible chip select generation indicate s status during serial frame transmission – Emergency stop without CPU intervention
• Low-speed asynchronous serial reception on upstream channel – Baud rate: fMSC divided by 4, 8, 16, 32, 64, 128, or 256 – Standard asynchronous serial frames – Parity error checker – 8-to-1 input multip lexer for SDI lines – Built-in spike fi lter on SDI lines

Functional DescriptionPreliminary Data Sheet 59 V1.0, 2008-04

3.11 MultiCAN Controller (CAN)

Note: Section 3.11 is not applicable to TC1163. Figure 3-7 shows a global view of the MultiCAN module with its functional blocks and interfaces. Figure 3-7 Block Diagra m of MultiCAN Module The MultiCAN module contains two independently-operating CAN nodes with Full-CAN functionality that are able to exchange Data and Remote Frames via a gateway function. Transmission and reception of CAN fram es is handled in accordance with CAN specification V2.0 B (active). Each CAN node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Both CAN nodes share a common set of message objects. Each message object can be individually allocated to one of the CAN nodes. Besides serving as a storage container for incoming and outgoing frames, message objects can be combined to build gateways between the CAN nodes or to setup a FIFO buffer. The message objects are organi zed in double-chained linke d lists, where each CAN node has its own list of message objects. A CAN node stores frames only into message objects that are allocated to the message object list of the CAN node, and it transmits only messages belonging to this message ob ject list. A powerful, command-driven list controller performs all message object list operations. MultiCAN Module Kernel MCA0628 1 Interrupt Control fCAN Port 3 Control CAN Control Message Object Buffer Objects TXDC0 RXDC0 TXDC1 RXDC1Linked List Control P3.15 / TXDCAN 1 P3.14 / RXDCAN 1 P3.13 / TXDCAN 0 P3.12 / RXDCAN 0 fCLC Clock Control Address Decoder DMA INT_O [1:0] INT_O15 INT_O [5:2] CAN Node 0 CAN Node 1

Functional DescriptionPreliminary Data Sheet 60 V1.0, 2008-04 The bit timings for the CA N nodes are derived from the module timer clock ( fCAN), and are programmable up to a data rate of 1 Mbit/s. External bus transceivers are connected to a CAN node via a pair of receive and transmit pins. MultiCAN Features

• CAN functionality conforms to CAN specif ication V2.0 B active for each CAN node (compliant to ISO 11898)
• Two independent CAN nodes
• 64 independent message objects (shared by the CAN nodes)
• Dedicated control regi sters for each CAN node
• Data transfer rate up to 1Mbit/s, individually programmable for each node
• Flexible and powerful me ssage transfer control and error handling capabilities
• Full-CAN functionality: messa ge objects can be individually – assigned to one of the two CAN nodes – configured as transmit or receive object – configured as message bu ffer with FIFO algorithm – configured to handle frames with 11-bit or 29-bit identifiers – provided with programmable accept ance mask register for filtering – monitored via a frame counter – configured for Remote Monitoring Mode
• Automatic Gateway Mode support
• 6 individually programmable interrupt nodes
• CAN analyzer mode for bus monitoring

Functional DescriptionPreliminary Data Sheet 61 V1.0, 2008-04

3.12 Micro Link Serial Bus Interface (MLI0)

The Micro Link Interface is a fast synchronous serial interface that allows data exchange between microcontrollers of the 32-bit AUDO microcontroller family without intervention of a CPU or other bus masters. Figure 3-8 shows how two microcontrollers are typically connected together via their MLI interfaces . The MLI operates in both microcontrollers as a bus master on the system bus. Figure 3-8 Typical Micro Li nk Interface Connection

• Synchronous serial commun ication between MLI transmi tters and MLI receivers located on the same or on different microcontroller devices
• Automatic data transfer/request transact ions between local/remote controller
• Fully transparent read/ write access supported (= remote programming)
• Complete address range of re mote controller available
• Specific frame protocol to tr ansfer commands, addresses and data
• Error control by parity bit
• 32-bit, 16-bit, and 8-bit data transfers
• Programmable baud rates – MLI transmitter baud rate: max. fMLI/2 (= 40 Mbit/s @ 80 MHz module clock) – MLI receiver baud rate: max. fMLI
• Multiple remote (slave) controllers are supported MLI transmitter and MLI receiver communicate with other off-chip MLI receivers and MLI transmitters via a 4-line serial I/O bus each. Several I/O lines of these I/O buses are available outside the MLI module kernel as four-line output or input buses. MCA06061 Controller 1 CPU Peripheral B Peripheral A MLI System Bus Controller 2 CPU Peripheral D Peripheral C MLI System Bus Memory Memory

Functional DescriptionPreliminary Data Sheet 63 V1.0, 2008-04

3.13 General Purpose Timer Array

The GPTA provides a set of timer, compare, a nd capture functional ities that can be flexibly combined to form signal measurement and signa l generation units. They are optimized for tasks typical of electrical motor control applications, but can also be used to generate simple and complex signal waveforms needed in other industrial applications. The TC1163/TC1164 contains one General Purpose Timer Array (GPTA0). Figure 3-10 shows a global view of the GPTA module. Figure 3-10 Block Diagram of the GPTA Module Signal Generation Unit MCB06063 GT1 GT0 FPC5 FPC4 FPC3 FPC2 FPC1 FPC0 PDL1 PDL0 DCM2 DCM1 DCM0 DIGITAL PLL DCM3 GTC02 GTC01 GTC00 GTC31 Global Timer Cell Array GTC03 GTC30 Clock Bus GPTA Clock Generation Unit Clock Con n. Clock Distribution UnitfGPTA LTC02 LTC01 LTC00 LTC63 Local Timer Cell Array LTC03 LTC62 I/O Line Sharing Unit Interrupt Sharing Unit

Functional DescriptionPreliminary Data Sheet 64 V1.0, 2008-04

3.13.1 Functionality of GPTA0

The General Purpose Timer Array GPTA0 provides a set of hardware modules required for high-speed digital signal processing:

• Filter and Prescaler Cells (F PC) support input noise filtering and prescaler operation.
• Phase Discrimination Logic units (PDL) decod e the direction information output by a rotation tracking system.
• Duty Cycle Measurement Cells (DCM ) provide pulse-width measurement capabilities.
• A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA module clock ticks during an input signal’s period.
• Global Timer units (GT) driven by various clock sources are implemented to operate as a time base for the associated Global Timer Cells.
• Global Timer Cells (GTC) can be programmed to capt ure the contents of a Global Timer on an external or internal event. A GTC may also be used to control an external port pin depending on the result of an internal compare operation. GTCs can be logically concatenated to provide a common external port pin with a complex signal waveform.
• Local Timer Cells (LTC) operat ing in Timer, Capture, or Compare Mode may also be logically tied together to drive a common external port pin with a complex signal waveform. LTCs — enabled in Timer Mode or Capture Mode — can be clocked or triggered by various external or internal events. Input lines can be shared by an LTC and a GTC to trig ger their programmed operation simultaneously. The following list summarizes the specific features of the GPTA unit. Clock Generation Unit
• Filter and Prescaler Cell (FPC) – Six independent units – Three basic operating modes: Prescaler, Delayed Debounce Filter, Immediate Debounce Filter – Selectable input sources: Port lines, GPTA module clock, FPC output of preceding FPC cell – Selectable input clocks: GPTA module clock, prescaled GPTA module clock, DCM clock, compensated or uncompensated PLL clock fGPTA/2 maximum input signal frequency in Filter Modes
• Phase Discriminator Logic (PDL) – Two independent units – Two operating modes (2- and 3-sensor signals) – fGPTA/4 maximum input signal frequency in 2-sensor Mode, fGPTA/6 maximum input signal frequency in 3-sensor Mode

Functional DescriptionPreliminary Data Sheet 65 V1.0, 2008-04

• Duty Cycle Measurement (DCM) – Four independent units – 0 - 100% margin and time-out handling – fGPTA maximum resolution – fGPTA/2 maximum input signal frequency
• Digital Phase Locked Loop (PLL) – One unit – Arbitrary multiplicati on factor between 1 and 65535 fGPTA maximum resolution – fGPTA/2 maximum input signal frequency
• Clock Distribution Unit (CDU) – One unit – Provides nine clock output signals: fGPTA, divided fGPTA clocks, FPC1/FPC4 outputs, DCM clock, LTC prescaler clock Signal Generation Unit
• Global Timers (GT) – Two independent units – Two operating modes (Free-Running Timer and Reload Timer) – 24-bit data width fGPTA maximum resolution – fGPTA/2 maximum input signal frequency
• Global Time r Cell (GTC) – 32 units related to the Global Timers – Two operating modes (Capture, Co mpare and Capture after Compare) – 24-bit data width fGPTA maximum resolution – fGPTA/2 maximum input signal frequency
• Local Timer Cell (LTC) – 64 independent units – Three basic operating modes (Timer , Capture and Compare) for 63 units – Special compare modes for one unit – 16-bit data width fGPTA maximum resolution – fGPTA/2 maximum input signal frequency Interrupt Control Unit
• 111 interrupt sources, genera ting up to 38 service requests

Functional DescriptionPreliminary Data Sheet 66 V1.0, 2008-04 I/O Sharing Unit

• Interconnecting inputs and outp uts from internal clocks, FPC, GTC, LTC, ports, and MSC interface

Functional DescriptionPreliminary Data Sheet 67 V1.0, 2008-04

3.14 Analog-to-Digital Converter (ADC0)

Section 3.14 shows the global view of the A DC module with its functional blocks and interfaces and the features which are provided by the module. Figure 3-11 Block Diag ram of the ADC Module The ADC module has 16 analog input channels. An analog multiplexer selects the input line for the analog input channels from among 32 analog inputs. Additionally, an external analog multiplexer can be used for analog input extensio n. External Clock control, address decoding, and service request (interrupt) control are managed outside the ADC module kernel. External tri gger conditions are controlled by an External Request Unit. This unit generates the contro l signals for auto-scan contro l (ASGT), software trigger control (SW0TR, SW0GT), the event trigger control (ETR, EGT), q ueue control (QTR, QGT), and timer trigger control (TTR, TGT). An automatic self-calibrati on adjusts the ADC module to changing temperatures or process variations. Figure 3-11 shows the global view of the ADC module with its functional blocks and interfaces. ADC0 Module KernelInterrupt Control Clock Control Address Decoder fADC To DMA AIN16 Analog Multiplexer MCA0642 7 VAGND0 VDD VSS VDDM VAREF0VSSM Group 1 P1.13 /AD0EMUX1 P1.12 /AD0EMUX0 AN0 AN15 AN16 fCLC Port 1 Control AIN0 AIN15Group 0 ASGT SW0TR, SW0GT ETR, EGT QTR, QGT TTR, TGT External Request Unit (SCU) AIN30 From GPTA From Ports From MSC0 P1.14 / AD0EMUX2 (GRPS ) AN30 AIN31 AN31 Die Temperature Measurement SCU_CON.DTSON GPRS EMUX0 EMUX1 SR[3:0] SR[7:4] D D D D D

Functional DescriptionPreliminary Data Sheet 68 V1.0, 2008-04

• 8-bit, 10-bit, 12- bit A/D conversion
• Conversion time below 2.5 µs @ 10-bit resolution
• Extended channel status in formation on request source
• Successive approximat ion conversion method
• Total Unadjusted Error (TUE) of ±2 LSB @ 10-bit resolution
• Integrated sample & hold functionality
• Direct control of up to 16 analog input channels
• Dedicated control and status registers for each analog channel
• Powerful conversion request sources
• Selectable reference vo ltages for each channel
• Programmable sample and c onversion timing schemes
• Limit checking
• Flexible ADC module serv ice request control unit
• Automatic control of ex ternal analog multiplexers
• Equidistant samples initiated by timer
• External trigger and gating i nputs for conversion requests
• Power reduction and clock control feature
• On-chip die temperature sens or output voltage measurement

Functional DescriptionPreliminary Data Sheet 69 V1.0, 2008-04

3.15 Fast Analog-to-Digita l Converter Unit (FADC)

The on-chip FADC module of the TC1163/TC1164 basically is a 2-channel A/D converter with 10-bit resolution that operates by the method of the successive approximation. As shown in Figure 3-12, the main FADC functional blocks are:

• The Input Stage — con tains the differential inputs and the programmable amplifier
• The A/D Converter — is responsible for the analog-to-digital conversion
• The Data Reduction Unit — contains prog rammable antialiasing and data reduction filters
• The Channel Trigger Control block — dete rmines the trigger and gating conditions for the two FADC channels
• The Channel Timers — can independently trigger the conversion of each FADC channel
• The A/D Control block is responsible for the overall FADC functionality The FADC module is supplied by the following power supply and reference voltage lines:
• VDDMF/VDDMF:FADC Analog Part Power Supply (3.3 V)
• VDDAF/VDDAF:FADC Analog Part Logic Power Supply (1.5 V)
• VFAREF/VFAGND:FADC Reference Voltage (3.3 V)/FADC Reference Ground

Functional DescriptionPreliminary Data Sheet 70 V1.0, 2008-04 Figure 3-12 Block Diagra m of the FADC Module

• Extreme fast conversion, 21 cycles of fFADC clock (262.5 ns @ fFADC =8 0 M H z )
• 10-bit A/D conversion – Higher resolution by averaging of co nsecutive conversions is supported
• Successive approximat ion conversion method
• Two differential input channels
• Offset and gain calibrati on support for each channel
• Differential input amplifier with programmabl e gain of 1, 2, 4 and 8 for each channel
• Free-running (Channel Timers) or triggered conversion modes
• Trigger and gatin g control for external signals
• Built-in Channel Timers for internal triggering
• Channel timer request pe riods independently selectable for each channel
• Selectable, programmable anti-aliasi ng and data reduction filter block Clock Control Address Decoder MCA0644 5 VFAGND VDDAF VSSAF VDDMFVFAREF VSSMF Interrupt Control AN32 TS[7:0] GS[7:0] fFADC fCLC SR[1:0] FAIN0P FAIN0N FAIN1P FAIN1N AN33 AN34 AN35 P3.10 / REQ0 External Request Unit (SCU) P3.11 / REQ1 P0.14 / REQ4 P0.15 / REQ5 GPTA0 OUT1 OUT9 OUT18 OUT26 OUT2 OUT10 OUT19 OUT27 PDOUT2 PDOUT3 DMA SR[3:2] FADC Module Kernel D D D D

Functional DescriptionPreliminary Data Sheet 71 V1.0, 2008-04

3.16 System Timer

The TC1163/TC1164’s STM is designed for global system timing applications requiring both high precision and long period.

• Free-running 56-bit counter
• All 56 bits can be read synchronously
• Different 32-bit porti ons of the 56-bit counter can be read synchronously
• Flexible interrupt generation based on compare match with partial STM content
• Driven by maximum 80 MHz (= fSYS, default after reset = fSYS/2)
• Counting starts automatica lly after a reset operation
• STM is reset by: – Watchdog reset – Software reset (RST_REQ.RRSTM must be set) – Power-on reset
• STM (and clock divider STM_CLC.RMC) is not reset at a hardware reset (HDRST
• STM can be halted in debug/susp end mode (via STM_CLC register) The STM is an upward counter, running either at the system clock frequency fSYS or at a fraction of it. The STM clock frequency is fSTM = fSYS/RMC with RMC = 0-7 (default after reset is fSTM = fSYS/2, selected by RMC = 010B). RMC is a bit field in register STM_CLC. In case of a power-on reset, a watchdog reset, or a software reset, the STM is reset. After one of these reset conditions, the STM is enabled and immediately starts counting up. It is not possible to affect th e content of the timer during normal operation of the TC1163/TC1164. The timer registers can only be read but not written to. The STM can be optionally di sabled for power-saving pur poses, or suspended for debugging purposes via its clock control register. In suspend mode of the TC1163/TC1164 (initiated by wr iting an appropriate value to STM_CLC register), the STM clock is stopped but all registers are still readable. Due to the 56-bit width of the STM, it is not possible to read its entire content with one instruction. It needs to be read with two load instructions. Since the timer would continue to count between the two load operations, there is a chance that the two values read are not consistent (due to possible overflow from the low part of the timer to the high part between the two read operations). To enable a synchro nous and consistent reading operation of the STM content, a capture register (STM_CAP) is implemented. It latches the content of the high part of the STM each time when one of the registers STM_TIM0 to STM_TIM5 is read. Thus, STM_CAP holds the upper value of the timer at exactly the same time when the lower part is read. The second read operation would then read the content of the STM_CAP to get the complete timer value.

Functional DescriptionPreliminary Data Sheet 72 V1.0, 2008-04 The STM can also be read in sections from seven r egisters, STM_TIM0 through STM_TIM6, that select increa singly higher-order 32-bit r anges of the STM. These can be viewed as individual 32-bit timers, each with a different resolution and timing range. The content of the 56-bit System Timer can be compar ed with the content of two compare values stored in the STM_CMP0 and STM_CMP1 registers. Interrupts can be generated on a compare match of the STM with the STM_CMP0 or STM_CMP1 registers. The maximum clock period is 256 × fSTM. At fSTM = 80 MHz, for example, the STM counts 28.56 years before overflowing. Thus, it is capable of timing the entire expected product life-time of a system without overflowing continuously. Figure 3-13 shows an overview on the System Timer with the options for reading parts of the STM contents.

Functional DescriptionPreliminary Data Sheet 73 V1.0, 2008-04 Figure 3-13 General Block Diagram of the STM Module Registers STM Module 00H STM_CAP STM_TIM6 STM_TIM5 00H 56-Bit System Timer Address Decoder Clock Control MCB06185 Compare Register 0 Interrupt Control Compare Register1 PORST STM_TIM4 STM_TIM3 STM_TIM2 STM_TIM1 STM_TIM0 STM_CMP1 STM_CMP0 Enable / Disable fSTM STMIR1 STMIR0 31 23 15 7 0 31 23 15 7 0 55 47 39 31 23 15 7 0

Functional DescriptionPreliminary Data Sheet 74 V1.0, 2008-04

3.17 Watchdog Timer

The WDT provides a highly reliable and secure way to detect and recover from software or hardware failure. The WD T helps to abort an accide ntal malfunction of the TC1163/TC1164 in a user-specified time period. When enabled, the WDT will cause the TC1163/TC1164 system to be reset if th e WDT is not serviced within a user- programmable time period. The CPU must se rvice the WDT within th is time interval to prevent the WDT from causing a TC1163/TC1164 system reset. Hence, routine service of the WDT confirms that the system is functioning as expected. In addition to this standard “Watchdog” function, the WDT incorporates the End-of- Initialization (Endinit) featur e and monitors its modifica tions. A system-wide line is connected to the WDT_CON0.ENDINIT bit, serving as an additional write-protection for critical registers (besides Supervisor Mode protection). Registers protected via this line can only be modified when Supervisor Mode is active and bit ENDINIT = 0. A further enhancement in the TC1163/TC1164’s WDT is its reset prewarning operation. Instead of resetting the device upon the detection of an error immediately (the way that standard Watchdogs do), the WD T first issues a Non-Maskab le Interrupt (NMI) to the CPU before resetting the device at a specified time period later. This step gives the CPU a chance to save the system state to the memory for later investigation of the cause of the malfunction; an important aid in debugging.

• 16-bit Watchdog counter
• Selectable input frequency: fSYS/256 or fSYS/16384
• 16-bit user-definable reload value for norm al Watchdog operation, fixed reload value for Time-Out and Prewarning Modes
• Incorporation of the ENDINIT bit and monitoring of its modifications
• Sophisticated Password Access mechanism with fixed and user-definable password fields
• Proper access always requires two writ e accesses. The time between the two accesses is monitored by the WDT and is limited.
• Access Error Detection: Invalid password ( during first access) or invalid guard bits (during second access) trigger the Watchdog reset generation
• Overflow Error Detection: An overflow of the counte r triggers the Watchdog reset generation.
• Watchdog function c an be disabled; access protection and ENDINIT monitor function remain enabled.
• Double Reset Detection: If a Watchdog indu ced reset occurs twice, a severe system malfunction is assumed and the TC1163/TC1164 is held in reset until a power-on or hardware reset occurs. This pr events the device from being periodically reset if, for instance, connection to the external memory has been lost such that system initialization could not even be performed.

Functional DescriptionPreliminary Data Sheet 75 V1.0, 2008-04

• Important debugging suppor t is provided through the reset prewarning operation by first issuing an NMI to the CPU before fina lly resetting the device after a certain period of time.

3.18 System Control Unit

The System Control Unit (SCU) of the TC1163/TC1164 handles several system control tasks. The system control tasks of the SCU are:

• Clock system sele ction and control
• Reset and boot operation control
• Power management control
• Configuration input sampling
• External Request Unit
• System clock output control
• On-chip SRAM parity control
• Pad driver temperatur e compensation control
• Emergency stop input co ntrol for GPTA outputs
• GPTA input IN1 control
• Pad test mode contro l for dedicated pins
• ODCS level 2 trace control
• NMI control
• Miscellaneous SCU control

Functional DescriptionPreliminary Data Sheet 76 V1.0, 2008-04

3.19 Boot Options

The TC1163/TC1164 booting schemes provide a number of different boot options for the start of code execution. Table 3-7 shows the boot options available in the TC1163/TC1164. Table 3-7 TC1163/TC11 64 Boot Selections BRKIN HWCFG [3:0] TESTMODE Type of Boot BootROM Exit Jump Address Normal Boot Options 1 0000 B 1 Enter bootstrap loader mode 1: Serial ASC0 boot via ASC0 pins D400 0000H 0001B 1) This option is not applicable to TC1163. Enter bootstrap loader mode 2: Serial CAN boot via P3.12 and P3.13 pins 0010 B Start from internal PFLASH A000 0000 H 0011B Alternate boot mode (ABM): Start from internal PFLASH after CRC check is correctly executed; enter a serial bootstrap loader mode 2) if CRC check fails 2) The type of the alternate bootstrap loader mode is sele cted by the value of the SCU_SCLIR.SWOPT[2:0] bit field, which contains the levels of the P0.[2:0] latched in with the rising edge of the HDRST. Defined in ABM header or D400 0000 H 1111B Enter bootstrap loader mode 3: Serial ASC0 boot via P3.12 and P3.13 pins D400 0000 H others Reserved; execute stop loop – Debug Boot Options 0 0000 B 1 Tri-state chip – others irrel. Reserved; execute stop loop –

Functional DescriptionPreliminary Data Sheet 77 V1.0, 2008-04

3.20 Power Management System

The TC1163/TC1164 pow er management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. There are three power management modes:

• Run Mode
• Idle Mode
• Sleep Mode The operation of each system component in each of these states can be configured by software. The power-managem ent modes provide flex ible reduction of power consumption through a combin ation of techniques, includ ing stopping the CPU clock, stopping the clocks of other system com ponents individually, and individually clock- speed reduction of some peripheral components. Besides these explicit software-controlled power-saving modes, sp ecial attention has been paid to automatic power-saving in those operating units which are not required at a certain point of time, or id le in the TC1163/TC1164. In th at case, they are shut off automatically until their operation is required again. Table 3-8 describes the features of the power management modes. In typical operation, Idle Mode and Sleep Mode may be entered and exited frequently during the run time of an application. For example, system software will typically cause the CPU to enter Idle Mode each time it has to wait for an interrupt before continuing its tasks. In Sleep Mode and Idle Mode, wake-u p is performed auto matically when any Table 3-8 Power Manage ment Mode Summary Mode Description Run The system is fully operational. All clocks and peripherals are enabled, as determined by software. Idle The CPU clock is disabled, waiting for a condition to return it to Run Mode. Idle Mode can be entered by software when the processor has no active tasks to perform. All peripherals remain powered and clocked. Processor memory is accessible to peripherals. A reset, Watchdog Timer event, a falling edge on the NMI pin, or any enabled interrupt event will return the system to Run Mode. Sleep The system clock signal is distributed only to those peripherals programmed to operate in Sleep Mode. The other peripheral module will be shut down by the suspend signal. Interrupts from operating peripherals, the Watchdog Timer, a falling edge on the NMI pin, or a reset event will return the system to Run Mode. Entering this state requires an orderly shut-down controlled by the Power Management State Machine.

Functional DescriptionPreliminary Data Sheet 78 V1.0, 2008-04 enabled interrupt signal is detected, or when the c ount value (WDT_SR.WDTTIM) changes from 7FFFH to 8000H.

3.21 On-Chip Debug Support

Figure 3-14 shows a block diagram of the TC1163/TC1164 OCDS system. Figure 3-14 OCDS System Block Diagram The TC1163/TC1164 basically supports two levels of debug operation:

• OCDS Level 1 debug support
• OCDS Level 2 debug support MCB0619 5 Enable, Control and Reset OCDS DMA System Peripheral Bus SPB Peripheral Unit 1 SPB Peripheral Unit n Break andSuspend Signals BCU PCP OCDS OCDS TriCore OCDS OCDS Watch- dog Timer JDI Debug I/F JTAG Controller MCBS Break Switch Cerberus OSCU DMA L2 BRKIN TDI TDO BRKOUT TRST TMS TCK O CDS2[15:0] Multiplexer

Functional DescriptionPreliminary Data Sheet 79 V1.0, 2008-04 OCDS Level 1 Debug Support The OCDS Level 1 debug support is mainly assigned for real-time software debugging purposes which have a demand for low-cost standard debugger hardware. The OCDS Level 1 is based on a JTAG interface that is used by the external debug hardware to communicate with the system. The on -chip Cerberus module controls the interactions between the JTAG interface and the on-chip modules. The external debug hardware may become master of the internal buses, and read or write the on-chip register/memory resources. The Cerberus also makes it possible to define breakpoint and trigger conditions as we ll as to control us er program execution (run/stop, break, single-step). OCDS Level 2 Debug Support The OCDS Level 2 debug sup port makes it possible to implement program tracing capabilities for enhanced debuggers by extending the OCDS Level 1 debug functionality with an additional 16-bit wide trace output port with trace clock. With the trace extension, the following four trace capabilities are prov ided (only one of the four trace capabilities can be selected at a time):

• Trace of the CPU program flow
• Trace of the PCP2 program flow
• Trace of the DMA Contro ller transaction requests
• Trace of the DMA Controller Move Engine status information

Functional DescriptionPreliminary Data Sheet 80 V1.0, 2008-04

3.22 Clock Generation and PLL

The TC1163/TC1164 clock system performs the following functions:

• Acquires and buffers incoming clock sig nals to create a master clock frequency
• Distributes in-phase synchronized clo ck signals throughout the TC1163/TC1164’s entire clock tree
• Divides a system master clock frequency into lower frequencies required by the different modules for operation.
• Dynamically reduces power consumption during operation of functional units
• Statically reduces power consumption through programmable power-saving modes
• Reduces electromagnetic interference (EMI) by switching off unused modules The clock system must be operational bef ore the TC1163/TC1164 can function, so it contains special logic to handle power-up and reset operations. Its services are fundamental to the operation of the entire system, so it contains special fail-safe logic.
• PLL operation for multiplying clo ck source by different factors
• Direct drive capability for direct clocking
• Comfortable state machine for secure switching betw een basic PLL, direct or prescaler operation
• Sleep and Power-Down Mode support The TC1163/TC1164 Clock Generation Unit (CGU) as shown in Figure 3-15 allows a very flexible clock generation. It basically consists of an main oscillator circuit and a Phase- Locked Loop (PLL). The PLL can converts a low-frequency external clock signal from the oscillator circuit to a high-speed internal clock for maximum performance. The system clock fSYS is generated from an oscillator clock fOSC in either one of the four hardware/software selectable ways:
• Direct Drive Mode (PLL Bypass): In Direct Drive Mode, the TC1163/TC1164 clock system is directly driven by an external clock signal. input, i.e. fCPU = fOSC and fSYS = fOSC. This allows operation of the TC1163/TC1164 with a reasonably small fundamental mode crystal.
• VCO Bypass Mode (Prescaler Mode): In VCO Bypass Mode, fCPU and fSYS are derived from fOSC by the two divider stages, P-Divider and K-Divider. The system clock fSYS is equal to fCPU.
• PLL Mode: In PLL Mode, the PLL is running. The VCO clock fVCO is derived from fOSC, divided by the P factor, multiplied by the PL L (N-Divider). The clock signals fCPU and fSYS are derived from fVCO by the K-Divider. The system clock fSYS is equal to fCPU.
• PLL Base Mode: In PLL Base Mode, the PLL is running at its VCO base frequency and fCPU and fSYS

Functional DescriptionPreliminary Data Sheet 81 V1.0, 2008-04 are derived from fVCO only by the K-Divider. In this mode, the system clock fSYS is equal to fCPU. Figure 3-15 Clock Generation Unit Recommended Oscillator Circuits The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal oscillator or an external stable clock source. It basically consists of an inverting amplifier and a feedback element with XTAL1 as input, and XTAL2 as output. When using a crystal, a proper external oscillator circuitr y must be con nected to both pins, XTAL1 and XTAL2. Th e crystal frequency can be within the range of 4 MHz to 25 MHz. Additionally, it is necessary to have two load capacitances CX1 and CX2, and depending on the crystal type, a series resistor RX2, to limit the current. A test resistor RQ may be temporarily inserted to measure the oscillation allowance (negative resistance) of the oscillator circuitry. RQ values are typically specified by the crystal vendor. The CX1 and CX2 values shown in Figure 3-16 can be used as starti ng points for the negative resistance evaluation and for non-producti ve systems. The exact values and related operating range are dependent on the crystal frequency and have to be determined and optimized together wit h the crystal vendor using the negative resistance method. System Control Unit (SCU) Clock Generation Unit (CGU) PLL 1:1 Divider M U X M U XK:1 Divider MCA06083 Oscillator Circuit XTAL1 XTAL2 fOSC Phase Detect. VCO N Divider fVCO fSYS Lock Detector OSCR PLL_ LOCK NDIV [6:0] VCO_ BYPASS KDIV [3:0] PLL_ BYPASS Register PLL_CLC VCO_ SEL[1:0] fCPU SYS FSL P Divi- der PDIV [2:0] OSC DISC Register OSC_CON MOSCOGCBYPASS OSC_ BYPASS Osc. Run Detect.

Functional DescriptionPreliminary Data Sheet 82 V1.0, 2008-04 Oscillation measurement with the final target system is strongly recommended to verify the input amplitude at XTAL1 and to determine the actual oscillation allowance (margin negative resistance) for the oscillator-crystal system. When using an external clock signal, the signal must be connected to XTAL1. XTAL2 is left open (unconnected). The external clock frequency can be in the range of 0 - 40 MHz if the PLL is bypassed, and 4 - 40 MHz if the PLL is used. The oscillator can also be us ed in combination with a ceramic re sonator. The final circuitry must also be verified by the resonator vendor. Figure 3-16 shows the recommended external oscill ator circuitries fo r both operating modes, external crystal mode and extern al input clock mode. A block capacitor is recommended to be placed between VDDOSC/VDDOSC3 and VSSOSC. Figure 3-16 Oscillat or Circuitries Note: For crystal operation, it is st rongly recommended to measure the negative resistance in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the minimum and maximum values of the negative resistance specified by the crystal supplier. TC1163/TC1164 Oscillator TC1163/TC1164 Oscillator TC1163/TC1164 Oscillator Circuitry VDDOSC VSSOSC CX1 4 - 25 MHz CX2 XTAL1 XTAL2 VDDOSC VSSOSC XTAL1 XTAL2 External Clock Signal fOSC fOSC Fundamental Mode Crystal 4 - 40 MHz VDDOSC3 VDDOSC3 Crystal Frequency CX1, CX2

4 MHz

8 MHz

12 MHz

1) Note that these are evaluation start values! RX2 RX2 RQ

Functional DescriptionPreliminary Data Sheet 83 V1.0, 2008-04

3.23 Power Supply

The TC1163/TC1164 has several power supply lines for different voltage classes:

• 1.5 V: Core logic, oscillator and A/D converter supply
• 3.3 V: I/O ports, Flash memories, oscillator, and A/D converter supply with reference voltages Figure 3-17 shows the power supply concept of the TC1163/TC1164 with the power supply pins and its connections to the functional units. Figure 3-17 Power Supply Concept of TC1163/TC1164 TC1163/TC1164 TC1163/TC1164 PwrSupply Core Fl ash Memories VDD (1.5 V) PLL OSC VDDFL 3 3.3 V FADC VDDAF (1.5V) VSSAF VDDMF (3.3V) VSSMF 2 2 VFAREF (3.3V) VFAGND VSSA Ports VDDP (3.3 V) VSS ADC VDDM (3.3V) VSSM VAREF (3.3V) VAGND VDDA (1.5 V) VDDOSC3 (3.3 V) V DDOSC (1.5 V) V SSOSC

Functional DescriptionPreliminary Data Sheet 84 V1.0, 2008-04

3.24 Identification Register Values

Table 3-9 shows the address map and reset values of the TC1163/TC1164 Identification Registers. Table 3-9 TC1163/TC1164 Id entification Registers Short Name Address Reset Value Stepping SCU_ ID F000 0008 H 002C C002H – MANID F000 0070 H 0000 1820H – CHIPID F000 0074 H 0000 8B02H – RTID F000 0078 H 0000 0001H AA-Step 0000 0007H AB-Step SBCU_ID F000 0108 H 0000 6A0AH – STM_ID F000 0208 H 0000 C006H – CBS_ JDPID F000 0408 H 0000 6307H – MSC0_ ID F000 0808 H 0028 C001H – ASC0_ ID F000 0A08 H 0000 4402H – ASC1_ ID F000 0B08 H 0000 4402H – GPTA0_ ID F000 1808 H 0029 C004H – DMA_ID F000 3C08 H 001A C012H – CAN_ID1) F000 4008H 002B C012H – SSC0_ ID F010 0108 H 0000 4510H – FADC_ ID F010 0308 H 0027 C012H – ADC0_ID F010 0408 H 0030 C001H – MLI0_ ID F010 C008 H 0025 C006H – MCHK_ ID F010 C208 H 001B C001H – CPS_ID F7E0 FF08 H 0015 C006H – CPU_ID F7E1 FE18 H 000A C005H – PMU_ID F800 0508 H 002E C012H – FLASH_ID F800 2008 H 0041 C002H – DMI_ID F87F FC08 H 0008 C004H – PMI_ID F87F FD08 H 000B C004H – LBCU_ID F87F FE08 H 000F C005H – LFI_ID F87F FF08 H 000C C005H –

Functional DescriptionPreliminary Data Sheet 85 V1.0, 2008-04 1) The address and reset value of CAN_ID is not applicable to TC1163.

Electrical ParametersPreliminary Data Sheet 86 V1.0, 2008-04

4 Electrical Parameters

Chapter 4 provides the characteristics of the electrical par ameters which are implementation-specific for the TC1163/TC1164.

4.1 General Parameters

The general parameters are described here to aid the us ers in interpreting the parameters mainly in Section 4.2 and Section 4.3. The absolute maximum ratings and its operating conditions are provided for the appropriate setting in the TC1163/TC1164.

4.1.1 Parameter Interpretation

The parameters listed in this section par tly represent the characteristics of the TC1163/TC1164 and partly it s requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column “Symbol”:

• CC Such parameters indicate Controller Characteristics which are a distinctive feature of the TC1163/TC1164 and must be regarded for a system design.
• SR Such paramete rs indicate System Requirements which must provided by the microcontroller system in which the TC1163/TC1164 designed in.

Electrical ParametersPreliminary Data Sheet 87 V1.0, 2008-04

4.1.2 Pad Driver and Pad Classes Summary

This section gives an overview on the di fferent pad driver cl asses and its basic characteristics. More details (mainly DC parameters) are defined in Section 4.2.1. Table 4-1 Pad Driver an d Pad Classes Overview Class Power Supply Type Sub Class Speed Grade Load Leakage 1) 1) Values are for TJmax =1 2 5° C . Termination A 3.3V LVTTL I/O, LVTTL outputs (e.g. GPIO)

6 MHz 100 pF 500 nA No

(e.g. serial I/Os) MHz 50 pF 6 µAS e r i e s termination recommended (e.g. BRKIN, BRKOUT) MHz/ 50 pF 6 µAS e r i e s termination recommended (for f > 25 MHz) (e.g. Trace Clock) MHz 25 pF 6 µAS e r i e s termination recommended C 3.3V LVDS – 50 MHz – Parallel termination2), 100Ω± 10% 2) In applications where the LVDS pins are not used (d isabled), these pins must be either left unconnected, or properly terminated with the differential parallel termination of 100Ω± 10%. D – Analog inputs, refe rence voltage inputs

Electrical ParametersPreliminary Data Sheet 88 V1.0, 2008-04

4.1.3 Absolute Maximum Ratings

Table 4-2 shows the absolute maximum ratings of the TC1163/TC1164 parameters. Note: Stresses above thos e listed under “Absolute Ma ximum Ratings” may cause permanent damage to the device. This is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions ( VIN > related VDD or VIN < VSS) the voltage on the related VDD pins with respect to ground ( VSS) must not exceed the values defined by the absolute maximum ratings. Table 4-2 Absolute Maxi mum Rating Parameters Parameter Symbol Limit Values Unit Notes Min. Max. Ambient temperature TA SR -40 85 °C Under bias Storage temperature TST SR -65 150 °C– Junction temperature TJ SR -40 125 °C Under bias Voltage at 1.5 V power supply pins with respect to VSS 1) Applicable for VDD, VDDOSC, VDDPLL, and VDDAF. VDD SR – 2.25 V – Voltage at 3.3 V power supply pins with respect to VSS 2) Applicable for VDDP, VDDFL3, VDDM, and VDDMF. VDDP SR – 3.75 V – Voltage on any Class A input pin and dedicated input pins with respect to VSS VIN SR -0.5 VDDP + 0.5 or max. 3.7 VW h a t e v e r i s lower Voltage on any Class D analog input pin with respect to VAGND VAIN, VAREFx SR -0.5 VDDM + 0.5 or max. 3.7 VW h a t e v e r i s lower Voltage on any Class D analog input pin with respect to VSSAF VAINF, VFAREF SR -0.5 VDDMF + 0.5 or max. 3.7 VW h a t e v e r i s lower CPU & LMB Bus Frequency fCPU SR – 80 3) 3) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter parameters. MHz – FPI Bus Frequency fSYS SR – 80 3) MHz 4) 4) The ratio between fCPU and fSYS is fixed at 1:1.

Electrical ParametersPreliminary Data Sheet 89 V1.0, 2008-04

4.1.4 Operating Conditions

The following operating conditi ons must not be exceeded in order to ensure correct operation of the TC1163/TC1164. All parameters specified in the following table refer to these operating conditions, unless otherwise noted. Table 4-3 Operating Condition Parameters Parameter Symbol Limit Values Unit Notes Conditions Min. Max. Digital supply voltage1) VDD VDDOSC SR 1.42 1.58 2) V– VDDP VDDOSC3 SR 3.13 3.47 3) V For Class A pins (3.3V ± 5%) VDDFL3 SR 3.13 3.47 3) V– Digital ground voltage VSS SR 0 V – Ambient temperature under bias TA SR -40 +85 °C– Analog supply voltages – – – – See separate specification Page 4-95, Page 4-102 CPU clock fCPU SR – 4) 805) MHz – Short circuit current ISC SR -5 +5 mA 6) Absolute sum of short circuit currents of a pin group (see Table 4-4) Σ|ISC| SR – 20 mA See note 7) Absolute sum of short circuit currents of the device Σ|ISC| SR – 100 mA See note 7) Inactive device pin current IID SR -1 1 mA Voltage on all power supply pins V DDx =0 External load capacitance CL SR – See DC chara cterist ics pF Depending on pin class

Electrical ParametersPreliminary Data Sheet 90 V1.0, 2008-04 1) Digital supply voltages applied to the TC1163/TC1164 must be static regulated voltages which allow a typical voltage swing of ±5%. 2) Voltage overshoot up to 1.7 V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 µs and the cumulated summary of the pulses does not exceed 1 h. 3) Voltage overshoot to 4 V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 µs and the cumulated summary of the pulses does not exceed 1 h. 4) The TC1163/TC1164 uses a static design, so the mi nimum operation frequency is 0 MHz. Due to test time restriction no lower frequency boundary is tested, however. 5) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter parameters. 6) Applicable for digital outputs. 7) See additional document “TC1796 Pin Reliability in Overload“ for overload current definitions.

Electrical ParametersPreliminary Data Sheet 91 V1.0, 2008-04 Table 4-4 Pin Groups for Overload/Sho rt-Circuit Current Sum Parameter Group Pins 2 P0.[13:12], P0.[5:4], P2.[13:8], SOP0A, SON0, FCLP0A, FCLN0

5 HDRST

, PORST, NMI, TESTMODE, BRKIN, BRKOUT, BYPASS, TCK, TRST, TDO, TMS, TDI, P1.[7:4] 8 P5.[15:8]

Electrical ParametersPreliminary Data Sheet 92 V1.0, 2008-04

4.2 DC Parameters

The electrical characteristics of the DC Parameters are detailed in this section.

4.2.1 Input/Output Pins

Table 4-5 provides the characteristics of the input/output pins of the TC1163/TC1164. Table 4-5 Input/Output DC-Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions Min. Max. General Parameters Pull-up current 1) |IPUH|C C 1 0 1 0 0 µA VIN < VIHAmin; class A1/A2/Input pads. 20 200 µA VIN < VIHAmin; class A3/A4 pads. Pull-down current1) |IPDL|C C 1 0 1 5 0 µA VIN > VILAmax; class A1/A2/Input pads. 20 200 µA VIN > VILAmax; class A3/A4 pads. Pin capacitance1) (Digital I/O) CIO CC – 10 pF f = 1 MHz TA = 25 °C Input only Pads (VDDP = 3.13 to 3.47 V = 3.3V ±5%) Input low voltage class A1/A2 pins VILA SR -0.3 0.34 × VDDP Input high voltage class A1/A2 pins VIHA SR 0.64 × VDDP VDDP+ 0.3 or max. 3.6 V Whatever is lower Ratio VIL/VIH CC 0.53 – – – Input low voltage class A3 pins VILA3 SR – 0.8 V – Input high voltage class A3 pins VIHA3 SR 2.0 – V – Input hysteresis HYSA CC 0.1 × VDDP –V 2)5) Input leakage current IOZI CC – ±3000 ±6000 nA (( VDDP/2)-1) < VIN < ((VDDP/2)+1) otherwise3)

Electrical ParametersPreliminary Data Sheet 93 V1.0, 2008-04 Class A Pads (VDDP = 3.13 to 3.47 V = 3.3V ±5%) Output low voltage4) VOLA CC – 0.4 V IOL = 2 mA for strong driver mode, (Not applicable to Class A1 pins) IOL = 1.8 mA for medium driver mode, A2 pads IOL = 1.4 mA for medium driver mode, A1 pads IOL =3 7 0µA for weak driver mode Output high voltage3) VOHA CC 2.4 – V IOH = -2 mA for strong driver mode, (Not applicable to Class A1 pins) IOH = -1.8 mA for medium driver mode, A1/A2 pads IOH = -370 µA for weak driver mode VDDP - 0.4 –V IOH = -1.4 mA for strong driver mode, (Not applicable to Class A1 pins) IOH = -1 mA for medium driver mode, A1/A2 pads IOH = -280 µA for weak driver mode Input low voltage class A1/2 pins VILA SR -0.3 0.34 × VDDP Input high voltage class A1/2 pins VIHA SR 0.64 × VDDP VDDP + 0.3 or 3.6 V Whatever is lower Ratio VIL/VIH CC 0.53 – – – Input hysteresis HYSA CC 0.1 × VDDP –V 2)5) Table 4-5 Input/Output DC-Characteristics (cont’d)(Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions Min. Max.

Electrical ParametersPreliminary Data Sheet 94 V1.0, 2008-04 Input leakage current Class A2/3/4 pins IOZA24 CC – ±3000 ±6000 nA (( VDDP/2)-1) < VIN <((VDDP/2)+1) otherwise3) Input leakage current Class A1 pins IOZA1 CC – ±500 nA 0 V < VIN < VDDP Class C Pads (VDDP = 3.13 to 3.47 V = 3.3V ±5%) Output low voltage VOL CC 815 mV Parallel termination 100 Ω± 1%Output high voltage VOH CC 1545 mV Output differential voltage VOD CC 150 600 mV Output offset voltage VOS CC 1075 1325 mV Output impedance R0 CC 40 140 – Class D Pads see ADC Characteristics – – – – 1) Not subject to production test, verified by design / characterization. 2) The pads that have spike filter function in the input path: PORST , HDRST, NMI do not have hysteresis. 3) Only one of these parameters is tested, the other is verified by design characterization 4) Max. resistance between pin and next power supply pin 25 Ω for strong driver mode (verified by design characterization). 5) Function verified by design, value is not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching due to external system noise. Table 4-5 Input/Output DC-Characteristics (cont’d)(Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions Min. Max.

Electrical ParametersPreliminary Data Sheet 95 V1.0, 2008-04

4.2.2 Analog to Digital Converter (ADC0)

Table 4-6 provides the characteristics of the ADC module in the TC1163/TC1164. Table 4-6 ADC Characteristics (Operating Conditions apply) Parameter Symbol Limit Valu es Unit Test Conditions / RemarksMin. Typ. Max. Analog supply voltage VDDM SR 3.13 3.3 3.47 1) V– VDD SR 1.42 1.5 1.58 2) V Power supply for ADC digital part, internal supply Analog ground voltage VSSM SR -0.1 – 0.1 V – Analog reference voltage 17) VAREFx SR VAGNDx+ VDDM VDDM+ 0.05 1)3)4) Analog reference ground 17) VAGNDx SR VSSMx - 0.05V

0 VAREF

• 1 V Analog reference voltage range5)17) VAREFx- VAGNDx SR VDDM/2 VDDM + 0.05 Analog input voltage range VAIN SR VAGNDx –V AREFx V– VDDM supply current IDDM SR 2.5 4 mA rms Power-up calibration time tPUC CC – – 3840 fADC CLK Internal ADC clocks fBC CC 2 – 40 MHz fBC = fANA × 4 fANA CC 0.5 – 10 MHz fANA = fBC /4 Sample time tS CC 4 × (CHCONn.STC +2 ) × tBC µs– 8 × tBC –– µs

Electrical ParametersPreliminary Data Sheet 96 V1.0, 2008-04 Conversion time tC CC tS +4 0 × tBC +2 × tDIV µs For 8-bit conversion tS +4 8 × tBC +2 × tDIV µs For 10-bit conversion tS +5 6 × tBC +2 × tDIV µs For 12-bit conversion Total unadjusted error 5) TUE7) CC – – ±1 LSB For 8-bit conv. –– ±2 LSB For 10-bit conv. –– ±4 LSB For 12-bit conv. 8)9) –– ±8 LSB For 12-bit conv.10)9) DNL error11)5) TUEDNL CC – ±1.5 ±3.0 LSB For 12-bit conv. 12) INL error11)5) TUEINL CC – ±1.5 ±3.0 LSB For 12-bit conv. 12) Gain error11)5) TUEGAIN CC – ±0.5 ±3.5 LSB For 12-bit conv. 12) Offset error11)5) TUEOFF CC – ±1.0 ±4.0 LSB For 12-bit conv. 12) Input leakage current at analog inputs AN0, AN1 and AN31. see Figure 4-313) IOZ1 14) CC –1000 – 300 nA (0% VDDM) < VIN < (2% VDDM) –200 400 nA (2% VDDM) < VIN < (95% VDDM) –200 1000 nA (95% VDDM) < VIN < (98% VDDM) –200 3000 nA (98% VDDM) < VIN < (100% VDDM) Table 4-6 ADC Characteristics (cont’d) (Operating Conditions apply) Parameter Symbol Limit Valu es Unit Test Conditions / RemarksMin. Typ. Max.

Electrical ParametersPreliminary Data Sheet 97 V1.0, 2008-04 Input leakage current at analog inputs AN2 to AN30, see Figure 4-3 IOZ1 14) CC –1000 – 200 nA (0% VDDM) < VIN < (2% VDDM) –200 300 nA (2% VDDM) < VIN < (95% VDDM) –200 1000 nA (95% VDDM) < VIN < (98% VDDM) –200 3000 nA (98% VDDM) < VIN < (100% VDDM) Input leakage current at VAREF IOZ2 CC – – ±1 µA0 V < VAREF < VDDM, no conversion running Input current at VAREF 17) IAREF CC – 35 75 µA rms 0V< VAREF < VDDM 15) Total capacitance of the voltage reference inputs16)17) CAREFTOT CC – – 25 pF 9) Switched capacitance at the positive reference voltage input 17) CAREFSW CC – 15 20 pF 9)18) Resistance of the reference voltage input path 16) RAREF CC – 1 1.5 k Ω 500 Ohm increased for AN[1:0] used as reference input 9) Total capacitance of the analog inputs 16) CAINTOT CC – – 25 pF 6)9) Switched capacitance at the analog voltage inputs CAINSW CC – – 7 pF 9)19) Table 4-6 ADC Characteristics (cont’d) (Operating Conditions apply) Parameter Symbol Limit Valu es Unit Test Conditions / RemarksMin. Typ. Max.

Electrical ParametersPreliminary Data Sheet 98 V1.0, 2008-04 ON resistance of the transmission gates in the analog voltage path RAIN CC – 1 1.5 k Ω 9) ON resistance for the ADC test (pull-down for AIN7) RAIN7T CC 200 300 1000 Ω Test feature available only for AIN7 Current through resistance for the ADC test (pull- down for AIN7) IAIN7T CC – 15 rms peak mA Test feature available only for AIN7 1) Voltage overshoot to 4 V are permissible, provided the pulse duration is less than 100 µs and the cumulated summary of the pulses does not exceed 1 h. 2) Voltage overshoot to 1.7 V are permissible, provided the pulse duration is less than 100 µs and the cumulated summary of the pulses does not exceed 1 h. 3) A running conversion may become inexact in case of violating the normal operating conditions (voltage overshoot). 4) If the reference voltage VAREF increases or the VDDM decreases, so that VAREF =( VDDM + 0.05 V to VDDM + 0.07 V), then the accuracy of the ADC decreases by 4LSB12. 5) If a reduced reference voltage in a range of VDDM/2 to VDDM is used, then the ADC converter errors increase. If the reference voltage is reduced with the factor k (k<1), then TUE, DNL, INL Gain and Offset errors increase with the factor 1/k. If a reduced reference voltage in a range of 1 V to VDDM/2 is used, then there are additional decrease in the ADC speed and accuracy. 6) Current peaks of up to 6 mA with a duration of max. 2 ns may occur 7) TUE is tested at VAREF =3 . 3V , VAGND = 0 V and VDDM =3 . 3V 8) ADC module capability. 9) Not subject to production test, verified by design / characterization. 10) Value under typical application conditions due to integration (switching noise, etc.). 11) The sum of DNL/INL/Gain/Offset errors does not exceed the related TUE total unadjusted error. 12) For 10-bit conversions the DNL/INL/Gain/Offset error values must be multiplied with factor 0.25. For 8-bit conversions the DNL/INL/Gain/Offset error values must be multiplied with 0.0625. 13) The leakage current definition is a continuous function, as shown in Figure 4-3. The numerical values defined determine the characteristic points of the given continuous linear approximation - they do not define step function. 14) Only one of these parameters is tested, the other is verified by design characterization. Table 4-6 ADC Characteristics (cont’d) (Operating Conditions apply) Parameter Symbol Limit Valu es Unit Test Conditions / RemarksMin. Typ. Max.

Electrical ParametersPreliminary Data Sheet 99 V1.0, 2008-04 Figure 4-1 ADC0 Clock Circuit 15) IAREF_MAX is valid for the minimum specified conversion time. The current flowing during an ADC conversion with a duration of up to tC =2 5µs can be calculated with the formula IAREF_MAX = QCONV/tC. Every conversion needs a total charge of QCONV = 150pC from VAREF. All ADC conversions with a duration longer than tC = 25µs consume an IAREF_MAX = 6µA. 16) For the definition of the parameters see also Figure 4-2. 17) Applies to AIN0 and AIN1, when used as auxiliary reference inputs. 18) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead of this smaller capacitances are successively switched to the reference voltage. 19) The sampling capacity of the conversion C-Network is pre-charged to VAREF/2 before the sampling moment. Because of the parasitic elements the voltage measured at AINx is lower then VAREF/2. MCA04657_mod Programmable C lock D ivider (1:1) to (1:256) fBCfDIVFractional DividerfCLC fANA Programmable Counter Sample Time tS CON. CTC CHCONn. STC fTIMER Control/Status Logic Interrupt Logic External Trigger Logic External Multiplexer Logic Request Generation Logic A/D Converter Module Arbiter (1:20) C ontrol U nit (Tim er) 1:4

Electrical ParametersPreliminary Data Sheet 100 V1.0, 2008-04 Figure 4-2 ADC0 Input Circuits Reference Voltage Input Circuitry Analog Input Circuitry Analog_InpRefDiag REXT =VAIN CEXT RAIN, On CAINTOT - CAINSW CAINSW ANx VAREF RAREF, On CAREFTOT - CAREFSW CAREFSW VAGNDx VAREFx RAIN7TVAGNDx

Electrical ParametersPreliminary Data Sheet 101 V1.0, 2008-04 Figure 4-3 ADC0 Analog Inputs Leakage AN2 to AN30 VIN[VDDM%]300nA 1uA 3uA 2% 95% 100%98% Ioz1 AN0, AN1 and AN31 VIN[VDDM%]400nA -1uA 3uA 2% 95% 100%98% Ioz1 300nA -200nA 200nA 1uA -1uA -200nA

Electrical ParametersPreliminary Data Sheet 102 V1.0, 2008-04

4.2.3 Fast Analog to Digital Converter (FADC)

Table 4-7 provides the characteristics of the FADC module in the TC1163/TC1164. Table 4-7 FADC Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit Remarks ConditionsMin. Max. DNL error EDNL CC – ±1 LSB 12) INL error EINL CC – ±4 LSB 12) Gradient error1)12) EGRAD CC – ±3 % 2)With calibration, gain 1, 2 – ±5 % Without calibration gain 1, 2, 4 – ±6 % Without calibration gain 8 Offset error12) EOFF 3) CC – ±20 4) mV 2)With calibration –± 6 0 4) mV Without calibration Reference error of internal VFAREF/2 EREF CC – ±60 mV – Input leakage current at analog inputs AN32 to AN35. 5) see Figure 4-5 IOZ1 6) CC –1000 300 nA (0% VDDM) < VIN < (2% VDDM) –200 400 nA (2% VDDM) < VIN < (95% VDDM) –200 1000 nA (95% VDDM) < VIN < (98% VDDM) –200 3000 nA (98% VDDM) < VIN < (100% VDDM) Analog supply voltages VDDMF SR 3.13 3.47 7) V– VDDAF SR 1.42 1.58 8) V– Analog ground voltage VSSAF SR -0.1 0.1 V – Analog reference voltage VFAREF SR 3.13 3.47 7)9) V Nominal 3.3 V Analog reference ground VFAGND SR VSSAF - 0.05V VSSAF +0.05V Analog input voltage range VAINF SR VFAGND VDDMF V–

Electrical ParametersPreliminary Data Sheet 103 V1.0, 2008-04 Analog supply currents IDDMF SR – 9 mA – IDDAF SR – 17 mA 10) Input current at each VFAREF IFAREF CC – 150 µA rms Independent of conversion Input leakage current at VFAREF 11) IFOZ2 CC – ±500 nA 0 V < VIN < VDDMF Input leakage current at VFAGND IFOZ3 CC ±8 µA Conversion time tC CC – 21 CLK of fADC For 10-bit conv. Converter Clock fADC CC – 80 MHz – Input resistance of the analog voltage path (Rn, Rp) RFAIN CC 100 200 k Ω 12) Channel Amplifier Cutoff Frequency fCOFF CC 2 MHz – Settling Time of a Channel Amplifier after changing ENN or ENP tSET CC 5 µsec – 1) Calibration of the gain is possible for the gain of 1 and 2, and not possible for the gain of 4 and 8. 2) Callibration should be performed at each power-up. In case of continuous operation, callibration should be performed minimum once per week. 3) The offset error voltage drifts over the whole temperature range typically ±2 LSB. 4) Applies when the gain of the channel equals one. For the other gain settings, the offset error increases; it must be multiplied with the applied gain. 5) The leakage current definition is a continuous function, as shown in Figure 4-5. The numerical values defined determine the characteristic points of the given continuous linear approximation - they do not define step function. 6) Only one of these parameters is tested, the other is verified by design characterization. 7) Voltage overshoot to 4 V are permissible, provided the pulse duration is less than 100 µs and the cumulated summary of the pulses does not exceed 1 h. 8) Voltage overshoot to 1.7 V are permissible, provided the pulse duration is less than 100 µs and the cumulated sum of the pulses does not exceed 1 h. 9) A running conversion may become inexact in case of violating the normal operating conditions (voltage overshoots). 10) Current peaks of up to 40 mA with a duration of max. 2 ns may occur Table 4-7 FADC Characteristics (cont’d)(Operating Conditions apply) Parameter Symbol Limit Values Unit Remarks ConditionsMin. Max.

Electrical ParametersPreliminary Data Sheet 104 V1.0, 2008-04 The calibration procedure should run afte r each power-up, wh en all power supply voltages and the reference voltage have stabilized. The offset calibration must run first, followed by the gain calibration. Figure 4-4 FADC Input Circuits 11) This value applies in power-down mode. 12) Not subject to production test, verified by design / characterization. FADC_InpRefDiag RN FAINxN FAINxP VFAGND FADC Analog Input Stage RP VFAREF/2 VFAREF FADC Reference Voltage Input Circuitry VFAGND VFAREF IFAREF

Electrical ParametersPreliminary Data Sheet 105 V1.0, 2008-04 Figure 4-5 Analog Inputs AN32-AN35 Leakage AN32 to AN35 VIN[VDDM%]400nA -1uA 3uA 2% 95% 100%98% Ioz1 300nA -200nA 1uA

Electrical ParametersPreliminary Data Sheet 106 V1.0, 2008-04

4.2.4 Oscillator Pins

Table 4-8 provides the characteristics of the oscillator pins in the TC1163/TC1164. Note: It is strongly recommended to meas ure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits specified by the crystal supplier. Table 4-8 Oscillator Pins Characteristics (Operating Conditions apply) Parameter Symbol Limit values Unit Test Conditions Min. Max. Frequency Range fOSC CC 4 25 MHz – Input low voltage at XTAL11) 1) If the XTAL1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.3 × VDDOSC3 is necessary. VILX SR -0.2 0.3 × VDDOSC3 Input high voltage at XTAL11) VIHX SR 0.7 × VDDOSC3 VDDOSC3 + 0.2 Input current at XTAL1 IIX1 CC – ±25 µA0 V < VIN < VDDOSC3

Electrical ParametersPreliminary Data Sheet 107 V1.0, 2008-04

4.2.5 Temperature Sensor

Table 4-9 provides the characteristics of the temperature sensor in the TC1163/TC1164. Table 4-9 Temperature Sensor Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit Remarks Min. Max. Temperature Sensor Range TSR SR -40 150 °C – Start-up time after resets inactive tTSST SR 10 µs Temperature of the die at the sensor location TTS CC TTS = (ADC_Code - 487) × 0.396 - 40 °C 10-bit ADC result TTS = (ADC_Code - 1948) × 0.099 - 40 °C 12Bit ADC result Sensor Inaccuracy TTSA CC ±10 °C A/D Converter clock for DTS signal fANA SR – 10 MHz Conversion with ADC0

Electrical ParametersPreliminary Data Sheet 108 V1.0, 2008-04

4.2.6 Power Supply Current

Table 4-10 provides the characteristics of the power supply current in the TC1163/TC1164. Table 4-10 Power Supply Current (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions / Remarks Min. Typ. Max. PORST low current at VDD IDD_PORST CC – – 63 mA The PLL running at the base frequency PORST low current at VDDP IDDP_PORST CC – – 5 mA The PLL running at the base frequency Active mode core supply current1) 1) Infineon Power Loop: CPU running, all peripherals active . The power consumption of each custom application will most probably be lower than this value, but must be evaluated separately. IDD CC – – 260 mA fCPU = 80MHz fCPU/fSYS =1 : 1 Active mode analog supply current IDDAx; IDDMx CC – – – mA See ADC0/FADC Oscillator and PLL core power supply IDDOSC CC – – 5 mA – Oscillator and PLL pads power supply IDDOSC3 CC – – 3.6 2) 2) Estimated value; double-bonded at package level with V DDP. mA – FLASH power supply current IDDFL3 CC – – 45 mA – LVDS port supply (via VDDP)3) 3) In case the LVDS pads are disabled, the power consumption per pair is negligible (less than 1mA). ILVDS CC – – 25 mA LVDS pads active Maximum Allowed Power Dissipation4) 4) For the calculation of the junction to ambient thermal resistance R TJA, see Chapter 5.1. PDmax SR PD × RTJA < 40°C – At worst case, TA =8 5° C

Electrical ParametersPreliminary Data Sheet 109 V1.0, 2008-04

4.3 AC Parameters

All AC parameters are defined with the temperature compensation disabled, which means that pads are constantly kept at the maximum strength.

4.3.1 Testing Waveforms

The testing waveforms for rise /fall time, output delay an d output high impedance are shown in Figure 4-6, Figure 4-7 and Figure 4-8. Figure 4-6 Rise/Fall Time Parameters Figure 4-7 Testing Waveform, Output Delay Figure 4-8 Testing Waveform, Output High Impedance 10% 90% 10% 90% VSS VDDP tR rise_fall tF Mct04881_LL.vsd VDDE / 2 Test Points VDDE / 2 VSS VDDP MCT04880_LL VLoad + 0.1 V VOH - 0.1 VTiming Reference PointsVLoad - 0.1 V VOL - 0.1 V

Electrical ParametersPreliminary Data Sheet 110 V1.0, 2008-04

4.3.2 Output Rise/Fall Times

Table 4-11 provides the characteristics of the output rise/fal l times in the TC1163/TC1164. Table 4-11 Output Rise/Fall Times (Operating Conditions apply) Parameter Symbol Limit Va lues Unit Test Conditions Min. Max. Class A1 Pads Rise/fall times1) Class A1 pads 1) Not all parameters are subject to production test, but verified by design/characterization and test correlation. tRA1, tFA1 50 140 18000 150 550 65000 ns Regular (medium) driver, 50 pF Regular (medium) driver, 150 pF Regular (medium) driver, 20 nF Weak driver, 20 pF Weak driver, 150 pF Weak driver, 20 000 pF Class A2 Pads Rise/fall times Class A2 pads tFA2, tFA2 3.3 5.5 140 18000 150 550 65000 ns Strong driver, sharp edge, 50 pF Strong driver, sharp edge, 100pF Strong driver, med. edge, 50 pF Strong driver, soft edge, 50 pF Medium driver, 50 pF Medium driver, 150 pF Medium driver, 20 000 pF Weak driver, 20 pF Weak driver, 150 pF Weak driver, 20 000 pF Class A3 Pads Rise/fall times Class A3 pads tFA3, tFA3 2.5 ns 50 pF Class A4 Pads Rise/fall times 1) Class A4 pads tFA4, tFA4 2.0 ns 25 pF Class C Pads Rise/fall times Class C pads trC, tfC 2n s

Electrical ParametersPreliminary Data Sheet 111 V1.0, 2008-04

4.3.3 Power Sequencing

There is a restriction for the power sequ encing of the 3.3 V domain as shown in Figure 4-9. It must always be higher than 1.5 V domain - 0.5 V. The gray area shows the valid range for V 3.3V relative to an exemplary V 1.5V ramp. V DDP, VDDOSC3, VDDM, VDDMF, VDDFL3 belong to the 3.3 V domain. The VDDM and VDDMF subdomains are connected with antiparallel ESD protection di odes. There are no other su ch connections between the subdomains. VDD , VDDOSC and VDDAF belong to the 1.5 V domain. Figure 4-9 Power Up Sequence All ground pins VSS must be externally connected to one single star point in the system. The difference voltage between the ground pins must not exceed 200 mV. The PORST signal must be activated at latest before any power s upply voltage falls below the levels shown on the figure below. In this case, only the memory row of a Flash memory that was the target of the write at the moment of the power loss will contain unreliable cont ent. Additionally, the PORST signal should be activated as soon as possible. The sooner the PORST signal is activated, the less time the system operates outside of the normal operating power supply range. PowerSeq 1.5V 3.3V V1.5 V3.3 V3.3 > V1.5 - 0.5V Time Power Supply Voltage Valid area for V3.3 Valid area for V 3.3 Time VDDP (3.3V) PORST

Electrical ParametersPreliminary Data Sheet 112 V1.0, 2008-04 Figure 4-10 Power Down / Power Loss Sequence VDDP Power Supply Voltage tPORST VPORST3.3 VDDP -5% -12% 3.3V 3.13V 2.9V VDDPmin t tPORST t VDD -5% -12% 1.5V 1.42V 1.32V VDD VPORST1.5min VDDmin PowerDown3.3_1.5_reset_only_LL.vsd

Electrical ParametersPreliminary Data Sheet 113 V1.0, 2008-04

4.3.4 Power, Pad and Reset Timing

Table 4-12 provides the characteristics of the power, pad and reset timing in the TC1163/TC1164. Table 4-12 Power, Pad and Reset Timing Parameters Parameter Symbol Limit Values Unit Min. Max. Min. VDDP voltage to ensure defined pad states1) 1) This parameter is valid under assumption that PORST signal is constantly at low-level during the power- up/power-down of the VDDP. VDDPPA CC 0.6 – V Oscillator start-up time2) 2) This parameter is verified by device characterization. The external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended and specified by crystal suppliers. tOSCS CC – 10 ms Minimum PORST active time after power supplies are stable at operating levels tPOA SR 10 – ms HDRST pulse width tHD CC 1024 clock cycles3) 3) Any HDRST activation is internally prolonged to 1024 FPI bus clock (fSYS) cycles. – fSYS PORST rise time tPOR SR – 50 ms Setup time to PORST rising edge4) tPOS SR 0 – ns Hold time from PORST rising edge4) tPOH SR 100 – ns Setup time to HDRST rising edge5) tHDS SR 0 – ns Hold time from HDRST rising edge5) tHDH SR 100 + (2 × 1/fSYS) –n s Ports inactive after PORST reset active6)7) tPIP CC – 150 ns Ports inactive after HDRST reset active8) tPI CC – 150 + 5 × 1/fSYS ns Minimum VDDP PORST activation threshold.9) VPORST3.3 SR – 2.9 V Minimum VDD PORST activation threshold. 9) VPORST1.5 SR – 1.32 V Power-on Reset Boot Time10) tBP CC 2.15 3.50 ms Hardware/Software Reset Boot Time at fCPU=80MHz11) tB CC 500 800 µs

Electrical ParametersPreliminary Data Sheet 114 V1.0, 2008-04 Figure 4-11 Power, Pad and Reset Timing 4) Applicable for input pins TESTMODE , TRST, BRKIN, and TXD1A with noise suppression filter of PORST switched-on (BYPASS = 0). 5) The setup/hold values are applicable for Port 0 and Port 4 input pins with noise suppression filter of HDRST switched-on (BYPASS = 0), independently whether HDRST is used as input or output. 6) Not subject to production test, verified by design / characterization. 7) This parameter includes the delay of the analog spike filter in the PORST pad. 8) Not subject to production test, verified by design / characterization. 9) In case of power loss during internal flash write, prevents Flash write to random address. 10) Booting from Flash, the duration of the boot-time is defined between the rising edge of the PORST and the moment when the first user instruction has entered the CPU and its processing starts. 11) Booting from Flash, the duration of the boot time is defined between the following events: 1. Hardware reset: the falling edge of a short HDRST pulse and the moment when the first user instruction has entered the CPU and its processing starts, if the HDRST pulse is shorter than 1024 × TSYS. If the HDRST pulse is longer than 1024 × TSYS, only the time beyond the 1024 × TSYS should be added to the boot time (HDRST falling edge to first user instruction). 2. Software reset: the moment of starting the software reset and the moment when the first user instruction has entered the CPU and its processing starts reset_beh 1) as programmed VDDP PORST HDRST Pads Pad- state undefined tpi VDD VDDPPA VDDPPA Pad- state undefined 2) Tri-state, pull device active thd VDDPR OSC toscs 1) 2) 1) 2)2) tPOA tPOA thd

Electrical ParametersPreliminary Data Sheet 115 V1.0, 2008-04

4.3.5 Phase Locked Loop (PLL)

Section 4.3.5 provides the characteristics of the PLL parameters and its operation in the TC1163/TC1164. Note: All PLL characteristics de fined on this and t he next page are ve rified by design characterization. Phase Locked Loop Operation When PLL operation is enabled and configured, the PLL clock fVCO (and with it the CPU clock fCPU) is constantly adjusted to the sele cted frequency. The relation between fVCO and fSYS is defined by: fVCO =K × fCPU. The PLL causes a jitter of fCPU and affects the clock outputs TRCLK and SYSCLK (P4.3) which are derived from the PLL clock fVCO. There are two formulas that de fine the (absolute) approximate maximum value of jitter DP in ns dependent on the K-factor, the CPU clock frequency fCPU i n M H z , a n d t h e number P of consecutive fCPU clock periods. (4.1) (4.2) K : K-Divider Value P : Number of fCPU periods DP : Jitter in ns fCPU : CPU frequency in MHz Table 4-13 PLL Parameters (Operating Conditions apply) Parameter Symbol Limit Values Unit Min. Max. Accumulated jitter DP See Figure 4-12 – VCO frequency range fVCO 400 500 MHz 500 600 MHz 600 700 MHz PLL base frequency1) 1) The CPU base frequency which is selected after reset is calculated by dividing the limit values by 16 (this is the K factor after reset). fPLLBASE 140 320 MHz 150 400 MHz 200 480 MHz PLL lock-in time tL – 200 µs P K 900<× Dp ns[] 5P× ±= P K 900≥× Dp ns[] 4500 ±=

Electrical ParametersPreliminary Data Sheet 117 V1.0, 2008-04 Figure 4-13 Approximated Maximum Accumulated PLL Jitter for Typical CPU Clock Frequencies fCPU (detail) Note: The maximum peak-to-p eak noise on the main osc illator and PLL power supply (measured between V DDOSC and V SSOSC) is limited to a peak -to-peak voltage of VPP = 10 mV. This condition can be achieved by appropriate blocking to the supply pins and using PCB supply and ground planes. ±0.90 ±1.00 ±1.10 ±1.40 23 45 TC1163/TC1164 PLL Jitter (preliminary ) ±1.20 ±1.30Jitter [ns] P [Periods] fCPU = 40 MHz fCPU = 66 MHz fCPU = 80 MHz TC 1163/TC 1164 PLL J itter -D etail

Electrical ParametersPreliminary Data Sheet 118 V1.0, 2008-04

4.3.6 Debug Trace Timing

VSS = 0 V; VDDP = 3.13 to 3.47 V (Class A); TA = -40 °C to +85 °C; CL (TRCLK) = 25 pF; CL (TR[15:0]) = 50 pF Figure 4-14 Debug Trace Timing Table 4-14 Debug Trace Timing Parameter 1) 1) Not subject to production test, verified by design/characterization. Parameter Symbol Limit Values Unit Min. Max. TR[15:0] new state from TRCLK t9 CC -1 4 ns Trace_Tmg TRCLK TR[15:0] Old State New State

Electrical ParametersPreliminary Data Sheet 119 V1.0, 2008-04

4.3.7 Timing for JTAG Signals

(Operating Conditions apply, CL = 50 pF) Figure 4-15 TCK Clock Timing Table 4-15 TCK Clock Timing Parameter Parameter Symbol Limit Values Unit Min. Max. TCK clock period1) 1) fTCK should be lower or equal to fSYS tTCK SR 25 – ns TCK high time t1 SR 10 – ns TCK low time t2 SR 10 – ns TCK clock rise time t3 SR – 4 ns TCK clock fall time t4 SR – 4 ns TCK

0.9 VDD

0.1 VDD

0.5 VDD

Electrical ParametersPreliminary Data Sheet 120 V1.0, 2008-04 Table 4-16 JTAG Timing Parameter 1) 1) Not subject to production test, verified by design / characterization. Parameter Symbol Limit Values Unit Test Conditions / RemarksMin. Max. TMS setup to TCK t1 SR 6.0 – ns – TMS hold to TCK t2 SR 6.0 – ns – TDI setup to TCK t1 SR 6.0 – ns – TDI hold to TCK t2 SR 6.0 – ns – TDO valid output from TCK2) 2) The falling edge on TCK is used to capture the TDO timing. t3 CC – 14.5 ns C L = 50 pF3)4) 3) By reducing the load from 50 pF to 20 pF, a reduction of approximately 1.0 ns in timing is expected. 4) By reducing the power supply range from +/-5 % to +5/-2 %, a reduction of approximately 0.5 ns in timing is expected. 3.0 – C L = 20 pF TDO high impedance to valid output from TCK2) t4 CC – 15.5 ns C L = 50 pF3)4) TDO valid output to high impedance from TCK2) t5 CC – 14.5 ns C L = 50 pF4)

Electrical ParametersPreliminary Data Sheet 121 V1.0, 2008-04 Figure 4-16 JTAG Timing Note: The JTAG module is fully compliant with IEEE1149.1-200 0 with JTAG clock at 20 MHz. The JTAG clock at 40 MHz is possible with the modified timing diagram shown in Figure 4-16. TMS TDI TCK TDO t1 t2 t1 t2 t4 t3 t5

Electrical ParametersPreliminary Data Sheet 122 V1.0, 2008-04

4.3.8 Peripheral Timings

Section 4.3.8 provides the charac teristics of the peri pheral timings in the TC1163/TC1164. Note: Peripheral timing parameters are not subject to production test. They are verified by design/characterization.

4.3.8.1 Micro Link Interface (MLI) Timing

Table 4-17 provides the characteristics of the MLI timing in the TC1163/TC1164. Table 4-17 MLI Timing (Operating Conditions apply, CL = 50 pF) Parameter Symbol Limit Values Unit Min. Max. TCLK clock period1)2) 1) TCLK signal rise/fall times are the same as the A2 Pads rise/fall times. 2) TCLK high and low times can be minimum 1 × TMLI t30 CC 2 3) 3) TMLImin = TSYS = 1/fSYS. When fSYS = 80MHz, t30 = 25ns –1 / fSYS RCLK clock period t31 SR 1 – 1/ fSYS MLI outputs delay from TCLK t35 CC 0 8 ns MLI inputs setup to RCLK t36 SR 4 – ns MLI inputs hold to RCLK t37 SR 4 – ns RREADY output delay from RCLK t38 CC 0 8 ns

Electrical ParametersPreliminary Data Sheet 123 V1.0, 2008-04 Figure 4-17 MLI Interface Timing Note: The generation of RREADYx is in t he input clock domain of the receiver. The reception of TREADYx is asynchronous to TCLKx. MLI_Tmg_1.vsd TDATAx TVALIDx t35 t35 t37 t36 TCLKx 0.1 VDDP

0.9 VDDP

Electrical ParametersPreliminary Data Sheet 124 V1.0, 2008-04

4.3.8.2 Micro Second Channel (MSC) Interface Timing

Table 4-18 provides the characteristics of the MSC timing in the TC1163/TC1164. Figure 4-18 MSC Interface Timing Note: The data at SOP should be sampled with the falling edge of FCLP in the target device. Table 4-18 MSC Interface Timing (Operating Conditions apply, CL = 50 pF) Parameter Symbol Limit Values Unit Min. Max. FCLP clock period1)2) 1) FCLP signal rise/fall times are the same as the A2 Pads rise/fall times. 2) FCLP signal high and low can be minimum 1 × TMSC. t40 CC 2 × TMSC 3) TMSCmin = TSYS = 1/fSYS. When fSYS = 80MHz, t40 = 25ns –n s SOP/ENx outputs delay from FCLP t45 CC -10 10 ns SDI bit time t46 SR 8 × TMSC –n s SDI rise time t48 SR 100 ns SDI fall time t49 SR 100 ns MSC_Tmg_1.vsd t45 t45 t40

0.1 VDDP

Electrical ParametersPreliminary Data Sheet 125 V1.0, 2008-04

4.3.8.3 Synchronous Serial Channel (SSC) Master Mode Timing

Table 4-19 provides the characteristics of the SSC timing in the TC1163/TC1164. Figure 4-19 SSC Master Mode Timing Table 4-19 SSC Master Mode Timing (Operating Conditions apply, CL = 50 pF) Parameter Symbol Limit Values Unit Min. Max. SCLK clock period1)2) 1) SCLK signal rise/fall times are the same as the A2 Pads rise/fall times. 2) SCLK signal high and low times can be minimum 1 × TSSC. t50 CC 2 × TSSC 3) TSSCmin = TSYS = 1/fSYS. When fSYS = 80 MHz, t50 = 25ns –n s MTSR/SLSOx delay from SCLK t51 CC 0 8 ns MRST setup to SCLK t52 SR 10 – ns MRST hold from SCLK t53 SR 5 – ns SSC_Tmg_1.vsd SCLK1)2) MTSR1) t51 t51 MRST1) t53 Data valid t52 SLSOx2) t51 1) This timing is based on the following setup: CON.PH = CON.PO = 0. 2) The transition at SLSOx is based on the following setup: SSOTC.TRAIL = 0 and the first SCLK high pulse is in the first one of a transmission. t50

Package and ReliabilityPreliminary Data Sheet 126 V1.0, 2008-04

5 Package and Reliability

Chapter 5 provides the information of the TC1163/TC1164 packa ge and reliability section.

5.1 Package Parameters (PG-LQFP-176-2)

Table 5-1 provides the thermal characteristics of the package. Table 5-1 Thermal Character istics of the Package Parameter Symbol Limit Values Unit Notes Min. Max. Thermal resistance junction case top1) 1) The thermal resistances between the case top and the ambient (R TCAT), the leads and the ambient (RTLA) are to be combined with the thermal resistances between the junction and the case top (RTJCT ), the junction and the leads (RTJL) given above, in order to calculate the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between the case top and the ambient (R TCAT ), the leads and the ambient (RTLA) depend on the external system (PCB, case) characteristics, and are under user responsibility. The junction temperature can be calculated using the following equation: TJ=TA+RTJA × PD, where the RTJA is the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA can be obtained from the upper four partial thermal resistances. RTJCT CC – 5.4 K/W – Thermal resistance junction leads1) RTJL CC – 21.5 K/W –

Package and ReliabilityPreliminary Data Sheet 127 V1.0, 2008-04

5.2 Package Outline

Figure 5-1 shows the package outlines of the TC1163/TC1164. Figure 5-1 Package Outl ines PG-LQFP-176-2 PG-LQFP-176-2 Plastic Low Profile Quad Flat Package You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mmSMD = Surface Mounted Device

Package and ReliabilityPreliminary Data Sheet 128 V1.0, 2008-04

5.3 Flash Memory Parameters

The data retention time of the TC1163/TC1164’s Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed. Table 5-2 Flash Parameters Parameter Symbol Limit Values Unit Notes Min. Max. Program Flash Retention Time, Physical Sector1)2) 1) Storage and inactive time included. 2) At average weighted junction temperature T J = 100 °C. tRET 15 – years Max. 1000 erase/program cycles Program Flash Retention Time, Logical Sector1)2) tRETL 15 – years Max. 50 erase/program cycles Data Flash Endurance (128 Kbyte) NE 15 000 – – Max. data retention time 2 years Data Flash Endurance, EEPROM Emulation (8 × 16 Kbyte) NE8 120 000 – – Max. data retention time 2 years Programming Time per Page3) 3) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The reprogramming takes additional 5ms. tPR –5 m s – Program Flash Erase Time per 256-Kbyte sector tERP –5 s fCPU = 80 MHz Data Flash Erase Time per 16-Kbyte sector tERD –0 . 6 2 5 s fCPU = 80 MHz Wake-up time tWU 4300 × 1/fCPU +4 0µs

Package and ReliabilityPreliminary Data Sheet 129 V1.0, 2008-04

5.4 Quality Declaration

Table 5-3 shows the characteristics of the quality parameters in the TC1163/TC1164. Note: Information about sold ering can be found on the “package” information page under: http://www.infineon.com/products. Table 5-3 Quality Parameters Parameter Symbol Limit Values Unit Notes Min. Max. ESD susceptibility according to Human Body Model (HBM) VHBM – 2000 V Conforming to EIA/JESD22- A114-B ESD susceptibility of the LVDS pins VHBM1 –5 0 0 V – ESD susceptibility according to Charged Device Model (CDM) pins VCDM – 500 V Conforming to JESD22-C101-C Moisture Sensitivity Level (MSL) – – 3 – Conforming to J-STD-020C for 240°C

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