TC1130

TC1130_08 INFINEON | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 114

Technical content

Data Sheet, V1.1, Dec 2008 TC1130 32-Bit Single-Chip Microcontroller Microcontrollers Never stop thinking.

Published by Infineon Technologies AG, St.-Martin-Strasse 53,

81669 München, Germany

© Infineon Technologies AG 2008. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Data Sheet, V1.1, Dec 2008 TC1130 32-Bit Single-Chip Microcontroller Microcontrollers Never stop thinking.

Controller Area Network (CAN): License of Robert Bosch GmbH TC1130 Data Sheet Revision History: 2008-12 V1.1 Previous Version: V1.0, 2005-02 Page Subjects (major cha nges since last revision) 77, 78, 79 ,81, 82 Added “Operating Conditons apply” statement We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com

Data Sheet I-1 V1.1, 2008-12

Data Sheet I-2 V1.1, 2008-12

Data Sheet 1 V1.1, 2008-12 TC113032-Bit Single-Chip Microcontroller TriCore™ Family

1 Summary of Features

• High Performance 32-bit TriCore™ V1.3 CPU with 4-Stage Pipeline
• Floating Point Unit (FPU)
• Dual Issue super-sca lar implementation – MAC Instruction maximum triple issue
• Circular Buffer and bit-reverse add ressing modes for DSP algorithms
• Very fast interrupt response time
• Hardware controlled context switch for task switch and interrupts
• Memory Management Unit (MMU)
• On-chip Memory – 28-Kbyte Data Memory (SPRAM) – 32-Kbyte Code Memory (SPRAM) – 16-Kbyte Instruction Cache (ICACHE) – 4-Kbyte Data Cache (DCACHE) – 64-Kbyte SRAM Data Memory Unit (DMU) – 16-Kbyte Boot ROM
• On-chip Bus Systems – 64-bit High Performance Local Memory Bus (LMB) for fast access between caches and on-local memories and FPI Interface – On-chip Flexible Peripheral Interconn ect Bus (FPI) for interconnections of functional units
• DMA Controller with 8 channel s for data transfer operations between peripheral units and memory locations
• Two high speed Micro Link Interfaces (MLI0/1) for controller communication and emulation
• Flexible External Bus Inte rface Unit (EBU) to access external data memories
• One Multifunctional General Purpose Timer Unit (GPTU) with three 32-bit timer/ counters
• Two Capture and Compare units (CCU60/1) for PWM signal generation, each with – 3-channel, 16 bit Capt ure and Compare unit – 1-channel, 16 bit Compare unit
• Three Asynchronous/Synchronous Serial Channels (ASC0/1/2) with baud-rate generator, parity, framing an d overrun error detection, su pport FIFO and IrDA data transmission
• Two High Speed Synchronous Serial Channels (SSC0/1) with programmable data length, FIFO support and shift direction

Data Sheet 2 V1.1, 2008-12

• One MultiCAN module with four CAN nodes and 128 message buffers for high efficiency data handling
• Fast Ethernet Controller with 10/100 Mb it/sec MII-Based physical devices support
• USB module with compliance to USB Specification Revisi on 1.1, with support for

1.5 MBaud to 12 MBaud devices

• Inter-IC (IIC) module wi th two physical IIC buses
• Digital I/O ports with 3.3 V I/O capabilities
• Level 2 On-chip Debug Support
• Power Management System
• Clock Generation Unit with PLL
• Maximum CPU and Bus clock frequency at 150 MHz without MMU and 120 MHz with MMU
• Ambient temperature under bias: -40° to +85°C
• P-LBGA-208 package

General Device Information Data Sheet 3 V1.1, 2008-12

2 General Device Information

2.1 Block Diagram

Figure 2-1 TC1130 Block Diagram C e dar_ BLK B oo t-R O M 16 KB ASC0 FIFO , IrDA ASC 1 FIFO, Ir DA AS C 2 FI F O, Ir DA SSC0 SSC1 IIC Ch an n els SCU (P W R ) Power Ma na ge me nt, Wat ch dog T i mer , Re set SB CU FPI BUS Ce rbe rus JT AG PLL TriCor eTM 1M CPU FPU OCDS PMI ( Pro g r am Me mo ry Int er f ac e)

32 KB Scr atch Pad RAM

16 KB In str uctio n Ca ch e

(Da t a Me mo r y In t er f ac e)

28 KB Scra tch Pad R AM

4 KB Data Cache

L MB (Local Mem ory B us) 64 Bit Ex ternal Interrupt s 128 64 VDD 1 .5- 3. 3 V VSS TC1130 Block Diagram STMUSB Ethernet MultiCAN 4 no de s CC U6 CC U 6 1CCU6 0 ML I 1 MLI0Mem Ch eck er 2841 1 2 213 161616168 8 3633788 8 CPS EBU AD [3 1:0] EBU_ Co nt ro l

24 A[ 23:0]

FPI Bus ( Fl ex i bl e Pe r iph er a l In t er f a ce ) , 3 2 Bi t D MA Bus, 32 Bit SMIF DMA ch an nel s GPT U

3 Ti mer s

General Device Information Data Sheet 4 V1.1, 2008-12

2.2 Logic Symbol

Figure 2-2 TC1130 Logic Symbol MC B04945mod Port 0 16-Bit WAI T RD/WR RD HWCFG[0:2] NMI HDRST PORST VSS VDDOSC3 RAS ALE EBU Cont rol Alternate Functions Digital Circuitry Power Supply General Control CAS CS[0:3] 4 CSCOMB SDCLKI CKE MR/ W BFCLKI BAA ADV SDCLKO MI I _ TxCL K MII_RxCLK MI I _ MDI O XTAL1 XTAL2 Ethernet Clock VSSOSC3 Oscillator 6VDD VDDP TDI TCK TRST A[0:23] B C[0:3] A D[0:31] Port 1 16-Bit Port 2 16-Bit Port 3 16-Bit Port 4 8-Bit GPTU, MultiCAN, SSC0/1, ASC1/2, CCU60, M LI0, EBU, S CU, E xternal Interrupts SSC0/1, M ultiCAN, Ethernet, EBU, SCU, OCDS ASC0/1/2, SSC0/1, IIC, CCU60, EBU, SCU SSC0/1, CCU61, MLI1, OCDS TDO OCDS / JTAG Control USB, MLI 0, SCU BFCLKO TC1130 TMS BRKI N TRCLK USB VDDOSC VSSOSC

General Device Information Data Sheet 5 V1.1, 2008-12

2.3 Pin Configuration

Figure 2-3 TC1130 Pins: P-BGA-208 Package (top view) MCP04950mod ABCDEF G HJ P2. 7 KL M N VDD OSC3 PR VSS T Reser vedP3. 1016 15 P0. 9P0. 1 14 P1. 10 V SS Reser ved Reser ved ABCD E F G H JK L M NP RT V SSV DD VDD VDDV SSV SSV DD V DD VDDV SSV SS V DD V SS V SS VDD CFG 1 HW CFG 0 P2. 5 P2. 3 P0. 10 D+ P1. 6 P1. 3 P1. 1 P1. 2 BAA ADV P1. 4 P1. 0 A17 A18 A19 A20 A16 WAI T CS2 CS 0 CS 1AD0CS 3A15 BC 3 AD 1BC 2 AD 16 BC 1 AD 2 AD 3 RA S BC 0 AD 17 AD 4 CA S AD 18 AD 19 AD 20 V DDP AD 5 AD 21 AD 7 AD 25 AD 6 AD 22 AD 8 AD 9 Reser ved AD 23 AD 24 BFC LKI AD 28 AD 29 A14 CKE V DDP A23 A22V DDP V SS VSS A21V SS TCKP0. 5P2. 0P2. 6 P0. 0 TRSTP0. 4 P4. 3 HW CF G2P4. 6P4. 4 TDOP0. 6P0. 2P0. 7 P0. 11 TMSP4. 1P0. 12 P0. 14 TR C LKP4. 0P0. 13 P4. 2 NMIP4. 5P0. 15 HDRS T P4. 7 PO R STBR KI N AD 11 AD 12 AD 15 AD 30 A10 A11 A12 A13 CS COMB MR/W ALE RD/W R AD 26 AD 27 AD 31 AD14 A5 A6 A7 A8 A9 RD MII_ RX CLK MII_ TXC LK A3 MII_ MDIOA4A2A1A0SDCLKISDCL KOAD 13AD 10BFC LKO 208-Pin P-LBGA Package Pin Configuration (top view) for TC1130 VSS P2. 1

General Device Information Data Sheet 6 V1.1, 2008-12

2.4 Pin Definitions and Functions

Table 2-1 Pin Definitions and Functions Symbol Pin In Out PU/ PD1) Functions P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9 P0.10 P0.11 N11 P15 P10 M15 R11 R12 R10 N10 R13 R15 R14 I/O I/O I/O I/O O I/O I/O I/O O I/O I O I/O I I O I/O I/O I O I/O O I I O O I I I I O O I O PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC Port 0 Port 0 is a 16-bit bi-directional general purpose I/O port which can be alternatively used for GPTU, MultiCAN, ASC1/2, SSC0/1, MLI0, EBU and SCU. GPTU_0 GPTU input/output line 0 RXD1B ASC1 receiver input/output B GPTU_1 GPTU input/output line 1 TXD1B ASC1 transmitter output B GPTU_2 GPTU input/output line 2 RXD2B ASC2 receiver input/output B GPTU_3 GPTU input/output line 3 TXD2B ASC2 transmitter output B GPTU_4 GPTU input/output line 4 SLSI1 SSC1 Slave Select input BREQ EBU Bus Request Output GPTU_5 GPTU input/output line 5 HOLD EBU Hold Request Input CC60_T12HR CCU60 Timer 12 hardware run BRKOUT _B OCDS Break Out B GPTU_6 GPTU input/output line 6 HLDA EBU Hold Ackn owledge Input/Output CC60_T13HR CCU60 Timer 13 hardware run SLSO0_0 SSC0 Slave Select output 0 GPTU_7 GPTU input/output line 7 SLSO1_0 SSC1 Slave Select output 0 RXDCAN0_A CAN node 0 receiver input A REQ0 External Trigger Input 0 TCLK0A MLI0 transmit channel clock output A TXDCAN0_A CAN node 0 tr ansmitter output A TREADY0A MLI0 transmit channel ready input A REQ1 External Trigger Input 1 RXDCAN1_A CAN node 1 receiver input A REQ2 External Trigger Input 2 TVALID0A MLI0 transmit channel valid output A TXDCAN1_A CAN node 1 tr ansmitter output A REQ3 External Trigger Input 3 TDATA0A MLI0 transmit channel data output A

General Device Information Data Sheet 7 V1.1, 2008-12 P0.12 P0.13 P0.14 P0.15 I I I O I O I I I O I I PUC PUC PUC PUC RXDCAN2 CAN node 2 receiver input RCLK0A MLI0 receive channel clock input A REQ4 External Trigger Input 4 TXDCAN2 CAN node 2 transmitter output REQ5 External Trigger Input 5 RREADY0A MLI0 receive channel ready output A RXDCAN3 CAN node 3 receiver input REQ6 External Trigger Input 6 RVALID0A MLI0 receive channel valid input A TXDCAN3 CAN node 3 transmitter output REQ7 External Trigger Input 7 RDATA0A MLI0 receive c hannel data input A Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out PU/ PD Functions

General Device Information Data Sheet 8 V1.1, 2008-12 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 D11 C12 D12 B12 C11 C13 A12 I/O O I I O O I O O O I I O O O I O O I O O I O O I O PUC PUC PUC PUC PUC PUC PUC Port 1 Port 1 serves as 16-bit bi-directional general purpose I/O port which can be used for input/output for Ethernet controller, MultiCAN, CAN, OCDS L2, SSC0/1, EBU and SCU. MII_TXD0 Ethernet controller transmit data output line 0 RXDCAN0_B CAN node 0 receiver input B SWCFG0 Software configuration 0 OCDSA_0 OCDS L2 Debug Line A0 MII_TXD1 Ethernet controller transmit data output line 1 SWCFG1 Software configuration 1 TXDCAN0_B CAN node 0 tr ansmitter output B OCDSA_1 OCDS L2 Debug Line A1 MII_TXD2 Ethernet controller transmit data output line 2 RXDCAN1_B CAN node 1 receiver input B SWCFG2 Software configuration 2 OCDSA_2 OCDS L2 Debug Line A2 MII_TXD3 Ethernet controller transmit data output line 3 TXDCAN1_B CAN node 1 tr ansmitter output B SWCFG3 Software configuration 3 OCDSA_3 OCDS L2 Debug Line A3 MII_TXER Ethernet controller transmit error output line SWCFG4 Software configuration 4 OCDSA_4 OCDS L2 Debug Line A4 MII_TXEN Ethernet controller transmit enable output line SWCFG5 Software configuration 5 OCDSA_5 OCDS L2 Debug Line A5 MII_MDC Ethernet controller management data clock output line SWCFG6 Software configuration 6 OCDSA_6 OCDS L2 Debug Line A6 Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out PU/ PD Functions

General Device Information Data Sheet 9 V1.1, 2008-12 P1.7 P1.8 P1.9 P1.10 P1.11 P1.12 P1.13 P1.14 P1.15 B13 A13 A14 B14 C14 F13 E14 D14 F14 I I O I I O I I O I I O I I O O I I O O I I O O I O I O I O I O PUC PUC PUC PUC PUC PUC PUC PUC PUC MII_RXDV Ethernet Contro ller receive data valid input line SWCFG7 Software configuration 7 OCDSA_7 OCDS L2 Debug Line A7 MII_CRS Ethernet Contro ller carrier input line SWCFG8 Software configuration 8 OCDSA_8 OCDS L2 Debug Line A8 MII_COL Ethernet Controlle r collision input line SWCFG9 Software configuration 9 OCDSA_9 OCDS L2 Debug Line A9 MII_RXD0 Ethernet Contro ller receive data input line 0 SWCFG10 Software configuration 10 OCDSA_10 OCDS L2 Debug Line A10 MII_RXD1 Ethernet Contro ller receive data input line 1 SWCFG11 Software configuration 11 OCDSA_11 OCDS L2 Debug Line A1 SLSO0_1 SSC0 Slave Select output 1 MII_RXD2 Ethernet Contro ller receive data input line 2 SWCFG12 Software configuration 12 OCDSA_12 OCDS L2 Debug Line A12 SLSO1_1 SSC1 Slave Select output 1 MII_RXD3 Ethernet Contro ller receive data input line 3 SWCFG13 Software configuration 13 OCDSA_13 OCDS L2 Debug Line A13 SLSO0_2 SSC0 Slave Select output 2 MII_RXER Ethernet Contro ller receive error input line SLSO1_2 SSC1 Slave Select output 2 SWCFG14 Software configuration 14 OCDSA_14 OCDS L2 Debug Line A14 SLSI0 SSC0 Slave Select Input RMW EBU Read Modify Write SWCFG15 Software configuration 15 OCDSA_15 OCDS L2 Debug Line A15 Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out PU/ PD Functions

General Device Information Data Sheet 10 V1.1, 2008-12 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 P2.12 P12 P11 P13 P14 N15 N14 N12 K16 J16 H16 L13 G16 K15 I/O I/O O O I I/O I/O I/O O I/O I/O I/O O I/O I/O I/O O O I/O I/O O O I/O I O PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC Port 2 Port 2 is a 16-bit bi-directional general purpose I/O port which can be alternatively used for ASC0/1/2, SSC0/1, CCU60, IIC, EBU and SCU. RXD0 ASC0 receiver input/output line CSEMU EBU Chip Select Output for Emulator Region TXD0 ASC0 transmitter output line TESTMODE Test Mode Select Input MRST0 SSC0 master receive/slave transmit input/output MTSR0 SSC0 master tr ansmit/slave receive input/output SCLK0 SSC0 clock input/output line COUT60_3 CCU60 compare channel 3 output MRST1A SSC1 master receive/slave transmit input/output A CC60_0 CCU60 input/output of capture compare channel 0 MTSR1A SSC1 master tran smit/slave receive input/output A COUT60_0 CCU60 output of capture/compare channel 0 SCLK1A SSC1 clock input/output line A CC60_1 CCU60 input/output of capture/ compare channel 1 RXD1A ASC1 receiver input/output line A COUT60_1 CCU60 output of capture/compare channel 1 TXD1A ASC1 transmit ter output line A CC60_2 CCU60 input/output of capture/ compare channel 2 RXD2A ASC2 receiver input/output line A COUT60_2 CCU60 output of capture/compare channel 2 TXD2A ASC2 transmit ter output line A SDA0 IIC Serial Data line 0 CTRAP0 CCU60 trap input SLSO0_3 SSC0 Slave Select output 3 Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out PU/ PD Functions

General Device Information Data Sheet 11 V1.1, 2008-12 P2.13 P2.14 P2.15 K14 F16 E16 I/O I O I I/O O I I/O O SCL0 IIC clock line 0 CCPOS0_0 CCU60 Hall input signal 0 SLSO1_3 SSC1 Slave Select output 3 CCPOS0_1 CCU60 Hall input signal 1 SDA1 IIC Serial Data line 1 SLSO0_4 SSC0 Slave Select output 4 CCPOS0_2 CCU60 Hall input signal 2 SCL1 IIC clock line 1 SLSO1_4 SSC1 Slave Select output 4 Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out PU/ PD Functions

General Device Information Data Sheet 12 V1.1, 2008-12 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 A15 B15 D15 E15 G14 G15 F15 H14 C15 H15 B16 I/O O O O I/O O O O I/O O O O I/O O O O I O O I O O O I I O O I O O PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC Port 3 Port 3 is a 16-bit bi-directional general purpose I/O port which can be alternatively used for MLI1, CCU61, SSC0/1 and OCDS Level 2 debug lines. OCDSB_0 OCDS L2 Debug Line B0 COUT61_3 CCU61 compare channel 3 output OCDSB_1 OCDS L2 Debug Line B1 CC61_0 CCU61 input/output of capture/ compare channel 0 OCDSB_2 OCDS L2 Debug Line B2 COUT61_0 CCU61 output of capture/compare channel 0 OCDSB_3 OCDS L2 Debug Line B3 CC61_1 CCU61 input/output of capture/ compare channel 1 OCDSB_4 OCDS L2 Debug Line B4 COUT61_1 CCU61 output of capture/compare channel 1 OCDSB_5 OCDS L2 Debug Line B5 CC61_2 CCU61 input/output of capture/ compare channel 2 OCDSB_6 OCDS L2 Debug Line B6 COUT61_2 CCU61 output of capture/compare channel 2 OCDSB_7 OCDS L2 Debug Line B7 CTRAP1 CCU61 trap input SLSO0_5 SSC0 Slave Select output 5 OCDSB_8 OCDS L2 Debug Line B8 CCPOS1_0 CCU61 Hall input signal 0 TCLK1 MLI1 transmit channel clock output SLSO1_5 SSC1 Slave Select output 5 OCDSB_9 OCDS L2 Debug Line B9 CCPOS1_1 CCU61 Hall input signal 1 TREADY1 MLI1 transmit channel ready input SLSO0_6 SSC0 Slave Select output 6 OCDSB_10 OCDS L2 Debug Line B10 CCPOS1_2 CCU61 Hall input signal 2 TVALID1 MLI1 transmit channel valid output SLSO1_6 SSC1 Slave Select output 6 Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out PU/ PD Functions

General Device Information Data Sheet 13 V1.1, 2008-12 P3.11 P3.12 P3.13 P3.14 P3.15 C16 D16 K13 J14 J15 O O O I O I O I O O I/O O I I/O O I I/O PUC PUC PUC PUC PUC OCDSB_11 OCDS L2 Debug Line B11 TDATA1 MLI1 transmit channel data output SLSO0_7 SSC0 Slave Select output 7 CC61_T12HR CCU61 Timer 12 hardware run OCDSB_12 OCDS L2 Debug Line B12 RCLK1 MLI1 receive channel clock input SLSO1_7 SSC1 Slave Select output 7 CC61_T13HR CCU61 Timer 13 hardware run OCDSB_13 OCDS L2 Debug Line B13 RREADY1 MLI1 receive channel ready output MRST1B SSC1 master receive/slave transmit input/output B OCDSB_14 OCDS L2 Debug Line B14 RVALID1 MLI1 receive channel valid input MTSR1B SSC1 master transmit/slave receive input/output B OCDSB_15 OCDS L2 Debug Line B15 RDATA1 MLI1 receive channel data input SCLK1B SSC1 clock input/output line B Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out PU/ PD Functions

General Device Information Data Sheet 14 V1.1, 2008-12 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 I/O I O I I I O I O O I O O O I I O PUC PUC PUC PUC PUC PUC PUC PUC Port 4 Port 4 is an 8-bit bi-directional general purpose I/O port which can be alternatively used for USB, MLI0 and SCU. USBCLK 48 MHz input clock TCLK0B MLI0 transmit ch annel clock output B RCVI USB data input TREADY0B MLI0 transmit channel ready input B VPI USB D+ CMOS level mirror of differential signal TVALID0B MLI0 transmit channel valid output B VMI USB D- CMOS level mirror of differential signal TDATA0B MLI0 transmit channel data output B VPO USB D+ CMOS level output RCLK0B MLI0 receive channel clock input B VMO USB D- CMOS level output RREADY0B MLI0 receive ch annel ready output B USBOE Direction select for transmit or receive RVALID0B MLI0 receive channel valid input B RDATA0B MLI0 receive ch annel data input B BRKOUT _A OCDS Break Out A HDRST N5 I/O PUA Hardware Reset Input/Reset Indication Output Assertion of this bi-directional open-drain pin causes a synchronous reset of the chip through external circuitry. This pin must be driven for a minimum 4 fCPU clock cycles. The internal reset circuitry drives this pin in response to a power-on, hardware, watchdog and power-down wake-up reset for a specific period of time. For a software reset, activation of this pin is programmable. PORST R5 I PUC Power-on Reset Input A low level on PORST causes an asynchronous reset of the entire chip. PORST is a fully asynchronous level sensitive signal. NMI T7 I PUC Non-Maskable Interrupt Input A high-to-low transition on this pin causes an NMI-Trap request to the CPU. Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out PU/ PD1) Functions

General Device Information Data Sheet 15 V1.1, 2008-12 TRST T11 I PDC JTAG Module Reset/Enable Input A low level at this pin resets and disables the JTAG module. A high level enables the JTAG module. TCK T12 I PUC JTAG Module Clock Input TDI T13 I PUC JTAG Module Serial Data Input TDO T10 O ⎯ JTAG Module Serial Data Output TMS T9 I PUC JTAG Module State Machine Control Input TRCLK T8 O ⎯ Trace Clock for OCDS_L2 Lines HWCFG0 HWCFG1 HWCFG2 M14 L14 I I I PUC PUC PDC Hardware Configuration Inputs The Configuration Inputs define the boot options of the TC1130 after a hardware invoked reset operation. BRKIN T5 I PUC OCDS Break Input A low level on this pin causes a break in the chip’s execution when the OCDS is enabled. In addition, the level of this pin during power-on reset determines the boot configuration. MII_ TXCLK T2 I PDC Ethernet Controller Transmit Clock MII_TXD[3:0] and MII_TXEN are driven off the rising edge of the MII_TXCLK by the core and sampled by the PHY on the rising edge of the MII_TXCLK. MII_ RXCLK R2 I PDC Ethernet Controller Receive Clock MII_RXCLK is a continuous clock. Its frequency is 25 MHz for 100 Mbit/sec operation, and 2.5 MHz for 10 Mbit/sec. MII_RXD[3:0], MII_RXDV and MII_EXER are driven by the PHY off the falling edge of MII_RXCLK and sampled on the rising edge of MII_RXCLK. MII_ MDIO R1 I/O PDA Ethernet Controller Management Data Input/ Output When a read command is being executed, the data that is clocked out of the PHY will be presented on the input line. When the Core is clocking control or data onto the MII_MDIO line, the signal will carry the information. D+ T14 I/O ⎯ USB D+ Data Line Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out PU/ PD Functions

General Device Information Data Sheet 16 V1.1, 2008-12 D- T15 I/O ⎯ USB D- Data Line CS0 CS1 CS2 CS3 O O O O PUC PUC PUC PUC EBU Chip Select Output Line 0 EBU Chip Select Output Line 1 EBU Chip Select Output Line 2 EBU Chip Select Output Line 3 Each corresponds to a programmable region. Only one can be active at one time. CSCOMB N3 O PUC EBU Chip Select Output for combination function (Overlay Memory and Global) SDCLKI J1 I ⎯ SDRAM Clock Input (Clock Feedback) SDCLKO H1 O ⎯ SDRAM Clock Output Accesses to SDRAM devices are synchronized to this clock. RAS D6 O PUC EBU SDRAM Row Address Strobe Output CAS D5 O PUC EBU SDRAM Column Address Strobe Output CKE L4 O PUC EBU SDRAM Clock Enable Output BFCLKI D1 I ⎯ Burst Flash Clock Input (Clock Feedback) BFCLKO E1 O ⎯ Burst Flash Clock Output Accesses to Burst Flash devices are synchronized to this clock. RD P2 O PUC EBU Read Control Line Output in master mode Input in slave mode RD/WR T3 O PUC EBU Write Control Line Output in master mode Input in slave mode WAIT B9 I PUC EBU Wait Control Line ALE R3 O PDC EBU Address Latch Enable Output MR/W P3 O PUC EBU Motorola-style Read/Write Output BAA A11 O PUC EBU Burst Address Advance Output For advancing address in a Burst Flash access ADV B11 O PUC EBU Burst Flash Address Valid Output Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out PU/ PD1) Functions

General Device Information Data Sheet 17 V1.1, 2008-12 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC EBU Address/Data Bus Input/Output Lines EBU Address/Data Bus Line 0 EBU Address/Data Bus Line 1 EBU Address/Data Bus Line 2 EBU Address/Data Bus Line 3 EBU Address/Data Bus Line 4 EBU Address/Data Bus Line 5 EBU Address/Data Bus Line 6 EBU Address/Data Bus Line 7 EBU Address/Data Bus Line 8 EBU Address/Data Bus Line 9 EBU Address/Data Bus Line 10 EBU Address/Data Bus Line 11 EBU Address/Data Bus Line 12 EBU Address/Data Bus Line 13 EBU Address/Data Bus Line 14 EBU Address/Data Bus Line 15 EBU Address/Data Bus Line 16 EBU Address/Data Bus Line 17 EBU Address/Data Bus Line 18 EBU Address/Data Bus Line 19 EBU Address/Data Bus Line 20 EBU Address/Data Bus Line 21 EBU Address/Data Bus Line 22 EBU Address/Data Bus Line 23 EBU Address/Data Bus Line 24 EBU Address/Data Bus Line 25 EBU Address/Data Bus Line 26 EBU Address/Data Bus Line 27 EBU Address/Data Bus Line 28 EBU Address/Data Bus Line 29 EBU Address/Data Bus Line 30 EBU Address/Data Bus Line 31 BC0 BC1 BC2 BC3 O O O O PUC PUC PUC PUC EBU Byte Control Line 0 EBU Byte Control Line 1 EBU Byte Control Line 2 EBU Byte Control Line 3 Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out PU/ PD1) Functions

General Device Information Data Sheet 18 V1.1, 2008-12 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A10 B10 C10 D10 O O O O O O O O O O O O O O O O O O O O O O O O PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC EBU Address Bus Input/Output Lines EBU Address Bus Line 0 EBU Address Bus Line 1 EBU Address Bus Line 2 EBU Address Bus Line 3 EBU Address Bus Line 4 EBU Address Bus Line 5 EBU Address Bus Line 6 EBU Address Bus Line 7 EBU Address Bus Line 8 EBU Address Bus Line 9 EBU Address Bus Line 10 EBU Address Bus Line 11 EBU Address Bus Line 12 EBU Address Bus Line 13 EBU Address Bus Line 14 EBU Address Bus Line 15 EBU Address Bus Line 16 EBU Address Bus Line 17 EBU Address Bus Line 18 EBU Address Bus Line 19 EBU Address Bus Line 20 EBU Address Bus Line 21 EBU Address Bus Line 22 EBU Address Bus Line 23 XTAL1 XTAL2 M16 N16 I O Oscillator/PLL/Clock Generator Input/Output Pins XTAL1 is the input to the main oscillator amplifier and input to the internal clock generator. XTAL2 is the output of the main oscillator amplifier circuit. For clocking of the device from an external source, XTAL1 is driven with the clock signal while XTAL2 is left unconnected. For crystal oscillator operation, XTAL1 and XTAL2 are connected to the crystal with the appropriate recommended oscillator circuitry. VDDOSC3 P16 ⎯⎯ Main Oscillator Power Supply (3.3 V) VSSOSC3 R16 ⎯⎯ Main Oscillator Ground VDDOSC L16 ⎯⎯ Main Oscillator Power Supply (1.5 V) Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out PU/ PD1) Functions

General Device Information Data Sheet 19 V1.1, 2008-12 Note: P2.12 to P2.15 are always configured as open drain. VSSOSC L15 ⎯⎯ Main Oscillator Ground VDD G7 G10 G13 K7,K8 K10 ⎯⎯ Core and Logic Power Supply (1.5 V) VDDP D4 D13 J13 N13 ⎯⎯ Ports Power Supply (3.3 V) VSS E4 E13 H10 H13 J4,J7 J8,J9 J10 M13 ⎯⎯ Ground N.C. A1 A16 T16 ⎯⎯ Not Connected These pins must not be connected. 1) Refers to internal pull-up or pull-down device connected and corresponding type. The notation ‘⎯’ indicates that the internal pull-up or pull-down device is not enabled. Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out PU/ PD1) Functions

Data Sheet 20 V1.1, 2008-12

3 Functional Description

3.1 On-Chip Memories

The TC1130 provides the following on-chip memories:

• Program Memory Interface (PMI) with – 32-Kbyte Scratch-pad Code RAM (SPRAM) – 16-Kbyte Instruction Cache Memory (ICACHE)
• Data Memory Interface (DMI) with – 28-Kbyte Scratch-pad Data RAM (SPRAM) – 4-Kbyte Data Cache Memory (DCACHE)
• Data Memory Unit (DMU) with – 64-Kbyte SRAM
• 16-Kbyte Boot ROM (BROM)

Data Sheet 21 V1.1, 2008-12

3.2 Address Map

Table 3-1 defines the specific segment oriented address blocks of the TC1130 with its address range, size, and PMI/DMI access view. Table 3-2 shows the block address map of the Segment 15 which includes on-chip peripheral units and ports. Table 3-1 TC1130 Bl ock Address Map Seg- ment Address Range Size Description DMI Acc. PMI Acc. 0 – 7 0000 0000 H – 7FFF FFFFH

2 GB MMU Space via FPI via

c a c h e d 8 8000 0000 H – 8FFF FFFFH

256 MB External Memory Space

9 9000 0000 H – 9FDF FFFFH

256 MB Reserved via FPI via

A000 0000H – AFBF FFFFH

252 MB External Memory Space via

n o c a c h e d AFC0 0000H – AFC0 FFFFH

64 KB DMU Space

AFC1 0000H – AFFF FFFFH ~4 MB Reserved

11 B000 0000 H –

256 MB Reserved via

C000 0000H – C000 FFFFH

64 KB DMU via

c a c h e d C001 0000H – CFFF FFFFH ~ 256 MB Reserved

Data Sheet 22 V1.1, 2008-12 D000 0000H – D000 6FFFH

28 KB DMI Local Data RAM

(LDRAM) DMI local via LMB non-cached D000 7000H – D3FF FFFFH ~ 64 MB Reserved D400 0000H – D400 7FFFH

32 KB PMI Local Code Scratch Pad

RAM (SPRAM) via LMB PMI local D400 8000H – D7FF FFFFH ~64 MB Reserved D800 0000H – DDFF FFFFH

96 MB External Memory Space

LMBDE00 0000H – DEFF FFFFH

16 MB Emulator Memory Space

DF00 0000H – DFFF BFFFH ~16 MB Reserved – – DFFF C000H – DFFF FFFFH

16 KB Boot ROM Space via FPI via

E000 0000H – E7FF FFFFH

128 MB External Memory Space via

E800 0000H – E83F FFFFH

4 MB Reserved for mapped space

for lower 4 Mbytes of Local Memory in Segment 12 (Transformed by LFI bridge to C000 0000 H – C03F FFFFH) access only from FPI bus side of LFI access only from FPI bus side of LFI E840 0000 H – E84F FFFFH

1 MB Reserved for mapped space

for lower 1 Mbyte of Local Memory in Segment 13 (Transformed by LFI bridge to D000 0000 H – D00F FFFFH) access only from FPI bus side of LFI access only from FPI bus side of LFI E850 0000 H – E85F FFFFH for 1 Mbyte of Local Memory in Segment 13 (Transformed by LFI bridge to D400 0000 H – D40F FFFFH) Table 3-1 TC1130 Bl ock Address Map (cont’d) Seg- ment Address Range Size Description DMI Acc. PMI Acc.

Data Sheet 23 V1.1, 2008-12

14 E860 0000 H –

122 MB Reserved – – n

o c a c h e d

15 F000 0000 H –

256 MB See Table 3-2 via

Table 3-2 Block Addre ss Map of Segment 15 Symbol Description Address Range Size System Peripheral Bus (SPB) SCU System Control Unit (incl. WDT) F000 0000 H - F000 00FFH 256 Bytes SBCU FPI Bus Control Unit F000 0100 H - F000 01FFH 256 Bytes STM System Timer F000 0200 H - F000 02FFH 256 Bytes OCDS On-Chip Debug Support (Cerberus) F000 0300H - F000 03FFH 256 Bytes – Reserved F000 0400 H - F000 04FFH 256 Bytes – Reserved F000 0500 H - F000 05FFH 256 Bytes GPTU General Purpose Timer Unit F000 0600 H - F000 06FFH 256 Bytes – Reserved F000 0700 H - F000 07FFH 256 Bytes – Reserved F000 0800 H - F000 08FFH 256 Bytes – Reserved F000 0900 H - F000 09FFH 256 Bytes – Reserved F000 0A00 H - F000 0AFFH 256 Bytes – Reserved F000 0B00 H - F000 0BFFH 256 Bytes P0 Port 0 F000 0C00 H - F000 0CFFH 256 Bytes P1 Port 1 F000 0D00 H - F000 0DFFH 256 Bytes P2 Port 2 F000 0E00 H - F000 0EFFH 256 Bytes P3 Port 3 F000 0F00 H - F000 0FFFH 256 Bytes P4 Port 4 F000 1000 H - F000 10FFH 256 Bytes – Reserved F000 1100 H - F000 11FFH 256 Bytes Table 3-1 TC1130 Bl ock Address Map (cont’d) Seg- ment Address Range Size Description DMI Acc. PMI Acc.

Data Sheet 24 V1.1, 2008-12 – Reserved F000 1200 H - F000 12FFH 256 Bytes – Reserved F000 1300 H - F000 13FFH 256 Bytes – Reserved F000 1400 H - F000 14FFH 256 Bytes – Reserved F000 1500 H - F000 15FFH 256 Bytes – Reserved F000 1600 H - F000 16FFH 256 Bytes – Reserved F000 1700 H - F000 17FFH 256 Bytes – Reserved F000 1800 H - F000 18FFH 256 Bytes – Reserved F000 1900 H - F000 19FFH 256 Bytes CCU60 Capture/Compare Unit 0 F000 2000 H - F000 20FFH 256 Bytes CCU61 Capture/Compare Unit 1 F000 2100 H - F000 21FFH 256 Bytes – Reserved F000 2200 H - F000 3BFFH – DMA Direct Memory Access Controller F000 3C00 H - F000 3EFFH 3 × 256 Bytes – Reserved F000 3F00 H - F000 3FFFH – CAN MultiCAN Controller F000 4000 H - F000 5FFFH 8 Kbytes – Reserved F000 6000 H - F00E 1FFFH – USB USB RAM based Registers F00E 2000 H - F00E 219FH 416 Bytes USB USB RAM F00E 21A0 H - F00E 27FFH 1.6 Kbytes USB USB Registers F00E 2800 H - F00E 28FFH 256 Bytes – Reserved F00E 2900 H - F00F FFFFH – Units on SMIF Interface of DMA Controller – Reserved F010 0000 H - F010 00FFH 256 Bytes SSC0 Synchronous Serial Interface 0 F010 0100 H - F010 01FFH 256 Bytes SSC1 Synchronous Serial Interface 1 F010 0200 H - F010 02FFH 256 Bytes ASC0 Async./Sync. Serial Interface 0 F010 0300 H - F010 03FFH 256 Bytes ASC1 Async./Sync. Serial Interface 1 F010 0400 H - F010 04FFH 256 Bytes ASC2 Async./Sync. Serial Interface 2 F010 0500 H - F010 05FFH 256 Bytes I2C Inter IC F010 0600 H - F010 06FFH 256 Bytes – Reserved F010 0700 H - F010 BFFFH – MLI0 Micro Link Interface 0 F010 C000 H - F010 C0FFH 256 Bytes MLI1 Micro Link Interface 1 F010 C100 H - F010 C1FFH 256 Bytes Table 3-2 Block Addre ss Map of Segment 15 (cont’d) Symbol Description Address Range Size

Data Sheet 25 V1.1, 2008-12 MCHK Memory Checker F010 C200 H - F010 C2FFH 256 Bytes – Reserved F010 C300 H - F01D FFFFH – MLI0_ SP0 MLI0 Small Transfer Window 0 F01E 0000 H - F01E 1FFFH 8 Kbytes MLI0_ SP1 MLI0 Small Transfer Window 1 F01E 2000 H - F01E 3FFFH 8 Kbytes MLI0_ SP2 MLI0 Small Transfer Window 2 F01E 4000 H - F01E 5FFFH 8 Kbytes MLI0_ SP3 MLI0 Small Transfer Window 3 F01E 6000 H - F01E 7FFFH 8 Kbytes MLI1_ SP0 MLI1 Small Transfer Window 0 F01E 8000 H - F01E 9FFFH 8 Kbytes MLI1_ SP1 MLI1 Small Transfer Window 1 F01E A000 H - F01E BFFFH 8 Kbytes MLI1_ SP2 MLI1 Small Transfer Window 2 F01E C000 H- F01E DFFFH 8 Kbytes MLI1_ SP3 MLI1 Small Transfer Window 3 F01E E000 H - F01E FFFFH 8 Kbytes – Reserved F01F 0000 H - F01F FFFFH – MLI0_ LP0 MLI0 Large Transfer Window 0 F020 0000 H - F020 FFFFH 64 Kbytes MLI0_ LP1 MLI0 Large Transfer Window 1 F021 0000 H - F021 FFFFH 64 Kbytes MLI0_ LP2 MLI0 Large Transfer Window 2 F022 0000 H - F022 FFFFH 64 Kbytes MLI0_ LP3 MLI0 Large Transfer Window 3 F023 0000 H - F023 FFFFH 64 Kbytes MLI1_ LP0 MLI1 Large Transfer Window 0 F024 0000 H - F024 FFFFH 64 Kbytes MLI1_ LP1 MLI1 Large Transfer Window 1 F025 0000 H - F025 FFFFH 64 Kbytes MLI1_ LP2 MLI1 Large Transfer Window 2 F026 0000 H - F026 FFFFH 64 Kbytes Table 3-2 Block Addre ss Map of Segment 15 (cont’d) Symbol Description Address Range Size

Data Sheet 26 V1.1, 2008-12 MLI1_ LP3 MLI1 Large Transfer Window 3 F027 0000 H - F027 FFFFH 64 Kbytes – Reserved F028 0000 H - F200 00FFH – ECU Ethernet Controller Unit F200 0100 H - F200 05FFH 1280Bytes – Reserved F200 0600 H - F7E0 FEFFH – CPU (Part of System Peripheral Bus) CPU SFRs CPU Slave Interface F7E0 FF00 H - F7E0 FFFFH 256 Bytes Reserved F7E1 0000 H - F7E1 7FFFH – MMU F7E1 8000 H - F7E1 80FFH 256 Bytes Reserved F7E1 8100 H - F7E1 BFFFH – Memory Protection Registers F7E1 C000 H -F7E1 EFFFH 12 Kbytes Reserved F7E1 F000 H - F7E1 FCFFH – Core Debug Register (OCDS) F7E1 FD00 H -F7E1 FDFFH 256 Bytes Core Special Function Registers (CSFRs) F7E1 FE00H -F7E1 FEFFH 256 Bytes General Purpose Register (GPRs) F7E1 FF00 H - F7E1 FFFFH 256 Bytes – Reserved F7E2 0000 H - F7FF FFFFH – Local Memory Buses (LMB) EBU External Bus Inte rface Unit F800 0000 H - F800 03FFH 1 Kbyte DMU Data Memory Unit F800 0400 H - F800 04FFH 256 Bytes – Reserved F800 0500 H - F87F FBFFH – DMI Data Memory Interface Unit F87F FC00 H - F87F FCFFH 256 Bytes PMI Program Memory Interface Unit F87F FD00 H - F87F FDFFH 256 Bytes LBCU Local Memory Bus Control Unit F87F FE00 H - F87F FEFFH 256 Bytes LFI LMB to FPI Bu s Bridge F87F FF00 H - F87F FFFFH 256 Bytes – Reserved F880 0000 H - FFFF FFFFH – Table 3-2 Block Addre ss Map of Segment 15 (cont’d) Symbol Description Address Range Size

Data Sheet 27 V1.1, 2008-12

3.3 Memory Protection System

The TC1130 memory protection system specifies the addressable range and read/write permissions of memory segments available to the currently executing task. The memory protection system controls the position and range of addressable segments in memory. It also controls the types of read and write operations allowed within addressable memory segments. Any illegal memory access is detected by the memo ry protection hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the error. Thus, the memory protection system protects critical system functions against both software and hardware erro rs. The memory protection hardware can also generate signals to the Debug Unit to facilitate tracing illegal memory accesses. In TC1130, TriCore™ supports two address spaces: the virtual address space and the physical address space. Both address spaces are 4 Gbytes in size and are divided into 16 segments with each segment being 256 M bytes. The upper 4 bits of the 32-bit address are used to identify the segment. Virtual segments are numbered 0 - 15. But a virtual address is always translated into a physical address before accessing memory. The virtual address is translated into a physical addre ss using one of two translation mechanisms: (a) direct translation, and (b) Page Table Entry (PTE) based translation. If the virtual address belongs to the upper half of the virtual address space then the virtual address is directly used as the physical address (direct translation). If the virtual address belongs to the lower half of the address space, then the virtual address is used directly as the physical address if the processor is operating in physical mode (direct translation) or translated using a Page Table Entry if the processor is operating in Virtual mode (PTE translation). These are managed by Memory Management Unit (MMU). Memory protection is enforced using separate mechanisms for the two translation paths.

3.3.1 Protection for Direct translation

Memory protection for addresse s that undergo direct translat ion is enforced using the range based protection that has been used in the previous generation of the TriCore™ architecture. The range bas ed protection mechanism prov ides support for protecting memory ranges from unauthor ized read, write, or inst ruction fetch accesses. The TriCore™ architecture provides up to four protection register se ts with the PSW.PRS field controlling the selection of the protection register set. Because the TC1130 uses a Harvard-style memory architec ture, each Memory Protecti on Register Set is broken down into a Data Protection Register Set and a Code Protection Register Set. Each Data Protection Register Set can sp ecify up to four address ranges to rece ive particular protection modes. Each Code Protection Re gister Set can specif y up to two address ranges to receive particular protection modes. Each of the Data Protecti on Register Sets and Code Protection Register Sets determines the range and protection modes for a separate memory area. Each contains register pairs which determine the addre ss range (the Data Segment Protection Registers and Code Segment Pr otection Registers) and o ne register (Data Protection

Data Sheet 28 V1.1, 2008-12 Mode Register) which determines the me mory access modes which apply to the specified range.

3.3.2 Protection for PTE based translation

Memory protection for addresses that undergo PTE based translation is enforced using the PTE used for the address translation. The PTE pr ovides support for protecting a process from unauthoriz ed read, write, or instruction fetches by other processes. The PTE has the following bits that are provided for the purpose of protection:

• Execute Enable (XE) enables instruction fetch to the page
• Write Enable (WE) enables data writes to the page
• Read Enable (RE) enables data reads from the page Furthermore, User-0 accesses to virtual addresses in th e upper half of the virtual address space are disallowed when operating in virtual mode. In physical mode, User-0 accesses are disallowed only to segments 14 and 15. Any User-0 access to a virtual address that is restricted to User-1 or supervisor mode will cause a Virtual Address Protection (VAP) Trap in both the physical and virtual modes.

3.3.3 Memory Checker

The Memory Checker module (MCHK) makes it possible to check the data consistency of memories. It uses DMA moves to read from the selected address area and to write the value read in a memory checke r input register (the moves should be 32-bit moves). A polynomial checksum calculation is done wi th each write oper ation to the memory checker input register.

Data Sheet 29 V1.1, 2008-12

3.4 On-Chip Bus System

The TC1130 includes two bus systems:

• Local Memory Bus (LMB)
• Flexible Peripheral Interface Bus (FPI) The LMB-to-FPI (LFI) bridge interconnects the FPI bus and LMB Bus.

3.4.1 Local Memory Bus (LMB)

The Local Memory Bus interc onnects the memory units a nd functional units, such as CPU and DMU. The main obje ctive of the LMB bus is to support devices with fast response time. This allows the DMI and PMI fast access to local memory and reduces load on the FPI bus. The TriCore™ system itself is located on the LMB bus. Via External Bus Unit, it interconnects TC1130 and external components. The Local Memory Bus is a syn chronous, pipelined, split bus with va riable block size transfer support. It supports 8, 16, 32 and 64 bits single beat transactions and variable length 64 bits block transfers. Features: The LMB provides the following features:

• Synchronous, Pipelined, Multimas ter, 64-bit high performance bus
• Optimized for high s peed and high performance
• 32-bit address, 64-bit data buses
• Central, simple per cycle arbitration
• Slave controlled wa it state insertion
• Address pipelining (max depth - 2)
• Supports Split transactions
• Supports Variable block size transfer
• Supports Locked transact ion (read-modify-write)

3.4.2 Flexible Peripheral Interconnect Bus (FPI)

The FPI Bus is an on-chip bus that is used in modular and highly integrated microprocessors and microcontrollers ( systems-on-chips). FPI Bus is designed for memory mapped data transfers between its bus agents. Bus agents are on-chip function blocks (modules), equipped with an FP I Bus interface and c onnected via FPI Bus signals. An FPI Bus agent acts as an FPI Bus master when it initiates data read or data write operations once bus ownership has been granted to the agent. An FPI Bus agent that is addressed by an FPI Bus operation acts as an FPI Bus slave when it performs the requested data read or write operation.

Data Sheet 30 V1.1, 2008-12 Features: The FPI Bus is designed with the requirements of high-p erformance systems in mind. The features are:

• Core independent
• Multimaster capabilit y (up to 16 masters)
• Demultiplexed operation
• Clock synchronous
• Peak transfer rate of up to 80 0 Mbytes/sec (@ 100 MHz bus clock)
• Address and data bus scalable (address bu s up to 32 bits, data bus up to 64 bits)
• 8-/16-/32- and 64-bit data transfers
• Broad range of transfer types from single to multiple data transfers
• Split transaction su pport for agents with long response time
• Burst transfer capability
• EMI and power consumption minimized

3.4.3 LFI

The LMB-to-FPI Interface (LFI) block provides the circuitry to interface (bridge) the FPI bus and the Local Memory Bus (LMB). LFI Features:

• Full support for bus transactions found within current TriCore™ 1.3 based systems: – Single 8/16/32-bit Write/Read transfers from FPI to LMB – Single 8/16/32/64-bit Write/Re ad transfers from LMB to FPI – Read-Modify-Write transfers of 8/16/32-bit in both directions – Burst transactions of 2, 4 or 8 data beats from the FPI to the LMB – Burst transactions of 2 or 4 da ta beats from the LMB to the FPI
• Address decoding a nd translation as required by TriCore™ 1.3 implementation
• FPI master interf ace supports full pipelining on FPI bus
• LMB master interface suppo rts pipelining on LMB with in the scope of the LMB specification
• FPI master interface can act as default master on FPI bus
• Programmable support for split LMB to FPI read transactions
• Retry generation on both FPI and LMB buses
• Full support for abort, retry, error and FPI timeout conditions
• Flexible LMB/FPI clock rati o support including dynamic clock switching support
• LFI core clock may be shut down when no transactions are being issued to LFI from either bus and the LFI has no transactions in progress, thus saving power.

Data Sheet 31 V1.1, 2008-12

3.5 LMB External Bus Unit

The LMB External Bus Control Unit (EBU) of the TC1130 is the interface between external resources, like memories and per ipheral units, and th e internal resources connected to on-chip buses if enabled. The basic structure and external interconnections of the EBU are shown in Figure 3-1. Figure 3-1 EBU Structure and Interface MCB04941_mod EBU_LMB AD[31:0] BC[3:0] A[23:0] RD RD/WR WAIT CSCOMB ADV ALE RAS CS[3:0] BFCLKO CAS CKE MR/W P1.15/RMW P0.5/HOLD BFCLKI BAA LMB PMI DMI LFI MMUTri CoreTM FPI To Peripherals SDCLKI SDCLKO Port 0 Control P0.6/HLDA P0.4/BREQ Port 1 Control P2.0/CSEMUPort 2 Control

Data Sheet 32 V1.1, 2008-12 The EBU is used primarily for any Local Memory Bus (LMB) master accessing external memories. The EBU controls all transactions required for this operation and in particular handles the arbitration between the internal EBU master and the external EBU master. The types of external devices/bus modes controlled by the EBU are:

• Intel-style perip herals (separate RD and WR signals)
• R O M s , E P R O M s
• S t a t i c R A M s
• PC100 and PC133 SDRAMs (Burst Read/W rite Capacity/Multi-Bank/Page support)
• Specific types of Burs t Mode Flash devices
• Special support for extern al emulator/debug hardware Features:
• Supports 64-bit Local Memory Bus (LMB)
• Supports external bus frequency: internal LMB frequency = 1:1 or 1:2
• Provides highly programm able access parameters
• Supports Intel-style peripherals/devices
• Supports PC100 and PC133 (runs in maximum 120 MHz ) SDRAM (burst access, multibanking, precharge, refresh)
• Supports 16- and 32-bit SDRAM data bus and 64-,128-, and 256-Mbit devices
• Supports Burst Flash devices
• Supports Multiplexed access (address and data on the same bus) when PC100 and PC133 SDRAM are not presented on the external bus
• Supports data buffering : Code Prefetch Buffer, Read/Write Buffer
• External master arbitration compatible to C166 and other TriCore™ devices
• Provides 4 programmable address regions (1 dedicated for emulator)
• Provides a CSGLB signal, bit programmable to combine one or more CS lines for buffer control
• Provides RMW signal reflecting read-modify-write action
• Supports Little En dian byte ordering
• Provides signal for controlling data flow of slow-memory buffer

Data Sheet 33 V1.1, 2008-12

3.6 Direct Memory Access (DMA)

The Direct Memory Access Controller executes DMA tr ansactions from a source address location to a destination address location, without intervention of the CPU. One DMA transaction is controlled by one DM A channel. Each DMA channel has assigned its own channel register set. The total of 8 channels are provided by one DMA sub-block. The DMA module is co nnected to 3 bus inte rfaces in TC1130, the Flexible Peripheral Interconnect Bus (FPI), the DMA Bus and the Micro Link Bus. It can do transfers on each of the buses as well as between the buses. In addition, it bridge s accesses from the Fl exible Peripheral Inte rconnect Bus to the peripherals on the DMA Bus, allowing easy access to these peripherals by CPU. Clock control, address decoding, DMA request wiring, and DM A interrupt service request control are implementation specific and managed outside the DMA controller kernel. Features:

• 8 independent DMA channels – Up to 8 selectable reques t inputs per DMA channel – Programmable priority of DMA channels within a DMA sub-block (2 levels) – Software and hardware DMA request generation – Hardware requests by selected peripherals and external inputs
• Programmable priority of the DM A sub-block on the bus interfaces
• Buffer capability for move actions on th e buses (min. 1 move per bus is buffered).
• Individually programma ble operation modes for each DMA channel – Single mode: stops and disables DMA chan nel after a predefined number of DMA transfers – Continuous mode: DMA chann el remains enabled after a predefined number of DMA transfers; DMA transaction can be repeated. – Programmable address modification
• Full 32-bit addressi ng capability of each DMA channel – 4-Gbyte address range – Support of circular buffer addressing mode
• Programmable data width of a DMA tr ansaction: 8-bit, 16-bit, or 32-bit
• Micro Link supported
• Register set for each DMA channel – Source and destinatio n address register – Channel control an d status register – Transfer count register
• Flexible interrupt generation (the service req uest node logic for the MLI channels is also implemented in the DMA module)
• All buses/interfaces connected to the DMA module must work at the same frequency
• Read/write requests of the FP I Bus Side to the Remote Peripherals are bridged to the DMA Bus (only the DMA is master on the DMA bus)

Data Sheet 34 V1.1, 2008-12 The basic structure and external interconnections of the DMA are shown in Figure 3-2. Figure 3-2 DMA Controller Stru cture and Interconnections DMA Request Wiring Matrix Interrupt Control TC1130_DMAImplementation Clock Control Address Decoder DMA Controller Arbiter/ Switch Control Switch Bus Interface 0 M/S Bus Interface 2 SMIF SR [3:0] fDMA ASC0 ASC1 ASC2 SSC0 SSC1 CCU60 4SCU (Ext.Trg) MLI1 DMA Interrupt Control Unit MultiCAN To FPI Bus MLI0 I2C CCU61 SR [15:12] Channel 00-07 Registers DMA Sub-Block 0 Request Assignment and Priorisation Unit 0 Transaction Control Engine USB Bus Interface 1 M/S ASC0 ASC1 ASC2 SSC0 SSC1 IIC DMA Bus MLI0 MLI1 Mem Check DMA Bus

Data Sheet 35 V1.1, 2008-12

3.7 Interrupt System

An interrupt request can be serviced by the CPU, which is called “Service Provider”. Interrupt requests are referred to as “Service Requests” in this document. Each peripheral in the TC1 130 can generate service requ ests. Additionally, the Bus Control Unit, the Debug Unit, the DMA Controller and even the CPU itself can generate service requests to the Service Provider. As shown in Figure 3-3, each unit that can generate service requ ests is connected to one or multiple Se rvice Request Nodes (SRN). Each SRN contains a Service Request Control Register mod_SRC, where “mod” is the identifier of the unit requesting service. The SRNs are connected to the Interrupt Control Unit (ICU) via the CP U Interrupt Arbitration Bus. The ICU arbitrates service requests for the CPU and administers the Interrupt Arbitration Bus. Units that can generate service requests are:

• Asynchronous/Synchronous Se rial Interfaces (ASC0, ASC1 and ASC2) with 4 SRNs each
• High-Speed Synchro nous Serial Interfaces (SSC0 and SSC1) with 3 SRNs each
• Inter IC Interface (IIC) with 3 SRNs
• Universal Serial Bu s (USB) with 8 SRNs
• Micro Link Interface MLI0 with 4 SRNs and MLI1 with 2 SRNs
• General Purpose Timer Unit (GPTU) with 8 SRNs
• Capture/Compare Un it (CCU60 and CCU61) with 4 SRNs each
• MultiCAN (CAN) with 16 SRNs
• Ethernet Controll er with 9 SRNs
• External Interrupts with 4 SRNs
• Direct Memory Access Cont roller (DMA) with 4 SRNs
• DMA Bus with 1 SRN
• System Timer (STM) with 2 SRNs
• Bus Control Units (SBCU and LBCU) with 1 SRN each
• Central Processing Unit (CPU) with 4 SRNs
• Floating Point Unit (FPU) with 1 SRN
• Debug Unit (OCDS) with 1 SRN The CPU can make service requ ests directly to itself (v ia the ICU). The CPU Service Request Nodes are activated through software.

Data Sheet 36 V1.1, 2008-12 Figure 3-3 Block Diagram of the TC1130 Interrupt System Service Req. Nodes Service Req. Nodes Service Requestors Interrupt System CPU Interrupt Arbitration Bus Service Requestors

4 SRNs4ASC0 4

4 SRNs4ASC1 4

4 SRNs4ASC2 4

3 SRNs3SSC0 3

4 SRNs4MLI0 4

3 SRNs3SSC1 3

2 SRNs2MLI1 2

16 SRNs16MultiCAN 16

8 SRNs8USB 8

9 SRNs9ETHERNET

8 SRNs8GPTU 8

2 SRNs2STM 2

1 SRN1FPU 1

4 SRNs DMA44

1 SRN SBCU11

1 SRN LBCU11

4 SRNs CCU6144

4 SRNs CCU6044

4 SRN Ext. Int.44

3 SRNs IIC33

Service Req. Nodes 4 4 SRNs 4 CPU Interrupt Control Unit Interrupt Service Providers Int. Req. PIPN CPU CCPN Int. Ack. Software Interrupts ICU

1 SRN1OCDS 1

1 SRN1DMA BUS 1

Data Sheet 37 V1.1, 2008-12

3.8 Parallel Ports

The TC1130 has 72 digital input/output port lines, which are organized into four parallel 16-bit ports and one parallel 8-bit port, Port P0 to Port P4 with 3.3 V nominal voltage. The digital parallel ports can be used as general purpos e I/O lines or they can perform input/output functions for the on-chip peripheral units. An overview on the port-to- peripheral unit assignment is shown in Figure 3-4. Figure 3-4 Parallel Ports of the TC1130 MCA04951mod TC1130 Parallel Ports GPIO3 GPIO4 GPIO Alternate Functions SSC0/ SSC1/ CCU61/ MLI1/ OCDS USB/ MLI0/ SCUGPIO1 GPIO0 GPIO2 GPIOAlternate Functions ASC0/ ASC1/ ASC2/ SSC0/ SSC1/ IIC/ CCU60/EBU/ SCU SSC0/ SSC1/ MultiCAN/ Ethernet/ EBU/ SCU/ OCDS GPTU/ ASC1/ ASC2/ SSC0/ SSC1/ CCU60/ MultiCAN/ MLI0/ EBU/ SCU/ External Interrupts

Data Sheet 38 V1.1, 2008-12

3.9 Asynchronous/Synchronous Serial Interface (ASC)

Figure 3-5 shows a global view of the func tional blocks of three Asynchronous/ Synchronous Serial interfaces (ASC0, ASC1 and ASC2). Each ASC module (ASC0/ASC1/ASC2) communica tes with the extern al world via one pair of I/O lines. The RXD line is the receive data input signal (in synchronous mode also output). TXD is the transmit output signal. Clock control, address decoding, and interrupt service request control are managed outside the ASC module kernel. The Asynchronous/Synchrono us Serial interfaces pr ovide serial communication between the TC1130 and other microcontr ollers, microprocessors or external peripherals. Each ASC supports full-d uplex asynchronous commu nication and half-duplex synchronous communication. In synchronous mode, data is transmitted or received synchronous to a shift clock which is generated by the ASC internally. In asynchronous mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be selected. Parity, framing, and overrun erro r detection are provi ded to increase the reliability of data transfers. Transmission and reception of data is double-buffered. For multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. Testing is supported by a loop-back option. A 13-bit baud-rate generator provides the ASC with a separate serial clock signal that can be accurately adjusted by a prescaler implemented as a fractional divider.

Data Sheet 39 V1.1, 2008-12 Figure 3-5 General Block Diag ram of the ASC Interfaces MCB04485_mod ASC0 Module (Kernel) Port Control ASC1 Module (Kernel) Clock Control Address Decoder Interrupt Control fASC1 to DMA EIR TBIR TIR RIR Clock Control Address Decoder Interrupt Control fASC0 to DMA EIR TBIR TIR RIR P2.0/ RXD0 P2.1/ TXD0 P0.0/ RXD1B P0.1/ TXD1B P2.8/ RXD1A P2.9/ TXD1A RXD_I1 RXD_O RXD_I0 TXD_O RXD_I1 RXD_O RXD_I0 TXD_O ASC2 Module (Kernel) Clock Control Address Decoder Interrupt Control fASC1 to DMA EIR TBIR TIR RIR P0.2/ RXD2B P0.3/ TXD2B P2.10/ RXD2A P2.11/ TXD2ARXD_I1 RXD_O RXD_I0 TXD_O

Data Sheet 40 V1.1, 2008-12 Features:

• Full-duplex asynchrono us operating modes – 8-bit or 9-bit data frames, LSB first – Parity bit generation/checking – One or two stop bits – Baud rate from 4.6875 MBaud to 1.1 Baud (@ 75 MHz clock)
• Multiprocessor mode for automatic address/data byte detection
• Loop-back capability
• Half-duplex 8-bit syn chronous operating mode – Baud rate from 9.375 MBaud to 762.9 Baud (@ 75 MHz clock)
• Support for IrDA data transmis sion up to 115.2 kBaud maximum
• Double buffered transmitter/receiver
• Interrupt generation – On a transmitter bu ffer empty condition – On a transmit last bit of a frame condition – On a receiver buff er full condition – On an error condit ion (frame, parity, overrun error)
• F I F O – 8-byte receive FIFO (RXFIFO) – 8-byte transmit FIFO (TXFIFO) – Independent control of RXFIFO and TXFIFO – 9-bit FIFO data width – Programmable Receive/Trans mit Interrupt Trigger Level – Receive and Transmit FIFO filling level indication – Overrun error generation – Underflow error generation

Data Sheet 41 V1.1, 2008-12

3.10 High-Speed Synchronous Serial Interface (SSC)

Figure 3-6 shows a global view of the functional blocks of two High-Speed Synchronous Serial interfaces (SSC0 and SSC1). Each SSC supports full-duplex and half-duplex serial synchronous communication up to 37.5 MBaud (@ 75 MHz module clock) with re ceive and transmit FIFO support. The serial clock signal can be generated by the SSC itself (master mode) or can be received from an external master (slave mode). Data width, shift directio n, clock polarity and phase are programmable. Thi s allows communication wi th SPI-compatible devices. Transmission and reception of data is double-buffered. A shift clock generator provides the SSC with a separate serial clock signal. Eight slave sele ct inputs are available for slave mode operation. Eight programmable slave select ou tputs (chip selects) are supported in master mode. Features:

• Master and slav e mode operation – Full-duplex or half-duplex operation – Automatic pad control possible
• Flexible data format – Programmable number of data bits: 2 to 16 bits – Programmable shift directi on: LSB or MSB shift first – Programmable clock polarity: idle lo w or high state for the shift clock – Programmable clock/data phase: data shift with leading or trailing edge of the shift clock
• Baud rate generation minimum at 572.2 Baud (@ 75 MHz module clock)
• Interrupt generation – On a transmitte r empty condition – On a receiver full condition – On an error condit ion (receive, phase, baud rate, transmit error)
• Four-pin interface
• Flexible SSC pin configuration
• Up to eight slave select inputs in slave mode
• Up to eight programmable slave sele ct outputs SLSO in master mode – Automatic SLSO generation with programmable timing – Programmable active le vel and enable control
• 4-stage receive FIFO (RXFIFO) an d 4-stage transmit FIFO (TXFIFO) – Independent control of RXFIFO and TXFIFO – 2- to 16-bit FIFO data width – Programmable receive/transmi t interrupt trigger level – Receive and transmit FIFO filling level indication – Overrun error generation – Underflow error generation

Data Sheet 42 V1.1, 2008-12 Figure 3-6 General Block Diag ram of the SSC Interfaces Port 1 Control MCB04486_mod Clock Control Address Decoder Interrupt Control fSSC0 Address Decoder Interrupt Control to DMA EIR TIR RIR to DMA EIR TIR RIR Port 2 Control SSC0 Module (Kernel) MRSTB MTSR Master SLSI1 SLSO[2:1] MRSTA MTSRB MRST MTSRA SCLKB SLCK SCLKA Slave Slave Master Slave Master Port 2 Control SSC1 Module (Kernel) MRSTB MTSR Master SLSO[7:5] MRSTA MTSRB MRST MTSRA SCLKB SLCK SCLKA Slave Slave Master Master P2.3/MTSR0 P2.2/MRST0 P2.4/SCLK0 P2.5/MRST1A P1.15/SLSI0 fCLC0 fSSC1 fCLC1 Clock Control SLSI[7:2]1) SLSI1 Slave SLSI[7:2]1) Enable M/S Select P1.11/SLSO01 1)These lines are not connect ed SLSO0 Enable1) M/S Select1) P1.13/SLSO02 P2.12/SLSO03 P2.14/SLSO04 SLSO[4:3] Port 0 Control P0.6/SLSO00 P0.7/SLSO10 Port 3 Control SLSO[7:5] P3.7/SLSO05 P3.9/SLSO06 P3.11/SLSO07 P3.8/SLSO15 P3.10/SLSO16 P3.12/SLSO17 SLSO0 SLSO[2:1] SLSO[4:3] Port 1 Control P1.12/SLSO11 P1.14/SLSO12 P3.13/MRST1B P2.6/MTSR1A P3.14/MTSR1B P2.7SCLK1A P3.15/SCLK1B P2.13/SLSO13 P2.15/SLSO14 P0.4/SLSI1

Data Sheet 43 V1.1, 2008-12

3.11 Inter IC Serial Interface (IIC)

Figure 3-7 shows a global view of t he functional blocks of the Inter IC Serial interface (IIC). The IIC module has four I/O li nes, located at Port 2. The IIC module is further supplied with clock control, interrupt control and address decoding logic. One DMA request can be generated by IIC module. Figure 3-7 General Block Diagram of the IIC Interface The on-chip IIC bus module conn ects the platform buses to other external controllers and/or peripherals via the two-line serial II C interface. One line is responsible for clock transfer and synchronization (SCL), the other is responsible for the data transfer (SDA). The IIC bus module provides communication at data rates of up to 400 kbit/sec and features 7-bit addressing as well as 10-bit addressing. This module is fully compatible to the IIC bus protocol. The module can operate in three different modes: Master mode, where the IIC controls the bus transactions and provides the clock signal. Slave mode, where an external master controls the bus transactions and provides the clock signal. Multimaster mode, where several masters can be connected to the bus, i.e. the IIC can be master or slave. The on-chip IIC bus module allows efficient communication via the common IIC bus. The module unloads the CPU of low level tasks such as:

• (De)Serialization of bus data
• Generation of star t and stop conditions
• Monitoring the bus lines in slave mode Address Decoder Interrupt Control IIC Module Port 2 Control P2.13/SCL0 P2.15/SCL1 SDA0 P2.14/SDA1 P2.12/SDA0 Clock Control fIIC SCL0 SDA1 SCL1INT_P INT_E INT_D to DMA

Data Sheet 44 V1.1, 2008-12

• Evaluation of the devic e address in slave mode
• Bus access arbitratio n in multimaster mode Features:
• Extended buffer allows up to 4 send/receive data bytes to be stored
• Selectable baud rate generation
• Support of standard 100 kBaud and extended 400 kBaud data rates
• Operation in 7-bit a ddressing mode or 10-bit addressing mode
• Flexible control via interrupt se rvice routines or by polling
• Dynamic access to up to 2 physical IIC buses

Data Sheet 45 V1.1, 2008-12

3.12 Universal Serial Bus Interface (USB)

Figure 3-8 shows a global view of the function al blocks of the Universal Serial Bus interface (USB). The USB module is further supplied with clock control, interrupt control, address decoding, and port control logic. One DMA request can be generated by USB module. Figure 3-8 General Block Diagram of the USB Interface The USB handles all transactions between the serial USB bus and the internal (parallel) bus of the microcontroller. The USB module includes several units which are required to support data handling with the USB bus: the on-chip USB tr ansceiver (optionally), the flexible USB buffer block with a 32-bit wide RAM, the buffer control unit with sub modules for USB and CPU memory access control, the UDC_IF device interface for USB protocol handling, the microcontroller interface unit (MCU) with the USB specific special function registers and the interrupt ge neration unit. A cl ock generation unit pr ovides the clock signal for the USB module for full speed and low speed USB operation. Interrupt Control USB Module (Kernel) Clock Control Address Decoder fUSB To DMA ISR0 ISR1 Port 4 Control P4.4 /VPO P4.0 /USBCLK VPOB VMOB VMIB USBOEB USBCLKB RCVIB VPIB P4.1 /RCVI P4.2 /VPI P4.3 /VMI P4.5 /VMO P4.6 /USBOEISR2 ISR3 ISR4 ISR5 ISR6 ISR7

Data Sheet 46 V1.1, 2008-12 Features:

• USB1.1 Device St andard Interface
• On-chip transceiver
• Differential I/O allow cable length up to 5m without additional hardware at target’s end.
• Hot attach
• USB1.1 full speed device
• USB protocol handling in hardware
• Clock and data recovery from USB
• Bit stripping and bi t stuffing functions
• CRC5 checking, CRC16 ge neration and checking
• Serial to parallel data conversion
• Maintenance of data synchronizati on bits (DATA0/DATA1 Toggle Bits)
• Supports multiple configurations, interfaces and alternate settings
• 11 endpoints with user config urable endpoint information
• Flexible intermediate buffe ring of transmission data
• Powerful data handling capability, FIFO-support
• Back-to-back transfers fully su pported by module automatism
• Multi-packet transfer without CPU load
• Handles data transfer with minimum CPU load
• Auto increment and single address mo des selectable for easy data access
• Powerful interrupt generation
• Meets suspend power consumption restrictions in power-down mode
• Remote wakeup from USB bus activity
• Explicit support of setup information
• Enhanced stat us monitoring

Data Sheet 47 V1.1, 2008-12

3.13 MultiCAN

Figure 3-9 shows a global view of the functional blocks of the MultiCAN module. Figure 3-9 General Block Diagram of the MultiCAN Interface The MultiCAN module cont ains 4 Full-CAN nodes op erating independently or exchanging data and remote frames via a gateway function. Transmission and reception of CAN frames is handled in accordance to CAN specification V2.0 B (active). Each CAN node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. All CAN nodes share a common set of message objects, where each message object may be individually allocate d to one of the CAN nodes. Besides serving as a storage container for incoming and outgoing frames, message objects may be combined to build gateways between the CAN nodes or to setup a FIFO buffer. The message objects are organized in double chained lists, where each CAN node has its own list of message object s. A CAN node stores frames only into message objects that are allocated to the list of the CAN node. It only transmits messages from objects of this list. A powerful, command driven list controller performs all list operations. MultiCAN Module Kernel MultiCAN_TC1130_impl Interrupt Control fCAN Port 0 Control CAN Node 1 CAN Control Message Object Buffer 128 Objects TXDC0A RXDC0ACAN Node 0 CAN Node 2 CAN Node 3 TXDC1A RXDC1A TXDC2 RXDC2 TXDC3 RXDC3 Linked List Control P0.15 / TXDCAN3 P0.14 / RXDCAN3 P0.13 / TXDCAN2 P0.12 / RXDCAN2 P0.11 / TXDCAN1A P0.10 / RXDCAN1A P0.9 / TXDCAN0A P0.8 / RXDCAN0A fCLC Clock Control Address Decoder DMA INT_O [3:0] INT_O [15:4] INT_O15 Port 1 Control P1.1 / TXDCAN0B P1.0 / RXDCAN0B P1.3 / TXDCAN1B P1.2 / RXDCAN1B TXDC1B RXDC1B TXDC0B RXDC0B

Data Sheet 48 V1.1, 2008-12 The bit timings for the CAN nodes are derived from the peripheral clock (fCAN) and are programmable up to a data rate of 1 MBaud. A pair of receive and transmit pins connects each CAN node to a bus transceiver. Features:

• Compliant to ISO 11898
• CAN functionality according to CAN specification V2.0 B (active)
• Dedicated control registers ar e provided for each CAN node
• A data transfer rate up to 1 MBaud is supported
• Flexible and powerful message transfer control and erro r handling cap abilities are implemented
• Advanced CAN bus bit timing analysis and baud rate detection can be performed for each CAN node via the frame counter
• Full-CAN functionality: A set of 12 8 message objects can be individually – allocated (assigned ) to any CAN node – configured as transmi t or receive object – setup to handle fr ames with 11-bit or 29-bit identifier – counted or assi gned a timestamp via a frame counter – configured to remote monitoring mode
• Advanced Acceptance Filtering: – Each message object provides an indivi dual acceptance mask to filter incoming frames. – A message object c an be configured to accept only standard or only extended frames or to accept both standard and extended frames. – Message objects c an be grouped into 4 priority classes. – The selection of the message to be tran smitted first can be performed on the basis of frame identifier, IDE bit and RTR bit according to CAN arbitration rules.
• Advanced Message Ob ject Functionality: – Message objects can be comb ined to build FIFO message buffers of arbitrary size, which is only limited by the total number of message objects. – Message objects can be link ed to form a gateway to automatically transfer frames between two different CAN buses. A single gateway can link any two CAN nodes. An arbitrary number of gateways may be defined.
• Advanced Data Management: – The Message objects are organi zed in double chained lists. – List reorganizations may be performed at any time, even during full operation of the CAN nodes. – A powerful, command driven list controller manages th e organization of the list structure and ensures consistency of the list. – Message FIFOs are based on the list stru cture and can easily be scaled in size during CAN operation.

Data Sheet 49 V1.1, 2008-12 – Static Allocation Commands o ffer compatibility with Tw inCAN applications, which are not list based.

• Advanced Interrupt Handling: – Up to 16 interrupt output lines are available. Most interrupt requests can be individually routed to one of the 16 interrupt output lines. – Message postprocessing notif ications can be flexibly aggregated into a dedicated register field of 256 notification bits.

Data Sheet 50 V1.1, 2008-12

3.14 Micro Link Serial Bus Interface (MLI)

Figure 3-10 shows a global view of the functional blocks of two Micro Link Serial Bus interfaces (MLI0 and MLI1). Figure 3-10 General Block Diagram of the MLI0 and MLI1 Interfaces Interrupt Control MLI_Interfaces Clock Control Address Decoder fMLI0 MLI Interface MLI0 Module (Kernel) TREADYA Port Control TVALIDA TDATA TCLK RREADYA RVALIDA RDATAA RCLKA P0.8/ TCLK0A P0.9/ TREADY0A P0.10/ TVALID0A P0.11/ TDATA0A P0.12/RCLK0A P0.13/ RREADY0A P0.14/ RVALID0A P0.15/ RDATA0ADMA INT_O [3:0] INT_O [7:4] TREADYB Port Control TVALIDB TDATA TCLK RREADYB RVALIDB RDATAB RCLKB P4.0/ TCLK0B P4.1/ TREADY0B P4.2/ TVALID0B P4.3/ TDATA0B P4.4/RCLK0B P4.5/ RREADY0B P4.6/ RVALID0B P4.7/ RDATA0B Interrupt Control Clock Control Address Decoder fMLI1 MLI Interface MLI1 Module (Kernel) TREADYA Port Control TVALIDA TDATA TCLK RREADYA RVALIDA RDATAA RCLKA P3.8 /TCLK1 P3.9 / TREADY1A P3.10 / TVALID1A P3.11 / TDATA1 P3.12/ RCLK1A P3.13 / RREADY1A P3.14 / RVALID1A P3.15 / RDATA1A DMA INT_O [1:0] INT_O [7:4]

Data Sheet 51 V1.1, 2008-12 The Micro Link Serial Bus Interface is de dicated to the serial communication between the other Infineon 32-bit controllers with MLI. The communication is intended to be fast due to an address translation system, and it is not necessary to have any special program in the second controller. Features:

• Serial communication from th e MLI transmitter to MLI receiver of another controller
• Module supports connection of each MLI with up to four MLI from other controllers
• Fully transparent read/write access supported (= remote programming)
• Complete address range of ta rget controller available
• Special protocol to tran sfer data, address offset, or address offset and data
• Error control using a parity bit
• 32-bit, 16-bit, and 8-bit data transfers
• Address offset width: from 1- to 16-bit
• Baud rate: fMLI / 2 (symmetric shift clock approach), baud rate definition by the corresponding fractional divider

Data Sheet 52 V1.1, 2008-12

3.15 General Purpose Timer Unit (GPTU)

Figure 3-11 shows a global view of the functional blocks of the General Purpose Timer Unit (GPTU). Figure 3-11 General Block Diagra m of the GPTU Interface The GPTU consists of three 32 -bit timers designed to so lve such application tasks as event timing, event counting , and event recording. The GPTU communicates with the external world via eight I/O lines located at Port 0. The three timers of GPTU module, T0, T1 and T2, can operate independently of each other or can be combined: General Features:

• All timers are 32-bit precision time rs with a maximum input frequency of fGPTU
• Events generated in T0 or T1 c an be used to trigger actions in T2
• Timer overflow or underflow in T2 ca n be used to clock either T0 or T1
• T0 and T1 can be concatenated to form one 64-bit timer Features of T0 and T1:
• Each timer has a dedicated 32-b it reload register with automatic reload on overflow
• Timers can be split into indi vidual 8-, 16-, or 24-bit ti mers with individual reload registers Clock Control Address Decoder Interrupt Control fGPTU0 GPTU Module Port 0 Control P0.0/GPTU_0 SR0 SR1 SR2 SR3 SR4 SR5 SR6 SR7 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 P0.1/GPTU_1 P0.2/GPTU_2 P0.3/GPTU_3 P0.4/GPTU_4 P0.5/GPTU_5 P0.6/GPTU_6 P0.7/GPTU_7

Data Sheet 53 V1.1, 2008-12

• Overflow signals can be selected to generate service requests, pin output signals, and T2 trigger events
• Two input pins can define a count option Features of T2:
• Count up or down is selectable
• Operating modes: –T i m e r – Counter – Quadrature counter (incremental/p hase encoded counter interface)
• Options: – External start/stop, one-shot operati on, timer clear on external event – Count direction control through software or an external event – Two 32-bit reload/ capture registers
• Reload modes: – Reload on overflow or underflow – Reload on external event: pos itive transition, negative transition, or both transitions
• Capture modes: – Capture on external event: positive tr ansition, negative transition, or both transitions – Capture and clear timer on external event: positive transition, negative transition, or both transitions
• Can be split into two 16-bit counter/timers
• Timer count, reload, capture, and trigger functions can be assigned to input pins. T0 and T1 overflow events can also be assigned to these functions.
• Overflow and underflo w signals can be used to trigge r T0 and/or T1 and to toggle output pins
• T2 events are freely assignable to the service request nodes

Data Sheet 54 V1.1, 2008-12

3.16 Capture/Compare Unit 6 (CCU6)

Figure 3-12 shows a global view of the functional blocks of two Capture/Compare Units (CCU60 and CCU61). Both of the CCU6 modules are further supplied with clock control, inte rrupt control, address decoding, and port control logic. One DMA request can be generated by each CCU6 module. Each CCU6 provides two ind ependent timers (T12, T13), which can be used for PWM generation, especially for AC-motor control. Additionally, special control modes for block commutation and multi-phase machines are supported. Timer 12 Features:

• Three capture/compare channel s, each channel can be used either as capture or as compare channel
• Generation of a three-phase PWM supported (six output s, individual signals for highside and lowside switches)
• 16-bit resolution, ma ximum count frequency = peripheral clock
• Dead-time control for each channel to avoid short-circuits in the power stage
• Concurrent update of the required T12/13 registers
• Center-aligned and edge-al igned PWM can be generated
• Single-shot mode supported
• Many interrupt request sources
• Hysteresis-like control mode Timer 13 Features:
• One independent compare channel with one output
• 16-bit resolution, ma ximum count frequency = peripheral clock
• Can be synchr onized to T12
• Interrupt generation at pe riod-match and compare-match
• Single-shot mode supported Additional Features:
• Block commutation for Brushless DC-drives implemented
• Position detection vi a Hall-sensor pattern
• Automatic rotational speed me asurement for block commutation
• Integrated error handling
• Fast emergency stop without CPU l oad via external signal (CTRAP
• Control modes for mu lti-channel AC-drives
• Output levels can be selected and adapted to the power stage

Data Sheet 55 V1.1, 2008-12 Figure 3-12 General Block Diag ram of the CCU6 Interfaces Interrupt Control TC1130_CCU6_imple CCU60 Module (Kernel) Port 2 Control To DMA Clock Control Address Decoder fCCU To DMA SRC0 SRC1 SRC2 SRC3 P2.6 /CC600 P2.12 /CTRAP0 CC62 COUT62 COUT61 COUT63 CC60 COUT60 CCPOS2 CC61 /CTRAP CCPOS0 CCPOS1 P2.13 /CCPOS00 P2.14 /CCPOS01 P2.15 /CCPOS02 P2.7 /COUT600 P2.8 /CC601 P2.9 /COUT601 P2.10 /CC602 P2.11 /COUT602 P2.5 /COUT603 CCU61 Module (Kernel) Port 3 Control P3.1 /CC610 P3.7 /CTRAP1 CC62 COUT62 COUT61 COUT63 CC60 COUT60 CCPOS2 CC61 /CTRAP CCPOS0 CCPOS1 P3.8 /CCPOS10 P3.9 /CCPOS11 P3.10 /CCPOS12 P3.2 /COUT610 P3.3 /CC611 P3.4 /COUT611 P3.5 /CC612 P3.6 /COUT612 P3.0 /COUT613 SRC0 SRC1 SRC2 SRC3 P0.5 / CCU60_T12HR P0.6 / CCU60_T13HR T12HR T13HR P3.11 / CCU61_T12HR P3.12 / CCU61_T13HR T12HR T13HR

Data Sheet 56 V1.1, 2008-12

3.17 Ethernet Controller

The MAC controller implements the IEEE 802.3 and operates either at 100 Mbit/sec or 10 Mbit/sec. Figure 3-13 shows a global view of the Ethernet Controller module with the module specific interface connections. Figure 3-13 General Block Diagram of the Ethernet Controller The Ethernet controller comprises the following functional blocks:

• Media Access Controller (MAC)
• Receive Buffer (RB)
• Transmit Buffer (TB)
• Data Management Unit in Receive Direction (DMUR)
• Data Management Unit in Transmit Direction (DMUT) MCB04942mod Port Control P1.14 / MII_RxER FPI (M/S) P1.13 / MII_RxD[3] P1.12 / MII_RxD[2] P1.11 / MII_RxD[1] P1.10 / MII_RxD[0] P1.9 / MII_COL P1.8 / MII_CRS P1.7 / MII_RxDV P1.6 / MII_MDC P1.5 / MII_TxEN P1.4 / MII_TxER P1.3 / MII_TxD[3] P1.2 / MII_TxD[2] P1.1 / MII_TxD[1] P1.0 / MII_TxD[0] MII_TxCLK MII_TxCLK MII_TDIO MIIMAC Ethernet Controller RB TB DMUR DMUT

Data Sheet 57 V1.1, 2008-12 RB and TB provide on-chip data bufferi ng whereas DMUR and DMUT perform data transfer from/to the shared memory. Two interfaces are provided by the Ethernet Controller module:

• MII interface for connection of Et hernet PHYs via 18 Input/Output lines
• Master/slave FPI bus interf ace for connection to the on-chip system bus for data transfer as well as configuration Features:
• Media Independent Interface (M II) according to IEEE 802.3
• Supports 10 or 100 Mbit/sec MII-based Physical devices
• Supports Full Du plex Ethernet
• Supports data transfer between Et hernet Controller and COM-DRAM
• Supports data transfer between Ethe rnet Controller and SDRAM via EBU
• 256 x 32 bit Receive buffe r and Transmit buffer each
• Supports burst transfers up to 8 x 32 Bytes Media Access Controller (MAC)
• 100/10 Mbit/sec operations
• Full IEEE 802.3 compliance
• Station manage ment signaling
• Large on-chip CAM (Conte nt Addressable Memory)
• Full duplex mode
• 80-byte transmit FIFO
• 16-byte receive FIFO
• PAUSE Operation
• Flexible MAC Control Support
• Supports Long Pack et mode and Short Packet mode
• PAD generation Media Independent Interface (MII)
• Media independence
• Multi-vendor point of interoperability
• Supports connection of MAC layer and Physical (PHY) layer devices
• Capable of supporting both 100 Mbit/sec and 10 Mbit/sec data rates
• Data and delimiters are sync hronous to clock references
• Provides independent fo ur bits wide transmit and receive data paths
• Supports connection of PHY layer a nd Station Management (STA) devices
• Provides a simple m anagement interface
• Capable of drivin g a limited length of shielded cable

Data Sheet 58 V1.1, 2008-12

3.18 System Timer

The STM within the TC1130 is designed for global system timing applications requiring both high precision and long range. The STM provides the following features:

• Free-running 56 -bit counter
• All 56 bits can be read synchronously
• Different 32-bit portions of the 56 -bit counter can be read synchronously
• Flexible interrupt gene ration on partial STM content compare match
• Driven by clock fSTM after reset (default after reset is fSTM = fSYS = 150 MHz)
• Counting starts automatica lly after a reset operation
• STM is reset under following reset causes: – Wake-up reset (PMG_CON.DSRW must be set) – Software reset (RST_REQ .RRSTM must be set) – Power-on reset
• STM (and the clock divider) is not reset at watch dog reset and hardware reset (HDRST = 0) The STM is an upward counter, running with the system clock frequency fSYS (after reset fSTM = fSYS). It is enabled per default after rese t, and immediately starts counting up. Other than via reset, it is not possible to affect the contents of the timer during normal operation of the application; it can only be read, but not written to. Depending on the implementation of the clock control of the STM, the timer ca n optionally be disabled or suspended for power-saving and debugging purposes via a clock control register. The maximum clock period is 256/fSTM. At fSTM = 150 MHz (maximum), for example, the STM counts 15.2 years before overflowing. Thus, it is capable of continuously timing the entire expected product lifetime of a system without overflowing.

Data Sheet 59 V1.1, 2008-12 Figure 3-14 Block Diagram of the STM Module STM Module 00H CAP TIM6 TIM5 TIM4 TIM3 TIM2 TIM1 TIM0 00H 55 47 39 31 23 15 7 56-Bit System Timer Address Decoder Clock Control Enable / Disable fSTM MCA04795_mod 31 23 15 7 Compare Register CMP0 Interrupt Control Compare Register CMP1 STMIR1 STMIR0 PORST 31 23 15 7 0

Data Sheet 60 V1.1, 2008-12

3.19 Watchdog Timer

The Watchdog Timer (W DT) provides a highly reliable and secure way to detect and recover from software or hardware failure. The WD T helps to abor t an accidental malfunction of the TC1130 in a user-specified time period. When enabled, the WDT will cause the TC1130 system to be reset if the WDT is not serviced within a user-programmable time period. The CPU must service the WDT within this time interval to prevent the WDT from causing a TC1130 system reset. Hence, routine service of the WDT confirms that the system is functioning properly. In addition to this standar d “Watchdog” function, the WDT incorpor ates the ENDINIT feature and monitors its modifications. A system-wide line is connected to the ENDINIT bit implemented in a WDT contro l register, serving as an a dditional write-protection for critical registers (besides supervisor mode pr otection). Registers protected via this line can be modified only when supervisor mode is active and bit ENDINIT = 0. A further enhancement in the TC1130’s Watchdog Timer is its reset prewarning operation. Instead of immediat ely resetting the device upon detection of an error, the WDT first issues a Non-Maskable Interrupt (NMI) to the CPU before finally resetting the device at a specified time period later. This gives the CPU a chance to save system state to memory for later examinat ion of the cause of the malfunction, thus providing an important aid in debugging. Features:

• 16-bit Watchdog counter
• Selectable input frequency: fSYS/256 or fSYS/16384
• 16-bit user-definable reload value for norm al Watchdog operation, fixed reload value for time-out and prewarning modes
• Incorporation of the ENDINIT bit and monitoring of its modifications
• Sophisticated password ac cess mechanism with fixed and user-definable password fields
• Proper access always requires two writ e accesses. The time between the two accesses is monitored by the WDT.
• Access Error Detection: Invalid password (during first access) or invalid guard bits (during second access) trigger the Watchdog reset generation.
• Overflow Error Detection: An overflow of the counter trigger s the Watchdog reset generation.
• Watchdog function can be di sabled; access protection and ENDINIT monitor function remain enabled.
• Double Reset Detection: If a Watchdog induced reset oc curs twice without a proper access to its control register in between, a severe system malfunction is assumed and the TC1130 is held in reset until a powe r-on reset or a hardwar e reset occurs. This prevents the device from be ing periodically reset if, for instance, connection to the

Data Sheet 61 V1.1, 2008-12 external memory has been lost such that even system initiali zation could not be performed.

• Important debugging support is provided through the reset prewarning operation by first issuing an NMI to the CPU before finally resetting the device after a certain period of time.

Data Sheet 62 V1.1, 2008-12

3.20 System Control Unit

The System Control Unit (SCU) of the TC1130 handles the system control tasks. All of these system functions are tightly coupled; th us, they are conveniently handled by one unit, the SCU. The system tasks of the SCU are:

• C l o c k C o n t r o l – Clock generation – Oscillator and PLL control
• Reset and Boot Control – Generation of all in ternal reset signals – Generation of external hard ware and software reset signal
• Power Management Control – Enabling of several power management modes
• Configuration input sampling
• Ethernet Interrupts
• FPU interrupts
• External Request Unit
• Parity Error Control
• Fault SRAM Fuse Box
• CSCOMB Control
• EBU Pull-Up Control
• NMI Control and Status
• DMA Request Signal Selection

Data Sheet 63 V1.1, 2008-12

3.21 Boot Options

The TC1130 booting schemes provides a number of different boot options for the start of code execution. Table 3-3 shows the boot options available in the TC1130. Table 3-3 Boot Selections BRKIN1) 1) This input signal is active low. TM1) HWCFG [2:0] Type of Boot PC Start Value (User Entry) 11 0 0 0 Bootstrap Loader Serial boot from ASC to PMI scratch pad, run loaded program DFFF FFFCH (D400 0000H) 2) This is the BootROM entry address; the start address of user program in parentheses.

001 Bootstrap Loader

Serial boot from CAN to PMI scratch pad, run loaded program

010 Bootstrap Loader

Serial boot from SSC to PMI scratch pad, run loaded program

011 External memory, EBU as master DFFF FFFC H

(A000 0000H)

100 External memory, EBU as slave DFFF FFFC H

(A000 0000H)

101 Reserved (STOP) ----

110 PMI scratch pad D400 0000 H

111 Reserved (STOP) DFFF FFFC H

1 0 000-111 Reserved (STOP) DFFF FFFC H 0 1 000 Tristate chip ----

001 Go to external em ulator space DFFF FFFC H

(DE00 0000H)

010 Reserved (STOP) ----

011 OSC and PLL Bypass ----

100-111 Reserved (STOP) DFFFFFFC H 0 0 000-111 Reserved (STOP) DFFFFFFC H

Data Sheet 64 V1.1, 2008-12

3.22 Power Management System

The TC1130 power man agement system allows softwa re to configur e the various processing units to adjust automatically in order to draw the minimum necessary power for the application. There are four power management modes:

• Run Mode
• Idle Mode
• Sleep Mode
• Deep Sleep Mode Table 3-4 describes the features of the power management modes. Besides these expl icit software-controlled power-sav ing modes, specia l attention has been paid in the TC1130 to automatic power-saving in operating units that are currently not required or idle. In this case, they are shut off automatically until their operation is required again. Table 3-4 Power Managem ent Mode Summary Mode Description Run The system is fully operational. All clocks and peripherals are enabled, as determined by software. Idle The CPU clock is disabled, waiting for a condition to return it to run mode. Idle mode can be entered by software when the processor has no active tasks to perform. All peripherals remain powered and clocked. Processor memory is accessible to peripherals. A reset, Watchdog Timer event, a falling edge on the NMI pin, or any enabled interrupt event will return the system to run mode. Sleep The system clock continues to be distributed only to those peripherals programmed to operate in sleep mode. The other peripheral modules will be shut down by the suspend signal. Interrupts from operating peripherals, the Watchdog Timer, a falling edge on the NMI pin, or a reset event will return the system to run mode. Entering this state requires an orderly shut-down controlled by the Power Management State Machine. Deep Sleep The system clock is shut off; only an external signal will restart the system. Entering this state requires an orderly shut-down controlled by the Power Management State Machine (PMSM).

Data Sheet 65 V1.1, 2008-12

3.23 On-Chip Debug Support

The On-Chip Debug Support of the TC1130 consists of the following building blocks:

• OCDS L1 module of TriCore™
• OCDS L2 interface of TriCore™
• OCDS L1 module in th e BCU of the FPI Bus
• OCDS L1 facilities within the DMA
• OCDS L2 interface of DMA
• OCDS System Control Unit (OSCU)
• Multi Core Break Switch (MCBS)
• JTAG based Debug Interface (Cerberus JDI)
• Suspend functionality of peripherals Features:
• TriCore™ L1 OCDS: – Hardware event generation unit – Break by DEBUG instru ction or break signal – Full Single-Step support in hardware , possible also with software break – Access to memory, SF Rs, etc. on the fly
• DMA L1 OCDS: – Output break request on errors – Suspension of pre- selected channels
• Level 2 trace port with 16 pins that outputs either TriCore™, or DMA trace
• OCDS System Control Unit (Cerberus OSCU) – Minimum number of pins required (no OCDS enable pin) – Hardware allows hot attach of a debugger to a running system – System is secure (can be locked from internal)
• Multi Core Break Switch (Cerberus MCBS): – TriCore™, DMA, break pins, and BCUs as break sources – TriCore™ as break targets; other parts can in addition be suspended – Synchronous stop and restart of the system – Break to Susp end converter Figure 3-15 shows a basic block diagram of the building blocks.

Data Sheet 66 V1.1, 2008-12 Figure 3-15 OCDS Support Basic Block Diagram Enable, Control and Reset TC1130 OCDS Block Diagram BCU TriCoreTM OCDS OCDS OCDS DMA FPI Watch- dog timer Periph.1 Periph.n JDI Debug I/F JTAG Controller MCBS Break Switch Ce rber us OSCU Break and Suspend Signals Multiplexer DMA L2 BRKIN TDI TDO BRKOUT TRST TMS TCK OCDS2[15:0]

Data Sheet 67 V1.1, 2008-12

3.24 Clock Generation Unit

The Clock Generation Unit (CGU) allows a flexible clock genera tion for TC1130. The power consumption is indirectly proportional to the frequency, whereas the performance of the microcontroller is directly proportion al to the frequency. During user program execution, the frequency can be programmed for an optimal ratio between performance and power consumption. Therefore, the power consumption can be adapted to the actual application state. Features: The Clock Generation Unit serves several purposes:

• PLL feature for multiplying clo ck source by different factors
• Direct Drive for direct clock input
• Comfortable state machine for secure switching between basic PLL, direct, or prescaler operation
• Sleep and Power-d own mode support
• USB Clock source and control The Clock Generation Unit in the TC1130, shown in Figure 3-16, consists of an oscillator circuit and one Phase-Locked Loop (PLL). The PLL can conver t a low-frequency external clock signal to a high-speed internal clock for maximum performance. The PLL also has fail-safe logic that detects degenerate external clock behavior such as abnormal frequency deviations or a tota l loss of the external cloc k. It can execute emergency actions if it looses the lock on the external clock. In general, the Clock Generati on Unit (CGU) is controlled through the System Control Unit (SCU) module of the TC1130. Figure 3-16 Clock Generation Unit Block Diagram MCA04940mod Oscillator Circuit XTAL1 XTAL2 fOSC Phase Detect. VCO N Divider PLL fVCO 1:1/1:2 Divider fSYS Lock Detector OSCR PLL_ LOCK NDIV [6:0] VCO_ BYPASS KDIV [3:0] PLL_ BYPASS System Control Unit SCU Register PLL_CLC MUX MUX K:1/K:2 Divider VCO_ SEL[1:0] fCPU SYS FSL Clock Generation Unit CGU P Divi- der Osc. Run Detect. PDIV [2:0] OSC DISC P4.0/ USBCLK Divider MUX fUSB Register SCU_CON USBC LDIV USBC LSEL Register OSC_CON MOSCOGC

Data Sheet 69 V1.1, 2008-12 A block capacitor between VDDOSC3 and VSSOSC, VDDOSC and VSSOSC is recommended, too. 20 10 24 10 Table 3-5 Load Capacitors Select (cont’d) Fundamental Mode Crystal Frequency (approx., MHz) Load Capacitors C1, C2 (pF)

Data Sheet 70 V1.1, 2008-12

3.25 Power Supply

The TC1130 provides an ingenious power supply concept in order to improve the EMI behavior as well as to minimize the crosstalk within on-chip modules. Figure 3-18 shows the TC1130’s power supply concept, where cert ain logic modules are individually supplied with power. This concept improves the EMI behavior by reduction of the noise cross coupling. Figure 3-18 TC1130 Po wer Supply Concept MCB04953mod DMU DMI PMI CPU & Peripheral Logic GPIO Ports (P0-P4) EBU PortsOSC VDDO SC3 (3.3V) VSS VDDO SC (1.5V) VSS VDDP (3.3 V) VSS V SS (1.5 V) V DD

Data Sheet 71 V1.1, 2008-12

3.26 Power Sequencing

During power-up, reset pin PORST has to be held active until both power supply voltages have reached at least their minimum values. During the power-up time (rising of the supply voltages from 0 to their regular operating values), it must be ensured that the core VDD power supply reaches its operating value first, and then follow ed by the GPIO V DDP power supply. During t he rising time of the core voltage, it must be ensured that 0< VDD-VDDP <0.5 V. During power-down, the core power supply VDD and GPIO power supply VDDP must be switched off completely unti l all capacitances are discharged to ze ro before the next power-up. Note: The state of the pins are unde fined when only the port voltage V DDP is switched on.

Data Sheet 72 V1.1, 2008-12

3.27 Identification Register Values

Table 3-6 TC1130 Identification Registers Short Name Address Value SCU_ID F000 0008 H 002C C001H MANID F000 0070 H 0000 1820H CHIPID F000 0074 H 0000 8C01H RTID F000 0078 H 0000 0000H SBCU_ID F000 0108 H 0000 6A0AH STM_ID F000 0208 H 0000 C005H CBS_JDPID F000 0308 H 0000 6307H GPTU_ID F000 0608 H 0001 C002H CCU60_ID F000 2008 H 0042 C004H CCU61_ID F000 2108 H 0042 C004H DMA_ID F000 3C08 H 001A C011H CAN_ID F000 4008 H 002B C022H USB_ID F00E 2808 H 0000 4A00H SSC0_ID F010 0108 H 0000 4530H SSC1_ID F010 0208 H 0000 4530H ASC0_ID F010 0308 H 0000 44E2H ASC1_ID F010 0408 H 0000 44E2H ASC2_ID F010 0508 H 0000 44E2H IIC_ID F010 0608 H 0000 4604H MLI0_ID F010 C008 H 0025 C004H MLI1_ID F010 C108 H 0025 C004H MCHK_ID F010 C208 H 001B C001H CPS_ID F7E0 FF08 H 0015 C006H MMU_ID F7E1 8008 H 0009 C002H CPU_ID F7E1 FE18 H 000A C005H EBU_ID F800 0008 H 0014 C004H DMU_ID F800 0408 H 002D C001H DMI_ID F87F FC08 H 0008 C004H PMI_ID F87F FD08 H 000B C004H

Data Sheet 73 V1.1, 2008-12 LBCU_ID F87F FE08 H 000F C005H LFI_ID F87F FF08 H 000C C005H Table 3-6 TC1130 Identification Registers (cont’d) Short Name Address Value

Data Sheet 74 V1.1, 2008-12

4 Electrical Parameters

4.1 General Parameters

4.1.1 Parameter Interpretation

The parameters listed in this section represent partly the characteristics of the TC1130 and partly its requirements on the system. To aid interpre ting the parameters easily when evaluating them for design purposes, they are indicated by the abbreviations in the “Symbol” column:

• CC These parameters indicate Controller Characteristics, which are distinctive features of the TC1130 and must be considered for system design.
• SR These parameters indicate System Requirements, which mu st be provided by the microcontroller system in which the TC1130 is included.

Data Sheet 75 V1.1, 2008-12

4.1.2 Absolute Maximum Rating

Parameter Symbol Limit Values Unit Notes min. max. Ambient temperature TA -40 85 °C under bias Storage temperature TST -65 150 °C– Junction temperature TJ -40 125 °C under bias Voltage at 1.5 V power supply pins with respect to VSS 1) Applicable for VDD and VDDOSC. VDD -0.5 1.7 V – Voltage at 3.3 V power supply pins with respect to VSS 2) Applicable for VDDP and VDDOSC3. The maximum voltage difference must not exceed 4.0 V in any case (i.e. Supply Voltage = 4.0 V and Input Voltage = -0.5 V is not allowed). VDDP -0.5 4.0 V – Voltage on any pin with respect to VSS VIN -0.5 4.0 V – Input current on any pin during overload condition IIN -10 10 mA – Absolute sum of all input currents during overload condition ΣIIN – |100| mA – CPU & LMB Bus Frequency fSYS –1 5 0 M H z – FPI Bus Frequency fFPI –1 0 0 M H z –

Data Sheet 76 V1.1, 2008-12

4.1.3 Operating Condition

The following operating conditions must be complied with in order to ensure correct operation of the TC1130 . All parameters specif ied in the following table refer to these operating conditions, unless otherwise indicated. Parameter Symbol Limit Values Unit Notes Conditionsmin. max. Digital supply voltage VDD 1.43 1.58 V – VDDP 3.14 3.47 V – Digital ground voltage VSS 0V – Digital core supply current IDD –5 2 5 m A – Ambient temperature under bias TA -40 +85 °C– CPU clock fSYS –1) 1) The TC1130 uses a static design, so the minimum oper ation frequency is 0 MHz. However, due to test time restriction no lower frequency boundary is tested.

150 MHz –

Overload current IOV -1 1 mA 2)3) 2) Overload conditions occur if the standard operating condi tions are exceeded, i.e. the voltage on any pin overload currents on all digital I/O pins may not exceed 50 mA. The supply voltage must remain within the specified limits. 3) Not subject to production test, verified by design/characterization. -3 3 duty cycle ≤ 25% Short circuit current ISC -1 1 mA 4) 4) Applicable for digital inputs. -3 3 duty cycle ≤ 25% Absolute sum of overload + short circuit currents Σ|IOV|+ |ISC| –| 5 0 | m A 3) |100| duty cycle ≤ 25% Inactive device pin current (VDD =V DDP =0 ) IID -1 1 mA – External load capacitance CL –5 0 p F – ESD strength – 2000 – V Human Body Model (HBM)

Data Sheet 77 V1.1, 2008-12

4.2 DC Parameters

4.2.1 Input/Output Characteristics

Table 4-1 Input/Output DC-Characteristics (Operating Conditions apply) Parameter Symbol Limit Valu es Unit Test Condition min. max. GPIO pins, Dedicated pins and EBU pins Input low voltage VIL SR -0.3 0.8 V LvTTL Input high voltage VIH SR 2.0 V DDP + 0.3 VL v T T L Output low voltage VOL CC – 0.4 V I OL = 2mA Output high voltage VOH CC 2.4 – V I OH = -2mA Pull-up current 1) 1) The current is applicable to the pins, for which a pull-up has been specified. Refer to Table 2-1. IPUx refers to the pull-up current for type x in absolute values. |IPUA|CC −1 4 9 μ A VIN = 0V |IPUC|CC −7 . 2 μ A VIN = 0V Pull-down current 2) 2) The current is applicable to the pins, for which a pull-down has been specified. Refer to Table 2-1. IPDx refers to the pull-down current for type x in absolute values. |IPDA|CC – 156 μA VIN = VDDP |IPDC|CC – 15.7 μA VIN = VDDP Input leakage current 3) 3) Excluded following pins: NMI , TRST , TCK, TDI, TMS, MII_ TXCLK, MII_ RXCLK, MII_ MDIO, ALE, P2.1,HWCFG0, HWCFG1, HWCFG2, BRKIN, PORST, HDRST. IOZ1 CC – ±350 nA 0 < VIN < VDDP Pin Capacitance 4) 4) Not subject to production test, verified by design/characterization. CIO CC – 10 pF f = 1 MHz TA = 25 °C

Data Sheet 78 V1.1, 2008-12

4.2.2 Oscillator Characteristics

Table 4-2 Oscillator Pins Characteristics (Operating Conditions apply) Parameter Symbol Limit Valu es Unit Test Condition min. max. Oscillator Pins Input low voltage at XTAL1 VILX SR -0.3 – V 1) 1) Quartz mode: using a quartz crystal Input high voltage at XTAL1 VIHX S R –3V 1) Quartz oscillation peak-peak amplitude at oscillator Input VPPOSC SR 0.6 – V 1) Input low voltage at XTAL1 VILX SR -0.3 0.1 V 2) 2) Bypass mode: using an external clock Input high voltage at XTAL1 VIHX SR 1.4 VDDC + 0.3V V 2) Oscillator input current IOSCIN –2 5 μA–

Data Sheet 79 V1.1, 2008-12

4.2.3 USB Characteristics

4.2.3.1 DC Electrical Characteristics

Table 4-3 USB Electrical Characteristics (Operating Conditions apply)

4.2.3.2 Full Speed Electrical Characteristics

Table 4-4 Full Speed Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Input Level Differential Input Level VDI 0.2 – – V | V(D+) - V(D-)| Differential Common Mode Range VDCM 0.8 – 2.5 V Range of Sensitivity Single Ended Receiver Threshold VSE low < 0.8 – high > 2.0 Output Levels Static Output Low VSOL – – < 0.3 V with 1.5 k Ω to 3.6 V Static Output High VSOH 2.8 3.3 3.6 V with 15 k Ω to ground Leakage Current Hi_Z State Data Line Leakage VHIZ -10 – 10 μA0 < V in < 3.3 V Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Driver Characteristics Rise/Fall Time tRF 4 – 20 ns Capacitive load 50 pF Rise/Fall Time Matching tRFM 90 100 110 % Capacitive load 50 pF Crossover Voltage of Differential Signals VCV 1.3 – 2.0 V Capacitive load 50 pF

Data Sheet 80 V1.1, 2008-12 Figure 4-1 USB Interface Driver Output Impedance RDO 28 – 44 Ω Steady State Driver Termination Impedance RT 1.425 1.5 1.575 k Ω – Parameter Symbol Limit Values Unit Test Conditions min. typ. max. USB Interface 22 Ω 22 Ω 1.5kΩ RS RS D + D - VDDP VDDP VDDP

Data Sheet 81 V1.1, 2008-12

4.2.4 IIC Characteristics

Each IIC Pin is an open drain output pin with different characteristics than other pins. The related characteristics are given in the following table. Table 4-5 IIC Pin Characteristics (Operating Conditions Apply) Note: No 5 V IIC interface is supported with these pads. Only voltages lower than 3.63 V must be applied to these pads. Note: IIC pins have no pull-up and pull-down devices. Parameter Symbol Lim it Values Unit Test Conditionsmin. max. Output low voltage V OL CC – 0.4 0.6 V3 m A s i n k current 6 mA sink current Input high voltage 1) Not subject to production test, verified by design/characterization. VIH SR 0.7V DDP VDDP+0.5 V – Input low voltage1) VIL SR -0.5 0.3V DDP V–

Data Sheet 82 V1.1, 2008-12

4.2.5 Power Supply Current

Table 4-6 Power Supply Currents (Operating Conditions apply) Parameter Symbol Limit Va lues Unit Test Conditions typ. 1) 1) Typical values are measured at 25°C, CPU clock at 150 MHz, and nominal supply voltage that is 3.3 V for VDDP, VDDOSC3 and 1.5 V for VDD, VDDOSC. These currents are measured using a typical application pattern. The power consumption of modules can increase or decrease using other application programs. max. Active mode supply current IDD 314 679 mA Sum of IDDS 2) 2) These power supply currents are defined as the sum of all currents at the VDD power supply lines: VDD + VDDP + VDDOSC3 + VDDOSC 153 345 mA IDD at VDD 3) 3) This measurement includes the TriCoreTM and Logic power supply lines. 156 322 mA IDD at VDDP Idle mode supply current IID 74 154 mA Sum of IDDS 2)4) 4) CPU is in idle state, input clocks to all peripherals are enabled. 66 130 mA IDD at VDD 3)4) 61 5 m A IDD at VDDP Deep sleep mode supply current IDS 2 19 mA Sum of IDDS 2)5) 5) Clock generation is disabled at the source. 21 9 m A IDD at VDD 3)5) 3.6 58 μA IDD at VDDP

Data Sheet 83 V1.1, 2008-12

4.3 AC Parameters

4.3.1 Power, Pad and Reset Timing

Parameter Symbol Limit Values Unit min. max. Min. VDDP voltage to ensure defined pad states1) 1) This parameter is valid under assumption that PORST si gnal is constantly at low level during the power-up/ power-down of the VDDP. VDDPPA CC 0.6 – V Oscillator start-up time2) 2) Not subject to production test, verified by design/characterization. tOSCS CC – 30 ms Minimum PORST active time after power supplies are stable at operating levels tPOA CC 50 – ms HDRST pulse width tHD CC 1024 cycles3) 3) Any HDRST activation is internally prolonged to 1024 FPI bus clock cycles. fSYS Ports inactive after any reset active2) tPI CC – 30 ns

Data Sheet 84 V1.1, 2008-12 Figure 4-2 Power and Reset Timing reset_beh 1) as programmed VDDP PORST HDRST Pads Pad- state undefined tpi VDD VDDPPA VDDPPA Pad- state undefined 2) Tri-state, pull device active thd VDDPR OSC toscs 1) 2) 1) 2)2) tPOA tPOA thd

Data Sheet 85 V1.1, 2008-12

4.3.2 PLL Parameters

When PLL operation is configured (PLL_CLC.LOCK = 1), the on-chip phase locked loop is enabled and provides the master clock. The PLL multiplies the input frequency by the factor F (fMC = fOSC × F) which results from the input divider, the multiplication factor (N Factor), and the output divider ( F = NDIV+1 / (PDIV+1 × KDIV+1) ). The PLL circuit synchronizes the master clock to the input clock. This synchronization is done smoothly, i.e. the master clock frequency does not change abruptly. Due to this adaptation to the input clock, the frequency of fMC is constantly adjusted so it is locked to fOSC. The slight variati on causes a jitter of fMC which also affects the duration of individual TCMs. The timing listed in the AC Characteristics refers to TCPs. Because fCPU is derived from fMC, the timing must be calculated using the minimum TCP possible under the respective circumstances. The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is constantly adjusting its outp ut frequency in order to correspond to the applied input frequency (crystal or oscillator), the relative deviation for periods of more than one TCP is lower than for one single TCP (see formula and Figure 4-3). This is especially importan t for bus cycles using waitst ates and for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measur ement, lower baud rates, etc.) th e deviation caused by the PLL jitter is negligible. The value of the accumulated PLL jitter depends on the number of consecutive VCO output cycles within the resp ective timeframe. The VCO outp ut clock is divided by the output prescaler (K = KDIV+1) to generate the master clock signal fMC. Therefore, the number of VCO cycles ca n be represented as K × N, where N is the number of consecutive fMC cycles (TCM). For a period of N × TCM, the accumulated PLL jitter is defined by the corresponding deviation DN: DN [ns] = ±(1.5 + 6.32 × N / fMC); fMC in [MHz], N = number of consecutive TCMs. So, for a period of 3 TCMs @ 20 MHz and K = 12: D3 = ±(1.5 + 6.32 × 3 / 20) = 2.448 ns. This formula is applicable for K × N < 95. For longer periods, the K×N=95 value can be used. This steady value can be approximated by: DNmax [ns] = ±(1.5 + 600 / (K × fMC)).

Data Sheet 86 V1.1, 2008-12 Figure 4-3 Approximated Accumulated PLL Jitter Note: The bold lines indicate the minimum accumulated jitter which can be achieved by selecting the maximum possible output prescaler factor K. Different frequency bands can be selected for the VCO, so the operation of the PLL can be adjusted to a wide range of input and output frequencies: Table 4-7 VCO Bands for PLL Operation PLL_CLC.VCOSEL VCO Frequency Ra nge Base Frequency Range 1) Base Frequency Range is the free running operation frequency of the PLL, when no input clock is available.

11 Reserved 2)

2) This option cannot be used. mcb04413_xc.vsd Acc. jitter DN ns 0 51 0 2 0 25 N

10 MHz

K=5

20 MHz

40 MHz

K=6K=12K=15 K=8K=10

Data Sheet 87 V1.1, 2008-12

4.3.3 AC Characteristics

(Operating Conditions apply) Figure 4-4 Input/Output Waveforms for AC Tests - for GPIO, Dedicated and EBU pins 2.0V 0.8V test points 2.0V 0.8V 2.4V 0.4V AC inputs during testing are driven at 2.4V for a logic “1” and 0.4V for a logic “0”. Timing measurements are made at VIHmin for a logic “1” and VILmax for a logic “0”.

Data Sheet 88 V1.1, 2008-12

4.3.4 Input Clock Timing

(Operating Conditions apply) Figure 4-5 Input Clock Timing Parameter Symbol Limits Unit min max Oscillator clock frequency with PLL fOSC SR 4 25 MHz Input clock frequency driving at XTAL1 with PLL fOSCDD SR -4 0 M H z Input Clock Duty Cycle (t1 /t2) S R 4 55 5% Input Clock at XTAL1

0.5 VDD

Data Sheet 89 V1.1, 2008-12

4.3.5 Port Timing

(Operating Conditions apply; CL=50pF) Figure 4-6 Port Timing Parameter Symbol Limits Unit min max Port data valid from TRCLK 1) up to 120 MHz2) 1) Port data is output with respect to the FPI clock. The TRCLK is used as a reference here since the FPI clock is not available as an external pin and TRCLK is same frequency as CPU clock. Port lines maintain their states for at least 2 CPU clocks. 2) 120 MHz is verified by design/characterization. t1 CC − 13 ns TRCLK Old State New State Port Lines FPI_CLK

Data Sheet 90 V1.1, 2008-12

4.3.6 Timing for JTAG Signals

(Operating Conditions apply; CL=50pF) Figure 4-7 TCK Clock Timing Parameter Symbol Limits Unit min max TCK clock period tTCK SR 50 − ns TCK high time t1 SR 10 − ns TCK low time t2 SR 29 − ns TCK clock rise time t3 SR − 0.4 ns TCK clock fall time t4 SR − 0.4 ns TCK

0.9 VDD

0.1 VDD

Data Sheet 91 V1.1, 2008-12 Figure 4-8 JTAG Timing Parameter Symbol Limits Unit min max TMS setup to TCK t1 SR 7.85 − ns TMS hold to TCK t2 SR 3.0 − ns TDI setup to TCK t1 SR 10.9 − ns TDI hold to TCK t2 SR 3.0 − ns TDO valid output from TCK t3 CC − 10.7 ns TDO high impedance to valid output from TCK t4 CC − 23.0 ns TDO valid output to high impedance from TCK t5 CC − 26.0 ns TMS TDI TCK TDO t4 t3 t5

Data Sheet 92 V1.1, 2008-12

4.3.7 Timing for OCDS Trace and Breakpoint Signals

(Operating Conditions apply; CL(TRCLK) = 25 pF, CL = 50 pF) Figure 4-9 OCDS Trace Signals Timing Parameter Symbol Limits Unit min max BRK_OUT valid from TRCLK t1 CC − 5.2 ns OCDS2_STATUS[4:0] valid from TRCLK t1 CC 0 5 ns OCDS2_INDIR_PC[7:0] valid from TRCLK t1 CC 0 5 ns OCDS2_BRKPT[2:0] valid from TRCLK t1 CC 0 5 ns CPU Trace Signals TRCLK Old State New State Note: CPU Trace Signals include BRK_IN , BRK_OUT , OCDS2_STATUS[4:0] , OCDS2_INDIR_PC[7:0] and OCDS_BRKPT[2:0].

Data Sheet 93 V1.1, 2008-12

4.3.8 EBU Timings

4.3.8.1 SDCLKO Output Clock Timing

(Operating Conditions apply; CL = 50 pF)

4.3.8.2 BFCLKO Output Clock Timing

(Operating Conditions apply; CL =5 0 p F ) Parameter Symbol Limits 1) 1) The parameters are applicable for PC100 SDRAM access and the maximum SDCLKO is up to 100 MHz. Limits2) 2) The parameters are applicable for PC133 SDRAM access and the maximum SDCLKO is up to 120 MHz. Unit min max min max SDCLKO period t1 CC 10 – 8.3 – ns SDCLKO high time t2 CC 3 − 2.5 − ns SDCLKO low time t3 CC 3 − 2.5 − ns SDCLKO rise time t4 CC − 2.5 − 2.5 ns SDCLKO fall time t5 CC − 2.5 − 2.5 ns Parameter Symbol Limit 1) 1) The CPU runs at 150 MHz and the Burst Flash runs at divided by 3 clock. Limit 2) 2) The CPU runs at 120 MHz and the Burst Flash runs at divided by 2 clock. Unit min max min max Clock period t1 CC 20 – 16.7 – ns BFCLKO high time t2 CC 6.6 – 7.5 – ns BFCLKO low time t3 CC 6.6 – 7.5 – ns BFCLKO rise time t4 C C –3 . 5 –3 . 5 n s BFCLKO fall time t5 C C –2 . 5 –2 . 5 n s

Data Sheet 94 V1.1, 2008-12 Figure 4-10 EBU Clock Output Timing

4.3.8.3 Timing for SDRAM Access Signals

(Operating Conditions apply; CL =5 0 p F1)) 1) If application conditions other than 50 pf capacitive load are used, then the proper correlation factor should be used for your specific application condition. For design team, the load should be set according to the system requirement. 2) The parameters are applicable for PC100 SDRAM access and the maximum SDCLKO is up to 100 MHz. 3) The parameters are applicable for PC133 SDRAM access and the maximum SDCLKO is up to 120 MHz. Parameter Symbol Limits 2) Limits3) Unit min max min max SDCLKO period t1 CC 10 – 8.3 – ns CKE output valid time from SDCLKO t1 CC − 8.0 − 6.8 ns CKE output hold time from SDCLKO t2 CC 0 − 0.8 − ns Address output valid time from SDCLKO t3 CC − 8.0 − 6.8 ns Address output hold time from SDCLKO t4 CC 1.0 − 0.8 − ns CSx, RAS, CAS, RD/WR, BC(3:0) output valid time from SDCLKO t5 CC − 8.0 − 6.8 ns CSx, RAS, CAS, RD/WR, BC(3:0) output hold time from SDCLKO t6 CC 1.0 − 0.8 − ns AD(31:0) output valid time from SDCLKO t7 CC − 8.0 − 6.8 ns AD(31:0) output hold time from SDCLKO t8 CC 1.0 − 0.8 − ns AD(31:0) input setup time to SDCLKO t9 SR 4.0 − 2.9 − ns AD(31:0) input hold time from SDCLKO t10 SR 3.0 − 3.0 − ns BFCLKO / SDCLKO

Data Sheet 95 V1.1, 2008-12 Figure 4-11 SDRAM Access Timing SDCLKO CKE Address ROW CSx RAS CAS RD/WR BC[3:0] AD[31:0] Column t10 D(0) D(n) SDCLKO CKE Address ROW CSx RAS CAS RD/WR BC[3:0] AD[31:0] Column D(0) D(n) Read Access Write Access t5 t6 SDRAM_Timing t5 t6

Data Sheet 96 V1.1, 2008-12

4.3.8.4 Timing for Burst Flash Access Signals

(Operating Conditions apply; CL =5 0 p F ) Parameter Symbol Limits Unit min max Address output valid time from BFCLKO t1 CC − 11.0 ns Address output hold time from BFCLKO t2 CC 10.0 − ns CSx output valid time from BFCLKO t3 CC − 9.0 ns RD output valid time from BFCLKO t4 CC − 10.0 ns ADV output valid time from BFCLKO t5 CC − 10.0 ns ADV output hold time from BFCLKO t6 CC 3.0 − ns BAA output valid time from BFCLKO t7 CC − 10.0 ns BAA output hold time from BFCLKO t8 CC 3.0 − ns AD(31:0) input setup time to BFCLKO t9 SR 5.0 − ns AD(31:0) input hold time from BFCLKO t10 SR 3.0 − ns WAIT input setup time to BFCLKO t11 SR 5.0 − ns WAIT input hold time from BFCLKO t12 SR 3.0 − ns

Data Sheet 97 V1.1, 2008-12 Figure 4-12 Burst Fl ash Access Timing Note: Output delays are always referenced to BFCLKO. The refe rence clock for input characteristics depends on bit BFCON.FDBKEN. BFCON.FDBKEN = 0: BFCLKO is the input reference clock. BFCON.FDBKEN = 1: BFCLKI is the input reference cl ock (EBULMB clock feedback enabled). BFCLKO Address CSx ADV RD BAA D[31:0] t9 t11 t12 t10 BF_Timing Address D(0) D(n-1) WAIT Address Phase(s) Command Delay Phase(s) Command Phase(s) Burst Phase(s) Burst Phase(s) Recovery Phase New Addr. Phase(s)

Data Sheet 98 V1.1, 2008-12

4.3.8.5 Timing for Demultiplexed Access Signals

(Operating Conditions apply; CL =5 0 p F ) 1) 1) The purpose for characterization of Asynchronous access is to provide the performance of all of the signals to user. User can decide whether an extra cycle is needed or not based on above parameters to generate signals with correct timing sequence. It is user’s responsibility to program the correct phase length according to the memory/peripheral device specification and EBU specification. Parameter Symbol Limits Unit min max CSx, RD/WR, RD, MR/W, BC(3:0) output valid time from output clock t1 CC − 9n s CSx, RD/WR, RD, MR/W, BC(3:0) output hold time from output clock t2 CC 0.0 − ns Address output valid time from output clock t3 CC − 9n s Address output hold time from output clock t4 CC 0.0 − ns WAIT input setup time to output clock t7 SR 12 − ns WAIT input hold time from output clock t8 SR 3 − ns AD(31:0) output valid time from output clock t9 CC − 9n s AD(31:0) output hold time from output clock t10 CC 0.0 − ns AD(31:0) input setup time to output clock t11 SR 1.3 − ns AD(31:0) input hold time from output clock t12 SR 3 − ns RMW output valid time from output clock t13 CC − 8n s RMW output hold time from output clock t14 CC 1.3 − ns AD(31:0) output hold time from RD/WR t16 CC 0 − ns

Data Sheet 99 V1.1, 2008-12 Figure 4-13 Demultiplexed Asy nchronous Device Access Timing SDCLKO Address Address CSx RD/WR MR/W CMDELAY BC[3:0] AD[31:0] t10 DataOut Read Access Write Access t5 t6 Demux_Timing WAIT t7 t8 SDCLKO/ SDCLKI Address Address CSx RD MR/W CMDELAY BC[3:0] AD[31:0] t11 t12 DataIn t5 t6 WAIT t7 t8 RMW t13 t14 Address Phase(s) Command Delay Phase(s) (int.) Command Delay Phase(s) (ext.) Command Phase(s) Data Hold Phase(s) Recovery Phase Address Phase(s) Command Delay Phase(s) (int.) Command Delay Phase(s) (ext.) Command Phase(s) Recovery Phase t16 t15 t15

Data Sheet 100 V1.1, 2008-12

4.3.8.6 Timing for Multiplexed Access Signals

(Operating Conditions apply; CL =5 0 p F )1) 1) The purpose for characterization of Asynchronous access is to provide the performance of all of the signals to user. User can decide whether an extra cycle is needed or not based on above parameters to generate signals with correct timing sequence. It is user’s responsibility to program the correct phase length according to the memory/peripheral device specification and EBU Specification. Parameter Symbol Limits Unit min max ALE, CSx, RD/WR, RD, MR/W, BC(3:0) output valid time from output clock t1 CC − 9n s ALE, CSx, RD/WR, RD, MR/W, BC(3:0) output hold time from output clock t2 CC 0.0 − ns AD(31:0) output valid time from output clock t3 CC − 9n s AD(31:0) output hold time from output clock t4 CC 0.0 − ns AD(31:0) input setup time to output clock t5 SR 1.4 − ns AD(31:0) input hold time from output clock t6 SR 3 − ns WAIT input setup time to output clock t9 SR 12 − ns WAIT input hold time from output clock t10 SR 3 − ns RMW output valid time from output clock t11 CC − 8n s RMW output hold time from output clock t12 CC 1.3 − ns ALE width t13 CC 8.5 − ns AD(31:0) output hold time from RD/WR t14 CC 0 − ns

Data Sheet 101 V1.1, 2008-12 Figure 4-14 Write Access in Multiplexed Access SDCLKO AD[31:0] Address CSx RD/WR MR/W CMDELAY BC[3:0] Read Access Write Access t7 t8 Mux_Timing WAIT t9 t10 SDCLKO/ SDCLKI AD[31:0] Address CSx RD MR/W CMDELAY BC[3:0] t7 t8 WAIT t9 t10 RMW t11 t12 t4 t3 Data Data Address Phase(s) Address Hold Phase(s) Command Delay Phase(s) (int.) Command Delay Phase(s) (ext.) Command Phase(s) Data Hold Phase(s) Recovery Phase(s) t13 t14 Address Phase(s) Address Hold Phase(s) Command Delay Phase(s) (int.) Command Delay Phase(s) (ext.) Command Phase(s) Recovery Phase(s) t13

Data Sheet 102 V1.1, 2008-12

4.3.9 Peripheral Timings

4.3.9.1 Timing for Ethernet Signals

(Operating Conditions apply; CL =5 0 p F ) Parameter Symbol Limits Unit min max ETXCLK period (10 Mbit/sec Ethernet) t1 SR 400.0 − ns ETXCLK high time (10 Mbit/sec Ethernet) t2 SR 140 260 ns ETXCLK low time (10 Mbit/sec Ethernet) t3 SR 140 260 ns ETXCLK period (100 Mbit/sec Ethernet) t1 SR 40.0 − ns ETXCLK high time (100 Mbit/sec Ethernet) t2 SR 14 26 ns ETXCLK low time (100 Mbit/sec Ethernet) t3 SR 14 26 ns ERXCLK period (10 Mbit/sec Ethernet) t1 SR 400.0 − ns ERXCLK high time (10 Mbit/sec Ethernet) t2 SR 140 260 ns ERXCLK low time (10 Mbit/sec Ethernet) t3 SR 140 260 ns ERXCLK period (100 Mbit/sec Ethernet) t1 SR 40.0 − ns ERXCLK high time (100 Mbit/sec Ethernet) t2 SR 14 26 ns ERXCLK low time (100 Mbit/sec Ethernet) t3 SR 14 26 ns ERXD(3:0) input setup to ERXCLK t4 SR 10.0 − ns ERXD(3:0) input hold from ERXCLK t5 SR − 10.0 ns ERXDV input setup to ERXCLK t4 SR 10.0 − ns ERXDV input hold from ERXCLK t5 SR − 10.0 ns ERXER input setup to ERXCLK t4 SR 10.0 − ns ERXER input hold from ERXCLK t5 SR − 10.0 ns ETXD(3:0) output valid from ETXCLK t6 CC − 25.0 ns ETXEN output valid from ETXCLK t6 CC − 25.0 ns ETXER output valid from ETXCLK t6 CC − 25.0 ns EMDC clock period t7 CC 400.0 − ns EMDC high time t8 CC 160 − ns EMDC low time t9 CC 160 − ns EMDIO input setup to EMDC (sourced by STA) t10 SR 10.0 − ns

Data Sheet 103 V1.1, 2008-12 Note: Any other parameters wh ich are not stated here, pl ease refer to ANSI/IEEE Std 802.3, Section 22.3. Figure 4-15 Ethernet Timing EMDIO input hold from EMDC (sourced by STA) t11 SR − 10.0 ns EMDIO output valid from EMDC (sourced by PHY) t12 CC − 300.0 ns Parameter Symbol Limits Unit min max ETXCLK ERXCLK ERXD(3:0) ERXDV ERXER t4 t5 valid data ETXD(3:0) ETXEN ETXER valid data EMDC EMDIO (sourced by STA) t10 t11 valid data t12 EMDIO (sourced by PHY) valid data t2 t3 t8 t9

Data Sheet 104 V1.1, 2008-12

4.3.9.2 SSC Master Mode Timing

(Operating Conditions apply; CL =5 0 p F ) Figure 4-16 SSC Master Mode Timing Parameter Symbol Limit Values Unit min. max. SCLK clock period t0 CC 2*T SSC 1) 1) TSSCmin = TSYS = 1/fSYS. When fSYS = 120MHz, t0 = 16.7ns –n s MTSR/SLSOx delay from SCLK t1 CC 0 8 ns MRST setup to SCLK t2 SR 10 – ns MRST hold from SCLK t3 SR 5 – ns SSC_Tmg1 SCLK1)2) MTSR1) t1 t1 MRST1) Data valid SLSOx2) 1) This timing is based on the following setup: CON.PH = CON.PO = 0. 2) The transition at SLSOx is based on the following setup: SSOTC.TRAIL = 0 and the first SCLK high pulse is in the first one of a transmission.

Data Sheet 105 V1.1, 2008-12

4.3.9.3 MLI Interface Timing

(Operating Conditions apply; CL =5 0 p F ) Figure 4-17 MLI Interface Timing Note: The generation of RREADYx is in th e input clock domain of the receiver. The reception of TREADYx is asynchronous to TCLKx. Parameter Symbol Limit Values Unit min. max. TCLK/RCLK clock period t0 CC/SR 2*TMLI 1) 1) TMLImin = TSYS = 1/fSYS. When fSYS = 120MHz, t0 = 16.7ns –n s MLI outputs delay from TCLK t5 CC 0 8 ns MLI inputs setup to RCLK t6 SR 4 – ns MLI inputs hold to RCLK t7 SR 4 – ns RREADY output delay from TCLK t8 CC 0 8 ns MLI_Tmg1 TDATAx TVALIDx t5 t5 TCLKx

0.1 VDDP

0.9 VDDP

Data Sheet 106 V1.1, 2008-12

4.3.9.4 Timing for USB Transceiver Signals

(Operating Conditions apply; CL =5 0 p F ) Figure 4-18 AC Testing: I nput, Output Waveforms Parameter Symbol Limits Unit min max Full speed mode rise time tFR CC 4 20 ns Full speed mode fall time tFF CC 4 20 ns tR 10% 90% 10% 90% tF rise_fall_USB.emf

Data Sheet 107 V1.1, 2008-12

4.4 Package Outline

Figure 4-19 P-LBGA-208-2 Package Plastic Package, P-LBGA-208-2 (SMD) (Low Profile Ball Grid Array Package) You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mmSMD = Surface Mounted Device

www.infineon.com Published by Infineon Technologies AG