TC1130

TC1130 INFINEON | Alldatasheet

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Never stop thinking. Microcontrollers Data Sheet, V0.3, Sep. 2003 TC1130 32-Bit Single-Chip Microcontroller Pr el im inar y

Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2003. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Data Sheet, V0.3, Sep. 2003 Never stop thinking. TC1130 32-Bit Single-Chip Microcontroller

Revision History: 2003-09 V0.3 Previous Version: Page Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com

Data Sheet 1 V0.3, 2003-09 TC113032-Bit Single-Chip Microcontroller TriCore Family Advance Information

• High Performance 32-bit TriCore V1.3 CPU with 4-Stage Pipeline  Floating Point Unit (FPU)  Dual Issue super-scalar implementation – MAC Instruction maximum triple issue  Circular Buffer and bit-reverse addressing modes for DSP algorithms  Flexible multi-master interrupt system  Very fast interrupt response time  Hardware controlled context switch for task switch and interrupts  Memory Management Unit (MMU)  On-chip Memory – 32 KByte Data Memory (SPRAM) – 32 KByte Code Memory (SPRAM) – 16 KByte Instruction Cache (ICACHE). – 64KByte SRAM Data Memory Unit (DMU) – 16 KByte Boot ROM  On-chip Bus Systems – 64-Bit High Performance Local Memory Bus (LMB) for fast access between caches and on-local memories and FPI Interface – On-chip Flexible Peripheral Interconnect Buses (FPI) for interconnections of functional units  DMA Controller with 8 channels for data transfer operations between peripheral units and memory locations – Two high speed Micro Link Interfaces (MLI0/1) for controller communication and emulation  Flexible External Bus Interface Unit (EBU) to access external data memories  One Multifunctional General Purpose Timer Units (GPTU) with three 32-bit timer/ counters  Two Capture and Compare units (CCU60/1) for PWM signal generation, each with – 3-channel, 16 bit Capture and Compare unit – 1-channel, 16 bit Compare unit  Three Asynchronous/Synchronous Serial Channels (ASC0/1/2) with baudrate generator, parity, framing and overrun error detection, support FIFO and IrDA data transmission  Two High Speed Synchronous Serial Channels (SSC0/1) with programmable data length, FIFO support and shift direction  One MultiCAN Module with four CAN nodes and 64 message buffers for high efficiency data handling  Fast Ethernet Controller with 10/100 Mbps MII-Based physical devices support

Data Sheet 2 V0.3, 2003-09  USB module with compliance to USB Specification Revision 1.1, with support for 1.5MBaud to 12MBaud devices  Inter-IC (IIC) module with two physical IIC buses  Digital I/O ports with 3.3V IO capabilities  Level 2 On-chip Debug Support  Power Management System  Clock Generation Unit with PLL  Maximum CPU and Bus clock frequency at 150MHz without MMU and 120MHz with MMU  Ambient temperature under bias: -40° to +85°C  P-LBGA-208 package

Data Sheet 3 V0.3, 2003-09 Block Diagram Figure 1 TC1130 Block Diagram Ce d a r_ BLK Boot- ROM

16 Kby te s

FI F O, IrDA ASC1 FIF O , Ir DA ASC2 FIF O, IrDA SSC0 SSC1II C

2 Chan nel s

(PWR) Powe r Man agement, Watchd og T i mer, Reset SBCU FPI BUS Cerber us JTAG PLL Tr iCor e 1M CPU FP U OCDS PM I (Pro gr a m M emor y In ter face )

32 KB Scr atch Pad RAM

16 KB Inst ruction Cache

(Dat a Memor y In ter face) LMB (Lo cal Memor y Bus ) 64 Bit Exter nal I nterr upts 128 64 VDD 1.5 - 3.3 V VSS TC113 0 Bl ock Diag ra m STMUSB Eth ern etMultiCAN 4 no des DMA chan nel s GPTU

3 T imers

AD[31: 0] EBU_ Contro l

24 A[23:0]

FPI Bus ( Flex ible Per iph eral Inte rfa ce), 32 Bit DMA Bus, 32 Bit SMIF

Data Sheet 4 V0.3, 2003-09 Logic Symbol Figure 2 TC1130 Logic Symbol MC B04945mod Port 0 16-Bit WAI T RD/WR RD HWCFG[0:2] NMI HDRST PORST VSS VDDOSC3 RAS ALE EBU Cont rol Alternate Functions Digital Circuitry Power Supply General Control CAS CS [0:3] 4 CSCOMB SDCLKI CKE MR/ W BFCLKI BAA ADV SDCLKO MI I _ TxCL K MI I _ RxCL K MI I _ MDI O XTAL1 XTAL2 Ethernet Clock VSSOSC3 Oscillator 6VDD VDDP TDI TCK TRST A[0:23] B C[0:3] A D[0:31] Port 1 16-Bit Port 2 16-Bit Port 3 16-Bit Port 4 8-Bit GPTU, Mult iCAN, SSC0/ 1, A S C1/2, CCU60, M LI0, E B U, S CU, E xternal Interrupts S S C0/1, M ultiCA N, E thernet, EBU, SCU, OCDS A S C0/1/2, S S C0/1, IIC, CCU60, EBU, SCU S S C0/1, CCU61, M LI1, OCDS TDO OCDS / JTAG Control US B , M LI0, S CU BFCLKO TC1130 TMS BRKI N TRCLK USB VDDOSC VSSOSC

Data Sheet 5 V0.3, 2003-09 Pin Configuration Figure 3 TC1130 Pinning : P-BGA-208 Package (top view) MCP04950mod ABCDEF G HJ P2. 7 KL M N VDD OSC3 PR VSS T Reser vedP3. 1016 15 P0. 9P0. 1 14 P1. 10 V SS Reser ved Reser ved ABCD EFGHJ KL M N P R T V SSV DD VDD VDDV SSV SSV DD V DD VDDV SSV SS V DD V SS V SS VDD CFG 1 HW CFG 0 P2. 5 P2. 3 P0. 10 D+ P1. 6 P1. 3 P1. 1 P1. 2 BAA ADV P1. 4 P1. 0 A17 A18 A19 A20 A16 WAI T CS2 CS 0 CS 1AD0CS 3A15 BC 3 AD 1BC 2 AD 16 BC 1 AD 2 AD 3 RA S BC 0 AD 17 AD 4 CA S AD 18 AD 19 AD 20 V DDP AD 5 AD 21 AD 7 AD 25 AD 6 AD 22 AD 8 AD 9 Reser ved AD 23 AD 24 BFC LKI AD 28 AD 29 A14 CKE V DDP A23 A22V DDP V SS VSS A21V SS TCKP0. 5P2. 0P2. 6 P0. 0 TRSTP0. 4 P4. 3 HW CF G2P4. 6P4. 4 TDOP0. 5P0. 2P0. 7 P0. 11 TMSP4. 1P0. 12 P0. 14 T RCLKP4. 0P0. 13 P4. 2 NMIP4. 5P0. 15 HDRS T P4. 7 POR STBR KI N AD 11 AD 12 AD 15 AD 30 A10 A11 A12 A13 CS COMB MR/W ALE RD/W R AD 26 AD 27 AD 31 AD14 A5 A6 A7 A8 A9 RD MII_ RX CLK MII_ TXC LK A3 MII_ MDIOA4A2A1A0SDCL KISDCL KOAD 13AD 10BFC LKO 208-Pin P-LBGA Package Pin Configuration (top view) for TC1130 VSS

Data Sheet 6 V0.3, 2003-09 Table 1 Pin Definitions and Functions Symbol Pin In Out PU/ PD 1) Functions P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9 P0.10 P0.11 N11 P15 P19 M15 R11 R12 R10 N10 R13 R15 R14 I/O I/O I/O I/O O I/O I/O I/O O I/O I O I/O I I O I/O I/O I O I/O O I I O O I I I I O O I O PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC Port 0 Port 0 is a 16-bit bidirectional general purpose I/O port which can be alternatively used for GPTU, MultiCAN, ASC1/2, SSC0/1, MLI0, EBU and SCU. GPTU_0 GPTU input/output line 0 RXD1B ASC1 receiver input/output B GPTU_1 GPTU input/output line 1 TXD1B ASC1 transmitter output B GPTU_2 GPTU input/output line 2 RXD2B ASC2 receiver input/output B GPTU_3 GPTU input/output line 3 TXD2B ASC2 transmitter output B GPTU_4 GPTU input/output line 4 SLSI1 SSC1 Slave Select input BREQ EBU Bus Request Output GPTU_5 GPTU input/output line 5 HOLD EBU Hold Request Input CC60_T12HR CCU0 Timer 12 hardware run BRKOUT#_B OCDS Break Out B GPTU_6 GPTU input/output line 6 HLDA EBU Hold Acknow ledge Input/Output CC60_T13HR CCU0 Timer 13 hardware run SLSO0_0 SSC0 Slave Select output 0 GPTU_7 GPTU input/output line 7 SLSO1_0 SSC1 Slave Select output 0 RXDCAN0_A CAN node 0 receiver input A REQ0 External Trigger Input 0 TCLK0A MLI0 transmit ch annel clock output A TXDCAN0_A CAN node 0 transmitter output A TREADY0A MLI0 transmit channel ready input A REQ1 External Trigger Input 1 RXDCAN1_A CAN node 1 receiver input A REQ2 External Trigger Input 2 TVALID0A MLI0 transmit channel valid output A TXDCAN1_A CAN node 1 transmitter output A REQ3 External Trigger Input 3 TDATA0A MLI0 transmit ch annel data output A

Data Sheet 7 V0.3, 2003-09 P0.12 P0.13 P0.14 P0.15 I I I O I O I I I O I I PUC PUC PUC PUC RXDCAN2 CAN node 2 receiver input RCLK0A MLI0 receive channel clock input A REQ4 External Trigger Input 4 TXDCAN2 CAN node 2 transmitter output REQ5 External Trigger Input 5 RREADY0A MLI0 receive channel ready output A RXDCAN3 CAN node 3 receiver input REQ6 External Trigger Input 6 RVALID0A MLI0 receive channel valid input A TXDCAN3 CAN node 3 transmitter output REQ7 External Trigger Input 7 RDATA0A MLI0 receive channel data input A Table 1 Pin Definitions and Functions(cont’d) Symbol Pin In Out PU/ PD Functions

Data Sheet 8 V0.3, 2003-09 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 D11 C12 D12 B12 C11 C13 A12 I/O O I I O O I O O O I I O O O I O O I O O I O O I O PUC PUC PUC PUC PUC PUC PUC Port 1 Port 1 serves as 16-bit bidirectional general purpose I/ O port which can be used for input/output for Ethernet controller, MultiCAN, CAN, OCDS L2, SSC0/1, EBU and SCU MII_TXD0 Ethernet cont roller transmit data output line 0 RXDCAN0_B CAN node 0 receiver input B SWCFG0 Software configuration 0 OCDSA_0 OCDS L2 Debug Line A0 MII_TXD1 Ethernet cont roller transmit data output line 1 SWCFG1 Software configuration 1 TXDCAN0_B CAN node 0 transmitter output B OCDSA_1 OCDS L2 Debug Line A1 MII_TXD2 Ethernet cont roller transmit data output line 2 RXDCAN1_B CAN node 1 receiver input B SWCFG2 Software configuration 2 OCDSA_2 OCDS L2 Debug Line A2 MII_TXD3 Ethernet cont roller transmit data output line 3 TXDCAN1_B CAN node 1 transmitter output B SWCFG3 Software configuration 3 OCDSA_3 OCDS L2 Debug Line A3 MII_TXER Ethernet controller transmit error output line SWCFG4 Software configuration 4 OCDSA_4 OCDS L2 Debug Line A4 MII_TXEN Ethernet controller transmit enable output line SWCFG5 Software configuration 5 OCDSA_5 OCDS L2 Debug Line A5 MII_MDC Ethernet contro ller management data clock output line SWCFG6 Software configuration 6 OCDSA_6 OCDS L2 Debug Line A6 Table 1 Pin Definitions and Functions(cont’d) Symbol Pin In Out PU/ PD Functions

Data Sheet 9 V0.3, 2003-09 P1.7 P1.8 P1.9 P1.10 P1.11 P1.12 P1.13 P1.14 P1.15 B13 A13 A14 B14 C14 F13 E14 D14 F14 I I O I I O I I O I I O I I O O I I O O O I O O I O I O I O I O PUC PUC PUC PUC PUC PUC PUC PUC PUC MII_RXDV Ethernet Contro ller receive data valid input line SWCFG7 Software configuration 7 OCDSA_7 OCDS L2 Debug Line A7 MII_CRS Ethernet Controll er carrier input line SWCFG8 Software configuration 8 OCDSA_8 OCDS L2 Debug Line A8 MII_COL Ethernet Controller collision input line SWCFG9 Software configuration 9 OCDSA_9 OCDS L2 Debug Line A9 MII_RXD0 Ethernet Contro ller receive data input line 0 SWCFG10 Software configuration 10 OCDSA_10 OCDS L2 Debug Line A10 MII_RXD1 Ethernet Contro ller receive data input line 1 SWCFG11 Software configuration 11 OCDSA_11 OCDS L2 Debug Line A1 SLSO0_1 SSC0 Slave Select output 1 MII_RXD2 Ethernet Contro ller receive data input line 2 SWCFG12 Software configuration 12 OCDSA_12 OCDS L2 Debug Line A12 SLSO1_1 SSC1 Slave Select output 1 MII_RXD3 Ethernet Contro ller receive data input line 3 SWCFG13 Software configuration 13 OCDSA_13 OCDS L2 Debug Line A13 SLSO0_2 SSC0 Slave Select output 2 MII_RXER Ethernet Controller receive error input line SLSO1_2 SSC1 Slave Select output 2 SWCFG14 Software configuration 14 OCDSA_14 OCDS L2 Debug Line A14 SLSI0 SSC0 Slave Select Input RMW EBU Read Modify Write SWCFG15 Software configuration 15 OCDSA_15 OCDS L2 Debug Line A15 Table 1 Pin Definitions and Functions(cont’d) Symbol Pin In Out PU/ PD Functions

Data Sheet 10 V0.3, 2003-09 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 P2.12 P12 P11 P13 P14 N15 N14 N12 K16 J16 H16 L13 G16 K15 I/O I/O O O I I/O I/O I/O O I/O I/O I/O O I/O I/O I/O O O I/O I/O O O I/O I O PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC Port 2 Port 2 is a 16-bit bidirectional general purpose I/O port which can be alternatively used for ASC0/1/2, SSC0/1, CCU0, IIC, EBU and SCU. RXD0 ASC0 receiver input/output line CSEMU EBU Chip Select Output for Emulator Region TXD0 ASC0 transmitter output line TESTMODE Test Mode Select Input MRST0 SSC0 master receive / slave transmit input/output MTSR0 SSC0 master tran smit / slave receive input/output SCLK0 SSC0 clock input/output line COUT60_3 CCU0 compar e channel 3 output MRST1A SSC1 master receive / slave transmit input/output A CC60_0 CCU0 inpu t/output of capture/compare channel 0 MTSR1A SSC1 master tran smit / slave receive input/output A COUT60_0 CCU0 output of capture/compare channel 0 SCLK1A SSC1 clock input/output line A CC60_1 CCU0 input/output of capture/ compare channel 1 RXD1A ASC1 receiver input/output line A COUT60_1 CCU0 output of capture/compare channel 1 TXD1A ASC1 transmitter output line A CC60_2 CCU0 input/output of capture/ compare channel 2 RXD2A ASC2 receiver input/output line A COUT60_2 CCU0 output of capture/compare channel 2 TXD2A ASC2 transmitter output line A SDA0 IIC Serial Data line 0 CTRAP0 CCU0 trap input SLSO0_3 SSC0 Slave Select output 3 Table 1 Pin Definitions and Functions(cont’d) Symbol Pin In Out PU/ PD Functions

Data Sheet 11 V0.3, 2003-09 P2.13 P2.14 P2.15 K14 F16 E16 I/O I O I I/O O I I/O O SCL0 IIC clock line 0 CCPOS0_0 CCU0 Hall input signal 0 SLSO1_3 SSC1 Slave Select output 3 CCPOS0_1 CCU0 Hall input signal 1 SDA1 IIC Serial Data line 1 SLSO0_4 SSC0 Slave Select output 4 CCPOS0_2 CCU0 Hall input signal 2 SCL1 IIC clock line 1 SLSO1_4 SSC1 Slave Select output 4 Table 1 Pin Definitions and Functions(cont’d) Symbol Pin In Out PU/ PD Functions

Data Sheet 12 V0.3, 2003-09 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 A15 B15 D15 E15 G14 G15 F15 H14 C15 H15 B16 I/O O O O I/O O O O I/O O O O I/O O O O I O O I O O O I I O O I O O PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC Port 3 Port 3 is a 16-bit bidirectional general purpose I/O port which can be alternatively used for MLI1, CCU1, SSC0/1 and OCDS Level 2 debug lines. OCDSB_0 OCDS L2 Debug Line B0 COUT61_3 CCU1 compare channel 3 output OCDSB_1 OCDS L2 Debug Line B1 CC61_0 CCU1 input/output of capture/ compare channel 0 OCDSB_2 OCDS L2 Debug Line B2 COUT61_0 CCU1 output of capture/compare channel 0 OCDSB_3 OCDS L2 Debug Line B3 CC61_1 CCU1 input/output of capture/ compare channel 1 OCDSB_4 OCDS L2 Debug Line B4 COUT61_1 CCU1 output of capture/compare channel 1 OCDSB_5 OCDS L2 Debug Line B5 CC61_2 CCU1 input/output of capture/ compare channel 2 OCDSB_6 OCDS L2 Debug Line B6 COUT61_2 CCU1 output of capture/compare channel 2 OCDSB_7 OCDS L2 Debug Line B7 CTRAP1 CCU1 trap input SLSO0_5 SSC0 Slave Select output 5 OCDSB_8 OCDS L2 Debug Line B8 CCPOS1_0 CCU1 Hall input signal 0 TCLK1 MLI1 transmit channel clock output SLSO1_5 SSC1 Slave Select output 5 OCDSB_9 OCDS L2 Debug Line B9 CCPOS1_1 CCU1 Hall input signal 1 TREADY1 MLI1 transmit channel ready input SLSO0_6 SSC0 Slave Select output 6 OCDSB_10 OCDS L2 Debug Line B10 CCPOS1_2 CCU1 Hall input signal 2 TVALID1 MLI1 transmit channel valid output SLSO1_6 SSC1 Slave Select output 6 Table 1 Pin Definitions and Functions(cont’d) Symbol Pin In Out PU/ PD Functions

Data Sheet 13 V0.3, 2003-09 P3.11 P3.12 P3.13 P3.14 P3.15 C16 D16 K13 J14 J15 O O O I O I O I O O I/O O I I/O O I I/O PUC PUC PUC PUC PUC OCDSB_11 OCDS L2 Debug Line B11 TDATA1 MLI1 transmit channel data output SLSO0_7 SSC0 Slave Select output 7 CC61_T12HR CCU1 Timer 12 hardware run OCDSB_12 OCDS L2 Debug Line B12 RCLK1 MLI1 receive channel clock input SLSO1_7 SSC1 Slave Select output 7 CC61_T13HR CCU1 Timer 13 hardware run OCDSB_13 OCDS L2 Debug Line B13 RREADY1 MLI1 receive channel ready output MRST1B SSC1 master receive / slave transmit input/output B OCDSB_14 OCDS L2 Debug Line B14 RVALID1 MLI1 receive channel valid input MTSR1B SSC1 master transmit / slave receive input/output B OCDSB_15 OCDS L2 Debug Line B15 RDATA1 MLI1 receive channel data input SCLK1B SSC1 clock input/output line B Table 1 Pin Definitions and Functions(cont’d) Symbol Pin In Out PU/ PD Functions

Data Sheet 14 V0.3, 2003-09 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 I/O I O I I I O I O O I O O O I I O PUC PUC PUC PUC PUC PUC PUC PUC Port 4 Port 4 is a 8-bit bidirectional general purpose I/O port which can be alternatively used for USB, MLI0 and SCU. USBCLK 48MHz input clock TCLK0B MLI0 transmit ch annel clock output B RCVI USB data input TREADY0B MLI0 transmit channel ready input B VPI USB D+ CMOS level mirror of differential signal TVALID0B MLI0 transmit channel valid output B VMI USB D- CMOS level mirror of differential signal TDATA0B MLI0 transmit ch annel data output B VPO USB D+ CMOS level output RCLK0B MLI0 receive channel clock input B VMO USB D- CMOS level output RREADY0B MLI0 receive ch annel ready output B USBOE Direction select fo r transmit or receive RVALID0B MLI0 receive channel valid input B RDATA0B MLI0 receive ch annel data input B BRKOUT#_A OCDS Break Out A HDRST N5 I/O PUA Hardware Reset Input/Reset Indication Output Assertion of this bidirectional open-drain pin causes a synchronous reset of the chip through external circuitry. This pin must be driven for a minimum duration. The internal reset circuitry drives this pin in response to a power-on, hardware, watchdog and power-down wake-up reset for a specific period of time. For a software reset, activation of this pin is programmable. PORST R5 I PUC Power-on Reset Input A low level on PORST causes an asynchronous reset of the entire chip. PORST is a fully asynchronous level sensitive signal. NMI T7 I PUC Non-Maskable Interrupt Input A high-to-low transition on this pin causes a NMI-Trap request to the CPU. Table 1 Pin Definitions and Functions(cont’d) Symbol Pin In Out PU/ PD 1) Functions

Data Sheet 15 V0.3, 2003-09 TRST T11 I PDC JTAG Module Reset/Enable Input A low level at this pin resets and disables the JTAG module. A high level enables the JTAG module. TCK T12 I PUC JTAG Module Clock Input TDI T13 I PUC JTAG Module Serial Data Input TDO T10 O  JTAG Module Serial Data Output TMS T9 I PUC JTAG Module State Machine Control Input TRCLK T8 O  Trace Clock for OCDS_L2 Lines HWCFG0 HWCFG1 HWCFG2 M14 L14 I I I PUC PUC PDC Hardware Configuration Inputs The Configuration Inputs define the boot options of the TC1130 after a hardware invoked reset operation. BRKIN T5 I PUC OCDS Break Input A low level on this pin causes a break in the chip’s execution when the OCDS is enabled. In addition, the level of this pin during power-on reset determines the boot configuration. MII_ TXCLK T2 I PDC Ethernet Controller Transmit Clock MII_TXD[3:0] and MII_TXEN are driven off the rising edge of the MII_TXCLK by the core and sampled by the PHY on the rising edge of the MII_TXCLK. MII_ RXCLK R2 I PDC Ethernet Controller Receive Clock MII_RXCLK is a continuous clock. Its frequency is 25 MHz for 100 Mbps operation, and 2.5 MHz for 10Mbps. MII_RXD[3:0], MII_RXDV and MII_EXER are driven by the PHY off the falling edge of MII_RXCLK and sampled on the rising edge of MII_RXCLK. MII_ MDIO R1 I/O PDA Ethernet Controller Management Data Input / Output When a read command is being executed, data which is clocked out of the PHY will be presented on the input line. When the Core is clocking control or data onto the MII_MDIO line, the signal will carry the information. D+ T14 I/O  USB D+ data line D- T15 I/O  USB D- data line Table 1 Pin Definitions and Functions(cont’d) Symbol Pin In Out PU/ PD Functions

Data Sheet 16 V0.3, 2003-09 CS0 CS1 CS2 CS3 O O O O PUC PUC PUC PUC EBU Chip Select Output Line 0 EBU Chip Select Output Line 1 EBU Chip Select Output Line 2 EBU Chip Select Output Line 3 Each corresponds to a programmable region. Only one can be active at one time. CSCOMB N3 O PUC EBU Chip Select Output for combination function (Overlay Memory and Global) SDCLKI J1 I  SDRAM clock input (clock feedback). SDCLKO H1 O  SDRAM clock output.Accesses to SDRAM devices are synchronized to this clock RAS D6 O PUC EBU SDRAM Row Address Strobe Output CAS D5 O PUC EBU SDRAM Column Address Strobe Output CKE L4 O PUC EBU SDRAM Clock Enable Output BFCLKI D1 I  Burst FLASH clock input (clock feedback). BFCLKO E1 O  Burst FLASH clock output. Accesses to Burst FLASH devices are synchronized to this clock. RD P2 O PUC EBU Read Control Line Output in the master mode Input in the slave mode. RD/WR T3 O PUC EBU Write Control Line Output in the master mode Input in the slave mode. WAIT B9 I PUC EBU Wait Control Line ALE R3 O PDC EBU Address Latch Enable Output MR/W P3 O PUC EBU Motorola-style Read / Write Output BAA A11 O PUC EBU Burst Address Advance Output For advancing address in a burst flash access ADV B11 O PUC EBU Burst Flash Address Valid Output Table 1 Pin Definitions and Functions(cont’d) Symbol Pin In Out PU/ PD 1) Functions

Data Sheet 17 V0.3, 2003-09 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC EBU Address / Data Bus Input / Output Lines EBU Address / Data Bus Line 0 EBU Address / Data Bus Line 1 EBU Address / Data Bus Line 2 EBU Address / Data Bus Line 3 EBU Address / Data Bus Line 4 EBU Address / Data Bus Line 5 EBU Address / Data Bus Line 6 EBU Address / Data Bus Line 7 EBU Address / Data Bus Line 8 EBU Address / Data Bus Line 9 EBU Address / Data Bus Line 10 EBU Address / Data Bus Line 11 EBU Address / Data Bus Line 12 EBU Address / Data Bus Line 13 EBU Address / Data Bus Line 14 EBU Address / Data Bus Line 15 EBU Address / Data Bus Line 16 EBU Address / Data Bus Line 17 EBU Address / Data Bus Line 18 EBU Address / Data Bus Line 19 EBU Address / Data Bus Line 20 EBU Address / Data Bus Line 21 EBU Address / Data Bus Line 22 EBU Address / Data Bus Line 23 EBU Address / Data Bus Line 24 EBU Address / Data Bus Line 25 EBU Address / Data Bus Line 26 EBU Address / Data Bus Line 27 EBU Address / Data Bus Line 28 EBU Address / Data Bus Line 29 EBU Address / Data Bus Line 30 EBU Address / Data Bus Line 31 BC0 BC1 BC2 BC3 O O O O PUC PUC PUC PUC EBU Byte Control Line 0 EBU Byte Control Line 1 EBU Byte Control Line 2 EBU Byte Control Line 3 Table 1 Pin Definitions and Functions(cont’d) Symbol Pin In Out PU/ PD Functions

Data Sheet 18 V0.3, 2003-09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A10 B10 C10 D10 O O O O O O O O O O O O O O O O O O O O O O O O PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC PUC EBU Address Bus Input / Output Lines EBU Address Bus Line 0 EBU Address Bus Line 1 EBU Address Bus Line 2 EBU Address Bus Line 3 EBU Address Bus Line 4 EBU Address Bus Line 5 EBU Address Bus Line 6 EBU Address Bus Line 7 EBU Address Bus Line 8 EBU Address Bus Line 9 EBU Address Bus Line 10 EBU Address Bus Line 11 EBU Address Bus Line 12 EBU Address Bus Line 13 EBU Address Bus Line 14 EBU Address Bus Line 15 EBU Address Bus Line 16 EBU Address Bus Line 17 EBU Address Bus Line 18 EBU Address Bus Line 19 EBU Address Bus Line 20 EBU Address Bus Line 21 EBU Address Bus Line 22 EBU Address Bus Line 23 XTAL1 XTAL2 M16 N16 I O Oscillator/PLL/Clock Generator Input/Output Pins XTAL1 is the input to the main oscillator amplifier and input to the internal clock generator. XTAL2 is the output of the main oscillator amplifier circuit. For clocking the device from an external source, XTAL1 is driven with the clock signal while XTAL2 is left unconnected. For crystal oscillator operation XTAL1 and XTAL2 are connected to the crystal with the appropriate recommended oscillator circuitry. V DDOSC3 P16  Main Oscillator Power Supply (3.3V) V SSOSC3 R16  Main Oscillator Ground V DDOSC L16  Main Oscillator Power Supply (1.5V) Table 1 Pin Definitions and Functions(cont’d) Symbol Pin In Out PU/ PD 1) Functions

Data Sheet 19 V0.3, 2003-09 V SSOSC L15  Main Oscillator Ground V DD G7, G10 G13 K7,K8 K10  Core and Logic Power Supply (1.5V) V DDP D4, D13, H4, J13, M4, N13,  Ports Power Supply (3.3V) V SS E4 E13 H7, H10 H13 J4,J7 J8,J9 J10 M13  Ground N.C. A1, A16, T1, T16  Not Connected These pins must not be connected. 1) Refers to internal pull-up or pull-down device connected and corresponding type. The notation ‘’ indicates that the internal pull-up or pull-down device is not enabled. Table 1 Pin Definitions and Functions(cont’d) Symbol Pin In Out PU/ PD 1) Functions

Data Sheet 20 V0.3, 2003-09 Parallel Ports The TC1130 has 72 digital input/output port lines, which are organized into four parallel 16-bit ports and one parallel 8-bit port, Port P0 to Port P4 with 3.3V nominal voltage. The digital parallel ports can be all used as general purpose I/O lines or they can perform input/output functions for the on-chip peripheral units. An overview on the port-to- peripheral unit assignment is shown in Figure 4. Figure 4 Parallel Ports of the TC1130 MCA04951mod TC1130 Parallel Ports GPIO3 GPIO4 GPIO Alternate Functions SSC0/ SSC1/ CCU61/ MLI1/ OCDS USB/ MLI0/ SCUGPIO1 GPIO0 GPIO2 GPIOAlternate Functions ASC0/ ASC1/ ASC2/ SSC0/ SSC1/ IIC/ CCU60/EBU/ SCU SSC0/ SSC1/ MultiCAN/ Ethernet/ EBU/ SCU/ OCDS GPTU/ ASC1/ ASC2/ SSC0/ SSC1/ CCU60/ MultiCAN/ MLI0/ EBU/ SCU/ External Interrupts

Data Sheet 21 V0.3, 2003-09 Serial Interfaces The TC1130 includes five serial peripheral interface units: – Asynchronous/Synchronous Serial Interface (ASC) – High-Speed Synchronous Serial Interface (SSC) – Inter IC Serial Interface (IIC) – Universal Serial Bus Interface (USB) – Micro Link Serial Bus Interface (MLI) Asynchronous/Synchronous Serial Interface (ASC) Figure 5 shows a global view of the functional block of three Asynchronous/ Synchronous Serial interfaces (ASC0, ASC1 and ASC2). Each ASC Module, (ASC0/ASC1/ASC2) communicates with the external world via one pair of I/O lines. The RXD line is the receive data input signal (in Synchronous Mode also output). TXD is the transmit output signal. Clock control, address decoding, and interrupt service request control are managed outside the ASC Module kernel. The Asynchronous/Synchronous Serial Interfaces provide serial communication between the TC1130 and ot her microcontrollers, microprocessors or external peripherals. Each ASC supports full-duplex asynchronous communication and half-duplex synchronous communication. In Synchronous Mode, data is transmitted or received synchronous to a shift clock which is generated by the ASC internally. In Asynchronous Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be selected. Parity, framing, and overrun error detection are provided to increase the reliability of data transfers. Transmission and reception of data are double-buffered. For multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator provides the ASC with a separate serial clock signal that can be very accurately adjusted by a prescaler implemented as a fractional divider.

Data Sheet 22 V0.3, 2003-09 Figure 5 General Block Diag ram of the ASC Interfaces MCB04485_mod ASC0 Module (Kernel) Port Control ASC1 Module (Kernel) Clock Control Address Decoder Interrupt Control fASC1 to DMA EIR TBIR TIR RIR Clock Control Address Decoder Interrupt Control fASC0 to DMA EIR TBIR TIR RIR P2.0/ RXD0 P2.1/ TXD0 P0.0/ RXD1B P0.1/ TXD1B P2.8/ RXD1A P2.9/ TXD1A RXD_I1 RXD_O RXD_I0 TXD_O RXD_I1 RXD_O RXD_I0 TXD_O ASC2 Module (Kernel) Clock Control Address Decoder Interrupt Control fASC1 to DMA EIR TBIR TIR RIR P0.2/ RXD2B P0.3/ TXD2B P2.10/ RXD2A P2.11/ TXD2ARXD_I1 RXD_O RXD_I0 TXD_O

Data Sheet 23 V0.3, 2003-09 Features:  Full-duplex asynchronous operating modes – 8-bit or 9-bit data frames, LSB first – Parity bit generation/checking – One or two stop bits – Baud rate from 4.6875 MBaud to 1.1 Baud (@ 75 MHz clock)  Multiprocessor mode for automatic address/data byte detection  Loop-back capability  Half-duplex 8-bit synchronous operating mode – Baud rate from 9.375 MBaud to 762.9 Baud (@ 75 MHz clock)  Support for IrDA data transmission up to 115.2 KBaud maximum.  Double buffered transmitter/receiver  Interrupt generation – On a transmitter buffer empty condition – On a transmit last bit of a frame condition – On a receiver buffer full condition – On an error condition (frame, parity, overrun error) F I F O – 8 byte receive FIFO (RXFIFO) – 8 byte transmit FIFO (TXFIFO) – Independent control of RXFIFO and TXFIFO – 9-bit FIFO data width – Programmable Receive/Transmit Interrupt Trigger Level – Receive and Transmit FIFO filling level indication – Overrun error generation – Underflow error generation

Data Sheet 24 V0.3, 2003-09 High-Speed Synchronous Serial Interface (SSC) Figure 6 shows a global view of the functional blocks of two High-Speed Synchronous Serial interfaces (SSC0 and SSC1). Each SSC supports full-duplex and half-duplex serial synchronous communication up to 37.5 MBaud (@ 75 MHz module clock) with receive and transmit FIFO support. The serial clock signal can be generated by the SSC itself (master mode) or can be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data is double-buffered. A shift clock generator provides the SSC with a separate serial clock signal. Eight slave select inputs are available for slave mode operation. Eight programmable slave select outputs (chip selects) are supported in master mode. Features:  Master and slave mode operation – Full-duplex or half-duplex operation – Automatic pad control possible  Flexible data format – Programmable number of data bits: 2 to 16 bit – Programmable shift direction: LSB or MSB shift first – Programmable clock polarity: idle low or high state for the shift clock – Programmable clock/data phase: data shift with leading or trailing edge of the shift clock  Baud rate generation minimum at 572.2 Baud (@ 75 MHz module clock)  Interrupt generation – On a transmitter empty condition – On a receiver full condition – On an error condition (receive, phase, baud rate, transmit error)  Four-pin interface  Flexible SSC pin configuration  Up to eight slave select inputs in slave mode  Up to eight programmable slave select outputs SLSO in master mode – Automatic SLSO generation with programmable timing – Programmable active level and enable control  4-stage receive FIFO (RXFIFO) and 4-stage transmit FIFO (TXFIFO) – Independent control of RXFIFO and TXFIFO – 2 to 16 bit FIFO data width – Programmable receive/transmit interrupt trigger level – Receive and transmit FIFO filling level indication – Overrun error generation – Underflow error generation

Data Sheet 25 V0.3, 2003-09 Figure 6 General Block Diag ram of the SSC Interfaces Port 1 Control MCB04486_mod Clock Control Address Decoder Interrupt Control fSSC0 Address Decoder Interrupt Control to DMA EIR TIR RIR to DMA EIR TIR RIR Port 2 Control SSC0 Module (Kernel) MRSTB MTSR Master SLSI1 SLSO[2:1] MRSTA MTSRB MRST MTSRA SCLKB SLCK SCLKA Slave Slave Master Slave Master Port 2 Control SSC1 Module (Kernel) MRSTB MTSR Master SLSO[7:5] MRSTA MTSRB MRST MTSRA SCLKB SLCK SCLKA Slave Slave Master Master P2.3/MTSR0 P2.2/MRST0 P2.4/SCLK0 P2.5/MRST1A P1.15/SLSI0 fCLC0 fSSC1 fCLC1 Clock Control SLSI[7:2]1) SLSI1 Slave SLSI[7:2]1) Enable M/S Select P1.11/SLSO01 1) These lines are not connected SLSO0 Enable1) M/S Select1) P1.13/SLSO02 P2.12/SLSO03 P2.14/SLSO04 SLSO[4:3] Port 0 Control P0.6/SLSO00 P0.7/SLSO10 Port 3 Control SLSO[7:5] P3.7/SLSO05 P3.9/SLSO06 P3.11/SLSO07 P3.8/SLSO15 P3.10/SLSO16 P3.11/SLSO17 SLSO0 SLSO[2:1] SLSO[4:3] Port 1 Control P1.12/SLSO11 P1.14/SLSO12 P3.13/MRST1B P2.6/MTSR1A P3.14/MTSR1B P2.7SCLK1A P3.15/SCLK1B P2.13/SLSO13 P2.15/SLSO14 P0.4/SLSI1

Data Sheet 27 V0.3, 2003-09

Features

 Software compatible to V1.0 of C161RI.  Extended buffer allows up to 4 send/receive data bytes to be stored.  Selectable baud rate generation.  Support of standard 100 KBaud and extended 400 KBaud data rates.  Operation in 7-bit addressing mode or 10-bit addressing mode.  Flexible control via interrupt service routines or by polling.  Dynamic access to up to 2 physical IIC busses.

Data Sheet 29 V0.3, 2003-09  USB1.1 Device Standard Interface  Differential I/O allow cable length up to 5m without additional hardware at target’s end.  Hot attach  USB1.1 full speed device  USB protocol handling in hardware  Clock and data recovery from USB  Bit stripping and bit stuffing functions  CRC5 checking, CRC16 generation and checking  Serial to parallel data conversion  Maintenance of data synchronization bits (DATA0/DATA1 Toggle Bits)  Supports multiple configurations, interfaces and alternate settings  Sixteen endpoints with user configurable endpoint information  Flexible intermediate buffering of transmission data  Powerful data handling capability, FIFO-support  Back-to-back transfers fully supported by module automatism  Multi packet transfer without CPU load  Handles data transfer with minimum CPU load  Auto increment and single address modes selectable for easy data access  Powerful interrupt generation  Meets suspend power consumption restrictions in Power Down Mode  Remote wakeup from USB bus activity  Explicit support of setup information  Enhanced status monitoring

Data Sheet 31 V0.3, 2003-09 The Micro Link Serial Bus Interface is dedicated for the serial communication between controllers of the AUDO - NG family. The communication is intended to be fast and intelligent due to an address translation system, and it is not necessary to have any special program in the second controller. Features:  Serial communication from the MLI transmitter to MLI receiver of another controller  Module supports connection of each MLI with up to four MLI from other controllers (see implementation sub-chapter for details for this product)  Fully transparent read/write access supported (= remote programming)  Complete address range of target controller available  Special protocol to transfer data, address offset, or address offset and data  Error control using a parity bit  32 - bits, 16 - bits, and 8 - bits data transfers  Address offset width: from 1 to 16 - bits  Baud rate: fMLI / 2 (symmetric shift clock approach), baud rate definition by the corresponding fractional divider

Data Sheet 33 V0.3, 2003-09  Overflow signals can be selected to generate service requests, pin output signals, and T2 trigger events  Two input pins can define a count option Features of T2:  Count up or down is selectable  Operating modes: –T i m e r – Counter – Quadrature counter (incremental/phase encoded counter interface) O p t i o n s : – External start/stop, one-shot operation, timer clear on external event – Count direction control through software or an external event – Two 32-bit reload/capture registers  Reload modes: – Reload on overflow or underflow – Reload on external event: positive transition, negative transition, or both transitions  Capture modes: – Capture on external event: positive transition, negative transition, or both transitions – Capture and clear timer on external event: positive transition, negative transition, or both transitions  Can be split into two 16-bit counter/timers  Timer count, reload, capture, and trigger functions can be assigned to input pins. T0 and T1 overflow events can also be assigned to these functions.  Overflow and underflow signals can be used to trigger T0 and/or T1 and to toggle output pins  T2 events are freely assignable to the service request nodes.

Data Sheet 34 V0.3, 2003-09 Capture/Compare Unit 6 (CCU6) Figure 11 shows a global view of all functional blocks of two Capture/Compare Units (CCU60 & CCU61). Both of the CCU6 modules is further supplied by clock control, interrupt control, address decoding, and port control logic. One DMA request can be generated by each CCU6 module. Each CCU6 provides two independent timers (T12, T13), which can be used for PWM generation, especially for AC-motor control. Additionally, special control modes for block commutation and multi-phase machines are supported. Timer 12 Features  Three capture/compare channels, each channel can be used either as capture or as compare channel.  Generation of a three-phase PWM supported (six outputs, individual signals for highside and lowside switches)  16 bit resolution, maximum count frequency = peripheral clock  Dead-time control for each channel to avoid short-circuits in the power stage  Concurrent update of the required T12/13 registers  Center-aligned and edge-aligned PWM can be generated  Single-shot mode supported  Many interrupt request sources  Hysteresis-like control mode Timer 13 Features  One independent compare channel with one output  16 bit resolution, maximum count frequency = peripheral clock  Can be synchronized to T12  Interrupt generation at period-match and compare-match  Single-shot mode supported Additional Features  Block commutation for Brushless DC-drives implemented  Position detection via Hall-sensor pattern  Automatic rotational speed measurement for block commutation  Integrated error handling  Fast emergency stop without CPU load via external signal (CTRAP  Control modes for multi-channel AC-drives  Output levels can be selected and adapted to the power stage

Data Sheet 35 V0.3, 2003-09 Figure 11 General Block Diagram of the CCU6 Interrupt Control TC1130_CCU6_imple CCU60 Module (Kernel) Port 2 Control To DMA Clock Control Address Decoder fCCU To DMA SRC0 SRC1 SRC2 SRC3 P2.6 /CC600 P2.12 /CTRAP0 CC62 COUT62 COUT61 COUT63 CC60 COUT60 CCPOS2 CC61 /CTRAP CCPOS0 CCPOS1 P2.13 /CCPOS00 P2.14 /CCPOS01 P2.15 /CCPOS02 P2.7 /COUT600 P2.8 /CC601 P2.9 /COUT601 P2.10 /CC602 P2.11 /COUT602 P2.5 /COUT603 CCU61 Module (Kernel) Port 3 Control P3.1 /CC610 P3.7 /CTRAP1 CC62 COUT62 COUT61 COUT63 CC60 COUT60 CCPOS2 CC61 /CTRAP CCPOS0 CCPOS1 P3.8 /CCPOS10 P3.9 /CCPOS11 P3.10 /CCPOS12 P3.2 /COUT610 P3.3 /CC611 P3.4 /COUT611 P3.5 /CC612 P3.6 /COUT612 P3.0 /COUT613 SRC0 SRC1 SRC2 SRC3 P0.5 / CCU60_T12HR P0.6 / CCU60_T13HR T12HR T13HR P3.11 / CCU61_T12HR P3.12 / CCU61_T13HR T12HR T13HR

Data Sheet 37 V0.3, 2003-09 The bit timings for the CAN nodes are derived from the peripheral clock (fCAN ) and are programmable up to a data rate of 1 MBaud. A pair of receive and transmit pins connects each CAN node to a bus transceiver.  Compliant to ISO 11898.  CAN functionality according to CAN specification V2.0 B active.  Dedicated control registers are provided for each CAN node.  A data transfer rate up to 1 MBaud is supported.  Flexible and powerful message transfer control and error handling capabilities are implemented.  Advanced CAN bus bit timing analysis and baud rate detection can be performed for each CAN node via the frame counter.  Full-CAN functionality: A set of 128 message objects can be individually – allocated (assigned) to any CAN node – configured as transmit or receive object – setup to handle frames with 11-bit or 29-bit identifier – counted or assigned a timestamp via a frame counter – configured to remote monitoring mode  Advanced Acceptance Filtering: – Each message object provides an individual acceptance mask to filter incoming frames. – A message object can be configured to accept only standard or only extended frames or to accept both standard and extended frames. – Message objects can be grouped into 4 priority classes. – The selection of the message to be transmitted first can be performed on the basis of frame identifier, IDE bit and RTR bit according to CAN arbitration rules.  Advanced Message Object Functionality: – Message Objects can be combined to build FIFO message buffers of arbitrary size, which is only limited by the total number of message objects. – Message objects can be linked to form a gateway to automatically transfer frames between 2 different CAN buses. A single gateway can link any two CAN nodes. An arbitrary number of gateways may be defined.  Advanced Data Management: – The Message objects are organized in double chained lists. – List reorganizations may be performed any time, even during full operation of the CAN nodes. – A powerful, command driven list controller manages the organization of the list structure and ensures consistency of the list. – Message FIFOs are based on the list structure and can easily be scaled in size during CAN operation.

Data Sheet 38 V0.3, 2003-09 – Static Allocation Commands offer compatibility with TwinCAN applications, which are not list based.  Advanced Interrupt Handling: – Up to 16 interrupt output lines are available. Most interrupt requests can be individually routed to one of the 16 interrupt output lines. – Message postprocessing notifications can be flexibly aggregated into a dedicated register field of 256 notification bits.

Data Sheet 39 V0.3, 2003-09 Ethernet Controller The MAC controller implements the IEEE 802.3 and operates either at 100 Mbps or 10 Mbps. Figure 13 shows a global view of the Ethernet Controller module with the module specific interface connections. Figure 13 General Block Diagram of the Ethernet Controller The Ethernet controller comprises the following functional blocks: 1. Media Access Controller (MAC) 2. Receive Buffer (RB) 3. Transmit Buffer (TB) 4. Data Management Unit in Receive Direction (DMUR) 5. Data Management Unit in Transmit Direction (DMUT) MCB04942mod Port Control P1.14 / MII_RxER FPI (M/S) P1.13 / MII_RxD[3] P1.12 / MII_RxD[2] P1.11 / MII_RxD[1] P1.10 / MII_RxD[0] P1.9 / MII_COL P1.8 / MII_CRS P1.7 / MII_RxDV P1.6 / MII_MDC P1.5 / MII_TxEN P1.4 / MII_TxER P1.3 / MII_TxD[3] P1.2 / MII_TxD[2] P1.1 / MII_TxD[1] P1.0 / MII_TxD[0] MII_TxCLK MII_TxCLK MII_TDIO MIIMAC Ethernet Controller RB TB DMUR DMUT

Data Sheet 40 V0.3, 2003-09 RB as well as TB provides on-chip data buffering whereas DMUR and DMUT perform data transfer from/to the shared memory. Two interfaces are provided by the Ethernet Controller Module: 1. MII interface for connection of Ethernet PHYs via eighteen Input / Output lines 2. Master/slave FPI bus interface for connection to the on-chip system bus for data transfer as well as configuration.  Media Independent Interface (MII) according to IEEE 802.3  Support 10 or 100 Mbps MII-based Physical devices.  Support Full Duplex Ethernet.  Support data transfer between Ethernet Controller and COM-DRAM.  Support data transfer between Ethernet Controller and SDRAM via EBU.  256 x 32 bit Receive buffer and Transmit buffer each.  Support burst transfers up to 8 x 32 Byte. Media Access Controller (MAC)  100/10-Mbps operations  Full IEEE 802.3 compliance  Station management signaling  Large on-chip CAM (Content Addressable Memory)  Full duplex mode  80-byte transmit FIFO  16-byte receive FIFO  PAUSE Operation  Flexible MAC Control Support  Support Long Packet Mode and Short Packet Mode  PAD generation Media Independent Interface (MII)  Media independence.  Multi-vendor point of interoperability.  Support connection of MAC layer and Physical (PHY) layer devices.  Capable of supporting both 100 Mb/s and 10 Mb/s data rates.  Data and delimiters are synchronous to clock references.  Provides independent four bit wide transmit and receive data paths.  Support connection of PHY layer and Station Management (STA) devices.  Provides a simple management interface.  Capable of driving a limited length of shielded cable.

Data Sheet 41 V0.3, 2003-09 On-Chip Memories The TC1130 provides the following on-chip memories:  Program Memory Interface (PMI) with – 32 KBytes Scratch-pad Code RAM (SRAM) – 16 KBytes Instruction Cache Memory (I-CACHE)  Data Memory Interface (DMI) with – 28 KBytes Scratch-pad Data RAM (SRAM) – 4 KBytes Data Cache Memory (D-CACHE)  Data Memory Unit (DMU) with – 64 KBytes SRAM  16 KBytes Boot ROM (BROM)

Data Sheet 42 V0.3, 2003-09 Address Map Table 2 defines the specific segment oriented address blocks of the TC1130 with its address range, size, and PMI/DMI access view. Table 3 shows the block address map of the Segment 15 which includes on-chip peripheral units and ports. Table 2 TC1130 Block Address Map Seg- ment Address Range Size Description DMI Acc. PMI Acc. 0 – 7 0000 0000H – 7FFF FFFFH

2 GB MMU Space via

c a c h e d 8 8000 0000 H – 8FFF FFFFH

256 MB External Memory Space

9 9000 0000 H – 9FDF FFFF H

256 MB Reserved via

A000 0000H – AFBF FFFF H

252 MB External Memory Space via

n o c a c h e d AFC0 0000 H – AFC0 FFFF H

64 KB DMU Space

AFC1 0000H – AFFF FFFF H ~4 MB Reserved

11 B000 0000 H –

C000 0000H – C000 FFFFH

64 KB DMU via

c a c h e d C001 0000H – CFFF FFFF H ~ 256 MB Reserved

Data Sheet 43 V0.3, 2003-09 D000 0000H – D000 7FFFH

32 KB DMI Local Data RAM (LDRAM) DMI

D000 8000H – D3FF FFFF H ~ 64 MB Reserved D400 0000H – D400 7FFFH

32 KB PMI Local Code Scratchpad

RAM (SPRAM) via LMB PMI local D400 8000H – D7FF FFFF H ~64 MB Reserved D800 0000H – DDFF FFFF H

96 MB External Memory Space

LMBDE00 0000H – DEFF FFFF H

16 MB Emulator Memory Space

DF00 0000H – DFFF BFFF H ~16 MB Reserved – – DFFF C000 H – DFFF FFFF H

16 KB Boot ROM Space via

E000 0000H – E7FF FFFF H

128 MB External Memory Space via

E800 0000H – E83F FFFFH

4 MB Reserved for mapped space for

lower 4 MByte of Local Memory in segment 12 (Transformed by LFI bridge to C000 0000 H – C03F FFFFH ) – – E840 0000H – E84F FFFFH

1 MB Reserved for mapped space for

lower 1 MByte of Local Memory in segment 13 (Transformed by LFI bridge to D000 0000 H – D00F FFFFH ) acces s only from FPI bus side of LFI access only from FPI bus side of LFI E850 0000 H – E85F FFFFH

1 MByte of Local Memory in

(Transformed by LFI bridge to D400 0000 H – D40F FFFFH ) E860 0000H – EFFF FFFF H

122 MB Reserved – –

Table 2 TC1130 Block Address Map (cont’d) Seg- ment Address Range Size Description DMI Acc. PMI Acc.

Data Sheet 44 V0.3, 2003-09 F000 0000H – F00F FFFFH

1 MB On-Chip System Peripherals &

F010 0000H – F027 FFFFH

1.5 MB Peripherals on SMIF Interface

F028 0000H – F200 00FFH ~29.5 MB Reserved – – F200 0100 H – F200 05FFH 1280 Bytes Ethernet Controller Registers via FPI via FPI F200 0600 H – F7E0 FEFF H ~94 MB Reserved – – F7E0 FF00H – F7E0 FFFFH 256 Bytes CPU Slave Interface Registers (CPS) via LMB via LMB F7E1 0000 H – F7E1 FFFFH

64 KB Core SFRs

F7E2 0000H – F7FF FFFFH ~1.8 MB Reserved – – F800 0000H – F87F FFFFH

8 MB LMB Peripheral Space (EBU

and local memory DMU control registers) via LMB via LMB F880 0000 H – FFFF FFFF H

120 MB Reserved – –

Table 3 Block Address Map of Segment 15 Symbol Description Address Range Size System Peripheral Bus (SPB) SCU System Control Unit (incl. WDT) F000 0000 H - F000 00FFH 256 Bytes SBCU FPI Bus Control Unit F000 0100 H - F000 01FFH 256 Bytes STM System Timer F000 0200 H - F000 02FFH 256 Bytes OCDS On-Chip Debug Support (Cerberus) F000 0300H - F000 03FFH 256 Bytes – Reserved F000 0400 H - F000 04FFH 256 Bytes – Reserved F000 0500 H - F000 05FFH 256 Bytes Table 2 TC1130 Block Address Map (cont’d) Seg- ment Address Range Size Description DMI Acc. PMI Acc.

Data Sheet 45 V0.3, 2003-09 GPTU General Purpose Timer Unit F000 0600 H - F000 06FFH 256 Bytes – Reserved F000 0700 H - F000 07FFH 256 Bytes – Reserved F000 0800 H - F000 08FFH 256 Bytes – Reserved F000 0900 H - F000 09FFH 256 Bytes – Reserved F000 0A00 H - F0000AFFH 256 Bytes – Reserved F000 0B00 H - F0000BFFH 256 Bytes P0 Port 0 F000 0C00 H -F0000CFFH 256 Bytes P1 Port 1 F000 0D00 H -F0000DFFH 256 Bytes P2 Port 2 F000 0E00 H -F000 0EFFH 256 Bytes P3 Port 3 F000 0F00 H - F000 0FFFH 256 Bytes P4 Port 4 F000 1000 H - F000 10FFH 256 Bytes – Reserved F000 1100 H - F000 11FFH 256 Bytes – Reserved F000 1200 H - F000 12FFH 256 Bytes – Reserved F000 1300 H - F000 13FFH 256 Bytes – Reserved F000 1400 H - F000 14FFH 256 Bytes – Reserved F000 1500 H - F000 15FFH 256 Bytes – Reserved F000 1600 H - F000 16FFH 256 Bytes – Reserved F000 1700 H - F000 17FFH 256 Bytes – Reserved F000 1800 H - F000 18FFH 256 Bytes – Reserved F000 1900 H - F000 19FFH 256 Bytes CCU60 Capture/Compare Unit 0 F000 2000 H - F000 20FFH 256 Bytes CCU61 Capture/Compare Unit 1 F000 2100 H - F000 21FFH 256 Bytes – Reserved F000 2200 H - F000 3BFFH – DMA Direct Memory Access Controller F000 3C00 H - F0003EFFH 3 × 256 Bytes – Reserved F000 3F00 H - F000 3FFFH – CAN MultiCAN Controller F000 4000 H - F000 5FFFH 8 KBytes – Reserved F000 6000 H - F00E1FFFH – USB USB RAM based Registers F00E 2000 H - F00E 219FH 416 Bytes USB USB RAM F00E 21A0 H - F00E 27FFH 1.6 KBytes USB USB Registers F00E 2800 H - F00E 28FFH 256 Bytes Table 3 Block Address Ma p of Segment 15(cont’d) Symbol Description Address Range Size

Data Sheet 46 V0.3, 2003-09 – Reserved F00E 2900 H - F00F FFFFH – Units on SMIF Interface of DMA Controller – Reserved F010 0000 H - F010 00FFH 256 Byte SSC0 Synchronous Serial Interface 0 F010 0100H - F010 01FFH 256 Byte SSC1 Synchronous Serial Interface 1 F010 0200H - F010 02FFH 256 Byte ASC0 Async./Sync. Serial Interface 0 F010 0300H - F010 03FFH 256 Byte ASC1 Async./Sync. Serial Interface 1 F010 0400H - F010 04FFH 256 Byte ASC2 Async./Sync. Serial Interface 2 F010 0500H - F010 05FFH 256 Byte I2C Inter IC F010 0600 H - F010 06FFH 256 Byte – Reserved F010 0700 H - F010BFFFH – MLI0 Multi Link Interface 0 F010 C000 H -F010C0FFH 256 Bytes MLI1 Multi Link Interface 1 F010 C100 H -F010C1FFH 256 Bytes MCHK Memory Checker F010 C200 H -F010C2FFH 256 Bytes – Reserved F010 C300 H -F01D FFFFH – MLI0_ SP0 MLI0 Small Transfer Window 0 F01E 0000H - F01E 1FFFH 8 KBytes MLI0_ SP1 MLI0 Small Transfer Window 1 F01E 2000H - F01E 3FFFH 8 KBytes MLI0_ SP2 MLI0 Small Transfer Window 2 F01E 4000H - F01E 5FFFH 8 KBytes MLI0_ SP3 MLI0 Small Transfer Window 3 F01E 6000H - F01E 7FFFH 8 KBytes MLI1_ SP0 MLI1 Small Transfer Window 0 F01E 8000H - F01E 9FFFH 8 KBytes MLI1_ SP1 MLI1 Small Transfer Window 1 F01E A000H - F01E BFFFH 8 KBytes MLI1_ SP2 MLI1 Small Transfer Window 2 F01E C000 H - F01E DFFFH 8 KBytes MLI1_ SP3 MLI1 Small Transfer Window 3 F01E E000H - F01E FFFFH 8 KBytes – Reserved F01F 0000 H - F01F FFFFH – MLI0_ LP0 MLI0 Large Transfer Window 0 F020 0000H - F020 FFFFH 64 K Bytes Table 3 Block Address Ma p of Segment 15(cont’d) Symbol Description Address Range Size

Data Sheet 47 V0.3, 2003-09 MLI0_ LP1 MLI0 Large Transfer Window 1 F021 0000H - F021 FFFFH 64 K Bytes MLI0_ LP2 MLI0 Large Transfer Window 2 F022 0000H - F022 FFFFH 64 K Bytes MLI0_ LP3 MLI0 Large Transfer Window 3 F023 0000H - F023 FFFFH 64 K Bytes MLI1_ LP0 MLI1 Large Transfer Window 0 F024 0000H - F024 FFFFH 64 K Bytes MLI1_ LP1 MLI1 Large Transfer Window 1 F025 0000H - F025 FFFFH 64 K Bytes MLI1_ LP2 MLI1 Large Transfer Window 2 F026 0000H - F026 FFFFH 64 K Bytes MLI1_ LP3 MLI1 Large Transfer Window 3 F027 0000H - F027 FFFFH 64 K Bytes – Reserved F028 0000 H - F200 00FFH – ECU Ethernet Controller Unit F200 0100 H - F200 05FFH 1280Bytes – Reserved F200 0600 H - F7E0FEFFH – CPU (Part of System Peripheral Bus) CPU SFRs CPU Slave Interface F7E0 FF00 H -F7E0FFFFH 256 Bytes Reserved F7E1 0000 H –F7E17FFFH – MMU F7E1 8000 H –F7E180FFH 256 Bytes Reserved F7E1 8100 H -F7E1BFFFH – Memory Protection Registers F7E1 C000 H -F7E1EFFF H 12K Bytes Reserved F7E1 F000 H - F7E1FCFFH – Core Debug Register (OCDS) F7E1 FD00 H -F7E1FDFF H 256 Bytes Core Special Function Registers (CSFRs) F7E1 FE00H -F7E1FEFF H 256 Bytes General Purpose Register (GPRs) F7E1 FF00H -F7E1 FFFFH 256 Bytes – Reserved F7E2 0000 H -F7FFFFFFH – Local Memory Buses (LMB) EBU External Bus Interface Unit F800 0000 H - F800 03FFH 1KBytes Table 3 Block Address Ma p of Segment 15(cont’d) Symbol Description Address Range Size

Data Sheet 48 V0.3, 2003-09 Memory Protection System The TC1130 memory protection system specifies the addressable range and read/write permissions of memory segments available to the currently executing task. The memory protection system controls the position and range of addressable segments in memory. It also controls the kinds of read and write operations allowed within addressable memory segments. Any illegal memory access is detected by the memory protection hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the error. Thus, the memory protection system protects critical system functions against both software and hardware errors. The memory protection hardware can also generate signals to the Debug Unit to facilitate tracing illegal memory accesses. In TC1130, TriCore supports two address spaces: The virtual address space and The physical address space. Both address space are 4GB in size and divided into 16 segments with each segment being 256MB. The upper 4 bits of the 32-bit address are used to identify the segment. Virtual segments are numbered 0 - 15. But a virtual address is always translated into a physical address before accessing memory. The virtual address is translated into a physical address using one of two translation mechanisms: (a) direct translation, and (b) Page Table Entry (PTE) based translation. If the virtual address belongs to the upper half of the virtual address space then the virtual address is directly used as the physical address (direct translation). If the virtual address belongs to the lower half of the address space, then the virtual address is used directly as the physical address if the processor is operating in Physical mode (direct translation) or translated using a Page Table Entry if the processor is operating in Virtual mode (PTE translation). These are managed by Memory Managem ent Unit (MMU) Memory protection is enforced using separate mechanisms for the two translation paths. Protection for direct translation Memory protection for addresses that undergo direct translation is enforced using the range based protection that has been used in the previous generation of the TriCore architecture. The range based protection mechanism provides support for protecting DMU Data Memory Unit F800 0400 H - F800 04FFH 256 Bytes - Reserved F800 0500 H -F87F FBFFH – DMI Data Memory Interface Unit F87F FC00 H -F87FFCFF H 256 Bytes PMI Program Memory In terface Unit F87F FD00H -F87FFDFF H 256 Bytes LBCU Local Memory Bus Co ntrol Unit F87F FE00H - F87F FEFFH 256 Bytes LFI LMB to FPI Bus Bridge F87F FF00 H - F87F FFFFH 256 Bytes – Reserved F880 0000 H - FFFF FFFFH – Table 3 Block Address Ma p of Segment 15(cont’d) Symbol Description Address Range Size

Data Sheet 49 V0.3, 2003-09 memory ranges from unauthorized read, write, or instruction fetch accesses. The TriCore architecture provides up to four protection register sets with the PSW.PRS field controlling the selection of the protection register set. Because the TC1130 uses a Harvard-style memory architecture, each Memory Protection Register Set is broken down into a Data Protection Register Set and a Code Protection Register Set. Each Data Protection Register Set can specify up to four address ranges to receive particular protection modes. Each Code Protection Register Set can specify up to two address ranges to receive particular protection modes. Each of the Data Protection Register Sets and Code Protection Register Sets determines the range and protection modes for a separate memory area. Each contains register pairs which determine the address range (the Data Segment Protection Registers and Code Segment Protection Registers) and one register (Data Protection Mode Register) which determines the memory access modes wh ich apply to the specified range. Protection for PTE based translation Memory protection for addresses that undergo PTE based translation is enforced using the PTE used for the address translation. The PTE provides support for protecting a process from unauthorized read, write, or instruction fetches by other processes. The PTE has the following bits that are provided for the purpose of protection: l XE (Execute Enable) enables instruction fetch to the page. l WE (Write Enable) enables data writes to the page. l RE (Read Enable) enables data reads from the page. Furthermore, User-0 accesses to virtual addresses in the upper half of the virtual address space are disallowed when operating in Virtual mode. In Physical mode, User- 0 accesses are disallowed only to segments 14 and 15. Any User-0 access to a virtual address that is restricted to User-1 or Super-visor mode will cause a Virtual Address Protection (VAP) Trap in both the Physical and Virtual modes. Memory Checker The Memory Checker Module (MCHK) al lows to check the data consistency of memories. It uses DMA moves to read from the selected address area and to write the value read in a memory checker input register (the moves should be 32 bit moves). A polynomial checksum calculation is done with each write operation to the memory checker input register

Data Sheet 50 V0.3, 2003-09 On-Chip Bus System The TC1130 includes two bus systems: – Local Memory Bus (LMB) – On-Chip FPI Bus (FPI) The LMB-to-FPI (LFI) bridge interconnects the FPI bus and LMB Bus. Local Memory Bus (LMB) The Local Memory Bus interconnects the memory units and functional units, such as CPU and DMU. The main target of the LMB bus is to support devices with fast response times, optimized for speed. This allows the DMI and PMI fast access to local memory and reduces load on the FPI bus. The Tricore system itself is located on LMB bus. Via External Bus Unit, it interconnects TC1130 and external components. The Local Memory Bus is a synchronous, pipelined, split bus with variable block size transfer support. It supports 8, 16, 32 & 64 bits single beat transactions and variable length 64 bits block transfers. Key Features The LMB provides the following features:  Synchronous, Pipelined, Multi-master, 64-bit high performance bus  Optimized for high speed and high performance  32 bit address, 64 bit data busses  Support Split transactions  Support Variable block size transfer  Burst Mode Read/Write to Memories  Connect Caches and on-chip memory and FPI Bus  Slave controlled wait state insertion  Support Locked transaction (read-modify-write)

Data Sheet 51 V0.3, 2003-09 On-Chip FPI Bus The FPI Bus interconnects the functional units of the TC1130, such as the DMA and on- chip peripheral components. The FPI Bus is designed to be quick to acquire by on-chip functional units, and quick to transfer data. The low setup overhead of the FPI Bus access protocol guarantees fast FPI Bus acquisition, which is required for time-critical applications.The FPI Bus is designed to sustain high transfer rates. For example, a peak transfer rate of up to 800 MBytes/s can be achieved with a 100 MHz bus clock and 32- bit data bus. Multiple data transfers per bus arbitration cycle allow the FPI Bus to operate at close to its peak bandwidth.  Supports multiple bus masters  Supports demultiplexed address/data operation  Address bus up to 32 bits and data buses are 64 bits wide  Data transfer types include 8-, 16-, 32- and 64 bit sizes  Supports Burst transfer  Single- and multiple-data transfers per bus acquisition cycle  Designed to minimize EMI and power consumption  Controlled by an Bus Control Unit (BCU) – Arbitration of FPI Bus master requests – Handling of bus error. LFI The LMB-to-FPI Interface (LFI) block provides the circuitry to interface (bridge) the FPI bus to the Local Memory Bus (LMB). LFI Features  Compatible with the FPI 3.2 and LMB bus Specification V2.4  Supports Burst/Single transactions, from FPI to LMB.  Supports Burst/Single transactions, from LMB to FPI  High efficiency and performance: – fastest access across the bridge takes three cycles, using a bypass. – There are no dead cycles on arbitration.  Acts as the default master on FPI side.  Supports abort, error and retry conditions on both sides of the bridge.  Supports FPI’s clock the same, or half, as the LMB’s clock frequency.  LMB clock is shut when no transactions are issue to LFI from both buses and none are in process in the LFI to minimize the power consumption.

Data Sheet 52 V0.3, 2003-09 LMB External Bus Unit The LMB External Bus Control Unit (EBU) of the TC1130 is the interface between external resources, like memories and peripheral units, and the internal resources connected to on-chip buses if enabled. The basic structure and external interconnections of the EBU are shown in Figure 14. Figure 14 EBU Struct ure and Interfaces MCB04941_mod EBU_LMB AD[31:0] BC[3:0] A[23:0] RD RD/WR WAIT CSCOMB ADV ALE RAS CS[3:0] BFCLKO CAS CKE MR/W P1.15/RMW P0.5/HOLD BFCLKI BAA LMB PMI DMI LFI MMUTri Core FPI To Peripherals SDCLKI SDCLKO Port 0 Control P0.6/HLDA P0.4/BREQ Port 1 Control P2.0/CSEMUPort 2 Control

Data Sheet 53 V0.3, 2003-09 The EBU is mainly used for the operation that masters on LMB bus access external memories through EBU. The EBU controls all transactions required for this operations and in particular handles the arbitration of the external bus between multi-masters. The types of external resources accessed by the EBU are:  INTEL style peripherals (separate RD and WR signals)  ROMs, EPROMs  Static RAMs  PC 100 SDRAMs (Burst Read/Write Capacity / Multi-Bank/Page support)  Specific types of Burst Mode Flashes (Intel 28F800F3/28F160F3, AMD 29BL162)  Special support for external emulator/debug hardware  Support Local Memory Bus (LMB 64-bit)  Support External bus frequency: LMB frequency =1:1 or 1:2  Highly programmable access parameters  Support Intel-style peripherals/devices  Support PC 100 SDRAM (burst access, multibanking, precharge, refresh)  Support 16-and 32-bit SDRAM data bus and 64,128 and 256MBit devices  Support Burst flash (Intel 28F800F3/160F3,AMD 29BL162)  Support Multiplexed access (address &data on the same bus) when PC 100 SDRAM is not implemented  Support Data Buffering: Code Prefetch Buffer, Read/Write Buffer.  External master arbitration compatible to C166 and other Tricore devices  4 programmable address regions (1 dedicated for emulator)  Support Little-endian  Signal for controlling data flow of slow-memory buffer

Data Sheet 54 V0.3, 2003-09 Direct Memory Access (DMA) The Direct Memory Access Controller executes DMA transactions from a source address location to a destination address location, without intervention of the CPU. One DMA transaction is controlled by one DMA channel. Each DMA channel has assigned its own channel register set. The total of 8 channels are provided by one DMA sub-block. The DMA module is connected to 3 bus interfaces in TC1130, the Flexible Peripheral Interconnect Bus (FPI), the DMA Bus and the Micro Link Bus. It can do transfers on each of the buses as well as between the buses. In addition it bridges accesses from the Flexible Peripheral Interconnect Bus to the peripherals on the DMA Bus, allowing easy access to these peripherals by CPU. Clock control, address decoding, DMA request wiring, and DMA interrupt service request control are implementation specific and managed outside the DMA controller kernel.  8 independent DMA channels – Up to 8 selectable request inputs per DMA channel – Programmable priority of DMA channels within a DMA sub-block (2 levels) – Software and hardware DMA request generation – Hardware requests by selected peripherals and external inputs  Programmable priority of the DMA sub-block on the bus interfaces  Buffer capability for move actions on the buses (min. 1 move per bus is buffered).  Individually programmable operation modes for each DMA channel – Single mode: stops and disables DMA channel after a predefined number of DMA transfers – Continuous mode: DMA channel remains enabled after a predefined number of DMA transfers; DMA transaction can be repeated. – Programmable address modification  Full 32-bit addressing capability of each DMA channel – 4 GByte address range – Support of circular buffer addressing mode  Programmable data width of a DMA transaction: 8-bit, 16-bit, or 32-bit  Micro Link supported  Register set for each DMA channel – Source and destination address register – Channel control and status register – Transfer count register  Flexible interrupt generation (the service request node logic for the MLI channels is also implemented in the DMA module)  All buses/interfaces connected to the DMA module must work at the same frequency.  Read/write requests of the System Bus Side to the Remote Peripherals are bridged to the DMA Bus (only the DMA is master on the DMA bus)

Data Sheet 55 V0.3, 2003-09 The basic structure and external interconnections of the DMA are shown in Figure 15 Figure 15 DMA Controller Structure and Interconnections DMA Request Wiring Matrix Interrupt Control TC1130_DMAImplementation Clock Control Address Decoder DMA Controller Arbiter/ Switch Control Switch Bus Interface 0 M/S Bus Interface 2 SMIF SR [3:0] fDMA ASC0 ASC1 ASC2 SSC0 SSC1 CCU60 4SCU (Ext.Trg) MLI1 DMA Interrupt Control Unit MultiCAN To FPI Bus MLI0 I2C CCU61 SR [15:12] Channel 00-07 Registers DMA Sub-Block 0 Request Assignment and Priorisation Unit 0 Transaction Control Engine USB Bus Interface 1 M/S ASC0 ASC1 ASC2 SSC0 SSC1 IIC DMA Bus MLI0 MLI1 Mem Check DMA Bus

Data Sheet 56 V0.3, 2003-09 System Timer The STM within the TC1130 is designed for global system timing applications requiring both high precision and long range. The STM provides the following features:  Free-running 56-bit counter  All 56 bits can be read synchronously  Different 32-bit portions of the 56-bit counter can be read synchronously  Flexible interrupt generation on partial STM content compare match  Driven by clock fSTM after reset (default after reset is fSTM = fSYS = 150 MHz)  Counting starts automatically after a reset operation  STM is reset under following reset causes: – Wake-up reset (PMG_CON.DSRW must be set) – Software reset (RST_REQ.RRSTM must be set) – Power-on reset  STM (and clock divider) is not reset at watchdog reset and hardware reset (HDRST = The STM is an upward counter, running with the system clock frequency fSYS (after reset fSTM = fSYS ). It is enabled per default after reset, and immediately starts counting up. Other than via reset, it is no possible to affect the contents of the timer during normal operation of the application, it can only be read, but not written to. Depending on the implementation of the clock control of the STM, the timer can optionally be disabled or suspended for power-saving and debugging purposes via a clock control register The maximum clock period is 256/fSTM . At fSTM = 150 MHz (maximum), for example, the STM counts 15.2 years before overflowing. Thus, it is capable of continuously timing the entire expected product life-time of a system without overflowing.

Data Sheet 57 V0.3, 2003-09 Figure 16 Block Diagram of the STM Module STM Module

00 H CAP

MCA04795_mod 31 23 15 7 Compare Register CMP0 Interrupt Control Compare Register CMP1 STMIR1 STMIR0 PORST 31 23 15 7 0

Data Sheet 58 V0.3, 2003-09 Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failure. The WDT helps to abort an accidental malfunction of the TC1130 in a user-specified time period. When enabled, the WDT will cause the TC1130 system to be reset if the WDT is not serviced within a user- programmable time period. The CPU must service the WDT within this time interval to prevent the WDT from causing a TC1130 system reset. Hence, routine service of the WDT confirms that the system is functioning properly. In addition to this standard “Watchdog” function, the WDT incorporates the EndInit feature and monitors its modifications. A system-wide line is connected to the ENDINIT bit implemented in a WDT control register, serving as an additional write-protection for critical registers (besides Supervisor Mode protection). Registers protected via this line can only be modified when Supervisor Mode is active and bit ENDINIT = 0. A further enhancement in the TC1130’s Watchdog Timer is its reset prewarning operation. Instead of immediately resetting the device on the detection of an error, as known from standard Watchdogs, the WDT first issues an Non-maskable Interrupt (NMI) to the CPU before finally resetting the device at a specified time period later. This gives the CPU a chance to save system state to memory for later examination of the cause of the malfunction, an important aid in debugging.  16-bit Watchdog counter  Selectable input frequency: fSYS /256 or fSYS /16384  16-bit user-definable reload value for normal Watchdog operation, fixed reload value for Time-Out and Prewarning Modes  Incorporation of the ENDINIT bit and monitoring of its modifications  Sophisticated password access mechanism with fixed and user-definable password fields  Proper access always requires two write accesses. The time between the two accesses is monitored by the WDT and limited.  Access Error Detection: Invalid password (during first access) or invalid guard bits (during second access) trigger the Watchdog reset generation.  Overflow Error Detection: An overflow of the counter triggers the Watchdog reset generation.  Watchdog function can be disabled; access protection and ENDINIT monitor function remain enabled.  Double Reset Detection: If a Watchdog induced reset occurs twice without a proper access to its control register in between, a severe system malfunction is assumed and the TC1130 is held in reset until a power-on reset. This prevents the device from being periodically reset if, for instance, connection to the external memory has been lost such that even system initialization could not be performed.

Data Sheet 59 V0.3, 2003-09  Important debugging support is provided through the reset prewarning operation by first issuing an NMI to the CPU before finally resetting the device after a certain period of time. System Control Unit The System Control Unit (SCU) of the TC1130 handles the system control tasks. All these system functions are tightly coupled, thus, they are conveniently handled by one unit, the SCU. The system tasks of the SCU are: P L L C o n t r o l – PLL_CLC Clock Control Register  Reset Control – Generation of all internal reset signals – Generation of external HDRST reset signal B o o t S c h e m e – Hardware Booting Scheme – Software Booting Scheme  Power Management Control – Enabling of several power-down modes – Control of the PLL in power-down modes  Watchdog Timer  OCDS2 Trace Port Control  Device Identification Registers

Data Sheet 60 V0.3, 2003-09 Interrupt System An interrupt request can be serviced by the CPU which is called “Service Provider”. Interrupt requests are referred as “Service Requests” in this document. Each peripheral in the TC1130 can generate service requests. Additionally, the Bus Control Unit, the Debug Unit, the DMA Controller and even the CPU itself can generate service requests to the Service Provider. As shown in Figure 17, each unit that can generate service requests is connected to one or multiple Service Request Nodes (SRN). Each SRN contains a Service Request Control Register mod_SRCx, where “mod” is the identifier of the service requesting unit and “x” an optional index. The SRNs are connected to the Interrupt Control Unit (ICU) via the CPU Interrupt Arbitration Bus. The ICU arbitrates service requests for the CPU and administers the Interrupt Arbitration Bus. Units which can generate service requests are: – Asynchronous/Synchronous Serial Interfaces (ASC0 & ASC1 & ASC2) with 4 SRNs each – High-Speed Synchronous Serial Interfaces (SSC0 & SSC1) with 3 SRNs each – Inter IC Interface (IIC) with 3 SRNs – Universal Serial Bus (USB) with 8 SRNs – Micro Link Interface MLI0 with 4 SRNs and MLI1 with 2 SRNs – General Purpose Timer Unit (GPTU) with 8 SRNs – Capture/Compare Unit (CCU60 & CCU61) with 4 SRNs each – MultiCAN (CAN) with 16 SRNs – Ethernet Controller with 9 SRNs – External Interrupts with 4 SRNs – Direct Memory Access Controller (DMA) with 4 SRNs – DMA Bus with 1 SRN – System Timer (STM) with 2 SRNs – Bus Control Units (SBCU and LBCU) with 1 SRN each – Peripheral Control Processor (PCP) with 12 SRNs – Central Processing Unit (CPU) with 4 SRNs – Floating Point Unit (FPU) with 1 SRN – Debug Unit (OCDS) with 1 SRN The CPU can make service requests directly to itself (via the ICU). The CPU Service Request Nodes are activated through software.

Data Sheet 61 V0.3, 2003-09 Figure 17 Block Diagram of the TC1130 Interrupt System Service Req. Nodes Service Req. Nodes Service Requestors Interrupt System CPU Interrupt Arbitration Bus Service Requestors

4 SRNs4ASC0 4

4 SRNs4ASC1 4

4 SRNs4ASC2 4

3 SRNs3SSC0 3

4 SRNs4MLI0 4

3 SRNs3SSC1 3

2 SRNs2MLI1 2

16 SRNs16MultiCAN 16

8 SRNs8USB 8

9 SRNs9ETHERNET

8 SRNs8GPTU 8

2 SRNs2STM 2

1 SRN1FPU 1

4 SRNs DMA44

1 SRN SBCU11

1 SRN LBCU11

4 SRNs CCU6144

4 SRNs CCU6044

4 SRN Ext. Int.44

3 SRNs IIC33

Service Req. Nodes 4 4 SRNs 4 CPU Interrupt Control Unit Interrupt Service Providers Int. Req. PIPN CPU CCPN Int. Ack. Software Interrupts ICU

1 SRN1OCDS 1

1 SRN1DMA BUS 1

Data Sheet 62 V0.3, 2003-09 Boot Options The TC1130 booting schemes provides a number of different boot options for the start of code execution. Table 4 shows the boot options available in the TC1130. Table 4 Boot Selections BRKIN 1) 1) This input signal is active low. TM 1) HWCFG [2:0] Type of Boot PC Start Value (User Entry) 11 0 0 0 Bootstrap Loader. Serial boot from ASC to PMI scratchpad, run loaded program DFFF FFFC H (D400 0000H ) 2) This is the BootROM entry address; The start address of user program in parentheses 001 Bootstrap Loader. Serial boot from CAN to PMI scratchpad, run loaded program DFFF FFFC H (D400 0000H ) 010 Bootstrap Loader. Serial boot from SSC to PMI scratchpad, run loaded program DFFF FFFC H (D400 0000H )

011 External memory, EBU as master DFFF FFFC H

(A000 0000H )

100 External memory, EBU as slave DFFF FFFC H

(A000 0000H )

101 Reserved ----

110 PMI scratchpad D400 0000 H

111 Reserved (STOP) ----

0 1 000 Tristate chip ----

001 Go to external emulator space DFFFFFFC H

(DE00 0000H ) 010-111 Reserved (STOP) ---- 0 0 000-111 Reserved (STOP) ----

Data Sheet 63 V0.3, 2003-09 Power Management System The TC1130 power mana gement system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. There are three power management modes:  Run Mode  Idle Mode  Deep Sleep Mode Table 5 describes these features of the power management modes. Besides these explicit software-controlled power-saving modes, TC1130 supports automatic power-saving in that operating units, which are currently not required or idle, are shut off automatically until their operation is required again. Table 5 Power Manageme nt Mode Summary Mode Description Run The system is fully operational. All clocks and peripherals are enabled, as determined by software. Idle The CPU clock is disabled, waiting for a condition to return it to Run Mode. Idle Mode can be entered by software when the processor has no active tasks to perform. All peripherals remain powered and clocked. Processor memory is accessible to peripherals. A reset, Watchdog Timer event, a falling edge on the NMI pin, or any enabled interrupt event will return the system to Run Mode. Deep Sleep The system clock is shut off; only an external signal will restart the system. Entering this state requires an orderly shut-down controlled by the Power Management State Machine (PMSM).

Data Sheet 64 V0.3, 2003-09 On-Chip Debug Support The On-Chip Debug Support of the TC1130 consists of the following building blocks:  OCDS L1 module of TriCore  OCDS L2 interface of TriCore  OCDS L1 module in the BCU of the FPI Bus  OCDS L1 facilities within the DMA  OCDS L2 interface of DMA  OCDS System Control Unit (OSCU)  Multi Core Break Switch (MCBS)  JTAG based Debug Interface (Cerberus JDI)  Suspend functionality of peripherals  TriCore L1 OCDS: – Hardware event generation unit – Break by DEBUG instruction or break signal – Full Single-Step support in hardware, possible also with software break – Access to memory, SFRs, etc. on the fly  DMA L1 OCDS: – Output break request on errors – Suspending of pre-selected channels  Level 2 trace port with 16 pins that outputs either TriCore, or DMA trace  OCDS System Control Unit (Cerberus OSCU) – Minimum number of pins required (no OCDS enable pin) – Hardware allows hot attach of a debugger to a running system – System is secure (can be locked from internal)  Multi Core Break Switch (Cerberus MCBS): – TriCore, DMA, break pins, and BCUs as break sources – TriCore as break targets; other parts can in addition be suspended – Synchronous stop and restart of the system – Break to Suspend converter Figure 18 shows a basic block diagram of the building blocks.

Data Sheet 65 V0.3, 2003-09 Figure 18 OCDS Support Basic Block Diagram Enable, Control and Reset TC1130 OCDS Block Diagram BCU TriCore OCDS OCDS OCDS DMA FPI Watch- dog timer Periph.1 Periph.n JDI Debug I/F JTAG Controller MCBS Break Switch Ce rber us OSCU Break and Suspend Signals Multiplexer DMA L2 BRKIN TDI TDO BRKOUT TRST TMS TCK OCDS2[15:0]

Data Sheet 66 V0.3, 2003-09 Clock Generation Unit The Clock Generation Unit (CGU) allows a very flexible clock generation for TC1130. The power consumption is indirect proportional to the frequency, whereas the performance of the microcontroller is direct proportional to the frequency. During user program execution the frequency can be programmed for an optimal ratio between performance and power consumption. Therefore the power consumption can be adapted to the actual application state. The Clock Generation Unit serves different purposes:  PLL Feature for multiplying clock source by different factors  Direct Drive for direct clock put through  Comfortable state machine for secure switching between basic PLL, direct or prescaler operation  Power Down Mode support  USB Clock source and control The Clock Generation Unit in the TC1130, shown in Figure 19, consists of an oscillator circuit and one Phase-Locked Loop (PLL). The PLL can convert a low-frequency external clock signal to a high-speed internal clock for maximum performance. The PLL also has fail-safe logic that detects degenerate external clock behavior such as abnormal frequency deviations or a total loss of the external clock. It can execute emergency actions if it losses the lock on the external clock. In general, the Clock Generation Unit (CGU) is controlled through the System Control Unit (SCU) module of the TC1130. Figure 19 Clock Generation Unit Block Diagram MCA04940mod Oscillator Circuit XTAL1 XTAL2 fOSC Phase Detect. VCO N Divider PLL fVCO 1:1/1:2 Divider fSYS Lock Detector OSCR PLL_ LOCK NDIV [6:0] VCO_ BYPASS KDIV [3:0] PLL_ BYPASS System Control Unit SCU Register PLL_CLC MUX MUX K:1/K:2 Divider VCO_ SEL[1:0] fCPU SYS FSL Clock Generation Unit CGU P Divi- der Osc. Run Detect. PDIV [2:0] OSC DISC P4.0/ USBCLK Divider MUX fUSB Register SCU_CON USBC LDIV USBC LSEL Register OSC_CON MOSCOGC

Data Sheet 67 V0.3, 2003-09 Recommended Oscillator Circuits Figure 20 Oscillator Circuitries For the main oscillator of the TC1130, the following external passive components are recommended: – Crystal: 0~40 MHz – C1, C2: 10 pF A block capacitor between VDDOSC3 and VSSOSC , VDDOSC and VSSOSC is recommended, too. osc_Cedar TC1130 Oscillator VDDOSC VSSOSC C 1 4 - 40 MHz C 2 XTAL1 XTAL2 TC1130 Oscillator VDDOSC VSSOSC XTAL1 XTAL2 External Clock SignalfOSC fOSC Fundamental Mode Crystal VDDOSC3 VDDOSC3

Data Sheet 69 V0.3, 2003-09 Power Sequencing During Power-Up reset pin PORST has to be held active until both power supply voltages have reached at least their minimum values. During the Power-Up time (rising of the supply voltages from 0 to their regular operating values) it has to be ensured, that the core VDD power supply reaches its operating value first, and then the GPIO VDDP power supply. During the rising time of the core voltage it must be ensured that 0< VDD -VDDP <0.5 V. During power-down, the core and GPIO power supplies VDD and VDDP respectively, have to be switched off completely until all capacitances are discharged to zero, before the next power-up. Note: The state of the pins are undefined when only the port voltage VDDP is switched on.

Data Sheet 70 V0.3, 2003-09 Identification Register Values Table 6 TC1130 Identi fication Registers Short Name Address Value SCU_ID F000 0008 H 002C C001H MANID F000 0070 H 0000 1820H CHIPID F000 0074 H 0000 8C01H RTID F000 0078 H 0000 0000H SBCU_ID F000 0108 H 0000 6A0AH STM_ID F000 0208 H 0000 C005H JDP_ID F000 0308 H 0000 6307H GPTU_ID F000 0608 H 0001 C002H CCU60_ID F000 2008 H 0042 C004H CCU61_ID F000 2108 H 0042 C004H DMA_ID F000 3C08 H 001A C011H CAN_ID F000 4008 H 002B C021H USB_ID F00E 2808 H 0000 4A00H SSC0_ID F010 0108 H 0000 4530H SSC1_ID F010 0208 H 0000 4530H ASC0_ID F010 0308 H 0000 44E2H ASC1_ID F010 0408 H 0000 44E2H ASC2_ID F010 0508 H 0000 44E2H IIC_ID F010 0608 H 0000 4604H MLI0_ID F010 C008 H 0025 C004H MLI1_ID F010 C108 H 0025 C004H MCHK_ID F010 C208 H 001B C001H CPS_ID F7E0 FF08 H 0015 C006H MMU_ID F7E1 8008 H 0009 C002H CPU_ID F7E1 FE18 H 000A C005H EBU_ID F800 0008 H 0014 C004H DMU_ID F800 0408 H 002D C001H DMI_ID F87F FC08 H 0008 C004H PMI_ID F87F FD08 H 000B C004H

Data Sheet 71 V0.3, 2003-09 LBCU_ID F87F FE08 H 000F C005H LFI_ID F87F FF08 H 000C C005H Table 6 TC1130 Identi fication Registers Short Name Address Value

Data Sheet 72 V0.3, 2003-09 Absolute Maximum Rating Targets Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS ) the voltage on VDD pins with respect to ground (VSS ) must not exceed the values defined by the absolute maximum ratings. Parameter Symbol Limit Values Unit Notes min. max. Ambient temperature TA -40 85 °C under bias Storage temperature TST -65 150 °C– Junction temperature TJ -40 125 °C under bias Voltage at 1.5V power supply pins with respect to VSS 1) Applicable for VDD and VDDOSC . VDDC -0.5 1.7 V – Voltage at 3.3V power supply pins with respect to VSS 2) Applicable for VDDP and VDDOSC3 . The maximum voltage difference must not exceed 4.0V in any case (i.e. Supply Voltage = 4.0V and Input Voltage = -0.5V is not allowed). VDDP -0.5 4.0 V – Voltage on any pin with respect to VSS VIN -0.5 4.0 V – Input current on any pin during overload condition IIN -10 10 mA 3) 3) Restricted life time: TBD Absolute sum of all input currents during overload condition Σ IIN – |100| mA 3) CPU & LMB Bus Frequency fsys –1 5 0 M H z – FPI Bus Frequency fFPI –1 0 0 M H z – Power dissipation PD –t b d W –

Data Sheet 73 V0.3, 2003-09 Operating Condition The following operating conditions must not be exceeded in order to ensure correct operation of the TC1130. All parameters specified in the following table refer to these operating conditions, unless otherwise noticed. Parameter Symbol Limit Values Unit Notes Conditionsmin. max. Digital supply voltage VDDC 1.43 1.58 V VDDP 3.14 3.47 V Digital ground voltage VSS 0V – Digital core supply currentIDD 525 mA Ambient temperature under bias TA -40 +85 °C– CPU clock fSYS –1) 1) The TC1130 uses a static design, so the minimum operation frequency is 0 MHz. Due to test time restriction no lower frequency boundary is tested, however.

150 MHz –

Overload current IOV -1 1 mA 2)3) 2) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin overload currents on all digital IO pins may not exceed 50 mA . The supply voltage must remain within the specified limits. 3) Not 100% tested, guaranteed by design and characterization. -3 3 duty cycle ≤ 25% Short circuit current ISC -1 1 mA 4) -3 3 duty cycle ≤ 25% Absolute sum of overload + short circuit currents Σ|IOV |+ |ISC | –| 5 0 | m A 3) |100| duty cycle ≤ 25% Inactive device pin current (VDD =V DDP =0 ) IID -1 1 mA – External load capacitanceC L –5 0 p F ESD strength 2000 – V Human Body Model (HBM)

Data Sheet 74 V0.3, 2003-09 4) Applicable for digital inputs. Parameter Interpretation The parameters listed on the following pages partly represent the characteristics of the TC1130 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: CC (C ontroller C haracteristics): The logic of the TC1130 will provide signals with the respective timing characteristics. SR (System R equirement): The external system must provide signals with the respective timing characteristics to the TC1130.

Data Sheet 75 V0.3, 2003-09 DC Characteristics DC-Characteristics VSS = 0 V; TA = -40°C to +125°C Parameter Symbol Limit Va lues Unit Test Condition min. max. GPIO pins, Dedicated pins and EBU pins Input low voltage VIL SR -0.3 0.8 V LvTTL Input high voltage VIH SR 2.0 V DDP + 0.3 V LvTTL Output low voltage VOL CC – 0.4 V I OL = 2mA Output high voltage VOH CC 2.4 – V I OH = -2mA Pull-up current 1) 1) The current is applicable to the pins, for which a pull up has been specified. Refer to Table 1. IPU x refers to the pull up current for type x in absolute values. |IPUA |CC − 149 µ A VIN = 0V |IPUC |CC −7 . 2 µ A VIN = 0V Pull-down current 2) 2) The current is applicable to the pins, for which a pull down has been specified. Refer to Table 1. IPD x refers to the pull down current for type x in absolute values. |IPDA |CC – 156 µA VIN = VDDP |IPDC |CC – 15.7 µA VIN = VDDP Input leakage current 3) 3) Excluded following pins : NMI, TRST , TCK, TDI, TMS, MII_TXCLK, MII_RXCLK, MII_ MDIO, ALE, P2.1,HWCFG0, HWCFG1, HWCFG2, BRKIN, PORST, HDRST. IOZ1 CC – ±350 nA 0 < VIN < VDDP Pin Capacitance 4) 4) Not 100% tested, guaranteed by design characterization. CIO CC – 10 pF f = 1 MHz TA = 25 °C Oscillator Pins Input low voltage at XTAL1VILX SR 0 0.1 V Input high voltage at XTAL1VIHX SR 1.4 1.5 V Notes:

Data Sheet 76 V0.3, 2003-09 USB Interface Table 8 Full Speed Electr ical Characteristic Table 7 DC Electrical Characteristics Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Supply Voltage Supply Voltage Extern VDDP 3.14 3.3 3.47 V Supply Voltage InternVDDE 1.4 1.5 1.6 V Input Level Differential Input Level Differential Common Mode Range 0.8 2.5 V Range of Sensitivity Single Ended Receiver Threshold low < 0.8 high > 2.0 V Output Levels Static Output Low < 0.3 V with 1.5 kΩ to 3.6 V Static Output High 2.8 3.3 3.6 V with 15 k Ω to ground Leakage Current Hi_Z State Data Line Leakage -10 10 µA0 < V in < 3.3V Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Driver Characteristics Rise / Fall Time 4 20 ns Capacitive load 50 pF Rise / Fall Time Matching 90 100 110 % Capacitive load 50 pF Crossover Voltage of differential Signals 1.3 2.0 V Capacitive load 50 pF Driver Output Impedance 28 44 Ω Steady State Driver Termination Impedance 1.425 1.5 1.575 k Ω

Data Sheet 77 V0.3, 2003-09 Figure 22 USB Interface USB Interface 22 Ω 22 Ω 1.5kΩ RS RS D + D - VDDP VDDP VDDP

Data Sheet 78 V0.3, 2003-09 IIC Pins Each IIC Pin is an open drain output pin with different characteristics than other pins. The related characteristics are given in the following table Note: No 5 V IIC interface is supported with these pads. Only voltages lower than 3.63 V must be applied to these pads. Note: IIC pins have no Pull-Up and Pull-Down devices. Parameter Symbol Limit values Unit Test Conditionsmin. max. Output low voltage V OL CC -0 . 4 0.6 V 3 mA sink current 6 mA sink current Input high voltage 1) Guaranteed by design characterization VIH SR 0.7VDDP VDDP +0.5 V - Input low voltage1) VIL SR -0.5 0.3V DDP V-

Data Sheet 79 V0.3, 2003-09 Power Supply Current Parameter Symbol Limit values Unit Test Conditions typ. 1) 1) Typical values are measured at 25°C, CPU clock at xxx MHz and nominal supply voltage, i.e. 3.3V for VDDP , VDDOSC3 and 1.5V for VDD , VDDOSC . These currents are measured using a typical application pattern. The power consumption of modules can increase or decrease using other application programs. max. Active mode supply current IDD 314 679 mA Sum of IDDS 2) 2) These power supply currents are defined as the sum of all currents at the VDD power supply lines: VDD + VDDP + VDDOSC3 + VDDOSC 153 345 mA IDD at VDD 3) 3) This measurement includes the TriCore and Logic power supply lines. 156 322 mA IDD at VDDP Idle mode supply currentIID 74 154 mA Sum of IDDS 2)4) 4) CPU is in idle state, input clock to all peripherals are enabled, 66 130 mA IDD at VDD 3)4) 61 5 mA IDD at VDDP Deep sleep mode supply current IDS 21 9 mA Sum of IDDS 2)5) 5) Clock generation is disabled at the source. 21 9 mA IDD at VDD 3)5) 3.6 58 µA IDD at VDDP

Data Sheet 80 V0.3, 2003-09 AC Characteristics Note: The values in Blue color are gotten from STA. Power, Pad and Reset Timing Parameter Symbol Limit Values Unit min. max. Min. VDDP voltage to ensure defined pad states VDDPPA CC xxxx – V Oscillator start-up time1) 1) Not measured, guaranteed by device characterization tOSCS CC – 30 ms Minimum PORST active time after power supplies are stable at operating levels tPOA CC 50 – ms H RST pulse width tHD CC 1024 cycles2) 2) Any HDRST activation is internally prolonged to 1024 FPI bus clock cycles fSYS Ports inactive after any reset active3) 3) Not measured, guaranteed by design characterization tPI CC – 30 ns

Data Sheet 81 V0.3, 2003-09 PLL Parameters Phase Locked Loop (PLL) When PLL operation is configured (PLL_CLC.LOCK = 1) the on-chip phase locked loop is enabled and provides the master clock. The PLL multiplies the input frequency by the factor F (fMC = fOSC × F) which results from the input divider, the multiplication factor (N Factor), and the output divider (F = NDIV+1 / (PDIV+1 × KDIV+1)). The PLL circuit synchronizes the master clock to the input clock. This synchronization is done smoothly, i.e. the master clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fMC is constantly adjusted so it is locked to fOSC . The slight variation causes a jitter of fMC which also affects the duration of individual TCMs. The timing listed in the AC Characteristics refers to TCPs. Because fCPU is derived from fMC , the timing must be calculated using the minimum TCP possible under the respective circumstances. The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCP is lower than for one single TCP (see formula and Figure 23). reset_beh 1) as programmed VDDP PORST HDRST Pads Pad- state undefined tpi VDD V DDPPA V DDPPA Pad- state undefined 2) Tri-state, pull device active thd V DDPR OSC toscs 1) 2) 1) 2)2) tPOA tPOA thd

Data Sheet 82 V0.3, 2003-09 This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible. The value of the accumulated PLL jitter depends on the number of consecutive VCO output cycles within the respective timeframe. The VCO output clock is divided by the output prescaler (K = KDIV+1) to generate the master clock signal fMC . Therefore, the number of VCO cycles can be represented as K× N , where N is the number of consecutive fMC cycles (TCM). For a period of N × TCM the accumulated PLL jitter is defined by the corresponding deviation DN : D N [ns] = ±(1.5 + 6.32× N / fMC ); fMC in [MHz], N = number of consecutive TCMs. So, for a period of 3 TCMs @ 20 MHz and K = 12: D3 = ±(1.5 + 6.32× 3 / 20) = 2.448 ns. This formula is applicable for K× N < 95. For longer periods the K×N =95 value can be used. This steady value can be approximated by: DN max [ns] = ±(1.5 + 600/ (K × fMC )). Figure 23 Approximated Accumulated PLL Jitter Note: The bold lines indicate the minimum accumulated jitter which can be achieved by selecting the maximum possible output prescaler factor K. mcb04413_xc.vsd Acc. jitter D N ns 0 51 0 2 0 25 N

10 MHz

K=5

20 M Hz

40 M Hz

K=6K=12K=15 K=8K=10

Data Sheet 83 V0.3, 2003-09 Different frequency bands can be selected for the VCO, so the operation of the PLL can be adjusted to a wide range of input and output frequencies: Table 9 VCO Bands for PLL Operation PLL_CLC.VCOSEL VCO Frequency Range Base Frequency Range 1) Base Frequency Range is the free running operation frequency of the PLL, when no input clock is available.

11 Reserved 2)

2) This option can not be used.

Data Sheet 84 V0.3, 2003-09 AC Characteristics (Operating Conditions apply) Figure 24 Input/Output Wa veforms for AC Tests - for GPIO, Dedicated and EBU pins 2.0V 0.8V test points 2.0V 0.8V 2.4V 0.4V AC inputs during testing are driven at 2.4V for a logic “1” and 0.4V for a logic “0”. Timing measurements are made at VIHmin for a logic “1” and VILmax for a logic “0”.

Data Sheet 85 V0.3, 2003-09 Input Clock Timing (Operating Conditions apply) Figure 25 Input Clock Timing Parameter Symbol Limits Unit min max Oscillator clock frequency with PLL fOSC SR 4 40 MHz Input clock frequency driving at XTAL1 with PLL fOSCDD SR -4 0 M H z Input Clock Duty Cycle (t1 /t2 )S R 4 5 5 5 % Input Clock at XTAL1

0.5 VDD

Data Sheet 86 V0.3, 2003-09 Port Timing (Operating Conditions apply; C L = 50 pF) Figure 26 Port Timing Parameter Symbol Limits Unit min max Port data valid from TRCLK 1) 1) Port data is output with respect to the FPI clock. The TRCLK is used as a reference here since the FPI clock is not available as an external pin and TRCLK is same frequency as CPU clock. Port lines maintain its state for at least 2 CPU clocks. t1 CC − 13 ns TRCLK Old State New State Port Lines FPI_CLK

Data Sheet 87 V0.3, 2003-09 Timing for EBU_LMB Clock Outputs SDCLKO Output Clock Timing (Operating Conditions apply; CL = 50 pF) BFCLKO Output Clock Timing (Operating Conditions apply; C L = 50 pF) Figure 27 EBU Cloc k Output Timing Parameter Symbol Limits Unit min max SDCLKO period t1 C C 1 0 ––n s SDCLKO high time t2 CC 4.5 – − ns SDCLKO low time t3 CC 3 – − ns SDCLKO rise time t4 CC − –2 . 5 n s SDCLKO fall time t5 CC − –2 . 5 n s SDCLKO duty cycle t2/(t2 + t3) DC CC 45 50 55 % Parameter Symbol Limit Values Unit min. typ. max. Clock period t1 C C 2 0 ––n s BFCLKO high time t2 C C 9––n s BFCLKO low time t3 C C 9––n s BFCLKO rise time t4 CC – – 3.5 ns BFCLKO fall time t5 CC – – 2.5 ns BFCLKO duty cycle t2/(t2 + t3)1) 1) This duty cycle is not applicable when BFCON.extclock equals to 10 (1/3 of LMBCLK frequency) DC CC 45 50 55 % BFCLKO/ SDCLKO t5t2 t3 t

Data Sheet 88 V0.3, 2003-09 Timing for SDRAM Access Signals (Operating Conditions apply; C L = 50 pF1)) 1) If application conditions other than 50 pf capacitive load are used, then the proper correlation factor should be used for your specific application condition. For design team, the load should be set according to the system requirement. Parameter Symbol Limits Unit min max CKE output valid time from SDCLKO t1 CC − 8.0 ns CKE output hold time from SDCLKO t2 CC 1.0 − ns Address output valid time from SDCLKO t3 CC − 8.0 ns Address output hold time from SDCLKO t4 CC 1.0 − ns CSx , RAS, CAS, RD/WR, BC(3:0) output valid time from SDCLKO t5 CC − 8.0 ns CSx , RAS, CAS, RD/WR, BC(3:0) output hold time from SDCLKO t6 CC 1.0 − ns AD(31:0) output valid time from SDCLKO t7 CC − 8.0 ns AD(31:0) output hold time from SDCLKO t8 CC 1.0 − ns AD(31:0) input setup time to SDCLKO t9 SR 4.0 − ns AD(31:0) input hold time from SDCLKO t10 SR 3.0 − ns

Data Sheet 89 V0.3, 2003-09 Figure 28 SDRAM Access Timing SDCLKO CKE Address ROW CSx RAS CAS RD/WR BC[3:0] AD[31:0] Column t10 D(0) D(n) SDCLKO CKE Address ROW CSx RAS CAS RD/WR BC[3:0] AD[31:0] Column D(0) D(n) Read Access Write Access t5 t6 SDRAM_Timing t5 t6

Data Sheet 90 V0.3, 2003-09 Timing for Burst Flash Access Signals Operating Conditions apply; C L = 50 pF) Parameter Symbol Limits Unit min max Address output valid time from BFCLKO t1 CC − 11.0 ns Address output hold time from BFCLKO t2 CC 10.0 − ns CSx output valid time from BFCLKO t3 CC − 9.0 ns RD output valid time from BFCLKO t4 CC − 10.0 ns ADV output valid time from BFCLKO t5 CC − 10.0 (7.0) ns ADV output hold time from BFCLKO t6 CC 3.0 (0.0) − ns BAA output valid time from BFCLKO t7 CC − 10.0 (7.0) ns BAA output hold time from BFCLKO t8 CC 3.0 − ns AD(31:0) input setup time to BFCLKO t9 SR 5.0 − ns AD(31:0) input hold time from BFCLKO t10 SR 3.0 − ns WAIT input setup time to BFCLKO t11 SR 5.0 − ns WAIT input hold time from BFCLKO t12 SR 3.0 − ns

Data Sheet 91 V0.3, 2003-09 Figure 29 Burst Flash Access Timing Note: Output delays are always referenced to BFCLKO. The reference clock for input characteristics depends on bit BFCON.FDBKEN. BFCON.FDBKEN = 0: BFCLKO is the input reference clock. BFCON.FDBKEN = 1: BFCLKI is the input reference clock (EBULMB clock feedback enabled) BFCLKO Address CSx ADV RD BAA D[31:0] t9 t11 t12 t10 BF_Timing Address D(0) D(n-1) WAIT Address Phase(s) Command Delay Phase(s) Command Phase(s) Burst Phase(s) Burst Phase(s) Recovery Phase New Addr. Phase(s)

Data Sheet 92 V0.3, 2003-09 Timing for Demultiplexed Access Signals (Operating Conditions apply; C L = 50 pF) 1) 1) The purpose for characterization of Asynchronous access is to provide the performance of all of the signals to user. User can decide whether an extra cycle is needed or not based on above parameters to generate signals with correct timing sequence. It is user’s responsibility to program the correct phase length according to the memory/peripheral device specification and EBU specification. Parameter Symbol Limits Unit min max ALE, CSx, RD/WR, RD, MR/W, BC(3:0) output valid time from output clock t1 CC − 3.2 ns ALE, CSx, RD/WR, RD, MR/W, BC(3:0) output hold time from output clock t2 CC 0.0 − ns Address output valid time from output clock t3 CC − 3.5 ns Address output hold time from output clock t4 CC 0.0 − ns WAIT input setup time to output clock t7 SR 10.6 − ns WAIT input hold time from output clock t8 SR 0.0 − ns AD(31:0) output valid time from output clock t9 CC − 2.6 ns AD(31:0) output hold time from output clock t10 CC 0.0 − ns AD(31:0) input setup time to output clock t11 SR 1.3 − ns AD(31:0) input hold time from output clock t12 SR 0.9 − ns RMW output valid time from output clock t13 CC − 6.3 ns RMW output hold time from output clock t14 CC 1.3 − ns ADV width t15 CC 10 − ns AD(31:0) output hold time from RD/WR t16 CC 0 − ns

Data Sheet 93 V0.3, 2003-09 Figure 30 Demultiplexed Asynch ronous Device Access Timing SDCLKO ADV Address Address CSx RD/WR MR/W CMDELAY BC[3:0] AD[31:0] t10 DataOut Read Access Write Access t5 t6 Demux_Timing WAIT t7 t8 SDCLKO/ SDCLKI ADV Address Address CSx RD MR/W CMDELAY BC[3:0] AD[31:0] t11 t12 DataIn t5 t6 WAIT t7 t8 RMW t13 t14 Address Phase(s) Command Delay Phase(s) (int.) Command Delay Phase(s) (ext.) Command Phase(s) Data Hold Phase(s) Recovery Phase Address Phase(s) Command Delay Phase(s) (int.) Command Delay Phase(s) (ext.) Command Phase(s) Recovery Phase t16 t15 t15

Data Sheet 94 V0.3, 2003-09 Timing for Multiplexed Access Signals (Operating Conditions apply; C L = 50 pF)1) 1) The purpose for characterization of Asynchronous access is to provide the performance of all of the signals to user. User can decide whether an extra cycle is needed or not based on above parameters to generate signals with correct timing sequence. It is user’s responsibility to program the correct phase length according to the memory/peripheral device specification and EBU Specification. Parameter Symbol Limits Unit min max ALE, CSx, RD/WR, RD, MR/W, BC(3:0) output valid time from output clock t1 CC − 3.2 ns ALE, CSx, RD/WR, RD, MR/W, BC(3:0) output hold time from output clock t2 CC 0.0 − ns AD(31:0) output valid time from output clock t3 CC − 2.6 ns AD(31:0) output hold time from output clock t4 CC 0.0 − ns AD(31:0) input setup time to output clock t5 SR 1.4 − ns AD(31:0) input hold time from output clock t6 SR 0.8 − ns WAIT input setup time to output clock t9 SR 10.6 − ns WAIT input hold time from output clock t10 SR 0.0 − ns RMW output valid time from output clock t11 CC − 6.3 ns RMW output hold time from output clock t12 CC 1.3 − ns ADV width t13 CC 10.0 − ns AD(31:0) output hold time from RD/WR t14 CC 0 − ns

Data Sheet 95 V0.3, 2003-09 Figure 31 Write Access in Multiplexed Access SDCLKO ADV AD[31:0] Address CSx RD/WR MR/W CMDELAY BC[3:0] Read Access Write Access t7 t8 Mux_Timing WAIT t9 t10 SDCLKO/ SDCLKI ADV AD[31:0] Address CSx RD MR/W CMDELAY BC[3:0] t7 t8 WAIT t9 t10 RMW t11 t12 t4 t3 Data Data Address Phase(s) Address Hold Phase(s) Command Delay Phase(s) (int.) Command Delay Phase(s) (ext.) Command Phase(s) Data Hold Phase(s) Recovery Phase(s) t13 t14 Address Phase(s) Address Hold Phase(s) Command Delay Phase(s) (int.) Command Delay Phase(s) (ext.) Command Phase(s) Recovery Phase(s) t13

Data Sheet 96 V0.3, 2003-09 Timing for External Bus Arbitration Signals (Operating Conditions apply; C L = 50 pF) Parameter Symbol Limits Unit min max HOLD input setup time to output clock t1 SR 7.3 − ns HOLD input hold time from output clock t2 SR 0.0 − ns HLDA output valid time from output clock t3 CC − 6.2 ns HLDA output hold time from output clock t4 CC 1.0 − ns HLDA input setup time to output clock t5 SR 7.4 − ns HLDA input hold time from output clock t6 SR 0.0 − ns BREQ output valid time from output clock t7 CC − 6.4 ns BREQ output hold time from output clock t8 CC 1.0 − ns CSx drive from EBUCLK t9 CC − 3.1 ns CSx high-impedance from EBUCLK t10 CC − 3.1 ns Other signals high-impedance from EBUCLK t11 CC − 3.2 ns Other signals drive from EBUCLK t12 CC − 3.2 ns

Data Sheet 97 V0.3, 2003-09 Figure 32 External Bus Arbitration Timing SDCLKO HOLD HLDA BREQ CSx Other signals t7t9 t10 t12 Participant Mode Arbiter Mode Arbitration_Timing t11 SDCLKO BREQ HLDA HOLD CSx Other signals t11 t10 t12

Data Sheet 98 V0.3, 2003-09 Timing for Ethernet Signals (Operating Conditions apply; C L = 50 pF) Note: Any other parameters which are not stated here, please refer to ANSI/IEEE Std 802.3, Section 22.3. Parameter Symbol Limits Unit min max ETXCLK period (10 Mbps Ethernet) t1 SR 400.0 − ns ETXCLK high time (10 Mbps Ethernet) t2 SR 140 260 ns ETXCLK low time (10 Mbps Ethernet) t3 SR 140 260 ns ETXCLK period (100 Mbps Ethernet) t1 SR 40.0 − ns ETXCLK high time (100 Mbps Ethernet) t2 SR 14 26 ns ETXCLK low time (100 Mbps Ethernet) t3 SR 14 26 ns ERXCLK period (10 Mbps Ethernet) t1 SR 400.0 − ns ERXCLK high time (10 Mbps Ethernet) t2 SR 140 260 ns ERXCLK low time (10 Mbps Ethernet) t3 SR 140 260 ns ERXCLK period (100 Mbps Ethernet) t1 SR 40.0 − ns ERXCLK high time (100 Mbps Ethernet) t2 SR 14 26 ns ERXCLK low time (100 Mbps Ethernet) t3 SR 14 26 ns ERXD(3:0) input setup to ERXCLK t4 SR 10.0 − ns ERXD(3:0) input hold from ERXCLK t5 SR − 10.0 ns ERXDV input setup to ERXCLK t4 SR 10.0 − ns ERXDV input hold from ERXCLK t5 SR − 10.0 ns ERXER input setup to ERXCLK t4 SR 10.0 − ns ERXER input hold from ERXCLK t5 SR − 10.0 ns ETXD(3:0) output valid from ETXCLK t6 CC − 25.0 ns ETXEN output valid from ETXCLK t6 CC − 25.0 ns ETXER output valid from ETXCLK t6 CC − 25.0 ns EMDC clock period t7 CC 400.0 − ns EMDC high time t8 CC 160 − ns EMDC low time t9 CC 160 − ns EMDIO input setup to EMDC (sourced by STA) t10 SR 10.0 − ns EMDIO input hold from EMDC (sourced by STA) t11 SR − 10.0 ns EMDIO output valid from EMDC (sourced by PHY) t12 CC − 300.0 ns

Data Sheet 99 V0.3, 2003-09 Figure 33 Ethernet Timing ETXCLK ERXCLK ERXD(3:0) ERXDV ERXER t4 t5 valid data ETXD(3:0) ETXEN ETXER valid data EMDC EMDIO (sourced by STA) t10 t11 valid data t12 EMDIO (sourced by PHY) valid data t2 t3 t8 t9

Data Sheet 100 V0.3, 2003-09 SSC Master Mode Timing (Operating Conditions apply; C L = 50 pF) Figure 34 SSC Master Mode Timing Parameter Symbol Limit Values Unit min. max. SCLK clock frequency 1 / t SCLK CC - 25 MHz SCLK clock high time t 1 CC 18 - ns SCLK clock low time t 2 CC 18 - ns SCLK clock rise time t 3 CC - 11 ns SCLK clock fall time t 4 CC - 11 ns MTSR/SLSOx low/high from SCLK edge t 5 CC - 2.0 ns MRST setup to SCLK edge t 6 SR7 -n s MRST hold from SCLK edge t 7 SR5 -n s (CON.PO,CON.PH = 00 or 11)

0.9 V DD

0.1 V DD

State n-1 State n State n+1 (CON.PO,CON.PH = 01 or 10) SCLK MTSR MRST SLSOx1) 1) The transition SLSOx is based on the following setup: SSOTC.TRAIL = 0 and the first SCLK high pulse is in the first one of a transmission.

Data Sheet 101 V0.3, 2003-09 Timing for MLI Interface (Operating Conditions apply; C L = 50 pF) Parameter Symbol Limit Values Unit min. max. TCLK/RCLK clock period t0 CC/SR 26.67 – ns TCLK high time t1 CC 9 – ns TCLK low time t2 CC 9 – ns TCLK rise time t3 CC – 3 ns TCLK fall time t4 CC – 3 ns TDATAx, TVALIDx outputs delay from TCLK t5 CC 08 ns TREADYx inputs setup to TCLK t6 SR tbd – ns RDATAx, RVALIDx inputs setup to RCLK t7 SR 5.3 –n s RDATAx, RVALIDx inputs hold from RCLK t8 SR tbd – ns RREADYx outputs delay hold RCLK t9 CC tbd tbd ns

Data Sheet 102 V0.3, 2003-09 Figure 35 MLI Interface Timing Note: The generation of RREADYx is in the input clock domain of the receiver. The reception of TXREADY is asynchronous to TCLKx (input synchronization with each edge of TCLKx). Meeting the setup time for TXREADY guarantees recognition of the TXREADY at a certain clock edge. TDATAx TVALIDx t5 t5 TCLKx t1 t2 t4t3 RDATAx RVALIDx RCLKx t1 t2 TREADYx

Data Sheet 103 V0.3, 2003-09 Timing for JTAG Signals (Operating Conditions apply; C L = 50 pF) Figure 36 TCK Clock Timing Parameter Symbol Limits Unit min max TCK clock period tTCK CC 50 − ns TCK high time t1 CC 10 − ns TCK low time t2 CC 29 − ns TCK clock rise time t3 CC − 0.4 ns TCK clock fall time t4 CC − 0.4 ns TCK

0.9 VDD

0.1 VDD

Data Sheet 104 V0.3, 2003-09 Figure 37 JTAG Timing Parameter Symbol Limits Unit min max TMS setup to TCK t1 SR 7.85 − ns TMS hold to TCK t2 SR 3.0 − ns TDI setup to TCK t1 SR 10.9 − ns TDI hold to TCK t2 SR 3.0 − ns TDO valid output from TCK t3 CC − 10.7 ns TDO high impedance to valid output from TCK t4 CC − 23.0 ns TDO valid output to high impedance from TCK t5 CC − 26.0 ns TMS TDI TCK TDO t4 t3 t5

Data Sheet 105 V0.3, 2003-09 Timing for OCDS Trace and Breakpoint Signals (Operating Conditions apply;C L(TRCLK) = 25 pF, C L = 50 pF) Figure 38 OCDS Trace Signals Timing Parameter Symbol Limits Unit min max BRK_OUT valid from TRCLK t1 CC − 5.2 ns OCDS2_STATUS[4:0] valid from TRCLK t1 CC 1.7 3.7 ns OCDS2_INDIR_PC[7:0] valid from TRCLK t1 CC 1.7 3.7 ns OCDS2_BRKPT[2:0] valid from TRCLK t1 CC 1.7 3.7 ns CPU Trace Signals TRCLK Old State New State Note: CPU Trace Signals include BRK_IN , BRK_OUT , OCDS2_STATUS[4:0] , OCDS2_INDIR_PC[7:0] and OCDS_BRKPT[2:0].

Data Sheet 106 V0.3, 2003-09 Timing for USB Transceiver Signals (Operating Conditions apply; C L = 50 pF) Figure 39 AC Testing: Input, Output Waveforms Parameter Symbol Limits Unit min max Full speed mode rise time tFR CC 4 20 ns Full speed mode fall time tFF CC 4 20 ns tR 10% 90% 10% 90% tF rise_fall_USB.emf

Data Sheet 107 V0.3, 2003-09 Package Outline Figure 40 P-LBGA-208-2 Package Plastic Package, P-LBGA-208-2 (SMD) (Low Profile Ball Grid Array Package) Y ou can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mmSMD = Surface Mounted Device

Data Sheet 108 V0.3, 2003-09

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