T9000

T9000 AGERE | Alldatasheet

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ISDN Network Termination Node (NTN) Device

1 Description

The T9000 is an ISDN network termination node device that is highly integrated and provides a low- cost solution to support the following: ■ All standard NT1 functions required to attach an S/T interface device to an ISDN network. In addi- tion, the T9000 also supports attachment of two standard analog (POTS) telephones for communi- cations over an ISDN network. ■ Intelligent network termination (INT/Smart NT1) functions, with its built-in controller and support for attachment of two analog phones for communica- tions over an ISDN network. ■ A variation of the V5.1 signaling protocol called narrowband multiservice delivery system (NMDS) adopted by countries using the V5 signaling proto- col (e.g., United Kingdom) In addition, the T9000 can also be used for pair-gain applications where support for more than one tele- phone line is required without the installation of an additional pair of wires from the telephone central office to the customer premises.

2 Features

■ Complete interface to basic rate ISDN networks at the S/T-interface and U-interface reference points. ■ U-interface (LT or NT operation) conforms to ANSI* T1.601 and ETSI TS 080 standards. ■ S/T-interface conforms to ANSI T1.605 standard, ITU-T I.430 recommendation, and ETSI ETS 300 012 standard for the network termination (NT) side of the network. ■ Low power consumption. ■ D-channel HDLC formatter with address recogni- tion and integrated contention resolution scheme. ■ 64-byte D-channel FIFOs. ■ GCI+ interface supporting GCI and generic TDM modes for interfacing to a wide variety of POTS cir- cuits. ■ General-purpose I/O (GPIO) ports with interrupt capability for interfacing to SLICs, codecs, DTMF decoders, and other peripheral devices. ■ Three low-power, general-purpose comparators. ■ Two 100 kHz programmable PWM outputs with an automatic sine wave generation mode to support ringing, pulse metering, etc. ■ 20 kHz—200 kHz programmable dc/dc converter synchronization output. ■ JTAG boundary scan on all digital pins. ■ Power-saving mode. — In this mode, the unused interfaces of the T9000, such as, microcontroller, PWMs, and comparator can remain in powerdown mode, thus resulting in significant reduction in power consumption (see Section 20.2, Power Con- sumption). ■ Packaged in a 100-pin TQFP (thin quad flat pkg). ■ 5 V power supply. ■ Operating temperature range: –40 °C to +85 °C. ■ Integrated 80C32 microcontroller with the following features: — Programmable clock rates (MHz): 15.36, 7.68, 3.84, 1.92, 0.96. — 4K internal SRAM. — 64K internal ROM. — Supports external ROM/RAM. — Can be disabled via pin strap (sleep mode) for use with an external emulator. — Programmable watchdog timer. External ROM and RAM (64K x 8 maximum each) are accessed through an external data/address bus. Support for ROM and RAM space above the 64K limit can be accomplished by memory paging using one or more GPIO signals as an external chip select. Power management routines may be implemented through the microcontroller to power down most of the internal submodules, including the microcontrol- ler itself. An autosleep mode is also included, allow- ing the microcontroller to stop its internal clock and be automatically restarted (microcontroller wake-up) whenever any interrupt is triggered. * ANSI is a registered trademark of American National Standards Institute, Inc.

Contents Page Contents Page 2 Lucent Technologies Inc. Preliminary Data Sheet November 2000ISDN Network Termination Node (NTN) Device T9000 6.1 80C32 Microcontroller Module (80C32 Block) ..17

6.12 Special Instructions for Using the Lucent

7.3 Data Flow/Activation Control Module (DFAC)...30

7.4 Microcontroller Access to Upstream and

10.3.1 GCI-SCIT Mode (GCCF,

20.3 S/T-Interface Receiver Common-Mode

Table 12. GIR0: Global Interrupt Register 0 Table 13. GIR1: Global Interrupt Register 1 Table 14. GIE: Global Interrupt Enable Register Table 15. UPCK: Microcontroller Clock Control Table 16. WDT: Microcontroller Watchdog Timer Table 20. External Program Memory Table 21. AUTOEOC = 1 Messages Table 22. DFCF: DFAC Configuration Register Table 23. DFR: Data Flow Register Table 24. UCR0: U-Interface Control Register #0 Table 25. UCR1: U-Interface Control Register #1 Table 26. USR0: U-Interface Status Register #0 Table 27. USR1: U-Interface Status Register #1 Table 28. ECR0: EOC Control Register 0—Command Table 29. ECR1: EOC Control Register 1—Message Table 30. ESR0: EOC Status Register 0—Command Table 31. ESR1: EOC Status Register 1—Message Table 32. SCR0: S-Interface Control Register #0 Table 33. SCR1: S-Interface Control Register #1 Table 34. SSR: S-Interface Status Register Table 35. MFR0: Multiframe Register, Q-Chan- Table 36. MFR1: Multiframe Register, S-Sub- Table 37. UIR: U-Interface Interrupt Register Table 38. UIE: U-Interface Interrupt Enable Table 39. SIR: S-Interface Interrupt Register Table 40. SIE: S-Interface Interrupt Enable Register Table 41. DOCR: Device Operation Control Table 42. B1UP: B1-Channel Upstream Data Table 43. B2UP: B2-Channel Upstream Data Table 44. B1DN: B1-Channel Downstream Data Table 45. B2DN: B2-Channel Downstream Data Table 46. Reserved 1: Reserved Register for Table 47. Reserved 2: Reserved Register for Table 48. Reserved 3: Reserved Register for Table 49. Reserved 4: Reserved Register for Table 50. Reserved 5: Reserved Register for Table 51. Reserved 6: Reserved Register for Table 52. Reserved 7: Reserved Register for Table 53. Reserved 8: Reserved Register for Table 54. Reserved 9: Reserved Register for Table 55. HTCF: HDLC Transmitter Configuration Table 56. HRCF: HDLC Receiver Configuration Table 57. HTTH: HDLC Transmit FIFO Threshold Table 58. HRTH: HDLC Receive FIFO Threshold Table 59. HTSA: HDLC Transmit FIFO Space

Table 60. HRDA: HDLC Receive FIFO Data Table 62. HTXL: HDLC Transmit Data Last Byte Table 64. HSCR: HDLC SAPI C/R Bit Mask Table 65. HSM0: HDLC SAPI Match Pattern 0 Table 66. HTM0: HDLC TEI Match Pattern 0 Table 67. HSM1: HDLC SAPI Match Pattern 1 Table 68. HTM1: HDLC TEI Match Pattern 1 Table 69. HSM2: HDLC SAPI Match Pattern 2 Table 70. HTM2: HDLC TEI Match Pattern 2 Table 71. HSM3: HDLC SAPI Match Pattern 3 Table 72. HTM3: HDLC TEI Match Pattern 3 Table 73. HSMOD: HDLC SAPI Modifier Register Table 74. HTMOD: HDLC TEI Modifier Register Table 76. HIE: HDLC Interrupt Enable 15 (0x2D) ...68 Table 80. GCCF: GCI+ Configuration Register Table 81. GCOF1: GCI PFS1 Offset Select Table 82. GCOF2: GCI PFS2 Offset Select Table 83. GCDMD: GCI Downstream (Transmit) Table 84. GCDML: GCI Downstream (Transmit) Table 85. GCUMD: GCI Upstream (Receive) Monitor Table 86. GCDCI: GCI Downstream (Transmit) C/I Table 87. GCUCI: GCI Upstream (Receive) C/I Table 90. GPDIR0: GPIO Port 0 Pin Direction Table 91. GPDIR1: GPIO Port 1 Pin Direction Table 92. GPDIR2: GPIO Port 2 Pin Direction Table 93. GPAF0: GPIO Alternate Function Table 94. GPAF1: GPIO Alternate Function Table 95. GPD0: GPIO Port 0 Data Register Table 96. GPD1: GPIO Port 1 Data Register Table 97. GPD2: GPIO Port 2 Data Register Table 98. GPLEI: GPIO Level-Edge-Triggered Table 99. GPPOL: GPIO Interrupt Polarity Table 100. GPIR: GPIO Interrupt Register Table 101. GPIE: GPIO Interrupt Enable Table 103. PWM Sine Modulator Programming Table 104. PW0CF: Pulse-Width Modulator 0 Table 105. PW0VH: Pulse-Width Modulator 0 Table 106. PW0VL: Pulse-Width Modulator 0 Table 107. PW1CF: Pulse-Width Modulator 1 Table 108. PW1VH: Pulse-Width Modulator 1 Table 109. PW1VL: Pulse-Width Modulator 1 Table 110. PWIR: Pulse-Width Modulator Interrupt Table 111. DCCF: dc/dc Configuration Register Table 114. CMT: Comparator Transition Polarity Table 115. CMIR: Comparator Interrupt Register Table 116. CMIE: Comparator Interrupt Enable

3 Block Diagram

Figure 1 shows the architecture of the NTN device. Figure 1. NTN Block Diagram

24 GPIO PINS

4 Pin Information

Note: Alternate pin functions, shown in parentheses (), are selected when the TEST pin is asserted. Alternate pin functions, shown in brackets [], are selected when the corresponding register bits are set. Figure 2. T9000 Pinout

4 Pin Information (continued)

Table 1. S/T-Interface Pins (6) Table 2. U-Interface Pins (7) CSENS 58 — Current Sense. Connect an 11.5 kΩ , 1%, resistor from this pin to GNDA. SCR0[FT] subsequent to this). Internal 50 kΩ pull-down. an adaptive timing algorithm. relative to the S/T transmitter clock. transmitter. Connect to transformer through a 121 Ω , 1% resistor. transmitter. Connect to transformer through a 121 Ω , 1% resistor. receiver. Connect to transformer through a 10 kΩ , 10% resistor. receiver. Connect to transformer through a 10 kΩ , 10% resistor. through a 16.9 Ω, 1% resistor. through a 16.9 Ω, 1% resistor. A (as close to the device pins as possible). capacitor to GNDA (as close to the device pins as possible). 20% capacitor to GNDA (as close to the device pins as possible).

Table 3. GCI+ Pins (5)

• OD = open-drain output, Id = input with an internal 50 kΩ pull-down.

† Depending on the setting of register bit GCCF[GDRIVER], this output can be programmed to either open drain or push-pull. DU 33 I Data Upstream. GCI+ data input. Data Downstream. GCI+ data output. Open-drain† output (typical). running if the U-interface is inactive). GCI Data Clock. Rate defined by GCCF[GRATE(1:0)]. synchronous to the received data on the U-interface. sync pulse for B1 channel (TDM mode). See Table 28. chronous to the received data on the U-interface. Programmable Frame Sync 2. Frame sync pulse for B2 channel. See Table 28. density. Internal 50 kΩ pull-down. 0: No effect on device operation. 1: U transmitter sends SN1 tone continuously.

Table 4. GPIO Pins (24)

• I = input, O = output, Id = input with an internal 50 kΩ pull-down, IU = input with an internal 100 kΩ pull-up.

Schmitt trigger input buffers. Internal 100 kΩ pull-up. as outputs from PWM modules 1 and 0, respectively. Schmitt trigger input buffers. Internal 100 kΩ pull-up. U-interface to continuously transmit single 2B1Q pulses on the U-interface. 0: No effect on device operation. 1: U transmitter sends single pulses continuously. figured as inputs or outputs (see register GPDIR2). Internal 100 kΩ pull-up. is set to 1 (register 0x50). signal FSC (see Section 10, GCI+ Interface Module). signal BCLK (see Section 10, GCI+ Interface Module). interface should be maintained inactive while this function is enabled.

Table 5. 80C32 External Access Pins (27) pin or group of pins first, followed by the function when in ONCE mode. ory. AD[7:0] are open-drain bidirectional I/O ports requiring external pull-ups. drive data onto the bus to be read by the emulator. respond to addresses above 4K. and is used to latch the address applied on A[15:7], AD[7:0]. fetches from internal program memory. —H Z ONCE mode . PSEN is 3-stated. RD 27 O Read Strobe (Active-Low). External data memory read strobe output. 28 O Write Strobe (Active-Low). External data memory write strobe output. and the result is presented to the 80C32 INT0_B input. this signal low whenever an internal interrupt type 0 condition occurs.

Table 5. 80C32 External Access Pins (27) (continued) result is presented to the 80C32 INT1_B input. this signal low whenever an internal interrupt type 1 condition occurs. (see Section 6.7, Clock Generator). upon an exit from RESET. Internal 100 kΩ pull-up. —I U ONCE mode . Same behavior as in normal mode. Internal pull-up. register DIR3 and the SFR port register P3. Internal 50 kΩ pull-down. ONCE mode . RXD is 3-stated. for Using the Lucent 80C32 Block). Internal 50 kΩ pull-down. ONCE mode . TXD is 3-stated.

Table 6. Comparators (6) Table 7. JTAG Pins (4)

• I = input, O = output, IU = input with an internal 100 kΩ pull-up.

INP0 46 I Input Positive, Comparator 0. Connect to 5 V via 1 kΩ. INN0 45 I Input Negative, Comparator 0. Connect to GND via 1 kΩ. INP1 48 I Input Positive, Comparator 1. Connect to 5 V via 1 kΩ. INN1 47 I Input Negative, Comparator 1. Connect to GND via 1 kΩ. INP2 50 I Input Positive, Comparator 2. Connect to 5 V via 1 kΩ. INN2 49 I Input Negative, Comparator 2. Connect to GND via 1 kΩ.

41 I U

during normal operation. Internal 100 kΩ pull-up. 15.36 MHz system clock that is used by the NTN device. mately 20 kΩ . Internal 100 kΩ pull-up. function TCI. This pin is used for factory testing. mately 20 kΩ . Internal 100 kΩ pull-up. alternate function TDI. This pin is used for factory testing. 35 O JTAG Serial Data Output. function TDO. This pin is used for factory testing.

Table 8. Miscellaneous Pins (2)

• I = input, O = output, Id = input with an internal 50 kΩ pull-down.

Table 9. Oscillator Pins (2) Table 10. Power and Ground Pins made on the U-interface. Internal 50 kΩ pull-down. oscillator with CMOS output levels. DDD 3, 22, 39, 80 — Digital Power. 5 V ± 5% power supply pins for digital circuitry. — Digital Ground. Ground leads for digital circuitry. VDDA 53, 57, 67 — Analog Power. 5 V ± 5% power supply lead for the analog circuitry. GND A 52, 59, 66 — Analog Ground. Ground leads for analog circuitry.

5 Control Register Memory Space

Table 11. Control Register Memory Space

5 Control Register Memory Space (continued)

Table 11. Control Register Memory Space (continued)

Lucent Technologies Inc. 17 Preliminary Data Sheet November 2000 ISDN Network Termination Node (NTN) Device T9000

6 Functional Modules

This section covers the functionality of the NTN core modules. 6.1 80C32 Microcontroller Module (80C32 Block) The NTN IC includes an embedded 80C32 microcon- troller, incorporating a 256-byte internal RAM, three 16-bit timer/counters, six interrupt sources, and one serial port I/O. Typical functions of the microcontroller module are as follows: ■ Definition of operation modes for all other NTN mod- ules (U-interface, S/T-interface, etc.) ■ Configuration of the 2B+D data flow paths in the DFAC module ■ Layer 2 and layer 3 processing of the D channel for POTS calls ■ Supervision of the POTS circuitry ■ Device power management

6.2 Program Address Space

The on-chip 64K x 8 mask-programmable ROM occu- pies the full program memory space addressable by the 80C32. The 80C32 addresses this memory via the microcontroller interface (UCI) module. The internal ROM can be disabled so that code from an external ROM can be executed by tying the EA pin low. The microcontroller then fetches the program instruc- tions through its external access port (see Table 5). Applications requiring a larger program space than the 64K x 8 available with the standard 80C32 may use GPIO ports to extend the address space using a pag- ing scheme.

6.3 Data Address Space

The NTN data address space is comprised of several distinct regions as shown in Figure 3. The 80C32 internal RAM is an integral part of the 80C32 architecture and is accessed using the 80C32 MOV instruction (see any standard 80C32 data sheet for details on the internal memory space). The NTN has on-chip registers and SRAM that occupy the lowest 4 Kbytes of the 80C32’s external data mem- ory address space and is accessed using the 80C32 MOVX instruction. The on-chip read and write signals from the 80C32 (shown in Figure 3 as RDi and WRi) are asserted during access to this memory space. The lowest 94 bytes of the 80C32 external space (00—5Dh) are comprised of the device configuration and control registers, and the remaining (4002) bytes (5Eh—0FFFh) are comprised of SRAM. The NTN can also access off-chip RAM up to the 64K address space limit through the external access port (see Table 5). When accessing the 4K on-chip RAM at the bottom of the address space, the on-chip external qualifier function shown in Figure 3 prevents the RDi and WRi signals from propagating to the NTN pins RD and WR (the pins remain 3-stated). When accessing an address outside the 4K range of the on-chip mem- ory space, the RD and WR signals appear on the NTN pins RD and WR. The external qualifier function elimi- nates the need for any external decoding (chip-select) logic when an external RAM is being used. In this scheme, the lowest 4K of any external RAM is not usable. External address decoding logic may be used if it is desirable to use the lowest 4K of the external RAM.

6.4 Timers

Timer 0 and timer 1 can be configured as either inde- pendent timers or counters as specified in the 80C32 data sheet. In counter mode, GPIO ports 1.5 and 1.6 may be configured to generate timer 0’s and timer 1’s trigger sources, respectively (see Section 11, GPIO Ports). Timer 2 can be configured as a timer, a counter, or as a serial baud rate generator. In counter and baud generator mode, GPIO 1.7 may be configured as timer 2’s trigger source.

6.5 Interrupts

The 80C32 accepts six interrupts sources. These inter- rupt sources are interrupt lines INT0 and INT1 (the 80C32 block external interrupts); timer 0, timer 1, and timer 2; and a serial port interrupt. The NTN has an embedded interrupt controller which collapses a large number of interrupt sources (GPIR, UIR, SIR, PWIR, CMIR, GCIR, and HIR) into the two 80C32 interrupt inputs INT0 and INT1. Since the inter- rupt controller can be viewed as an AND function of the NTN interrupt sources, the 80C32 interrupts should be programmed as level-triggered interrupts (TCON.IT0 and TCON.IT1, cleared to 0, the reset default condi- tion). If external edge-triggered interrupts sources must be interfaces to the NTN, ports GPIO0[3:0] and GPIO1[3:0] can be used.

6 Functional Modules (continued)

6.5 Interrupts (continued)

rupt enable bits (see register GIE). Figure 3. NTN Data Memory Address Space

6.6 Interrupt Register Set

Table 12. GIR0: Global Interrupt Register 0 (0x00) until the interrupt condition causing the interrupt goes away. of the microcontroller to access the B-channel data. register (UIR) are active, i.e., all of the U-interface interrupts are collapsed into this bit. register (SIR) are active, i.e., all of the S-interface interrupts are collapsed into this bit. register (GPIR) are active, i.e., all of the GPIO interrupts are collapsed into this bit.

6.6 Interrupt Register Set (continued)

Table 13. GIR1: Global Interrupt Register 1 (0x01) until the interrupt condition causing the interrupt goes away. register (HIR) are active, i.e., all of the HDLC interrupts are collapsed into this bit. register (GCIR) are active, i.e., all of the GCI interrupts are collapsed into this bit. register (PWIR) are active, i.e., all of the PWM interrupts are collapsed into this bit.

Table 14. GIE: Global Interrupt Enable Register (0x02) This register contains enable bits for the interrupts in registers GIR0 and GIR1. 7—5 — Reserved. Program to 0. 4 125IE 125 µs Interrupt Enable. Enables the 125 µs interrupt. 3 II1E Internal Interrupt #1 Enable. Enables internal interrupt #1 bits (HDLCI, GCII, CMPI, PWMI). 2X I 1 E External Interrupt #1 Enable. Enables external interrupt XI1I. 1 II0E Internal Interrupt #0 Enable. Enables internal interrupt #0 bits (BODI, UII, SII, GPIOI). 0X I 0 E External Interrupt #0 Enable. Enables external interrupt XI0I.

6.7 Clock Generator

microcontroller is stopped (UPCK[2:0] = 000), any interrupt will immediately set UPCK = 15.36 MHz. Table 15. UPCK: Microcontroller Clock Control Register (0x03) 0: Output driver is 3-stated. 1: Output driver is enabled. 6—3 — Reserved. Program to 0. 000: Stops clock (clock is restarted on detection of interrupt).

2222 Lucent Technologies Inc.

6.8 Watchdog Timer

counter, the entire chip is reset (including the 80C32).

15.36 MHz 80C32 clock:

Table 16 lists the watchdog timer control register bits. Table 16. WDT: Microcontroller Watchdog Timer Control (0x04) 7W D T E Watchdog Timer Enable. Enables the watchdog timer function. 6:0 WDT[6:0] Watchdog Timer Value. Multiplication selection for the watchdog timer.

Lucent Technologies Inc. 23 Preliminary Data Sheet November 2000 ISDN Network Termination Node (NTN) Device T9000

6.9 On-Circuit Emulation (ONCE) Mode

The external access port pin SLP is used to put the device under the control of an external microcontroller. The ONCE mode is invoked by the following two steps: ■ Pulling SLP and RESET low. ■ Holding SLP low while releasing RESET. Table 5 lists the functions of the microcontroller’s exter- nal access pins during ONCE mode.

6.10 Emulation

When using ONCE mode, some special provisions must be made on the target system to ensure accurate emulation as follows: ■ If the target system’s NTN uses external RAM, a memory decoder must be added to the board to sup- port emulation. This decoder must select the external RAM only during accesses to addresses above the lowest 4K of memory. This is not necessary during normal operation because the NTN disables the RD and WR strobes that are routed to the external mem- ory whenever an access is being made to the inter- nal 4K of RAM. However, during emulation mode, the signals are being driven by the external emulator and will be presented to the external RAM for all external data accesses, including the lowest 4K. This will create contention between the internal 4K of RAM and the lowest 4K of external RAM. As a simple example of required decoding logic, if using an exter- nal 4K RAM, the A12 address line could be inverted and used to drive the RAM’s CS signal. For an exter- nal 8K RAM, the NOR of the A12 and A13 lines could be used to drive CS . For an external 16K RAM, the NOR of A12 through A14 could be used to drive CS, etc. This logic is not required when using the system in normal (nonemulation) mode. ■ If any of the GPIO1.[7:5] pins are being used as inputs to trigger internal timers T2, T1, and T0 (see register GPAF1), these signals must also be routed to the 80C32 emulator’s port pins P1.0, P3.5, and P3.4, respectively, in order to trigger the correspond- ing timers on the emulator. ■ External interrupt sources that normally drive XINT0 and XINT1 should be open-drain drivers to avoid contention with the XINT0 and XINT1 pins during ONCE mode. In normal operation, XINT0 and XINT1 pins on the NTN are inputs with internal pull-ups (thus an external open-drain driver does not require a pull-up). In ONCE mode, the XINT0 and XINT1 pins become open-drain outputs (with internal pull- ups) so that the NTN can drive the internal status of the XINT0 and XINT1 signals onto the corresponding emulator pins. Note that this means that, in ONCE mode, the interrupt service routine (ISR) for INT0 and INT1 will need to be modified to reflect this differ- ence. This is because in normal mode, the microcon- troller will see X|0| or X|1| go high in registers GR0 and GR1, respectively, when an external interrupt occurs. However, in ONCE mode, the occurrence of an external interrupt will change the level on the emulator’s INT0 and INT1 pins, but this change will not show up in the X|0| or X|1| interrupt bits in the NTN. Therefore, the ISR will need to assume that, if no bits in GIR0 (for an XINT0 interrupt) or GIR1 (for an XINT1 interrupt) are set and an interrupt has occurred, then the ISR for the corresponding exter- nal interrupt should be invoked.

6.11 Module I/O

The I/O interface for this module is identical to that doc- umented in the Lucent 80C31/32/51/52 data sheet, with the exception of the ALE signal. ALE is also an input to the 80C32 block. This is required to allow an external microcontroller to access the internal 4 Kbytes address space during ONCE mode. During ONCE mode, there is a direct connection between the external access port signals and their associated signals on the microcontroller interface. For this purpose, a shell was created around the original block. This shell is essentially a set of multiplexers that, during ONCE mode, allows the external port access signals to drive the XDBALE, XDBTI, IOLAD, IOHAD, WR , and RD signals on the internal microcontroller interface.

2424 Lucent Technologies Inc.

6.12 Special Instructions for Using the

6.12.1 Port Configuration

tion register will configure the pin as an input.

6.12.1.1 Ports 0 and 2

regard to the setting of the direction control registers.

6.12.1.2 Port 1

Note that P1.1 is not available on the 80C32 block. input on the NTN, this mode is not allowed.

6.12.1.3 Port 3

All of the pins on port 3 are used by the NTN device. set according to the use of the pins. general external interrupt sources XINT1 and XINT0. must be set to 1 to configure these bits as inputs. 7 and 6 in port 3 direction register are don’t cares. Table 17. Port Direction Registers

6.13 Serial Port Timing

register T2CON, which controls the mode of operation of timer 2. The RCLK/TCLK options are shown in Table 18. Table 18. Standard 80C32 RCLK/TCLK Options TXclock must be drawn from the same source, either timer 1 or timer 2, depending on the value selected for TCLK. Table 19. Lucent 80C32 RCLK/TCLK Options paring Table 18 and Table 19.

• Intel is a registered trademark of Intel Corporation.

6.14 External Program Memory Characteristics

Table 20. External Program Memory Characteristics (Use with Figure 4 through Figure 6.) itance for all other outputs = 80 pF.

6.14 External Program Memory Characteristics (continued)—

Figure 4. External Program Memory Read Cycle Figure 5. External Data Memory Read Cycle

6.14 External Program Memory Characteristics (continued)

Figure 6. External Data Memory Write Cycle

Lucent Technologies Inc. 29 Preliminary Data Sheet November 2000 ISDN Network Termination Node (NTN) Device T9000

7 Transmission Superblock

The transmission superblock (TSB) contains all the modules that are directly involved in the transmission of data to/from the S, U, HDLC, or GCI+ interfaces. It is comprised of the following modules (contained in a box labeled Transmission Superblock in Figure 1). ■ U block—This module provides the NT-mode and LT-mode U-interface function. ■ S block—This module provides the NT-mode S/T-interface function. ■ Data Flow/Activation Control (DFAC)—This module manages the data flow between the U, S, HDLC, and GCI+ interfaces. In addition, it serves as the central control element for activation/deactivation of the S and U blocks, and implements the embedded operation channel (EOC) processing state machine. ■ HDLC—This module provides the HDLC controller function for D-channel access. ■ GCI+—This module provides the GCI+ interface for external components such as codecs.

7.1 U-Interface Block (U Block)

The ISDN U-interface block offers the following features: ■ Conforms to ETSI TS 080 and ANSI T1.601 stan- dards in both LT and NT operation. ■ Meets loop range requirement per the British Tele- com * specification BT RC7355D. ■ Single pulse and ILOSS output modes for test sup- port. ■ Manual/auto activation, manual/auto dying gasp (power status indication), and manual/auto activation of the EOC control. ■ M4 control and status bits incorporate 3x (trinal) bit filtering. The primary interface to this block is provided via the DFAC module (see Section 7.3, Data Flow/Activation Control Module (DFAC)). A bank of registers contained in the DFAC module defines the operation of the U- interface. * British Telecom is a trademark of British Telecommunications plc.

7.2 S/T-Interface Block (S Block)

The ISDN S/T-interface block offers the following fea- tures: ■ Conforms to ITU-T I.430, ETSI 300-012, and ANSI T1.605 standards for the network termination (NT) side of the network. ■ Fixed/adaptive timing modes under microcontrol, or pin control, defaulting to adaptive timing from a reset state. ■ Provides knowledge of the S/T-interface activation state to the microcontroller by supplying INFO-1 and INFO-3 state information. ■ Manual/auto activation, multiframing (S and Q chan- nels), and POTS D-channel contention resolution. ■ Microcontrolled powerdown feature supports a scan mode that looks for activity on the S/T-interface. ■ Supports point-to-point and multipoint arrangement. Data to/from this block is provided by/to the DFAC. A bank of registers contained in the DFAC module defines the operation of the S/T-interface.

3030 Lucent Technologies Inc. Preliminary Data Sheet November 2000ISDN Network Termination Node (NTN) Device T9000

7 Transmission Superblock (continued)

7.3 Data Flow/Activation Control Module

(DFAC) This module provides the following functions: ■ S/T-interface and U-interface activation/deactivation control. ■ U-interface management. — M4 bit filtering. — Automatic/manual EOC channel control. — Register interface. — Activation/deactivation management. ■ S/T-interface management. — Register interface. — Activation/deactivation management. ■ Data flow functions: — Mapping of B1-, B2-, and D-channel data between S/T bus and U bus. — Mapping of D-channel data between the HDLC transmitter module and the U bus. — Mapping of B1- and B2-channel data between the GCI+ interface and the U bus.

7.3.1 EOC State Machine (EOCSM)

EOCSM module processes the downstream EOC. The received EOC data/message is transferred to the microcontroller. The upstream EOC channel may be directly controlled by the microcontroller (DFCF[AUTOEOC = 0]) or automatically generated by the EOCSM as shown in Figure 7.

7.3.2 Automatic EOC (AUTOEOC) Mode

In the automatic EOC (AUTOEOC) mode, the down- stream EOC messages are interpreted and acted upon by the NTN with no need for microcontroller interven- tion. The appropriate upstream response is automati- cally generated. The set of EOC messages supported by the NTN are those defined in ETSI TS 080 and ANSI T1.601, and are shown in Table 21.

7.3.3 Manual EOC Mode

In the manual EOC mode, the microcontroller is responsible for interpreting the downstream EOC mes- sage, taking the appropriate action, and responding correctly in the upstream direction. In both manual and AUTOEOC modes, the NTN stores the most recent downstream EOC contents in registers ESR0 and ESR1. The microcontroller can be inter- rupted on either a single change in the EOC contents (see bit UIR[EOCSC]) or a trinal-checked change in the EOC contents (see bit UIR[EOC3SC]). Actions in response to the standard set of messages shown in Table 21 can be taken by writing to register ECR0[7:4]. The microcontroller writes the upstream EOC response to registers ECR0[3:0] and ECR1[7:0]. The half-super- frame interrupt UIR[RHSF] can be used to determine the correct EOC message timing. All actions are latched, permitting multiple EOC-initi- ated actions to be in effect simultaneously. The transi- tion of transmission system through either receiver reset or full reset states releases all the outstanding EOC-controlled operations, and resets the EOC pro- cessor to return-to-normal.

7.3 Data Flow/Activation Control Module (DFAC) (continued)

7.3.3 Manual EOC Mode (continued)

Table 21. AUTOEOC = 1 Messages (Data/Messages = 1) That Initiate Actions Note: EOC_UP = EOC upstream contents. EOC_DN = EOC downstream contents. Figure 7. Downstream EOC Analysis (AUTOEOC = 1) and Upstream EOC Processing

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7.3.4 Data Flow Control

upstream paths, respectively. never passed to the GCI interfaces. All D-channel packets are passed to the S/T-interface. Figure 8. 2B+D Data Flow Block Diagram ting in the proper direction.

7.5 LT Mode

The T9000 device can also be operated in LT mode.

7.6 DFAC Register Set

Table 22. DFCF: DFAC Configuration Register (0x05) SN1. The U-interface transceiver remains reset during this mode. 0: No effect on device operation. 1: U transmitter sends SN1 tone continuously. tory testing of the U block. This bit should always be programmed to 0. 0: No effect on device operation. 1: U-block simulation reset (nonlatching-value readback will always be 0). 0: No effect on device operation. 1: U block is held in reset (nonlatching-value readback will always be 0). chronize and then a transition to the UOA state occurs. It is recommended that UOADS be programmed to 1. quested. The loopback occurs automatically if AUTOEOC bit is set. Otherwise, bit U2BDLT must be set to 0. data received by the NT is not looped back towards the LT until after ACT = 1 is received from the LT. Prior to this time, 2B+D data toward the LT is all 1s. LT as soon as the 2B+D loopback is enabled. ation). The EOC state machine only responds to the addresses 000 and 111 as valid addresses. 0: EOC state machine disabled. 1: EOC state machine enabled. default state, it is not necessary to write it back to a 0 after writing a 1. 0: No effect on device operation. 1: Reset all circuitry except internal 80C32.

7.6 DFAC Register Set (continued)

Table 23. DFR: Data Flow Register (0x06) assuming that DFR[B2_SEL] = 1 and ECR0[LB2] = 0. assuming that DFR[B1_SEL] = 1 and ECR0[LB1] = 0. and upstream access to the D channel is granted exclusively to the local HDLC controller. 1: Upstream D-channel access is granted exclusively to the HDLC controller. face Module for detailed information. 3-stated during the corresponding time slot. is 3-stated during the corresponding time slot. assuming GPAF1[GPAF2.2] = 1). 2 B2_SEL U-Interface B2-Channel Source/Destination. 0: U-interface B2 channel to/from S/T-interface. 1: U-interface B2 channel to/from GCI+ interface (or microcontroller if U_FORCE_B2UP is set). 1 B1_SEL U-Interface B1-Channel Source/Destination. 0: U-interface B1 channel to/from S/T-interface. 1: U-interface B1 channel to/from GCI+ interface (or microcontroller if U_FORCE_B1UP is set).

Table 24. UCR0: U-Interface Control Register #0 (0x07) 7 NTM_n NT Test Mode. Controls upstream U-interface overhead bit NTM. 0: NTM = 0, Indicates the NT is in test mode. 1: NTM = 1, Normal operation. the S/T reference point. Otherwise, it is set to 0. 0: SAI follows activity on S/T-interface per ETR 080. 1: Forces SAI = 1 on the U-interface. becomes the UOA (U-only-activation) bit. This bit needs to be set to 1 to allow S/T activation at the NT. 0: No effect on device operation. 1: Forces U-block data transparency. control of the upstream ACT bit (via the ACTUP bit, below). 1: ACT bit follows ACTUP bit (see ACTUP below). this bit controls the downstream ACT bit (via the ACTDN bit, described below). 0: Downstream ACT bit is zero. 1: Forces the value of ACTDN bit (described below) to be transferred downstream. upstream U-interface ACT bit. 0: Forces upstream ACT bit = 0. 1: Forces upstream ACT bit = 1. state of the downstream U-interface ACT bit. 0: Forces downstream ACT bit = 0. 1: Forces downstream ACT bit = 1.

Table 24. UCR0: U-Interface Control Register #0 (0x07) (continued) Table 25. UCR1: U-Interface Control Register #1 (0x08) attempt, this bit is internally cleared to 0, automatically. 0: No effect on device operation. 1: Attempt one U activation. 7R 6 4 T Transmit Reserved Bit. Controls upstream U-interface overhead bit R64. 6R 2 5 T Transmit Reserved Bit. Controls upstream U-interface overhead bit R25. 5—4 R[16:15]T Transmit Reserved Bits. Controls upstream U-interface overhead bits R16 and R15. loopback takes place when the ULLBK bit (see below) is asserted. of the U block. Line need not be disconnected during this operation. so that the device can detect the echo as received data and synchronize to it. 0: No effect on device operation. 1: U-interface local loopback. pulses is controlled by USPMAG (see above). 0: No effect on device operation. 1: Send single pulses on the U-interface.

Table 26. USR0: U-Interface Status Register #0 (0x09) Table 27. USR1: U-Interface Status Register #1 (0x0A) 7A I B _ n Alarm Indication Bit. Filtered (3x) version of downstream U-interface overhead bit AIB. U-interface received superframe at the far end. 0: CRC error in most recent far-end U superframe. 1: No CRC error detected at far end. U-interface received superframe. 0: CRC error in most recent received U superframe. 1: No CRC error detected in most recent received U superframe. 2 OOF_n Out of Frame. Indicates whether synchronization has been achieved on the U-interface. 0: U-interface out of frame. 1: U-interface is synchronized (SWs and ISWs are being properly detected). 1 XACT U-Transceiver Active. and line driver is in a high-impedance power-saving mode. 1: Transceiver starting up or active. 2R 2 5 R Receive U Bit. Filtered (3x) version of downstream U-interface overhead bit R25.

Table 28. ECR0: EOC Control Register 0—Command and Address (0x0B) (see ECCRC bit in register ESR0). 0: CRC is generated correctly. ELBK2 bit in register ESR0). 1: D-channel transparent loopback from U-interface receiver to transmitter. (see ELBK2 and ELB2 bits in register ESR0). 1: B2-channel transparent loopback from U-interface receiver to transmitter. (see ELBK2 and ELB1 bits in register ESR0). 1: B1-channel transparent loopback from U-interface receiver to transmitter. data/message indicator when in manual EOC mode. It has no effect when in AUTOEOC mode. I1T is the first bit transmitted.

Table 29. ECR1: EOC Control Register 1—Message (0x0C) Table 30. ESR0: EOC Status Register 0—Command and Address (0x0D) Table 31. ESR1: EOC Status Register 1— Message (0x0E) monitor the current output of the EOCSM. current output of the EOCSM. valid in both auto and manual EOC modes. data/message bit and is valid in both auto and manual EOC modes. message or data and are valid in both auto and manual EOC modes.

Table 32. SCR0: S-Interface Control Register #0 (0x0F) 7—6 — Reserved. Program to 0. 1: Allows S/T activation independent of the U-interface state. order for this bit to have any effect, the S/T-interface must be enabled. 1: Forces S block to transmit INFO4. activation attempts will be recognized by the device. from 10 µs to 42 µs, but the differential delay between various TEs is less than 2 µs. short passive bus, where the round-trip delay variations are 10 µs to 14 µs. MFR0(3:0) are forced to 1 and MFR1(3:0) are forced to 0 when multiframing is disabled. 0: Disable multiframing controller. 1: Enable multiframing controller. 1S T _ E S/T-Interface Enable. This signal enables the S/T-interface. 0: S/T-interface is powered down and disabled. 1: S/T-interface is enabled and can respond to activation attempts. in the same manner as the external RESET pin. 1: Reset S/T-interface (nonlatching—this bit clears itself and will always be read back as 0).

Table 33. SCR1: S-Interface Control Register #1 (0x10) 7—5 — Reserved. Program to 0. 4 RLB_D S/T Remote Loopback—D Channel. 1: D-channel data received at the S/T-interface is transmitted back to the TE. 3R L B _ B 2 S/T Remote Loopback—B2 Channel. 1: B2-channel data received at the S/T-interface is transmitted back to the TE. 2R L B _ B 1 S/T Remote Loopback—B1 Channel. 1: B1-channel data received at the S/T-interface is transmitted back to the TE. vation is requested. It will force deactivation of the S-interface. 1: Force deactivation of S/T-interface.

Table 34. SSR: S-Interface Status Register (0x11) error-free frame. Note that bit SIR[FSERRL] is a latched version of this signal. 4R X I N F O 3 Receiving INFO3. This bit tracks the reception of INFO3 on the S/T-interface. 3R X I N F O 1 Receiving INFO1. This bit tracks the reception of INFO1 on the S/T-interface. 000: S/T-interface disabled. Sending INFO0. (ACT bit = 1) and is receiving INFO0. 100: (I.430 G4 State) pending deactivation. S/T-interface is sending INFO0. but is required for NT1 implementation.

Table 35. MFR0: Multiframe Register, Q-Channel Data (0x12) Table 36. MFR1: Multiframe Register, S-Subchannel Data (0x13) 7—4 — Reserved. Program to 0. notify the microcontroller that this register is ready to accept a new set of S-subchannel data.

Table 37. UIR: U-Interface Interrupt Register (0x14) to 0 when the register is read. face superframe, and signifies that a new group of U-overhead bits is available. the response data to registers ECR0 and ECR1 before it is transmitted. ues are available in register USR0. (found in register USR1) change state: R15R, R16R, R25R, R34R, R44R, R54R, R64R. is different from the previous EOC message (no trinal-checking is performed). and is logically part of the group of bits ECCRC, ELBK2, ELB2, ELB1 found in ESR0.

Table 38. UIE: U-Interface Interrupt Enable (0x15) This register contains enable bits for the interrupts in register UIR. 7R S F E RSF Interrupt Enable. 6 RHSFE RHSF Interrupt Enable. 5 BERRE BERR Interrupt Enable. 4A C T S C E ACTSC Interrupt Enable. 3 OUSCE OUSC Interrupt Enable. 2E O C 3 S C E EOC3SC Interrupt Enable. 1E O C S C E EOCSC Interrupt Enable.

Table 39. SIR: S-Interface Interrupt Register (0x16) cleared to 0 when the register is read. Table 40. SIE: S-Interface Interrupt Enable Register (0x17) This register contains enable bits for the interrupts in register SIR. RXINFO3, RXINFO1, and ASI[2:0] bits in register SSR changes state. has been received and is available in register MFR0. 7—4 — Reserved. Program to 0. 3S S C E SSC Interrupt Enable. 2 FSERRLE FSERRL Interrupt Enable. 1Q S C E QSC Interrupt Enable. 0 SSRDYE SSRDY Interrupt Enable.

8 Device Operation Control

8.1 Device Operation Register

Table 41. DOCR: Device Operation Control Register (0x50)

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Table 42. B1UP: B1-Channel Upstream Data from GCI to U-Interface (0x51) not initiate U-only activation when TE-initiated activation is being tested. feature on the S/T-interface. It is recommended that this bit be programmed to 0. 0: Backswing suppression enabled. 1: Backswing suppression not used. 5—4 — Reserved. Program to 0. of the GPDIR2 value) for the 8 kHz MTC signal. 2—0 — Reserved. Program to 0. wants to be transferred on the upstream B1 channel from GCI to the U-interface.

8 Device Operation Control (continued)

8.1 Device Operation Register (continued)

Table 43. B2UP: B2-Channel Upstream Data from GCI to U-Interface (0x52) Table 44. B1DN: B1-Channel Downstream Data from U-Interface to GCI (0x53) Table 45. B2DN: B2-Channel Downstream Data from U-Interface to GCI (0x54) wants to be transferred on the upstream B2 channel from GCI to the U-interface. user wants to be transferred on the downstream B1 channel from GCI to the U-interface. user wants to be transferred on the downstream B2 channel from GCI to the U-interface.

Table 46. Reserved 1: Reserved Register for Internal Use (0x55) Table 47. Reserved 2: Reserved Register for Internal Use (0x56) Table 48. Reserved 3: Reserved Register for Internal Use (0x57) 7—0 — Reserved Register for Internal Use. 7—6 — Reserved for Internal Use. four U superframes of dea = 0 and then switch the transceiver off. When the NTN device is in NT mode, this bit has no effect. this bit is sent as the R54 reserved bit. When the NTN device is in NT mode, this bit has no effect. (and loop3 reversed) with +2.5 dB noise level. 2—0 — Reserved for Internal Use. 7—0 — Reserved Register for Internal Use.

Table 49. Reserved 4: Reserved Register for Internal Use (0x58) Table 50. Reserved 5: Reserved Register for Internal Use (0x59) Table 51. Reserved 6: Reserved Register for Internal Use (0x5A) Table 52. Reserved 7: Reserved Register for Internal Use (0x5B) 7—0 — Reserved for Internal Use. 7—0 — Reserved for Internal Use. 7—0 — Reserved for Internal Use. 7—0 — Reserved for Internal Use.

Table 53. Reserved 8: Reserved Register for Internal Use (0x5C) Table 54. Reserved 9: Reserved Register for Internal Use (0x5D) 7—0 — Reserved for Internal Use. 7—0 — Reserved for Internal Use.

5252 Lucent Technologies Inc. Preliminary Data Sheet November 2000ISDN Network Termination Node (NTN) Device T9000

9 HDLC with FIFO Module

The HDLC (high-level data link) module supports stan- dard HDLC framing and deframing functionality on the D channel of the NTN. Two 64 x 9 register files are used to implement transmitter and receiver FIFOs, and address recognition is performed on the incoming frames. Data/parameter exchange between the microcontroller and the HDLC module is done by reading/writing a set of registers. Interrupts are used to request microcon- troller intervention. Data to be framed and transmitted is written into the FIFO by the microcontroller via registers HTX and HTXL. All bytes of a packet, except the last one, are written to HTX. The last byte is written to HTXL. HTX and HTXL occupy the same physical space (the trans- mit FIFO). The microcontroller reads data from the receive FIFO via register HRX.

9.1 HDLC Transmitter

The HDLC transmitter automatically frames user data packets (UDPs) by inserting starting and closing flags, inserting (if requested) the frame check sequence (cal- culated according to the ITU-16 polynomial cyclic redundancy check [CRC]) and performing zero-bit insertion on the user data and frame check sequence (FCS). Packets to be framed are transferred by the microcon- troller into the transmitter FIFO by writing to the HTX and HTXL registers. Multiple HDLC packets can be written into the transmitter FIFO. For all bytes of a packet, except the last one, the microcontroller should write the data byte into the HTX register. The last byte of a packet is written into the HTXL register. Figure 9 shows the transmitter FIFO contents in the case where the microcontroller has written two complete 9-byte packets into the transmitter FIFO and partially written a third packet. For packets #1 and #2, bytes 0 to 7 are written to register HTX and byte 8 is written to register HTXL. The HDLC transmitter FIFO manager indicates the number of free bytes currently in the transmitter FIFO via read-only register HTSA. At the snapshot in time represented by the figure, the HDLC transmitter is ready to accept byte P3-B2. Also, the microcontroller can write up to 48 bytes before the FIFO is filled, because the first four bytes of the first packet have been transmitted.

9.1.1 HDLC Transmitter Initialization

On powerup, the HDLC transmitter is initialized auto- matically. After powerup, whenever there is any change to the HTCF[MANCRC] or HTCF[TXMODE] configura- tion bits, the bit HTCF[TX_INIT] needs to be set to 1 to reinitialize the HDLC transmitter. Once the initialization is completed, the HTCF[TX_INIT] bit returns to 0. During initialization, register bit HTCF[MANCRC] is sampled. If it is zero (the default), the FCS will be cal- culated automatically, according to the ITU 16 polyno- mial cyclic redundancy check (CRC-16) and inserted at the end of the user data. If HTCF[MANCRC] = 1, no FCS automatic insertion is done; it is the responsibility of the user software to perform the FCS insertion if desired. This feature may be useful in cases where it is necessary to use an FCS other than that in the ITU standard. Users may abort the current frame transmission by asserting register bit HTCF[ABRT_RQ]. When this occurs, the transmitter FIFO manager will flush the contents of the transmitter FIFO. This bit automatically returns to 0 once the abort sequence has been initi- ated. Register bit HTCF[IDL] determines the idle pattern to be sent by the HDLC transmitter when there are no packets to be framed. If set to 0, flags (01111110) will be inserted between the closing flag of a frame and the opening flag of the next frame. If set to 1, idles (11111111) will be inserted. In certain applications where buffer overloading at the far-end receiver can occur, there may be a requirement to add a minimum number of extra interframe fill bytes at the end of each frame. HTCF[FCNT(2:0)] deter- mines the number of fill bytes to be sent at the end of a packet. For FCNT(2:0) = n (where n > 0), n – 1 inter- frame flags are padded after the closing flag of one frame and the opening flag of the next frame. For the case of n = 0, the closing flag of one frame acts as the opening flag of the next frame (i.e., back-to-back frames are supported). The HTTH[TFAE] register bits determine the threshold that the queue manager uses to control assertion of the HIR[TTHR] interrupt register bit. This bit is asserted when, as a consequence of a read of the transmitter FIFO by the HDLC framer, the available space of the FIFO exceeds the number in the HTTH[TFAE]. Interrupt register bit HIR[TFC] is asserted at the end of the closing flag of a transmitted frame.

9 HDLC with FIFO Module (continued)

9.1 HDLC Transmitter (continued)

9.1.1 HDLC Transmitter Initialization (continued)

Note: RPTR = read pointer, WPTR = write pointer. Figure 9. HDLC Transmitter FIFO

9.2 HDLC Transmitter D-Channel Access

received on the S/T-interface). ■ SCR0[FACT] register bit is set to 1. ■ DFR[FORCE_D] register bit is set to 1. tive ones are received on the upstream S/T D channel. level (i.e., 8/9 or 10/11) is automatically managed. protocol, HTCF[IDL] should be set to 1.

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9.3 HDLC Receiver

9.3.1 HDLC Receiver Initialization

HRCF[RX_INIT] bit automatically returns to 0. including its FCS, will be stored in the receiver FIFO. frame-complete, frame-error, and frame-abort. (see section 9.3.1.1 Overrun Condition ). ITU CRC-16 polynomial) did not match. is the case, CBIT = 111. Otherwise, CBIT ≠ 111. rectly received frames will have 47h as the status byte. Bit 3 is reserved and is set to 0. Figure 10. HDLC Receiver Status Word rently stored into the FIFO. HRCF[DROPCRC] = 1) are automatically rejected.

9.3 HDLC Receiver (continued)

9.3.1 HDLC Receiver Initialization (continued)

Figure 11 represents a sequence of snapshots in time of the receiver FIFO. In Figure 11 (a), the FIFO is empty, so HRDA = 00h. indicates that the status byte is the ninth byte in the FIFO. been received, and some bytes of the first packet have been read by the microcontroller. packet, as shown in Figure 11 (f). Figure 11. HDLC Receiver FIFO Snapshot Sequence

5656 Lucent Technologies Inc. Preliminary Data Sheet November 2000ISDN Network Termination Node (NTN) Device T9000 Up to 16 status bytes can be stored in the receiver FIFO at a given time. Once this condition is reached, it is indicated by assertion of the HIR[RSTF] interrupt register bit and the FIFO is considered full. In the worst case, the microcontroller has approximately 2 ms from the time HIR[RSTF] is asserted to read data from the FIFO and avoid overrun errors (an overrun error is indi- cated by assertion of the HIR[ROVR] interrupt bit). When a status word with its EOF bit set is loaded into the FIFO, interrupt bit HIR[REOF] is set. Similarly, when a status word with its ABRT bit set is loaded into the FIFO, interrupt bit HIR[RABT] is set. When the receive FIFO is filled at or above the level programmed in register HRTH, an interrupt is asserted by enabling the bit HIR[RTHR]. The interrupt should clear when the interrupt status register is read, and should not be asserted again until the receive FIFO is emptied to the point that more spaces remain in the FIFO than the value programmed in the HRTH register, and then enough bytes are received to again cause the delay FIFO fill level to reach the HRTH register value.

9.3.1.1 Overrun Condition

An overrun condition occurs when the receiver is unable to download a processed byte into the FIFO because the FIFO is full or contains 16 status words. Interrupt bit HIR[ROVR] is set when an overrun occurs. If the overrun condition occurs during the reception of a packet with a matching address field, the current frame will be closed and its status word’s OVR bit will be set. The remainder of the frame will be dropped even if the overrun condition has been removed. The receiver must be reinitialized after the overrun condition, before new packets can be properly received.

9.4 Address Recognition

A very flexible address comparison scheme is imple- mented in the NTN device. Eight registers are used for storing SAPI or TEI patterns for comparison with the incoming address. The registers are grouped logically into the pairs HSM0/HTM0, HSM1/HTM1, HSM2/ HTM2, HSM3/HTM3 to define a total of four DLCI (data link connection identifier) address matching patterns. If HSMOD and HTMOD are programmed for address matching, only frames with an address field matching one of the programmed address values (or special addresses) are transferred to the receive FIFO. All oth- ers are ignored. If an address match occurs, the address field is also loaded into the HDLC receive FIFO. The address modifier registers, HSMOD and HTMOD, are used to control the address recognition modes and can be used to extend the DLCIs defined in the four HSMx/HTMx register pairs. Figure 12 shows an exam- ple of this for the SAPI0/TEI0 pair (i.e., bits SAPI0M[1:0] and TEI0M[1:0] in HSMOD and HTMOD, respectively). Consider the default setting of TEI0M = 00 and SAPI0M = 00 on powerup. In this case, TEIM0 = 00 causes rejection of all packets for a given DLCI pair, independent of the state of SAPI0M. This means that on powerup, the HDLC receiver is disabled and will not receive any packets. Now consider the effect of setting TEI0M to the other three possible values while leaving SAPI0M set to 00. Setting TEI0M = 01 enables the recognition of the DLCI0 address programmed in the HSM0/HTM0 pair. Setting TEI0M = 10 extends the definition of DLCI0 to include the broadcast TEI value, 127. Setting TEI0M = 11 extends the definition of DLCI0 to include all TEI val- ues. In a similar way, setting SAPI0M to the values 01, 10, or 11 will extend the existing definition of DLCI0 to include SAPI0 = 0, SAPI = 63, or all SAPI values, respectively. Note, then, that when SAPI0M/TEI0M = 1111, any packet more than 2 bytes in length (4 bytes if HRCF[DROPCRC] = 1) will be downloaded to the receiver FIFO, regardless of its address. This effec- tively disables address recognition for all four DLCI pairs, since the values programmed into the other three pairs become irrelevant in this case. One further level of address recognition control is avail- able via the HSCR register, which provides a means for enabling/disabling comparison of the command response (C/R) bit for each SAPI. When HSCR[SxCRE] = 0, no comparison is done on the C/R bit of the SAPI defined by HSMx register. When HSCR[SXCRE] = 1, the C/R bit is included in compari- son. However, for extended SAPI values of 0 or 63 (HSMOD[SAPIxM] = 01 or = 10), no comparison is ever done on the C/R bit. In the transmit direction, no automatic address inser- tion is performed.

9.4 Address Recognition (continued)

Figure 12. DLCI Extension and Function of SAPI0M-TEI0M Bits

0 TEI0

63 TEI0

9.5 HDLC Register Set

Table 55. HTCF: HDLC Transmitter Configuration Register (0x18) causes sharing of the closing flag of one frame with the opening flag of the next. 000: Back-to-back frames (closing/opening flag is shared). 001: No fill bytes are inserted. DFR[FORCE_D] = 1. See DFR[FORCE_D] description. by setting DFR[FORCE_D] = 1. See DFR[FORCE_D] description. transparent mode. The transmitter must be reinitialized after changing this bit. automatically returns to 0 once the abort sequence has been set. any of the other transmitter registers.

9.5 HDLC Register Set (continued)

Table 56. HRCF: HDLC Receiver Configuration Register (0x19) 7—4 — Reserved. Program to 0. mode. The receiver must be reinitialized after changing this bit. vides the byte alignment pattern. The receiver must be reinitialized after changing this bit. 0: Byte alignment mechanism is disabled. 1: Byte alignment mechanism is enabled. loaded into the receive FIFO. The receiver must be reinitialized after changing this bit. 0: Load 2 CRC bytes into receive FIFO. 1: Drop CRC (CRC bytes are not loaded into the receive FIFO). 0 RX_INIT HDLC Receiver Initialize. Writing this bit to 1 will cause initialization of the HDLC receiver. DROPCRC after initialization is disregarded.

Table 57. HTTH: HDLC Transmit FIFO Threshold (0x1A) Table 58. HRTH: HDLC Receive FIFO Threshold (0x1B) nel in order to grant D-channel access to the HDLC transmitter. 0: Priority class 2 (data) as defined in ITU-I.430. 1: Priority class 1 (signaling) as defined in ITU-I.430. Within a class, priority levels are automatically managed. bytes are transmitted to again cause the FIFO empty level to exceed the TFAE[5:0] value. 7—6 — Reserved. Program to 0. received to again cause the FIFO fill level to exceed the RFAF[5:0] value.

Table 59. HTSA: HDLC Transmit FIFO Space Available (0x1C) Table 60. HRDA: HDLC Receive FIFO Data Available (0x1D) Table 61. HTX: HDLC Transmit Data (0x1E) there is a status word in the receive FIFO.

Table 62. HTXL: HDLC Transmit Data Last Byte (0x1F) Table 63. HRX: HDLC Receive Data (0x20) Table 64. HSCR: HDLC SAPI C/R Bit Mask (0x21) 7—0 RXD[7:0] Received Data/Status. The content of the FIFO is read when addressing this register. The first received bit is the least significant bit of this byte. 7—4 — Reserved. Program to 0. 3 S3CRE SAPI3 Command/Response Bit Comparison Enable. 0: SAPI3 C/R bit is ignored. 1: SAPI3 comparison includes C/R bit (HSM3.1). 2 S2CRE SAPI2 Command/Response Bit Comparison Enable. 0: SAPI2 C/R bit is ignored. 1: SAPI2 comparison includes C/R bit (HSM2.1). 1 S1CRE SAPI1 Command/Response Bit Comparison Enable. 0: SAPI1 C/R bit is ignored. 1: SAPI1 comparison includes C/R bit (HSM1.1). 0 S0CRE SAPI0 Command/Response Bit Comparison Enable. 0: SAPI0 C/R bit is ignored. 1: SAPI0 comparison includes C/R bit (HSM0.1).

Table 65. HSM0: HDLC SAPI Match Pattern 0 (0x22) Table 66. HTM0: HDLC TEI Match Pattern 0 (0x23) Table 67. HSM1: HDLC SAPI Match Pattern 1 (0x24) pattern for SAPI. See Section 9.4, Address Recognition for details. alignment pattern if HRCF[BAE] = 1. 1C / R 0 Command/Response Bit. Set according to the Q.920 standard. alignment pattern if HRCF[BAE] = 1. alignment pattern if HRCF[BAE] = 1. 7—1 TEI0[6:0] Match Pattern 0 for TEI. See Section 9.4, Address Recognition for details. tern for SAPI. See Section 9.4, Address Recognition for details. 1C / R 1 Command/Response Bit. Set according to the Q.920 standard.

Table 68. HTM1: HDLC TEI Match Pattern 1 (0x25) Table 69. HSM2: HDLC SAPI Match Pattern 2 (0x26) Table 70. HTM2: HDLC TEI Match Pattern 2 (0x27) Table 71. HSM3: HDLC SAPI Match Pattern 3 (0x28) 7—1 TEI1[6:0] Match Pattern 1 for TEI. See Section 9.4, Address Recognition for details. pattern for SAPI. See Section 9.4, Address Recognition for details. 1C / R 2 Command/Response Bit. Set according to the Q.920 standard. 7—1 TEI2[6:0] Match Pattern 2 for TEI. See Section 9.4, Address Recognition for details. pattern for SAPI. See Section 9.4, Address Recognition for details. 1C / R 3 Command/Response Bit. Set according to the Q.920 standard.

Table 72. HTM3: HDLC TEI Match Pattern 3 (0x29) Table 73. HSMOD: HDLC SAPI Modifier Register (0x2A) See Section 9.4, Address Recognition for details on the function of this register. 7—1 TEI3(6—0) Match Pattern 3 for TEI. See Section 9.4, Address Recognition for details. 7—6 SAPI3M[1:0] SAPI3 Modifier. This field indicates the value(s) for the SAPI of DLCI3. 01: SAPI3 = value of HSM3 or 0. 10: SAPI3 = value of HSM3 or 63. 5—4 SAPI2M[1:0] SAPI2 Modifier. This field indicates the value(s) for the SAPI of the DLCI2. 01: SAPI2 = value of HSM2 or 0. 10: SAPI2 = value of HSM2 or 63. 3—2 SAPI1M[1:0] SAPI1 Modifier. This field indicates the value(s) for the SAPI of the DLCI1. 01: SAPI1 = value of HSM1 or 0. 10: SAPI1 = value of HSM1 or 63. 1—0 SAPI0M[1:0] SAPI0 Modifier. This field indicates the value(s) for the SAPI of the DLCI0. 01: SAPI0 = value of HSM0 or 0. 10: SAPI0 = value of HSM0 or 63.

Table 74. HTMOD: HDLC TEI Modifier Register (0x2B) See Section 9.4, Address Recognition for details on the function of this register. 7—6 TEI3M[1:0] TEI3 Modifier. This field indicates the value(s) for the TEI of DLCI3. 10: TEI3 = value of HTM3 or broadcast TEI (127). 5—4 TEI2M[1:0] TEI2 Modifier. This field indicates the value(s) for the TEI of DLCI2. 10: TEI2 = value of HTM2 or broadcast TEI (127). 3—2 TEI1M[1:0] TEI1 Modifier. This field indicates the value(s) for the TEI of DLCI1. 10: TEI1 = value of HTM1 or broadcast TEI (127). 1—0 TEI0M[1:0] TEI0 Modifier. This field indicates the value(s) for the TEI of DLCI0. 10: TEI0 = value of HTM0 or broadcast TEI (127).

Table 75. HIR: HDLC Interrupt Register (0x2C) to 0 when the register is read. status byte is written to the receive FIFO. to transmit a byte from an empty transmit FIFO. successfully transmitted a frame. empty threshold is exceeded.

Table 76. HIE: HDLC Interrupt Enable 15 (0x2D) 7R S T F E RSTFE Interrupt Enable. 6R O V R E ROVR Interrupt Enable. 5R E O F E REOF Interrupt Enable. 4R A B T E RABT Interrupt Enable. 3 RTHRE RTHR Interrupt Enable. 2 TUNDRE TUNDR Interrupt Enable. 1 TFCE TFC Interrupt Enable. 0 TTHRE TTHR Interrupt Enable.

10 GCI+ Interface Module

Siemens, National*, and Motorola†). signal to be available for other uses in most cases. Table 77. GCI+ Interface Signals ■ GCI-NT mode (GCCF[GMODE(1:0)] = 00). ■ GCI-TE mode (GCCF[GMODE(1:0)] = 01). ■ TDM mode (GCCF[GMODE(1:0)] = 1x).

10.1 TDM Mode (GCCF, GMODE[1:0] = 1x)

GCI+ interface when programmed in TDM mode. occurs once per bit time and is a divide-by-two version of the DCL signal. BCLK is always 0 in single clock mode.

• National is a registered trademark of National Semiconductor Corporation.

† Motorola is a registered trademark of Motorola, Inc. FSC FS1 GPIO2.2 O Reference frame sync (marks start of frame). PFS1 GPIO2.2 FS1 O Programmable frame sync 1 (marks location of B1 channel). PFS2 FS2 FS2 O Programmable frame sync 2 (marks location of B2 channel). DCL DCL DCL O Data clock (defined with GRATE bits). BCLK GPIO2.1 GPIO2.1 O Bit clock (only active during 2 times data clock mode). DU DU DU I Data upstream (U transmit data). DD DD DD O Data downstream (U receive data).

10 GCI+ Interface Module (continued)

10.1 TDM Mode (GCCF, GMODE[1:0] = 1x) (continued)

Table 78. TDM Data Rate and Clock Options slots on the TDM highway and are output on the FS1 and FS2 pins, respectively (see Table 78). ments) by programming the GCOF1 and GCOF2 registers with the desired offset. and PFS2, respectively. This ordering can be switched by setting the DFAC[BSWAP] register bit to 1. prior to the first data bit of the corresponding time slot.

1. Only present if programmed on GPAF1 register.
2. Not outputs. Shown only for reference.

A: PFSDEL = 0 and PFSPE = 0. B: PFSDEL = 0 and PFSPE = 1. C: PFSDEL = 1 and PFSPE = 0. D: PFSDEL = 1 and PFSPE = 1. Figure 13. GCI+ Interface, TDM Mode Timing, Double Clock Mode: GCCF[CKMODE] = 0,

1. Only present if programmed on GPAF1 register.
2. Not outputs. Shown only for reference.

A: PFSDEL = 0 and PFSPE = 0. B: PFSDEL = 0 and PFSPE = 1. C: PFSDEL = 1 and PFSPE = 0. D: PFSDEL = 1 and PFSPE = 1. Figure 14. GCI+ Interface, TDM Mode Timing, Single Clock Mode: GCCF[CKMODE] = 1, GCCF[GMODE(1)] = 1 The figure below shows an example of how a codec with a TDM interface would be connected to an NTN device. The codec shown is the Lucent T8503 dual codec. The correct register settings are shown in the NTN block. Figure 15. NTN/T8503 Glueless TDM Interconnection

Lucent Technologies Inc. 73 Preliminary Data Sheet November 2000 ISDN Network Termination Node (NTN) Device T9000

10.2 GCI Modes (GCCF[GMODE(1:0)] = 0x)

GCI mode is for use with codecs having a GCI inter- face. Two GCI modes are supported by the NTN device: ■ GCI-NT mode with a GCI frame structure of only one GCI channel. ■ GCI-SCIT mode with a GCI frame structure of three GCI channels. In both modes, the circuit operates as a GCI master device, i.e., the DCL output pin provides the GCI clock signal (512 kHz or 1536 kHz). A BCLK signal is avail- able on the GPIO2.1 pin when GPAF1[GPAF2.1] = 1. BCLK occurs once per bit time and is a divide-by-two version of the DCL signal. The FS1 output pin provides the frame synchronization clock (FSC) signal as defined by the GCI standard (see Figure 17). The internal PFS1 and PFS2 signals mark the location of the B1 and B2 time slots on the TDM highway. PFS2 is output on the FS2 pin (see Table 77). PFS1 can be made available on the GPIO2.2 pin by setting GPAF1[GPAF2.2] = 1. The PFS1 and PFS2 (programmable frame sync) sig- nals may be programmed to be a pulse (duration of one bit period, sometimes referred to as short frame sync) or envelope (duration of one time slot, some- times referred to as long frame sync). Register bit GCCF[PFSPE] sets the short or long frame sync mode. The U-interface B1 and B2 channels are normally transferred to/from the codec on the time slots marked by PFS1 and PFS2, respectively. This ordering can be switched by setting the DFAC[BSWAP] register bit to 1. Register bit GCCF[PFSDEL] controls the relative delay between PFSx (x = 1 or x = 2) and the first data bit of the time slot associated with PFSx. When GCCF[PFSDEL] = 0, the PFSx rising edge is coinci- dent with the start of the first data bit of the correspond- ing time slot. When GCCF[PFSDEL] = 1, the PFSx rising edge occurs one data bit prior to the first data bit of the corresponding time slot. Generation of the PFSx signals and data transfer to/from the corresponding time slots may be disabled by setting DFR[PFSx_ACT] = 0.

10.3 GCI-NT Mode (GCCF[GMODE(1:0)] = 00)

Figure 16 shows the frame structure for the GCI-NT mode. The DCL clock rate is automatically set to 512 kHz, overriding the value defined by GCCF[GRATE(1:0)]. In addition, a powerdown mode is available in which DCL is stopped (see Section 10.5, GCI+ Powerdown Mode). The data rate in GCI-NT mode is automatically set to 256 kHz, overriding the value defined by GCCF[CKMODE]. A total of four 8-bit time slots are contained in each frame. Time slots 0 and 1 carry user data, time slot 2 is the GCI monitor (MON) channel, and time slot 3 is the GCI signaling and control chan- nel. The FS1 output pin provides the frame synchronization clock (FSC) as defined by the GCI standard. It becomes active with the rising edge of DCL at the start of time slot 0 and is turned off one-half of a DCL period prior to the start of time slot 1. In this mode, the NTN device: ■ May transfer upstream/downstream data on time- slots 0 and 1. ■ Manages the MON channel’s operation, mainte- nance, and data transfer (see Section 10.3.2, Moni- tor Message Transfer for more details). ■ Provides control of the C/I subchannel (see Section 10.4, C/I Message Transfer for more details). Register bit GCOF1[OFF10] controls the time slots to which PFS1 and PFS2 are associated. If GCOF1[OFF10] = 0 PFS1 occurs during time slot 0 (GCI-B1 channel) and PFS2 occurs during time slot 1 (GCI-B2 channel). If GCOF1[OFF10] = 1 the associa- tion is reversed, PFS1 occurs during time slot 1 (GCI-B2 channel) and the PFS2 occurs during time slot 0 (GCI-B1 channel). Note that the GCOF1(OFF1[4:1]) bits are ignored in GCI-NT mode, as is the entire GCOF2 register.

10.3 GCI-NT Mode (GCCF[GMODE(1:0)] = 00) (continued)

1. Not an output. Shown only for reference.

Note: GCCF[GMODE] = 00 (GCI-NT); DCL = 512 kHz; data rate = 256 kHz. Figure 16. GCI-NT Frame Structure Figure 17 shows the generation of PFS1/PFS2 signals, assuming GCOF1[OFF10] = 0.

1. Only present if programmed on GPAF1 register.
2. Not outputs. Shown only for reference.

Figure 17. GCI-NT Timing Diagram

Lucent Technologies Inc. 75 Preliminary Data Sheet November 2000 ISDN Network Termination Node (NTN) Device T9000 (continued)

10.3.1 GCI-SCIT Mode (GCCF, GMODE[1:0] = 01)

Figure 18 shows the frame structure for GCI-SCIT (Special Circuit Interface-T) mode, also known as GCI- TE mode. In this mode, the DCL clock rate is automati- cally set to 1536 kHz, overriding the value defined by GCCF[GRATE]. In addition, a powerdown mode is available in which DCL is stopped (see Section 10.5, GCI+ Powerdown Mode). The data rate in GCI-SCIT mode is automatically set to 768 kHz, ignoring the value defined by GCCF[CKMODE]. A total of twelve 8-bit time slots are contained in each frame comprising three GCI chan- nels of four time slots each. Time slots 0 and 1 carry user data, time slot 2 is the GCI monitor (MON) chan- nel, and time slot 3 is the GCI signaling and control channel. The FS1 output pin provides the frame synchronization clock (FSC) as defined by the GCI standard. It becomes active with the rising edge of DCL at the start of time slot 0 and is turned off one-half of a DCL period prior to the start of time slot 1. In this mode, the NTN device: ■ May transfer upstream/downstream data on time slots 0 (B1), 1 (B2), 4 (IC1), and 5 (IC2). ■ Does not provide control over MON-0 (time slot 2) because layer-1 transceiver control is done through the internal microcontroller bus. The downstream monitor code will be FFh. Downstream A and E bits for GCI channel 0 will be set to 1. Upstream data in time slot 2 will be ignored. ■ Does not support external layer-2 devices. This implies: — No data transfer is provided over GCI-D channel (time slot 3, first and second data bits) as the internal HDLC controller and microcontroller pro- vide this service. Downstream data during these 2 bits will be set to 1. — There is no need to support GCI subchannel C/I control on channel 0 (C/I-0). The downstream C/I code will be Fh. The upstream C/I code will be ignored. — There is no need for terminal IC (TIC) subchannel control. The downstream TIC code will be Fh. The upstream TIC code will be ignored. ■ Automatically manages the MON-1 channel’s opera- tion, maintenance, and data transfer (see Section 10.3.2, Monitor Message Transfer, for more details). ■ Provides control of the C/I-1 subchannel (see Sec- tion 10.4, C/I Message Transfer, for more details). Register GCOF1[OFF1(4:0)] controls the time slots to which PFS1 and PFS2 are assigned. Table 79 illus- trates the relationship between the value of GCOF1[OFF1(4:0)] and the time-slot assignment of the PFS1 and PFS2 signals. Note that the GCOF2 register is ignored in GCI-NT mode.

10.3.1 GCI-SCIT Mode (GCCF, GMODE[1:0] = 01) (continued)

1. Not output. Shown only for reference.

GCCF[GMODE] = 01 (GCI-TE) ≥ DCL = 1536 kHz. Figure 18. GCI-TE Mode Frame Structure Table 79. GCI-TE Data-Slot Association

Lucent Technologies Inc. 77 Preliminary Data Sheet November 2000 ISDN Network Termination Node (NTN) Device T9000 (continued)

10.3.2 Monitor Message Transfer

For both GCI-NT and GCI-TE modes, the NTN man- ages the monitor channel (MON) protocol as defined by the GCI standard. In GCI-NT mode, monitor data transfer occurs in time slot 2 (MON-0) using the A&E bit pair in time slot 3. In GCI-TE mode, monitor data transfer occurs in time slot 6 (MON-1) using the A&E bit pair in time slot 7. Monitor messages may be one or more bytes in length. To transmit a single byte message downstream, the microcontroller writes the monitor byte into the GCDML register. Once this byte is internally loaded, the GCI- controller asserts the interrupt bit GCIR[DMRDY] indi- cating to the microcontroller that it is ready to accept a new message to be transmitted. If the transmission is successfully completed, the GCI controller asserts interrupt bit GCIR[DMEOM]. Otherwise, if the transmis- sion has been aborted, it will assert interrupt bit GCIR(DMABRT). Downstream monitor message aborts may occur as a consequence of an abort request by the downstream device or an expiration of the GCI controller downstream timer (if GCOF1[GTMODE] = 1). Multibyte monitor messages operate in a similar man- ner to single-byte messages, except that for an N-byte message, bytes 1 to N – 1 are written into register GCDMD, and the last monitor byte is written into regis- ter GCDML. The interrupt bit GCIR[DMRDY] is used in both cases to signify when new downstream data may be written to either GCDMD or GCDML. Upstream monitor bytes, when confirmed, are trans- ferred to the GCUMD register. Interrupt bit GCIR[UMRDY] is asserted to indicate a new monitor byte has been successfully received. At the completion of an upstream message, interrupt bit GCIR[UMEOM] is asserted. If the upstream message is aborted, the interrupt bit GCIR [UMABRT] is asserted. Upstream monitor message aborts may occur as a consequence of an implicit abort produced by an invalid upstream A&E bit pair sequence (normally produced by the downstream device) or an expiration of the GCI con- troller upstream timer (if GCOF1[GTMODE] = 1). The embedded GCI controller has one timer associ- ated with each monitor direction to avoid deadlock situ- ations. Both timers may be enabled by setting GCOF1[GTMODE] = 1. The downstream timer will be started each time the transfer of a downstream monitor byte is initiated. If the byte is not acknowledged within four frames, the timer will expire and generate an abort request. The upstream timer will be started upon the detection of a new byte. If this byte is not confirmed by the far end (because it did not detect identical bytes in two consecutive frames—upstream RNR event) or the byte cannot be transferred to the GCUMD register (because the microcontroller has not yet read the previ- ous byte—upstream RNR event), the timer will expire.

10.4 C/I Message Transfer

For both GCI-NT and GCI-TE modes, the NTN man- ages data transfer over the command/indication chan- nel as defined by the GCI standard. In GCI-NT mode, C/I data transfer occurs in the first 6 bits of time slot 3 (C/I-0). In GCI-TE mode, C/I data transfer occurs in the first 6 bits of time slot 7 (C/I-1). To transmit a downstream C/I code, the microcontroller writes the code into the GCDCI register. This code will be continuously transmitted until a new code is written to GCDCI. The internal GCI controller will not read the new code from GCDCI until the current code has been transferred in at least two consecutive frames. Upstream command/indication codes are first filtered before they are transferred to the GCUCI register. A double last look criterion is used to validate a new C/I code, i.e., a new code is transferred to the GCUCI reg- ister only if it is different from the previously loaded value and is received in two consecutive GCI frames. Whenever this happens, the GCIR[UCIC] interrupt is asserted.

10.5 GCI+ Powerdown Mode

The GCI+ may be placed in a powerdown mode by set- ting GCCF[GRATE(1:0)] = 00). Prior to enabling power- down mode, the user must set DFR[PFS1_ACT] = 0 and DFR[PFS2_ACT] = 0. While in powerdown mode, the DCL clock signal is stopped (held low), the PFS1 and PFS2 signals are held low, and the DD signal is 3-stated. When in powerdown, a falling edge on the DU signal causes an assertion of the interrupt bit GCIR[GWUP]. This allows the user to write a powerup routine for the GCI+ interface.

10.6 GCI+ Loopbacks

DFR (G_L_LBK) and DFR (G_R_LBK) register bits control the loopback mode of the GCI interface. at the same time. Note that loopbacks only operate over data channels; no other channels will be looped back. Figure 19. GCI Loopback Logic

10.7 GCI+ Register Set

Table 80. GCCF: GCI+ Configuration Register (0x2E) 7 GDRIVER GCI+ Driver Type. Sets the type of output driver to be used for the GCI+ signal DD. the time slot associated with PFSx. 0: PFSx rising edge is coincident with the start of the corresponding time slot. duration of the PFSx (x = 1 or x = 2) pulse. 0: PFS is an 8-bit envelope lasting from one time slot minus one-half of a DCL period. 1: PFS lasts for one data bit time. clock mode when in TDM mode. This bit is ignored in GCI mode. 0: DCL set to double clock mode (two clocks per data bit). 1: DCL set to single clock mode (one clock per data bit). (GMODE[1:0] = 0x), these bits are ignored, unless they are equal to 00.

10.7 GCI+ Register Set (continued)

Table 81. GCOF1: GCI PFS1 Offset Select (0x2F) Table 82. GCOF2: GCI PFS2 Offset Select (0x30) Enables the GCI time-out mechanism. 0: Time-out mechanism disabled. 6 G_R_LBK GCI Remote Loopback. 5 G_L_LBK GCI Local Loopback. offset from the first time slot of the frame. is offset from the first time slot of the frame.

The following registers are only relevant in GCI mode, with the exception of GCIR[GWUP] and GCIE[GWUPE]. Table 83. GCDMD: GCI Downstream (Transmit) Monitor Data (0x31) Table 84. GCDML: GCI Downstream (Transmit) Monitor Data Last (0x32) Table 85. GCUMD: GCI Upstream (Receive) Monitor Data (0x33) tion that a new byte may be loaded.

Table 86. GCDCI: GCI Downstream (Transmit) C/I Data (0x34) Table 87. GCUCI: GCI Upstream (Receive) C/I Data (0x35) 7—6 — Reserved. Program to 0. 7—6 — Reserved. Program to 0. dated byte has been received.

Table 88. GCIR: GCI Interrupt Register (0x36) to 0 when the register is read.

1. GCI clocks are stopped (GCCF[GRATE(1:0)] = 00).
2. A falling edge of DU occurs.

new, validated C/I code in register GCUCI. At reset, the internal C/I code is set to 111111. is available in register GCUMD. message has been successfully received. buffer is empty and a new byte may be loaded into GCDMD or GCDML. successful reception of the last byte of a downstream message.

Table 89. GCIE: GCI Interrupt Enable (0x37) 7 GWUPE GCI Wake-Up Interrupt Enable. 6 UCICE UCIC Interrupt Enable. 5 UMRDYE UMRDY Interrupt Enable. 4U M E O M E UMEOM Interrupt Enable. 3U M A B R T E UMABRT Interrupt Enable. 2 DMRDYE DMRDY Interrupt Enable. 1D M E O M E DMEOM Interrupt Enable. 0D M A B R T E DMABRT Interrupt Enable.

Lucent Technologies Inc. 85 Preliminary Data Sheet November 2000 ISDN Network Termination Node (NTN) Device T9000

11 GPIO Ports

Three general-purpose input/output ports are available on the T9000 device with each port being 8 bits wide. For any port, each signal may be individually config- ured as an input or as an output by proper program- ming of registers GPDIR[0:2]. On reset, all ports are configured as inputs. All GPIO signals have a weak pull-up resistor of 100 kΩ (nominal value). Unneeded GPIO signals should be configured as inputs, and may be left uncon- nected. If connected on the board, it is recommended that they be tied to V DD to avoid power consumption. Registers GPD[0:2] contain the value on the GPIO pin. For GPIO pins configured as inputs, the microcontroller accesses the port value by reading its corresponding GPD register. For GPIO pins configured as outputs, the microcontroller writes the desired value into its corre- sponding GPD register. GPIO0.[3:0] and GPIO1.[3:0] pins, when configured as inputs (see registers GPDIR0 and GPDIR1), may also be configured as level-activated or transition-activated external interrupt sources for the microcontroller (see registers GPPOL and GPLEI). Any of these eight exter- nal interrupt sources may be masked by proper pro- gramming of register GPIE. On module reset, all interrupts are disabled. GPIO interrupt register (GPIR) is cleared when read by the microcontroller. GPIO0.[3:0] and GPIO1.[3:0] pins, when configured as inputs, present a Schmitt trigger buffer for better noise immunity. GPAF0 and GPAF1 registers define alternate functional modes for some GPIO pins. ■ GPAF0[GPAF0.(7:6)] register bits, when set, override GPDIR0 [DIR0.(7:6)] and configure GPIO0.[7:6] as the PWM 1 output. ■ GPAF0[GPAF0.(5:4)] register bits, when set, override GPDIR0[DIR0.(5:4)] and configure GPIO0.[5:4] as PWM0 outputs. ■ GPAF1[GPAF1.(7:5)] register bits, when set, override GPDIR[DIR1.(7:5)] and configure GPIO1.[7:5] as input trigger sources for timers 2, 1, and 0 (for proper timer operation, the microcontroller should also con- figure the associated SFR register bit for each timer). ■ GPAF1[GPAF2.3] register bit, when set, overrides the GPDIR2[DIR2.3] register bit and configures GPIO2.3 as a SYNCO output from the dc/dc module (see Section 13, dc/dc Control Generator). ■ GPAF1[GPAF2.2] register bit, when set, overrides the GPDIR2[DIR2.2] register bit and configures GPIO2.2 as the reference frame sync clock (FSC) output as specified in Section 10, GCI+ Interface Module. ■ GPAF1[GPAF2.1] register bit, when set, overrides the GPDIR2[DIR2.1] register bit and configures GPIO2.1 as the GCI bit clock (BCLK) output (as specified in Section 10, GCI+ Interface Module). ■ GPAF1[GPRESET] provides a nonlatching software reset of the GPIO module. It has the same effect as a global reset or a global software reset. ■ DOCR[LT_NT] register bit, when set, ignores GPDIR2[DIR2.6] and configures GPIO2.6 as the input for 8 kHz master transmit clock (MTC) signal. ■ When the test pin (pin 43) is asserted, GPIO1.4 and GPIO2.7 change their functions to USSP_E and PTLB_S, respectively, as explained in Table 4. All registers are read/write to allow read-modify-write operations by the microcontroller. Transition activated interrupt sources may be individually reset by writing a 1 to the associated bits of GPPOL register. All GPIO port signals are TTL levels. Driving capability is 6 mA for GPIO2.0 signal and 1 mA for all others. Figure 20 summarizes features available for all GPIO signals.

11 GPIO Ports (continued)

Note:Alternate pin functions, shown in parentheses (), are selected when the TEST pin is asserted. Alternate pin functions, shown in brackets [], are selected when the corresponding register bits are set. Figure 20. GPIO Pin Capabilities Summary

11.1 GPIO Register Set

Table 90. GPDIR0: GPIO Port 0 Pin Direction (0x38) 7—0 DIR0.[7:0] GPIO0.[7:0] Pin Direction. α : External interrupt capability. χ : Optional trigger sources for timers. : Schmitt trigger when inputs.

11.1 GPIO Register Set (continued)

Table 91. GPDIR1: GPIO Port 1 Pin Direction (0x39) Table 92. GPDIR2: GPIO Port 2 Pin Direction (0x3A) 7—0 DIR1.[7:0] GPIO1.[7:0] Pin Direction. is ignored and pin GPIO2.6 becomes an input to the 8 kHz MTC signal.

Table 93. GPAF0: GPIO Alternate Function Register #0 (0x3B) 7G P A F 0 . 7 GPIO0.7 Alternate Function Selection. 0: No effect on device operation. 6G P A F 0 . 6 GPIO0.6 Alternate Function Selection. 0: No effect on device operation. 5G P A F 0 . 5 GPIO0.5 Alternate Function Selection. 0: No effect on device operation. 4G P A F 0 . 4 GPIO0.4 Alternate Function Selection. 0: No effect on device operation. 3—0 — Reserved. Program to 0.

Table 94. GPAF1: GPIO Alternate Function Register #1 (0x3C) Table 95. GPD0: GPIO Port 0 Data Register (0x3D) 7G P A F 1 . 7 GPIO1.7 Alternate Function Selection. 0: No effect on device operation. input (connects directly to P1.0 of the microcontroller module). 6G P A F 1 . 6 GPIO1.6 Alternate Function Selection. 0: No effect on device operation. input (connects directly to P3.5 of the microcontroller module). 5G P A F 1 . 5 GPIO1.5 Alternate Function Selection. 0: No effect on device operation. input (connects directly to P3.4 of the microcontroller module). 3G P A F 2 . 3 GPIO2.3 Alternate Function Selection. 0: No effect on device operation. 2G P A F 2 . 2 GPIO2.2 Alternate Function Selection. 0: No effect on device operation. 1G P A F 2 . 1 GPIO2.1 Alternate Function Selection. 0: No effect on device operation. 0 GPRESET GPIO Reset. Resets all the GPIO bits. 7—0 GPD0.[7:0] I/O Data on GPIO Port 0.

Table 96. GPD1: GPIO Port 1 Data Register (0x3E) Table 97. GPD2: GPIO Port 2 Data Register (0x3F) Table 98. GPLEI: GPIO Level-Edge-Triggered Interrupt Control (0x40) 7—0 GPD1.[7:0] I/O Data on GPIO Port 1. 7—0 GPD2.[7:0] I/O Data on GPIO Port 2. mode (see register GPDIR1). ILE1.x defines the interrupt mechanism for GPIO1.x pin. mode (see register GPDIR0). ILE0.x defines the interrupt mechanism for GPIO0.x.

Table 99. GPPOL: GPIO Interrupt Polarity Control (0x41) Table 100. GPIR: GPIO Interrupt Register (0x42) ing a one to the corresponding bits in GPPOL registers. ter GPDIR1). IPOL1.x specifies value of GPIO1.x that generates an interrupt. 0: Level-triggered => Interrupt when level is 0. Edge-triggered => Interrupt on falling edge. 1: Level-triggered => Interrupt when level is 1. Edge-triggered => Interrupt on rising edge. ter GPDIR0). IPOL0.x specifies value of GPIO0.x that generates an interrupt. 0: Level-triggered => Interrupt when level is 0. Edge-triggered => Interrupt on falling edge. 1: Level-triggered => Interrupt when level is 1. Edge-triggered => Interrupt on rising edge.

Table 101. GPIE: GPIO Interrupt Enable (0x43) 7—4 GPIE1.[3:0] GPIO1.x Interrupt Enable. 3—0 GPIE0.[3:0] GPIO0.x Interrupt Enable.

12 PWM Module

The PWM module is comprised of a general-purpose dual pulse-width modulator with sine modulation capability. pulse train generation. Pulse-width values change according to the user’s desired algorithm. at pulse period intervals. The PWM signal is then low-pass filtered with a simple RC integrator. the outputs of PWM1 (PWMO10 and PWMO11) can also drive 2 different external devices. Figure 21. Pulse-Width Modulated Output Signal

9494 Lucent Technologies Inc. Preliminary Data Sheet November 2000ISDN Network Termination Node (NTN) Device T9000

12 PWM Module (continued)

For low-frequency tones (Hz range), the algorithm that defines the width of the pulse is easily accomplished with microcontroller routines (manual mode). However, implementing higher frequency tones (kHz range) requires a large degree of microcontroller intervention. To address this issue, the PWM generators were designed to operate in two different modes: manual/ timer mode and auto mode.

12.1 PWM Manual/Timer Operation Mode

In manual mode, the user may implement any desired algorithm to define the width of the pulses. Two impor- tant parameters that are controlled via the PWxCF reg- ister are pulse-width granularity and pulse-width range. Pulse-width granularity defines the minimum duration (or tick) of a pulse width. Pulse-width range denotes the number of possible ticks in a pulse period or, in other words, the number of different width values with which the pulse can be modulated. The tick size and pulse period may be expressed as: Tick = Granularity x 65 ns (1) PP = Range x Tick = Range x Granularity x 65 ns (2) Concerning the above relationships, note the following: ■ A small granularity allows for a finer resolution of the resulting output signal in time, and therefore requires less filtering. ■ A large range allows for a finer resolution, in ampli- tude, of the resulting output signal. ■ Power consumption is roughly inversely proportional to the granularity value, so the larger the granularity, the less power the circuit will consume. ■ As granularity and range are increased, the equiva- lent oversampling rate is decreased (i.e., the pulse period, PP, increases as shown in equation 2 above). At the start of a pulse period, the controller loads the value contained in register PWxVH and generates a pulse with a width PWxVH multiplied by the tick value (where only the appropriate MSBs of PWxVH are used according to the tick value, see register PWxVH). The value in PWxVL determines the rate at which the PWIR[PWxI] interrupt register bit will be asserted. The module asserts the PWIR (PWxI) interrupt register bit every PWxVL + 1 pulse period intervals. The interrupt is generated only if the PWxCF (PWxIE) bit is set. The interrupt is asserted even if GPIO pin is not assigned to the PWMx generator. The interrupt register is reset upon a register read operation.

12.2 PWM Auto Operation (Sine) Mode

The auto mode uses a sine modulator controller (PWSM) to substantially reduce the overhead require- ment of the microcontroller. In this mode, the width of the pulses automatically follows the amplitude of a sine wave of frequency Fs. A 256-byte ROM is used to store discrete values of amplitude for one period of a sine wave, where each successive ROM location, n, represents the sine amplitude at a normalized time of t = n/256. Figure 22 shows a simplified architecture of the PWM block (the shaded areas indicate the extra logic required for implementing the sine wave functionality). The 8-bit ROM address is derived from the upper 8 bits of the 16-bit accumulator output. The accumulator sim- ply adds the 16-bit value formed by the PWxVH and PWxVL registers (PWV) to its output every cycle, where the cycle time is determined by the pulse period, PP. Consider then, how PWV and PP affect the output. When PWV is <2 8, each ROM value will be output for a least one cycle, and possibly even more (depending on how far below 2 8 the PWV value is). Conversely, when PWV is >28, some ROM values will be skipped. Thus, as the value of PWV drops below 28, it has the effect of increasing the quantization error in the amplitude of the sinewave output. PWV, then, can be thought of as controlling the ROM step size (where the step size can be <1). When PP is large, the rate at which each newly formed ROM address is output is slower than when PP is small. Therefore, if all other factors are equal, a larger PP will result in a lower frequency sinewave output. PP , then, can be thought of as controlling the ROM step rate. In auto mode, range and granularity take on a some- what different meaning than in manual mode. In auto mode, Equations (1) and (2) still hold with respect to range and granularity, but tick does not play a direct role in this case. Rather, it is the combination of range and granularity that determines the frequency and amplitude resolution of the output waveform as explained above.

12.2 PWM Auto Operation (Sine) Mode (continued)

Figure 22. PWMCNTRL Architecture

12.3 PWSM ROM

sine amplitudes in the ROM represent a sine wave with a 2.5%—97.5% scale and a dc offset of 128 (out of 256). Table 102 illustrates the resulting value W(A) at each ROM address A. Table 102. ROM Code Values in decimal (A = address; W = width).

Lucent Technologies Inc. 97 Preliminary Data Sheet November 2000 ISDN Network Termination Node (NTN) Device T9000

12.4 PWM Auto Mode Example

Consider an example of how to set up the PWM mod- ule in auto mode. Suppose we want to generate a sine wave of frequency Fs. First select the values of range and granularity, and then compute the appropriate value of PWxVH/L. To accomplish this, the procedure is as follows: Calculate the pulse period, PP , (from equation 2) PP = Range x Granularity x 65 ns (3) Calculate the sine period, SP: SP = (4) Based on PP and SP, we can calculate the number of samples (Ks) per sine period: Ks = = (5) Now calculate the 16-bit quantity PWV (i.e., PWVxH/L, the amount by which the accumulator will increment each time as shown in Figure 22). There are 2 16 total addresses in one sine period, SP. Since there are Ks samples in one sine period, 2 16 must be divided by Ks so that exactly one cycle of all 216 addresses has been completed in one sine period, SP. The rounded result is PWV, which gets written into the PWxVH and PWxVL registers: PWV = ROUND = ROUND (6) Now, back-calculate the actual number of samples (Ka) based on the rounded result: Ka = (7) To find the error in frequency due to rounding, first back-calculate the actual frequency of the sine modula- tor output by taking the inverse of the pulse period times the actual number of samples, as follows: Fa = (8) Then calculate the error in frequency as: Ferr = x 100% (9) To further understand the operation of the PWSM mod- ule, consider the math behind the operation. The sine wave being generated can be described by the follow- ing equation: f(t) = Asin (2 π x Fa x t) (10) where Fa is computed per equation 8. A new value for this equation is computed every pulse period, PP. Therefore, in the nth pulse period (where n is an inte- ger representing the current sample number, beginning with sample 0), the time (t) in the above equation is: t = n x PP (11) Substituting equation 11 into equation 10 yields: f(t) = Asin (2 π x Fa x n x PP) (12) Now rearranging equation 8, PP = (13) and substituting the value of Ka computed in equation 7 results in: PP = (14) Substituting equation 14 into equation 12 yields: f(t) = Asin (2π ) (15) From equation 15, it is evident that the argument gen- erated sine wave is n x PWV. This term is generated at the output of the accumulator shown in Figure 22 by clocking the accumulator at PP intervals. The maxi- mum value of n x PWV is 2 16 because the accumulator will roll over after it reaches 216. Therefore, the factor of 216 in the denominator is the normalization factor, which is equal to the maximum value of n x PWM. FS SP PP 216 K S

216 Range× Granularity× 65 ns×

Fa F S– FS PWV Fa 2 16× nP W V×

12.4 PWM Auto Mode Example (continued)

guide the selection of these values for a particular application. Consider an example using real numbers. PWV, Ka, Fa, and frequency error (Ferr) for all possible values of range and granularity. Table 103. PWM Sine Modulator Programming Example

that only three of the entries meet this requirement in this example. Figure 23. Widths of PWM Pulses Generated with a 2.5%— 97.5% Modulation Width

100 Lucent Technologies Inc.

12.5 PWM Powerdown Mode

Each PWM generator can be powered down by setting PWxCF (PwxE) register bit to 0.

12.6 PWM Module Register Set

Table 104. PW0CF: Pulse-Width Modulator 0 Configuration (0x44) 0: Powerdown mode. PWMO0 output is maintained at 0. 6 PW0AUTO PWM 0 Auto/Manual Operation Mode. 0: Manual/timer operation mode. 1: Sine modulator activated. 5 PW0IE PWM 0 Interrupt Enable. tick0 value (see pulse-width range below).

12.6 PWM Module Register Set (continued)

Table 105. PW0VH: Pulse-Width Modulator 0 Pulse-Width Value, High Byte (0x45) Table 106. PW0VL: Pulse-Width Modulator 0 Pulse-Width Value, Low Byte (0x46) order byte of the programmed sine frequency (Fs). PWIR[PW0I] assertion rate = PP0 x (PW0VL + 1).

102 Lucent Technologies Inc. Table 107. PW1CF: Pulse-Width Modulator 1 Configuration (0x47) 0: Powerdown mode. PWMO1 output is maintained at 0. after defining PP1 (see pulse-width range below). 6 PW1AUTO PWM 1 Auto/Manual Operation Mode. 1: Sine modulator activated. 5 PW1IE PWM 1 Interrupt Enable. tick1 value (see pulse-width range below).

Table 108. PW1VH: Pulse-Width Modulator 1 Pulse-Width Value, High Byte (0x48) Table 109. PW1VL: Pulse-Width Modulator 1 Pulse-Width Value, Low Byte (0x49) Table 110. PWIR: Pulse-Width Modulator Interrupt Register (0x4A) to 0 when the register is read. order byte of the programmed sine frequency (Fs). PWIR[PW1I] assertion rate = PP1 x (PW1VL + 1). 1—0 PWxI PWM x Interrupt. This interrupt occurs only in manual/timer mode (PWxAUTO = 0). is the enable bit for this interrupt.

104 Lucent Technologies Inc. As an example, DCV = 14 generates a 32 kHz square wave output signal. This module can be disabled by setting DCCF[DC_E] to 0. Table 111. DCCF: dc/dc Configuration Register (0x4B) DCCF may be read by the microcontroller, allowing a read-modify-write operation. 7—6 — Reserved. Program to 0. 5D C _ E dc/dc Controller Enable. When disabled, SYNCO = 0. 4—0 DCV[4:0] dc Prescale Value. SYNCO Frequency = 960/(2 * (DCV + 1)) kHz.

14 Comparators

power consumption is minimized. A: Interrupt generated (CMI[i] = 1), if enabled (CMIE[i] = 1) and falling transition (CMT[i] = 0). B: Interrupt generated (CMI[i] = 1), if enabled (CMIE[i] = 1) and falling transition (CMT[i] = 1). Figure 24. (A) CMV When CME Is a Periodic Pulse and (B) CMV When CME Is Static

106 Lucent Technologies Inc.

14 Comparators (continued)

Table 112 shows the major characteristics of the comparators. Table 112. Comparator Characteristics

14.1 Comparators Register Set

Table 113. CME: Comparator Enable (0x4C) Table 114. CMT: Comparator Transition Polarity (0x4D) of the corresponding comparator output. 2—0 CME.[2:0] Comparator [2:0] Enable. 0: Comparator disabled (powerdown mode). Note: On powerdown, any pending interrupts are reset. of the corresponding comparator output. 2—0 CMT.[2:0] Comparator [2:0] Transition Polarity. 0: Interrupt on 1-to-0 transition. 1: Interrupt on 0-to-1 transition.

14.1 Comparators Register Set (continued)

Table 115. CMIR: Comparator Interrupt Register (0x4E) cleared to 0 when the register is read. Table 116. CMIE: Comparator Interrupt Enable (0x4F)

14.2 Configuration Sequence

■ The comparator interrupt is disabled. ■ The comparator is powered down. ing comparator output. No interrupt is generated in response to the value in these bits. gled in the direction specified in register CMT. of the corresponding comparator output. 2—0 CMIE.[2:0] Comparator [2:0] Interrupt Enable. 0: Interrupt disabled (masked). Masked interrupts are not latched.

108 Lucent Technologies Inc. Preliminary Data Sheet November 2000ISDN Network Termination Node (NTN) Device T9000

15 Test Mode

When the TEST pin (pin 43) is asserted, pins 34, 85, and 97 change their existing functions so that the customer can put the device in ILOSS, single pulses on the U-interface, and pulse template/loopback on S/T-interface test modes, respectively. When the TEST pin (pin 43) is asserted, pins 29, 30, 32, 35, 40, 41, and 42 also change their existing functions to enable factory testing of the device as explained in Table 3 and Table 7. Note:The existing functions on the above pins will not be available when the TEST pin is asserted.

16 Loopbacks

Following is a description of the loopbacks supported by the NTN. T1.605, Appendix G. A complete discussion of these loopbacks is presented in ITU-T I.430, Appendix I. Figure 25. Location of the Loopback Configurations

110 Lucent Technologies Inc. extended periods can adversely affect device reliability. External leads can be soldered safely at temperatures up to 300 °C. Table 117. Absolute Maximum Ratings

18 Handling Precautions

Table 118. ESD Threshold Voltage

19 Recommended Operating Conditions

Table 119. Recommended Operating Conditions

• To meet ANSI T1.601 free-run line rate requirement, NT tolerance is 100 ppm.

20.1 Power Supply

20.2 Power Consumption

Table 120. Power Consumption

20.3 S/T-Interface Receiver Common-Mode Rejection

Table 121. S/T-Interface Receiver Common-Mode Rejection

112 Lucent Technologies Inc.

20.4 Pin Electrical Characteristics

Table 122. Digital dc Characteristics (Over Operating Ranges)

21 Crystal Characteristics

Table 123. Fundamental Mode Crystal Characteristics the range of 0.6 pF ± 0.4 pF. **Table 124. Internal PLL Characteristics * Set by digital PLL; therefore, variations track MTC (LT mode) or U-interface line rate (NT mode).**

22 Timing Characteristics

**Table 125. MTC (Master Timing Clock) Requirements and Characteristics* (LT Mode)**

• To meet ANSI T1.601-1992, see not for Recommended Operating Conditions.

114 Lucent Technologies Inc. Figure 26. NT1 Application Figure 27. NT1+ Application

Figure 28. Pair Gain Application

116 Lucent Technologies Inc. Preliminary Data Sheet November 2000ISDN Network Termination Node (NTN) Device T9000

24 Outline Diagram

24.1 100-Pin TQFP Dimensions are in millimeters. Note:The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Lucent Technologies Account Manager. 5-2146C

0.50 TYP

1.60 MAX

0.08 1.40 ± 0.05 0.05/0.15 DETAIL A DETAIL B 14.00 ± 0.20 16.00 ± 0.20 76100 26 50 14.00 ± 0.20 16.00 ± 0.20 PIN #1 IDENTIFIER ZONE DETAIL B 0.19/0.27 0.08 M 0.106/0.200 DETAIL A 0.45/0.75 GAGE PLANE SEATING PLANE

1.00 REF

0.25

Lucent Technologies Inc. 117 Preliminary Data Sheet November 2000 ISDN Network Termination Node (NTN) Device T9000 Device Code Package Temperature Comcode T-9000- - -TL 100-pin TQFP –40 °C to +85 °C 108556523

118 Lucent Technologies Inc.

26 Register Set Summary

The following section contains tables that list a summary of the entire register set for the T9000. Table 126. Register Set Summary Global Registers Table 127. Register Set Summary DFAC Registers Table 128. Register Set Summary U-Interface Control Registers

26 Register Set Summary (continued)

Table 129. Register Set Summary EOC Control Registers Table 130. Register Set Summary S-Interface Registers Table 131. Register Set Summary Multiframe Registers Table 132. Register Set Summary U-Interface Interrupt Registers

120 Lucent Technologies Inc. Table 133. Register Set Summary S-Interface Interrupt Registers

Table 134. Register Set Summary HDLC Registers

122 Lucent Technologies Inc. Table 134. Register Set Summary HDLC Registers (continued)

Table 135. Register Set Summary GCI+ Registers

124 Lucent Technologies Inc. Table 136. Register Set Summary GPIO Registers

Table 137. Register Set Summary PWM Registers Table 138. Register Set Summary dc/dc Register

rights under any patent accompa ny the sale of any such product(s) or information. Co pyright © 2000 Lucent Technologies Inc. Table 139. Register Set Summary C om parator Registers