T8XC51SND1

T83C51SND1 ATMEL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 60

Technical content

Rev. D – 15-Nov-01 1. Features  MPEGI/II-Layer 3 Hardwired Decoder – Stand-alone MP3 decoder – 48, 44.1, 32, 24, 22.05, 16 KHz sampling freq. – Separated digital volume control on left and right channels (software control using 31 steps) – Bass, medium, and Treble Control (31 steps) – Bass Boost sound effect. – Ancillary data extraction – “CRC Error” and “MPEG Frame Synchronization” indicators  Programmable Audio Output for interfacing with common audio DAC available on the market – PCM format compatible – I2S format compatible  8-bit MCU C51 core based (FMAX= 20 MHz)  2304 bytes of Internal RAM  64 Kbytes of Code Memory – FLASH: T89C51SND1, ROM: T83C51SND1  4 Kbytes of Boot Flash Memory (T89C51SND1) – ISP: download from USB or UART to any external memory cards  USB Rev 1.1 controller –“ Full speed” data transmission  Built-in PLL – MP3 Audio clocks – USB clock  MultiMediaCard Interface Compatibility  Atmel DataFlash SPI Interface Compatibility  IDE/ATAPI Interface  2 Channels 10-bit ADC, 8KHz (8 true bit) – Battery voltage Monitoring – Voice recording controlled by software  Up to 44 bits of General Purpose I/Os for: – 4-bit interrupt keyboard port for a 4 x n matrix – Smartmedia software interface  Standard Two 16-bit Timers/Counters  Hardware Watchdog Timer  Standard Full Duplex UART with Baud Rate Generator  2-wire Master and Slave Modes Controller  SPI Master and Slave Modes Controller  Power Management – Power-On reset – Software programmable MCU clock – Idle mode, Power-Down mode  Operating conditions: – 3V, ±10%, 25 mA typical operating at 25°C – -40°C to +85°C  Packages – TQFP80, PLCC84 (development board) – Dice Single Chip Microcontroller with MP3 Decoder and Man Machine Interface T8xC51SND1

2 T8xC51SND1

Rev. D – 15-Nov-01 2. Description The T8xC51SND1 product is a fully integrated stand-alone hardwired MPEGI/II-Layer 3 decoder with a C51 microcontroller core handling data flow and MP3-player control. The T89C51SND1 includes 64 Kbytes of FLASH memory and allows In System Pro- gramming through an embedded 4 Kbytes of Boot FLASH Memory. The T83C51SND1 includes 64 Kbytes of ROM memory. The T8xC51SND1 includes 2304 bytes of RAM memory. The T8xC51SND1 provides all necessary features for man machine interface like tim- ers, keyboard port, serial or parallel interface (USB, 2-wire, SPI, IDE), ADC input, I output, and all external memory interface (NAND or NOR FLASH, SmartMedia, MultiMedia). 3. Typical Applications  MP3-Player  PDA, Camera, Mobile Phone MP3  Car Audio/Multimedia MP3  Home Audio/Multimedia MP3

4.1 Pinouts

Figure 1. T8xC51SND1 80-pin QFP Package

4 T8xC51SND1

Figure 2. T8xC51SND1 84-pin PLCC Package

4.2 Signals

All the T8xC51SND1 signals are detailed by functionality in Table 1 to Table 14. Table 1. Ports Signal Description P1 is an 8-bit bidirectional I/O port with internal pull-ups.

Table 2. Clock Signal Description Table 3. Timer 0 and Timer 1 Signal Description P3 is an 8-bit bidirectional I/O port with internal pull-ups. P4 is an 8-bit bidirectional I/O port with internal pull-ups. pin. X1 is the clock source for internal timing. this pin. If an external oscillator is used, leave X2 unconnected. is set by a low level on INT0#. is set by a low level on INT1#.

6 T8xC51SND1

Table 4. Audio Interface Signal Description Table 5. USB Controller Signal Description Table 6. MutiMediaCard Interface Signal Description (DOUT) and the channel selection signal (DSEL). unused MDAT input must be polarized to V DD or VSS.

Table 7. UART Signal Description Table 8. SPI Controller Signal Description Table 9. 2-wire Controller Signal Description Table 10. A/D Converter Signal Description serial I/O modes 1, 2 and 3. serial I/O modes 1, 2 and 3. When in master mode, MISO receives data from the slave peripheral. When in slave mode, MISO outputs data to the master controller. When in master mode, MOSI outputs data to the slave peripheral. When in slave mode, MOSI receives data from the master controller. in slave mode, SCK receives clock from the master controller. receives clock from the master controller.

8 T8xC51SND1

Table 11. Keypad Interface Signal Description Table 12. External Access Signal Description Table 13. System Signal Description Upper address lines for the external bus. Multiplexed higher address and data lines for the IDE interface. to demultiplex the address from address/data bus. falling reset to force execution of the internal bootloader. returns the chip to normal operation.

Table 14. Power Signal Description

10 T8xC51SND1

4.3 Internal Pin Structure

Table 15. Detailed Internal Pin Structure the Section “DC Characteristics”, page 34.

1. When the 2-wire controller is enabled, P 1, P2, and P3 transistors are disabled allowing

pseudo open-drain structure.

1. In Port 2, P 1 transistor is continuously driven when outputting a high level bit address

Figure 3. T8xC51SND1 Block Diagram

1 Alternate function of Port 1

3 Alternate function of Port 3

4 Alternate function of Port 4

64 Kbytes

4 Kbytes

12 T8xC51SND1

Figure 4. T8xC51SND1 Typical Application with On-Board Atmel DataFlash and 2-wire

14 T8xC51SND1

Figure 7. T8xC51SND1 Typical Application with IDE CD-ROM Drive

Rev. D – 15-Nov-01 7. Address Spaces The T8xC51SND1 derivatives implement four different address spaces:  Program/Code Memory  Boot Memory  Data Memory  Special Function Registers (SFRs)

7.1 Code Memory

The T89C51SND1 and T83C51SND1 implement 64 Kbytes of on-chip program/code memory. The T83C51SND1 product provides the internal program/code memory in ROM technology while the T89C51SND1 product provides it in FLASH technology. The FLASH memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing FLASH cells is generated on-chip using the standard VDD voltage. Thus, the T89C51SND1 can be programmed using only one voltage and allows in application software programming commonly known as IAP. Hardware programming mode is also available using specific programming tool.

7.2 Boot Memory

The T89C51SND1 implements 4 Kbytes of on-chip boot memory provided in FLASH technology. This boot memory is delivered programmed with a standard boot loader software allowing in system programming commonly known as ISP. It also contains some Application Programming Interfaces routines commonly known as API allowing user to develop its own boot loader.

7.3 Data Memory

The T89C51CC01 derivatives implement 2304 bytes of on-chip data RAM. This memory is divided in two separate areas:  256 bytes of on-chip RAM memory (standard C51 memory).  2048 bytes of on-chip expanded RAM memory (ERAM accessible via MOVX instructions).

7.4 Special Function Registers

The Special Function Registers (SFRs) of the T89C51CC01 derivatives fall into the cat- egories detailed in Table 16 to Table 32. The relative addresses of these SFRs are provided together with their reset values in Table 33. In this table, the bit-addressable registers are identified by Note 1.

16 T8xC51SND1

Table 16. C51 Core SFRs Table 17. System Management SFRs Table 18. PLL & System Clock SFRs Table 19. Interrupt SFRs

Table 20. Port SFRs Table 21. Flash Memory SFR Table 22. Timer SFRs Table 23. MP3 Decoder SFRs

1 Control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

1 Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

18 T8xC51SND1

Table 24. Audio Interface SFRs Table 25. USB Controller SFRs

Table 26. MMC Controller SFRs Table 27. IDE Interface SFR Table 28. Serial I/O Port SFRs

7 MMCD6 MMCD5 MMCD4 MMCD3 MMCD2 MMCD1 MMCD0

0 SM1 SM2 REN TB8 RB8 TI RI

20 T8xC51SND1

Table 29. SPI Controller SFRs Table 30. 2-wire Controller SFRs Table 31. Keyboard Interface SFRs Table 32. A/D Controller SFRs

Table 33. SFR Addresses and Reset Values

1. NVERS reset value depends on the silicon version.
2. FCON register is only available in T89C51SND1 product.
3. FCON reset value is 00h in case of reset with hardware condition.
4. CKCON reset value depends on the X2B bit (programmed or unprogrammed) in the

22 T8xC51SND1

Rev. D – 15-Nov-01 8. In System & In Application Programming

8.1 Introduction

As described in the section “Program/Code Memory” of the T8xC51SND1 design guide, The T89C51SND1 implements a 4 Kbytes FLASH boot memory. This boot memory is delivered programmed with a standard boot loader software allowing In System Pro- gramming (ISP). It also contains some Application Programming Interface routines named API routines allowing In Application Programming (IAP) by using user ’s own boot loader.

8.2 In System Programming

The ISP boot process is divided in two different processes: the hardware and software boot process detailed in the following sections. 8.3.1 Hardware Boot Process As detailed in Figure 8 there are two hardware conditions that allow user executing the boot loader: the hardware and the programmed conditions. Hardware condition The hardware condition is based on the ISP# pin. When driving this pin to low level, the chip reset forces the execution of the boot loader software. The hardware condition takes precedence on the programmed condition and always allows in system recovery when user’s memory has been corrupted. Programmed Condition The programmed condition is based on the Boot Loader Jump Bit (BLJB) in the hard- ware security bytes (HSB). When this bit is programmed (by hardware or software programming mode), the chip reset forces the execution of the boot loader software. 8.4.2 Software Boot Process Whatever the physical medium may be, the boot loader software always starts execu- tion by testing FCON to know if execution comes from hardware or programmed condition. If it is from hardware condition, the Atmel ’s boot loader is executed. If it is from programmed condition, the Software Boot Vector (SBV) is used to build a 16-bit address, SBV content being the MSB and the LSB being 00h. If this address is valid (< F000h), jump is done to this address to execute user ’s boot loader. Otherwise jump is done to the Atmel ’s boot loader. This implies that user ’s boot loader does not execute any code mapped from F000h to FFFFh.

Figure 8. Boot Process Algorithm

24 T8xC51SND1

8.5 Serial Boot Loader

8.6.1 Configuration The serial boot loader is based on the internal UART and needs only 3 pins: the TXD

and RXD pins of the UART and the VSS pin. The data transmission format on the serial link must be set to 8 data bits with 1 stop bit. The baud rate is automatically recognized during the synchronization phase. chronization by responding the same “U” character.

8.8.3 Command Protocol

checksum computed on the SIZE, ADDRESS, TYPE, DATA fields. Table 34. Hex Record Format ter followed by a CRLF sequence. “P” Not done. Part protected (secured by level 1 or 2).

Rev. D – 15-Nov-01 03h 02h XXXX Block Erase: DATA[0]= 01h DATA[1]= 00h Erase block 0 from address 0000h to 1FFFh. DATA[1]= 20h Erase block 1 from address 2000h to 3FFFh. DATA[1]= 40h Erase block 2 from address 4000h to 7FFFh. DATA[1]= 80h Erase block 3 from address 8000h to BFFFh. DATA[1]= C0h Erase block 4 from address C000h to FFFFh. Return “.” Done. “P” Not done. Part protected (secured by level 1 or 2). 01h XXXX Reset Software Boot Vector and Boot Status Byte: DATA[0]= 04h Set SBV to F0h and BSB to FFh. Return “.” Done. “P” Not done. Part protected (secured by level 1 or 2). 02h XXXX Program Software Security Bits: DATA[0]= 05h DATA[1]= 00h Program level 1. Disable FLASH programming. DATA[1]= 01h Program level 2. Disable FLASH programming & verifying. Return “.” Done. “P” Not done. Part protected (secured by level 1 or 2). 03h XXXX Program Software Boot Vector or Boot Status Byte: DATA[0]= 06h DATA[1]= 00h Program BSB with DATA[2]. DATA[1]= 01h Program SBV with DATA[2]. Return “.” Done. “P” Not done. Part already protected (secured by level 2). 01h XXXX Full Chip Erase: DATA[0]= 07h Erase user memory from address 0000h to FFFFh. Set SBV to F0h and BSB to FFh. Program software security to level 0. Return “.” 03h XXXX Program Fuse bits: DATA[0]= 0Ah DATA[1]= 04h DATA[2]= 00h Program BLJB bit. DATA[2]= 01h Erase BLJB bit. DATA[1]= 08h DATA[2]= 00h Program X2 bit. DATA[2]= 01h Erase X2 bit. Return “.” Done. “P” Not done. Part protected (secured by level 1 or 2). TYPE SIZE ADDRESS Description

26 T8xC51SND1

Rev. D – 15-Nov-01 04h 05h XXXX Read Data: DATA[4]= 00h Read data from address given by DATA[1:0] (start address) to address given by DATA[3:2] (end address). Return “AAAA=DD… DD” up to 16 data bytes by line. 05h XXXX Blank Check: DATA[4]= 01h Check blanked data from address given by DATA[1:0] (start address) to address given by DATA[3:2] (end address). Return “.” Done. “XXXX” First address not blanked. 05h 02h XXXX Read Id: DATA[0]= 00h DATA[1]= 00h Return manufacturer id. DATA[1]= 01h Return device id 1. DATA[1]= 02h Return device id 2. DATA[1]= 03h Return device id 3. Return “XX” Selected id value. 02h XXXX Read Special Bytes: DATA[0]= 07h DATA[1]= 00h Return SSB. DATA[1]= 01h Return BSB. DATA[1]= 02h Return SBV. Return “XX” Selected byte value. 01h XXXX Read HSB: DATA[0]= 0Bh Return HSB. Return “XX” HSB value. 02h XXXX Read Boot Id: DATA[0]= 0Eh DATA[1]= 00h Return boot id 1. DATA[1]= 01h Return boot id 1. Return “XX” Selected id value. 01h XXXX Read Boot Loader Version: DATA[0]= 0Fh Return boot loader version. Return “XX” Boot loader version. TYPE SIZE ADDRESS Description

8.9 In Application Programming

called by the user’s boot loader to allow programming of the FLASH memory. passed in registers as detailed in Table 36. Table 36. API Routines and Parameters Program a data in the FLASH memory at a given address. DPTR Address of the byte to program. Program a page of data in the FLASH memory at a given page address. DPTR0 Address of the page to program. DPTR1 Address in ERAM of the first data to program. ACC Number of bytes to program limited to 128. DPL 00h Program level 1. Disable FLASH programming. 01h Program level 2. Disable FLASH programming & verifying. DPL 00h Select BSB programming. DPL 01h Select SBV programming. DPL 04h Select BLJB programming.

28 T8xC51SND1

Rev. D – 15-Nov-01 06h PROGRAM X2 BIT Program X2B. Parameters DPL 08h Select X2B programming. ACC 00h Program X2B. 01h Erase X2B. Return None. 01h Erase BLOCK Erase one of the 5 available blocks. Parameters DPH 00h Erase block 0 from address 0000h to 1FFFh. 20h Erase block 1 from address 2000h to 3FFFh. 40h Erase block 2 from address 4000h to 7FFFh. 80h Erase block 3 from address 8000h to BFFFh. C0h Erase block 4 from address C000h to FFFFh. Return None. 04h ERASE SOFTWARE BOOT VECTOR and BOOT STATUS BYTE Erase SBV and BSB. Parameters None. Return None. 03h READ DATA BYTE Read data at a given address. Parameters DPTR Address of the byte to program. Return ACC Data read. 00h READ MANUFACTURER ID Read manufacturer Id. Parameters DPL 00h Select manufacturer Id. Return ACC Id value. 00h READ DEVICE ID 1 Read device Id 1 Parameters DPL 01h Select device Id 1. Return ACC Id value. 00h READ DEVICE ID 2 Read device Id 2. Parameters DPL 02h Select device Id 2. Return ACC Id value. R1 Description

Rev. D – 15-Nov-01 00h READ DEVICE ID 3 Read device Id 3. Parameters DPL 03h Select device Id 3. Return ACC Id value. 07h READ SOFTWARE SECURITY BYTE Read SSB. Parameters DPL 00h Select SSB. Return ACC SSB value. 07h READ BOOT STATUS BYTE Read BSB. Parameters DPL 01h Select BSB. Return ACC BSB value. 07h READ SOFTWARE BOOT VECTOR Read SBV. Parameters DPL 02h Select SBV. Return ACC SBV value. 0Bh READ HARDWARE SECURITY BYTE Read HSB. Parameters None. Return ACC HSB value. 0Eh READ BOOT ID 1 Read boot Id 1. Parameters DPL 00h Select boot Id 1. Return ACC Id value. 0Eh READ BOOT ID 2 Read boot Id 2. Parameters DPL 01h Select boot Id 2. Return ACC Id value. 0Fh READ BOOT LOADER VERSION Read BLV. Parameters None. Return ACC BLV value. R1 Description

30 T8xC51SND1

Rev. D – 15-Nov-01 9. Peripherals The T8xC51SND1 peripherals are briefly described in the following sections. For further details on how to interface (hardware and software) to these peripherals, please refer to the T8xC51SND1 design guide.

9.1 Clock Generator System

The T8xC51SND1 internal clocks are extracted from an on-chip PLL fed by an on-chip oscillator. Four clocks are generated respectively for the C51 core, the MP3 decoder, the audio interface, and the other peripherals. The C51 and peripheral clocks are derived from the oscillator clock. The MP3 decoder clock is generated by dividing the PLL output clock. The audio interface sample rates are also obtained by dividing the PLL output clock.

9.2 Ports

The T8xC51SND1 implements five 8-bit ports (P0 to P4) and one 4-bit port (P5). In addi- tion to performing general-purpose I/O, some ports are capable of external data memory operations; others allow for alternate functions. All I/O Ports are bidirectional. Each Port contains a latch, an output driver and an input buffer. Port 0 and Port 2 output drivers and input buffers facilitate external memory operations. Some Port 1, Port 3 and Port 4 pins serve for both general-purpose I/O and alternate functions.

9.3 Timers/Counters

The T8xC51SND1 implements the two general-purpose, 16-bit Timers/Counters of a standard C51. They are identified as Timer 0, Timer 1, and can independently be config- ured each to operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, a Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, a Timer/Counter counts neg- ative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request.

9.4 Watchdog Timer

The T8xC51SND1 implements a hardware Watchdog Timer that automatically resets the chip if it is allowed to time out. The WDT provides a means of recovering from rou- tines that do not complete successfully due to software or hardware malfunctions.

9.5 MP3 Decoder

The T8xC51SND1 implements a MPEG I/II audio layer 3 decoder (known as MP3 decoder). In MPEG I (ISO 11172-3) three layers of compression have been standardized support- ing three sampling frequencies: 48, 44.1, and 32 KHz. Among these layers, layer 3 allows highest compression rate of about 12:1 while still maintaining CD audio quality. For example, 3 minutes of CD audio (16-bit PCM, 44.1 KHz) data, which needs about 32 MBytes of storage, can be encoded into only 2.7 MBytes of MPEG I audio layer 3 data. In MPEG II (ISO 13818-3), three additional sampling frequencies: 24, 22.05, and 16 KHz are supported for low bit rates applications. The T8xC51SND1 can decode in real-time the MPEG I audio layer 3 encoded data into a PCM audio data, and also supports MPEG II audio layer 3 additional frequencies.

Rev. D – 15-Nov-01 Additional features are supported by the T8xC51SND1 MP3 decoder such as volume, bass, medium, and treble controls, bass boost effect and ancillary data extraction.

9.6 Audio Output Interface

The T8xC51SND1 implements an audio output interface allowing the decoded audio bit- stream to be output in various formats. It is compatible with right and left justification PCM and I 2S formats and thanks to the on-chip PLL (see Section 9.1) allows connection of almost all of the commercial audio DAC families available on the market.

9.7 Universal Serial Bus Interface

The T8xC51SND1 implements a full speed Universal Serial Bus Interface. It can be used for the following purposes:  Download of MP3 encoded audio files by supporting the USB mass storage class.  In System Programming by supporting the USB firmware upgrade class.

9.8 MultiMediaCard Interface

The T8xC51SND1 implements a MultiMediaCard (MMC) interface compliant to the V2.2 specification in MultiMediaCard Mode. The MMC allows storage of MP3 encoded audio files in removable flash memory cards that can be easily plugged or removed from the application. It can also be used for In System Programming.

9.9 IDE/ATAPI interface

The T8xC51SND1 provides an IDE/ATAPI interface allowing connexion of devices such as CD-ROM reader, CompactFlash cards, Hard Disk Drive … It consists in a 16-bit bidi- rectional bus part of the low-level ANSI ATA/ATAPI specification. It is provided for mass storage interface but could be used for In System Programming using CD-ROM.

9.10 Serial I/O Interface

The T8xC51SND1 implements a serial port with its own baud rate generator providing one single synchronous communication mode and three full-duplex Universal Asynchro- nous Receiver Transmitter (UART) communication modes. It is provided for the following purposes:  In System Programming.  Remote control of the T8xC51SND1 by a host.

9.11 Serial Peripheral Interface

The T8xC51SND1 implements a Serial Peripheral Interface (SPI) supporting master and slave modes. It is provided for the following purposes:  Interfacing DataFlash memory for MP3 encoded audio files storage.  Remote control of the T8xC51SND1 by a host.  In System Programming.

32 T8xC51SND1

Rev. D – 15-Nov-01 9.12 2-wire Controller The T8xC51SND1 implements a 2-wire controller supporting the four standard master and slave modes with multimaster capability. It is provided for the following purposes:  Connection of slave devices like LCD controller, audio DAC…  Remote control of the T8xC51SND1 by a host.  In System Programming.

9.13 A/D Controller

The T8xC51SND1 implements a 2-channel 10-bit (8 true bits) analog to digital converter (ADC). It is provided for the following purposes:  Battery monitoring.  Voice recording.  Corded remote control.

9.14 Keyboard Interface

The T8xC51SND1 implements a keyboard interface allowing connection of 4 x n matrix keyboard. It is based on 4 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1.3:0 and allow exit from idle and power down modes.

1. Absolute Maximum Rating and Operating Conditions

10.1 Absolute Maximum Rating

Table 37. Absolute Maximum Ratings

10.2 Operating Conditions

Table 38. Operating Conditions

34 T8xC51SND1

11.1 DC Characteristics - Digital Logic

Table 39. Digital DC Characteristics there is no guarantee on these values.

0.45 V I

Figure 9. IDD/IDL Versus XTAL Frequency; VDD= 2.7 to 3.3 V

11.2 DC Characteristics - IDD, IDL and IPD Test Conditions

Figure 10. IDD Test Condition, Active Mode Figure 11. IDL Test Condition, Idle Mode

36 T8xC51SND1

Figure 12. IPD Test Condition, Power-Down Mode

11.3 DC Characteristics - A to D Converter

Table 40. A to D Converter DC Characteristics

11.4 DC Characteristics - Oscillator & Crystal

cial cases (max 10 pF). X1 and X2 may not be used to drive other circuits.

2.4 AV DD

38 T8xC51SND1

Rev. D – 15-Nov-01

11.7 DC Characteristics - Phase Lock Loop

11.8.1 Schematic Figure 14. PLL Filter Connection 11.9.2 Parameters Table 42. PLL Filter Characteristics VDD= 2.7 to 3.3 V, TA= -40 to +85°C

11.10 DC Characteristics - In System Programming

11.11.1 Schematic Figure 15. ISP Pull-Down Connection 11.12.2 Parameters Table 43. ISP Pull-Down Characteristics VDD= 2.7 to 3.3 V, TA= -40 to +85°C VSS PFILT R VSS Symbol Parameter Min Typ Max Unit R Filter Resistor 100 Ω C1 Filter Capacitance 1 10 nF C2 Filter Capacitance 2 2.2 nF VSS ISP# RISP Symbol Parameter Min Typ Max Unit RISP ISP Pull-Down Resistor 2.2 K Ω

12.1 AC Characteristics - External 8-bit Bus Cycles

12.3.2 Timings Test conditions: capacitive load on all pins= 50 pF. Table 45. External 8-bit Bus Cycle - Data Read AC Timings

40 T8xC51SND1

Table 46. External 8-bit Bus Cycle - Data Write AC Timings Figure 17. External 8-bit Bus Cycle - Data Write Waveforms

Rev. D – 15-Nov-01 TWHLH TAVWL TLLAX TWHQX WR# ALE TLHLL TWLWH A15:8 TAVLL TQVWH D7:0 Data Out TLLWL A7:0

42 T8xC51SND1

12.5 AC Characteristics - External IDE 16-bit Bus Cycles

12.7.2 Timings Test conditions: capacitive load on all pins= 50 pF. Table 48. External IDE 16-bit Bus Cycle - Data Read AC Timings

Table 49. External IDE 16-bit Bus Cycle - Data Write AC Timings Note: D15:8 is written in DAT16H SFR.

44 T8xC51SND1

Figure 19. External IDE 16-bit Bus Cycle - Data Write Waveforms Note: D15:8 is the content of DAT16H SFR.

12.9 AC Characteristics - SPI Interface

12.11.2 Timings Test conditions: capacitive load on all pins= 100 pF. Table 51. SPI Interface Master AC Timing Notes: 1. Value of this parameter depends on software.

46 T8xC51SND1

Note: Not Defined but generally the MSB of the character which has just been received. Figure 21. SPI Slave Waveforms (SSCPHA= 1) Note: Not Defined but generally the LSB of the character which has just been received.

48 T8xC51SND1

Rev. D – 15-Nov-01

12.13 AC Characteristics - 2-wire Interface

12.14.1 Timings Table 52. 2-wire Interface AC Timing VDD= 2.7 to 3.3 V, TA= -40 to +85°C Notes: 1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 µs. 3. Spikes on the SDA and SCL lines with a duration of less than 3 ·TCLCL will be filtered out. Maximum capacitance on bus-lines SDA and SCL= 400 pF. 4. T CLCL= TOSC= one oscillator clock period. 12.15.2 Waveforms Figure 24. 2-wire Waveforms Symbol Parameter INPUT M i n Max OUTPUT Mi n Max THD; STA Start condition hold time 14 ·TCLCL(4) 4.0 µs(1) TLOW SCL low time 16 ·TCLCL(4) 4.7 µs(1) THIGH SCL high time 14 ·TCLCL(4) 4.0 µs(1) TRC SCL rise time 1 µs- (2) TFC SCL fall time 0.3 µs0 . 3 µs(3) TSU; DAT1 Data set-up time 250 ns 20 ·TCLCL(4)- TRD TSU; DAT2 SDA set-up time (before repeated START condition) 250 ns 1 µs(1) TSU; DAT3 SDA set-up time (before STOP condition) 250 ns 8 ·TCLCL(4) THD; DAT Data hold time 0 ns 8 ·TCLCL(4) - TFC TSU; STA Repeated START set-up time 14 ·TCLCL(4) 4.7 µs(1) TSU; STO STOP condition set-up time 14 ·TCLCL(4) 4.0 µs(1) TBUF Bus free time 14 ·TCLCL(4) 4.7 µs(1) TRD SDA rise time 1 µs - (2) TFD SDA fall time 0.3 µs0 . 3 µs(3) Tsu;DAT1 Tsu;STA Tsu;DAT/c21Thd;STA ThighTlow SDA (INPUT/OUTPUT) 0.3 VDD

0.7 VDD

TbufTsu;STO

0.3 VDD

(INPUT/OUTPUT) Thd;DAT Tsu;DAT3 START or Repeated START condition START condition STOP condition Repeated START condition

Rev. D – 15-Nov-01

12.16 AC Characteristics - MMC Interface

12.17.1 Definition of symbols Table 53. MMC Interface Timing Symbol Definitions 12.18.2 Timings Table 54. MMC Interface AC timings VDD= 2.7 to 3.3 V, TA= 0 to 70°C, CL ≤ 100pF (10 cards) 12.19.3 Waveforms Figure 25. MMC Input-Output Waveforms Signals Conditions C Clock H High D Data In L Low O Data Out V Valid X No Longer Valid Symbol Parameter Min Max Unit TCHCH Clock Period 50 ns TCHCX Clock High Time 10 ns TCLCX Clock Low Time 10 ns TCLCH Clock Rise Time 10 ns TCHCL Clock Fall Time 10 ns TDVCH Input Data Valid to Clock High 3 ns TCHDX Input Data Hold after Clock High 3 ns TCHOX Output Data Hold after Clock High 5 ns TOVCH Output Data Valid to Clock High 5 ns TIVCH MCLK MDAT Input TCHCH TCLCXTCHCX TCHCL TCLCH MCMD Input TCHIX TOVCH MDAT Output MCMD Output TCHOX

50 T8xC51SND1

Rev. D – 15-Nov-01

12.20 AC Characteristics - Audio Interface

12.21.1 Definition of symbols Table 55. Audio Interface Timing Symbol Definitions 12.22.2 Timings Table 56. Audio Interface AC timings VDD= 2.7 to 3.3 V, TA= 0 to 70°C, CL≤ 30pF Notes: 1. 32-bit format with Fs= 48 KHz. 12.23.3 Waveforms Figure 26. Audio Interface Waveforms Signals Conditions C Clock H High O Data Out L Low S Data Select V Valid X No Longer Valid Symbol Parameter Min Max Unit TCHCH Clock Period 325.5 (1) ns TCHCX Clock High Time 30 ns TCLCX Clock Low Time 30 ns TCLCH Clock Rise Time 10 ns TCHCL Clock Fall Time 10 ns TCLSV Clock Low to Select Valid 10 ns TCLOV Clock Low to Data Valid 10 ns DCLK TCHCH TCLCXTCHCX TCLCHTCHCL DSEL DDAT Right Left TCLSV TCLOV

Rev. D – 15-Nov-01

12.24 AC Characteristics - Analog to Digital Converter

12.25.1 Definition of symbols Table 57. Analog to Digital Converter Timing Symbol Definitions 12.26.2 Characteristics Table 58. Analog to Digital Converter AC Characteristics VDD= 2.7 to 3.3 V, TA= 0 to 70°C Notes: 1. AV DD= AVREFP= 3.0 V, AVSS= AVREFN= 0 V. ADC is monotonic with no missing code. 2. The differential non-linearity is the difference between the actual step width and the ideal step width (see Figure 28). 3. The integral non-linearity is the peak difference between the center of the actual step and the ideal transfer curve after appropriate adjustment of gain and offset errors (see Figure 28). 4. The offset error is the absolute difference between the straight line which fits the actual transfer curve (after removing of gain error), and the straight line which fits the ideal transfer curve (see Figure 28). 5. The gain error is the relative difference in percent between the straight line which fits the actual transfer curve (after removing of offset error), and the straight line which fits the ideal transfer curve (see Figure 28). 12.27.3 Waveforms Figure 27. Analog to Digital Converter Internal Waveforms Signals Conditions C Clock H High E Enable (ADEN bit) L Low S Start Conversion (ADSST bit) Symbol Parameter Min Max Unit TCLCL Clock Period 1.43 µs TEHSH Start-up Time 4 µs TSHSL Conversion Time 11 ·TCLCL µs DLe Differential non- linearity error1, 2 TBD LSB ILe Integral non- linearity error1, 3 TBD LSB OSe Offset error 1, 4 TBD LSB Ge Gain error 1, 5 TBD % ADEN Bit ADSST Bit TEHSH TSHSL CLK TCLCL

52 T8xC51SND1

Figure 28. Analog to Digital Converter Characteristics

12.28 AC Characteristics - FLASH Memory

1 LSB

Note: ISP# must be driven through a pull-down resistor (see Section 11.10, page 38). Figure 30. FLASH Memory - Internal Busy Waveforms

12.32 AC Characteristics - External Clock Drive and Logic Level References

12.35.3 Waveforms

Figure 31. External Clock Waveform

54 T8xC51SND1

Figure 32. AC Testing Input/Output Waveforms

1. Timing measurements are made on all outputs at V IH min for a logic 1 and VIL max for

Figure 33. Float Waveforms occurs with IOL/IOH= ±20 mA.

13.1 List of Packages

13.2 TQFP80 - Mechanical Outline

Figure 34. TQFP80 - Mechanical Outline

56 T8xC51SND1

13.3 PLCC84 - Mechanical Outline

Figure 35. PLCC84 - Mechanical Outline

Rev. D – 15-Nov-01 14. Ordering Information (*)check for availability. PLCC84 package only available for development board. Part-number Memory size Supply voltage Temperature range Max frequency Package Packing T89C51SND1- ROTIL 64K Flash 3V Industrial 40MHZ TQFP80 Tray T83C51SND1*- ROTIL 64K ROM 3V Industrial 40MHZ TQFP80 Tray

i T8xC51SND1 Rev. D – 15-Nov-01 Table of Contents

Rev. D – 15-Nov-01 12.9 AC Characteristics - External Clock Drive and Logic Level References .53

© Atmel Nantes SA, 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company ’s standard warranty which is detailed in Atmel ’s Terms and Conditions located on the Company ’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without n otice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of At mel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel ’s products are not authorized for use as critical components in life support devices or systems. Atmel Sales Offices France 3, Avenue du Centre 78054 St.-Quentin-en-Yvelines Cedex France Tel: 33130 60 70 00 Fax: 33130 60 71 11 Germany Erfurter Strasse 31

85386 Eching

Tel: 49893 19 70 0 Fax: 49893 19 46 21 Kruppstrasse 6

45128 Essen

Tel: 492 012 47 30 0 Fax: 492 012 47 30 47 Theresienstrasse 2

74072 Heilbronn

Tel: 4971 3167 36 36 Fax: 4971 3167 31 63 Italy Via Grosio, 10/8

20151 Milano

Tel: 390238037-1 Fax: 390238037-234 Spain Principe de Vergara, 112

28002 Madrid

Tel: 3491564 51 81 Fax: 3491562 75 14 Sweden Kavallerivaegen 24, Rissne

17402 Sundbyberg

Tel: 468587 48 800 Fax: 468587 48 850 United Kingdom Easthampstead Road Bracknell, Berkshire RG12 1LX United Kingdom Tel: 441344707 300 Fax: 441344427 371 USA

2325 Orchard Parkway

Tel: 1408441 0311 Fax: 1408436 4200

1465 Route 31, 5th Floor

Tel: 1908848 5208 Fax: 1908848 5232 Hong Kong 77 Mody Rd., Tsimshatsui East, Rm.1219 East Kowloon Hong Kong Tel: 85223789 789 Fax: 85223755 733 Korea Ste.605,Singsong Bldg. Young- deungpo-ku 150-010 Seoul Korea Tel: 8227851136 Fax: 8227851137 Singapore

25 Tampines Street 92

Rep. of Singapore Tel: 65260 8223 Fax: 65787 9819 Taiwan Wen Hwa 2 Road, Lin Kou Hsiang

244 Taipei Hsien 244

Taiwan, R.O.C. Tel: 88622609 5581 Fax: 88622600 2735 Japan 1-24-8 Shinkawa, Chuo-Ku 104-0033 Tokyo Japan Tel: 8133523 3551 Fax: 8133523 7581 Web site http://www.atmel-wm.com Printed on recycled paper.