T89C51RC2 ATMEL | Alldatasheet

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Rev. B - 30-Mar-01 1 Preliminary T89C51RB2/RC2 8-bit Microcontroller with 16 Kbytes/ 32 Kbytes FLASH 1. Description T89C51RB2/RC2 is a high performance FLASH version of the 80C51 8-bit microcontrollers. It contains a 16K or 32Kbytes Flash memory block for program and data. The 16 Kbytes or 32 Kbytes FLASH memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard V CC pin. The T89C51RB2/RC2 retains all features of the 80C52 with 256 bytes of internal RAM, a 7-source 4-level interrupt controller and three timer/counters. In addition, the T89C51RB2/RC2 has a Programmable Counter Array, an XRAM of 1024 byte, a Hardware Watchdog Timer, a Keyboard Interface, a SPI Interface, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improvement mechanism (X2 mode). Pinout is the standard 40/44 pins of the C52. The fully static design of the T89C51RB2/RC2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The T89C51RB2/RC2 has 2 software-selectable modes of reduced activity and 8 bit clock prescaler for further reduction in power consumption. In the Idle mode the CPU is frozen while the peripherals and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. The added features of the T89C51RB2/RC2 make it more powerful for applications that need pulse width modulation, high speed I/O and counting capabilities such as alarms, motor control, corded phones, smart card readers. 2. Features

  • 80C52 Compatible
  • 8051 pin and instruction compatible
  • Four 8-bit I/O ports
  • Three 16-bit timer/counters
  • 256 bytes scratch pad RAM
  • 10 Interrupt sources with 4 priority levels
  • Dual Data Pointer
  • Variable length MOVX for slow RAM/peripherals
  • ISP (In System Programming) using standard V CC power supply.
  • Boot ROM contains low level FLASH programming routines and a default serial loader
  • High-Speed Architecture
  • 40 MHz in standard mode
  • 20 MHz in X2 mode (6 clocks/machine cycle)
  • 16K/32K bytes on-chip FLASH program / data Memory
  • Byte and page (128 bytes) erase and write
  • 100k write cycles
  • On-chip 1024 bytes expanded RAM (XRAM)
  • Software selectable size (0, 256, 512, 768, 1024 bytes)
  • 256 bytes selected at reset for TS87C51RB2/RC2 compatibility
  • Keyboard interrupt interface on port P1
  • SPI Interface (Master / Slave Mode)
  • 8-bit clock prescaler
  • Improved X2 mode with independant selection for CPU and each peripheral
  • Programmable Counter Array 5 Channels with:
  • High Speed Output,
  • Compare / Capture,
  • Pulse Width Modulator,
  • Watchdog Timer Capabilities
  • Asynchronous port reset
  • Full duplex Enhanced UART
  • Dedicated Baud Rate Generator for UART
  • Low EMI (inhibit ALE)
  • Hardware Watchdog Timer (One-time enabled with Reset-Out)
  • Power control modes:
  • Idle Mode.
  • Power-down mode. -5 0 µA at 3V - 100 µA Commercial at 5V - 150 µA Industrial at 5V
  • Power-Off Flag.
  • Power supply: 4.5 to 5.5V or 2.7 to 3.6V
  • Temperature ranges: Commercial (0 to +70 °C) and industrial (-40 °C to +85 °C).
  • Packages: PDIL40, PLCC44, VQFP44

Table 1. Memory Size

Rev. B - 30-Mar-01 3 Preliminary T89C51RB2/RC2 4. SFR Mapping The Special Function Registers (SFRs) of the T89C51RB2/RC2 fall into the following categories:

  • C51 core registers: ACC, B, DPH, DPL, PSW, SP
  • I/O port registers: P0, P1, P2, P3
  • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H
  • Serial I/O port registers: SADDR, SADEN, SBUF, SCON
  • PCA ( Programmable Counter Array ) registers : CCON , CCAPMx , CL , CH , CCAPxH , CCAPxL (x : 0 to 4)
  • Power and clock control registers: PCON
  • Hardware Watchdog Timer registers : WDTRST, WDTPRG
  • Interrupt system registers: IE0, IPL0, IPH0 , IE1 , IPL1 , IPH1
  • Keyboard Interface registers : KBE , KBF , KBLS
  • SPI registers : SPCON , SPSTR , SPDAT
  • BRG ( Baud Rate Generator ) registers : BRL , BDRCON
  • Flash register : FCON
  • Clock Prescaler register : CKRL
  • Others: AUXR, AUXR1 , CKCON0 , CKCON1

Table 2. Sfr mapping Table below shows all SFRs with their address and their reset value. (1) FCON access is reserved for the FLASH API and ISP software.

Rev. B - 30-Mar-01 5 Preliminary T89C51RB2/RC2 5. Pin Configurations P1.7CEX4/MOSI P1.4/CEX1 RST P3.0/RxD P3.1/TxD P1.3CEX0 P1.5/CEX2/MISO P1.6/CEX3/SCK P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0/AD8 P2.1/AD9 P2.2/AD10 P2.3/AD11 P2.4/AD12 P0.4/AD4 P0.6/AD6 P0.5/AD5 P0.7/AD7 ALE/PROG PSEN EA P2.7/AD15 P2.5/AD13 P2.6/AD14 P1.0/T2 P1.2/ECI P1.1/T2EX/SS VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 PDIL40 43 42 41 40 3944 38 37 36 35 34 P1.4/CEX1 P1.0/T2 P1.1/T2EX/SS P1.3/CEX0 P1.2/ECI NIC* VCC P0.0/AD0 P0.2/AD2 P0.3/AD3 P0.1/AD1 P0.4/AD4 P0.6/AD6 P0.5/AD5 P0.7/AD7 ALE/PROG PSEN EA NIC* P2.7/A15 P2.5/A13 P2.6/A14 P1.5/CEX2/MISO P1.6/CEX3/SCK P1.7/CEX4/MOSI RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XT AL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 NIC* 12 13 17 161514 20 1918 21 22 VQFP44 1.4 18 19 23 222120 26 2524 27 28 5 4 3 2 1 6 44 43 42 41 40 P1.4/CEX1 P1.0/T2 P1.1/T2EX/SS P1.3/CEX0 P1.2/ECI NIC* VCC P0.0/AD0 P0.2/AD2 P0.1/AD1 P0.4/AD4 P0.6/AD6 P0.5/AD5 P0.7/AD7 ALE/PROG PSEN EA NIC* P2.7/A15 P2.5/A13 P2.6/A14 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P1.5/CEX2/MISO P1.6/CEX3/SCK P1.7/CEx4/MOSI RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P0.3/AD3 NIC* PLCC44 *NIC: No Internal Connection

Table 3. Pin Description for 40/44 pin packages have 1s written to them float and can be used as high impedance inputs. I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. programming and verification. When SPI is is in master mode , MOSI outputs data to the slave peripheral. internal clock generator circuits.

Rev. B - 30-Mar-01 7 Preliminary T89C51RB2/RC2 Mnemonic Pin Number Type Name and FunctionDIL LCC VQFP44 1.4 P2.0-P2.7 21-28 24-31 18-25 I/O Port 2 : Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull- ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some Port 2 pins receive the high order address bits during EPROM programming and verification: P2.0 to P2.5 for 16Kb devices P2.0 to P2.6 for 32Kb devices 13-19 7-13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull- ups. Port 3 also serves the special features of the 80C51 family, as listed below. 10 11 5 I RXD (P3.0): Serial input port 11 13 7 O TXD (P3.1): Serial output port 12 14 8 I INT0 (P3.2): External interrupt 0 13 15 9 I INT1 (P3.3): External interrupt 1 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe RST 9 10 4 I/O Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to V SS permits a power-on reset using only an external capacitor to V CC. This pin is an output when the hardware watchdog forces a system reset. ALE/PROG 30 33 27 O (I) Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG ) during Flash programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches. PSEN 29 32 26 O Program Strobe ENable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA 31 35 29 I External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to FFFFH (RD). If security level 1 is programmed, EA will be internally latched on Reset.

Rev. B - 30-Mar-01 8 Preliminary T89C51RB2/RC2 6. Ordering Information Packages: 3C: PDIL40 SL: PLCC44 RL: VQFP44 (1.4mm) T -M: VCC: 5V

40 MHz, X1 mode

20 MHz, X2 mode

-L: VCC: 3 V S Temperature Range C:Commercial 0 to 70oC I:Industrial -40 to 85oC -3C Conditioning S: Stick T: Tray B: Blue Tape W: Wafer M89C51Rx2 C 89C51RC2 ( 32k Flash ) 89C51RB2 ( 16k Flash )

Table 4. Possible order entries