T89C51CC02CA-TDSIM

T89C51CC02 ATMEL | Alldatasheet

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Technical content

Datasheet sections

Features

• 80C51 Core Architecture
• 256 Bytes of On-chip RAM
• 256 Bytes of On-chip XRAM
• 16K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Erase/Write Cycle: 100K
• Boot Code Section with Independent Lock Bits
• 2K Bytes of On-chip Flash for Bootloader
• In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability
• 2K Bytes of On-chip EEPROM – Erase/Write Cycle: 100K
• 14-sources 4-level Interrupts
• Three 16-bit Timers/Counters
• Full Duplex UART Compatible 80C51
• Maximum Crystal Frequency 40 MHz. In X2 Mode, 20 MHz (CPU Core, 40 MHz)
• Three or Four Ports: 16 or 20 Digital I/O Lines
• Two-channel 16-bit PCA – PWM (8-bit) – High-speed Output – Timer and Edge Capture
• Double Data Pointer
• 21-bit Watchdog Timer (7 Programmable bits)
• A 10-bit Resolution Analog-to-Digital Converter (ADC) with 8 Multiplexed Inputs
• Full CAN Controller – Fully Compliant with CAN rev.# 2.0A and 2.0B – Optimized Structure for Communication Management (Via SFR) – 4 Independent Message Objects -Each Message Object Programmable on Transmission or Reception -Individual Tag and Mask Filters up to 29-bit Identifier/Channel -8-byte Cyclic Data Register (FIFO)/Message Object -16-bit Status and Control Register/Message Object -16-bit Time-Stamping Register/Message Object -CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message Object -Access to Message Object Control and Data Registers Via SFR -Programmable Reception Buffer Length up to 4 Message Objects -Priority Management of Reception of Hits on Several Message Objects Simultaneously (Basic CAN Feature) -Priority Management for Transmission -Message Object Overrun Interrupt – Supports -Time Triggered Communication -Autobaud and Listening Mode -Programmable Automatic Reply Mode
• 1-Mbit/s Maximum Transfer Rate at 8 MHz(1) Crystal Frequency In X2 Mode
• Readable Error Counters
• Programmable Link to On-chip Timer for Time Stamping and Network Synchronization
• Independent Baud Rate Prescaler
• Data, Remote, Error and Overload Frame Handling
• Power-saving Modes – Idle Mode – Power-down Mode Enhanced 8-bit Microcontroller with CAN Controller and Flash T89C51CC02

4126H–CAN–01/05

• Power Supply: 3 Volts to 5.5 Volts
• Temperature Range: Industrial (-40° to +85°C)
• Packages: SOIC28, SOIC24, PLCC28, VQFP32 Note: 1. At BRP = 1 sampling point will be fixed.

Description

Part of the CANaryTM family of 8-bit microcontrollers dedicated to CAN network applica- tions, the T89C51CC02 is a low-pin count 8-bit Flash microcontroller. In X2 Mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time. Besides the full CAN controller T89C51CC02 provides 16K Bytes of Flash memory including In-System Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes EEPROM and 512 Bytes RAM. Special attention is payed to the reduction of the electro-magnetic emission of T89C51CC02. Block Diagram Note: 1. 8 analog Inputs/8 Digital I/O. 2. 2-bit I/O Port. Timer 0 INT RAM 256x8 RxD TxD XTAL2 XTAL1 UART CPU Timer 1 INT1 Ctrl INT0 C51 CORE P2(2) Port 1 Port 2 Port 3 Parallel I/O Ports P1(1) XRAM 256 x 8 IB-bus PCA RESET Watch Dog PCA ECI Vss Vcc Timer 2 T2EX Port 4 P4(2) 10-bit ADC Flash 16K x Boot loader 2K x 8 EE PROM 2K x 8 CAN CONTROLLER TxDC RxDC VAVCC VAREF VAGND

4126H–CAN–01/05 Pin Configurations P3.4/T0 P3.3/INT1 P4.1/RxDC P3.7 P3.2/INT0 P1.5/AN5 P1.7/AN7 P1.6/AN6 P2.0 VAREF VAVCC VAGND P1.0/AN0/T2 P1.1/AN1/T2EX P1.2/AN2/ECI P1.3/AN3/CEX0 P1.4/AN4/CEX1 RESET VCC VSS P4.0/TxDC P2.1 P3.6 P3.5/T1 P3.1/TxD P3.0/RxD XTAL1 XTAL2 SO28 P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 P3.7 P4.0/TxDC P4.1/RxDC P2.1 P3.6 P2.0 P1.4/AN4/CEX1 P1.5/AN5 P1.6/AN6 P1.7/AN7 P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 VAVCC PLCC-28 P3.1/TxD P3.0/RxD P4.1/RxDC P3.4/T0 XTAL2 P1.5/AN5 P1.7/AN7 P1.6/AN6 RESET VAREF VAVCC VAGND P1.0/AN0/T2 P1.1/AN1/T2EX P1.2/AN2/ECI P1.3/AN3/CEX0 P1.4/AN4/CEX1 VSS XTAL1 VCC P4.0/TxDC P3.5/T1 P3.3/INT1 P3.2/INT0 SO24

4126H–CAN–01/05 P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 P3.7 P4.0/TxDC P4.1/RxDC P2.1 P3.6 P2.0 P1.4/AN4/CEX1 P1.5/AN5 P1.6/AN6 P1.7/AN7 P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 VAVCC QFP-32 NC NC NC NC

4126H–CAN–01/05 Pin Description Pin Name Type Reference Voltage for ADC (input) VAVCC Supply Voltage for ADC VAGND Reference Ground for ADC (internaly connected with the VSS) P1.0:7 I/O Port 1: Is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins can be used for digital input/output or as analog inputs for the Analog Digital Converter (ADC). Port 1 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 1 pins that are being pulled low externally will be the source of current (IIL, See section ’Electrical Characteristic’) because of the internal pull-ups. Port 1 pins are assigned to be used as analog inputs via the ADCCF register (in this case the internal pull-ups are disconnected). As a secondary digital function, port 1 contains the Timer 2 external trigger and clock input; the PCA external clock input and the PCA module I/O. P1.0/AN0/T2 Analog input channel 0, External clock input for Timer/counter2. P1.1/AN1/T2EX Analog input channel 1, Trigger input for Timer/counter2. P1.2/AN2/ECI Analog input channel 2, PCA external clock input. P1.3/AN3/CEX0 Analog input channel 3, PCA module 0 Entry of input/PWM output. P1.4/AN4/CEX1 Analog input channel 4, PCA module 1 Entry of input/PWM output. P1.5/AN5 Analog input channel 5, P1.6/AN6 Analog input channel 6, P1.7/AN7 Analog input channel 7, It can drive CMOS inputs without external pull-ups. P2.0:1 I/O Port 2: Is an 2-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-ups. In the T89C51CC02 Port 2 can sink or source 5mA. It can drive CMOS inputs without external pull-ups.

4126H–CAN–01/05 P3.0:7 I/O Port 3: Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pulled low externally will be a source of current (IIL, See section ’Electrical Characteristic’) because of the internal pull-ups. The output latch corresponding to a secondary function must be programmed to one for that function to operate (except for TxD and WR). The secondary functions are assigned to the pins of port 3 as follows: P3.0/RxD: Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface P3.1/TxD: Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface P3.2/INT0: External interrupt 0 input/timer 0 gate control input P3.3/INT1: External interrupt 1 input/timer 1 gate control input P3.4/T0: Timer 0 counter input P3.5/T1: Timer 1 counter input P3.6: Regular I/O port pin P3.7: Regular I/O port pin P4.0:1 I/O Port 4: Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-up transistor. The output latch corresponding to a secondary function RxDC must be programmed to one for that function to operate. The secondary functions are assigned to the two pins of port 4 as follows: P4.0/TxDC: Transmitter output of CAN controller P4.1/RxDC: Receiver input of CAN controller. It can drive CMOS inputs without external pull-ups. RESET I/O Reset: A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down resistor to VSS permits power-on reset using only an external capacitor to VCC. XTAL1 I XTAL1: Input of the inverting oscillator amplifier and input of the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle of 50% should be maintained. XTAL2 O XTAL2: Output from the inverting oscillator amplifier. Pin Name Type

4126H–CAN–01/05 Read-Modify-Write Instructions Some instructions read the latch data rather than the pin data. The latch based instruc- tions read the data, modify the data and then rewrite the latch. These are called ’Read- Modify-Write’ instructions. Below is a complete list of these special instructions (See Table 1). When the destination operand is a Port or a Port bit, these instructions read the latch rather than the pin: It is not obvious that the last three instructions in this list are Read-Modify-Write instruc- tions. These instructions read the port (all 8 bits), modify the specifically addressed bit and write the new byte back to the latch. These Read-Modify-Write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic) levels at the pin. For example, a Port bit used to drive the base of an external bipolar transistor cannot rise above the transistor’s base-emitter junction voltage (a value lower than VIL). With a logic one written to the bit, attempts by the CPU to read the Port at the pin are misinterpreted as logic zero. A read of the latch rather than the pins returns the correct logic one value. Quasi Bi-directional Port Operation Port 1, Port 3 and Port 4 have fixed internal pull-ups and are referred to as ’quasi-bidi- rectional’ Ports. When configured as an input, the pin impedance appears as logic one and sources current in response to an external logic zero condition. Resets write logic one to all Port latches. If logical zero is subsequently written to a Port latch, it can be returned to input conditions by a logic one written to the latch. Note: Port latch values change near the end of Read-Modify-Write insruction cycles. Output buffers (and therefore the pin state) are updated early in the instruction after Read-Mod- ify-Write instruction cycle. Logical zero-to-one transitions in Port 1, Port 3 and Port 4 use an additional pull-up (p1) to aid this logic transition See Figure 2. This increases switch speed. This extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pull-ups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses logic zero and off when the gate senses logic one. pFET #1 is turned on for two oscillator periods immediately after a zero-to-one transition in the Port latch. A logic one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter and pFET pair form a latch to drive logic one. pFET #2 is a very weak pull-up switched on whenever the Table 1. Read/Modify/Write Instructions ANL P1, A ORL Logical OR ORL P2, A XRL Logical EX-OR XRL P3, A JBC Jump if bit = 1 and clear bit JBC P1.1, LABEL CPL Complement bit CPL P3.0 INC Increment INC P2 DEC Decrement DEC P2 DJNZ Decrement and jump if not zero DJNZ P3, LABEL MOV Px.y, C Move carry bit to bit y of Port x MOV P1.5, C CLR Px.y Clear bit y of Port x CLR P2.4 SET Px.y Set bit y of Port x SET P3.3

strengths are 1/10 that of pFET #3. Figure 2. Internal Pull-up Configurations

Table 2. C51 Core SFRs Table 3. I/O Port SFRs Table 4. Timers SFRs

1 Modes

Table 4. Timers SFRs (Continued) Table 5. Serial I/O Port SFRs Table 6. PCA SFRs

Table 6. PCA SFRs (Continued) Table 7. Interrupt SFRs Table 8. ADC SFRs Table 9. CAN SFRs

Table 9. CAN SFRs (Continued)

Table 10. Other SFRs

1. These registers are bit-addressable.

whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF.

1. AUXR1 bit ENBOOT is initialized with the content of the BLJB bit inverted.

Table 11. SFR Mapping

4126H–CAN–01/05 Clock The T89C51CC02 core needs only 6 clock periods per machine cycle. This feature, called “X2”, provides the following advantages: Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. Saves power consumption while keeping the same CPU power (oscillator power saving). Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes. Increases CPU power by 2 while keeping the same crystal frequency. In order to keep the original C51 compatibility, a divider-by-2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by the software. An extra feature is available to start after Reset in the X2 Mode. This feature can be enabled by a bit X2B in the Hardware Security Byte. This bit is described in the section ’In-System Programming’. The X2 bit in the CKCON register (See Table 12) allows switching from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 Mode) for the CPU Clock only (See Figure 3). The Timers 0, 1 and 2, Uart, PCA, watchdog or CAN switch in X2 Mode only if the corre- sponding bit is cleared in the CKCON register. The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1 input. In X2 Mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 3. shows the clock generation block diagram. The X2 bit is validated on the XTAL1 ÷ 2 rising edge to avoid glitches when switching from the X2 to the STD mode. Figure 4 shows the mode switching waveforms.

Figure 3. Clock CPU Generation Diagram

Figure 4. Mode Switching Waveforms(1)

1. In order to prevent any incorrect operation while operating in the X2 Mode, users must be aware that all peripherals using

4126H–CAN–01/05 Register Table 12. CKCON Register

1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit

CAN Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. WDX2 Watchdog Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. PCAX2 Programmable Counter Array Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. SIX2 Enhanced UART clock (MODE 0 and 2) (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. T2X2 Timer 2 Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. T1X2 Timer 1 Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. T0X2 Timer 0 Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. CPU Clock Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6 clock periods per machine cycle (X2 Mode) and to enable the individual peripherals ’X2’ bits.

cally divided by 2 using the X2 Mode detailed in Section “Clock”. internal reset source such as a watchdog, PCA, timer, etc. The level on xtal1 input must be outside the specification (VIH, VIL). Oscillator startup time (oscrst). To determine the capacitor the highest value of these two parameters has to be chosen. The reset circuitry is shown in Figure 5. Figure 5. Reset Circuitry two values of oscillator start-up time and two pull-down resistor values. Table 13. Minimum Reset Capacitor for a 50K Pull-down Resistor

4126H–CAN–01/05 Reset Recommendation to Prevent Flash Corruption When a Flash program memory is embedded on-chip, it is strongly recommended to use an external reset chip (brown out device) to apply a reset (Figure 7). It prevents sys- tem malfunction during periods of insufficient power-supply voltage (power-supply failure, power supply switched off, etc.). Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode, program execution halts. Idle mode freezes the clock to the CPU at known states while the peripherals continue to be clocked. The CPU status before entering Idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The status of the Port pins during Idle mode is detailed in Table 13. Entering Idle Mode To enter Idle mode, set the IDL bit in PCON register (See Table 15). The T89C51CC02 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed. Note: If IDL bit and PD bit are set simultaneously, the T89C51CC02 enters Power-down mode. Then it does not go in Idle mode when exiting Power-down mode. Exiting Idle Mode There are two ways to exit Idle mode: Generate an enabled interrupt. Hardware clears IDL bit in PCON register which restores the clock to the CPU. Exe- cution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately follow- ing the instruction that activated Idle mode. The general purpose flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt occurred dur- ing normal operation or during Idle mode. When Idle mode is exited by an interrupt, the interrupt service routine may examine GF1 and GF0. Generate a reset. A logic high on the RST pin clears IDL bit in PCON register directly and asynchro- nously. This restores the clock to the CPU. Program execution momentarily resumes with the instruction immediately following the instruction that activated the Idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the T89C51CC02 and vectors the CPU to address C:0000h. Notes: 1. During the time that execution resumes, the internal RAM cannot be accessed; how- ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated Idle mode should not write to a Port pin or to the external RAM. 2. If Idle mode is invoked by ADC Idle, the ADC conversion completion will exit Idle. Power-down Mode The Power-down mode places the T89C51CC02 in a very low power state. Power-down mode stops the oscillator, freezes all clock at known states. The CPU status prior to entering Power-down mode is preserved, i.e., the program counter, program status word register retain their data for the duration of Power-down mode. In addition, the SFRs and RAM contents are preserved. The status of the Port pins during Power-down mode is detailed in Table 13. Entering Power-down Mode To enter Power-down mode, set PD bit in PCON register. The T89C51CC02 enters the Power-down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed.

VDD is restored to the normal operating level. Generate an enabled external interrupt. following the instruction that activated Power-down mode.

1. The external interrupt used to exit Power-down mode must be configured as level

the duration of the interrupt must be long enough to allow the oscillator to stabilize. The execution will only resume when the interrupt is deasserted.

1. Exit from power-down by external interrupt does not affect the SFRs nor the internal

Figure 8. Power-down Exit Waveform Using INT1:0#

1. During the time that execution resumes, the internal RAM cannot be accessed; how-

Power-down mode should not write to a Port pin or to the external RAM.

1. Exit from power-down by reset redefines all the SFRs, but does not affect the internal

4126H–CAN–01/05 Registers Table 15. PCON Register Set to select double baud rate in mode 1, 2 or 3. SMOD0 Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. Reserved The value read from this bit is indeterminate. Do not set this bit. POF Power-off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. GF1 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. GF0 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. PD Power-down Mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. IDL Idle Mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode.

4126H–CAN–01/05 Data Memory The T89C51CC02 provides data memory access in two different spaces: The internal space mapped in three separate segments: The lower 128 Bytes RAM segment. The upper 128 Bytes RAM segment. The expanded 256 Bytes RAM segment (XRAM). A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode. Figure 9 shows the internal data memory spaces organization. Figure 9. Internal memory - RAM ing, and can be used for context switching in interrupt service routines. Table 16. Register Bank Selection addresses in this area are 00h to 7Fh.

256 Bytes

128 Bytes

Register bank 0 from 00h to 07h Register bank 0 from 08h to 0Fh Register bank 0 from 10h to 17h Register bank 0 from 18h to 1Fh

Figure 10. Lower 128 Bytes Internal RAM Organization must then be initialized properly.

4 Banks of

8 Registers

4126H–CAN–01/05 Dual Data Pointer The T89C51CC02 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR0 and DPTR1 are Seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (See Figure 18) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (See Figure 11). Figure 11. Dual Data Pointer Implementation using one data pointer as a “source” pointer and the other one as a “destination” pointer. enhanced algorithm libraries.

4126H–CAN–01/05 Registers Table 17. PSW Register Carry out from bit 1 of ALU operands. AC Auxiliary Carry Flag Carry out from bit 1 of addition operands. User Definable Flag 0 4 - 3 RS1:0 Register Bank Select bits Refer to Table 16 for bits description. OV Overflow Flag Overflow set by arithmetic operations. User Definable Flag 1 P Parity bit Set when ACC contains an odd number of 1’s. Cleared when ACC contains an even number of 1’s.

4126H–CAN–01/05 Table 18. AUXR1 Register

1. ENBOOT is initialized with the invert BLJB at reset. See In-System Programming

The value read from these bits is indeterminate. Do not set these bits. ENBOOT(1) Enable Boot Flash Set this bit to map the boot Flash between F800h -FFFFh Clear this bit to disable boot Flash. Reserved The value read from this bit is indeterminate. Do not set this bit. GF3 General Purpose Flag 3 Always Zero This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3 flag. Reserved for Data Pointer Extension DPS Data Pointer Select bit Set to select second dual data pointer: DPTR1. Clear to select first dual data pointer: DPTR0.

4126H–CAN–01/05 EEPROM Data Memory The 2K bytes on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/XRAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction. A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming). The number of data written on the page may vary from 1 up to 128 Bytes (the page size). When programming, only the data written in the column latch is programmed and a ninth bit is used to obtain this feature. This provides the capability to program the whole memory by Bytes, by page or by a number of Bytes in a page. Indeed, each ninth bit is set when the writing the corresponding byte in a row and all these ninth bits are reset after the writing of the complete EEPROM row. Write Data in the Column Latches Data is written by byte to the column latches as for an external RAM memory. Out of the 11 address bits of the data pointer, the 4 MSBs are used for page selection (row) and 7 are used for byte selection. Between two EEPROM programming sessions, all the addresses in the column latches must stay on the same page, meaning that the 4 MSB must no be changed. The following procedure is used to write to the column latches: Save and disable interrupt Set bit EEE of EECON register Load DPTR with the address to write Store A register with the data to be written Execute a MOVX @DPTR, A If needed loop the three last instructions until the end of a 128 Bytes page Restore interrupt Note: The last page address used when loading the column latch is the one used to select the page programming address. Programming The EEPROM programming consists of the following actions: Write one or more Bytes of one page in the column latches. Normally, all Bytes must belong to the same page; if not, the last page address will be latched and the others discarded. Launch programming by writing the control sequence (50h followed by A0h) to the EECON register. EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that the EEPROM segment is not available for reading. The end of programming is indicated by a hardware clear of the EEBUSY flag. Note: The sequence 5xh and Axh must be executed without instructions between then other- wise the programming is aborted. Read Data The following procedure is used to read the data stored in the EEPROM memory: Save and disable interrupt Set bit EEE of EECON register Load DPTR with the address to read Execute a MOVX A, @DPTR Restore interrupt

4126H–CAN–01/05 Examples ;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read. ;* Acc contain the reading value ;* NOTE: before execute this function, be sure the EEPROM is not BUSY api_rd_eeprom_byte: ; Save and clear EA MOV EECON, #02h; map EEPROM in XRAM space MOVX A, @DPTR MOV EECON, #00h; unmap EEPROM ; Restore EA ret ;* NAME: api_ld_eeprom_cl ;* DPTR contain address to load ;* Acc contain value to load ;* NOTE: in this example we load only 1 byte, but it is possible upto ;* 128 Bytes. ;* before execute this function, be sure the EEPROM is not BUSY api_ld_eeprom_cl: ; Save and clear EA MOV EECON, #02h ; map EEPROM in XRAM space MOVX @DPTR, A MOVEECON, #00h; unmap EEPROM ; Restore EA ret ;* NAME: api_wr_eeprom ;* NOTE: before execute this function, be sure the EEPROM is not BUSY api_wr_eeprom: ; Save and clear EA MOV EECON, #050h MOV EECON, #0A0h ; Restore EA ret

4126H–CAN–01/05 Registers Table 19. EECON Register Programming Launch Command bits Write 5Xh followed by AXh to EEPL to launch the programming. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. EEE Enable EEPROM Space bit Set to map the EEPROM space during MOVX instructions (Write in the column latches) Clear to map the XRAM space during MOVX. EEBUSY Programming Busy Flag Set by hardware when programming is in progress. Cleared by hardware when programming is done. Can not be set or cleared by software.

4126H–CAN–01/05 FM0 Memory Architecture The Flash memory is made up of 4 blocks (See Figure 13): The memory array (user space) 16K Bytes The Extra Row The Hardware security bits The column latch registers User Space This space is composed of a 16K Bytes Flash memory organized in 128 pages of 128 Bytes. It contains the user’s application code. Extra Row (XRow) This row is a part of FM0 and has a size of 128 Bytes. The extra row may contain infor- mation for boot loader usage. Hardware Security Byte The Hardware security Byte space is a part of FM0 and has a size of 1 byte. The 4 MSB can be read/written by software, the 4 LSB can only be read by software and written by hardware in parallel mode. Column Latches The column latches, also part of FM0, have a size of full page (128 Bytes). The column latches are the entrance buffers of the three previous memory locations (user array, XROW and Hardware security byte). Cross Flash Memory Access The FM0 memory can be programmed as describe on Table 20. Programming FM0 from FM0 is impossible. The FM1 memory can be program only by parallel programming. Table 20 show all software Flash access allowed. Table 20. Cross Flash Memory Access

The CPU interfaces the Flash memory through the FCON register and AUXR1 register. page while bits 14 to 7 are used to select the programming address of the page. Setting FPS bit takes precedence on the EEE bit in EECON register. dance with Table 21. A MOVC instruction is then used for reading these spaces. Table 21. FM0 blocks Select bits spaces to program according to FMOD1:0 bits. Table 22. Programming Spaces wise the programming is aborted. ous exit of the programming mode.

4126H–CAN–01/05 Status of the Flash Memory The bit FBUSY in FCON register is used to indicate the status of programming. FBUSY is set when programming is in progress. Selecting FM1 The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh. Loading the Column Latches Any number of data from 1 byte to 128 Bytes can be loaded in the column latches. This provides the capability to program the whole memory by byte, by page or by any number of Bytes in a page. When programming is launched, an automatic erase of the locations loaded in the col- umn latches is first performed, then programming is effectively done. Thus no page or block erase is needed and only the loaded data are programmed in the corresponding page. The following procedure is used to load the column latches and is summarized in Figure 14: Save then disable interrupt and map the column latch space by setting FPS bit. Load the DPTR with the address to load. Load Accumulator register with the data to load. Execute the MOVX @DPTR, A instruction. If needed loop the three last instructions until the page is completely loaded. unmap the column latch and Restore Interrupt

Figure 15. Flash and Extra row Programming Procedure Save then disable the interrupts. Load Accumulator register with the data to load. Execute the MOVX @DPTR, A instruction. FCON register. This step of the procedure must be executed from FM1. The end of the programming indicated by the FBusy flag cleared.

Figure 17. Reading Procedure aa = 10 for the Hardware Security Byte. chip code and data located in FM0 and FM1. The only way to write this bits are the parallel mode. They are set by default to level 3. Table 23. Program Lock bit See Section “Power Management”. external program memory returns code data. Parallel programming of the Flash is disabled. disabled. This is the factory defaul programming.

4126H–CAN–01/05 Registers Table 24. FCON Register FPL3:0 Programming Launch Command bits Write 5Xh followed by AXh to launch the programming according to FMOD1:0. (See Table 22.) FPS Flash Map Program Space Set to map the column latch space in the data memory space. Clear to re-map the data memory space. 2 - 1 FMOD1:0 Flash Mode See Table 21 or Table 22. FBUSY Flash Busy Set by hardware when programming is in progress. Clear by hardware when programming is done. Can not be changed by software.

Table 25. Cross Memory Access

Table 26. Instructions shared Table 27. Read MOVX A, @DPTR Table 28. Write MOVX @DPTR,A

Table 29. Read MOVC A, @DPTR

1. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from
2. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from

1. The user can also program his own bootloader in FM1.

This ISP allows code modification over the total lifetime of the product. This allow the customer to have a full use of the 16-Kbyte user memory. bootloader located in FM0 at [SBV]00h. A further method exist in activating the Atmel boot loader by hardware activation. See the Section “Hardware Security Byte”. The FM0 can be programmed also by the parallel mode using a programmer. Figure 18. Flash Memory Mapping

the different flags and Bytes. @0000h on FM0 or execute the boot loader at address @F800h on FM1. -To read or modify this bit, the APIs are used.

• This byte contains the MSB of the user boot loader address in FM0.
• The default value of SBV is FFh (no user boot loader in FM0).
• To read or modify this byte, the APIs are used.
• These Bytes are reserved for customer use.
• To read or modify these Bytes, the APIs are used.

Figure 19. Hardware Boot Process Algorithm All these APIs are described in detail in the following documents on the Atmel web site. Datasheet Bootloader CAN T89C51CC02. Datasheet Bootloader UART T89C51CC02. Is Initialized with BLJB Inverted.

4126H–CAN–01/05 XROW Bytes The EXTRA ROW (XROW) includes 128 bytes. Some of these bytes are used for spe- cific purpose in conjonction with the bootloader. Table 30. XROW Mapping met, the chip will start executing the bootloader at the end of the Reset. See a detailed description in the applicable Document. Datasheet Bootloader CAN T89C51CC02. Datasheet Bootloader UART T89C51CC02. Copy of the Manufacturer Code 58h 30h Copy of the Device ID#1: Family code D7h 31h Copy of the Device ID#2: Memories size and type BBh 60h Copy of the Device ID#3: Name and Revision FFh 61h

4126H–CAN–01/05 Hardware Security Byte Table 31. Hardware Security byte

1. Only the 4 MSB bits can be accessed by software.
2. The 4 LSB bits can only be accessed by parallel mode.

Set this bit to start in standard mode Clear this bit to start in X2 Mode. BLJB Boot Loader Jump bit - 1: To start the user’s application on next RESET (@0000h) located in FM0, - 0: To start the boot loader(@F800h) located in FM1. 5 - 3 Reserved The value read from these bits are indeterminate. 2 - 0 LB2:0 Lock bits (see Table 22)

4126H–CAN–01/05 Here is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0011b SADEN1111 1101b Given1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To com- municate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b). Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.: SADDR 0101 0110b SADEN 1111 1100b SADDR OR SADEN1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 1X11b, Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 1X11B, Slave C:SADDR=1111 0010b SADEN1111 1101b Given1111 1111b For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh.

4126H–CAN–01/05 Registers Table 32. SCON Register Framing Error bit (SMOD0 = 1) Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SM0 Serial port Mode bit 0 (SMOD0 = 0) Refer to SM1 for serial port mode selection. SM1 Serial port Mode bit 1 SM0 SM1 Mode Baud Rate Shift Register FXTAL/12 (or FXTAL/6 in mode X2) 8-bit UART Variable 9bit UART FXTAL/64 or FXTAL/32 9bit UART Variable SM2 Serial port Mode 2 bit/Multiprocessor Communication Enable bit Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3. REN Reception Enable bit Clear to disable serial reception. Set to enable serial reception. TB8 Transmitter bit 8/Ninth bit to Transmit in Modes 2 and 3 Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. RB8 Receiver bit 8/Ninth bit Received in Modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. TI Transmit Interrupt Flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. RI Receive Interrupt Flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, See Figure 22. and Figure 23. in the other modes.

4126H–CAN–01/05 Table 33. SADEN Register Table 34. SADDR Register Table 35. SBUF Register Mask Data for Slave Individual Address Bit Number Bit Mnemonic Data sent/received by Serial I/O Port

4126H–CAN–01/05 Table 36. PCON Register Set to select double baud rate in mode 1, 2 or 3. SMOD0 Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. Reserved The value read from this bit is indeterminate. Do not set this bit. POF Power-off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. GF1 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. GF0 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. PD Power-down Mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. IDL Idle Mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode.

4126H–CAN–01/05 Timers/Counters The T89C51CC02 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. The various operating modes of each Timer/Counter are described in the following sections. Timer/Counter Operations A basic operation is Timer registers THx and TLx (x = 0, 1) connected in cascade to form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (See Figure 37) turns the Timer on by allowing the selected input to increment TLx. When TLx overflows it increments THx; when THx overflows it sets the Timer overflow flag (TFx) in TCON register. Setting the TRx does not clear the THx and TLx Timer registers. Timer regis- ters can be accessed to obtain the current count or to enter preset values. They can be read at any time but TRx bit must be cleared to preset their values, otherwise the behav- ior of the Timer/Counter is unpredictable. The C/Tx# control bit selects Timer operation or Counter operation by selecting the divided-down peripheral clock or external pin Tx as the source for the counted signal. TRx bit must be cleared when changing the mode of operation, otherwise the behavior of the Timer/Counter is unpredictable. For Timer operation (C/Tx# = 0), the Timer register counts the divided-down peripheral clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock periods). The Timer clock rate is fPER/6, i.e. fOSC/12 in standard mode or fOSC/6 in X2 Mode. For Counter operation (C/Tx# = 1), the Timer register counts the negative transitions on the Tx external input pin. The external input is sampled every peripheral cycles. When the sample is high in one cycle and low in the next one, the Counter is incremented. Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition, the maximum count rate is fPER/12, i.e. fOSC/24 in standard mode or fOSC/12 in X2 Mode. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle. Timer 0 Timer 0 functions as either a Timer or event Counter in four modes of operation. Figure 24 through Figure 27 show the logical configuration of each mode. Timer 0 is controlled by the four lower bits of TMOD register (See Figure 38) and bits 0, 1, 4 and 5 of TCON register (See Figure 37). TMOD register selects the method of Timer gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10 and M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0). For normal Timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer operation. Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an inter- rupt request. It is important to stop Timer/Counter before changing mode.

and out of mode 3 to turn it off and on. It is important to stop Timer/Counter before changing mode. cascade (See Figure 25). The selected input increments TL1 register. Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3. interrupts are globally enabled by setting EA bit in IEN0 register. Figure 28. Timer Interrupt System

4126H–CAN–01/05 Registers Table 37. TCON Register Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. TR1 Timer 1 Run Control bit Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1. TF0 Timer 0 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 0 register overflows. TR0 Timer 0 Run Control bit Clear to turn off Timer/Counter 0. Set to turn on Timer/Counter 0. IE1 Interrupt 1 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (See IT1). Set by hardware when external interrupt is detected on INT1# pin. IT1 Interrupt 1 Type Control bit Clear to select low level active (level triggered) for external interrupt 1 (INT1#). Set to select falling edge active (edge triggered) for external interrupt 1. IE0 Interrupt 0 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (See IT0). Set by hardware when external interrupt is detected on INT0# pin. IT0 Interrupt 0 Type Control bit Clear to select low level active (level triggered) for external interrupt 0 (INT0#). Set to select falling edge active (edge triggered) for external interrupt 0.

4126H–CAN–01/05 Table 38. TMOD Register

1. Reloaded from TH1 at overflow.
2. Reloaded from TH0 at overflow.

Table 39. TH0 Register Timer 1 Gating Control bit Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. C/T1# Timer 1 Counter/Timer Select bit Clear for Timer operation: Timer 1 counts the divided-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1. M11 Timer 1 Mode Select bits M11 M01 Operating mode Mode 0: 8-bit Timer/Counter (TH1) with 5bit prescaler (TL1). Mode 1: 16-bit Timer/Counter. Mode 3: Timer 1 halted. Retains count. Mode 2: 8-bit auto-reload Timer/Counter (TL1).(1) M01 GATE0 Timer 0 Gating Control bit Clear to enable Timer 0 whenever TR0 bit is set. Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set. C/T0# Timer 0 Counter/Timer Select bit Clear for Timer operation: Timer 0 counts the divided-down system clock. Set for Counter operation: Timer 0 counts negative transitions on external pin T0. M10 Timer 0 Mode Select bit M10 M00 Operating mode Mode 0: 8-bit Timer/Counter (TH0) with 5bit prescaler (TL0). Mode 1: 16-bit Timer/Counter. Mode 2: 8-bit auto-reload Timer/Counter (TL0).(2) Mode 3: TL0 is an 8-bit Timer/Counter. TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits. M00 Bit Number Bit Mnemonic 7:0 High Byte of Timer 0

4126H–CAN–01/05 Table 40. TL0 Register Table 41. TH1 Register Table 42. TL1 Register 7:0 Low Byte of Timer 0 Bit Number Bit Mnemonic 7:0 High Byte of Timer 1 Bit Number Bit Mnemonic 7:0 Low Byte of Timer 1

The T89C51CC02 Timer 2 is compatible with Timer 2 in the 80C52.

1. C/T2 selects FT2 clock/6 (timer operation) or external pin T2 (counter operation) as

timer clock. Setting TR2 allows TL2 to be incremented by the selected input. this mode the T2EX pin controls the counting direction. in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. Figure 29. Auto-Reload Mode Up/Down Counter

Set T2OE bit in T2MOD register. Clear C/T2 bit in T2CON register. reload value or different depending on the application. To start the timer, set TR2 run control bit in T2CON register. independent since both functions use the values in the RCAP2H and RCAP2L registers. Figure 30. Clock-Out Mode

4126H–CAN–01/05 Registers Table 43. T2CON Register TF2 is not set if RCLK=1 or TCLK = 1. Must be cleared by software. Set by hardware on Timer 2 overflow. EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. Set to cause the CPU to vector to Timer 2 interrupt routine when Timer 2 interrupt is enabled. Must be cleared by software. RCLK Receive Clock bit Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3. TCLK Transmit Clock bit Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3. EXEN2 Timer 2 External Enable bit Clear to ignore events on T2EX pin for Timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if Timer 2 is not used to clock the serial port. TR2 Timer 2 Run Control bit Clear to turn off Timer 2. Set to turn on Timer 2. C/T2# Timer/Counter 2 Select bit Clear for timer operation (input from internal clock system: fOSC). Set for counter operation (input from T2 input pin). CP/RL2# Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on Timer 2 overflow. Clear to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1.

4126H–CAN–01/05 Table 44. T2MOD Register Table 45. TH2 Register The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. T2OE Timer 2 Output Enable bit Clear to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. DCEN Down Counter Enable bit Clear to disable Timer 2 as up/down counter. Set to enable Timer 2 as up/down counter. Bit Number Bit Mnemonic

4126H–CAN–01/05 Table 46. TL2 Register Table 47. RCAP2H Register Table 48. RCAP2L Register High Byte of Timer 2 Reload/Capture. Bit Number Bit Mnemonic Low Byte of Timer 2 Reload/Capture.

ter. When exiting reset, the WDT is -by default- disable. When the watchdog is enable it is impossible to change its period. Figure 31. Watchdog Timer

Table 49. Machine Cycle Count Table 50. Timeout Computation

4126H–CAN–01/05 Watchdog Timer During Power-down Mode and Idle In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are 2 methods of exiting Power-down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, the watchdog is disabled. Exiting Power-down with an interrupt is signif- icantly different. The interrupt shall be held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down. To ensure that the WDT does not overflow within a few states of exiting powerdown, it is best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting T89C51CC02 while in Idle mode, the user should always set up a timer that will periodi- cally exit Idle, service the WDT, and re-enter Idle mode. Register Table 51. WDTPRG Register The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Watchdog Timer Duration selection bit 2 Work in conjunction with bit 1 and bit 0. Watchdog Timer Duration selection bit 1 Work in conjunction with bit 2 and bit 0. Watchdog Timer Duration selection bit 0 Work in conjunction with bit 1 and bit 2.

4126H–CAN–01/05 Table 52. WDTRST Register sequence without instruction between these two sequences.

achieves a bitrate of 1-Mbit/s at 8 MHz1 Crystal frequency in X2 Mode.

1. At BRP = 1 sampling point will be fixed.

and ISO 11519-2 for low speed. dynamically. The identifier with the lowest binary number has the highest priority. highest priority and do not re-attempt transmission until the bus is available again. as CAN 2.0 B, supports a length of 29 bits for the identifier. Figure 32. CAN Standard Frames

there is no following bus access by any node, the bus remains idle. Figure 33. CAN Extended Frames frame in CAN standard frame format, and transmitted as recessive in the other case. has priority over the message in extended format. ing edge SOF and on each recessive to dominant edge. the smallest discrete timing resolution used by a CAN node.

Figure 34. CAN Bit Construction The first segment is used to synchronize the various bus nodes. is expected to occur within this segment by the receiving nodes. This segment is used to compensate for signal delays across the network. through the transceivers of the bus nodes. Phase Segment 1 is used to compensate for edge phase errors. This segment may be lengthened during resynchronization. This segment is also used to compensate for edge phase errors. It is the time required for the logic to determine the bit level of a sampled bit. less than the Information processing Time. adjust the sample point and the end of the bit time.

Resynchronization Jump Width. This segment may not be longer than Phase Segment 2. Programming of the sample point allows "tuning" of the characteristics to suit the bus. so that lower cost oscillators such as ceramic resonators may be used. a poorer bus topology and maximum bus length. Figure 35. Bus Arbitration Multiple Access with Arbitration on Message Priority”. the most important message is sent first without time loss. same time, the data frame prevails over the remote frame (c.f. RTR bit). the received bits. If they do not agree there has been a CRC error.

4126H–CAN–01/05 fields against the fixed format and the frame size. Errors detected by frame checks are designated "format errors". ACK Errors As already mentioned frames received are acknowledged by all receivers through positive acknowledgement. If no acknowledgement is received by the transmitter of the message an ACK error is indicated. Error at Bit Level Monitoring The ability of the transmitter to detect errors is based on the monitoring of bus signals. Each node which transmits also observes the bus level and thus detects differences between the bit sent and the bit received. This permits reliable detection of global errors and errors local to the transmitter. Bit Stuffing The coding of the individual bits is tested at bit level. The bit representation used by CAN is "Non Return to Zero (NRZ)" coding, which guarantees maximum efficiency in bit coding. The synchronization edges are generated by means of bit stuffing. Error Signalling If one or more errors are discovered by at least one node using the above mechanisms, the current transmission is aborted by sending an "error flag". This prevents other nodes accepting the message and thus ensures the consistency of data throughout the net- work. After transmission of an erroneous message that has been aborted, the sender automatically re-attempts transmission. CAN Controller The CAN controller accesses are made through SFR. Several operations are possible by SFR: arithmetic and logic operations, transfers and program control (SFR is accessible by direct addressing). 4 independent message objects are implemented, a pagination system manages their accesses. Any message object can be programmed in a reception buffer block (even non-consec- utive buffers). For the reception of defined messages one or several receiver message objects can be masked without participating in the buffer feature. An IT is generated when the buffer is full. The frames following the buffer-full interrupt will not be taken into account until at least one of the buffer message objects is re-enabled in reception. Higher priority of a message object for reception or transmission is given to the lower message object number. The programmable 16-bit Timer (CANTIMER) is used to stamp each received and sent message in the CANSTMP register. This timer starts counting as soon as the CAN con- troller is enabled by the ENA bit in the CANGCON register. The Time Trigger Communication (TTC) protocol is supported by the T89C51CC02.

Figure 36. CAN Controller Block Diagram register (CANPAGE) as illustrate in Figure 37.

Figure 37. CAN Controller Memory Organization

4 Message Objects

8 Bytes

each access. The range of this counter is 8. Note that the maibox is a pure RAM, dedicated to one message object, without overlap. lations or tests can be executed in the mailbox area which provide quicker access. Message object Status (CANSTCH). view of the message objects availability. The CAN messages can be handled by interrupt or polling modes. Table 53. Configuration for CONCH1:2 object, it is necessary to re-write the configuration in CANCONCH register. (Transmitter, Receiver and Receiver buffer).

sage objects, and with no limitation in number of message objects used up to 4. Figure 38. Buffer Mode The same acceptance filter must be defined for each message objects of the buffer. When there is no mask on the identifier or the IDE, all messages are accepted. A received frame will always be stored in the lowest free message object. the message object re-enabled in buffer reception in order to free the message object. message objects is re-enabled in reception. This flag must be cleared by the software in order to acknowledge the interrupt.

Figure 39. CAN Controller Interrupt Structure

4126H–CAN–01/05 To enable an interrupt on Buffer-full condition: Enable General CAN IT in the interrupt system register Enable interrupt on Buffer full, ENBUF To enable an interrupt when Timer overruns: Enable Overrun IT in the interrupt system register When an interrupt occurs, the corresponding message object bit is set in the SIT register. To acknowledge an interrupt, the corresponding CANSTCH bits (RXOK, TXOK,...) or CANGIT bits (OVRTIM, OVRBUF,...), must be cleared by the software application. When the CAN node is in transmission and detects a Form Error in its frame, a bit Error will also be raised. Consequently, two consecutive interrupts can occur, both due to the same error. When a message object error occurs and is set in CANSTCH register, no general error are set in CANGIE register.

quantum. So, the input clock for bit timing is the clock used into CAN channel FSM’s. TQ: Time Quantum (output of Baud Rate Prescaler). SYNS: SYNchronization Segment is 1 TQ long. PRS: PRopagation time Segment is programmable to be 1, 2, ..., 8 TQ long. PHS1: PHase Segment 1 is programmable to be 1, 2, ..., 8 TQ long. INFORMATION PROCESSING TIME is 2 TQ. The total number of TQ in a bit time has to be programmed at least from 8 to 25. Figure 40. Sample and Transmission Point

Figure 41. General Structure of a bit Period Verify that the CAN baud rate you want is an integer division of FCAN clock.

when the CAN macro detects an error. transmission, an error passive unit will wait before initiating further transmission. A bus off unit is not allowed to have any influence on the bus. For fault confinement, two error counters (TEC and REC) are implemented. See CAN Specification for details on Fault confinement. Figure 42. Line Error Mode

128 Occurrences

11 Consecutive

ID+RTR+RB+IDE received are written over the ID TAG Registers. Figure 43. Acceptance Filter Block Diagram To accept only ID = 318h in part A.

4126H–CAN–01/05 Data and Remote Frame Description of the different steps for: Data frame Remote frame, with automatic reply Remote frame u u u u u x 0 0 u u u u u ENCH RTR RPLV TXOK RXOK x 0 0 c u c u u x 1 0 u c c u u x 0 1 DATA FRAME Node A Node B ENCH RTR RPLV TXOK RXOK message object in reception message object disabled message object in transmission message object disabled u u u u u x 0 0 c u u u c x 1 0 u c c u u x 0 1 REMOTE FRAME DATA FRAME u u u u u 0 0 u u u c c 0 0 c u c c u 1 0 ENCH RTR RPLV TXOK RXOK ENCH RTR RPLV TXOK RXOK (immediate) message object in reception message object in transmission message object disabled message object in transmission message object in reception message object disabled by CAN controller by CAN controller u u u u u x 0 0 u u u u u ENCH RTR RPLV TXOK RXOK 0 0 c u u u c x 1 0 u c c u u 0 1 REMOTE FRAME ENCH RTR RPLV TXOK RXOK u u u u u x 0 0 c u c u u x 1 0 u c c u c x 0 1 DATA FRAME (deferred) u : modified by user i c : modified by CAN i message object in reception message object in transmission by user message object disabled message object disabled message object in transmission message object in reception message object disabled by user

bit in the CANGCON register. In this mode, CAN only sends the frame once, even if an error occurs. message object which received or sent the frame. The stamping of a received frame occurs when the RxOk flag is set. The stamping of a sent frame occurs when the TxOk flag is set. The CAN Timer works in a roll-over from FFFFh to 0000h which serves as a time base. in the interrupt enable register IEN1 is set. Figure 44. Block Diagram of CAN Timer

ing the received messages. It cannot send any message. The error flags are updated. The bit timing can be adjusted until no error occurs (good configuration find). In this mode, the error counters are frozen. To go back to the standard mode, the AUTOBAUD bit must be cleared. Figure 45. Autobaud Mode

4126H–CAN–01/05 // Enable the CAN macro CANGCON = 02h 2. Configure message object 3 in reception to receive only standard (11bit identifier) message 100h // Select the message object 3 CANPAGE = 30h // Enable the interrupt on this message object CANIE = 08h // Clear the status and control register CANSTCH = 00h CANCONCH= 00h // Init the acceptance filter to accept only message 100h in standard mode CANIDT1 = 20h CANIDT2 = 00h CANIDT3 = 00h CANIDT4 = 00h CANIDM1 = FFh CANIDM2 = FFh CANIDM3 = FFh CANIDM4 = FFh // Enable channel in reception CANCONCH = 88h // enable reception Note: to enable the CAN interrupt in reception: EA = 1 ECAN = 1 CANGIE = 20h 3. Send a message on the message object 0 // Select the message object 0 CANPAGE = 00h // Enable the interrupt on this message object CANIE = 01h // Clear the Status register CANSTCH = 00h; // load the identifier to send (ex: 555h) CANIDT1 = AAh; CANIDT2 = A0h; // load data to send CANMSG = 00h CANMSG = 01h CANMSG = 02h CANMSG = 03h CANMSG = 04h CANMSG = 05h CANMSG = 06h CANMSG = 07h // configure the control register CANCONCH = 18h 4. Interrupt routine // Save the current CANPAGE

4126H–CAN–01/05 // Find the first message object which generate an interrupt in CANSIT // Select the corresponding message object // Analyse the CANSTCH register to identify which kind of interrupt is generated // Manage the interrupt // Clear the status register CANSTCH = 00h; // if it is not a channel interrupt but a general interrupt // Manage the general interrupt and clear CANGIT register // restore the old CANPAGE

Table 54. SFR Mapping

4126H–CAN–01/05 Registers Table 55. CANGCON Register Not an auto-resetable bit. A reset of the ENCH bit (message object control & DLC register) is done for each message object. The pending transmission communications are immediately aborted but the on-going communication will be terminated normally, setting the appropriate status flags, TxOk or RxOk. OVRQ Overload Frame Request (Initiator). Auto-resetable bit. Set to send an overload frame after the next received message. Cleared by the hardware at the beginning of transmission of the overload frame. TTC Network in Timer Trigger Communication set to select node in TTC. clear to disable TTC features. SYNCTTC Synchronization of TTC When this bit is set the TTC timer is caught on the last bit of the End Of Frame. When this bit is clear the TTC timer is caught on the Start Of Frame. This bit is only used in the TTC mode. AUTOBAUD AUTOBAUD set to active listening mode. Clear to disable listening mode TEST Test mode. The test mode is intended for factory testing and not for customer use. ENA/STB Enable/Standby CAN Controller When this bit is set, it enables the CAN controller and its input clock. When this bit is clear, the on-going communication is terminated normally and the CAN controller state of the machine is frozen (the ENCH bit of each message object does not change). In the standby mode, the transmitter constantly provides a recessive level; the receiver is not activated and the input clock is stopped in the CAN controller. During the disable mode, the registers and the mailbox remain accessible. Note that two clock periods are needed to start the CAN controller state of the machine. GRES General Reset (Software Reset). Auto-resetable bit. This reset command is ‘ORed’ with the hardware reset in order to reset the controller. After a reset, the controller is disabled.

4126H–CAN–01/05 Table 56. CANGSTA Register

1. These fields are Read Only.

The values read from this bit is indeterminate. Do not set this bit. OVFG Overload frame flag(1) This status bit is set by the hardware as long as the produced overload frame is sent. This flag does not generate an interrupt Reserved The values read from this bit is indeterminate. Do not set this bit. TBSY Transmitter busy(1) This status bit is set by the hardware as long as the CAN transmitter generates a frame (remote, data, overload or error frame) or an ack field. This bit is also active during an InterFrame Spacing if a frame must be sent. This flag does not generate an interrupt. RBSY Receiver busy(1) This status bit is set by the hardware as long as the CAN receiver acquires or monitors a frame. This flag does not generate an interrupt. ENFG Enable on-chip CAN controller flag(1) Because an enable/disable command is not effective immediately, this status bit gives the true state of a chosen mode. This flag does not generate an interrupt. BOFF Bus off mode(1) See Figure 42 ERRP Error passive mode(1) See Figure 42

4126H–CAN–01/05 Table 57. CANGIT Register

1. These fields are Read Only.

General interrupt flag(1) This status bit is the image of all the CAN controller interrupts sent to the interrupt controller. It can be used in the case of the polling method. Reserved The values read from this bit is indeterminate. Do not set this bit. OVRTIM Overrun CAN Timer This status bit is set when the CAN timer switches 0xFFFF to 0x0000. If the bit ETIM in the IE1 register is set, an interrupt is generated. Clear this bit in order to reset the interrupt. OVRBUF Overrun BUFFER 0 - no interrupt. 1 - IT turned on This bit is set when the buffer is full. bit resetable by user. See Figure 39. SERG Stuff Error General Detection of more than five consecutive bits with the same polarity. This flag can generate an interrupt. resetable by user. CERG CRC Error General The receiver performs a CRC check on each destuffed received message from the start of frame up to the data field. If this checking does not match with the destuffed CRC field, a CRC error is set. This flag can generate an interrupt. resetable by user. FERG Form Error General The form error results from one or more violations of the fixed form in the following bit fields: CRC delimiter acknowledgment delimiter end_of_frame This flag can generate an interrupt. resetable by user. AERG Acknowledgment Error General No detection of the dominant bit in the acknowledge slot. This flag can generate an interrupt. resetable by user.

4126H–CAN–01/05 Table 58. CANTEC Register Table 59. CANREC Register TEC7:0 Transmit Error Counter See Figure 42 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 Bit Number Bit Mnemonic REC7:0 Reception Error Counter See Figure 42

4126H–CAN–01/05 Table 60. CANGIE Register The values read from these bits are indeterminate. Do not set these bits. ENRX Enable Receive Interrupt 0 - Disable 1 - Enable ENTX Enable Transmit Interrupt 0 - Disable 1 - Enable ENERCH Enable Message Object Error Interrupt 0 - Disable 1 - Enable ENBUF Enable BUF Interrupt 0 - Disable 1 - Enable ENERG Enable General Error Interrupt 0 - Disable 1 - Enable Reserved The value read from this bit is indeterminate. Do not set this bit. See Figure 39.

4126H–CAN–01/05 Table 61. CANEN Register Table 62. CANSIT Register The values read from these bits are indeterminate. Do not set these bits. 3 - 0 ENCH3:0 Enable Message Object 0 - message object is disabled => the message object is free for a new emission or reception. 1 - message object is enabled. This bit is resetable by re-writing the CANCONCH of the corresponding message object. SIT3 SIT2 SIT1 SIT0 Bit Number Bit Mnemonic The values read from these bits are indeterminate. Do not set these bits. 3 - 0 SIT3:0 Status of Interrupt by Message Object 0 - no interrupt. 1 - IT turned on. Reset when interrupt condition is cleared by user. SIT3:0 = 0b 0000 1001 -> IT’s on message objects 3 & 0. See Figure 39.

4126H–CAN–01/05 Table 63. CANIE Register Table 64. CANBT1 Register

1. The CAN controller bit timing registers must be accessed only if the CAN controller is

disabled with the ENA bit of the CANGCON register set to 0. No default value after reset. The values read from these bits are indeterminate. Do not set these bits. 3 - 0 IECH3:0 Enable Interrupt by Message Object 0 - disable IT. 1 - enable IT. IECH3:0 = 0b 0000 1100 -> Enable IT’s of message objects 3 & 2. BRP 5 BRP 4 BRP 3 BRP 2 BRP 1 BRP 0 Bit Number Bit Mnemonic The value read from this bit is indeterminate. Do not set this bit. 6 - 1 BRP5:0 Baud Rate Prescaler The period of the CAN controller system clock Tscl is programmable and determines the individual bit timing.(1) Reserved The value read from this bit is indeterminate. Do not set this bit. Tscl = BRP[5..0] + 1 FCAN

4126H–CAN–01/05 Table 65. CANBT2 Register

1. The CAN controller bit timing registers must be accessed only if the CAN controller is

disabled with the ENA bit of the CANGCON register set to 0. No default value after reset. The value read from this bit is indeterminate. Do not set this bit. 6 - 5 SJW1:0 Re-synchronization Jump Width To compensate for phase shifts between clock oscillators of different bus controllers, the controller must re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width defines the maximum number of clock cycles. A bit period may be shortened or lengthened by a re- synchronization. Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - 1 PRS2:0 Programming Time Segment This part of the bit time is used to compensate for the physical delay times within the network. It is twice the sum of the signal propagation time on the bus line, the input comparator delay and the output driver delay. Reserved The value read from this bit is indeterminate. Do not set this bit. Tsjw = Tscl x (SJW [1..0] +1) Tprs = Tscl x (PRS[2..0] + 1)

4126H–CAN–01/05 Table 66. CANBT3 Register

1. The CAN controller bit timing registers must be accessed only if the CAN controller is

disabled with the ENA bit of the CANGCON register set to 0. No default value after reset. The value read from this bit is indeterminate. Do not set this bit. 6 - 4 PHS2 2:0 Phase Segment 2 This phase is used to compensate for phase edge errors. This segment can be shortened by the re-synchronization jump width. Phasse segment 2 is the maximum of Phase segment1 and the Information Processing Time (= 2TQ). 3 - 1 PHS1 2:0 Phase Segment 1 This phase is used to compensate for phase edge errors. This segment can be lengthened by the re-synchronization jump width. SMP Sample Type 0 - once, at the sample point. 1 - three times, the threefold sampling of the bus is the sample point and twice over a distance of a 1/2 period of the Tscl. The result corresponds to the majority decision of the three values. Tphs2 = Tscl x (PHS2[2..0] + 1) Tphs1 = Tscl x (PHS1[2..0] + 1)

4126H–CAN–01/05 Table 67. CANPAGE Register Table 68. CANCONCH Register The values read from these bits are indeterminate. Do not set these bits. 5 - 4 CHNB3:0 Selection of Message Object Number The available numbers are: 0 to 3(See Figure 37). AINC Auto Increment of the Index (Active Low) 0 - auto-increment of the index (default value). 1 - non-auto-increment of the index. 2 - 0 INDX2:0 Index Byte location of the data field for the defined message object (See Figure 37). CONCH 1 CONCH 0 RPLV IDE DLC 3 DLC 2 DLC 1 DLC 0 Bit Number Bit Mnemonic CONCH1:0 Configuration of Message Object CONCH1 CONCH0 0: disable 1: Launch transmission 0: Enable Reception 1: Enable Reception Buffer NOTE: The user must re-write the configuration to enable the corresponding bit in the CANEN1:2 registers. RPLV Reply valid Used in the automatic reply mode after receiving a remote frame 0 - reply not ready. 1 - reply ready & valid. IDE Identifier Extension 0 - CAN standard rev 2.0 A (ident = 11 bits). 1 - CAN standard rev 2.0 B (ident = 29 bits). 3 - 0 DLC3:0 Data Length Code Number of Bytes in the data field of the message. The range of DLC is from 0 up to 8. This value is updated when a frame is received (data or remote frame). If the expected DLC differs from the incoming DLC, a warning appears in the CANSTCH register.

4126H–CAN–01/05 Table 69. CANSTCH Register No default value after reset. The incoming message does not have the DLC expected. Whatever the frame type, the DLC field of the CANCONCH register is updated by the received DLC. TXOK Transmit OK The communication enabled by transmission is completed. When the controller is ready to send a frame, if two or more message objects are enabled as producers, the lower index message object (0 to 13) is supplied first. Must be cleared by software. This flag can generate an interrupt. RXOK Receive OK The communication enabled by reception is completed. In the case of two or more message object reception hits, the lower index message object (0 to 13) is updated first. Must be cleared by software. This flag can generate an interrupt. BERR bit Error (only in transmission) The bit value monitored is different from the bit value sent. Exceptions: the monitored recessive bit sent as a dominant bit during the arbitration field and the acknowledge slot detecting a dominant bit during the sending of an error frame. Must be cleared by software. This flag can generate an interrupt. SERR Stuff Error Detection of more than five consecutive bits with the same polarity. Must be cleared by software. This flag can generate an interrupt. CERR CRC Error The receiver performs a CRC check on each destuffed received message from the start of frame up to the data field. If this checking does not match with the destuffed CRC field, a CRC error is set. Must be cleared by software. This flag can generate an interrupt. FERR Form Error The form error results from one or more violations of the fixed form in the following bit fields: CRC delimiter acknowledgment delimiter end_of_frame Must be cleared by software. This flag can generate an interrupt. AERR Acknowledgment Error No detection of the dominant bit in the acknowledge slot. Must be cleared by software. This flag can generate an interrupt.

4126H–CAN–01/05 Table 70. CANIDT1 Register for V2.0 part A No default value after reset. Table 71. CANIDT2 Register for V2.0 part A No default value after reset. Table 72. CANIDT3 Register for V2.0 part A No default value after reset. IDT10:3 IDentifier Tag Value See Figure 43. IDT 2 IDT 1 IDT 0 Bit Number Bit Mnemonic IDT2:0 IDentifier Tag Value See Figure 43. 4-0 Reserved The values read from these bits are indeterminate. Do not set these bits. Bit Number Bit Mnemonic The values read from these bits are indeterminate. Do not set these bits.

4126H–CAN–01/05 Table 73. CANIDT1 for V2.0 part A No default value after reset. Table 74. CANIDT2Register for V2.0 part A No default value after reset. Table 75. CANIDT2 Register for V2.0 Part B No default value after reset. The values read from these bits are indeterminate. Do not set these bits. RTRTAG Remote transmission request tag value. Reserved The values read from this bit are indeterminate. Do not set these bit. RB0TAG Reserved bit 0 tag value. IDT 28 IDT 27 IDT 26 IDT 25 IDT 24 IDT 23 IDT 22 IDT 21 Bit Number Bit Mnemonic IDT28:21 IDentifier Tag Value See Figure 43. IDT 20 IDT 19 IDT 18 IDT 17 IDT 16 IDT 15 IDT 14 IDT 13 Bit Number Bit Mnemonic IDT20:13 IDentifier Tag Value See Figure 43.

4126H–CAN–01/05 Table 76. CANIDT3 Register for V2.0 Part B No default value after reset. Table 77. CANIDT4 Register for V2.0 Part B No default value after reset. IDT12:5 IDentifier Tag Value See Figure 43. IDT 4 IDT 3 IDT 2 IDT 1 IDT 0 RTRTAG RB1TAG RB0TAG Bit Number Bit Mnemonic IDT4:0 IDentifier Tag Value See Figure 43. RTRTAG Remote Transmission Request Tag Value RB1TAG Reserved bit 1 tag value. RB0TAG Reserved bit 0 tag value.

4126H–CAN–01/05 Table 78. CANIDM1 Register for V2.0 part A No default value after reset. Table 79. CANIDM2 Register for V2.0 part A No default value after reset. Table 80. CANIDM3 Register for V2.0 part A No default value after reset. IDTMSK10:3 IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 43. IDMSK 2 IDMSK 1 IDMSK 0 Bit Number Bit Mnemonic IDTMSK2:0 IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 43. 4 -0 Reserved The values read from these bits are indeterminate. Do not set these bits. Bit Number Bit Mnemonic The values read from these bits are indeterminate.

4126H–CAN–01/05 Table 81. CANIDM4 Register for V2.0 part A The ID Mask is only used for reception. No default value after reset. Table 82. CANIDM1 Register for V2.0 Part B The ID Mask is only used for reception. No default value after reset. The values read from these bits are indeterminate. Do not set these bits. RTRMSK Remote transmission request Mask Value 0 - comparison true forced. 1 - bit comparison enabled. Reserved The value read from this bit is indeterminate. Do not set this bit. IDEMSK IDentifier Extension Mask Value 0 - comparison true forced. 1 - bit comparison enabled. IDMSK 28 IDMSK 27 IDMSK 26 IDMSK 25 IDMSK 24 IDMSK 23 IDMSK 22 IDMSK 21 Bit Number Bit Mnemonic IDMSK28:21 IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 43.

4126H–CAN–01/05 Table 83. CANIDM2 Register for V2.0 Part B

1. The ID Mask is only used for reception.

No default value after reset. Table 84. CANIDM3 Register for V2.0 Part B The ID Mask is only used for reception. No default value after reset. IDMSK20:13 IDentifier Mask Value(1) 0 - comparison true forced. 1 - bit comparison enabled. See Figure 43. IDMSK 12 IDMSK 11 IDMSK 10 IDMSK 9 IDMSK 8 IDMSK 7 IDMSK 6 IDMSK 5 Bit Number Bit Mnemonic IDMSK12:5 IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 43.

4126H–CAN–01/05 Table 85. CANIDM4 Register for V2.0 Part B The ID Mask is only used for reception. No default value after reset. Table 86. CANMSG Register No default value after reset. IDMSK4:0 IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 43. RTRMSK Remote transmission request Mask Value 0 - comparison true forced. 1 - bit comparison enabled. Reserved The value read from this bit is indeterminate. Do not set this bit. IDEMSK IDentifier Extension Mask Value 0 - comparison true forced. 1 - bit comparison enabled. MSG 7 MSG 6 MSG 5 MSG 4 MSG 3 MSG 2 MSG 1 MSG 0 Bit Number Bit Mnemonic MSG7:0 Message Data This register contains the mailbox data byte pointed at the page message object register. After writing in the page message object register, this byte is equal to the specified message location (in the mailbox) of the pre- defined identifier + index. If auto-incrementation is used, at the end of the data register writing or reading cycle, the mailbox pointer is auto-incremented. The range of the counting is 8 with no end loop

4126H–CAN–01/05 Table 87. CANTCON Register Table 88. CANTIMH Register Table 89. CANTIML Register TPRESC7:0 Timer Prescaler of CAN Timer This register is a prescaler for the main timer upper counter range = 0 to 255. See Figure 44. CANGTIM CANGTIM CANGTIM CANGTIM CANGTIM CANGTIM CANGTIM CANGTIM Bit Number Bit Mnemonic CANGTIM15:8 High byte of Message Timer See Figure 44. CANGTIM CANGTIM CANGTIM CANGTIM CANGTIM CANGTIM CANGTIM CANGTIM Bit Number Bit Mnemonic CANGTIM7:0 Low byte of Message Timer See Figure 44.

4126H–CAN–01/05 Table 90. CANSTMPH Register Table 91. CANSTMPL Register Table 92. CANTTCH Register Table 93. CANTTCL Register TIMSTMP15:8 High byte of Time Stamp See Figure 44. TIMSTMP 7 TIMSTMP 6 TIMSTMP 5 TIMSTMP 4 TIMSTMP 3 TIMSTMP 2 TIMSTMP 1 TIMSTMP 0 Bit Number Bit Mnemonic TIMSTMP7:0 Low byte of Time Stamp See Figure 44. TIMTTC 15 TIMTTC 14 TIMTTC 13 TIMTTC 12 TIMTTC 11 TIMTTC 10 TIMTTC 9 TIMTTC 8 Bit Number Bit Mnemonic TIMTTC15:8 High byte of TTC Timer See Figure 44. TIMTTC 7 TIMTTC 6 TIMTTC 5 TIMTTC 4 TIMTTC 3 TIMTTC 2 TIMTTC 1 TIMTTC 0 Bit Number Bit Mnemonic TIMTTC7:0 Low Byte of TTC Timer See Figure 44.

4126H–CAN–01/05 Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of two compare/capture modules. Its clock input can be programmed to count any of the following signals: PCA clock frequency/6 (See “clock” section) PCA clock frequency/2 Timer 0 overflow External input on ECI (P1.2) Each compare/capture modules can be programmed in any one of the following modes: Rising and/or falling edge capture, Software timer High-speed output Pulse width modulator When the compare/capture modules are programmed in capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. Both modules and the PCA timer overflow share one interrupt vector. The PCA timer/counter and compare/capture modules share Port 1 for external I/Os. These pins are listed below. If the pin is not used for the PCA, it can still be used for standard I/O. PCA Timer The PCA timer is a common time base for both modules (See Figure 9). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (See Table 8) and can be programmed to run at: 1/6 the PCA clock frequency. 1/2 the PCA clock frequency. The Timer 0 overflow. The input on the ECI pin (P1.2). PCA Component External I/O Pin 16-bit Counter P1.2/ECI 16-bit Module 0 P1.3/CEX0 16-bit Module 1 P1.4/CEX1

Figure 46. PCA Timer/Counter The CMOD register includes three additional bits associated with the PCA. The CIDL bit which allows the PCA to stop during idle mode. CCON register to be set when the PCA timer overflows. The CR bit must be set to run the PCA. The PCA is shut off by clearing this bit. if the ECF bit in CMOD register is set. The CF bit can only be cleared by software.

4126H–CAN–01/05 PCA Modules Each one of the two compare/capture modules has six possible functions. It can perform: 16-bit Capture, positive-edge triggered 16-bit Capture, negative-edge triggered 16-bit Capture, both positive and negative-edge triggered 16-bit Software Timer 16-bit High Speed Output 8-bit Pulse Width Modulator. Each module in the PCA has a special function register associated with it (CCAPM0 for module 0 ...). The CCAPM0:1 registers contain the bits that control the mode that each module will operate in. The ECCF bit enables the CCF flag in the CCON register to generate an interrupt when a match or compare occurs in the associated module. The PWM bit enables the pulse width modulation mode. The TOG bit when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module’s capture/compare register. The match bit MAT when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module’s capture/compare register. The two bits CAPN and CAPP in CCAPMn register determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled. The bit ECOM in CCAPM register when set enables the comparator function.

SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set. Figure 49. PCA 16-bit Software Timer and High Speed Output Mode

0 MATn TOGn0 ECCFn

For software Timer mode, set ECOMn and MATn. For high speed output mode, set ECOMn, MATn and TOGn.

each time a match occurs between the PCA counter and the module’s capture registers. Figure 50. PCA High Speed Output Mode

Figure 51. PCA PWM Mode

4126H–CAN–01/05 PCA Registers Table 94. CMOD Register PCA Counter Idle Control bit Clear to let the PCA run during Idle mode. Set to stop the PCA when Idle mode is invoked. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. 2-1 CPS1:0 EWC Count Pulse Select bits CPS1 CPS0 Clock source Internal Clock, FPca/6 Internal Clock, FPca/2 Timer 0 overflow External clock at ECI/P1.2 pin (Max. Rate = FPca/4) ECF Enable PCA Counter Overflow Interrupt bit Clear to disable CF bit in CCON register to generate an interrupt. Set to enable CF bit in CCON register to generate an interrupt.

4126H–CAN–01/05 Table 95. CCON Register PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA interrupt request if the ECF bit in CMOD register is set. Must be cleared by software. CR PCA Timer/Counter Run Control bit Clear to turn the PCA Timer/Counter off. Set to turn the PCA Timer/Counter on. 5-2 Reserved The value read from these bist are indeterminate. Do not set these bits. CCF1 PCA Module 1 Compare/Capture Flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 1 bit in CCAPM 1 register is set. Must be cleared by software. CCF0 PCA Module 0 Compare/Capture Flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 0 bit in CCAPM 0 register is set. Must be cleared by software.

4126H–CAN–01/05 Table 96. CCAPnH Registers Table 97. CCAPnL Registers 7:0 CCAPnH 7:0 High byte of EWC-PCA comparison or capture values CCAPnL 7 CCAPnL 6 CCAPnL 5 CCAPnL 4 CCAPnL 3 CCAPnL 2 CCAPnL 1 CCAPnL 0 Bit Number Bit Mnemonic 7:0 CCAPnL 7:0 Low byte of EWC-PCA comparison or capture values

4126H–CAN–01/05 Table 98. CCAPMn Registers The Value read from this bit is indeterminate. Do not set this bit. ECOMn Enable Compare Mode Module x bit Clear to disable the Compare function. Set to enable the Compare function. The Compare function is used to implement the software Timer, the high-speed output, the Pulse Width Modulator (PWM) and the Watchdog Timer (WDT). CAPPn Capture Mode (Positive) Module x bit Clear to disable the Capture function triggered by a positive edge on CEXx pin. Set to enable the Capture function triggered by a positive edge on CEXx pin CAPNn Capture Mode (Negative) Module x bit Clear to disable the Capture function triggered by a negative edge on CEXx pin. Set to enable the Capture function triggered by a negative edge on CEXx pin. MATn Match Module x bit Set when a match of the PCA Counter with the Compare/Capture register sets CCFx bit in CCON register, flagging an interrupt. TOGn Toggle Module x bit The toggle mode is configured by setting ECOMx, MATx and TOGx bits. Set when a match of the PCA Counter with the Compare/Capture register toggles the CEXx pin. PWMn Pulse Width Modulation Module x Mode bit Set to configure the module x as an 8-bit Pulse Width Modulator with output waveform on CEXx pin. ECCFn Enable CCFx Interrupt bit Clear to disable CCFx bit in CCON register to generate an interrupt request. Set to enable CCFx bit in CCON register to generate an interrupt request.

4126H–CAN–01/05 Table 99. CH Register Table 100. CL Register 7:0 CH 7:0 High byte of Timer/Counter CL 7 CL 6 CL 5 CL 4 CL 3 CL 2 CL 1 CL 0 Bit Number Bit Mnemonic 7:0 CL0 7:0 Low byte of Timer/Counter

4126H–CAN–01/05 Analog-to-Digital Converter (ADC) This section describes the on-chip 10-bit analog-to-digital converter of the T89C51CC02. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10-bit- cascaded potentiometric ADC. Two modes of conversion are available: - Standard conversion (8 bits). - Precision conversion (10 bits). For the precision conversion, set bit PSIDLE in ADCON register and start conversion. The device is in a pseudo-idle mode, the CPU does not run but the peripherals are always running. This mode allows digital noise to be as low as possible, to ensure high precision conversion. For this mode it is necessary to work with end of conversion interrupt, which is the only way to wake the device up. If another interrupt occurs during the precision conversion, it will be served only after this conversion is completed. 8 channels with multiplexed inputs 10-bit cascaded potentiometric ADC Conversion time 16 micro-seconds (typ.) Zero Error (offset) ± 2 LSB max Positive External Reference Voltage Range (VAREF) 2.4 to 3.0-volt (typ.) ADCIN Range 0 to 3-volt Integral non-linearity typical 1 LSB, max. 2 LSB Differential non-linearity typical 0.5 LSB, max. 1 LSB Conversion Complete Flag or Conversion Complete Interrupt Selectable ADC Clock ADC Port1 I/O Functions Port 1 pins are general I/O that are shared with the ADC channels. The channel select bit in ADCF register define which ADC channel/port1 pin will be used as ADCIN. The remaining ADC channels/port1 pins can be used as general purpose I/O or as the alter- nate function that is available. A conversion launched on a channel which are not selected on ADCF register will not have any effect. VAREF VAREF should be connected to a low impedance point and must remain in the range specified VAREF absolute maximum range (See section “AC-DC”). . If the ADC is not used, it is recommended to tie VAREF to VAGND.

Table 101. Selected Analog input 3FFh if greater than VAREF and 000h if less than VAGND. The ADC clock is the same as CPU. caler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency. Figure 54. A/D Converter Clock in ADCON register. In this mode the power dissipation is reduced. EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software.

Figure 55. ADC interrupt structure

1. Configure P1.2 and P1.3 in ADC channels
2. Start a standard conversion
3. Start a precision conversion (need interrupt ADC)

4126H–CAN–01/05 Registers Table 102. ADCF Register Table 103. ADCON Register CH 0:7 Channel Configuration Set to use P1.x as ADC input. Clear to use P1.x as standart I/O port. PSIDLE ADEN ADEOC ADSST SCH2 SCH1 SCH0 Bit Number Bit Mnemonic The value read from these bits are indeterminate. Do not set these bits. PSIDLE Pseudo Idle Mode (Best Precision) Set to put in idle mode during conversion Clear to convert without idle mode. ADEN Enable/Standby Mode Set to enable ADC Clear for Standby mode. ADEOC End Of Conversion Set by hardware when ADC result is ready to be read. This flag can generate an interrupt. Must be cleared by software. ADSST Start and Status Set to start an A/D conversion. Cleared by hardware after completion of the conversion 2-0 SCH2:0 Selection of Channel to Convert See Table 101

4126H–CAN–01/05 Table 104. ADCLK Register Table 105. ADDH Register Table 106. ADDL Register The value read from these bits are indeterminate. Do not set these bits. 4-0 PRS4:0 Clock Prescaler Fadc = Fcpuclock/(4*PRS)) in X1 mode Fadc=Fcpuclock/(2*PRS) in X2 mode ADAT 9 ADAT 8 ADAT 7 ADAT 6 ADAT 5 ADAT 4 ADAT 3 ADAT 2 Bit Number Bit Mnemonic ADAT9:2 ADC result bits 9-2 ADAT 1 ADAT 0 Bit Number Bit Mnemonic The value read from these bits are indeterminate. Do not set these bits. 1-0 ADAT1:0 ADC result bits 1-0

interrupt, a timer overrun interrupt and an ADC. These interrupts are shown below. Figure 56. Interrupt Control System

which must be cleared to disable all the interrupts at the same time. bit values and priority levels associated with each combination. Table 107. Priority Level bit Values determined by the polling sequence, See Table 108. Table 108. Interrupt Priority Within Level

4126H–CAN–01/05 Registers Figure 57. IEN0 Register Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. EC PCA Interrupt Enable Clear to disable the PCA interrupt. Set to enable the PCA interrupt. ET2 Timer 2 Overflow Interrupt Enable bit Clear to disable Timer 2 overflow interrupt. Set to enable Timer 2 overflow interrupt. ES Serial port Enable bit Clear to disable serial port interrupt. Set to enable serial port interrupt. ET1 Timer 1 Overflow Interrupt Enable bit Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. EX1 External Interrupt 1 Enable bit Clear to disable external interrupt 1. Set to enable external interrupt 1. ET0 Timer 0 Overflow Interrupt Enable bit Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. EX0 External Interrupt 0 Enable bit Clear to disable external interrupt 0. Set to enable external interrupt 0.

4126H–CAN–01/05 Figure 58. IEN1 Register The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. ETIM TImer overrun Interrupt Enable bit Clear to disable the timer overrun interrupt. Set to enable the timer overrun interrupt. EADC ADC Interrupt Enable bit Clear to disable the ADC interrupt. Set to enable the ADC interrupt. ECAN CAN Interrupt Enable bit Clear to disable the CAN interrupt. Set to enable the CAN interrupt.

4126H–CAN–01/05 Table 109. IPL0 Register The value read from this bit is indeterminate. Do not set this bit. PPC PCA Interrupt Priority bit Refer to PPCH for priority level PT2 Timer 2 Overflow Interrupt Priority bit Refer to PT2H for priority level. PS Serial Port Priority bit Refer to PSH for priority level. PT1 Timer 1 Overflow Interrupt Priority bit Refer to PT1H for priority level. PX1 External Interrupt 1 Priority bit Refer to PX1H for priority level. PT0 Timer 0 Overflow Interrupt Priority bit Refer to PT0H for priority level. PX0 External Interrupt 0 Priority bit Refer to PX0H for priority level.

4126H–CAN–01/05 Table 110. IPL1 Register The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. POVRL Timer Overrun Interrupt Priority Level Less Significant bit Refer to PI2CH for priority level. PADCL ADC Interrupt Priority Level Less Significant bit Refer to PSPIH for priority level. PCANL CAN Interrupt Priority Level Less Significant bit Refer to PKBH for priority level.

4126H–CAN–01/05 Table 111. IPH0 Register The value read from this bit is indeterminate. Do not set this bit. PPCH PCA Interrupt Priority Level Most Significant bit PPCH PPC Priority level Lowest Highest priority PT2H Timer 2 Overflow Interrupt High Priority bit PT2H PT2 Priority Level Lowest Highest PSH Serial Port High Priority bit PSH PS Priority Level Lowest Highest PT1H Timer 1 Overflow Interrupt High Priority bit PT1H PT1 Priority Level Lowest Highest PX1H External Interrupt 1 High Priority bit PX1H PX1 Priority Level Lowest Highest PT0H Timer 0 Overflow Interrupt High Priority bit PT0H PT0 Priority Level Lowest Highest PX0H External Interrupt 0 High Priority bit PX0H PX0 Priority Level Lowest Highest

4126H–CAN–01/05 Table 112. IPH1 Register The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. POVRH Timer Overrun Interrupt Priority Level Most Significant bit POVRH POVRLPriority level Lowest Highest PADCH ADC Interrupt Priority Level Most Significant bit PADCH PADCL Priority level Lowest Highest PCANH CAN Interrupt Priority Level Most Significant bit PCANH PCANLPriority level Lowest Highest

4126H–CAN–01/05

Electrical Characteristics

TA = -40°C to +85°C; VSS = 0 V; VCC = 3 volts to 5.5 volts; F = 0 to 40 MHz Notes: 1. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature. 2. Flash retention is guaranteed with the same formula for VCC min down to 0V. 3. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Absolute Maximum Ratings Note: Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Power Dissipation value is based on the maximum allowable die temperature and the thermal resistance of the package. Table 113. DC Parameters in Standard Voltage

0.7 VCC

Table 115. Symbol Description (F = 40 MHz) Table 117. AC Parameters for a Variable Clock Table 116. AC Parameters for a Fix Clock (F = 40 MHz)

10 T - x

5 T - x

2 T - x

5 T- x

Table 118. AC Parameters AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”.

Valid in normal clock mode. In X2 Mode XTAL2 must be changed to XTAL2/2. Table 119. Memory AC Timing Figure 63. Flash Memory - Internal Busy Waveforms Table 120. AC Parameters for A/D Conversion

4126H–CAN–01/05

Ordering Information

Factory default programming for T89C51CC02CA-xxxx is Bootloader CAN and HSB = BBh: X1 mode BLJB = 0 : jump to Bootloader LB2 = 0 : Security Level 3.(1) Factory default programming for T89C51CC02UA-xxxx is Bootloader UART and HSB = BBh: X1 mode BLJB = 0 : jump to Bootloader LB2 = 0 : Security Level 3.(1) Notes: 1. LB2 = 0 is not described in Table 22 Program load bit. LB2 = 0 is equivalent to LB1 = 0: Security Level 3. 2. Customer can change these modes by re-programming with a parallel programmer, this can be done by an Atmel distributor. Part Number Bootloader Temperature Range Package Packing Product Marking T89C51CC02CA-RATIM CAN(2) Industrial VQFP32 Tray 89C51CC02CA-IM T89C51CC02CA-SISIM CAN(2) Industrial PLCC28 Stick 89C51CC02CA-IM T89C51CC02CA-TDSIM CAN(2) Industrial SOIC24 Stick 89C51CC02CA-IM T89C51CC02CA-TISIM CAN(2) Industrial SOIC28 Stick 89C51CC02CA-IM T89C51CC02UA-RATIM UART(2) Industrial VQFP32 Tray 89C51CC02UA-IM T89C51CC02UA-SISIM UART(2) Industrial PLCC28 Stick 89C51CC02UA-IM T89C51CC02UA-TDSIM UART(2) Industrial SOIC24 Stick 89C51CC02UA-IM T89C51CC02UA-TISIM UART(2) Industrial SOIC28 Stick 89C51CC02UA-IM

4126H–CAN–01/05 Package Drawings VQFP32

4126H–CAN–01/05 PLCC28

4126H–CAN–01/05 SOIC24

4126H–CAN–01/05 SOIC28

4126H–CAN–01/05 Datasheet Change Log for T89C51CC02 Changes from 4126C- 10/02 to 4126D-04/03 Changed the endurance of Flash to 100, 000 Write/Erase cycles. Added note on Flash retention formula for VIH1, in Section "DC Parameters for Standard Voltage", page 141.Changes from 4129F-11/02 to 4129G-04/03 Changed the endurance of Flash to 100, 000 Write/Erase cycles. Added note on Flash retention formula for VIH1, in Section "DC Parameters for Standard Voltage", page 141. Changes from 4126D- 05/03 to 4126E - 10/03 Updated “Electrical Characteristics” on page 138. Corrected Figure 39 on page 80. Changes from 4126E - 10/03 to 4126F - 12/03 Changed value of IPDMAX to 400, Section "Absolute Maximum Ratings", page 138. PCA , CPS0, register correction, Section "PCA Registers", page 119. Cross Memory section added. Section "Operation Cross Memory Access", page 42. Changes from 4126F - 12/03 4126G - 08/04 Figure clock-out mode modified see, Figure 30 on page 63. Corrected error in Table 50 on page 68, (1.25ms to 1.25s) for Time-out Computation. Added exlplanation on the CAN protocol, see Section “CAN Controller”, page 71.

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