T89C51AC2-SLSE-M

T89C51AC2_01 ATMEL | Alldatasheet

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Draft.A- March 30, 2001 1 Preview - Confidential T89C51AC2 8-bit MCU with 32K bytes Flash, 10 bits A/D and EEPROM 1. Description The T89C51AC2 is a high performance CMOS FLASH version of the 80C51 CMOS single chip 8-bit microcontrollers. It contains a 32Kbytes Flash memory block for program and data. The 16K bytes or 32K bytes FLASH memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard V CC pin. The T89C51AC2 retains all features of the 80C52 with 256 bytes of internal RAM, a 7-source 4-level interrupt controller and three timer/counters. In addition, the T89C51AC2 has a 10 bits A/D converter, a 2Kbytes Boot Flash Memory, 2 Kbytes EEPROM for data, a Programmable Counter Array, an XRAM of 1024 byte, a Hardware Watchdog Timer and a more versatile serial channel that facilitates multiprocessor communication (EUART). The fully static design of the T89C51AC2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The T89C51AC2 has 2 software-selectable modes of reduced activity and 8 bit clock prescaler for further reduction in power consumption. In the Idle mode the CPU is frozen while the peripherals and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. The added features of the T89C51AC2 make it more powerful for applications that need A/D conversion, pulse width modulation, high speed I/O and counting capabilities such as industrial control, consumer goods, alarms, motor control, ... While remaining fully compatible with the 80C51 it offers a superset of this standard microcontroller. In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time. 2. Features

• 80C51 core architecture:
• 256 bytes of on-chip RAM
• 1Kbytes of on-chip XRAM
• 32 Kbytes of on-chip Flash memory
• 2 Kbytes of on-chip Flash for Bootloader
• 2 Kbytes of on-chip EEPROM
• 14-source 4-level interrupt
• Three 16-bit timer/counter
• Full duplex UART compatible 80C51
• maximum crystal frequency 40 MHz. In X2 mode,

20 MHz (CPU core, 40 MHz)

• Five ports: 32 + 2 digital I/O lines
• Five channel 16-bit PCA with: - PWM (8-bit) - High-speed output - Timer and edge capture
• Double Data Pointer
• 21 bit watchdog timer (including 7 programmable bits)
• A 10-bit resolution analog to digital converter (ADC) with 8 multiplexed inputs
• 20 microsecond conversion time
• Two conversion modes
• On-chip emulation Logic (enhanced Hook system)
• Power saving modes:
• Idle mode
• Power down mode
• Power supply: 5V +/- 10% (or 3V** +/- 10%)
• Temperature range: Industrial (-40 to +85C)
• Packages: TQFP44, PLCC44

2 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 3. Block Diagram Timer 0 INT RAM 256x8 RxD TxD WR RD EA PSEN ALE XTAL2 XTAL1 UART CPU Timer 1 INT1 CtrlINT0 C51 CORE Port 0 Port 1Port 2Port 3 Parallel I/O Ports & Ext. Bus P1(1) ERAM 1kx8 IB-bus PCA RESET Watch Dog PCA ECI Vss Vcc (1): 8 analog Inputs / 8 Digital I/O Timer2 T2EX Port 4 P4(2) Emul Unit 10 bit ADC Flash 32kx Boot loader 2kx8 EE PROM 2kx8 (2): 2-Bit I/O Port

Draft.A - March 30, 2001 3 Preview - Confidential T89C51AC2 4. Pin Configuration PLCC44 P1.3 / AN3 / CEX0 P1.2 / AN2 / ECI P1.1 / AN1 / T2EX P1.0 / AN 0 / T2 V AREF V AGND RESET VSS VCC XTAL1 XTAL2 P3.7 / RD P4.0 P4.1 P2.7 / A15 P2.6 / A14 P2.5 / A13 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P3.6 / WR ALE PSEN P0.7 / AD7 P0.6 / AD6 P0.5 / AD5 P0.2 / AD2 P0.3 / AD3 P0.4 / AD4 P0.1 / AD1 P0.0 / AD0 P2.0 / A8 P1.4 / AN4 / CEX1 P1.5 / AN5 / CEX2 P1.6 / AN6 / CEX3 P1.7 / AN7 / CEX4 EA P3.0 / RxD P3.1 / TxD P3.2 /INT0 P3.3 /INT1 P3.4 / T0 P3.5 / T1 43 42 41 40 3944 38 37 36 35 34 1213 17 161514 20 1918 2122 TQFP44 P1.4 / AN4 / CEX1 P1.5 / AN5 / CEX2 P1.6 / AN6 / CEX3 P1.7 / AN7 / CEX4 EA P3.0 / RxD P3.1 / TxD P3.2 /INT0 P3.3 /INT1 P3.4 / T0 P3.5 / T1 ALE PSEN P0.7 / AD7 P0.6 / AD6 P0.5 / AD5 P0.2 /AD2 P0.3 /AD3 P0.4 /AD4 P0.1 /AD1 P0.0 /AD0 P2.0 / A8 P1.3 / AN3 / CEX0 P1.2 / AN2 / ECI P1.1 / AN1 / T2EX P1.0 / AN 0 / T2 V AREF V AGND RESET VSS VCC XTAL1 XTAL2 P3.7 / RD P4.0 P4.1 P2.7 / A15 P2.6 / A14 P2.5 / A13 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P3.6 / WR

Table 1. Pin Description VSS GND Circuit ground potential. VCC Supply voltage during normal, idle, and power-down operation. In the T89C51AC2 Port 0 can sink or source 5mA. It can drive CMOS inputs without external pull-ups. of the internal pull-ups. Port 1 pins are assigned to be used as analog inputs via the ADCCF register. external clock input and the PCA module I/O. External clock input for Timer/counter2. Trigger input for Timer/counter2. PCA module 0 Entry of input/PWM output. PCA module 1 Entry of input/PWM output. PCA module 2 Entry of input/PWM output. PCA module 3 Entry of input/PWM output. PCA module 4 Entry ot input/PWM output. T89C51AC2 Port 1 can sink or source 5mA. It can drive CMOS inputs without external pull-ups. addresses (MOVX @Ri), Port 2 transmits the contents of the P2 special function register. It also receives high-order addresses and control signals during program validation. In the T89C51AC2 Port 2 can sink or source 5mA. It can drive CMOS inputs without external pull-ups.

Draft.A - March 30, 2001 5 Preview - Confidential T89C51AC2 P3.0:7 I/O Port 3: Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-ups. The output latch corresponding to a secondary function must be programmed to one for that function to operate (except for TxD and WR). The secondary functions are assigned to the pins of port 3 as follows: P3.0 / RxD: Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface P3.1 / TxD: Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface P3.2 /INT0: External interrupt 0 input / timer 0 gate control input P3.3 /INT1: External interrupt 1 input / timer 1 gate control input P3.4 / T0: Timer 0 counter input P3.5 / T1: Timer 1 counter input P3.6 /WR: External Data Memory write strobe; latches the data byte from port 0 into the external data memory P3.7 /RD: External Data Memory read strobe; Enables the external data memory. In the T89C51AC2 Port 3 can sink or source 5mA. It can drive CMOS inputs without external pull-ups. P4.0:1 I/O Port 4: Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull- up transistor. In the T89C51AC2 Port 3 can sink or source 5mA. It can drive CMOS inputs without external pull-ups. RESET I/O Reset: A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down resistor to VSS permits power-on reset using only an external capacitor to VCC. ALE O ALE: An Address Latch Enable output for latching the low byte of the address during accesses to the external memory. The ALE is activated every 1/6 oscillator periods (1/3 in X2 mode) except during an external data memory access. When instructions are executed from an internal FLASH ( EA = 1), ALE generation can be disabled by the software. PSEN O PSEN: The Program Store Enable output is a control signal that enables the external program memory of the bus during external fetch operations. It is activated twice each machine cycle during fetches from the external program memory. (However, when executing outside of the external program memory two activations of PSEN are skipped during each access to the external Data memory). The PSEN is not activated during fetches from the internal data memory. EA I EA: When External Access is held at the high level, instructions are fetched from the internal FLASH when the program counter is less then 8000H. When held at the low level, CANARY fetches all instructions from the external program memory XTAL1 I XTAL1: Input of the inverting oscillator amplifier and input of the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle of 50% should be maintained. XTAL2 O XTAL2: Output from the inverting oscillator amplifier. Pin Name Type Description

Table 2. Read-Modify-Write Instructions read of the latch rather than the pins returns the correct logic-one value. Port 1, Port 2, Port 3 and Port 4 have fixed internal pull-ups and are referred to as "quasi-bidirectional" Ports. condions by a logical one written to the latch. instruction after Read-Modify-Write instruction cycle. current during 2 oscillator clock periods. The internal pull-ups are field-effect transistors rather than linear resistors. transition in the Port latch. A logical one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter.

1. Port 2 p1 assists the logic-one output for memory bus cycles.

Figure 4. Internal Pull-Up Configurations

Table 3. C51 Core SFRs Table 4. I/O Port SFRs Table 5. Timers SFRs Table 6. Serial I/O Port SFRs

Table 7. PCA SFRs Table 8. Interrupt SFRs Table 9. ADC SFRs

Table 10. Other SFRs

Table 11. SFR’s mapping

1. These registers are bit-addressable.

ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF.

14 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 6. Clock 6.1. Introduction The T89C51AC2 core needs only 6 clock periods per machine cycle. This feature, called ”X2”, provides the following advantages:

• Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power.
• Saves power consumption while keeping the same CPU power (oscillator power saving).
• Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes.
• Increases CPU power by 2 while keeping the same crystal frequency. In order to keep the original C51 compatibility, a divider-by-2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by the software. An extra feature is available for selected hardware in the X2 mode. This feature allows starting of the CPU in the X2 mode, without starting in the standard mode. The hardware CPU X2 mode can be read and write via IAP (SetX2mode, ClearX2mode, ReadX2mode), see In- System Programming section. These IAPs are detailed in the "In-System Programming" section. 6.2. Description The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 5. shows the clock generation block diagram. The X2 bit is validated on the XTAL1÷2 rising edge to avoid glitches when switching from the X2 to the STD mode. Figure 6 shows the mode switching waveforms.

Figure 5. Clock CPU Generation Diagram

Figure 6. Mode Switching Waveforms UART with a 4800 baud rate will have a 9600 baud rate.

1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit has no effect.

Figure 7. CKCON Register The value read from this bit is indeterminate. Do not set this bit.

6 WDX2

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

5 PCAX2

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

4 SIX2

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

3 T2X2

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

2 T1X2

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

1 T0X2

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6 clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2"bits.

external program/code memory spaces depending on the product. The FLASH memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. available using specific programming tool. Figure 8. Program/Code Memory Organization

1. If the program executes exclusively from on-chip code memory (not from external memory), beware of executing code from the upper byte

does not affect Ports 0 and 2. Figure 9 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 12 describes the external memory interface signals.

32 Kbytes

• Flash memory FM0: containing 32 Kbytes of program memory (user space) organized into 128 byte pages,
• Flash memory FM1: 2 Kbytes for boot loader and Application Programming Interfaces (API). The FM0 supports both parallel programming and Serial In-System Programming (ISP) whereas FM1 supports only parallel programming by programmers. The ISP mode is detailed in the "In-System Programming" section. All Read/Write access operations on FLASH Memory by user application are managed by a set of API described in the "In-System Programming" section.

Figure 11. Flash memory architecture

1. The memory array (user space) 32 Kbytes
2. The Hardware security bits
3. The column latch registers

This row is a part of FM0 and has a size of 128 bytes. The extra row may contain information for boot loader usage.

2 Kbytes

Draft.A - March 30, 2001 21 Preview - Confidential T89C51AC2 7.3.1.3. Hardware security space The Hardware security space is a part of FM0 and has a size of 1 byte. The 4 MSB can be read/written by software, the 4 LSB can only be read by software and written by hardware in parallel mode. 7.3.1.4. Column latches The column latches, also part of FM0, have a size of full page (128 bytes). The column latches are the entrance buffers of the three previous memory locations (user array, XROW and Hardware security byte).

The CPU interfaces to the flash memory through the FCON register and AUXR1 register.

• Map the memory spaces in the adressable space
• Launch the programming of the memory spaces
• Get the status of the flash memory (busy/not busy)
• Select the flash memory FM0/FM1. 7.4.1. Mapping of the memory space By default, the user space is accessed by MOVC instruction for read only. The column latches space is made accessible by setting the FPS bit in FCON register. Writing is possible from 0000h to 7FFFh, address bits 6 to 0 are used to select an address within a page while bits 14 to 7 are used to select the programming address of the page. Setting this bit takes precedence on the EXTRAM bit in AUXR register. The other memory spaces (user, extra row, hardware security) are made accessible in the code segment by programming bits FMOD0 and FMOD1 in FCON register in accordance with Table 13. A MOVC instruction is then used for reading these spaces. Table 13..FM0 blocks select bits 7.4.2. Launching programming FPL3:0 bits in FCON register are used to secure the launch of programming. A specific sequence must be written in these bits to unlock the write protection and to launch the programming. This sequence is 5 followed by A. Table 14 summarizes the memory spaces to program according to FMOD1:0 bits.

Table 14. Programming spaces more available for fetching code. Interrupts that may occur during programming time must be disable to avoid any spurious exit of the idle mode.

5 X 0 0 No action

5 X 0 1 No action

5 X 1 0 No action

5 X 1 1 No action

Draft.A - March 30, 2001 23 Preview - Confidential T89C51AC2 7.4.3. Status of the flash memory The bit FBUSY in FCON register is used to indicate the status of programming. FBUSY is set when programming is in progress. 7.4.4. Selecting FM0/FM1 The bit ENBOOT in AUXR1 register is used to choose between FM0 and FM1 mapped up to F800h.

to program the whole memory by byte, by page or by any number of bytes in a page. programmed in the corresponding page.

• Map the column latch space by setting FPS bit.
• Load the DPTR with the address to load.
• Load Accumulator register with the data to load.
• Execute the MOVX @DPTR, A instruction.
• If needed loop the three last instructions until the page is completely loaded.

Figure 12. Column Latches Loading Procedure

Draft.A - March 30, 2001 25 Preview - Confidential T89C51AC2 7.4.6. Programming the FLASH Spaces User The following procedure is used to program the User space and is summarized in Figure 13:

• Load data in the column latches from address 0000h to 7FFFh1.
• Disable the interrupts.
• Launch the programming by writing the data sequence 50h followed by A0h in FCON register. The end of the programming indicated by the FBUSY flag cleared.
• Enable the interrupts. Note: 1. The last page address used when loading the column latch is the one used to select the page programming address. Extra Row The following procedure is used to program the Extra Row space and is summarized in Figure 13:
• Load data in the column latches from address FF80h to FFFFh.
• Disable the interrupts.
• Launch the programming by writing the data sequence 52h followed by A2h in FCON register. The end of the programming indicated by the FBUSY flag cleared.
• Enable the interrupts.

Figure 13. Flash and Extra row Programming Procedure

• Set FPS and map Harware byte (FCON = 0x0C)
• Disable the interrupts.
• Load DPTR at address 0000h.
• Load Accumulator register with the data to load.
• Execute the MOVX @DPTR, A instruction.
• Launch the programming by writing the data sequence 54h followed by A4h in FCON register. The end of the programming indicated by the FBusy flag cleared.
• Enable the interrupts.

Figure 14. Hardware Programming Procedure

• Map the User space by writing 00h in FCON register.
• Read one byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= 0000h to FFFFh. Extra Row The following procedure is used to read the Extra Row space and is summarized in Figure 15:
• Map the Extra Row space by writing 02h in FCON register.
• Read one byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= FF80h to FFFFh. Hardware Security The following procedure is used to read the HardwareSecurityspace and is summarized in Figure 15:
• Map the Hardware Security space by writing 04h in FCON register.
• Read the byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= 0000h.

Figure 15. Reading Procedure

Figure 16. FCON Register

3 FPS

Set to map the column latch space in the data memory space. Clear to re-map the data memory space.

0 FBUSY

Set by hardware when programming is in progress. Clear by hardware when programming is done. Can not be cleared by software.

1. The internal space mapped in three separate segments:

• the lower 128 bytes RAM segment.
• the upper 128 bytes RAM segment.
• the expanded 1024 bytes RAM segment (ERAM). 2. The external space. A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode. Figure 17 shows the internal and external data memory spaces organization.

Figure 17. Internal and External Data Memory Organization

64 Kbytes

for context switching in interrupt service routines. Table 15. Register Bank Selection these instructions. The bit addresses in this area are 00h to 7Fh. Figure 18. Lower 128 bytes Internal RAM Organization The upper 128 bytes of RAM are accessible from address 80h to FFh using only indirect addressing mode. and when EXTRAM= 1, the XRAM is selected. indeterminate after power-up and must then be initialized properly.

4 Banks of

8 Registers

of intensive usage of external memory accesses. is the data pointer 0 or the data pointer 1 (see Figure 22). Figure 22. Dual Data Pointer Implementation pointer and the other one as a “destination” pointer. compiler take also advantage of this feature by providing enhanced algorithm libraries.

Program Status Word Register. Figure 23. PSW Register Carry out from bit 1 of ALU operands. Carry out from bit 1 of addition operands. Refer to Table 15 for bits description. Overflow set by arithmetic operations. Set when ACC contains an odd number of 1’s. Cleared when ACC contains an even number of 1’s.

Figure 24. AUXR Register The value read from these bits are indeterminate. Do not set this bit. the RD/ and the WR/ pulse length is increased according to the value of M0. The value read from this bit is indeterminate. Do not set this bit.

1 EXTRAM

0 - Internal ERAM access using MOVX @ Ri / @ DPTR. 1 - External data memory access. 1 - ALE is active only during a MOVX or MOVC instruction.

Auxiliary Control Register 1. Figure 25. AUXR1 Register The value read from these bits is indeterminate. Do not set these bits.

5 ENBOOT

Clear this bit for disable boot flash. The value read from this bit is indeterminate. Do not set this bit. 3 GF3 General Purpose Flag 3.

20 Always Zero

This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3 flag. 1- Reserved for Data Pointer Extension.

0 DPS

Set to select second dual data pointer: DPTR1. Clear to select first dual data pointer: DPTR0.

38 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 9. EEPROM data memory 9.1. General description The 2k byte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction. A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming). The number of data written on the page may vary from 1 to 128 bytes (the page size). When programming, only the data written in the column latch is programmed and a ninth bit is used to obtain this feature. This provides the capability to program the whole memory by bytes, by page or by a number of bytes in a page. Indeed, each ninth bit is set when the writing the corresponding byte in a row and all these ninth bits are reset after the writing of the complete EEPROM row. 9.2. Write Data in the column latches Data is written by byte to the column latches as for an external RAM memory. Out of the 11 address bits of the data pointer, the 4 MSBs are used for page selection (row) and 7 are used for byte selection. Between two EEPROM programming sessions, all the addresses in the column latches must stay on the same page, meaning that the 4 MSB must no be changed. The following procedure is used to write to the column latches:

• Set bit EEE of EECON register
• Load DPTR with the address to write
• Store A register with the data to be written
• Execute a MOVX @DPTR, A
• If needed loop the three last instructions until the end of a 128 bytes page 9.3. Programming The EEPROM programming consists on the following actions:
• writing one or more bytes of one page in the column latches. Normally, all bytes must belong to the same page; if not, the first page address will be latched and the others discarded.
• launching programming by writing the control sequence (54h followed by A4h) to the EECON register.
• EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that the EEPROM segment is not available for reading.
• The end of programming is indicated by a hardware clear of the EEBUSY flag.

Draft.A - March 30, 2001 39 Preview - Confidential T89C51AC2 9.4. Read Data The following procedure is used to read the data stored in the EEPROM memory:

• Set bit EEE of EECON register
• Load DPTR with the address to read
• Execute a MOVX A, @DPTR

Figure 26. EECON Register Write 5Xh followed by AXh to EEPL to launch the programming. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.

1 EEE

Clear to map the XRAM space during MOVX.

0 EEBUSY

Set by hardware when programming is in progress. Cleared by hardware when programming is done. Can not be set or cleared by software.

Draft.A - March 30, 2001 41 Preview - Confidential T89C51AC2 10. In-System-Programming (ISP) 10.1. Introduction With the implementation of the User ROM and the Boot ROM in Flash technology the T89C51AC2 allows the system engineer the development of applications with a very high level of flexibility. This flexibility is based on the possibility to alter the customer programming on all stages of a product’s life:

• During the final production phase, the 1st personalization of the product by parallel or serial charging of the code in the User ROM and if wanted also a customized Boot loader in the Boot memory (Atmel will provide also a standard Boot loader by default).
• After assembling of the product in its final, embedded position by serial mode via the UART. This In-System-Programming (ISP) allows code modification over the total lifetime of the product. Besides the default Boot loader Atmel will provide to the customer also all the needed Application-Programming- Interfaces (API) which are needed for the ISP. The API will be located also in the Boot memory. This will allow the customer to have a full use of the 32 Kbyte user memory. Two blocks flash memories are implemented (see Figure 27):
• Flash memory FM0: containing 32 Kbytes of program memory organized in page of 128 bytes,
• Flash memory FM1: 2 Kbytes for default boot loader and Application Programming Interfaces (API). The FM0 supports both, hardware (parallel) and software programming whereas FM1 supports only hardware programming. The ISP functions are assumed by:
• FCON register & bit ENBOOT in AUXR1 register,
• Software Boot Vector (SBV), which can be read and modified by using an API or the parallel programming mode (see Figure 30) The SBV is stored in XROW.
• The Fuse bit Boot Loader Jump Bit (BLJB) can be read and modified using an API or the parallel programming mode. The BLJB is located in the Hardware security byte (see Figure 32).
• The Extra Byte (EB) and Boot Status Byte (BSB) can be modified only by using API (see Figure 32). EB is stored in XROW The bit ENBOOT in AUXR1 register allows to map FM1 between address F800h and FFFFh of FM0. The FM0 can be programed by: - The Atmel boot loader, located by default in FM1. - The user boot loader located in FM0 - The user boot loader located in FM1 in place of Atmel boot loader. API contained in FM1 can be called by the user boot loader located in FM0 at the address [SBV]00h. The user program simply calls the common entry point with appropriate parameters in FM1 to accomplish the desired operation (all these methods will describe in Application Notes on api-description). Boot Flash operations include: erase block, program byte or page, verify byte or page, program security lock bit, etc. Indeed, Atmel provides the binary code of the default Flash boot loader.

• The Atmel bootloader located in FM1 is activated by the application. Low level API routines (located in FM1) to program FM0 will be used. The interface used for serial downloading to FM0 is the UART. API can be called also by user’s bootloader located in FM0 at [SBV]00h.
• A further method exist in activating the Atmel boot loader by hardware activation.
• The FM0 can be programed also by the parallel mode using a programmer.

Figure 27. Flash Memory Mapping

2 Kbytes IAP

for the on-chip code and data located in FM0 and FM1. The only way for write this bits are the parallel mode. Table 17. Program Lock bit WARNING: Security level 2 and 3 should only be programmed after Flash and Core verification. memory returns non encrypted data. parallel programming of the Flash is disabled. 3 U P U Same as 2, also verify through parallel programming interface is disabled. 4 U U P Same as 3, also external execution is disabled.

44 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2

10.3 Boot Process

10.3.1. Software boot process example Many algorithms can be used for the software boot process. Before describing them, some explanations are needed for the utility of different flags and bytes available. Boot Loader Jump Bit (BLJB): - This bit indicates if on RESET the user wants jump on his application at address @0000h on FM0 or execute the boot loader at address @F800h on FM1. -B L J B=0o nparts delivered with bootloader programmed. - To read or modified this bit, the APIs are used. Boot Vector Address (SBV): - This byte contains the msb of the user boot loader address in FM0. - The default value of SBV is FFh (no user boot loader in FM0). - To read or modified this byte, the APIs are used. Extra Byte (EB) & Boot Status Byte (BSB): - These bytes are reserved for customer use. - To read or modified this byte, the APIs are used. Example of software boot process in FM1 (see Figure 29) In this example the Extra Byte (EB) is a configuration bit which forces the user boot loader execution even on the hardware condition. 10.3.2. Hardware boot process At the falling edge of RESET, the bit ENBOOT in AUXR1 register is initialized with the value of Boot Loader Jump Bit (BLJB). Further at the falling edge of RESET if the following conditions (called Hardware condition) are detected:

• PSEN low,
• EA high,
• ALE high (or not connected). FCON register is initialized with the value 00h and the program in FM1 can be executed. The Hardware condition allows jump in bootloader (FM1) whatever BLJB value. If no hardware condition is detected, the FCON register is initialized with the value F0h. Check of the BLJB value.
• If bit BLJB is cleared (BLJB = 1): User application in FM0 will be started at @0000h (standard reset).
• If bit BLJB is set (BLJB = 0): Boot loader will be started at @F800h in FM1.

Figure 28. Hardware Boot Process Algorithm

Figure 29. Example of Software Boot process is initialized with BLJB (Fuse bit).

Draft.A - March 30, 2001 47 Preview - Confidential T89C51AC2 10.4. 2 Application-Programming-Interface Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of FLASH pages. All calls are made by functions. All these APIs will be describe in an application note. API CALL Description PROGRAM DATA BYTE Write a byte in flash memory PROGRAM DATA PAGE Write a page (128 bytes) in flash memory PROGRAM EEPROM BYTE Write a byte in Eeprom memory ERASE BLOCK Erase all flash memory ERASE BOOT VECTOR (SBV) Erase the boot vector PROGRAM BOOT VECTOR (SBV) Write the boot vector PROGRAM EXTRA BYTE (EB) Write the extra byte READ DATA BYTE READ EEPROM BYTE READ FAMILY CODE READ MANUFACTURER CODE READ PRODUCT NAME READ REVISION NUMBER READ STATUS BIT (BSB) Read the status bit READ BOOT VECTOR (SBV) Read the boot vector READ EXTRA BYTE (EB) Read the extra byte PROGRAM X2 Write the hardware flag for X2 mode READ X2 Read the hardware flag for X2 mode PROGRAM BLJB Write the hardware flag BLJB READ BLJB Read the hardware flag BLJB

48 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 10.5. Application remarks

• After loading a new program using by the boot loader, the BLJB bit must be set to allow user application to start at RESET.
• A user bootloader can be mapped at address [SBV]00h. The byte SBV contains the high byte of the boot address, and can be read and written by API.
• The API can be called during user application, without disabling interrupt. The interrupts are disabled by some APIs, for complex operations.

Only the 4 MSB bits can be access by software. The 4 LSB bits can only be access by parallel mode. Figure 32. Hardware byte

7 X2B

Clear this bit to start in X2 mode.

6 BLJB

Set (=0)this bit to start the boot loader(@F800h) located in FM1. The value read from these bits are indeterminate.

Draft.A - March 30, 2001 53 Preview - Confidential T89C51AC2 11.3. Given Address Each device has an individual address that is specified in the SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be1111 1111b. For example: SADDR 0101 0110b SADEN11111100b Given 0101 01XXb Here is an example of how to use given addresses to address different slaves: Slave A: SADDR 1111 0001b SADEN11111010b Given 1111 0X0Xb Slave B: SADDR 1111 0011b SADEN11111001b Given 1111 0XX1b Slave C: SADDR 1111 0010b SADEN11111101b Given 1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g.1111 0000b). For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both set (e.g.1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g.1111 0001b). 11.4. Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.: SADDR 0101 0110b SADEN 1111 1100b SADDR OR SADEN 1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A: SADDR 1111 0001b SADEN11111010b Given 1111 1X11b, Slave B: SADDR 1111 0011b SADEN11111001b Given 1111 1X11B, Slave C: SADDR= 1111 0010b SADEN11111101b Given 1111 1111b For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh.

Figure 37. SCON Register Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. Refer to SM1 for serial port mode selection.

6 SM1

5 SM2

Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3.

4 REN

Clear to disable serial reception. Set to enable serial reception.

3 TB8

Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit.

2 RB8

Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. Clear to acknowledge interrupt. Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 35. and Figure 36. in the other modes.

Figure 41. PCON Register

7 SMOD1 Serial port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

6 SMOD0

Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. The value read from this bit is indeterminate. Do not set this bit.

4 POF

Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.

3 GF1

Cleared by user for general purpose usage. Set by user for general purpose usage.

2 GF0

Cleared by user for general purpose usage. Set by user for general purpose usage. Cleared by hardware when reset occurs. Set to enter power-down mode.

0 IDL

Clear by hardware when interrupt or reset occurs.

Draft.A - March 30, 2001 57 Preview - Confidential T89C51AC2 12. Timers/Counters 12.1. Introduction The T89C51AC2 implements two general-purpose, 16-bit Timers/Counters. They are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. The various operating modes of each Timer/Counter are described in the following sections. 12.2. Timer/Counter Operations For instance, a basic operation is Timer registers THx and TLx (x= 0, 1) connected in cascade to form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (see Figure 47) turns the Timer on by allowing the selected input to increment TLx. When TLx overflows it increments THx; when THx overflows it sets the Timer overflow flag (TFx) in TCON register. Setting the TRx does not clear the THx and TLx Timer registers. Timer registers can be accessed to obtain the current count or to enter preset values. They can be read at any time but TRx bit must be cleared to preset their values, otherwise the behavior of the Timer/Counter is unpredictable. The C/Tx# control bit selects Timer operation or Counter operation by selecting the divided-down peripheral clock or external pin Tx as the source for the counted signal. TRx bit must be cleared when changing the mode of operation, otherwise the behavior of the Timer/Counter is unpredictable. For Timer operation (C/Tx#= 0), the Timer register counts the divided-down peripheral clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock periods). The Timer clock rate is F PER / 6, i.e. FOSC / 12 in standard mode or FOSC / 6 in X2 mode. For Counter operation (C/Tx#= 1), the Timer register counts the negative transitions on the Tx external input pin. The external input is sampled every peripheral cycles. When the sample is high in one cycle and low in the next one, the Counter is incremented. Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition, the maximum count rate is F PER / 12, i.e. FOSC / 24 in standard mode or FOSC / 12 in X2 mode. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle. 12.3. Timer 0 Timer 0 functions as either a Timer or event Counter in four modes of operation. Figure 42 to Figure 45 show the logical configuration of each mode. Timer 0 is controlled by the four lower bits of TMOD register (see Figure 48) and bits 0, 1, 4 and 5 of TCON register (see Figure 47). TMOD register selects the method of Timer gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10 and M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0). For normal Timer operation (GATE0= 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer operation. Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an interrupt request. It is important to stop Timer/Counter before changing mode. 12.3.1. Mode 0 (13-bit Timer) Mode 0 configures Timer 0 as an 13-bit Timer which is set up as an 8-bit Timer (TH0 register) with a modulo 32 prescaler implemented with the lower five bits of TL0 register (see Figure 42). The upper three bits of TL0 register are indeterminate and should be ignored. Prescaler overflow increments TH0 register.

(TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode 3. Figure 45. Timer/Counter 0 in Mode 3: Two 8-bit Counters

• Timer 1 functions as either a Timer or event Counter in three modes of operation. Figure 42 to Figure 44 show the logical configuration for modes 0, 1, and 2. Timer 1’s mode 3 is a hold-count mode.
• Timer 1 is controlled by the four high-order bits of TMOD register (see Figure 48) and bits 2, 3, 6 and 7 of TCON register (see Figure 47). TMOD register selects the method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of operation (M11 and M01). TCON register provides Timer 1 control functions: overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type control bit (IT1).
• Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best suited for this purpose.
• For normal Timer operation (GATE1= 0), setting TR1 allows TL1 to be incremented by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control Timer operation.
• Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an interrupt request.
• When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it off and on.
• It is important to stop Timer/Counter before changing mode. 12.4.1. Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 register) with a modulo- 32 prescaler implemented with the lower 5 bits of the TL1 register (see Figure 42). The upper 3 bits of TL1 register are ignored. Prescaler overflow increments TH1 register. TR0 TCON.4 TF0 TCON.5 INT0# GATE0 TMOD.3 Overflow Timer 0 Interrupt Request C/T0# TMOD.2 TL0 (8 bits) TR1 TCON.6 TH0 (8 bits) TF1 TCON.7 Overflow Timer 1 Interrupt Request PERIPH CLOCK ÷ 6 PERIPH CLOCK ÷ 6

Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in cascade (see Figure 43). The selected input increments TL1 register. is preset by software. The reload leaves TH1 unchanged. control bit is not available i.e. when Timer 0 is in mode 3. setting ETx bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register. Figure 46. Timer Interrupt System

Timer/Counter Control Register. Figure 47. TCON Register

7 TF1

Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows.

6 TR1

Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1.

5 TF0

Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 0 register overflows.

4 TR0

Clear to turn off Timer/Counter 0. Set to turn on Timer/Counter 0.

3 IE1

Cleared by hardware when interrupt is processed if edge-triggered (see IT1). Set by hardware when external interrupt is detected on INT1# pin.

2 IT1

Clear to select low level active (level triggered) for external interrupt 1 (INT1#). Set to select falling edge active (edge triggered) for external interrupt 1.

1 IE0

Cleared by hardware when interrupt is processed if edge-triggered (see IT0). Set by hardware when external interrupt is detected on INT0# pin.

0 IT0

Clear to select low level active (level triggered) for external interrupt 0 (INT0#). Set to select falling edge active (edge triggered) for external interrupt 0.

Timer/Counter Mode Control Register. Figure 48. TMOD Register Figure 49. TH0 Register

7 GATE1

Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set.

6 C/T1#

Clear for Timer operation: Timer 1 counts the divided-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1.

5 M11

0 0 Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1). 0 1 Mode 1: 16-bit Timer/Counter. 1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL1). Reloaded from TH1 at overflow. 1 1 Mode 3: Timer 1 halted. Retains count.

4 M01

3 GATE0

Clear to enable Timer 0 whenever TR0 bit is set. Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set.

2 C/T0#

Clear for Timer operation: Timer 0 counts the divided-down system clock. Set for Counter operation: Timer 0 counts negative transitions on external pin T0.

1 M10

0 0 Mode 0: 8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0). 0 1 Mode 1: 16-bit Timer/Counter. 1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL0). Reloaded from TH0 at overflow. 1 1 Mode 3: TL0 is an 8-bit Timer/Counter. TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits.

0 M00

64 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 13. Timer 2 13.1. Introduction The T89C51AC2 timer 2 is compatible with timer 2 in the 80C52. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 that are cascade- connected. It is controlled by T2CON register (See Table 55) and T2MOD register (See Table 56). Timer 2 operation is similar to Timer 0 and Timer 1. C/ T2 selects FOSC /6 (timer operation) or external pin T2 (counter operation) as timer register input. Setting TR2 allows TL2 to be incremented by the selected input. Timer 2 includes the following enhancements:

• Auto-reload mode (up or down counter)
• Programmable clock-output 13.2. Auto-Reload Mode The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. This feature is controlled by the DCEN bit in T2MOD register (See Table 56). Setting the DCEN bit enables timer 2 to count up or down as shown in Figure 53. In this mode the T2EX pin controls the counting direction. When T2EX is high, timer 2 up-counts. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. When T2EX is low, timer 2 down-counts. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. The EXF2 bit toggles when timer 2 overflow or underflow, depending on the direction of the count. EXF2 does not generate an interrupt. This bit can be used to provide 17-bit resolution.

Figure 53. Auto-Reload Mode Up/Down Counter NOTE: X2 bit is located in CKCON register. In X2 mode, FOSC =F XTAL . In standard mode, FOSC =F XTAL /2. 4). The generated clock signal is brought out to T2 pin (P1.0).

• Set T2OE bit in T2MOD register.
• Clear C/T2 bit in T2CON register.
• Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers. (DOWN COUNTING RELOAD V ALUE) TF2 EXF2 TH2 (8-bit) TL2 (8-bit) RCAP2H (8-bit) RCAP2L (8-bit) FFh (8-bit) FFh (8-bit) TOGGLE (UP COUNTING RELOAD V ALUE) TIMER 2 INTERRUPT T2CONreg T2CONreg T2EX: 1=UP 2=DOWN CT/2 T2CON.1 TR2 T2CON.2 FT2 CLOCK Clock OutFrequency– F osc 2x2×

• Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or different depending on the application.
• To start the timer, set TR2 run control bit in T2CON register. It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers.

Figure 54. Clock-Out Mode

Figure 55. T2CON Register

7 TF2

TF2 is not set if RCLK=1 or TCLK = 1. Must be cleared by software. Set by hardware on timer 2 overflow.

6 EXF2

Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. Set to cause the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Must be cleared by software.

5 RCLK

Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.

4 TCLK

Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.

3 EXEN2

Clear to ignore events on T2EX pin for timer 2 operation.

2 TR2

1 C/T2#

Set for counter operation (input from T2 input pin).

0 CP/RL2#

If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1.

Figure 56. T2MOD Register Figure 57. TH2 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.

1 T2OE

Clear to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output.

0 DCEN

Clear to disable timer 2 as up/down counter. Set to enable timer 2 as up/down counter.

ranking from 16ms to 2s @Fosc = 12MHz. executed within the time required to prevent a WDT reset. Figure 61. WatchDog Timer

The three lower bits (S0, S1, S2) located into WDTPRG register permits to program the WDT duration. Table 19. Machine Cycle Count Table 20. Time-Out Computation

72 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 14.3. WatchDog Timer during Power down mode and Idle In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the user does not need to service the WDT. There are 2 methods of exiting Power Down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power Down is exited with hardware reset, servicing the WDT should occur as it normally does whenever T89C51AC2 is reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power Down. To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting T89C51AC2 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode.

74 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 15. Programmable Counter Array PCA 15.1. Introduction The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/ counter which serves as the time base for an array of five compare/capture modules. Its clock input can be programmed to count any of the following signals:

• PCA clock frequency / 6
• PCA clock frequency / 2
• Timer 0 overflow
• External input on ECI (P1.2) Each compare/capture modules can be programmed in any one of the following modes:
• rising and/or trailing edge capture,
• software timer,
• high-speed output,
• pulse width modulator. Module 4 can also be programmed as a watchdog timer. see Section "PCA Watchdog Timer". When the compare/capture modules are programmed in capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt vector. The PCA timer/counter and compare/capture modules share Port 1 for external I/Os. These pins are listed below. If the port is not used for the PCA, it can still be used for standard I/O. The PCA timer is a common time base for all five modules (see Figure 9). The timer count source is determined from the CPS1 and CPS0 bits in theCMOD SFR (see Table 8) and can be programmed to run at:
• 1/6 the PCA clock frequency.
• 1/2 the PCA clock frequency.
• the Timer 0 overflow.
• the input on the ECI pin (P1.2). PCA component External I/O Pin 16-bit Counter P1.2 / ECI 16-bit Module 0 P1.3 / CEX0 16-bit Module 1 P1.4 / CEX1 16-bit Module 2 P1.5 / CEX2 16-bit Module 3 P1.6 / CEX3 16-bit Module 4 P1.7 / CEX4

Figure 64. PCA Timer/Counter

Figure 65. PCA Timer Interrupts

ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated. Figure 66. PCA Capture Mode

an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set. Figure 67. PCA 16-bit Software Timer and High Speed Output Mode For software Timer mode, set ECOMn and MATn.

bits in the module’s CCAPMn SFR must be set. Figure 68. PCA High speed Output Mode

CCAPMn register must be set to enable the PWM mode. Figure 69. PCA PWM Mode

Draft.A - March 30, 2001 81 Preview - Confidential T89C51AC2 15.7. PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve system reliability without increasing chip count. Watchdog timers are useful for systems that are sensitive to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a watchdog. However, this module can still be used for other modes if the watchdog is not needed. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. To hold off the reset, the user has three options:

• 1. periodically change the compare value so it will never match the PCA timer,
• 2. periodically change the PCA timer value so it will never match the compare values, or
• 3. disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it. The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. If other PCA modules are being used the second option not recommended either. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option.

Figure 70. CMOD Register

7 CIDL

Clear to let the PCA run during Idle mode. Set to stop the PCA when Idle mode is invoked.

6 WDTE

The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.

2 CPS1

1 CPS0

0 ECF

Clear to disable CF bit in CCON register to generate an interrupt. Set to enable CF bit in CCON register to generate an interrupt.

Figure 71. CCON Register the ECF bit in CMOD register is set. Must be cleared by software. Clear to turn the PCA Timer/Counter off. Set to turn the PCA Timer/Counter on. The value read from this bit is indeterminate. Do not set this bit.

4 CCF4

4 bit in CCAPM 4 register is set. Must be cleared by software.

3 CCF3

3 bit in CCAPM 3 register is set. Must be cleared by software.

2 CCF2

2 bit in CCAPM 2 register is set. Must be cleared by software.

1 CCF1

1 bit in CCAPM 1 register is set. Must be cleared by software.

0 CCF0

0 bit in CCAPM 0 register is set. Must be cleared by software.

Figure 74. CCAPMn Registers The Value read from this bit is indeterminate. Do not set this bit.

6 ECOMn

Clear to disable the Compare function. Set to enable the Compare function. Width Modulator (PWM) and the Watchdog Timer (WDT).

5 CAPPn

Clear to disable the Capture function triggered by a positive edge on CEXx pin.

4 CAPNn

Clear to disable the Capture function triggered by a negative edge on CEXx pin. Set to enable the Capture function triggered by a negative edge on CEXx pin.

3 MATn

register, flagging an interrupt. Must be cleared by software.

2 TOGn

The toggle mode is configured by setting ECOMx, MATx and TOGx bits. Set when a match of the PCA Counter with the Compare/Capture register toggles the CEXx pin. Must be cleared by software.

1 PWMn

Set to configure the module x as an 8-bit Pulse Width Modulator with output waveform on CEXx pin. Must be cleared by software.

0 ECCFn

Clear to disable CCFx bit in CCON register to generate an interrupt request. Set to enable CCFx bit in CCON register to generate an interrupt request.

Draft.A - March 30, 2001 87 Preview - Confidential T89C51AC2 16. Analog-to-Digital Converter (ADC) 16.1. Introduction This section describes the on-chip 10 bit analog-to-digital converter of the T89C51AC2. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10 bit- cascaded potentiometric ADC. Two kind of conversion are available: - Standard conversion (8 bits). - Precision conversion (10 bits). For the precision conversion, set bit PSIDLE in ADCON register and start conversion. The chip is in a pseudo- idle mode, the CPU doesn’t run but the peripherals are always running. This mode allows digital noise to be as low as possible, to ensure high precision conversion. For this mode it is necessary to work with end of conversion interrupt, which is the only way to wake up the chip. If another interrupt occurs during the precision conversion, it will be treated only after this conversion is ended. 16.2. Features

• 8 channels with multiplexed inputs
• 10-bit cascaded potentiometric ADC
• Conversion time 20 micro-seconds
• Zero Error (offset) +/- 2 LSB max
• Positive Reference Voltage Range 2.4 to 3.0Volt
• ADCIN Range 0 to 3Volt
• Integral non-linearity typical 1 LSB, max. 2 LSB
• Differential non-linearity typical 0.5 LSB, max. 1 LSB
• Conversion Complete Flag or Conversion Complete Interrupt
• Selected ADC Clock 16.3. ADC Port1 I/O Functions Port 1 pins are general I/O that are shared with the ADC channels. The channel select bit in ADCF register define which ADC channel/port1 pin will be used as ADCIN. The remaining ADC channels/port1 pins can be used as general purpose I/O or as the alternate function that is available. Writes to the port register which aren’t selected by the ADCF will not have any effect.

A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). the A/D conversion, it is cleared by hardware. This flag can be read only, a write has no effect. (see Figure 80). Clear this flag for re-arming the interrupt. The bits SCH0 to SCH2 in ADCON register are used for the analog input channel selection. Before Starting Power reduction modes the ADC conversion has to be completed. Table 21. Selected Analog input linear conversion. All other voltages will result in 3FFh if greater than VAREF and 000h if less than VAGND.

clock from the oscillator frequency. Figure 79. A/D Converter clock When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN in ADCON register. In this mode the power dissipation is about 1uW.

the interrupt the bit ADEOC must be cleared by software. Figure 80. ADC interrupt structure

Figure 81. ADCF Register Figure 82. ADCON Register Set to use P1.x as ADC input. Clear tu use P1.x as standart I/O port.

6 PSIDLE

Clear to converte without idle mode.

5 ADEN

Clear for Standby mode (power dissipation 1 uW).

4 ADEOC

Set by hardware when ADC result is ready to be read. This flag can generate an interrupt. Must be cleared by software.

3 ADSST

Set to start an A/D conversion.

interrupts (timers 0, 1 and 2), a serial port interrupt, a PCA and an ADC. These interrupts are shown below. Figure 86. Interrupt Control System

Table 22. Priority Level Bit Values high-priority interrupt cannot be interrupted by any other interrupt source. determined by the polling sequence, see Table 23. Table 23. Interrupt priority Within level

Figure 87. IEN0 Register Clear to disable all interrupts. Set to enable all interrupts. Clear to disable the PCA interrupt. Set to enable the PCA interrupt.

5 ET2

Clear to disable timer 2 overflow interrupt. Set to enable timer 2 overflow interrupt. Clear to disable serial port interrupt. Set to enable serial port interrupt.

3 ET1

Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt.

2 EX1

Clear to disable external interrupt 1. Set to enable external interrupt 1.

1 ET0

Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt.

0 EX0

Clear to disable external interrupt 0. Set to enable external interrupt 0.

Figure 88. IEN1 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.

1 EADC

Clear to disable the ADC interrupt. Set to enable the ADC interrupt. The value read from this bit is indeterminate. Do not set this bit.

Figure 89. IPL0 Register The value read from this bit is indeterminate. Do not set this bit.

6 PPC EWC Counter Interrupt Priority bit

5 PT2 Timer 2 overflow interrupt Priority bit

Refer to PT2H for priority level. Refer to PSH for priority level.

3 PT1 Timer 1 overflow interrupt Priority bit

Refer to PT1H for priority level.

2 PX1 External interrupt 1 Priority bit

Refer to PX1H for priority level.

1 PT0 Timer 0 overflow interrupt Priority bit

Refer to PT0H for priority level.

0 PX0 External interrupt 0 Priority bit

Refer to PX0H for priority level.

Figure 90. IPL1 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. 1 PADCL ADC Interrupt Priority level less significant bit. Refer to PSPIH for priority level. The value read from this bit is indeterminate. Do not set this bit.

Figure 91. IPL0 Register The value read from this bit is indeterminate. Do not set this bit.

6 PPCH

5 PT2H

4 PSH

3 PT1H

2 PX1H

1 PT0H

0 PX0H

Figure 92. IPH1 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.

1 PADCH

The value read from this bit is indeterminate. Do not set this bit.

102 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 18. Electrical Characteristics 18.1. Absolute Maximum Ratings(1) Ambiant Temperature Under Bias: I = industrial -40°Ct o8 5°C Storage Temperature -65°Ct o+1 5 0°C Voltage on VCC to VSS- 0 . 5Vt o+6 V Voltage on Any Pin to VSS- 0 . 5Vt oVCC + 0.2 V Power Dissipation 1 W(2) NOTES 1. S tresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. 2. This value is based on the maximum allowable die temperature and the thermal resistance of the package.

Table 24. DC Parameters in Standard Voltage

1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH , TCHCL = 5 ns (see Figure 96.), VIL = VSS + 0.5 V ,
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH ,TCHCL = 5 ns, VIL =V SS + 0.5 V , VIH =V CC - 0.5 V; XTAL2

N.C; Port 0 = VCC ;EA = RST = VSS (see Figure 94.).

1. Power Down I CC is measured with all output pins disconnected;E A=V SS,P O R T0=VCC ; XTAL2 NC.; RST = VSS (see Figure 95.). In addition,

the WDT must be inactive and the POF flag must be set.

106 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 18.4. AC Parameters 18.4.1. Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example:T AVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. TA = -40°Ct o+ 8 5°C; VSS =0V ;V CC =5V ±1 0 %;F=0t o4 0 MHz. TA = -40°Ct o+ 8 5°C; VSS =0V ; V CC =5V ± 10%. (Load Capacitance for port 0, ALE and PSEN = 60 pF; Load Capacitance for all other outputs = 60 pF.) Table 26, Table 29 and Table 32 give the description of each AC symbols. Table 27, Table 30 and Table 33 give for each range the AC parameter. Table 28, Table 31 and Table 34 give the frequency derating formula of the AC parameter for each speed range description. To calculate each AC symbols. take the x value and use this value in the formula. Example: T LLIV and 20 MHz, Standard clock. x=3 0n s T=5 0n s T CCIV =4 T-x=1 7 0n s

Table 26. Symbol Description Table 27. AC Parameters for a Fix Clock (F= 40 MHz)

Table 28. AC Parameters for a Variable Clock

12 TCLCL

Table 29. Symbol Description

Table 30. AC Parameters for a Fix Clock (F= 40 MHz)

Table 31. AC Parameters for a Variable Clock

Table 32. Symbol Description (F= 40 MHz) Table 33. AC Parameters for a Fix Clock (F= 40 MHz)

Table 35. AC Parameters Table 34. AC Parameters for a Variable Clock

114 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 18.4.10. External Clock Drive Waveforms 18.4.11. AC Testing Input/Output Waveforms AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”. 18.4.12. Float Waveforms For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V OH /VOL level occurs. IOL /IOH ≥± 20mA. 18.4.13. Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2. V CC -0.5V 0.45V 0.7VCC 0.2VCC -0.1 TCHCL TCLCX TCLCL TCLCH TCHCX INPUT/OUTPUT 0.2 VCC + 0.9 0.2 VCC - 0.1 V CC -0.5 V 0.45 V FLOAT V OH - 0.1 V V OL + 0.1 V V LOAD V LOAD + 0.1 V V LOAD - 0.1 V

Draft.A - March 30, 2001 115 Preview - Confidential T89C51AC2 This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (T A =25°C fully loaded) RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. DATA PCL OUT DATA PCL OUT DATA PCL OUT SAMPLED SAMPLED SAMPLED STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 FLOAT FLOAT FLOAT THESE SIGNALS ARE NOT ACTIV ATED DURING THE EXECUTION OF A MOVX INSTRUCTION INDICATES ADDRESS TRANSITIONS EXTERN AL PR OGRAM MEMOR Y FETCH FLOAT DATA SAMPLED DPL OR Rt OUT INDICATES DPH OR P2 SFR TO PCH TRANSITION PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL) PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) OLD DATA NEW DATA P0 PINS SAMPLED P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED P0 PINS SAMPLED RXD SAMPLED INTERNAL CLOCK XTAL2 ALE PSEN P2 (EXT) READ CYCLE WRITE CYCLE RD WR POR T OPERA TION MOV PORT SRC MOV DEST P0 MOV DEST PORT (P1. P2. P3) (INCLUDES INTO. INT1. TO T1) SERIAL POR T SHIFT CLOCK TXD (MODE 0) DATA OUT DPL OR Rt OUT INDICATES DPH OR P2 SFR TO PCH TRANSITION RXD SAMPLED

116 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 19. Ordering Information Packages: RL: TQFP44 SL: PLCC44 T -M: VCC: 5V

40 MHz, X1 mode

20 MHz, X2 mode

S Temperature Range C:Commercial 0 to 70oC I:Industrial -40 to 85oC E:Enginering Sample -RL Conditioning S: Stick T: Tray M89C51AC2 C 89C51AC2 ( 32 Kbytes Flash )

Table 36. Possible order entries