T89C51AC2-RLTIM

AT89C51AC2_06 ATMEL | Alldatasheet

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Technical content

Features

 80C51 Core Architecture  256 Bytes of On-chip RAM  1 KB of On-chip XRAM  32 KB of On-chip Flash Memory – Data Retention: 10 Years at 85°C Read/Write Cycle: 10K  2 KB of On-chip Flash for Bootloader  2 KB of On-chip EEPROM Read/Write Cycle: 100K  14-sources 4-level Interrupts  Three 16-bit Timers/Counters  Full Duplex UART Compatible 80C51  Maximum Crystal Frequency 40 MHz, in X2 Mode, 20 MHz (CPU Core, 20 MHz)  Five Ports: 32 + 2 Digital I/O Lines  Five-channel 16-bit PCA with: – PWM (8-bit) – High-speed Output – Timer and Edge Capture  Double Data Pointer  21-bit Watchdog Timer (7 Programmable Bits)  10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs  On-chip Emulation Logic (Enhanced Hook System)  Power Saving Modes: – Idle Mode – Power-down Mode  Power Supply: 3V to 5.5V  Temperature Range: Industrial (-40 ° to +85°C)  Packages: VQFP44, PLCC44

Description

The A/T89C51AC2 is a high performance Flash version of the 80C51 single chip 8-bit microcontrollers. It contains a 32 KB Flash memory block for program and data. The 32 KB Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin. The A/T89C51AC2 retains all features of the 80C51 with 256 bytes of internal RAM, a 7-source 4-level interrupt controller and three timer/counters. In addition, the A/T89C51AC2 has a 10-bit A/D converter, a 2 KB Boot Flash memory, 2 KB EEPROM for data, a Programmable Counter Array, an XRAM of 1024 bytes, a Hardware Watch- Dog Timer, and a more versatile serial channel that facilitates multiprocessor communication (EUART). The fully static design of the A/T89C51AC2 reduces system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The A/T89C51AC2 has two software-selectable modes of reduced activity and an 8- bit clock prescaler for further reduction in power consumption. In the idle mode the CPU is frozen while the peripherals and the interrupt system are still operating. In the Power-down mode the RAM is saved and all other functions are inoperative. The added features of the A/T89C51AC2 make it more powerful for applications that need A/D conversion, pulse width modulation, high speed I/O and counting capabili- ties such as industrial control, consumer goods, alarms, motor control, among others. While remaining fully compatible with the 80C52, the T8C51AC2 offers a superset of this standard microcontroller. In X2 mode, a maximum external clock rate of 20 MHz reaches a 300 ns cycle time. Enhanced 8-bit Microcontroller with 32 KB Flash Memory AT89C51AC2 T89C51AC2

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4127G–8051–05/06 Block Diagram Notes: 1. 8 analog Inputs/8 Digital I/O 2. 2-Bit I/O Port Timer 0 INT RAM 256x8 RxD TxD WR RD EA PSEN ALE XTAL2 XTAL1 UART CPU Timer 1 INT1 CtrlINT0 C51 CORE Port 0 Port 1 Port 2 Port 3 Parallel I/O Ports and Ext. Bus P1(1) XRAM 1kx8 IB-bus PCA RESET Watch Dog PCA ECI Vss Vcc Timer 2 T2EX Port 4 P4(2) 10 bit ADC Flash 32kx Boot loader 2kx8 EE PROM 2kx8 VAREF VAVCC VAGND

4127G–8051–05/06 Pin Configuration PLCC44 P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 P3.7/RD P4.0 P4.1 P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P3.6/WR ALE PSEN P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.1/AD1 P0.0/AD0 P2.0/A8 P1.4/AN4/CEX1 P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4 EA P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 43 42 41 40 3944 38 37 36 35 34 12 13 17 161514 20 1918 21 22 VQFP44 P1.4/AN4/CEX1 P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4 EA P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 ALE PSEN P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.2 /AD2 P0.3 /AD3 P0.4 /AD4 P0.1 /AD1 P0.0 /AD0 P2.0/A8 P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 P3.7/RD P4.0 P4.1 P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P3.6/WR

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Table 1. Pin Description and Data Memory. In this application it uses strong internal pull-ups when emitting 1’s. Port 0 also outputs the code Bytes during program validation. External pull-ups are required during program verification. inputs via the ADCCF register (in this case the internal pull-ups are disconnected). External clock input for Timer/counter2. Trigger input for Timer/counter2. PCA module 0 Entry of input/PWM output. PCA module 1 Entry of input/PWM output. PCA module 2 Entry of input/PWM output. PCA module 3 Entry of input/PWM output. PCA module 4 Entry ot input/PWM output. Port 1 receives the low-order address byte during EPROM programming and program verification. It can drive CMOS inputs without external pull-ups. Memory that use 8 bit addresses (MOVX @Ri), Port 2 transmits the contents of the P2 special function register. It also receives high-order addresses and control signals during program validation. It can drive CMOS inputs without external pull-ups.

source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups. External Data Memory read strobe; Enables the external data memory. It can drive CMOS inputs without external pull-ups. current (IIL, on the datasheet) because of the internal pull-up transistor. It can drive CMOS inputs without external pull-ups. resistor to VSS permits power-on reset using only an external capacitor to VCC. = 1), ALE generation can be disabled by the software. memory. The PSEN is not activated for internal fetches. Input of the inverting oscillator amplifier and input of the internal clock generator circuits. above a frequency of 16 MHz, a duty cycle of 50% should be maintained. Output from the inverting oscillator amplifier. Table 1. Pin Description (Continued)

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independently programmed as input or output. I/O or for its alternate input output function. ister (x = 1,3 or 4). To use a pin for general-purpose input, set the bit in the Px register. This turns off the output FET drive. Figure 1. Port 1, Port 3 and Port 4 Structure Note: The internal pull-up can be disabled on P1 when analog function is selected. shows the structure of Port 2. An external source can pull a Port 2 pin low. turn off the output driver FET.

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It is not obvious the last three instructions in this list are Read-Modify-Write instructions. than the pins returns the correct logic-one value. to input conditions by a logical one written to the latch. vention. Current strengths are 1/10 that of pFET #3. Table 2. Read-Modify-Write Instructions

Figure 4. Internal Pull-Up Configurations Note: Port 2 p1 assists the logic-one output for memory bus cycles.

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Table 3. C51 Core SFRs Table 4. I/O Port SFRs Table 5. Timers SFRs

1 Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

Table 5. Timers SFRs (Continued) Table 6. Serial I/O Port SFRs Table 7. PCA SFRs

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Table 7. PCA SFRs (Continued) Table 8. Interrupt SFRs Table 9. ADC SFRs Table 10. Other SFRs

Note: 1. These registers are bit –addressable. whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF . Table 11. SFR Mapping

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4127G–8051–05/06 Clock The A/T89C51AC2 core needs only 6 clock periods per machine cycle. This feature, called ”X2”, provides the following advantages:  Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power.  Saves power consumption while keeping the same CPU power (oscillator power saving).  Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes.  Increases CPU power by 2 while keeping the same crystal frequency. In order to keep the original C51 compatibility, a divider-by-2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by the software. An extra feature is available to start after Reset in the X2 mode. This feature can be enabled by a bit X2B in the Hardware Security Byte. This bit is described in the section "In-System-Programming". Description The X2 bit in the CKCON register (see Table 12) allows switching from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode) for the CPU Clock only (see Figure 5.). The Timers 0, 1 and 2, Uart, PCA, or Watchdog switch in X2 mode only if the corre- sponding bit is cleared in the CKCON register. The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1 input. In X2 mode, as this divider is by passed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 5. shows the clock generation block diagram. The X2 bit is validated on the XTAL1÷2 rising edge to avoid glitches when switching from the X2 to the STD mode. Figure 6 shows the mode switching waveforms.

Figure 5. Clock CPU Generation Diagram

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Figure 6. Mode Switching Waveforms

4127G–8051–05/06 Register Table 12. CKCON Register CKCON (S:8Fh) Clock Control Register Note: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit has no effect. Reset Value = x000 0000b 76543210 - WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 Bit Number Bit Mnemonic Description -- Reserved Do not set this bit. 6W D X 2 Watchdog clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

5 PCAX2

Programmable Counter Array clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 4S I X 2 Enhanced UART clock (MODE 0 and 2) (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 3T 2 X 2 Timer 2 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 2T 1 X 2 Timer 1 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 1T 0 X 2 Timer 0 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 0X 2 CPU clock Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6 clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2"bits.

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cally divided by 2 using the X2 Mode detailed in Section “Clock”. internal reset source such as a watchdog, PCA, timer, etc.  The level on xtal1 input must be outside the specification (VIH, VIL).  Oscillator startup time (oscrst). To determine the capacitor the highest value of these two parameters has to be chosen. The reset circuitry is shown in Figure 7. Figure 7. Reset Circuitry two values of oscillato r start-up time and two pull-down resistor values. Table 13. Minimum Reset Capacitor for a 15k Pull-down Resistor discharged, leading to a bad reset sequence.

periods is mode independent (X2 or X1). tor must be added as shown Figure 8. Figure 8. Reset Circuitry for WDT reset out usage this bit allows mapping of the bootloader in the code area, a reset failure can be critical. (write or erase) may corrupt the Flash on-chip memory. supply failure, power supply switched off). status of the Port pins during Idle mode is detailed in Table 14. instruction that sets IDL bit is the last instruction executed. Note: If IDL bit and PD bit are set simultaneously, the T89C51CC02 enters Power-down mode. Then it does not go in Idle mode when exiting Power-down mode.

1. Generate an enabled interrupt.

instruction immediately following the instruction that activated Idle mode.

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4127G–8051–05/06 The general-purpose flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt occurred during normal operation or during Idle mode. When Idle mode is exited by an interrupt, the interrupt service routine may examine GF1 and GF0. 2. Generate a reset. – A logic high on the RST pin clears IDL bit in PCON register directly and asynchronously. This restores the clock to the CPU. Program execution momentarily resumes with the instruction immediately following the instruction that activated the Idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the T89C51CC02 and vectors the CPU to address C:0000h. Notes: 1. During the time that execution resumes, the internal RAM cannot be accessed; how- ever, it is possible for the Port pins to be accessed. T o avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated Idle mode should not write to a Port pin or to the external RAM. 2. If Idle mode is invoked by ADC Idle, the ADC conversion completion w ill exit Idle. Power-down Mode The Power-down mode places the T89C51CC02 in a very low power state. Power-down mode stops the oscillator and freezes all clocks at known states. The CPU status prior to entering Power-down mode is preserved, i.e., the program counter, program status word register retain their data for the duration of Power-down mode. In addition, the SFRs and RAM contents are preserved. The status of the Port pins during Power-down mode is detailed in Table 14. Entering Power-down Mode To enter Power-down mode, set PD bit in PCON register. The T89C51CC02 enters the Power-down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. Exiting Power-down Mode If VDD was reduced during the Power-down mode, do not exit Power-down mode until VDD is restored to the normal operating level. There are two ways to exit the Power-down mode: 1. Generate an enabled external interrupt. – The T89C51CC02 provides capability to exit from Power-down using INT0#, INT1#. Hardware clears PD bit in PCON register which starts the oscillator and restores the clocks to the CPU and peripherals. Using INTx# input, execution resumes when the input is released (see Figure 9) while using KINx input, execution resumes after counting 1024 clock ensuring the oscillator is restarted properly (see Figure 8). Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Power-down mode. Note: 1. The external interrupt used to exit Power-down mode must be configured as level sensitive (INT0# and INT1#) and must be assigned the highest priority. In addition, the duration of the interrupt must be long enough to allow the oscillator to stabilize. The execution will only resume when the interrupt is deasserted. 2. Exit from power-down by external interrupt does not affect the SFRs nor the internal RAM content.

Figure 9. Power-down Exit Waveform Using INT1:0# Power-down mode should not write to a Port pin or to the external RAM.

1. Exit from power-down by reset redefines all the SFRs, but does not affect the internal

Table 14. Pin Conditions in Special Operating Modes

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4127G–8051–05/06 Registers Table 15. PCON Register PCON (S:87h) – Power configuration Register Reset Value = 00X1 0000b 76543210 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Number Bit Mnemonic Description 7S M O D 1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3 6S M O D 0 Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4P O F Power-Off Flag Clear to recognize next reset type. Set by hardware when V cc rises from 0 to its nominal voltage. Can also be set by software. 3G F 1 General-purpose flag 1 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode. 2G F 0 General-purpose flag 0 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode. 1P D Power-down Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Power-down mode. If IDL and PD are both set, PD takes precedence. 0I D L Idle Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence.

1. The internal space mapped in three separate segments:

 the lower 128 Bytes RAM segment.  the upper 128 Bytes RAM segment.  the expanded 1024 Bytes RAM segment (XRAM). SFRs, (addresses 80h to FFh) accessible by direct addressing mode. Figure 11 shows the internal and external data memory spaces organization. Figure 10. Internal Memory - RAM Figure 11. Internal and External Data Memory Organization XRAM-XRAM

128 Bytes

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ing, and can be used for context switching in interrupt service routines. Table 16. Register Bank Selection addresses in this area are 00h to 7Fh. Figure 12. Lower 128 Bytes Internal RAM Organization EXTRAM = 1, the XRAM is selected. must then be initialized properly.

4 Banks of

8 Registers

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Figure 14. External Data Read Waveforms Notes: 1. RD signal may be stretched using M0 bit in AUXR register.

1. When executing MOVX @Ri instruction, P2 outputs SFR content.

Figure 15. External Data Write Waveforms Notes: 1. WR signal may be stretched using M0 bit in AUXR register.

1. When executing MOVX @Ri instruction, P2 outputs SFR content.

and reducing code size in case of intensive usage of external memory accesses. Figure 16. Dual Data Pointer Implementation using one data pointer as a “source” pointer and the other one as a “destination” pointer. enhanced algorithm libraries.

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Table 19. AUXR Register Carry out from bit 1 of ALU operands. Carry out from bit 1 of addition operands. Refer to Table 16 for bits description. Overflow set by arithmetic operations. Set when ACC contains an odd number of 1’s. Cleared when ACC contains an even number of 1’s. The value read from these bits are indeterminate. Do not set this bit. the RD/ and the WR/ pulse length is increased according to the value of M0. The value read from this bit is indeterminate. Do not set this bit.

Table 20. AUXR1 Register

1 EXTRAM

0 - Internal XRAM access using MOVX @ Ri/@ DPTR. 1 - External data memory access. 1 - ALE is active only during a MOVX or MOVC instruction. The value read from these bits is indeterminate. Do not set these bits.

5 ENBOOT (1)

Clear this bit for disable boot Flash. The value read from this bit is indeterminate. Do not set this bit. 1- Reserved for Data Pointer Extension. Set to select second dual data pointer: DPTR1. Clear to select first dual data pointer: DPTR0.

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4127G–8051–05/06 EEPROM Data Memory The 2 KB on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/XRAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction. A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming). The number of data written on the page may vary from 1 up to 128 Bytes (the page size). When programming, only the data written in the column latch is programmed and a ninth bit is used to obtain this feature. This provides the capability to program the whole memory by Bytes, by page or by a number of Bytes in a page. Indeed, each ninth bit is set when the writing the corresponding byte in a row and all these ninth bits are reset after the writing of the complete EEPROM row. Write Data in the Column Latches Data is written by byte to the column latches as for an external RAM memory. Out of the 11 address bits of the data pointer, the 4 MSBs are used for page selection (row) and 7 are used for byte selection. Between two EEPROM programming sessions, all the addresses in the column latches must stay on the same page, meaning that the 4 MSB must no be changed. The following procedure is used to write to the column latches:  Save and disable interrupt.  Set bit EEE of EECON register  Load DPTR with the address to write  Store A register with the data to be written  Execute a MOVX @DPTR, A  If needed loop the three last instructions until the end of a 128 Bytes page  Restore interrupt. Note: The last page address used when loading the column latch is the one used to select the page programming address. Programming The EEPROM programming consists of the following actions:  writing one or more Bytes of one page in the column latches. Normally, all Bytes must belong to the same page; if not, the last page address will be latched and the others discarded.  launching programming by writing the control sequence (50h followed by A0h) to the EECON register.  EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that the EEPROM segment is not available for reading.  The end of programming is indicated by a hardware clear of the EEBUSY flag. Note: The sequence 5xh and Axh must be executed without instructions between then other- wise the programming is aborted. Read Data The following procedure is used to read the data stored in the EEPROM memory:  Save and disable interrupt  Set bit EEE of EECON register  Load DPTR with the address to read  Execute a MOVX A, @DPTR  Restore interrupt

4127G–8051–05/06 ;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read. ;* Acc contain the reading value ;* NOTE: before execute this function, be sure the EEPROM is not BUSY api_rd_eeprom_byte: ; Save and clear EA MOV EECON, #02h; map EEPROM in XRAM space MOVX A, @DPTR MOV EECON, #00h; unmap EEPROM ; Restore EA ret ;* NAME: api_ld_eeprom_cl ;* DPTR contain address to load ;* Acc contain value to load ;* NOTE: in this example we load only 1 byte, but it is possible upto ;* 128 Bytes. ;* before execute this function, be sure the EEPROM is not BUSY api_ld_eeprom_cl: ; Save and clear EA MOV EECON, #02h ; map EEPROM in XRAM space MOVX @DPTR, A MOVEECON, #00h; unmap EEPROM ; Restore EA ret ;* NAME: api_wr_eeprom ;* NOTE: before execute this function, be sure the EEPROM is not BUSY api_wr_eeprom: ; Save and clear EA MOV EECON, #050h MOV EECON, #0A0h ; Restore EA ret

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4127G–8051–05/06 Registers Table 21. EECON Register EECON (S:0D2h) EEPROM Control Register Reset Value = XXXX XX00b Not bit addressable 76543210 EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY Bit Number Bit Mnemonic Description 7-4 EEPL3-0 Programming Launch command bits Write 5Xh followed by AXh to EEPL to launch the programming. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2- Reserved The value read from this bit is indeterminate. Do not set this bit.

1 EEE

Set to map the EEPROM space during MOVX instructions (Write in the column latches) Clear to map the XRAM space during MOVX.

0 EEBUSY

Set by hardware when programming is in progress. Cleared by hardware when programming is done. Can not be set or cleared by software.

available using specific programming tool. Figure 17. Program/Code Memory Organization stant from this location does not affect Ports 0 and 2.

1. Default factory programmed parts come with maximum hardware protection. Execu-

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the bus control signals (PSEN#, and ALE). describes the external memory interface signals. Figure 18. External Code Memory Interface Structure Figure 19) in the external program/code memory. mation on X2 mode see section “Clock “. form and do not provide precise timing information. For bus cycling parameters refer to the ‘AC-DC parameters’ section. Table 22. External Code Memory Interface Signals

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4127G–8051–05/06 FM0 Memory Architecture The Flash memory is made up of 4 blocks (see Figure 20):  The memory array (user space) 32 KB  The Extra Row  The Hardware security bits  The column latch registers User Space This space is composed of a 32 KB Flash memory organized in 256 pages of 128 Bytes. It contains the user’s application code. Extra Row (XRow) This row is a part of FM0 and has a size of 128 Bytes. The extra row may contain infor- mation for boot loader usage. Hardware Security Byte The Hardware security Byte space is a part of FM0 and has a size of 1 byte. The 4 MSB can be read/written by software, the 4 LSB can only be read by software and written by hardware in parallel mode. Column Latches The column latches, also part of FM0, have a size of full page (128 Bytes). The column latches are the entrance buffers of the three previous memory locations (user array, XROW and Hardware security byte). Cross Flash Memory Access The FM0 memory can be program only from FM1. Programming FM0 from FM0 or from external memory is impossible. The FM1 memory can be program only by parallel programming. The Table 23 show all software Flash access allowed. Table 23. Cross Flash Memory Access

page while bits 14 to 7 are used to select the programming address of the page. Setting FPS bit takes precedence on the EXTRAM bit in AUXR register. dance with Table 24. A MOVC instruction is then used for reading these spaces. Table 24. FM0 Blocks Select Bits spaces to program according to FMOD1:0 bits.

11 R e s e r v e d

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Table 25. Programming Spaces otherwise the programming is aborted.

1. Interrupts that may occur during programming time must be disabled to avoid any

spurious exit of the programming mode. Status of the Flash Memory The bit FBUSY in FCON register is used to indicate the status of programming. FBUSY is set when programming is in progress. Selecting FM1 The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh.  Save then disable interrupt and map the column latch space by setting FPS bit.  Load the DPTR with the address to load.  Load Accumulator register with the data to load.  Execute the MOVX @DPTR, A instruction.  If needed loop the three last instructions until the page is completely loaded.

5 X 0 0 No action

5 X 0 1 No action

5 X 1 0 No action

5 X 1 1 No action

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Figure 22. Flash and Extra Row Programming Procedure  Save and disable the interrupts.  Load DPTR at address 0000h.  Load Accumulator register with the data to load.  Execute the MOVX @DPTR, A instruction. the programming indicated by the FBUSY flag cleared. The end of the programming indicated by the FBusy flag cleared.

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Figure 24. Reading Procedure Note: 1. aa = 10 for the Hardware Security Byte. chip code and data located in FM0 and FM1. Table 26. Program Lock bit Preventing Flash Corruption See the “Power Management” section. external program memory returns non coded data. on reset, and further parallel programming of the Flash is disabled.

4 UUP Same as 3, also external execution is disabled if code roll over beyond

4127G–8051–05/06 Registers FCON RegisterFCON (S:D1h) Flash Control Register Reset Value = 0000 0000b 76543210 FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY Bit Number Bit Mnemonic Description 7-4 FPL3:0 Programming Launch Command Bits Write 5Xh followed by AXh to launch the programming according to FMOD1:0 (see Table 25) 3F P S Flash Map Program Space Set to map the column latch space in the data memory space. Clear to re-map the data memory space. 2-1 FMOD1:0 Flash Mode See Table 24 or Table 25.

0 FBUSY

Set by hardware when programming is in progress. Clear by hardware when programming is done. Can not be changed by software.

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Table 27. Cross Memory Access

Table 29. Read MOVX A, @DPTR Table 30. Write MOVX @DPTR,A

00 X X O K

10 X X O K

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Table 31. Read MOVC A, @DPTR

1. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to
2. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to

Note: 1. The user can also program his own bootloader in FM1. This allow the customer to have a full use of the 32 KB user memory.  A further method exists in activating the Atmel boot loader by hardware activation. See Section “Hardware Security Byte”.  The FM0 can be programmed also by the parallel mode using a programmer. Figure 25. Flash Memory Mapping

2 KB IAP

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4127G–8051–05/06 Boot Process Software Boot Process Example Many algorithms can be used for the software boot process. Below are descriptions of the different flags and Bytes. Boot Loader Jump Bit (BLJB): - This bit indicates if on RESET the user wants to jump to this application at address @0000h on FM0 or execute the boot loader at address @F800h on FM1. - BLJB = 0 (i.e. bootloader FM1 executed after a reset) is the default Atmel factory pro- gramming. - To read or modify this bit, the APIs are used. Boot Vector Address (SBV): - This byte contains the MSB of the user boot loader address in FM0. - The default value of SBV is FCh (no user boot loader in FM0). - To read or modify this byte, the APIs are used. Extra Byte (EB) and Boot Status Byte (BSB): - These Bytes are reserved for customer use. - To read or modify these Bytes, the APIs are used. Hardware Boot Process At the falling edge of RESET, the bit ENBOOT in AUXR1 register is initialized with the value of Boot Loader Jump Bit (BLJB). Further at the falling edge of RESET if the following conditions (called Hardware condi- tion) are detected. The FCON register is initialized with the value 00h and the PC is initialized with F800h (FM1 lower byte = Bootloader entry point). Harware Conditions:  PSEN low (1)  EA high,  ALE high (or not connected). The Hardware condition forces the bootloader to be executed, whatever BLJB value is. Then BLBJ will be checked. If no hardware condition is detected, the FCON register is initialized with the value F0h. Then BLJB value will be checked. Conditions are:  If bit BLJB = 1: User application in FM0 will be st arted at @0000h (standard reset).  If bit BLJB = 0: Boot loader will be started at @F800h in FM1. Note: 1. As PSEN is an output port in normal operating mode (running user applications or bootloader applications) after reset it is recommended to release PSEN after the fall- ing edge of Reset is signaled. The hardware conditions are sampled at reset signal Falling Edge, thus they can be released at any time when reset input is low. 2. To ensure correct microcontroller startup, the PSEN pin should not be tied to ground during power-on.

Figure 26. Hardware Boot Process Algorithm is initialized with BLJB inverted.

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4127G–8051–05/06 Hardware Security Byte Table 33. Hardware Security Byte After erasing the chip in parallel mode, the default value is : FFh The erasing in ISP mode (from bootloader) does not modify this byte. Notes: 1. Only the 4 MSB bits can be accessed by software. 2. The 4 LSB bits can only be accessed by parallel mode. 76543210 X2B BLJB - - - LB2 LB1 LB0 Bit Number Bit Mnemonic Description 7X 2 B X2 Bit Set this bit to start in standard mode. Clear this bit to start in X2 mode. 6B L J B Boot Loader JumpBit - 1: To start the user’s application on next RESET (@0000h) located in FM0, - 0: To start the boot loader(@F800h) located in FM1. 5-3 - Reserved The value read from these bits are indeterminate. 2-0 LB2:0 Lock Bits

52 A/T89C51AC2

Figure 29. UART Timing in Mode 1 Figure 30. UART Timing in Modes 2 and 3 nication feature is enabled (SM2 bit in SCON register is set). the CPU is not interrupted by command frames addressed to other devices. be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).

4127G–8051–05/06 Given Address Each device has an individual address that is specified in the SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example: SADDR0101 0110b SADEN1111 1100b Given0101 01XXb Here is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0011b SADEN1111 1101b Given1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To com- municate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b). Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.: SADDR 0101 0110b SADEN 1111 1100b SADDR OR SADEN1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 1X11b, Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 1X11B, Slave C:SADDR=1111 0010b SADEN1111 1101b Given1111 1111b

54 A/T89C51AC2

and B, but not slave C, the master can send and address FBh. Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. Refer to SM1 for serial port mode selection. Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3. Clear to disable serial reception. Set to enable serial reception. Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. Clear to acknowledge interrupt. stop bit in the other modes. Clear to acknowledge interrupt. Figure 30. in the other modes.

Table 35. SADEN Register Table 36. SADDR Register Table 37. SBUF Register

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Table 38. PCON Register Set to select double baud rate in mode 1, 2 or 3. Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. The value read from this bit is indeterminate. Do not set this bit. Clear to recognize next reset type. Cleared by user for general-purpose usage. Set by user for general-purpose usage. Cleared by user for general-purpose usage. Set by user for general-purpose usage. Cleared by hardware when reset occurs. Set to enter power-down mode. Clear by hardware when interrupt or reset occurs.

4127G–8051–05/06 Timers/Counters The A/T89C51AC2 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. The various operating modes of each Timer/Counter are described in the following sections. Timer/Counter Operations A basic operation is Timer registers THx and TLx (x = 0, 1) connected in cascade to form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (see Figure 39) turns the Timer on by allowing the selected input to increment TLx. When TLx overflows it increments THx; when THx overflows it sets the Timer overflow flag (TFx) in TCON register. Setting the TRx does not clear the THx and TLx Timer registers. Timer regis- ters can be accessed to obtain the current count or to enter preset values. They can be read at any time but TRx bit must be cleared to preset their values, otherwise the behav- ior of the Timer/Counter is unpredictable. The C/Tx# control bit selects Timer operation or Counter operation by selecting the divided-down peripheral clock or external pin Tx as the source for the counted signal. TRx bit must be cleared when changing the mode of operation, otherwise the behavior of the Timer/Counter is unpredictable. For Timer operation (C/Tx# = 0), the Timer register counts the divided-down peripheral clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock periods). The Timer clock rate is F PER/6, i.e. F OSC/12 in standard mode or F OSC/6 in X2 mode. For Counter operation (C/Tx# = 1), the Time r register counts the negative transitions on the Tx external input pin. The external input is sampled every peripheral cycles. When the sample is high in one cycle and low in the next one, the Counter is incremented. Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition, the maximum count rate is F PER/12, i.e. F OSC/24 in standard mode or F OSC/12 in X2 mode. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle. Timer 0 Timer 0 functions as either a Timer or event Counter in four modes of operation. Figure 31 to Figure 34 show the logical configuration of each mode. Timer 0 is controlled by the four lower bits of TMOD register (see Figure 40) and bits 0, 1, 4 and 5 of TCON register (see Figure 39). TMOD register selects the method of Timer gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10 and M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0). For normal Timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer operation. Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an inter- rupt request. It is important to stop Timer/Counter before changing mode.

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ignored. Prescaler overflow increments TH0 register. Figure 31. Timer/Counter x (x = 0 or 1) in Mode 0 cascade (see Figure 32). The selected input increments TL0 register. Figure 32. Timer/Counter x (x = 0 or 1) in Mode 1

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4127G–8051–05/06 Timer 1 Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. The fol- lowing comments help to understand the differences:  Timer 1 functions as either a Timer or event Counter in three modes of operation. Figure 31 to Figure 33 show the logical configuration for modes 0, 1, and 2. Timer 1’s mode 3 is a hold-count mode.  Timer 1 is controlled by the four high-order bits of TMOD register (see Figure 40) and bits 2, 3, 6 and 7 of TCON register (see Figure 39). TMOD register selects the method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of operation (M11 and M01). TCON register provides Timer 1 control functions: overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type control bit (IT1).  Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best suited for this purpose.  For normal Timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control Timer operation.  Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an interrupt request.  When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it off and on.  It is important to stop Timer/Counter before changing mode. Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg- ister) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (see Figure 31). The upper 3 bits of TL1 regi ster are ignored. Prescaler overflow incre- ments TH1 register. Mode 1 (16-bit Timer) Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in cascade (see Figure 32). The selected input increments TL1 register. Mode 2 (8-bit Timer with Auto- Reload) Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from TH1 register on overflow (see Figure 33). TL1 overflow sets TF1 flag in TCON register and reloads TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged. Mode 3 (Halt) Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3. Interrupt Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is set every time an overflow occurs. Fl ags are cleared when vectoring to the Timer interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register.

Figure 35. Timer Interrupt System

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4127G–8051–05/06 Registers Table 39. TCON Register TCON (S:88h) Timer/Counter Control Register Reset Value = 0000 0000b 76543210 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Number Bit Mnemonic Description 7T F 1 Timer 1 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. 6T R 1 Timer 1 Run Control Bit Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1. 5T F 0 Timer 0 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 0 register overflows. 4T R 0 Timer 0 Run Control Bit Clear to turn off Timer/Counter 0. Set to turn on Timer/Counter 0. 3I E 1 Interrupt 1 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (see IT1). Set by hardware when external interrupt is detected on INT1# pin. 2I T 1 Interrupt 1 Type Control Bit Clear to select low level active (level triggered) for external interrupt 1 (INT1#). Set to select falling edge active (edge triggered) for external interrupt 1. 1I E 0 Interrupt 0 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (see IT0). Set by hardware when external interrupt is detected on INT0# pin. 0I T 0 Interrupt 0 Type Control Bit Clear to select low level active (level triggered) for external interrupt 0 (INT0#). Set to select falling edge active (edge triggered) for external interrupt 0.

Table 40. TMOD Register Notes: 1. Reloaded from TH1 at overflow.

1. Reloaded from TH0 at overflow.

Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. Clear for Timer operation: Timer 1 counts the divided-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1. 0 0 Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1). 0 1 Mode 1: 16-bit Timer/Counter. Clear to enable Timer 0 whenever TR0 bit is set. Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set. Clear for Timer operation: Timer 0 counts the divided-down system clock. Set for Counter operation: Timer 0 counts negative transitions on external pin T0. 0 0 Mode 0: 8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0). 0 1 Mode 1: 16-bit Timer/Counter. TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits.

0 M00

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Table 41. TH0 Register Table 42. TL0 Register Table 43. TH1 Register

Table 44. TL1 Register

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Timer 2 The A/T89C51AC2 timer 2 is compatible with timer 2 in the 80C52. timer clock. Setting TR2 allows TL2 to be incremented by the selected input. Figure 36. In this mode the T2EX pin controls the counting direction. in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. Figure 36. Auto-Reload Mode Up/Down Counter

61 Hz (F

 Set T2OE bit in T2MOD register.  Clear C/T2 bit in T2CON register. reload value or different depending on the application.  To start the timer, set TR2 run control bit in T2CON register. independent since both functions use the values in the RCAP2H and RCAP2L registers. Figure 37. Clock-Out Mode

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4127G–8051–05/06 Registers Table 45. T2CON Register T2CON (S:C8h) Timer 2 Control Register Reset Value = 0000 0000b Bit addressable 76543210 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Number Bit Mnemonic Description 7T F 2 Timer 2 Overflow Flag TF2 is not set if RCLK=1 or TCLK = 1. Must be cleared by software. Set by hardware on timer 2 overflow. 6E X F 2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. Set to cause the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Must be cleared by software. 5R C L K Receive Clock bit Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. 4T C L K Transmit Clock bit Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.

3 EXEN2

Timer 2 External Enable bit Clear to ignore events on T2EX pin for timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to clock the serial port. 2T R 2 Timer 2 Run Control bit Clear to turn off timer 2. Set to turn on timer 2. 1C / T 2 # Timer/Counter 2 Select bit Clear for timer operation (input from internal clock system: F OSC). Set for counter operation (input from T2 input pin). 0C P / R L 2 # Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1.

Table 46. T2MOD Register Table 47. TH2 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Clear to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output.

0 DCEN

Clear to disable timer 2 as up/down counter. Set to enable timer 2 as up/down counter.

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Table 48. TL2 Register Table 49. RCAP2H Register Table 50. RCAP2L Register 7-0 High Byte of Timer 2 Reload/Capture. 7-0 Low Byte of Timer 2 Reload/Capture.

ter. When exiting reset, the WDT is -by default- disable. Note: When the Watchdog is enable it is impossible to change its period. Figure 38. Watchdog Timer

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Table 51. Machine Cycle Count Table 52. Time-Out Computation

4127G–8051–05/06 Watchdog Timer During Power-down Mode and Idle In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are 2 methods of exiting Power-down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, the Watchdog is disabled. Exiting Power-down with an interrupt is sig- nificantly different. The interrupt shall be held low long enough for the oscillator to stabilize. When t he interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the inter- rupt service for the interrupt used to exit Power-down. To ensure that the WDT does not overflow within a few states of exiting powerdown, it is best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator cont inues to run. To prevent the WDT from resetting A/T89C51AC2 while in Idle mode, the user should always set up a timer that will period- ically exit Idle, service the WDT, and re-enter Idle mode. Register Table 53. WDTPRG Register WDTPRG (S:A7h) Watchdog Timer Duration Programming Register Reset Value = XXXX X000b 76543210 Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2S 2 Watchdog Timer Duration selection bit 2 Work in conjunction with bit 1 and bit 0. 1S 1 Watchdog Timer Duration selection bit 1 Work in conjunction with bit 2 and bit 0. 0S 0 Watchdog Timer Duration selection bit 0 Work in conjunction with bit 1 and bit 2.

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Table 54. WDTRST Register sequence without instruction between these two sequences.

4127G–8051–05/06 Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules. Its clock input can be programmed to count any of the following signals:  PCA clock frequency/6 (see “clock” section)  PCA clock frequency/2  Timer 0 overflow  External input on ECI (P1.2) Each compare/capture modules can be programmed in any one of the following modes:  rising and/or falling edge capture,  software timer,  high-speed output,  pulse width modulator. Module 4 can also be programmed as a Watchdog timer. see the "PCA Watchdog Timer" section. When the compare/capture modules are programmed in capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt vector. The PCA timer/counter and compare/capture modules share Port 1 for external I/Os. These pins are listed below. If the port is not used for the PCA, it can still be used for standard I/O. PCA Timer The PCA timer is a common time base for all five modules (see Figure 39). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (see Table 8) and can be programmed to run at:  1/6 the PCA clock frequency.  1/2 the PCA clock frequency.  the Timer 0 overflow.  the input on the ECI pin (P1.2). PCA Component External I/O Pin 16-bit Counter P1.2/ECI 16-bit Module 0 P1.3/CEX0 16-bit Module 1 P1.4/CEX1 16-bit Module 2 P1.5/CEX2 16-bit Module 3 P1.6/CEX3 16-bit Module 4 P1.7/CEX4

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Figure 39. PCA Timer/Counter The CMOD register includes three additional bits associated with the PCA.  The CIDL bit which allows the PCA to stop during idle mode.  The WDTE bit which enables or disables the Watchdog function on module 4. CCON register to be set when the PCA timer overflows.  The CR bit must be set to run the PCA. The PCA is shut off by clearing this bit. if the ECF bit in CMOD register is set. The CF bit can only be cleared by software.  8-bit Pulse Width Modulator. In addition module 4 can be used as a Watchdog Timer.

when a match or compare occurs in the associated module.  The PWM bit enables the pulse width modulation mode. CAPP bit enables the positive edge. If both bits are set both edges will be enabled.  The bit ECOM in CCAPM register when set enables the comparator function. Figure 40. PCA Interrupt System ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated.

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Figure 41. PCA Capture Mode SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set. Figure 42. PCA 16-bit Software Timer and High Speed Output Mode For software Timer mode, set ECOMn and MATn. For high speed output mode, set ECOMn, MATn and TOGn.

each time a match occurs between the PCA counter and the module’s capture registers. Figure 43. PCA High Speed Output Mode

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Figure 44. PCA PWM Mode not cause the RST pin to be driven high. cations the first solution is the best option.

4127G–8051–05/06 PCA Registers Table 55. CMOD Register CMOD (S:D9h) PCA Counter Mode Register Reset Value = 00XX X000b 76543210 CIDL WDTE - - - CPS1 CPS0 ECF Bit Number Bit Mnemonic Description 7C I D L PCA Counter Idle Control bit Clear to let the PCA run during Idle mode. Set to stop the PCA when Idle mode is invoked. 6W D T E Watchdog Timer Enable Clear to disable Watchdog Timer function on PCA Module 4, Set to enable it. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2-1 CPS1:0 EWC Count Pulse Select bits CPS1 CPS0 Clock source 0 0 Internal Clock, FPca/6 0 1 Internal Clock, FPca/2 1 0 Timer 0 overflow 1 1 External clock at ECI/P1.2 pin (Max. Rate = FPca/4) 0E C F Enable PCA Counter Overflow Interrupt bit Clear to disable CF bit in CCON register to generate an interrupt. Set to enable CF bit in CCON register to generate an interrupt.

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Table 56. CCON Register interrupt request if the ECF bit in CMOD register is set. Must be cleared by software. Clear to turn the PCA Timer/Counter off. Set to turn the PCA Timer/Counter on. The value read from this bit is indeterminate. Do not set this bit. interrupt request if the ECCF 4 bit in CCAPM 4 register is set. Must be cleared by software. interrupt request if the ECCF 3 bit in CCAPM 3 register is set. Must be cleared by software. interrupt request if the ECCF 2 bit in CCAPM 2 register is set. Must be cleared by software. interrupt request if the ECCF 1 bit in CCAPM 1 register is set. Must be cleared by software. interrupt request if the ECCF 0 bit in CCAPM 0 register is set. Must be cleared by software.

Table 57. CCAPnH Registers Table 58. CCAPnL Registers

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Table 59. CCAPMn Registers The Value read from this bit is indeterminate. Do not set this bit. Clear to disable the Compare function. Set to enable the Compare function. output, the Pulse Width Modulator (PWM) and the Watchdog Timer (WDT).

5 CAPPn

Clear to disable the Capture function triggered by a positive edge on CEXx pin. Clear to disable the Capture function triggered by a negative edge on CEXx pin. Set to enable the Capture function triggered by a negative edge on CEXx pin. CCFx bit in CCON register, flagging an interrupt. The toggle mode is configured by setting ECOMx, MATx and TOGx bits.

0 ECCFn

Clear to disable CCFx bit in CCON register to generate an interrupt request. Set to enable CCFx bit in CCON register to generate an interrupt request.

Table 60. CH Register Table 61. CL Register

86 A/T89C51AC2

4127G–8051–05/06 Analog-to-Digital Converter (ADC) This section describes the on-chip 10 bit analog-to-digital converter of the A/T89C51AC2. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10-bit cascaded potentiometric ADC. Two modes of conversion are available: - Standard conversion (8 bits). - Precision conversion (10 bits). For the precision conversion, set bit PSIDLE in ADCON register and start conversion. The device is in a pseudo-idle mode, the CPU does not run but the peripherals are always running. This mode allows digital noise to be as low as possible, to ensure high precision conversion. For this mode it is necessary to work with end of conversion interrupt, which is the only way to wake the device up. If another interrupt occurs during the precision conversion, it will be served only after this conversion is completed. Features  8 channels with multiplexed inputs  10-bit cascaded potentiometric ADC  Conversion time 16 micro-seconds (typ.)  Zero Error (offset) ± 2 LSB max  Positive External Reference Voltage Range (VAREF) 2.4 to 3.0 Volt (typ.)  ADCIN Range 0 to 3Volt  Integral non-linearity typical 1 LSB, max. 2 LSB  Differential non-linearity typical 0.5 LSB, max. 1 LSB  Conversion Complete Flag or Conversion Complete Interrupt  Selectable ADC Clock ADC Port 1 I/O Functions Port 1 pins are general I/O that are shared with the ADC channels. The channel select bit in ADCF register define which ADC channel/port1 pin will be used as ADCIN. The remaining ADC channels/port1 pins can be used as general-purpose I/O or as the alter- nate function that is available. A conversion launched on a channel which are not selected on ADCF register will not have any effect. VAREF VAREF should be connected to a low impedance point and must remain in the range specified in Table 77. If the ADC is not used, it is recommended to connect VAREF to VAGND.

88 A/T89C51AC2

A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). After completion of the A/D conversion, the ADSST bit is cleared by hardware. high. In this case one should wait Tsetup only before the first conversion. Table 62. Selected Analog input 3FFh if greater than VAREF and 000h if less than VAGND. Clock Selection The ADC clock is the same as CPU. caler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency.

000 A N 0

001 A N 1

010 A N 2

011 A N 3

100 A N 4

101 A N 5

110 A N 6

111 A N 7

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4127G–8051–05/06 // clear the field SCH[2:0] ADCON and = F8h // Select the channel ADCON | = channel // Start conversion in precision mode ADCON | = 48h Note: to enable the ADC interrupt: EA = 1

Table 64. ADCON Register Set to use P1.x as ADC input. Clear to use P1.x as standart I/O port.

6 PSIDLE

Clear to convert without idle mode. Clear for Standby mode (power dissipation 1 uW). Must be cleared by software.

3 ADSST

Set to start an A/D conversion.

92 A/T89C51AC2

Table 65. ADCLK Register Table 66. ADDH Register Table 67. ADDL Register The value read from these bits are indeterminate. Do not set these bits. The value read from these bits are indeterminate. Do not set these bits.

interrupt and an ADC. These interrupts are shown below. Figure 49. Interrupt Control System

94 A/T89C51AC2

which must be cleared to disable all the interrupts at the same time. bit values and priority levels associated with each combination. Table 68. Priority Level Bit Values determined by the pollin g sequence, see Table 69. Table 69. Interrupt Priority Within level

4127G–8051–05/06 Registers Table 70. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register Reset Value = 0000 0000b bit addressable 76543210 EA EC ET2 ES ET1 EX1 ET0 EX0 Bit Number Bit Mnemonic Description 7E A Enable All Interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. 6E C PCA Interrupt Enable Clear to disable the PCA interrupt. Set to enable the PCA interrupt. 5E T 2 Timer 2 Overflow Interrupt Enable bit Clear to disable Timer 2 overflow interrupt. Set to enable Timer 2 overflow interrupt. 4E S Serial Port Enable bit Clear to disable serial port interrupt. Set to enable serial port interrupt. 3E T 1 Timer 1 Overflow Interrupt Enable bit Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. 2E X 1 External Interrupt 1 Enable bit Clear to disable external interrupt 1. Set to enable external interrupt 1. 1E T 0 Timer 0 Overflow Interrupt Enable bit Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. 0E X 0 External Interrupt 0 Enable bit Clear to disable external interrupt 0. Set to enable external interrupt 0.

96 A/T89C51AC2

Table 71. IEN1 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.

1 EADC

Clear to disable the ADC interrupt. Set to enable the ADC interrupt. The value read from this bit is indeterminate. Do not set this bit.

Table 72. IPL0 Register The value read from this bit is indeterminate. Do not set this bit.

6 PPC PCA Interrupt Priority bit

Refer to PT2H for priority level. Refer to PSH for priority level. Refer to PT1H for priority level. Refer to PX1H for priority level. Refer to PT0H for priority level. Refer to PX0H for priority level.

98 A/T89C51AC2

Table 73. IPL1 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.

1 PADCL ADC Interrupt Priority Level Less Significant Bit

Refer to PSPIH for priority level. The value read from this bit is indeterminate. Do not set this bit.

Table 74. IPH0 Register The value read from this bit is indeterminate. Do not set this bit.

6 PPCH

4 PSH

100 A/T89C51AC2

Table 75. IPH1 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.

1 PADCH

The value read from this bit is indeterminate. Do not set this bit.

4127G–8051–05/06

Electrical Characteristics

Absolute Maximum Ratings* DC Parameters for Standard Voltage TA = -40°C to +85°C; VSS = 0V; VCC = 3V to 5.5V; F = 0 to 40 MHz Ambiant Temperature Under Bias: Table 76. DC Parameters in Standard Voltage maximum rating conditions may affect device reliability.

102 A/T89C51AC2

if a crystal oscillator used (see Figure 50.).

1. Idle I CC is measured with all output pins disconnected; XTAL1 driven with T CLCH,
2. Power-down I CC is measured with all output pins disconnected; EA = VCC, PORT 0 =

and the POF flag must be set.

1. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be super-

Trigger use is not necessary.

1. Typicals are based on a limited number of samples and are not guaranteed. The val-

ues listed are at room temperature.

1. Under steady state (non-transient) conditions, I OL must be externally limited as fol-

not guaranteed to sink current greater than the listed test conditions.

1. ICC_FLASH_WRITE operating current while a Flash block write is on going.

Figure 50. ICC Test Condition, Active Mode All other pins are disconnected.

104 A/T89C51AC2

Notes: 1. Typicals are based on a limited number of samples and are not guaranteed. AVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. Table 78, Table 81 and Table 84 give the description of each AC symbols. Table 79, Table 83 and Table 85 give for each range the AC parameter. and use this value in the formula. LLIV and 20 MHz, Standard clock. Table 77. DC Parameters for AD Converter in Precision Conversion

Table 78. Symbol Description Table 79. AC Parameters for a Fix Clock (F = 40 MHz)

106 A/T89C51AC2

Table 80. AC Parameters for a Variable Clock

12 TCLCL

Table 81. Symbol Description Table 82. AC Parameters for a Variable Clock (F = 40 MHz)

108 A/T89C51AC2

Table 83. AC Parameters for a Variable Clock

Table 84. Symbol Description (F = 40 MHz)

110 A/T89C51AC2

Table 85. AC Parameters for a Fix Clock (F = 40 MHz) Table 86. AC Parameters for a Variable Clock Table 87. AC Parameters

4127G–8051–05/06 External Clock Drive Waveforms AC Testing Input/Output Waveforms AC inputs during testing are driven at V CC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at V IH min for a logic “1” and VIL max for a logic “0”. Float Waveforms For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V OH/VOL level occurs. IOL/IOH ≥ ± 20 mA. VCC-0.5V 0.45V 0.7VCC 0.2VCC-0.1 TCHCL TCLCX TCLCL TCLCH TCHCX INPUT/OUTPUT 0.2 VCC + 0.9 0.2 VCC - 0.1 VCC -0.5V 0.45V FLOAT VOH - 0.1 V VOL + 0.1 V VLOAD VLOAD + 0.1 V VLOAD - 0.1 V

112 A/T89C51AC2

4127G–8051–05/06 Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2. This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propa- gation also varies from output to output and component. Typically though (T A=25°C fully loaded) RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. DATA PCL OUT DATA PCL OUT DATA PCL OUT SAMPLED SAMPLED SAMPLED STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 FLOAT FLOAT FLOAT THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION INDICATES ADDRESS TRANSITIONS EXTERNAL PROGRAM MEMORY FETCH FLOAT DATA SAMPLED DPL OR Rt OUT INDICATES DPH OR P2 SFR TO PCH TRANSITION PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL) PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) OLD DATANEW DATA P0 PINS SAMPLED P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED P0 PINS SAMPLED RXD SAMPLED INTERNAL CLOCK XTAL2 ALE PSEN P2 (EXT) READ CYCLE WRITE CYCLE RD WR PORT OPERATION MOV PORT SRC MOV DEST P0 MOV DEST PORT (P1. P2. P3) (INCLUDES INTO. INT1. TO T1) SERIAL PORT SHIFT CLOCK TXD (MODE 0) DATA OUT DPL OR Rt OUT INDICATES DPH OR P2 SFR TO PCH TRANSITION RXD SAMPLED

114 A/T89C51AC2

4127G–8051–05/06

Ordering Information

Table 91. Possible Order Entries

40 MHz

4127G–8051–05/06 Package Drawings VQFP44

116 A/T89C51AC2

4127G–8051–05/06 PLCC44

4127G–8051–05/06 Datasheet Change Log for A/T89C51AC2 Changes from 4127D - 02/03 to 4127E - 01/05 1. Changed value of IPDMAX to 400, Section “Electrical Characteristics”, page 101. 2. PCA , CPS0, register correction, Section “PCA Registers”, page 81. 3. Cross Memory section added. Section “Operation Cross Memory Access”, page 44. Changes from 4127E - 01/05 to 4127F - 03/05 1. Changed product part number from “T89C51AC2” to “A/T89C51AC2”. 2. Added “Green” product ordering information. 3. Clarification to Mode Switching Waveform diagrams. See page page 16. Changes from 4127F - 03/05 to 4127G - 05/06 1. Minor corrections throughout the document.

i 4127G–8051–05/06 A/T89C51AC2 Table of Contents

4127G–8051–05/06 A/T89C51AC2

4127G–8051–05/06 A/T89C51AC2

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