Microcontroller

T89C5115

ATMEL Corporation

The T89C5115 is a high performance Flash version ofthe 80C51 single chip 8-bit microcontrollers. It contains a 16-KB Flash memory blockfor program and data.

Manufacturer: ATMEL Corporation

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Features

80C51 Core Architecture 256 Bytes of On-chip RAM 256 Bytes of On-chip ERAM – 16-KB of On-chip Flash Memory – Data Retention: 10 Years at 85 °C – Read/Write Cycle: 10K 2K Bytes of On-chip Flash for Bootloader 2K Bytes of On-chip EEPROM – Read/Write Cycle: 100k 14-sources 4-level Interrupts Three 16-bit Timers/Counters Full Duplex UART Compatible 80C51 Maximum Crystal Frequency 40 MHz – I nX 2M o d e ,2 0M H z( C P Uc o r e ,4 0M H z ) Three or Four Ports: 16 or 20 Digital I/O Lines Two-channel 16-bit PCA with: – PWM (8-bit) – High-speed Output – Timer and Edge Capture Double Data Pointer 21-bit WatchDog Timer (7 Programmable Bits) A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs Power Saving Modes: – Idle Mode – Power-down Mode Power Supply: 5V ± 10% (or 3V (1) ± 10%) Temperature Range: Industrial (-40 ° to +85°C) Packages: SOIC28, PLCC28, VQFP32 Note: 1. Ask for availability

Description

The T89C5115 is a high performance Flash version of the 80C51 single chip 8-bit microcontrollers. It contains a 16-KB Flash memory block for program and data. The 16-KB Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin. The T89C5115 retains all features of the 80C52 with 256 bytes of internal RAM, a 7- source 4-level interrupt controller and three timer/counters. In addition, the T89C5115 has a 10-bit A/D converter, a 2-KB Boot Flash memory, 2-KB EEPROM for data, a Programmable Counter Array, an ERAM of 256 bytes, a Hardware WatchDog Timer and a more versatile serial channel that facilitates multiprocessor communication (EUART). The fully static design of the T89C5115 reduces system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The T89C5115 has two software-selectable modes of reduced activity and an 8 bit clock prescaler for further reduction in power consumption. In the idle mode the CPU is frozen while the peripherals and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. The added features of the T89C5115 make it more powerful for applications that need A/D conversion, pulse width modulation, high speed I/O and counting capabilities such as industrial control, consumer goods, alarms, motor control, etc. While remain- ing fully compatible with the 80C52 it offers a superset of this standard microcontroller. Low Pin Count 8-bit MCU with A/D Converter and 16-Kbytes of Flash Memory T89C5115

2 T89C5115

4128A–8051–04/02 In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time. Block Diagram Notes: 1. 8 analog Inputs/8 Digital I/O 2. 2-Bit I/O Port Timer 0 INT RAM 256x8 RxD TxD XTAL2 XTAL1 UART CPU Timer 1 INT1 CtrlINT0 C51 CORE P2(2) Port 1 Port 2 Port 3 Parallel I/O Ports & Ext. Bus P1(1) ERAM 256x8 IB-bus PCA RESET Watch Dog PCA ECI Vss Vcc Timer2 T2EX Port 4 P4(2) 10-bit ADC Flash 16kx8 Boot loader 2kx8 EEPROM 2kx8

4128A–8051–04/02 Pin Configuration P3.4/T0 P3.3/INT1 P4.1 P3.7 P3.2/INT0 P1.5/AN5 P1.7/AN7 P1.6/AN6 P2.0 VAREF VAVCC VAGND P1.0/AN0/T2 P1.1/AN1/T2EX P1.2/AN2/ECI P1.3/AN3/CEX0 P1.4/AN4/CEX1 RESET VCC VSS P4.0 P2.1 P3.6 P3.5/T1 P3.1/TxD 13 P3.0/RxD 14

16 XTAL1

15 XTAL2

P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 P3.7 P4.0 P4.1 P2.1 P3.6 P2.0 P1.4/AN4/CEX1 P1.5/AN5 P1.6/AN6 P1.7/AN7 P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 VAVCC PLCC-28 P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 P3.7 P4.0 P4.1 P2.1 P3.6 P2.0 P1.4/AN4/CEX1 P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4 P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 VAVCC QFP-32 NC NC NC NC 2425

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Table 1. Pin Description inputs via the ADCCF register (in this case the internal pull-ups are disconnected). input; the PCA external clock input and the PCA module I/O. External clock input for Timer/counter2. Trigger input for Timer/counter2. PCA module 0 Entry of input/PWM output. PCA module 1 Entry of input/PWM output. It can drive CMOS inputs without external pull-ups. of current (IIL, on the datasheet) because of the internal pull-ups.

It can drive CMOS inputs without external pull-ups. of current (IIL, on the datasheet) because of the internal pull-up transistor. It can drive CMOS inputs without external pull-ups. using only an external capacitor to VCC. cycle of 50% should be maintained. Output from the inverting oscillator amplifier. Table 1. Pin Description (Continued)

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independently programmed as input or output. for its alternate input output function. ister (x = 1 to 4). To use a pin for general-purpose input, set the bit in the Px register. This turns off the output FET drive. operation of Ports is discussed further in "quasi-Bidirectional Port Operation" paragraph. Figure 1. Ports Structure Note: The internal pull-up can be disabled on P1 when analog function is selected.

It is not obvious the last three instructions in this list are Read-Modify-Write instructions. than the pins returns the correct logic-one value. returned to input conditions by a logical one written to the latch. Table 2. Read-Modify-Write Instructions

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Figure 2. Internal Pull-Up Configurations

Table 3. C 5 1C o r eS F R s Table 4. I/O Port SFRs Table 5. Timers SFRs

1 Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

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Table 5. Timers SFRs (Continued) Table 6. Serial I/O Port SFRs Table 7. PCA SFRs

Table 8. Interrupt SFRs Table 9. ADC SFRs Table 10. Other SFRs

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Note: 1. These registers are bit-addressable. whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF . Table 11. SFR Mapping

4128A–8051–04/02 Clock The T89C5115 core needs only 6 clock periods per machine cycle. This feature, called ‘X2’, provides the following advantages: Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. Saves power consumption while keeping the same CPU power (oscillator power saving). Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes. Increases CPU power by 2 while keeping the same crystal frequency. In order to keep the original C51 compatibility, a divider-by-2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by the software. An extra feature is available to start after Reset in the X2 mode. This feature can be enabled by a bit X2B in the Hardware Security Byte. This bit is described in the section "In-System Programming". Description The X2 bit in the CKCON register (see Table 12) allows switching from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode) for the CPU Clock only (see Figure 3.). The Timers 0, 1 and 2, Uart, PCA or WatchDog switch in X2 mode only if the corre- sponding bit is cleared in the CKCON register. The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 3. shows the clock generation block diagram. The X2 bit is validated on the XTAL1÷2 rising edge to avoid glitches when switching from the X2 to the STD mode. Figure 4 shows the mode switching waveforms.

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Figure 3. Clock CPU Generation Diagram

Figure 4. Mode Switching Waveforms

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4128A–8051–04/02 Register Table 12. CKCON Register CKCON (S:8Fh) Clock Control Register Notes: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit has no effect. Reset Value = x000 0000b 76543210 – WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6W D X 2 WatchDog clock(1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

5 PCAX2

Programmable Counter Array clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 4S I X 2 Enhanced UART clock (MODE 0 and 2) (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 3T 2 X 2 Timer2 clock(1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 2T 1 X 2 Timer1 clock(1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 1T 0 X 2 Timer0 clock(1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 0X 2 CPU clock Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6 clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2"bits.

divided by 2 using the X2 mode detailed in Section “Clock”. datasheet. The status of the Port pins during reset is detailed in Table 13. Figure 5. Reset Circuitry and Power-On Reset Table 13. Pin Conditions in Special Operating Modes lead to unpredictable behaviour of the C51 microcontroller. ping of the bootloader in the code area, a reset failure can be critical. (write or erase) may corrupt the Flash on-chip memory . supply failure, power supply switched off).

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4128A–8051–04/02 Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode, program execution halts. Idle mode freezes the clock to the CPU at known states while the peripherals continue to be clocked. The CPU status before entering Idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The status of the Port pins during Idle mode is detailed in Table 13. Entering Idle Mode To enter Idle mode, set the IDL bit in PCON register (see Table 14). The T89C5115 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed. Note: If IDL bit and PD bit are set simultaneously, the T89C5115 enters Power-down mode. Then it does not go in Idle mode when exiting Power-down mode. Exiting Idle Mode There are two ways to exit Idle mode: 1. Generate an enabled interrupt. – Hardware clears IDL bit in PCON register which restores the clock to the CPU. Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Idle mode. The general-purpose flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt occurred during normal operation or during Idle mode. When Idle mode is exited by an interrupt, the interrupt service routine may examine GF1 and GF0. 2. Generate a reset. – A logic high on the RST pin clears IDL bit in PCON register directly and asynchronously. This restores the clock to the CPU. Program execution momentarily resumes with the instruction immediately following the instruction that activated the Idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the T89C5115 and vectors the CPU to address C:0000h. Note: During the time that execution resumes, the internal RAM cannot be accessed; however, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated Idle mode should n o tw r i t et oaP o r tp i no rt ot h ee x t e r n a lR A M . Power-down Mode The Power-down mode places the T89C5115 in a very low power state. Power-down mode stops the oscillator, freezes all clock at known states. The CPU status prior to entering Power-down mode is preserved, i.e., the program counter, program status word register retain their data for the duration of Power-down mode. In addition, the SFRs and RAM contents are preserved. The status of the Port pins during Power-down mode is detailed in Table 13. N o t e : V D Dm a yb er e d u c e dt oa sl o wa sVRET during Power-down mode to further reduce power dissipation. T ake care, however, that VDD is not reduced until Power-down mode is invoked. Entering Power-down Mode To enter Power-down mode, set PD bit in PCON register. The T89C5115 enters the Power-down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed.

VDD is restored to the normal operating level.

Generate an enabled external interrupt.

following the instruction that activated Power-down mode. the duration of the interrupt must be long enough to allow the oscillator to stabilize. The execution will only resume when the interrupt is deasserted.

Exit from power-down by external interrupt does not affect the SFRs nor the internal

Figure 6. Power-down Exit Waveform Using INT1:0# Power-down mode should not write to a Port pin or to the external RAM.

Exit from power-down by reset redefines all the

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Table 14. PCON Register The value read from these bits is indeterminate. Do not set these bits. Cleared by hardware when an interrupt or reset occurs. Set to activate the Power-down mode. If IDL and PD are both set, PD takes precedence. Cleared by hardware when an interrupt or reset occurs. Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence.

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Figure 8. Lower 128 bytes Internal RAM Organization must then be initialized properly.

reducing code size in case of intensive usage of external memory accesses. Figure 9. Dual Data Pointer Implementation using one data pointer as a “source” pointer and the other one as a “destination” pointer. enhanced algorithm libraries.

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4128A–8051–04/02 Registers Table 16. PSW Register PSW (S:8Eh) Program Status Word Register Reset Value = 0000 0000b 76543210 CY AC F0 RS1 RS0 OV F1 P Bit Number Bit Mnemonic Description 7C Y Carry Flag Carry out from bit 1 of ALU operands. 6A C Auxiliary Carry Flag Carry out from bit 1 of addition operands. 5F 0 User Definable Flag 0 4-3 RS1:0 Register Bank Select Bits Refer to Table for bits description. 2O V Overflow Flag Overflow set by arithmetic operations. 1F 1 User Definable Flag 1 Parity Bit Set when ACC contains an odd number of 1’s. Cleared when ACC contains an even number of 1’s.

Table 17. AUXR1 Register The value read from these bits is indeterminate. Do not set these bits.

5 ENBOOT

Clear this bit for disable boot flash. The value read from this bit is indeterminate. Do not set this bit. 3G F 3 General-purpose Flag 3. 1 – Reserved for Data Pointer Extension. Set to select second dual data pointer: DPTR1. Clear to select first dual data pointer: DPTR0.

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4128A–8051–04/02 EEPROM Data Memory The 2-kbyte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/ERAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction. A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming). The number of data written on the page may vary from 1 up to 128 bytes (the page size). When programming, only the data written in the column latch is programmed and a ninth bit is used to obtain this feature. This provides the capability to program the whole memory by bytes, by page or by a number of bytes in a page. Indeed, each ninth bit is set when the writing the corresponding byte in a row and all these ninth bits are reset after the writing of the complete EEPROM row. Write Data in the Column Latches Data is written by byte to the column latches as for an external RAM memory. Out of the 11 address bits of the data pointer, the 4 MSBs are used for page selection (row) and 7 are used for byte selection. Between two EEPROM programming sessions, all the addresses in the column latches must stay on the same page, meaning that the 4 MSB must no be changed. The following procedure is used to write to the column latches: Save and disable interrupt. Set bit EEE of EECON register Load DPTR with the address to write Store A register with the data to be written Execute a MOVX @DPTR, A If needed loop the three last instructions until the end of a 128 bytes page Restore interrupt. Note: The last page address used when loading the column latch is the one used to select the page programming address. Programming The EEPROM programming consists of the following actions: writing one or more bytes of one page in the column latches. Normally, all bytes must belong to the same page; if not, the first page address will be latched and the others discarded. launching programming by writing the control sequence (50h followed by A0h) to the EECON register. EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that the EEPROM segment is not available for reading. The end of programming is indicated by a hardware clear of the EEBUSY flag. Note: The sequence 5xh and Axh must be executed without instructions between them, other- wise the programming is aborted. Read Data The following procedure is used to read the data stored in the EEPROM memory: Save and disable interrupt Set bit EEE of EECON register Load DPTR with the address to read Execute a MOVX A, @DPTR Restore interrupt

4128A–8051–04/02 ;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read. ;* Acc contain the reading value ;* NOTE: before execute this function, be sure the EEPROM is not BUSY api_rd_eeprom_byte: MOV EECON, #02h; map EEPROM in XRAM space MOVX A, @DPTR MOV EECON, #00h; unmap EEPROM ret ;* NAME: api_ld_eeprom_cl ;* DPTR contain address to load ;* Acc contain value to load ;* NOTE: in this example we load only 1 byte, but it is possible upto ;* 128 bytes. ;* before execute this function, be sure the EEPROM is not BUSY api_ld_eeprom_cl: MOV EECON, #02h ; map EEPROM in XRAM space MOVX @DPTR, A MOVEECON, #00h; unmap EEPROM ret ;* NAME: api_wr_eeprom ;* NOTE: before execute this function, be sure the EEPROM is not BUSY api_wr_eeprom: MOV EECON, #050h MOV EECON, #0A0h ret

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4128A–8051–04/02 Registers Table 18. EECON Register EECON (S:0D2h) EEPROM Control Register Reset Value = XXXX XX00b Not bit addressable 76543210 EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY Bit Number Bit Mnemonic Description 7-4 EEPL3-0 Programming Launch Command bits Write 5Xh followed by AXh to EEPL to launch the programming. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2- Reserved The value read from this bit is indeterminate. Do not set this bit.

1 EEE

S e tt om a pt h eE E P R O Ms p a c ed u r i n gM O V Xi n s t r u c t i o n s( W r i t ei nt h ec o l u m n latches). Clear to map the XRAM space during MOVX.

0 EEBUSY

Set by hardware when programming is in progress. Cleared by hardware when programming is done. Can not be set or cleared by software.

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4128A–8051–04/02 FM0 Memory Architecture The Flash memory is made up of 4 blocks (see Figure 11): 1. The memory array (user space) 16-KB. 2. The Extra Row. 3. The Hardware security bits. 4. The column latch registers. User Space This space is composed of a 16-KB Flash memory organized in 128 pages of 128 bytes. It contains the user’s application code. Extra Row (XROW) This row is a part of FM0 and has a size of 128 bytes. The extra row may contain infor- mation for boot loader usage. Hardware security Byte The Hardware Security Byte space is a part of FM0 and has a size of 1 byte. The 4 MSB can be read/written by software, the 4 LSB can only be read by software and written by hardware in parallel mode. Column Latches The column latches, also part of FM0, have a size of full page (128 bytes). The column latches are the entrance buffers of the three previous memory locations (user array, XROW and Hardware security byte). Cross Flash Memory Access The FM0 memory can be program only from FM1. Programming FM0 from FM0 or from external memory is impossible. The FM1 memory can be program only by parallel programming. The Table 19 show all software flash access allowed. Table 19. Cross Flash Memory Access

page while bits 14 to 7 are used to select the programming address of the page. Setting FPS bit takes precedence on the EEE bit in EECON register. dance with Table 20. A MOVC instruction is then used for reading these spaces. Table 20. FM0 Blocks Select Bits spaces to program according to FMOD1:0 bits. Table 21. Programming Spaces wise the programming is aborted.

5 X 0 0 No action

5 X 0 1 No action

5 X 1 0 No action

5 X 1 1 No action

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4128A–8051–04/02 Interrupts that may occur during programming time must be disabled to avoid any spuri- ous exit of the programming mode. Status of the Flash Memory The bit FBUSY in FCON register is used to indicate the status of programming. FBUSY is set when programming is in progress. Selecting FM1 The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh. Loading the Column Latches Any number of data from 1 byte to 128 bytes can be loaded in the column latches. This provides the capability to program the whole memory by byte, by page or by any number of bytes in a page. When programming is launched, an automatic erase of the locations loaded in the col- umn latches is first performed, then programming is effectively done. Thus no page or block erase is needed and only the loaded data are programmed in the corresponding page. The following procedure is used to load the column latches and is summarized in Figure 12: Disable interrupt and map the column latch space by setting FPS bit. Load the DPTR with the address to load. Load Accumulator register with the data to load. Execute the MOVX @DPTR, A instruction. If needed loop the three last instructions until the page is completely loaded. unmap the column latch and Enable Interrupt

34 T89C5115

Figure 13. Flash and Extra row Programming Procedure Save and disable the interrupts. Load DPTR at address 0000h. Load Accumulator register with the data to load. Execute the MOVX @DPTR, A instruction. FCON register (only from FM1). The end of the programming indicated by the FBusy flag cleared.

36 T89C5115

Figure 15. Reading Procedure chip code and data located in FM0 and FM1. The only way to write this bits are the parallel mode. They are set by default to level 3. Table 22. Program Lock bit Preventing Flash Corruption See paragraph in the "Power Management" section, page 17. external program memory returns non encrypted data. 2 P U U Parallel programming of the Flash is disabled.

4128A–8051–04/02 Registers FCON Register FCON (S:D1h) Flash Control Register Reset Value = 0000 0000b 76543210 FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY Bit Number Bit Mnemonic Description 7-4 FPL3:0 Programming Launch Command Bits Write 5Xh followed by AXh to launch the programming according to FMOD1:0. (see Table 21.) 3F P S Flash Map Program Space Set to map the column latch space in the data memory space. Clear to re-map the data memory space. 2-1 FMOD1:0 Flash Mode See Table 20 or T able 21.

0 FBUSY

Set by hardware when programming is in progress. Clear by hardware when programming is done. Can not be changed by software.

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and if needed also a customized Boot loader in the FM1. This allow the customer to have a full use of the 16-Kbyte user memory. A further method exist in activating the Atmel boot loader by hardware activation. The FM0 can be programmed also by the parallel mode using a programmer. Figure 16. Flash Memory Mapping

@0000h on FM0 or execute the boot loader at address @F800h on FM1.

BLJB = 0 on parts delivered with bootloader programmed.
To read or modify this bit, the APIs are used.
This byte contains the MSB of the user boot loader address in FM0.
The default value of SBV is FFh (no user boot loader in FM0).
To read or modify this byte, the APIs are used.
These bytes are reserved for customer use.
To read or modify these bytes, the APIs are used.

Figure 17. Hardware Boot Process Algorithm

40 T89C5115

on the Atmel web site at www.atmel.com. Table 23. List of API

4128A–8051–04/02 Hardware Security Byte Table 25. Hardware Security byte Default value after erasing chip: FFh Notes: 1. Only the 4 MSB bits can be accessed by software. 2. The 4 LSB bits can only be accessed by parallel mode. 76543210 X2B BLJB - - - LB2 LB1 LB0 Bit Number Bit Mnemonic Description 7X 2 B X2 Bit Set this bit to start in standard mode Clear this bit to start in X2 mode. 6B L J B Boot Loader Jump Bit - 1: To start the user’s application on next RESET (@0000h) located in FM0, - 0: To start the boot loader(@F800h) located in FM1. 5-3 - Reserved The value read from these bits are indeterminate. 2-0 LB2:0 Lock Bits

42 T89C5115

Serial I/O Port The T89C5115 I/O serial port is compatible with the I/O serial port in the 80C52. Figure 18. Serial I/O Port Block Diagram framing bit error detection feature, set SMOD0 bit in PCON register. Figure 19. Framing Error Block Diagram The software may examine the FE bit after each reception to check for data errors.

44 T89C5115

4128A–8051–04/02 Given Address Each device has an individual address that is specified in the SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example: SADDR0101 0110b SADEN1111 1100b Given0101 01XXb Here is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0010b SADEN1111 1101b Given1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To com- municate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b). Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.: SADDR 0101 0110b SADEN 1111 1100b SADDR OR SADEN1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 1X11b, Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 1X11B, Slave C:SADDR=1111 0010b SADEN1111 1101b Given1111 1111b

4128A–8051–04/02 For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. Registers Table 26. SCON Register SCON (S:98h) Serial Control Register Reset Value = 0000 0000b Bit addressable 76543210 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI Bit Number Bit Mnemonic Description 7F E Framing Error bit (SMOD0 = 1) C l e a rt or e s e tt h ee r r o rs t a t e ,n o tc l e a r e db yav a l i ds t o pb i t . Set by hardware when an invalid stop bit is detected. –S M 0 Serial port Mode bit 0 (SMOD0 = 0) Refer to SM1 for serial port mode selection. 6S M 1 Serial port Mode bit 1 SM0 SM1 Mode Baud Rate 0 0 Shift Register F XTAL/12 (or FXTAL /6 in mode X2) 0 1 8-bit UART Variable 1 0 9-bit UART F XTAL/64 or FXTAL/32 1 1 9-bit UART Variable 5S M 2 Serial port Mode 2 bit/Multiprocessor Communication Enable bit Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3. 4R E N Reception Enable bit Clear to disable serial reception. Set to enable serial reception. 3T B 8 Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3 Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. 2R B 8 Receiver Bit 8/Ninth bit received in modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. 1T I Transmit Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. 0R I Receive Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 20 and Figure 21 in the other modes.

46 T89C5115

Table 27. SADEN Register Table 28. SADDR Register Table 29. SBUF Register

Table 30. PCON Register S e tt os e l e c td o u b l eb a u dr a t ei nm o d e1 ,2o r3 . Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. The value read from this bit is indeterminate. Do not set this bit. Clear to recognize next reset type. Cleared by user for general-purpose usage. Set by user for general-purpose usage. Cleared by user for general-purpose usage. Set by user for general-purpose usage. Cleared by hardware when reset occurs. Set to enter power-down mode. Clear by hardware when interrupt or reset occurs.

48 T89C5115

4128A–8051–04/02 Timers/Counters The T89C5115 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. The various operating modes of each Timer/Counter are described in the following sections. Timer/Counter Operations A basic operation is Timer registers THx and TLx (x= 0, 1) connected in cascade to form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (see Figure 31) turns the Timer on by allowing the selected input to increment TLx. When TLx overflows it increments THx; when THx overflows it sets the Timer overflow flag (TFx) in TCON reg- ister. Setting the TRx does not clear the THx and TLx Timer registers. Timer registers can be accessed to obtain the current count or to enter preset values. They can be read at any time but TRx bit must be cleared to preset their values, otherwise the behavior of the Timer/Counter is unpredictable. The C/Tx# control bit selects Timer operation or Counter operation by selecting the divided-down peripheral clock or external pin Tx as the source for the counted signal. TRx bit must be cleared when changing the mode of operation, otherwise the behavior of the Timer/Counter is unpredictable. For Timer operation (C/Tx#= 0), the Timer register counts the divided-down peripheral clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock periods). The Timer clock rate is F PER/6, i.e. F OSC/12 in standard mode or F OSC/6 in X2 mode. For Counter operation (C/Tx#= 1), the Timer register counts the negative transitions on the Tx external input pin. The external input is sampled every peripheral cycles. When the sample is high in one cycle and low in the next one, the Counter is incremented. Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition, the maximum count rate is F PER/12, i.e. F OSC/24 in standard mode or F OSC/12 in X2 mode. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle. Timer 0 Timer 0 functions as either a Timer or event Counter in four modes of operation. Figure 22 to Figure 25 show the logical configuration of each mode. Timer 0 is controlled by the four lower bits of TMOD register (see Figure 32) and bits 0, 1, 4 and 5 of TCON register (see Figure 31). TMOD register selects the method of Timer gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10 and M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0). For normal Timer operation (GATE0= 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer operation. Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an inter- rupt request. It is important to stop Timer/Counter before changing mode.

50 T89C5115

reload value may be changed at any time by writing it to TH0 register. Figure 24. Timer/Counter x (x= 0 or 1) in Mode 2 Figure 25. Timer/Counter 0 in Mode 3: Two 8-bit Counters

4128A–8051–04/02 Timer 1 Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. Follow- ing comments help to understand the differences: Timer 1 functions as either a Timer or event Counter in three modes of operation. Figure 22 to Figure 24 show the logical configuration for modes 0, 1, and 2. Timer 1’s mode 3 is a hold-count mode. Timer 1 is controlled by the four high-order bits of TMOD register (see Figure 32) and bits 2, 3, 6 and 7 of TCON register (see Figure 31). TMOD register selects the method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of operation (M11 and M01). TCON register provides Timer 1 control functions: overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type control bit (IT1). Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best suited for this purpose. For normal Timer operation (GATE1= 0), setting TR1 allows TL1 to be incremented by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control Timer operation. Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an interrupt request. When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it off and on. It is important to stop Timer/Counter before changing mode. Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg- ister) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (see Figure 22). The upper 3 bits of TL1 register are ignored. Prescaler overflow incre- ments TH1 register. Mode 1 (16-bit Timer) Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in cascade (see Figure 23). The selected input increments TL1 register. Mode 2 (8-bit Timer with Auto- Reload) Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from TH1 register on overflow (see Figure 24). TL1 overflow sets TF1 flag in TCON register and reloads TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged. M o d e3( H a l t ) Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3.

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interrupts are globally enabled by setting EA bit in IEN0 register. Figure 26. Timer Interrupt System

4128A–8051–04/02 Registers Table 31. TCON Register TCON (S:88h) Timer/Counter Control Register Reset Value = 0000 0000b 76543210 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Number Bit Mnemonic Description 7T F 1 Timer 1 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. 6T R 1 Timer 1 Run Control Bit Clear to turn off Timer/Counter 1. S e tt ot u r no nT i m e r / C o u n t e r1 . 5T F 0 Timer 0 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 0 register overflows. 4T R 0 Timer 0 Run Control Bit Clear to turn off Timer/Counter 0. S e tt ot u r no nT i m e r / C o u n t e r0 . 3I E 1 Interrupt 1 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (see IT1). Set by hardware when external interrupt is detected on INT1# pin. 2I T 1 Interrupt 1 Type Control Bit Clear to select low level active (level triggered) for external interrupt 1 (INT1#). Set to select falling edge active (edge triggered) for external interrupt 1. 1I E 0 Interrupt 0 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (see IT0). Set by hardware when external interrupt is detected on INT0# pin. 0I T 0 Interrupt 0 Type Control Bit Clear to select low level active (level triggered) for external interrupt 0 (INT0#). Set to select falling edge active (edge triggered) for external interrupt 0.

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Table 32. TMOD Register Notes: 1. Reloaded from TH1 at overflow.

Reloaded from TH0 at overflow.

Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. Clear for Timer operation: Timer 1 counts the divided-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1. 0 0 Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1). 0 1 Mode 1: 16-bit Timer/Counter. 1 1 Mode 3: Timer 1 halted. Retains count. 1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL1). Clear to enable Timer 0 whenever TR0 bit is set. Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set. Clear for Timer operation: Timer 0 counts the divided-down system clock. Set for Counter operation: Timer 0 counts negative transitions on external pin T0. 0 0 Mode 0: 8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0). 0 1 Mode 1: 16-bit Timer/Counter. T H 0i sa n8 - b i tT i m e ru s i n gT i m e r1 ’ sT R 0a n dT F 0b i t s .

Table 33. TH0 Register Table 34. TL0 Register Table 35. TH1 Register

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Table 36. TL1 Register

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Set T2OE bit in T2MOD register. Clear C/T2 bit in T2CON register. reload value or different depending on the application. To start the timer, set TR2 run control bit in T2CON register. independent since both functions use the values in the RCAP2H and RCAP2L registers. Figure 28. Clock-out Mode

4128A–8051–04/02 Registers Table 37. T2CON Register T2CON (S:C8h) Timer 2 Control Register Reset Value = 0000 0000b Bit addressable 76543210 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Number Bit Mnemonic Description 7T F 2 Timer 2 overflow Flag TF2 is not set if RCLK=1 or TCLK = 1. Must be cleared by software. Set by hardware on Timer 2 overflow. 6E X F 2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. Set to cause the CPU to vector to Timer 2 interrupt routine when Timer 2 interrupt is enabled. Must be cleared by software. 5R C L K Receive Clock bit Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3. 4T C L K Transmit Clock bit Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.

3 EXEN2

Timer 2 External Enable bit Clear to ignore events on T2EX pin for Timer 2 operation. S e tt oc a u s eac a p t u r eo rr e l o a dw h e nan e g a t i v et r a n s i t i o no nT 2 E Xp i ni s detected, if Timer 2 is not used to clock the serial port. 2T R 2 Timer 2 Run control bit Clear to turn off Timer 2. S e tt ot u r no nT i m e r2 . 1C / T 2 # Timer/Counter 2 select bit Clear for timer operation (input from internal clock system: F OSC). Set for counter operation (input from T2 input pin). 0C P / R L 2 # Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on Timer 2 overflow. Clear to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1.

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Table 38. T2MOD Register Table 39. TH2 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Clear to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output.

0 DCEN

Clear to disable Timer 2 as up/down counter. Set to enable Timer 2 as up/down counter.

Table 40. TL2 Register Table 41. RCAP2H Register Table 42. RCAP2L Register 7-0 High Byte of Timer 2 Reload/Capture. 7-0 Low Byte of Timer 2 Reload/Capture.

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ter. When exiting reset, the WDT is -by default- disable. time required to prevent a WDT reset. Note: When the WatchDog is enable it is impossible to change its period. Figure 29. WatchDog Timer

Table 43. Machine Cycle Count Table 44. Time-Out Computation

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4128A–8051–04/02 WatchDog Timer during Power-down Mode and Idle In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are 2 methods of exiting Power-down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, the WatchDog is disabled. Exiting Power-down with an interrupt is sig- nificantly different. The interrupt shall be held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the inter- rupt service for the interrupt used to exit Power-down. To ensure that the WDT does not overflow within a few states of exiting powerdown, it is best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting T89C5115 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. Register Table 45. WDTPRG Register WDTPRG (S:A7h) WatchDog Timer Duration Programming Register Reset Value = xxxx x000b 76543210 - - - - - S2 S1 S0 Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2S 2 WatchDog Timer Duration selection bit 2 Work in conjunction with bit 1 and bit 0. 1S 1 WatchDog Timer Duration selection bit 1 Work in conjunction with bit 2 and bit 0. 0S 0 WatchDog Timer Duration selection bit 0 Work in conjunction with bit 1 and bit 2.

Table 46. WDTRST Register sequence without instruction between these two sequences.

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4128A–8051–04/02 Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules. Its clock input can be programmed to count any of the following signals: PCA clock frequency/6 (see “clock” section) PCA clock frequency/2 T i m e r 0 o v e r f l o w External input on ECI (P1.2) Each compare/capture modules can be programmed in any one of the following modes: rising and/or falling edge capture, software timer, high-speed output, pulse width modulator. When the compare/capture modules are programmed in capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt vector. The PCA timer/counter and compare/capture modules share Port 1 for external I/Os. T h e s ep i n sa r el i s t e db e l o w .I ft h ep o r ti sn o tu s e df o rt h eP C A ,i tc a ns t i l lb eu s e df o r standard I/O. PCA Timer The PCA timer is a common time base for all five modules (see Figure 9). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (see Table 8) and can be programmed to run at: 1/6 the PCA clock frequency. 1/2 the PCA clock frequency. the Timer 0 overflow. the input on the ECI pin (P1.2). PCA Component External I/O Pin 16-bit Counter P1.2/ECI 16-bit Module 0 P1.3/CEX0 16-bit Module 1 P1.4/CEX1

Figure 30. PCA Timer/Counter The CMOD register includes three additional bits associated with the PCA. The CIDL bit which allows the PCA to stop during idle mode. The WDTE bit which enables or disables the WatchDog function on module 4. CCON register to be set when the PCA timer overflows. The CR bit must be set to run the PCA. The PCA is shut off by clearing this bit. if the ECF bit in CMOD register is set. The CF bit can only be cleared by software.

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4128A–8051–04/02 PCA Modules Each one of the five compare/capture modules has six possible functions. It can perform: 16-bit Capture, positive-edge triggered 16-bit Capture, negative-edge triggered 16-bit Capture, both positive and negative-edge triggered 16-bit Software Timer 16-bit High Speed Output 8-bit Pulse Width Modulator. Each module in the PCA has a special function register associated with it (CCAPM0 for module 0 ...). The CCAPM0:1 registers contain the bits that control the mode that each module will operate in. The ECCF bit enables the CCF flag in the CCON register to generate an interrupt when a match or compare occurs in the associated module. The PWM bit enables the pulse width modulation mode. The TOG bit when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module’s capture/compare register. The match bit MAT when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module’s capture/compare register. The two bits CAPN and CAPP in CCAPMn register determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled. The bit ECOM in CCAPM register when set enables the comparator function.

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SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set. Figure 33. PCA 16-bit Software Timer and High Speed Output Mode For software Timer mode, set ECOMn and MATn. For high speed output mode, set ECOMn, MATn and TOGn.

each time a match occurs between the PCA counter and the module’s capture registers. Figure 34. PCA High Speed Output Mode

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Figure 35. PCA PWM Mode

4128A–8051–04/02 PCA Registers Table 47. CMOD Register CMOD (S:D9h) PCA Counter Mode Register Reset Value = 00XX X000b 76543210 CIDL WDTE - - - CPS1 CPS0 ECF Bit Number Bit Mnemonic Description 7C I D L PCA Counter Idle Control bit C l e a rt ol e tt h eP C Ar u nd u r i n gI d l em o d e . S e tt os t o pt h eP C Aw h e nI d l em o d ei si n v o k e d . 6W D T E WatchDog Timer Enable Clear to disable WatchDog Timer function on PCA Module 4, Set to enable it. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2C P S 1 EWC Count Pulse Select bits CPS1 CPS0 Clock Source 0 0 Internal Clock, FPca/6 0 1 Internal Clock, FPca/2 1 0 Timer 0 overflow 1 1 External clock at ECI/P1.2 pin (Max. Rate = FPca/4) 1C P S 0 0E C F Enable PCA Counter Overflow Interrupt bit Clear to disable CF bit in CCON register to generate an interrupt. Set to enable CF bit in CCON register to generate an interrupt.

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Table 48. CCON Register interrupt request if the ECF bit in CMOD register is set. Must be cleared by software. Clear to turn the PCA Timer/Counter off. Set to turn the PCA Timer/Counter on. The value read from these bist are indeterminate. Do not set these bits. interrupt request if the ECCF 1 bit in CCAPM 1 register is set. Must be cleared by software. interrupt request if the ECCF 0 bit in CCAPM 0 register is set. Must be cleared by software.

Table 49. CCAPnH Registers Table 50. CCAPnL Registers

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Table 51. CCAPMn Registers The Value read from this bit is indeterminate. Do not set this bit. Clear to disable the Compare function. Set to enable the Compare function. output, the Pulse Width Modulator (PWM) and the WatchDog Timer (WDT).

5 CAPPn

Clear to disable the Capture function triggered by a positive edge on CEXx pin. Clear to disable the Capture function triggered by a negative edge on CEXx pin. Set to enable the Capture function triggered by a negative edge on CEXx pin. CCFx bit in CCON register, flagging an interrupt. The toggle mode is configured by setting ECOMx, MATx and TOGx bits.

0 ECCFn

Clear to disable CCFx bit in CCON register to generate an interrupt request. Set to enable CCFx bit in CCON register to generate an interrupt request.

Table 52. CH Register Table 53. CL Register

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4128A–8051–04/02 Analog-to-Digital Converter (ADC) This section describes the on-chip 10-bit analog-to-digital converter of the T89C5115. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC chan- nels as ADC input voltage (ADCIN). ADCIN is converted by the 10 bit-cascaded potentiometric ADC. Two kind of conversion are available: - Standard conversion (8 bits). - Precision conversion (10 bits). For the precision conversion, set bit PSIDLE in ADCON register and start conversion. The device is in a pseudo-idle mode, the CPU does not run but the peripherals are always running. This mode allows digital noise to be as low as possible, to ensure high precision conversion. For this mode it is necessary to work with end of conversion interrupt, which is the only way to wake the device up. If another interrupt occurs during the precision conversion, it will be treated only after this conversion is ended. Features 8 channels with multiplexed inputs 10-bit cascaded potentiometric ADC Conversion time 16 micro-seconds (typ.) Zero Error (offset) ± 2 LSB max Positive External Reference Voltage Range (VREF) 2.4V to 3.0V (typ.) ADCIN Range 0V to 3V Integral non-linearity typical 1 LSB, max. 2 LSB Differential non-linearity typical 0.5 LSB, max. 1 LSB Conversion Complete Flag or Conversion Complete Interrupt Selectable ADC Clock ADC Port1 I/O Functions Port 1 pins are general I/O that are shared with the ADC channels. The channel select bit in ADCF register define which ADC channel/port1 pin will be used as ADCIN. The remaining ADC channels/port1 pins can be used as general-purpose I/O or as the alter- nate function that is available. A conversion launched on a channel which are not selected on ADCF register will not have any effect.

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Table 54. Selected Analog Input 3FFh if greater than VAREF and 000h if less than VAGND. Clock Selection The ADC clock is the same as CPU. to generate the ADC clock from the oscillator frequency. Figure 38. A/D Converter Clock in ADCON register. In this mode its power dissipation is about 1 uW.

000 A N 0

001 A N 1

010 A N 2

011 A N 3

100 A N 4

101 A N 5

110 A N 6

111 A N 7

EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software. Figure 39. ADC interrupt structure

Start a standard conversion
Start a precision conversion (need interrupt ADC)

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Table 56. ADCON Register Set to use P1.x as ADC input. Clear to use P1.x as standart I/O port.

6 PSIDLE

Clear to convert without idle mode. Clear for Standby mode (power dissipation 1 uW). Must be cleared by software.

3 ADSST

Set to start an A/D conversion.

Table 57. ADCLK Register Table 58. ADDH Register Table 59. ADDL Register The value read from these bits are indeterminate. Do not set these bits. The value read from these bits are indeterminate. Do not set these bits.

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ADC. These interrupts are shown below. Figure 40. Interrupt Control System which must be cleared to disable all the interrupts at the same time. bit values and priority levels associated with each combination.

Table 60. Priority Level Bit Values determined by the polling sequence, see Table 61. Table 61. Interrupt Priority Within Level

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4128A–8051–04/02 Registers Table 62. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register Reset Value = 0000 0000b bit addressable 76543210 EA EC ET2 ES ET1 EX1 ET0 EX0 Bit Number Bit Mnemonic Description 7E A Enable All interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. 6E C PCA Interrupt Enable Clear to disable the PCA interrupt. Set to enable the PCA interrupt. 5E T 2 Timer 2 overflow interrupt Enable bit Clear to disable Timer 2 overflow interrupt. Set to enable Timer 2 overflow interrupt. 4E S Serial port Enable bit Clear to disable serial port interrupt. Set to enable serial port interrupt. 3E T 1 Timer 1 overflow interrupt Enable bit Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. 2E X 1 External interrupt 1 Enable bit Clear to disable external interrupt 1. Set to enable external interrupt 1. 1E T 0 Timer 0 overflow interrupt Enable bit Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. 0E X 0 External interrupt 0 Enable bit Clear to disable external interrupt 0. Set to enable external interrupt 0.

Table 63. IEN1 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.

1 EADC

Clear to disable the ADC interrupt. Set to enable the ADC interrupt. The value read from this bit is indeterminate. Do not set this bit.

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Table 64. IPL0 Register The value read from this bit is indeterminate. Do not set this bit.

6 PPC PCA Interrupt Priority bit

Refer to PPCH for priority level. Refer to PT2H for priority level. R e f e rt oP S Hf o rp r i o r i t yl e v e l . Refer to PT1H for priority level. Refer to PX1H for priority level. Refer to PT0H for priority level. Refer to PX0H for priority level.

Table 65. IPL1 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. 1 PADCL ADC Interrupt Priority level less significant bit. Refer to PSPIH for priority level. The value read from this bit is indeterminate. Do not set this bit.

90 T89C5115

Table 66. IPL0 Register The value read from this bit is indeterminate. Do not set this bit.

6 PPCH

00 L o w e s t

4 PSH

Table 67. IPH1 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.

1 PADCH

The value read from this bit is indeterminate. Do not set this bit.

92 T89C5115

4128A–8051–04/02

Electrical Characteristics

DC Parameters for Standard Voltage TA =- 4 0°Ct o+ 8 5°C; VSS =0 V ; V CC =5 V ± 10%; F = 0 to 40 MHz Notes: 1. Operating I CC is measured with all output pins disconnected; XTAL1 driven with T CLCH,T CHCL = 5 ns (see Figure 44.), V IL = 2. Idle I CC is measured with all output pins disconnected; XTAL1 driven with T CLCH,T CHCL =5n s ,V IL =V SS +0 . 5 V ,VIH =V CC - 0.5V; XTAL2 N.C; Port 0 = VCC;R S T=V SS (see Figure 42.). 3. Power-down I CC is measured with all output pins disconnected; XTAL2 NC.; RST = V SS (see Figure 43.). In addition, the WDT must be inactive and the POF flag must be set. 4. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature. Ambiant T emperature Under Bias: Note: Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. The power dissipation is based on the maximum allowable die temperature and the thermal resistance of the package. Table 68. DC Parameters in Standard Voltage

94 T89C5115

Figure 44. Clock Signal Waveform for I CC Tests in Active and Idle Modes Table 69. DC Parameters for AD Converter in Precision conversion Note: 1. Typicals are based on a limited number of samples and are not guaranteed.

AVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. Table 70 and Table 74 give the description of each AC symbols. Table 71, Table 72 and Table 73 give for each range the AC parameter. LLIV and 20 MHz, Standard clock. Table 70. Symbol Description (F = 40 MHz) Table 71. AC Parameters for a Fix Clock (F = 40 MHz)

96 T89C5115

Table 72. AC Parameters for a Variable Clock Table 73. AC Parameters AC inputs during testing are driven at V CC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at V IH min for a logic “1” and VIL max for a logic “0”.

Figure 45. Flash Memory - Internal Busy Waveforms

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4128A–8051–04/02

Ordering Information

Table 75. Possible Order Entries

4128A–8051–04/02 Package Drawing PLCC28

100 T89C5115

4128A–8051–04/02 Package Drawing SOIC28

4128A–8051–04/02 Package Drawing VQFP32

i T89C5115 4128A–8051–04/02 Table of Contents

4128A–8051–04/02

P r i n t e do nr e c y c l e dp a p e r . ATMEL®, is a registered trademarkof Atmel. Other terms and product names may be the trademarks of others. © Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. Atmel Headquarters Atmel Operations Corporate Headquarters

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Product Information

T89C5115 specifications and overview.

Summary

Low Pin Count 8-bit MCU with A/D Converter and 16-Kbytes of Flash Memory

Description

The T89C5115 is a high performance Flash version ofthe 80C51 single chip 8-bit microcontrollers. It contains a 16-KB Flash memory blockfor program and data.

Source title T89C5115 Datasheet(PDF) - ATMEL Corporation

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