T87C5101 TEMIC | Alldatasheet
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Rev. E - 29 February 2000 1 T87C5101 T83C5101/02 8-bit Low pin count Microcontrollers, 0-66 MHz 1. Description TEMIC T8xC5101/02 family is a high performance CMOS ROM, OTP, EPROM derivative of the 80C51 CMOS single chip 8-bit microcontroller. The T8xC5101/02 family is a low pin count device where only Port 1, port 3 and 2/6 bits of a new port 4 are outputted. This prevents to do any external access, like external program memory access (fetch, MOVC) or external data memory (MOVX) The T8xC5101/02 family retains all features of the TEMIC 80C51 with extended capacity 8Kb ROM (5102), 16Kb ROM (5101) / 16Kb EPROM/OTP (5101) , 256 bytes of internal RAM, a 6-source, 4-level interrupt system, an on-chip oscillator and three timer/counters. In addition, the T8xC5101/02 family has an XRAM of 256 bytes, the X2 feature, a more versatile serial channel that facilitates multiprocessor communication (EUART), a dual data pointer and an improved timer 2. The fully static design of the T8xC5101/02 family allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The T8xC5101/02 family has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. 2. Features
- 80C51 code Compatible
- 8051 instruction compatible
- 16 I/O + 2 Outputs in 24 pin packages
16 I/O + 6 Outputs in 28 pin packages
- Three 16-bit timer/counters
- 256 bytes scratchpad RAM
- Program Memory
- 8Kb ROM T83C5102
- 16Kb ROM T83C5101
- 16Kb EPROM/OTP T87C5101
- High-Speed Architecture
- 40 MHz from 2.7 to 5.5V, commercial or industrial temperature range : - 40 MHz with a 40 MHz crystal in std mode - 40 MHz with a 20 MHz crystal in X2 mode
- 66 MHz from 4.5 to 5.5V, commercial temperature range - 40MHz with a 40 MHz crystal in std mode - 66MHz with a 33MHz crystal in X2 mode
- Dual Data Pointer
- On-chip eXpanded RAM (XRAM) (256 bytes)
- Programmable Clock Out and Up/Down Timer/ Counter 2
- Asynchronous port reset
- Interrupt Structure with
- 6 Interrupt sources,
- 4 level priority interrupt system
- Full duplex Enhanced UART
- Framing error detection
- Automatic address recognition
- Low EMI (no ALE)
- Power Control modes
- Idle mode
- Power-down mode
- Packages: SO24, DIL24, TSSOP24*, SO28* * check for availability
2 Rev. E - 29 February 2000 T87C5101 T83C5101/02 3. Block Diagram Timer 0 INT RAM 256x8 RxD TxD V PP TEST XTAL2 XTAL1 EUART CPU Timer 1 INT1 CtrlINT0 C51 CORE (2) (2) (2) (2) Port 1Port 4Port 3 Parallel I/O PortsP1 XRAM 256x8 IB-bus RESET PROG Vss Vcc (2)(2) (1): Alternate function of Port 1 (2): Alternate function of Port 3 Timer2 T2EX (1) (1) ROM /EPROM 16Kx8 (3) (3) (3): Multiplexed function of Port 4.
- C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
- I/O port registers: P1, P3, P4
- Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H
- Serial I/O port registers: SADDR, SADEN, SBUF, SCON
- Power and clock control registers: PCON
- Interrupt system registers: IE, IP, IPH
- Others: AUXR, CKCON No write must be made to reserved areas. Reading a reserved area will give indeterminate result.
Table 1. All SFRs with their address and their reset value
4 Rev. E - 29 February 2000 T87C5101 T83C5101/02 5. T8xC5101/02Pin Configuration P4.1 / Test P3.0 RST XTAL2 XTAL1 P3.1 Vpp P4.0 / Prog Vss P1.6 P1.4 P1.5 P1.3 P1.1 / T2EX P1.0 / T2 P1.2 P3.4 / T0 P3.2 /INT0 P3.3 /INT1 Vcc P3.5 / T1 P3.6 P3.7 P1.7DIL24 SSOP24* * Check for availability SO24 P4.1 / Test P3.0 RST XTAL2 XTAL1 P3.1 Vpp P4.0 / Prog Vss P1.6 P1.4 P1.5 P1.3 P1.1 / T2EX P1.0 / T2 P1.2 P3.4 / T0 P3.2 /INT0 P3.3 /INT1 Vcc P3.5 / T1 P3.6 P3.7 P1.7 * Check for availability SO28*P4.3 7 P4.4 14 15 P4.5 P4.2
Table 2. Pin Description for 24 and 28 pin packages address byte during memory programming and verification. especially during reset. These two pins are primarily designed to drive LEDs. in the corresponding chapter. the output: 1 if the output is 1, 0 if the output is 0. low will source current because of the internal pull-ups. features of the 80C51 family, as listed below. using only an external capacitor to VCC. Vpp pin must be tied to Vcc.
6 Rev. E - 29 February 2000 T87C5101 T83C5101/02 6. Low Pin Count specificities The T8xC5101/02 family is not able to perform any external memory access, such as a code fetch, a look-up table access (using MOVC) or a data access (using MOVX) because traditional Port 0and Port 2 are not implemented anymore. It should be noted that 2 bits of a new port 4 are available, but they are pure user outputs. On the 28 pin package, there is also a set of 4 extra I/Os, which cannot be used for external access. This inability to perform external memory accesses has the following consequences:
- Port 0 SFR doesn’t exist any more
- Port 2 SFR doesn’t exist any more
- Port 4 has six bits defined among which two are pure outputs for LED driving.
- Security level 4 is no longer applicable
- Code memory addresses is limited to 4000h. Accessing to any address above 3FFFh will return indeterminate value. Jumps, subroutine Calls, MOVC instructions should be limited to a maximum address range of 3FFFh to avoid any error.
- External data memory addresses is limited to 100h. Writing to any address above FFh will have no effect. Reading any address above FFh will return indeterminate value. To avoid any mistake, MOVX address should be limited to a maximum address range of FFh.
- In Rx devices, the user could disable the XRAM (for example, if he had shared resource at the corresponding address range). As no external access is possible with the T83/87C510x, it makes no sense to be able to disable accesses to XRAM. Nevertheless, access to AUXR bit 1 will cause no error and any write to this bit will have no effect.
- As there is no external access, EA, ALE, PSEN, RD and WR signals are not implemented. So, the corresponding pins or alternate functions are removed.
- As there is no ALE, there is no need for ALE disabling. Nevertheless, access to AUXR bit 0 will cause no error and any write to this bit will have no effect.
- Compared to the corresponding 16 Kbyte Rx2 device, the TS80C51RB2, the following features are removed:
- Port 0 & 2
- PCA
- Watchdog
- ONCE mode
- Power Off Flag (POF)
- T8xC5101/02 Enhanced Features
- The X2 option.
- The Dual Data Pointer.
- The extended RAM.
- The 4 level interrupt priority system.
- Some enhanced features are also located in the UART and the timer 2.
7.1 X2 Feature
- Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
- Save power consumption while keeping same CPU power (oscillator power saving).
- Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.
- Increase CPU power by 2 while keeping same crystal frequency. In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by software.
7.1.1 Description
diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode. Figure 2. shows the mode switching waveforms. Figure 1. Clock Generation Diagram state machine: 6 clock cycles.
Figure 2. Mode Switching Waveforms using clock frequency as time reference (UART, timers, PCA...) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate.
Table 3. CKCON Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Clear to select 12 clock periods per machine cycle (STD mode, FOSC =FXTAL /2). Set to select 6 clock periods per machine cycle (X2 mode, FOSC =FXTAL ).
7.2 Dual Data Pointer Register Ddptr
DPS = AUXR1/bit0 (See Table 4.) that allows the program code to switch between them (Refer to Figure 3). Figure 3. Use of Dual Pointer Table 4. AUXR1: Auxiliary Register 1 pointer and the other one as a "destination" pointer. value will be 1. The value read from a reserved bit is indeterminate. b. GF3 will not be available on first version of the RC devices.
0 DPTR0 Selected
1 DPTR1 Selected
Rev. E - 29 February 2000 11 T87C5101 T83C5101/02 ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added 00A2 AUXR1 EQU 0A2H 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6 JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.
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7.3 Expanded RAM (XRAM)
The T8xC5101/02 provide 256 additional Bytes of random access memory (RAM) space for increased data parameter handling and high level language usage. The T8xC5101/02 have internal data memory that is mapped into four separate segments. The four segments are:
- 1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable.
- 2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only.
- 3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable only.
- 4. The expanded RAM bytes are indirectly accessed by MOVX instructions. As external accesses are not possible on the T8xC5101/02 family, it makes no sense to have the possibility to disable accesses to XRAM. That’s why, compared to TS80C51RB2, writing a 1 in AUXR register bit 1 will have no effect, and won’t disable access to the XRAM. The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction.
- Instructions that use direct addressing access SFR space.For example: MOV 0A0H, # data, accesses the SFR at location 0B0H (which is P3).
- Instructions that use indirect addressing access the Upper 128 bytes of data RAM.For example: MOV @R0, # datawhere R0 contains 0B0H, accesses the data byte at address 0B0H, rather than P3 (which address is 0B0H).
- The 256 XRAM bytes can be accessed by indirect addressing, with MOVX instructions. This part of memory which is physically located on-chip, logically occupies the first 256 bytes of external data memory.
- The XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR.An access to XRAM will not affect any ports. A write to external data memory locations higher than FFH (i.e. 0100H to FFFFH) will have no effect. A read will return an indeterminate value. The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the XRAM.
Figure 4. Internal and External Data Memory Address Table 5. Auxiliary RegisterAUXR its active value will be 1. The value read from a reserved bit is indeterminate.
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7.4 Timer 2
The timer 2 in the T8xC5101/02 family is compatible with the timer 2 in the 80C52. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in cascade. It is controlled by T2CON register (See Table 6) and T2MOD register (See Table 7). Timer 2 operation is similar to Timer 0 and Timer 1. C/ T2 selects FOSC /12 (timer operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input. Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON), as described in the TEMIC 8-bit Microcontroller Hardware description. Refer to the TEMIC 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate Generator Modes. In T8xC5101/02 Timer 2 includes the following enhancements:
- Auto-reload mode with up or down counter
- Programmable clock-output
7.4.1 Auto-Reload Mode
The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the TEMIC 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in Figure 5. In this mode the T2EX pin controls the direction of count. When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution.
Figure 5. Auto-Reload Mode Up/Down Counter (DCEN = 1)
7.4.2 Programmable Clock-Output
input clock increments TL2 at frequency FOSC /2. The timer repeatedly counts to overflow from a loaded value. OSC /216) to 4 MHz (FOSC /4) in X1 mode. The generated clock signal is brought out to T2 pin (P1.0).
- Set T2OE bit in T2MOD register.
- Clear C/T2 bit in T2CON register.
- Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers.
- Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different one depending on the application.
- To start the timer, set TR2 run control bit in T2CON register. (DOWN COUNTING RELOAD V ALUE) C/T2 TF2 TR2 EXF2 TH2 (8-bit) TL2 (8-bit) RCAP2H (8-bit) RCAP2L (8-bit) FFh (8-bit) FFh (8-bit) TOGGLE (UP COUNTING RELOAD V ALUE) TIMER 2 INTERRUPT XTAL1 :12 FOSCFXTAL T2CONreg T2CONreg T2CONreg T2CONreg T2EX: if DCEN=1, 1=UP if DCEN=1, 0=DOWN if DCEN = 0, up counting (:6 in X2 mode) Clock OutFrequency– F osc 2x2×
Figure 6. Clock-Out Mode C/
Table 6. T2CON Register
7 TF2
Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
6 EXF2
Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled.
5 RCLK
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
4 TCLK
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3 EXEN2
Clear to ignore events on T2EX pin for timer 2 operation.
2 TR2
1 C/T2#
Clear for timer operation (input from internal clock system: FOSC ). Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.
0 CP/RL2#
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1.
Table 7. T2MOD Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
1 T2OE
Clear to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output.
0 DCEN
Clear to disable timer 2 as up/down counter. Set to enable timer 2 as up/down counter.
7.5 T8xC5101/02 Serial I/O Port
can occur simultaneously and at different baud rates.
- Framing error detection
- Automatic address recognition
7.5.1 Framing Error Detection
bit error detection feature, set SMOD0 bit in PCON register (See Figure 7). Figure 7. Framing Error Block Diagram is not found, the Framing Error bit (FE) in SCON register (See Table 8.) bit is set.
RI rises on stop bit instead of the last data bit (See Figure 8. and Figure 9.). Figure 8. UART Timings in Mode 1 Figure 9. UART Timings in Modes 2 and 3
7.5.2 Automatic Address Recognition
(SM2 bit in SCON register is set). the CPU is not interrupted by command frames addressed to other devices. device’s address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address. register in mode 0 has no effect).
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7.5.3 Given Address
Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be1111 1111b. For example: SADDR 0101 0110b SADEN11111100b Given 0101 01XXb The following is an example of how to use given addresses to address different slaves: Slave A: SADDR 1111 0001b SADEN11111010b Given 1111 0X0Xb Slave B: SADDR 1111 0011b SADEN11111001b Given 1111 0XX1b Slave C: SADDR 1111 0010b SADEN11111101b Given 1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g.1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g.1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g.1111 0001b).
7.5.4 Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.: SADDR 0101 0110b SADEN 1111 1100b Broadcast =SADDR OR SADEN 1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A: SADDR 1111 0001b SADEN11111010b Broadcast 1111 1X11b, Slave B: SADDR 1111 0011b SADEN11111001b Broadcast 1111 1X11B, Slave C: SADDR= 1111 0010b SADEN11111101b Broadcast 1111 1111b For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh.
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7.5.5 Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses areXXXX XXXXb(all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. SADEN - Slave Address Mask Register (B9h) Reset Value = 0000 0000b Not bit addressable SADDR - Slave Address Register (A9h) Reset Value = 0000 0000b Not bit addressable 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Table 8. SCON Register Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. Refer to SM1 for serial port mode selection.
6 SM1
5 SM2
Clear to disable multiprocessor communication feature.
4 REN
Clear to disable serial reception. Set to enable serial reception.
3 TB8
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3. Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit.
2 RB8
Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used. Clear to acknowledge interrupt. Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 8. and Figure 9. in the other modes.
Table 9. PCON Register Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit.
7 SMOD1 Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6 SMOD0
Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. The value read from this bit is indeterminate. Do not set this bit.
4 POF
Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.
3 GF1
Cleared by user for general purpose usage. Set by user for general purpose usage.
2 GF0
Cleared by user for general purpose usage. Set by user for general purpose usage. Cleared by hardware when reset occurs. Set to enter power-down mode.
0 IDL
Clear by hardware when interrupt or reset occurs.
7.6 Interrupt System
of the interrupt vectors are the same as in the standard C52. Figure 10. Interrupt Control System a bit in the Interrupt Priority register (See Table 12.) and in the Interrupt Priority High register (See Table 13.). shows the bit values and priority levels associated with each combination. Table 10. Priority Level Bit Values
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. Table 11. IE Register Clear to disable all interrupts. Set to enable all interrupts. The value read from this bit is indeterminate. Do not set this bit.
5 ET2
Clear to disable timer 2 overflow interrupt. Set to enable timer 2 overflow interrupt. Clear to disable serial port interrupt. Set to enable serial port interrupt.
3 ET1
Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt.
2 EX1
Clear to disable external interrupt 1. Set to enable external interrupt 1.
1 ET0
Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt.
0 EX0
Clear to disable external interrupt 0. Set to enable external interrupt 0.
Table 12. IP Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
5 PT2 Timer 2 overflow interrupt Priority bit
Refer to PT2H for priority level.
4 PS Serial port Priority bit
Refer to PSH for priority level.
3 PT1 Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
2 PX1 External interrupt 1 Priority bit
Refer to PX1H for priority level.
1 PT0 Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
0 PX0 External interrupt 0 Priority bit
Refer to PX0H for priority level.
Table 13. IPH Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
5 PT2H
4 PSH
3 PT1H
2 PX1H
1 PT0H
0 PX0H
7.7 Idle mode
An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. at the time Idle was activated. be executed will be the one following the instruction that put the device into idle. terminated by an interrupt, the interrupt service routine can examine the flag bits. the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset.
7.8 Power-Down Mode
To save maximum power, a power-down mode can be invoked by software (Refer to Table 9., PCON register). instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated. is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. and configured as level or edge sensitive interrupt input. Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 11. that put T8xC5101/02 into power-down mode. Figure 11. Power-Down Exit Waveform Exit from power-down by either reset or external interrupt does not affect the internal RAM content. PD and IDL bits are cleared and idle mode is not entered.
Table 14. The state of ports during idle and power-down modes
7.9 Reduced EMI mode
EXTRAM, writing any value to AO will have no effect on the device behavior. Table 15. AUXR Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
1 EXTRAM EXTRAM bit
Writing to this bit will have no effect. The value read from this bit is indeterminate.
0 AO ALE Output bit
Writing to this bit will have no effect. The value read from this bit is indeterminate.
8.1 ROM Structure
- the code array
8.2 ROM Lock System
The program Lock system, when programmed, protects the on-chip program against software piracy.
8.2.1 Encryption Array
state, will return the code in its original, unmodified form. should be programmed with random values.
8.2.2 Program Lock Bits
8.2.3 Signature bytes
Table 16. Program Lock bits
2 P U U Not applicable as usually this protection deals with executing MOVC from external memory
3 U P U
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8.2.4 Verify Algorithm
Refer to section Table 9.3.5
9.1 EPROM Structure
9.2 EPROM Lock System
The program Lock system, when programmed, protects the on-chip program against software piracy.
9.2.1 Encryption Array
the encryption array in the unprogrammed state, will return the code in its original, unmodified form. should be programmed with random values.
9.2.2 Program Lock Bits
WARNING: Security level 2 and higher should only be programmed after EPROM verification.
9.2.3 Signature bytes
Table 17. Program Lock bits 2 P U U Further programming of the program memory is disabled. 3 U P U Same as security level 2 + verify disabled.
4 U U P Not applicable as usually this protection deals with external execution, which is impos-
9.3 EPROM Programming
9.3.1 Set-up modes
Control and program signals must be held at the levels indicated in Table 18.
9.3.2 Definition of terms
Table 18. EPROM Set-Up Modes Figure 12. Programming and Verifying Modes Configuration
9.3.3 EPROM Programming and Verification Characteristics
9.3.4 Programming Algorithm
- step 1: Vpp and TEST low, present T code for programming on P3 and raise Vpp to 12.75V
- step 2: present Address High on P3 and pulse TEST high
- step 3: present address Low on P3 and data on P1
- step 4: pulse PROG low
- step 5: back to step 3 if the next byte to program is in the same 256 byte page OR
- step 5: back to step 2 if the next byte to program is in a different page
Figure 13. Programming signals’waveform Table 19. EPROM Programming Parameters
9.3.5 Verifying algorithm
- step 1: Vpp and TEST low, present T code for verification on P3 and Raise Vpp to Vcc
- step 2: present address High and pulse TEST high
- step 3: present address Low on P3 and read data on P1
- step 4: back to step 3 if the next byte is in the same 256 byte page OR
- step 4: back to step 2 if the next byte to program is in a different page
Figure 14. Verifying signals’waveform
12 MHz
38 Rev. E - 29 February 2000 T87C5101 T83C5101/02
9.3.6 Programming / Verify Algorithm
- step 1: Vpp and TEST low, present T code for programming on P3 and raise Vpp to 12.75V
- step 2: present Address High on P3 and pulse TEST high
- step 3: present address Low on P3 and data on P1
- step 4: pulse PROG low
- step 5: present T code for verifying on P3 and lower Vpp to 0V
- step 6: read previous data
- step 7: present T code for programming on P3 and raise Vpp to 12.75V
- step 8: goto step 3 if the next byte to program is in the same 256 byte page OR
- step 8: goto step 2 if the next byte to program is in a different page
Symbol Parameter Formula Min Max Unit tOSC Oscillator period 83.3 ns tCVPX Code input Valid to Vpp rising edge setup time 36 tOSC 3 µs tPHCX Code input valid from Vpp High hold time 1 tOSC 83.3 ns tPHTX Test input valid from Vpp High hold time 1 tOSC 83.3 ns tTHTX Test High pulse width 36 tOSC 3 µs tCVTX Address high Valid to Test falling edge setup time 36 tOSC 3 µs tTLCX Address input Valid from Test falling edge hold time 1 tOSC 83.3 ns tCVDV Address Valid to Data output Valid delay 36 tOSC 3 µs tCXDX Data valid from Address Invalid hold time 0
Figure 15. Programming / Verifying signals’waveform the device outputs directly the last written data.
9.3.7 Lock bits programmation and verification
9.3.7.1 Programmation :
- step 1: Vpp and TEST low, present T code for Lock bits programming on P3 and raise Vpp to 12.75V
- step 2: pulse PROG low
9.3.7.2 Verification :
- step 1 : Vpp and TEST low, present T code for Lock bits verification
- step 2 : read data
Figure 16. Lock bits programming signals’waveform and Lock bits verifying signals’waveform
- Vpp pin in driven : -to 0V when P3 contains the test code
- Test pin is driven : -to 5V when P3 contains high order address -to 0V in the other cases
9.4 EPROM Erasure (Windowed Packages Only)
Erasure leaves all the EPROM cells in a 1’s state (FF).
9.4.1 Erasure Characteristics
of about 25 mm, should be sufficient. An exposure of 1 hour is recommended with most of standard erasers. label be placed over the window.
9.5 Signature Bytes
9.5.1 Signature bytes content
- shows the content of the signature byte for the T8xC5101/02.
Table 20. Signature Bytes Content
42 Rev. E - 29 February 2000 T87C5101 T83C5101/02 10. Electrical Characteristics
10.1 Absolute Maximum Ratings(1)
Ambiant Temperature Under Bias: C = commercial 0 °Ct o7 0°C I = industrial -40 °Ct o8 5°C Storage Temperature -65 °Ct o+1 5 0°C Voltage on VCC to VSS - 0 . 5Vt o+7V Voltage on VPP to VSS - 0 . 5Vt o+1 3V Voltage on Any Pin to VSS - 0 . 5Vt oVCC + 0.5 V Power Dissipation 1 W (2) NOTES 1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. 2. This value is based on the maximum allowable die temperature and the thermal resistance of the package.
10.2 Power consumption measurement
Since the introduction of the first C51 devices, every manufacturer made operating Icc measurements under reset, which made sense for the designs were the CPU was running under reset. In TEMIC new devices, the CPU is no more active during reset, so the power consumption is very low but is not really representative of what will happen in the customer system. That’s why, while keeping measurements under Reset, TEMIC presents a new way to measure the operating Icc: Using an internal test ROM, the following code is executed: Label: SJMP Label (80 FE) Ports 1, 3, 4 are disconnected, RST = Vss, XTAL2 is not connected and XTAL1 is driven by the clock. This is much more representative of the real operating Icc.
10.3 DC Parameters for Standard Voltage
Table 21. DC Parameters in Standard Voltage
10.4 DC Parameters for Low Voltage
Table 22. DC Parameters for Low Voltage
- I CC under reset is measured with all output pins disconnected; XTAL1 driven with TCLCH , TCHCL = 5 ns (see Figure 21.), VIL = VSS + 0.5 V ,
- Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH ,TCHCL = 5 ns, VIL =V SS + 0.5 V , VIH =V CC - 0.5 V; XTAL2
N.C; Vpp = RST = VSS (see Figure 19.).
- Power Down I CC is measured with all output pins disconnected; Vpp = VSS; XTAL2 NC.; RST = VSS (see Figure 20).
- Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V .
0.15 Freq
- Under steady state (non-transient) conditions, IOL must be externally limited as follows:
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
- For other values, please contact your sales office.
- Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH , TCHCL = 5 ns (see Figure 21.), VIL = VSS + 0.5 V ,
a crystal oscillator is used. Measurements are made with OTP products when possible, which is the worst case. Figure 17. ICC Test Condition, under reset All other pins are disconnected.
10.5 AC Parameters
10.5.1 Explanation of the AC Symbols
a list of all the characters and what they stand for. XHDV = Time from clock rising edge to input data valid. TA =0t o+ 7 0°C (commercial temperature range); VSS =0V ;V CC =5V ± 10%; -V ranges. TA =0t o+ 7 0°C (commercial temperature range); VSS =0V ;2 . 7V<V CC < 5.5 V; -L range. TA = -40°Ct o+ 8 5°C (industrial temperature range); VSS =0V ;2 . 7V<V CC < 5.5 V; -L range. Table 23. gives the maximum applicable load capacitance for Port 1, 3 and 4. Timings will be guaranteed if these capacitances are respected. Higher capacitance values can be used, but timings will then be degraded. Table 23. Load Capacitance versus speed range, in pF Table 25. gives the description of each AC symbols. Table 26. gives for each range the AC parameter. Table 27. gives the frequency derating formula of the AC parameter. To calculate each AC symbols, take the x Table 24. Max frequency for derating formula regarding the speed grade
10.5.2 Serial Port Timing - Shift Register Mode
Table 26. AC Parameters for a Fix Clock Table 27. AC Parameters for a Variable Clock: derating formula Table 25. Symbol Description
33 MHz
40 MHz
20 MHz
10.5.3 Shift Register Timing Waveforms
Figure 22. Shift Register Timing Waveforms
10.5.4 External Clock Drive Characteristics (XTAL1)
10.5.5 External Clock Drive Waveforms
Figure 23. External Clock Drive Waveforms Table 28. AC Parameters
10.5.6 AC Testing Input/Output Waveforms
Figure 24. AC Testing Input/Output Waveforms are made at VIH min for a logic “1” and VIL max for a logic “0”.
10.5.7 Float Waveforms
Figure 25. Float Waveforms to float when a 100 mV change from the loaded VOH /VOL level occurs. IOL /IOH ≥± 20mA.
10.5.8 Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two. Figure 26. Clock Waveforms are incorporated in the AC specifications.
Table 29. Maximum Clock Frequency
40 MHz, X1 mode
33 MHz, X2 mode
20 MHz, X2 mode
Table 30. Possible order entries