T83C5101_03 ATMEL | Alldatasheet
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Technical content
Features
80C51 Code Compatible – 8051 Instruction Compatible – 16 I/O + 2 Outputs in 24 Pin Packages
16 I/O + 6 Outputs in 28 Pin Packages
– Three 16-bit Timer/Counters – 256 Bytes Scratchpad RAM Program Memory – 8 KB ROM T83C5102 – 16 KB ROM T83C5101 – 16 KB EPROM/OTP T87C5101 High-speed Architecture 40 MHz from 2.7 to 5.5V, Commercial or Industrial Temperature Range: – 40 MHz with a 40 MHz Crystal In Std. Mode – 40 MHz with a 20 MHz Crystal In X2 Mode 66 MHz from 4.5 to 5.5V, Commercial Temperature Range – 40 MHz with a 40 MHz Crystal in Std. Mode – 66 MHz with a 33 MHz Crystal in X2 Mode Dual Data Pointer On-chip eXpanded RAM (XRAM) (256 bytes) Programmable Clock Out and Up/Down Timer/Counter 2 Asynchronous Port Reset Interrupt Structure with – 6 Interrupt Sources, – 4-Level Priority Interrupt System Full-duplex Enhanced UART – Framing Error Detection – Automatic Address Recognition Low EMI (no ALE) Power Control Modes – Idle Mode – Power-down Mode Packages: SO24, DIL24, SSOP24, SO28
Description
The T8xC5101/02 family is a high performance CMOS ROM, OTP , EPROM derivative of the 80C51 CMOS single chip 8-bit microcontroller. The T8xC5101/02 family is a low pin count device where only Port 1, port 3 and 2/6 bits of a new port 4 are outputted. This prevents any external access, like external pro- gram memory access (fetch, MOVC) or external data memory (MOVX). The T8xC5101/02 family retains all features of the 80C51 with extended capacity 8 KB ROM (5102), 16 KB ROM (5101)/16 KB EPROM/OTP (5101), 256 bytes of internal RAM, a 6-source, 4-level interrupt system, an on-chip oscillator and three timer/counters. In addition, the T8xC5101/02 family has an XRAM of 256 bytes, the X2 feature, a more versatile serial channel that facilitates multiprocessor communication (EUART), a dual data pointer and an improved timer 2. The fully static design of the T8xC5101/02 family allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The T8xC5101/02 family has 2 software-selectable modes of reduced activity for fur- ther reduction in power consumption. In idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In power-down mode the RAM is saved and all other functions are inoperative. 8-bit Low Pin Count Microcontrollers T83C5101 T87C5101 T83C5102
2 T8xC5101/02
4233G–8051–03/03 Block Diagram Timer 0 INT RAM 256x8 RxD TxD VPP TEST XTAL2 XTAL1 EUART CPU Timer 1 INT1 CtrlINT0 C51 CORE (2) (2) (2) (2) Port 1 Port 4 Port 3 Parallel I/O Ports XRAM 256x8 IB-bus RESET PROG Vss Vcc (2)(2) (1): Alternate function of Port 1 (2): Alternate function of Port 3 Timer2 T2EX (1) (1) ROM /EPROM 16Kx8 (3) (3) (3): Multiplexed function of Port 4.
4233G–8051–03/03 SFR Mapping The Special Function Registers (SFRs) of the T8xC5101/02 fall into the following categories: C51 core registers: ACC, B, DPH, DPL, PSW, SP , AUXR1 I/O port registers: P1, P3, P4 Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H Serial I/O port registers: SADDR, SADEN, SBUF, SCON Power and clock control registers: PCON Interrupt system registers: IE, IP , IPH Others: AUXR, CKCON No write must be made to reserved areas. Reading a reserved area will give indetermi- nate results.
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Table 1. All SFRs With Their Address and Rest Values
4233G–8051–03/03 T8xC5101/02 Pin Configuration Mnemonic Pin Number Type Name and Function24 pins pins VSS 12 14 I Ground: 0V reference VCC 24 28 I Power Supply: This is the power supply voltage for normal, idle and power-down operation P1.0-P1.7 13-20 15-20 22-23 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification. Alternate functions for Port 1 include: I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control P4.0 (Prog)-P4.1 (Test) O (I) O (I) Port 4 bits 0 & 1: Except during programming and verifying, these two bits are output port driving 30 micro Amps at high level and sinking 10 mA at low level (Vol < 1V). If they have 1s written to them, they output a high level and if they have 0 written to them, they output a low level. These 2 pins cannot be used as inputs. Users should take care to never externally drive these pins low, especially during reset. These two pins are primarily designed to drive LEDs. During programming and verifying, these two pins are used as input, as explained in the corresponding chapter. A Read or a Read/Modify/Write instruction to these bits will read the status of the output: 1 if the output is 1, 0 if the output is 0. P4.2-P4.5 NA I/O Port 4 bits 2 to 5: bidirectional I/O port with internal pull-ups. Port 4.2 to 4.5 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 4.2 to 4.5 pins that are externally pulled low will source current because of the internal pull-ups. P3.0-P3.7 5-1 23-21 5-1 26-24 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3 also serves the special features of the 80C51 family, as listed below. 5 5 I RxD (P3.0): Serial input port 4 4 O TxD (P3.1): Serial output port
33 I INT0
(P3.2): External interrupt 0 22 I INT1 (P3.3): External interrupt 1 P4.1/Test P3.0 RST XTAL2 XTAL1 P3.1 VPP P4.0/Prog Vss P1.6 P1.4 P1.5 P1.3 P1.1/T2EX P1.0/T2 P1.2 P3.4/T0 P3.2/INT0 P3.3/INT1 Vcc P3.5/T1 P3.6 P3.7 P1.7 DIL24 SSOP24* * Check for availability SO24 P4.1/Test P3.0 RST XTAL2 XTAL1 P3.1 VPP P4.0/Prog Vss P1.6 P1.4 P1.5 P1.3 P1.1/T2EX P1.0/T2 P1.2 P3.4/T0 P3.2/INT0 P3.3/INT1 Vcc P3.5/T1 P3.6 P3.7 P1.7 * Check for availability SO28* P4.3 7 P4.4 14 15 P4.5 P4.2
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4233G–8051–03/03 11 I T0 (P3.4): Timer 0 external input 23 26 I T1 (P3.5): Timer 1 external input 22 25 I/O No alternate function on this pin 21 24 I/O No alternate function on this pin Reset 9 10 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to V SS permits a power-on reset using only an external capacitor to VCC. VPP 66 I Programming Supply Voltage: This pin receives the 12.75V programming supply voltage (VPP) during EPROM programming. During normal operation, VPP pin must be tied to Vcc. XTAL1 11 12 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 10 11 O Crystal 2: Output from the inverting oscillator amplifier Mnemonic Pin Number Type Name and Function24 pins pins
4233G–8051–03/03 Low Pin Count Specificities The T8xC5101/02 family is not able to perform any external memory access, such as a code fetch, a look-up table access (using MOVC) or a data access (using MOVX) because traditional Port ×0 and Port 2 are not implemented. It should be noted that 2 bits of a new port 4 are available, but they are pure user outputs. On the 28 pin package, there is also a set of 4 extra I/Os, which cannot be used for external access. This inability to perform external memory accesses has the following consequences: Port 0 SFR doesn’t exist Port 2 SFR doesn’t exist Port 4 has six bits defined among which two are pure outputs for LED driving. Security level 4 is no longer applicable Code memory addresses is limited to 4000h. Accessing to any address above 3FFFh will return indeterminate value. Jumps, subroutine Calls, MOVC instructions should be limited to a maximum address range of 3FFFh to avoid any error. External data memory addresses is limited to 100h. Writing to any address above FFh will have no effect. Reading any address above FFh will return indeterminate value. To avoid any mistake, MOVX address should be limited to a maximum address range of FFh. In Rx devices, the user could disable the XRAM (for example, if he had shared resource at the corresponding address range). As no external access is possible with the T83/87C510x, it makes no sense to be able to disable accesses to XRAM. Nevertheless, access to AUXR bit 1 will cause no error and any write to this bit will have no effect. As there is no external access, EA, ALE, PSEN, RD and WR signals are not implemented. So, the corresponding pins or alternate functions are removed. As there is no ALE, there is no need for ALE disabling. Nevertheless, access to AUXR bit 0 will cause no error and any write to this bit will have no effect. Compared to the corresponding 16 KB Rx2 device, the TS80C51RB2, the following features are removed: – Port 0 & 2 – PCA – Watchdog – ONCE mode – Power Off Flag (POF)
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The 4 level interrupt priority system. Some enhanced features are also located in the UART and the timer 2. Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. Save power consumption while keeping same CPU power (oscillator power saving). Increase CPU power by 2 while keeping same crystal frequency. mode. Figure 2 shows the mode switching waveforms. Figure 1. Clock Generation Diagram state machine: 6 clock cycles.
Figure 2. Mode Switching Waveforms (STD mode). Setting this bit activates the X2 feature (X2 mode). with 4800 baud rate will have 9600 baud rate. Table 2. CKCON Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Set to select 6 clock periods per machine cycle (X2 mode, F OSC=FXTAL).
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gram code to switch between them (Refer to Figure 3). Figure 3. Use of Dual Pointer Table 3. AUXR1: Auxiliary Register 1
- GF3 will not be available on first version of the RC devices.
- Not implemented, reserved for future use.
4233G–8051–03/03 Application Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’ pointer and the other one as a "destina- tion" pointer. ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added 00A2 AUXR1 EQU 0A2H 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a par- ticular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.
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4233G–8051–03/03 Expanded RAM (XRAM) The T8xC5101/02 provide 256 additional Bytes of random access memory (RAM) space for increased data parameter handling and high level language usage. The T8xC5101/02 have internal data memory that is mapped into four separate segments. The four segments are: 1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable. 2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only. 3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable only. 4. The expanded RAM bytes are indirectly accessed by MOVX instructions. As external accesses are not possible on the T8xC5101/02 family, it makes no sense to have the possibility to disable accesses to XRAM. That ’s why, compared to TS80C51RB2, writing a 1 in AUXR register bit 1 will have no effect, and won ’t disable access to the XRAM. The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction. Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data, accesses the SFR at location 0B0H (which is P3). Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0, # data where R0 contains 0B0H, accesses the data byte at address 0B0H, rather than P3 (which address is 0B0H). The 256 XRAM bytes can be accessed by indirect addressing, with MOVX instructions. This part of memory which is physically located on-chip, logically occupies the first 256 bytes of external data memory. The XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to XRAM will not affect any ports. A write to external data memory locations higher than FFH (i.e. 0100H to FFFFH) will have no effect. A read will return an indeterminate value. The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the XRAM.
Figure 4. Internal and External Data Memory Address Table 4. Auxiliary Register - AUXR
- User software should not write 1s to reserved bits. These bits may be used in future 8051
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4233G–8051–03/03 Timer 2 The timer 2 in the T8xC5101/02 family is compatible with the timer 2 in the 80C52. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in cascade. It is controlled by T2CON register (See Table 5) and T2MOD register (See Table 6). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects F OSC/12 (timer operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input. Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON), as described in the Atmel 8-bit Microcontroller Hardware description. Refer to the Atmel 8-bit Microcontroller Hardware description for the description of Cap- ture and Baud Rate Generator Modes. In T8xC5101/02 Timer 2 includes the following enhancements: Auto-reload mode with up or down counter Programmable clock-output Auto-Reload Mode The auto-reload mode configures timer 2 as a 16-bit timer or event counter with auto- matic reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the Atmel 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in Figure 5. In this mode the T2EX pin controls the direction of count. When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. The EXF2 bit toggles when timer 2 overflows or underflows according to the the direc- tion of the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution.
Figure 5. Auto-Reload Mode Up/Down Counter (DCEN = 1) Set T2OE bit in T2MOD register. Clear C/T2 bit in T2CON register. reload value or a different one depending on the application. To start the timer, set TR2 run control bit in T2CON register.
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independent since both functions use the values in the RCAP2H and RCAP2L registers. Figure 6. Clock-Out Mode C/T2
Table 5. T2CON Register Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3. Clear to ignore events on T2EX pin for timer 2 operation. Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.
0 CP/RL2#
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1.
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Table 6. T2MOD Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Clear to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output.
0 DCEN
Clear to disable timer 2 as up/down counter. Set to enable timer 2 as up/down counter.
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Figure 9. UART Timings in Modes 2 and 3 nication feature is enabled (SM2 bit in SCON register is set). is not interrupted by command frames addressed to other devices. be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect). slaves at a time. The following example illustrates how a given address is formed.
4233G–8051–03/03 The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don ’t-care bit; for slaves B and C, bit 0 is a 1. To com- municate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b). Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.: SADDR 0101 0110b SADEN 1111 1100b Broadcast =SADDR OR SADEN1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A:SADDR1111 0001b SADEN1111 1010b Broadcast1111 1X11b, Slave B:SADDR1111 0011b SADEN1111 1001b Broadcast1111 1X11B, Slave C:SADDR=1111 0010b SADEN1111 1101b Broadcast1111 1111b For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition.
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Table 7. SADEN Register Table 8. SAADR Register
Table 9. SCON Register Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. Refer to SM1 for serial port mode selection. Clear to disable multiprocessor communication feature. Clear to disable serial reception. Set to enable serial reception. Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3. Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used. Clear to acknowledge interrupt. Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 8. and Figure 9. in the other modes.
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Table 10. PCON Register doesn’t affect the value of this bit. Set to select double baud rate in mode 1, 2 or 3. Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. The value read from this bit is indeterminate. Do not set this bit. Clear to recognize next reset type. Cleared by user for general purpose usage. Set by user for general purpose usage. Cleared by user for general purpose usage. Set by user for general purpose usage. Cleared by hardware when reset occurs. Set to enter power-down mode. Clear by hardware when interrupt or reset occurs.
Figure 10. Interrupt Control System global disable bit, which must be cleared to disable all interrupts at once. associated with each combination. Table 11. Priority Level Bit Values
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Table 12. IE Register Clear to disable all interrupts. Set to enable all interrupts. clearing its own interrupt enable bit. The value read from this bit is indeterminate. Do not set this bit. Clear to disable timer 2 overflow interrupt. Set to enable timer 2 overflow interrupt. Clear to disable serial port interrupt. Set to enable serial port interrupt. Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. Clear to disable external interrupt 1. Set to enable external interrupt 1. Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. Clear to disable external interrupt 0. Set to enable external interrupt 0.
Table 13. IP Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Refer to PT2H for priority level. Refer to PSH for priority level. Refer to PT1H for priority level. Refer to PX1H for priority level. Refer to PT0H for priority level. Refer to PX0H for priority level.
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Table 14. IPH Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
the logical states they had at the time Idle was activated. the instruction that put the device into idle. service routine can examine the flag bits. machine cycles (24 oscillator periods) to complete the reset. long enough for the oscillator to restart and stabilize. interrupt must be enabled and configured as level or edge sensitive interrupt input. one following the instruction that put T8xC5101/02 into power-down mode. Figure 11. Power-Down Exit Waveform interrupt does no affect the SFRs.
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Table 15. State of Ports During Idle and Power-down Modes
ALE. EMI are then reduced intrinsically. Table 16. AUXR Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
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during program verify, 6 address lines are used to select a byte of the encryption array. return the code in its original, unmodified form. tection for the on-chip code and data. and Section “Signature Bytes”. Table 17. Program Lock Bits encrypted by the encryption array if programmed.
2 P U U
3 U P U
verified thanks to another method.
the signature array: 4 bytes. of protection for the on-chip code and data. these bytes, perform the process described in section and . Table 18. Program Lock Bits encrypted by the encryption array if programmed. 2 P U U Further programming of the program memory is disabled. 3 U P U Same as security level 2 + verify disabled. execution, which is impossible with this device.
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is placed in specific test modes (See Figure 12.). Control and program signals must be held at the levels indicated in Table 19. Table 19. EPROM Set-Up Modes Figure 12. Programming and Verifying Modes Configuration
Figure 13. Programming Signals Waveform Table 20. EPROM Programming Parameters Table 21. Programming Algorithm Parameters
12 MHz
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Figure 14. Verifying Signals Waveform Table 21. Programming Algorithm Parameters (Continued)
Table 22. Verify Algorithm Parameters
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Figure 15. Programming/Verifying Signals Waveform when switching to verify, the device outputs directly the last written data. Table 23. Programming/Verifying Signnal’s Wavaform Parameters
Figure 16. Lock Bits Programming Signals Waveform and Lock Bits Verifying Signals Waveform Table 23. Programming/Verifying Signnal’s Wavaform Parameters (Continued) Table 24. Lock Bits Programming Signals Waveform and Lock Bits Verifying Signals
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ing the parts to full functionality. Erasure leaves all the EPROM cells in a 1’s state (FF). 12,000 µW/cm2 rating for 30 minutes, at a distance of about 25 mm, should be sufficient. An exposure of 1 hour is recommended with most of standard erasers. that an opaque label be placed over the window.
signature byte for the T8xC5101/02. Table 25. Signature Bytes Content
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4233G–8051–03/03
Electrical Characteristics
Since the introduction of the first C51 devices, every manufacturer made operating Icc measurements under reset, which made sense for the designs were the CPU was run- ning under reset. In Atmel new devices, the CPU is no more active during reset, so the power consumption is very low but is not really representative of what will happen in the customer system. That ’s why, while keeping measurements under Reset, Atmel pre- sents a new way to measure the operating Icc: Using an internal test ROM, the following code is executed: Label: SJMP Label (80 FE) Ports 1, 3, 4 are disconnected, RST = Vss, XTAL2 is not connected and XTAL1 is driven by the clock. This is much more representative of the real operating Icc. Table 26. Absolute Maximum Ratings conditions may affect device reliability.
Table 27. DC Parameters in Standard Voltage
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- Idle I CC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC -
0.5 V; XTAL2 N.C; VPP = RST = VSS (see Figure 19.).
- Power Down I CC is measured with all output pins disconnected; VPP = VSS; XTAL2 NC.; RST = VSS (see Figure 20).
- Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and
Table 28. DC Parameters for Low Voltage
0.15 Freq
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Figure 19. ICC Test Condition, Idle Mode Figure 20. ICC Test Condition, Power-Down Mode Figure 21. Clock Signal Waveform for ICC Tests in Active and Idle Modes All other pins are disconnected. All other pins are disconnected.
XHDV = Time from clock rising edge to input data valid. Table 29. gives the maximum applicable load capacitance for Port 1, 3 and 4. Timings be used, but timings will then be degraded. Table 29. Load Capacitance versus speed range, in pF Table 31 gives the description of each AC symbols. Table 31 gives for each range the AC parameter. Table 30. Max frequency for derating formula regarding the speed grade
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Table 31. AC Parameters for a Fix Clock Table 32. AC Parameters for a Variable Clock: derating formula
33 MHz
40 MHz
20 MHz
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Figure 26. Clock Waveforms WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications.
4233G–8051–03/03
Ordering Information
Table 33. Maximum Clock Frequency Table 34. Possible Order Entries
Table 34. Possible Order Entries (Continued)
Note: For SSOP24 and S028 Packages, check with Atmel for availability.
4233G–8051–03/03 Package Drawings DIL24
4233G–8051–03/03 SO24
4233G–8051–03/03 SO28
4233G–8051–03/03 SSOP24
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