T8534

T8533 AGERE | Alldatasheet

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Technical content

Features

■ Includes codec, termination impedance, and echo canceller in one device for line card applications ■ Programmable µ-law, linear, or A-law PCM input and output (ITU-T G.712 compliant) ■ Per-channel programmable gains ■ Per-channel programmable internal termination impedance ■ Per-channel 64-tap echo canceller (ITU-T G.168 compliant) ■ Fully programmable time-slot assignment ■ Analog and digital loopback test modes ■ Serial microprocessor interface ■ Sigma-delta converters with dither to reduce noise ■ Six per-channel, bidirectional control pins for SLIC and line card function control (68-pin package) ■ Quad design to minimize package count on dense line card applications ■ Built-in level correction (transmit equalization) to accommodate current-sensing SLICs ■ Single 5 V operation ■ Available in 68-pin, 64-pin, and 44-pin packages General Description The quad programmable line card signal processor consists of four independent channels of codec and digital signal processing functions on one chip. In addition to the classic A-to-D and D-to-A conversion, the device includes termination impedance synthesis and a 64-tap echo canceller, functionally, on a per- channel basis. The device is capable of meeting all international standards for terminating impedance and digital encoding format. The processing circuitry for the adjustment of the transmit level (equalization) to accommodate current-sensing SLICs is also included. The device is controlled by a serial microprocessor interface, and a set of bidirectional I/O pins are pro- vided, on a per-channel basis, so that this control mechanism can be utilized to operate the battery feed device, ringing voltage switches, etc. Common data and clock paths can be shared over any number of devices. All the filter coefficients, signal process- ing, SLIC, and test features are accessible through this interface. This serial interface can be operated at speeds up to 4.096 Mbits/s. The PCM bus is also programmable, with any chan- nel capable of being assigned to any time slot. The PCM bus can be operated at speeds up to

16.384 Mbits/s, allowing for a maximum of 256 time

slots. Separate transmit and receive interfaces are available for 4-wire bus designs, or they can be strapped together for a 2-wire PCM bus. The device is available in 68-pin, 64-pin, and 44-pin surface-mount packages for economic use of board space.

Figure 1. Functional Block Diagram, Each Section

3 FACTORY TEST

and downloaded to the device at the time of powerup. face, and the control interface.

T8533/34 Quad Programmable Line Card 4 Agere Systems Inc. Functional Description (continued) The SLIC interface is designed to be flexible and con- venient to use with a variety of SLIC circuits. With an appropriate choice of SLIC, no external components are required in the interface, with the exception of a dc blocking capacitor in the transmit direction. In some cases, dc blocking capacitors in the receive direction may be necessary as well, since the device operates from a single 5 V supply. The PCM bus interface is flexible in that it allows, inde- pendently, the transmit and receive data for any chan- nel to be placed in any time slot. The bus can be operated at a maximum of a 16.384 Mbits/s rate to accommodate a maximum of 256 time slots. Separate pins are provided for each direction of transmission to allow 4-wire bus operation. The frame strobe signal is an 8 kHz signal that defines the beginning of the frame structure. The interface will count 8 bits per time slot and insert or read the data for each channel as pro- grammed. Lower speeds of the PCM bus are allowed. The PCM clock must be synchronous with the master clock for the device (if present) and with the frame strobe signal. The microprocessor control interface is a serial inter- face that uses the classic chip select type of operation. The interface controls the device by writing or reading various internal addresses. The command set com- prises simple read and write operations, with the address determining the effect. All the memory loca- tions, including the per-chip functions, are organized by channel, allowing a straightforward migration path to architectures other than quad. There are several test modes included to facilitate confirmation of correct operation. In the signal path, both an analog and four digital loopback tests are avail- able, while in the microprocessor interface, there is a write/read test mode that tests the operation of the memory. Use of external test access switches allows a complete test of the signal path through the line card so that correct operation of various operational modes can be verified.

Figure 2. 44-Pin PLCC Pin Diagram Table 1. Pin Assignments, 44-Pin PLCC, Per-Channel Functions 14 21 24 31 V DD PWR 5 V Analog Power Supply. or 20 MΩ resistance to AGND. 12 19 26 33 VF R OP O Receive Analog Output, Positive Polarity. 11 18 27 34 VF R ON O Receive Analog Output, Negative Polarity.

Table 2. Pin Assignments, 44-Pin PLCC, Common Functions 1D O O Serial Data Output. This is a 3-state output. 3 DCLK I Serial Data Clock Input. mode. This pin has an internal pull-up. 7 PVCOIN — Internal Test Point. Do not connect to this pin. 8P V C O — Internal Test Point. Do not connect to this pin. 9P L L T — Internal Test Point. Do not connect to this pin. plane is highly recommended. AGND, DGND, SGND plane is highly recommended. 17, 28, 35, 42 V DD PWR Digital Power Supply (5 V). source as BCLK. See the Clocking Considerations section. rates. See the Clocking Considerations section. 39 DX O PCM Bus Output Pin. This is a 3-state output. it may be driven by external logic. This pin has an internal pull-up. this pin may be left open. This pin has an internal pull-up.

Figure 3. 68-Pin PLCC Pin Diagram Table 3. Pin Assignments, 68-Pin PLCC, Per-Channel Functions 20 33 36 49 V DD PWR 5 V Analog Power Supply. or 20 MΩ resistance to AGND. 18 31 38 51 VF R OP O Receive Analog Output, Positive Polarity. 17 30 39 52 VF R ON O Receive Analog Output, Negative Polarity. 16 29 41 53 SLIC0 I/O SLIC Control Pin 0. 15 27 42 54 SLIC1 I/O SLIC Control Pin 1.

Table 4. Pin Assignments, 68-Pin PLCC, Common Functions 1D O O Serial Data Output. This is a 3-state output. 3 DCLK I Serial Data Clock Input. mode. This pin has an internal pull-up. 11 PVCOIN — Internal Test Point. Do not connect to this pin. 12 PVCO — Internal Test Point. Do not connect to this pin. 13 PLLT — Internal Test Point. Do not connect to this pin. plane is highly recommended. AGND, DGND, SGND plane is highly recommended. 28, 40, 55, 66 V DD PWR Digital Power Supply (5 V). source as BCLK. See the Clocking Considerations section. rates. See the Clocking Considerations section. 59 DX O PCM Bus Output Pin. This is a 3-state output. it may be driven by external logic. This pin has an internal pull-up. input for certain PCM bus rates. See the Clocking Considerations section. When unused, this pin may be left open. This pin has an internal pull-up.

Figure 4. 64-Pin TQFP Pin Diagram Table 5. Pin Assignments, 64-Pin TQFP, Per-Channel Functions 11 23 26 38 V DD PWR 5 V Analog Power Supply. or 20 MΩ resistance to AGND. 9 2 12 84 0 V FR OP O Receive Analog Output, Positive Polarity. 8 2 02 94 1 V FR ON O Receive Analog Output, Negative Polarity. 64 16 33 50 SLIC2 I/O SLIC Control Pin 2. 63 15 34 51 SLIC3 I/O SLIC Control Pin 3. 62 13 36 52 SLIC4 I/O SLIC Control Pin 4.

Table 6. Pin Assignments, 64-Pin TQFP , Common Functions 1F I L T V P W R Frequency Synthesizer Power (5 V). This pin must be tied to VDD . 2 PVCOIN — Internal Test Point. Do not connect to this pin. 3P V C O — Internal Test Point. Do not connect to this pin. 4P L L T — Internal Test Point. Do not connect to this pin. plane is highly recommended. AGND, DGND, SGND plane is highly recommended. 18, 30, 44, 54 V DD PWR Digital Power Supply (5 V). source as BCLK. See the Clocking Considerations section. rates. See the Clocking Considerations section. 48 DX O PCM Bus Output Pin. This is a 3-state output. it may be driven by external logic. This pin has an internal pull-up. input for certain PCM bus rates. See the Clocking Considerations section. When unused, this pin may be left open. This pin has an internal pull-up. 57 DO O Serial Data Output. This is a 3-state output. 59 DCLK I Serial Data Clock Input. mode. This pin has an internal pull-up.

Agere Systems Inc. 11 Preliminary Data Sheet July 2001 Signal Processor T8533/34 Quad Programmable Line Card Functional Description Clocking Considerations This device has several clock inputs for the various interfaces. The PCM bus uses BCLK as the bit clock and the one-going edge of FS to determine the location of the beginning of a frame. These two clocks must be derived from the same source. Internally, the device develops all the internal clocks with a phase-locked loop that uses BCLK as the timing source when BCLK instances, MCLK is not used and may be left open since any signal driving MCLK is ignored. For BCLK rates of 256 kHz and 512 kHz, MCLK is used as a source for the PLL and must be 1.024 MHz. In this lat- ter case, BCLK, MCLK, and FS must be derived from the same source and the rising edge of BCLK must be within 10 ns of the rising edge of MCLK. BCLK, FS, and MCLK (if required) must be continuously present and without gaps in order for the device to operate cor- rectly. Note that the nominal values in Table 15 are the valid frequencies for BCLK. DCLK is used to clock the internal serial interface and may be asynchronous to the other clocks. There is no need to derive this clock from the same source as the other clocks. The serial bus may be operated at any speed up to 4.096 Mbits/s. DCLK can be gapped, how- ever additional clock cycles are required in and around the command frame to process data, and during and after a hardware or a software reset to ensure com- plete clearing of internal logic. There is no limit on the number of devices on the same serial bus. The Control Interface The device is controlled via a series of memory loca- tions accessed by a serial data connection to the exter- nal master controller. This interface operates using the chip select lead to enable transmission of information. All chip functions are enabled or disabled by setting or clearing bits in the control memory. Filter coefficients and gain adjustments are also stored in this memory. The codec has both a serial input lead and a serial out- put lead. These may be used individually for a 4-wire serial interface, or tied together for a 2-wire interface. The line driver circuitry is capable of driving relatively high currents so that in the event that the line is long enough to show significant transmission line effects, it can be terminated in the characteristic impedance at each end with resistors to V CC and ground. All data transfers on the serial bus are byte oriented with the least significant bit (shown in this data sheet as bit 0) transmitted first, followed by the more significant bits. For data fields, the least significant byte of the first data byte is transmitted first, followed by the more sig- nificant bytes, each byte transmitted LSB first. This for- mat is compatible with the serial port on most microcontrollers. Modes There are two different modes of operation for the serial interface, the normal mode and the byte-by-byte mode. These two modes differ in the manner in which CS is used to control the transfer. Note that the CS lead is used to control the transfer of serial data from master controller to slave codec and in the reverse direction. In normal mode, (INTS pin open) the CS lead must go low for the duration of the transfer. The only error check performed by the codec is to verify that CS is low for an integral number of bytes. Detection of an active (active- low) chip select for other than an integral multiple of 8 bits results in the operation being terminated. The next active excursion of chip select will be interpreted as a new command; hence, the serial I/O interface can always be initialized by asserting CS for a number of clock periods that is not an integral multiple of 8. CS is captured using DCLK, so DCLK must be transitioned to perform this initialization. Undefined command codes are reserved for future use and may cause unwanted operation of the device. The byte-by-byte mode (INTS pin tied to ground) uses CS to control each byte of the transfer. In this mode, CS goes low for exactly 8 bits at a time, corresponding to a 1-byte transfer either to or from the codec chip. Repeated transitions of CS are used to control subse- quent bytes of data to/from the codec. For a write com- mand in this mode, CS must go low for each byte of the transfer until the transfer is complete. For a read com- mand, CS will go low for each of the 3 bytes of the read command transferred to the device, then low again for each byte to be read. Notice that the total number of bytes transferred (and excursions on CS) is N + 3, where N is the number of bytes to be read in the com- mand. This mode of operation is useful in cases where the master is a microprocessor with a built-in UART that transfers 1 byte at a time. Error detection is limited to detection of an active CS for other than an integral multiple of 8 bits. Recovery is the same as normal mode. Note that the clock phase is shifted in this mode. Flow control can be accomplished by suspending the transitions on DCLK by holding either state. During the data transfer, CS must remain low while clock transi- tions are suspended with DCLK in either state.

1212 Agere Systems Inc. Preliminary Data Sheet July 2001Signal Processor T8533/34 Quad Programmable Line Card Functional Description (continued) The Control Interface (continued) Protocol The format of the command protocol is shown in Fig- ures 5 and 6. The control interface operates with one external master controller and multiple slave codec devices. Each transfer is initiated by the master, and the slave responds for either read operations or the fast scan mode. The slave does not check the bus for activity prior to transmitting; it only checks for an active CS. The master should allow for a wait between the end of a read command until CS becomes active for the read data. The master must refrain from sending additional commands to the slave chip until the response is received. On a 4-wire bus, commands to other devices may be initiated before the response is received, but care in generating the CS function is needed to ensure that the multiple responses do not interfere. It should be noted that multiple memory locations can be accessed in the same command by setting the data field length field to the desired number of bytes to be transferred. If flow control is desired, it must be per- formed by using separate commands, each transfer- ring smaller blocks of information, or by controlling the serial clock (gapping the serial clock), or with CS in the case of byte-by-byte mode. There is no response from the slave to the master for a write operation. The response to a read operation sim- ply includes the data to be read in the data field. This data is sent least significant bit first, with the bytes sent in ascending sequence. Commands from the master controller include data for write operations, but not for read operations. Since the coefficients and gains are stored in volatile memory, all the coefficients and gains must be loaded after powerup. There is, however, no need to reload them when switching from active to standby modes, or vice versa. Great care should be exercised in loading memory when the codec channel is not in standby mode. Sudden changes in the termi- nation or balance impedances can result in undesirable system operation. All data is transmitted in a byte-oriented fashion with the least significant bit of each byte transferred first. Multibyte fields are transferred least significant byte first in both directions. The data field will contain the first addressed data location first, with subsequent data locations transmitted in ascending order.

transmitted LSB first. Additional memory locations are loaded in ascending sequence. Figure 5. Command Frame Format, Master to Slave, Read or Write Commands are loaded in ascending sequence. Figure 6. Command Frame Format, Slave to Master, Read Commands

00 C O M M A N D

critical with regard to gapped DCLK operation. and before the second to last full DCLK cycle. DCLK operation of 4.096 MHz would require 10 cycles of DCLK between LENGTH and DATA. cycles are required to process the read data. † Two or more DCLK cycles are required before the start of a new command frame. Note: Data field length of 1 shown. Figure 11. Read Operation, Normal Mode (Continuous DCLK)

Data field length of 1 shown. CK1 through CK8 are additional DCLK pulses required to properly process the data. CK7 and CK8 are not necessary if another command frame follows this sequence. Figure 12. Read Operation, Normal Mode (Gapped Clock)

and before the second to last full DCLK cycle. DCLK operation of 4.096 MHz would require 10 cycles of DCLK between LENGTH and DATA. cycles are required to process the read data. † Two or more DCLK cycles are required before the start of a new command frame. Note: Data field length of 1 shown. Figure 13. Read Operation, Byte-by-Byte Mode (Continuous DCLK)

Data field length of 1 shown. CK1 through CK8 are additional DCLK pulses required to properly process the data. CK7 and CK8 are not necessary if another command frame follows this sequence. Figure 14. Read Operation, Byte-by-Byte Mode (Gapped DCLK)

2, there are no start address or length fields. The command returns only a single byte of data, formatted as shown in Table 9. Table 7. Bit Assignments for Fast Scan Mode with continuous or gapped DCLKs. DCLK cycles are required to process the read data. † Two or more DCLK cycles are required before the start of a new command frame. Figure 15. Fast Scan, Normal Mode (Continuous DCLK)

1 Channel 0, bit 1 (ckt a, address 160, bit 1)

2 Channel 1, bit 0 (ckt b, address 160, bit 0)

3 Channel 1, bit 1 (ckt b, address 160, bit 1)

4 Channel 2, bit 0 (ckt c, address 160, bit 0)

5 Channel 2, bit 1 (ckt c, address 160, bit 1)

6 Channel 3, bit 0 (ckt d, address 160, bit 0)

Note: CK1 through CK8 are additional DCLK pulses required to properly process the data. Figure 16. Fast Scan, Normal Mode (Gapped DCLK)

Figure 19. Hardware Reset Procedure

2424 Agere Systems Inc. Preliminary Data Sheet July 2001Signal Processor T8533/34 Quad Programmable Line Card Functional Description (continued) Reset Functionality (continued) A 0.1 µF capacitor between the RST lead and ground will effectively hold the lead low long enough to reset the device on powerup, allowing for a cost-effective power-on reset function. Notice that the memory must be reloaded through the serial interface after a hard- ware reset function. For proper operation, it is neces- sary for FS and BCLK to be present and stable during a reset. DCLK transitions (frequency is not critical as long as the maximum rate is not exceeded) are also required in order for all internal logic to be properly cleared as is a wait period for the internal PLL to stabi- lize. See the timing diagram shown in Figure 19 for the proper hardware or power-on reset procedure. For a software reset, the control memory should not be accessed for a minimum of 256 µs following the reset. Memory Control Mapping Several memory locations are used to control the device. The Software Interface tables (Table 17, Mem- ory Mapping and Table 18, Control Bit Definition) show the memory assignments that are useful in call pro- cessing and system testing. It should be noted that other memory locations are used by the device to hold intermediate results and other device state information. Writing to these other locations can cause serious dis- ruptions in the operation of the device and should be avoided. Standby Mode The device enters a low-power standby mode with powerup or software reset, or by programming the CHACTIVE register 129, bit 0. In standby mode, the control interface is active, capable of writing or reading registers. SLIC read and write data latches are also active. Analog signals at VF XI and PCM signals at DR are ignored in this mode. BCLK must be present for proper standby mode operation. Test Capabilities The device has several built-in test capabilities that can be used to verify correct operation of the signal pro- cessing of the line card. These test functions are accessed in several different control addresses. Five loopback modes are employed (the first four in the list below are digital loopbacks): Digital 1. Allows the digital signal from the PCM bus to be looped back to the PCM bus. This loopback facility can be used to verify cor- rect operation of the PCM bus interface logic, as well as operation of the PCM bus. Digital 2. Allows complete testing of the digital pro- cessing capability of the codec by looping the data back at the analog/digital conver- sion interface. Digital 3. This loopback function is at the digital side of the sigma-delta mode converters and loops analog transmit data back to the analog receive path. Digital 4. This loopback is at the PCM bus interface and loops the transmit data from the line back to the receive path. Analog 5. The analog loopback facility can be used to check the operation of all the signal processing performed in the device, including the conversions to/from analog. Three of these loopback functions (digital 1 and 2, and the analog loopback) can be used with tone generation and reception via the PCM bus. By assigning the transmit and receive time slots identi- cally, a loopback arrangement at the PCM bus can be effectively programmed for signals generated on the line side of the codec. This mode is useful for testing from the line side through the entire device. An optional 16-bit encoding mode is included on a per- channel basis for use in various test scenarios, or for use by an external digital signal processor. This mode of operation differs from the companded modes in both the bit order and the use of multiple time slots on the PCM bus.

Agere Systems Inc. 25 Preliminary Data Sheet July 2001 Signal Processor T8533/34 Quad Programmable Line Card Functional Description (continued) Echo Canceller Functionality The echo canceller has three sets of coefficient mem- ory storage locations. One, called HPRE, contains the default balance coefficients and can be accessed as memory addresses 0—127. This serves as the coeffi- cients for a fixed balance network (adaptation dis- abled), or as a starting point for echo cancelllation. The contents of these memory locations do not change with adaptation. The adaptation coefficients, which are added to the corresponding coefficients in HPRE, are stored in the HHAT area. Normally, the user has no need to access these coefficients; thus, these addresses are not described in this data sheet. The HHAT coefficients cover either the first 8, 16, 32, or the entire 64-tap length of the balance filter, depending on the settings in the LMSGAIN address. Note that all echo canceller length options in this control location may not be implemented, but are reserved for future use. A third set of coefficients is contained in HDTA, which are used for special data call functions. SLIC Control Capabilities Memory locations 158, 159, and 160 are used to con- trol six bidirectional latches that are intended to allow the serial interface to control other line card devices, such as ringing/test switches, telecom electromechani- cal relays, and SLIC devices. When the TTL latches are configured as outputs, external devices should be set up to sink current from the latch. Location 158 sets the operational mode of these latches as either inputs or outputs. Location 159 specifies what is to be written on the latch leads driven by the device. Location 160 reports the actual state of these leads. It should be noted that a channel control reset forces all of these external leads, except those corresponding to bits 2 and 3, to the high-impedance state, so any inputs con- nected to bits 0, 1, 4, and 5 should have appropriate pull-up or pull-down resistors (off-chip, if required) to force the external device into a known state at power- up or in the event of a reset. Bits 2 and 3 will reset to outputs with a value of zero. The fast scan mode allows for a minimal data transfer on the serial bus to monitor bits 0 and 1 of the SLIC data memory location (159). If these 2 bits are wired as inputs to the off-hook and/or ring ground detection cir- cuits, a convenient method of rapidly scanning for these two functions is obtained. Bits 2 and 3 default to outputs; thus, they are convenient to provide control of the SLIC state. In any event, all six leads are program- mable for maximum flexibility. Suggested Initialization Procedures It is suggested that upon powerup, a hardware reset be used to set the device into a known state. The serial interface should then be used to load the memory addresses that differ from the default values (the write all channels command is convenient for this function). If other devices are controlled by the SLIC data mem- ory location, then it also should be loaded with a known configuration. After the completion of this sequence, the device is ready to be activated. Depending on the application, the next step may either be normal opera- tion or a set of test sequences. After the initialization of the memory, the device and associated line card devices can be controlled by using memory locations 130, 131, 145, 155, 156, 157, 158, 159, and 129; that is, by supplying the PCM bus time-slot addresses, switching the SLIC into the proper mode, and activating the codec. Within memory location 129, the codec would normally be placed into active mode, with both directions of the PCM bus enabled at the start of a call. At the completion of a call, the codec should be placed into standby mode and the PCM bus disabled. Great caution should be used when changing the memory while the codec is in active mode, since termination impedances, balance impedances, and gains may change. These changes are likely to yield undesirable system effects. It is safe to refresh coefficients that are known to be unchanging in the application. It is always possible to read the memory to verify its contents with- out deleterious effects on codec operation. Normal operation would load the memory and perform all gain adjustments while the codec is in standby mode. Under no circumstances should memory above address 162 be written, since this section of memory is used for state data and intermediate results. Also, all reserved addresses should not be written. Changing this infor- mation may have deleterious effects on system opera- tion.

July 2001 Signal Processor T8533/34 Quad Programmable Line Card Agere Systems Inc. 27 Operating Ranges Handling Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (ESD) during handling and mounting. Agere Systems Inc. employs a human-body model (HBM) and a charged-device model (CDM) for ESD susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide stan- dard has been adopted for the CDM. A standard HBM (resistance = 1500 Ω , capacitance = 100 pF) is widely accepted and can be used for comparison. The HBM ESD threshold of >1000 V was obtained by using these cir- cuit parameters:

Electrical Characteristics

For all specifications: TA = −40 °C to +85 °C, VDD = 5 V ± 5%, unless otherwise noted. Typical values are for TA = 25 °C and VDD = 5 V. Input signal frequency is 1004 Hz, unless otherwise noted. dc Characteristics Table 8. dc Characteristics

The following specifications pertain to the analog SLIC interface for each channel. Table 9. Analog Interface

Table 10. Power Requirements Table 11. Transmission Characteristics

Table 11. Transmission Characteristics (continued)

• Applied to all four channels.

Table 12. Per-Channel Noise Characteristics

• RTZ and CTZ paths open. All channels active.

4600 Hz to 7600 Hz

7600 Hz to 8400 Hz

Table 13. Distortion and Group Delay

200 Hz < fIN < 3400 Hz; measured

300 Hz to 3400 Hz

Table 14. Crosstalk

Table 15. Timing Characteristics the rising edge of BCLK within 10 ns. †T h e tSXBDLY delay is from either DCLK or CS, whichever transition is later, for the first bit of the byte.

Table 15. Timing Characteristics (continued) the rising edge of BCLK within 10 ns. † The tSXBDLY delay is from either DCLK or CS, whichever transition is later, for the first bit of the byte. Table 16. Echo Canceller Characteristics

16.384 MHz

received first. See the Clocking Considerations section for the relationship between BCLK and MCLK, if used. Figure 23. PCM Bus Timing (Diagram Shown has Bit Offset of Zero and Minimum Width of FS)

Table 17. Memory Mapping ory locations can be programmed on a per-channel basis. Note that the entire coefficient set for a channel (or all four channels) may be loaded with one command.

• The coefficients to be entered can be obtained from the Aquarium coefficient software.

Balance impedance tap coefficients. force until the bit is written as a 0. CHACTIVE 129 1 0x00 Standby/active control. RXBITOFF 130 3 0x00 Bit offset for receive direction. Time-slot offset for receive direction. GRX1* 132—133 11 0x0400 Control of gain affecting receive direction gain transfer. NORMCTRL* 136 6 0x25 Peak and far-end speech detector control. NESCTRL* 137 3 0x06 Near-end speech detector control. LMSGAIN* 138 8 0xee Adaptation control address. TDETCTRL* 139 6 0x00 Data call control address. CTZCTRL* 140—143 31 0x07ed0000 CTZ bleed coefficients. LMSCTRL* 144 3 0x01 Adaptation leak values. RECCTRL* 145 5 0x00 Residual echo control. state referenced in this data sheet. GTX2* 148—149 12 0x0400 Control of gain affecting transmit direction gain transfer. choices, transmit direction. TXBITOFF 155 3 0x00 Bit offset for transmit direction. Time-slot offset for transmit direction. PCMCTRL 157 7 0x00 PCM control address. ing SLIC pin to operate as an output pin.

Table 17. Memory Mapping (continued) Table 18. Control Bit Definition bit being set places the function into the active mode as defined in the function column. bit is set in the SLICTS control word. PCM frame (125 µs), the data will be overwritten. VERIFY 162 8 — Test address for serial interface verification. — 254—255 16 — Factory test only, do not access. for addresses 3 and 5, which are 0x80, and address 69, which is 0x88. 3 A one resets the state associated with special data call processing. 2 A one resets the echo canceller coefficients to 0 when channel is active. ing any other serial I/O transactions. vates the channel and the corresponding PCM bus interface. Default is 0.

Table 18. Control Bit Definitions (continued) 2 (6 dB). 0 dB is the maximum recommended setting. gain of 2 (6 dB). 0 dB is the maximum recommended setting.

2 Enable near-end speech detector. Defaults to 1 (active). taps). Defaults to 3 (64 taps). to 5. A setting of 0 provides no adaptive loop gain. 0—2 Loop gain for adaptation algorithm.

5 This bit being set allows the echo canceller coefficients developed off-

the next data call. Default is 0 (do not capture).

4 This bit enables the echo canceller to continue to adapt during a data

call. Default is 0 (do not adapt during a data call).

3 This bit, when set, enables the use of the internal logic to determine the

proper time for the off-line adaptation during a data call. Default is 0.

2 Selects the internal set of hybrid balance network coefficients to use on

1 This bit, when set to a 1, clears the H register at the start of a data call. 0 This bit being set freezes the echo canceller. Default is 0.

0—30 Coefficients for the CTZ termination bleed. Defaults to 0x07ed0000. 0—2 Leak coefficient for LMS adaptation algorithm. Defaults to 1. 4 Noise match enable (comfort noise). Defaults to 0 (disabled). 3 Enable residual echo control. Defaults to 0 (disabled). 0—2 Residual echo control sensitivity factor. 6 Enable analog loopback. Defaults to 0 (no loopback). 3—5 RTZ gain. Defaults to 3 (equal level point value of 3 * 0.075 = 0.225).

6 Digital loopback, loopback from receive to transmit at the sigma-delta

converters (digital loopback 2). Defaults to 0 (no loopback). 3 Send idle channel code (alternating bits) to this analog receive path. Defaults to 0 (do not send idle channel code).

2 Loopback from transmit to receive at the sigma-delta converters (digital

loopback 3). Defaults to 0 (no loopback). 0—1 Analog channel feeding this digital channel in the transmit direction.

ing SLICs. Defaults to 0x000000. condition on the transmit interface. 6 Transmit zeroes instead of data. Defaults to 0 (off). 4 Place idle channel code on receive path. Defaults to 0 (off).

3 Loopback receive to transmit at PCM conversion interface (digital loop-

back 1). Defaults to 0 (no loopback).

2 Loopback transmit to receive at PCM conversion interface (digital loop-

back 4). Defaults to 0 (no loopback). slots used, LSB transmitted first. Linear data is in two’s complement form. mitted first. Defaults to 0. has no effect if bit 1 of this address is set to 1. Defaults to 0 (µ-law). pin as an output. Defaults to 0x0c (bits 2 and 3 set, the rest cleared). all channel commands. Default is 0. 6—7 Not used, ignore on a codec read command addressing this location. is ignored. Updates within 125 µs. merely latches write data for the purpose of testing the serial interface. This register does not clear with reset. 0—4, 6, 7 Internal state control bits; do not write and ignore on read.

T8533/34 Quad Programmable Line Card 44 Agere Systems Inc.

Applications

The following reference circuit shows a complete schematic for interfacing to the Agere L9215G SLIC. All ac parameters are programmed by the T8534. Note that this implementation differentiates itself in that no external components are required in the ac interface to provide a dc termination impedance or for stability. For illustration purposes, 0.5 Vrms PPM injection was assumed in this example and no meter pulse rejection is used. Also, this example illustrates the device using programmable overhead and current limit. 12-3534.z (F) *RVFxI is required for complex terminations. Optional for resistive terminations. Figure 24. POTS Interface

0.5 Vrms

July 2001 Signal Processor T8533/34 Quad Programmable Line Card Agere Systems Inc. 45 Outline Diagrams 68-Pin PLCC Dimensions are in millimeters. Note:The dimensions in this outline diagram are intended for informational purposes only. For detailed footprint drawings to assist your design efforts, please contact your Agere Sales Representa- tive. 5-2139(F) 27 43 PIN #1 IDENTIFIER ZONE 25.146 ± 0.127 24.231 ± 0.102 25.146 ± 0.127 24.231 ± 0.102 1.27 TYP 0.330/0.533 5.080 MAX

0.51 MIN,

0.10

T8533/34 Quad Programmable Line Card 46 Agere Systems Inc. Outline Diagrams (continued) 64-Pin TQFP Dimensions are in millimeters. Note:The dimensions in this outline diagram are intended for informational purposes only. For detailed footprint drawings to assist your design efforts, please contact your Agere Sales Representa- tive. 5-3080(F) DETAIL A

0.50 TYP

1.60 MAX

0.08 DETAIL B 0.05/0.15 1.40 ± 0.05 10.00 ± 0.20 12.00 ± 0.20 64 49 17 32 10.00 ± 0.20 12.00 ± 0.20 PIN #1 IDENTIFIER ZONE DETAIL A 0.45/0.75 GAGE PLANE SEATING PLANE

1.00 REF

0.25 DETAIL B 0.19/0.27 0.08 M 0.106/0.200

July 2001 Signal Processor T8533/34 Quad Programmable Line Card Agere Systems Inc. 47 Outline Diagrams (continued) 44-Pin PLCC Dimensions are in millimeters. Note:The dimensions in this outline diagram are intended for informational purposes only. For detailed footprint drawings to assist your design efforts, please contact your Agere Sales Representa- tive. 5-2506(F) 4.57 MAX 1.27 TYP 0.53 MAX 0.10 SEATING PLANE

0.51 MIN

PIN #1 IDENTIFIER ZONE

16.66 MAX

17.65 MAX

16.66 MAX 17.65 MAX

T8533/34 Quad Programmable Line Card Agere Systems Inc. reserves the right to make changes to the product(s) or inform ation contained herein without notice. No liability is assume d as a result of their use or application. Co pyright © 2001 Agere Systems Inc. All Rights Reserved July 2001 DS01 -250ALC (Replaces DS01-058ALC) For additional information, contact your Agere Systems Account Manager or the following: IN TERNE T: http://www .agere.com E-M AIL: docm aster@mi cro.lucent.com N. AM ERIC A: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentow n, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CAN AD A: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC :Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHIN A: Agere Systems (Shanghai) Co ., Ltd., 33/F Jin Mao Towe r, 88 Century Boulevard Pudong, Shanghai 200121 PRC Tel. (86) 21 50471212, FAX (86) 21 50472266 JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chom e, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EU R OP E: D ata Requests: D ATALIN E: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries:G ER MA N Y: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FR AN CE: (33) 1 40 83 68 00 (Paris), SWE D EN : (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN : (34) 1 807 1441 (Madrid)

Ordering Information

Dev ice Code Package Comcode T-8533 - - - M L - D 44-Pin PLCC, Dry-bagged 108269408 T-8534 - - - TL - DB 64-Pin TQFP, Dry pack tray 108420217 T-8534 - - - M L - D 68-Pin PLCC, Dry-bagged 108269424