T8531

T8531 AGERE | Alldatasheet

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Technical content

Features

■ Single 5 V power supply operation ■ Per-channel programmable transmit gain — 25.6 dB range, better than 0.01 dB steps ■ Per-channel programmable receive gain — 17.8 dB range, better than 0.01 dB steps ■ Per-channel programmable hybrid balance ■ Programmable termination impedances ■ Programmable µ-law, A-law, or linear PCM output ■ DTMF generator ■ DTMF receiver ■ Caller ID generator ■ Call progress tones generator ■ Automatic gain calibration ■ Programmable time-slot assignment with bit offset ■ Low-noise, balanced, receive SLIC interface ■ Few or no SLIC/codec interface components required ■ Analog and digital loopbacks ■ Sigma-delta converters with dither noise reduction ■ Serial microcontroller control interface ■ Available in 64-pin MQFP and TQFP packages General Description The Multichannel Programmable Codec Chip Set is comprised of the T8531 16-channel line card signal processor and one or two custom T8532 octal A/D and D/A converters. A ROM-coded tone plant is included on the signal processor. Together these devices achieve a highly integrated and highly pro- grammable multichannel voice codec solution. Software is provided to compute the gain and filter coefficients required to program the codec. 5-3793F (F) Figure 1. System Block Diagram

Table 3. Active Time-Slot Spacing in a PCM Table 4. DSP Engine RAM Map for Channel_0 ac Table 6. DSP Engine RAM Map for Time-Slot Table 7. Summary of Microprocessor Commands Table 19. T8531 Time-Slot Assignment Memory Table 21. T8531 Channel Register Memory Map Table 22. T8531 Channel Register Memory Map Table 23. Bit Map for T8532 Powerup/Powerdown Table 24. Bit Map for T8532 Channel Control Table 25. T8532 Control Register 1: Transmit Table 26. T8532 Control Register 1: Analog Table 27. T8532 Control Register 1: Digital Table 28. Bit Map for T8532 All Channel Test Table 29. Bits 3:0 of T8532 All Channel Test Table 30. Bit Map for T8532 Channel Control Table 31. T8532 Control Register 2: Receive Gain...38 Table 33. Bits 15:8 of T8531 Board Control Word 1 Table 34. Bits 7:0 of T8531 Board Control Word 1 Table 35. Bits 15:9 of T8531 Board Control Word 2 Table 36. Bits 8:0 of T8531 Board Control Word 2 Table 37. Bits 15:0 of T8531 Board Control Word 3 Table 38. Bits 15:0 of T8531 Board Control Word 4 Table 39. Bits 15:0 of T8531 Board Control Word 5 Table 40. Bits 15:0 of T8531 Reset of Table 42. Transmit Path Group Delay vs. Bit Offset..48

gain. The digital oversampled data is multiplexed onto a serial data port designed to interface with the T8531. powerdown modes. This chip also contains a precision voltage reference. Figure 2. Block Diagram of T8532 Octal Converter Figure 3. Block Diagram of One T8532 Analog Channel

1.024 MHz

Figure 4. T8531 Block Diagram

Figure 5. T8531 Digital ac Path Figure 6. Control, PCM, and Octal Interfaces

4 MHz CLOCK

4 CH RX DATA

4 CH TX DATA

Figure 7. T8532 64-Pin MQFP

Table 1. T8532 Pin Descriptions device is included on this lead, Id indicates a pull-down device is included on this lead. VTX[7:0] AI Analog Input. Transmit signal voltage to be encoded. arate supply associated with the corresponding VTX pin. either differentially or single ended. It is the complement of the VRN output. differentially or single ended. It is the complement of the VRP output. should be located as close as possible to the device pins. this chip and the T8531. This is the master clock input for the T8532. sampled data interface between the T8532 and the T8531. enables the control interface. 55 RSTB TIu Reset (Active-Low). This input must be pulled high for normal operation. powerup initialization. This pin has an internal pull-up resistor.

Figure 8. T8531 64-Pin TQFP

Table 2. T8531 Pin Descriptions device is included on this lead. address and data to the T8531 through this pin. ter contents from this pin. Inactive state is high impedance. 39 OSCK CO 4.096 MHz Clock. Clock for data transfer to/from T8532 chips. DDA — Synthesizer VDD . Power supply for clock synthesizer block. 13 V SSA — Synthesizer Ground. Ground connection for the clock synthesizer block. generate all internal clocks. Rate is 4.096 MHz.

17 SCKSEL TI

viding 4.096 MHz SCK operation with no external connections.

Table 2. T8531 Pin Descriptions (continued)

• The DSP is not configured for boundary-scan operation.

up device is included on this lead, Id indicates that a pull-down device is included on this lead. except during the transmit time slots as defined in the TSA registers. Data is shifted out on the rising edge of SCK. select one of the associated T8532 chips. 7T C K T I JTAG Test Port*—Common Test Clock. Rate ≤20 MHz. 4T D I T I u JTAG Test Port*—Serial Data Input. A pull-up device is provided. 5T D O T O JTAG Test Port*—Serial Data Output. 6T M S T I u JTAG Test Port*—Mode Select. A pull-up device is provided. pin. A pull-up device is provided. pins go into a high-impedance state. A pull-up device is provided. sizer and uses TSTCLK to drive the chip. A pull-up device is provided. of CK16 is unaffected by software reset. 8T S T C L K C I Test Clock. 12, 14 NC — No Connect. This pin may be used as a tie point.

64 DSPCKSL1 CI

d DSP Clock Select. See DSP Clock Frequency Selection on page 14. 1 DSPCKSL2 CI d DSP Clock Select. See DSP Clock Frequency Selection on page 14. nection to this pin. A pull-up device is provided. located as close as possible to the device pins.

1212 Lucent Technologies Inc. Preliminary Data Sheet November 2000Codec Chip Set T8531/T8532 Multichannel Programmable Chip Set Functional Description Transmit Path Antialias Filter and Σ-Δ Converter The line interface circuit must provide a transmit signal, VTX, and a reference voltage, VRTX, which is the dc voltage of the VTX signal for that channel. The input signal goes into a programmable-gain ampli- fier. The signal is then passed through an antialias filter followed by a Σ-Δ A/D converter. The Σ-Δ converter operates at 1.024 MHz. The processed output signals are multiplexed into two groups of four channels each onto output pins OSDX[1:0], each of which operates at 4.096 MHz. A precision, on-chip voltage reference helps ensure accurate and highly stable transmission levels. It is important to understand the difference between how the gain levels should be set in the T8532 and how these levels would be set in a standard codec. The T8532 is best thought of as a data acquisition sys- tem, not a codec. Hybrid balance, fine gain adjust, µ- or A-law coding, filtering, and equalization are done after the A/D in the T8532 and by the DSP processor in the T8531. The analog gain adjust taps should not be used to set the absolute level at the PCM output. This can be done using the DSP gain adjust taps. The ana- log taps should be set so the signal at the input to the A/D converter is as close as possible to the full-scale input level of the A/D for the largest signal level that will be present at the VTX input. This optimizes the dynamic range of the A/D. The 0 dB gain tap should thus be used if the maximum signal level is in the range between 2.25 Vp-p and 3.2 Vp-p. The 3 dB tap should be used for signals with a maximum signal level in the range of 1.6 Vp-p and 2.25 Vp-p. The 6 dB tap should be used for signals with a maximum signal level in the range between 1.1 Vp-p and 1.6 Vp-p. Higher gain lev- els should be used for signals with smaller absolute levels. The signal level to produce a 0 dBm0 level at the digital transmit output of the T8531 is not a fixed quantity as explained above. For a line with a complex impedance or an RX echo signal, extra headroom must be allowed and the TX signal level must be set to account for the headroom. In this specification, the largest possible 0 dBm0 level for the TX signal is assumed. This guar- antees that the distortion specification will not be exceeded for all practical 0 dBm signal levels. The larg- est possible 0 dBm signal is one that has no headroom for TX gain equalization. For the case of 0 dB transmit gain, this level is found as: (3.2 V/log This level is the worst-case 0 dBm0 level. Decimator The decimator filters out the high-frequency compo- nents and down-samples to 16 kHz. It also reorders the 16 channels of transmit signals into a sequence that is determined by the time-slot assignment. Digital Transmit Gain Adjustment The transmit absolute and relative gains are specified as 15-bit binary numbers representing their linear magnitude. These gains default to 4000 Hex. This equates to a 0 dB gain for the relative gain but equates to a 1.65 dB gain for the absolute gain. For a 0 dB gain, program the absolute gain for 34ED Hex. Gain can be varied from minus infinity dB (off) (0000 Hex) to 6 dB for relative gain or to 7.65 dB for absolute gain (7FFF Hex). The relative gain control allows for TLP adjustment without hybrid balance or termination coefficient modifi- cation. Band Filtering The bandpass filter in the transmit path removes power line and ringing frequencies, and eliminates most of the signal energy at 4 kHz and above. This allows the encoder to transmit the filtered signal at 8 ksamples/s, the worldwide standard. The transmit filtering is implemented with a low-pass filter, followed by a high-pass filter. The data samples enter the filter at 16 ksamples/s. They are first low-pass filtered to 3.4 kHz. After low-pass filtering, the sampling rate is reduced to 8 ksamples/s. The samples are then high-pass filtered to 300 Hz. The low-pass filter also serves as an equalizer for fre- quency response alterations. A set of equalizer coeffi- cients that modify this filter are required for each complex termination impedance when using a voltage feed, current-sensed SLIC. µ-Law, A-Law, and Linear PCM Modes In the transmit path, the 8 ksamples/s PCM signal out- put from the filter is processed prior to transmission over the system interface. The 16-bit linear PCM signal may be compressed according to either µ-law or A-law, or transmitted as two consecutive 8-bit words. The selection is programmable via the microprocessor interface. Please note, when using A-law, a linear value of 0 is always encoded as 7F.

Lucent Technologies Inc. 13 Preliminary Data Sheet November 2000 Codec Chip Set T8531/T8532 Multichannel Programmable Chip Set Functional Description (continued) Receive Path In the receive direction, the signal received from the system interface is converted to a 16-bit linear PCM sig- nal. Receive Path Filtering The 16-bit linear PCM signal is filtered and interpolated to 16 ksamples/s to meet the receive signal loss charac- teristics. This filter smooths the data following interpola- tion from 8 ksamples/s to 16 ksamples/s. The filter can also serve as an equalizer for frequency response alter- ation. This is required for complex termination imped- ance cases when using a current feed, voltage-sensed SLIC. One of two receive filters can be used, the receive filter and the extended receive filter. The receive filter has two poles and three zeros. This filter can be used to minimize downloadable code (to use this receive filter, select the T7531x codec in the Aquarium coefficient software). The extended receive filter provides more flexibility in coefficient optimization by providing three poles and three zeros. The Aquarium coefficient soft- ware defaults to the extended receive filter when the T8531x codec is selected. Digital Receive Gain The receive absolute and relative gains are specified as 15-bit binary numbers representing their linear magni- tude. These gains default to 4000 Hex. This equates to a 0 dB gain for the relative gain but equates to a –0.211 dB gain for the absolute gain. For a 0 dB gain, program the absolute gain for 4193 Hex. Gain can be varied from minus infinity dB (0) (0000 Hex) to 6 dB for relative gain or to 5.8 dB for absolute gain (7FFF Hex). The relative gain control allows for TLP adjustment with- out hybrid balance or termination coefficient modifica- tion. Interpolator and Digital Sigma-Delta Modulator The sampling frequency of the receive signal from the digital gain adjustment is increased from 16 kHz to 64 kHz by the interpolator, which removes most of the high-frequency signal images above 8 kHz. The interpo- lator also maps each of 16 time slots to the appropriate line channel through the digital sigma-delta modulator. The digital sigma-delta modulator converts the interpo- lated signal to a 1.024 MHz bit stream which is then sent to the T8532 device. Decoder, Filters, and Receive Amplifier Receive data enters the T8532 on pins OSDR[1:0] at

4.096 MHz; four channels are time-division multiplexed

onto each pin. The data is demultiplexed into eight indi- vidual channels. The processed signal for each chan- nel passes through switched-capacitor D/A and reconstruct filters, followed by a smoothing filter. A pro- grammable gain amplifier is included, followed by an output amplifier capable of driving a 50 kΩ load to ±1.58 V single-ended (relative to VOS) or ±3.16 V dif- ferential at peak overload. For single-ended operation, the load must be ac coupled to VRP (or VRN). Other Chip Set Functions Voltage Reference The T8532 has a precision on-chip voltage reference which ensures accurate and highly stable transmission levels. Hybrid Balance The hybrid balance function is provided as a digital block in the T8531. The T8531 implements a 9-tap FIR and a single-pole IIR digital balance filter in which a replica of the echo is digitally subtracted from the transmit plus near-end echo signal. The coefficients are user programmable on a per-line basis via the microprocessor interface. Analog Termination Impedance Synthesis Termination impedance matching is implemented to maximize the power transfer capability at the loop inter- face and to minimize signal reflections between the transmit and receive paths. The resistive component, implemented in the T8532 device, comprises a variable attenuated path between VTX and VRP. The capacitive component is imple- mented in the digital domain. Analog termination impedance (ATI) is provided with 16 gain settings to match a voltage drive/current sense line interface circuit with the following characteristics: Z T = 2RP + GTX * GRX * AT where ZT is the termination impedance in ohms, RP is the resistance of each protection resistor (for stability R P ≥ 50 Ω ), GTX is the SLIC transmit gain, GRX is the SLIC receive gain, and AT is the T8532 feedback gain. The polarity of the AT gain is positive (positive voltage swing on VTX gives a positive voltage swing on VRP). The gain values are shown in Table 26; gain tolerances are ±2%. Differential receive output is assumed. Digital Termination Impedance Synthesis The CTZ filter in the T8531 synthesizes complex termi- nation impedances. The CTZ filter utilizes alpha and beta coefficients (board control words 4 and 5, respec- tively) to perform the synthesis. One set of alpha beta coefficients is required for each termination impedance and balance network.

1414 Lucent Technologies Inc. Preliminary Data Sheet November 2000Codec Chip Set T8531/T8532 Multichannel Programmable Chip Set Functional Description (continued) Other Chip Set Functions (continued) Digital Termination Impedance Synthesis (continued) Alpha bits [9:0] represent the RC time constant of the impedance that the filter is going to synthesize. The bits are formatted as two’s complement. Alpha bits must be a nonzero value. Beta bits [7:0] represent the dc gain of the filter. Beta coefficients are also formatted as two’s complement. Setting beta equal to zero turns off the CTZ function. There is a constraint on the value of the protection resistor with regard to termination impedance synthesis and hybrid balance. For synthesis to operate properly, the combined series resistance of the tip protection resistor and the ring protection resistor must be 100 Ω or greater. Loopback Modes There are four loopback modes in the T8532. The first two loopback modes are controlled by the all- channel test (ACT) register. ACT bits 0 and 1 place all eight channels into loopback mode. Analog and digital loopback are described and shown in block diagram form in Table 29. Analog loopback allows one to check functionality from tip/ring up to and including the T8532. Digital loopback allows the T8531 to check T8532 functionality. The third loopback mode is used in the autocalibration sequence (control register 2). This mode provides a loopback between a selected channel and channel four of a given T8532. The channel to be calibrated is selected via control register 1 (see Table 27). Channel four is the only channel in the T8532 that is trimmed for gain accuracy. Every other channel uses channel four as a reference and is calibrated to it during the autocal- ibration sequence. The fourth loopback mode is a digital loopback mode located in control register 1. This operates like the digi- tal loopback mode described in the notes for the ACT register (table 29). Unlike the ACT register, this digital loopback mode is selectable per channel. This loop- back mode can be used to check T8532 functionality from the T8531 device. It is also used during the cali- bration sequence. There is one loopback mode in the T8531. Loopback at the oversampled data interface is controlled by board control word 1. This mode allows the T8531 to test itself. When bit 0 of 0x1FFE is selected, all 16 channels of octal interface receive data (OSDRn) are looped back to the T8531 transmit inputs (OSDXn). Interchip Control Interface The control interface is a 4-pin interface used to send control information to the T8532 from the T8531, and to read back the control register contents. The pins con- sist of a chip select input (CCS0 /CCS1 ), a data input (CDI), and a data output (CDO). The transfer of control data is synchronous with the 4.096 MHz OSCK, which is also used for oversampled data transfer. T8531 Functional Blocks Clock Synthesizer The clock synthesizer block is a phase-lock loop (PLL) circuit which takes SCK supplied by the backplane and uses it to produce the DSP engine clock. The input clock, SCK, can be 2.048 MHz or 4.096 MHz. An on-chip clock synthesizer has the advantages shown below: ■ Precludes the need for extra clocks to be fed over the backplane. ■ Constrains the high-speed DSP engine clock within the device. ■ Synchronizes all clocks used on the line card to the backplane clock, thus reducing board noise due to beat frequencies. A clock generator block takes the PLL output and divides it down to produce all the lower-frequency clocks used by the T8531 and T8532. Two pins, DSPCKSL1 (pin 64) and DSPCKSL2 (pin 1), select the DSP1627’s operating clock frequency as shown below. The default frequency is 49.152 MHz (e.g., no connection to pins 1 and 64). Normal codec operations will perform at this frequency. For tone plant operation, 81.92 MHz must be used. DSP Clock Frequency Selection DSPCKSL2 DSPCKSL1 DSP Freq. (MHz) 0 0 49.152 0 1 65.536 1 0 81.920 1 1 93.304

sented to the system interface at an 8 kHz rate. skew takes place in the system PCM interface block. mands consist of two words, address and data. or send data (receive, R/W = 0; send, R/W = 1). is outstanding from the microprocessor interface block. Table 3. Active Time-Slot Spacing in a PCM Bus Frame

1616 Lucent Technologies Inc. Preliminary Data Sheet November 2000Codec Chip Set T8531/T8532 Multichannel Programmable Chip Set Functional Description (continued) T8531 Functional Blocks (continued) A pause therefore exists between the external control- ler issuing an address and receiving a data read back. The data rate of 2.048 MHz allows 256 SCK cycles in a frame, i.e., eight address/data pairs with no pause between words. Since the DSP engine can process only one interrupt every 7.8 µs, the T8531 requires a separation between address and data on read and write instructions to the microprocessor interrupt (see Figure 10). This, in effect, requires UPCK to be gapped. Addresses ≥0x1400 refer to registers or TSA RAM external to the DSP engine. If the address word from the microprocessor is 0x1400 through 0x140F, it activates the TSA state machine. If the address word from the microprocessor is 0x1500 through 0x15FF, it activates the T8532 control state machine. Microprocessor data and address words can be flushed out of the T8531 by addressing 0x7FFF with data word 0xFFFF (see Table 40). T8532 Octal Control Interface The two T8532 chips cannot be accessed by the micro- controller directly; the T8532's registers are all accessed via the T8531 microprocessor interface. The microprocessor communicates serially with the T8532 by simply writing or reading 16-bit address and 16-bit data. The octal control interface block translates this address and data into 8-bit address and 8-bit data needed by the T8532. The octal control interface block waits until the microprocessor interface block receives all 16 bits of the address word and determines whether this is a read or write operation by looking at bit 15. If this is a write operation for a T8532 chip, it receives another 16-bit data word. T8531 Time-Slot Assignment (TSA) The TSA block contains a 16 x 6 dual-port RAM which is readable or writable via the microprocessor inter- face. Table 18 gives the bit map for TSA RAM words. The TSA RAM is in time-slot order, i.e., location 0x1400 is for time slot 0 and 0x1401 for time slot 1 and so on. The low 4 bits (B3—B0) indicate which of the 16 possible channel numbers is assigned to this time slot. The time-slot assignment is controlled by the micropro- cessor writing to address 0x1400 through 0x140F. The TSA block also generates the control signals and flags used to synchronize the TSA, interpolator and decimator, and T8532 interface blocks. The TSA RAM is not preinitialized, so the microprocessor is required to write to all 16 locations of the TSA RAM at start-up to ensure proper operation. Twice a frame, the TSA state machine reads the entire TSA RAM from top to bottom in sequence and sends the contents of each RAM loca- tion to the interpolator as channel numbers for RX channels. The TSA state machine performs the same procedure for the decimator to provide it with the TX channel numbers. By performing TSA at the oversam- pled sigma-delta rate, round trip group delay is signifi- cantly minimized. DSP Engine Timing The DSP engine processes all 16 lines every frame. In order to simplify synchronization of data exchanges, the processing frame is broken into 16 equal time seg- ments of 7.8 µs each. The ROM code is identical for each time segment. Synchronization between the engine and the rest of the chip is enforced by the system interface block, which issues an interrupt every 7.8 µs. This interrupt is the only unmasked interrupt processed by the engine. The interrupt service routine forces the ROM code to branch to the start of the processing loop. T8531 Program Structure The DSP engine firmware performs three types of operations: 1. Signal processing of the ac path data. 2. RAM accesses initiated by the microprocessor interface. 3. Data and program flow operations. The signal processing algorithms performed by the T8531 are implemented in firmware and are held in ROM. Many firmware parameters are user programmable via the microprocessor interface. Interrupts from the micro- processor interface are handled once every time seg- ment (7.8 µs), and the appropriate accesses are made to the DSP engine RAM registers.

1. Activating and deactivating lines.
2. Changing the RX and TX routine to be run.
3. Periodic read and/or refresh of RAM space.

when a microprocessor interface command is received. and to write to specified addresses. each channel, labeled channel_0 through channel_15. change with the time slot (see Table 18).

10 Not

1818 Lucent Technologies Inc. function is performed by the decimator/interpolator. enable the time slot to link to the correct ac coefficients. nel-order time-slot assignment. time slot 0) are shown in Table 6. enabled and the DSP engine enters sleep mode. Table 6. DSP Engine RAM Map for Time-Slot Information Table 0

5 Modify Coefficients 0

Lucent Technologies Inc. 19 Preliminary Data Sheet November 2000 Codec Chip Set T8531/T8532 Multichannel Programmable Chip Set Functional Description (continued) DSP Engine Timing (continued) Microprocessor Start-Up of the DSP Engine Once the interrupt system is enabled, the DSP engine looks for a read or write interrupt from the microproces- sor interface once every time segment, i.e., 16 times a frame. If the ac coefficients for every channel are to be inde- pendently controlled, the microprocessor can write directly to the addresses of the 16 ac coefficient tables. This requires a total of 16 microprocessor commands to set up each channel, i.e., 16 frames to set up all 16 channels. Prior to activating any time slots, the microprocessor has the option of bulk downloading the coefficients to set up the ac coefficient tables. When a channel needs to be set up and linked to its time slot, the microprocessor must send the TCW for that time slot with the modify coefficient (MC) bit (see Table 5A). The MC bit causes the inactive routine for that time slot to set pointers from that time-slot space to the channel space in RAM. The MC bit also causes the inactive routine to check the default coefficient bits of the TCW. If set, the appropriate default table coeffi- cients are copied over to the RAM space for the chan- nel. This mechanism allows the microprocessor to download a set of coefficients that can be used by mul- tiple channels. A mix-and-match approach can be used, i.e., some channels are set up with independent sets of coeffi- cients, while other channels get a default setting. During start-up, the microprocessor must also down- load the 16 TSA commands used by the TSA block to map physical channels to time slots. This is required to initialize the TSA RAM to known values. When all 16 locations have been set up, the microprocessor must send BCW2 (0x1FFC). This flags the TSA control to start normal operation. Powering Up a Time Slot in the T8531 Depending on the application, the microprocessor may choose to set up the ac coefficients for a channel just prior to enabling it for use. This requires 16 micropro- cessor commands if the coefficients must be set up from scratch, or no commands if an appropriate default set has already been set up. In either case, the micro- processor must ensure that all the TX and RX parts of a channel are set up prior to enabling the time slot. If dynamic time-slot assignment is used, the micropro- cessor must next download a TSA command, which the TSA block uses to map the time slot to the required channel number. The microprocessor must enable the time slot by set- ting the go to powerup bit of the TCW. This causes the DSP engine to change the TX and RX ac routine addresses to active. A maximum of 17 commands or a minimum of one command is therefore needed to power up a channel. Disabling a Time Slot in the T8531 To disable a time slot, the microprocessor must send a command that sets the address of either the TX or RX ac routine to TX_inactive and RX_inactive, respec- tively. The inactive routines come into use in the next TX or RX time segment for this time slot. Upon returning from the inactive routine, the DSP engine checks for a microprocessor interrupt and then enters sleep mode for the rest of the time segment. T8532 Powerup/Powerdown Each channel can be powered up independently. There are two control register addresses that can be used to control the power for each channel. In both cases, the first bit of the address word controls the power. P = 1 for powerup, and P = 0 for powerdown. One address is provided for each channel which controls the power (0x1508—0x150F and 0x1548—0x154F), and the address is followed by a data word which controls the other programmable functions for the same channel. A second address (0x1500—0x1507 and 0x1540—0x1547) is provided for each channel that controls only the power.

2020 Lucent Technologies Inc. engine/microprocessor interface and rewriting them. device. The RAM memory map is given in Table 18. The on-chip ROM is used for both program and data. ware development system code is also ROM based. The chips support both hardware and software reset.

1. The PCM bus signals SCK and SFS should be valid

at the start of the 1 ms power-on reset period. cuit has had time to clear the JTAG controller. described above must be repeated. Table 7. Summary of Microprocessor Commands for Control of T8531 Data Processing

1 Start-up or when time slot is inactive

Lucent Technologies Inc. 21 Preliminary Data Sheet November 2000 Codec Chip Set T8531/T8532 Multichannel Programmable Chip Set Functional Description (continued) T8531 Reset and Start-Up (continued) Internal Reset Internal reset is defined as the process that starts when the internal reset line is brought low. This happens as a consequence of hardware (RTSB ) or software (BCW1) reset. The internal reset process performs the following functions: 1. The frequency synthesizer does not receive any reset signal, and is thus unaffected by reset. Follow- ing power-on reset of the T8531, the frequency syn- thesizer takes the mode determined by the SCKSEL pin. 2. The T8531 custom logic jams all resettable latches, counters, and registers to their default values. No data is latched on any of the T8531 interfaces during internal reset. 3. The DSP engine is held in reset state. 4. The internal reset line is held low for a minimum of 18 ms to allow the frequency synthesizer to reach its final accuracy. An internal counter is started when the internal reset line goes low. It counts 80 frame sync pulses on SFS before releasing the internal reset line. 5. When the internal reset line goes high and the EXM (internal) signal is held low, the DSP engine begins its start-up routine by fetching the first instruction from location 0 of the internal ROM. 6. At the rising edge of the internal reset line, all the T8531 custom logic blocks commence their normal operation. Reset of the T8532 Devices There are two options for reset of the T8532 chips. The T8532s can make use of the same hardware reset pulse as the T8531. The T8531 supplies OSCK to the T8532s as soon as it is available, i.e., before the hard- ware reset has gone away. It is recommended that hardware reset be applied to all chips simultaneously. Alternatively, the T8532s can be reset through software reset (Tables 21 and 22), which is generated by the external controlling device and routed to the T8532s via the T8531. This can only occur when OSCK is guaranteed to be valid, i.e., not within 10 ms of power- on hardware reset. Start-Up After Internal Reset There is a specific sequence of microprocessor inter- face instructions that must be followed after internal reset in order to properly configure the T8531 and T8532s for normal operation. 1. If nondefault values are required, the T8531 board control word 1 (address 0x1FFE) must be updated. 2. The 16 TSA RAM locations must be written before 0x1FFC. CTZ must be disabled (see Table 20B). 3. The all channel test register must be set for normal operation (addresses 0x1510 and 0x1550 set to 0x0004). 4. The T8531 control registers must be set. All 16 channels must be powered up (addresses 0x1500—0x1507 and 0x1540—0x1547 must be set to 0x8000). 5. The amplitude of the calibration sine wave must be set by writing address 0x0580 to coefficient 0xAA20, and address 0x0581 to coefficient 0xF49D. 6. All 16 channels must be put into initialization mode (addresses 0x1518—0x151F and 0x1558—0x155F must be set to 0x0080). 7. The DSP engine RAM address 0x0002 must be set to 0x0700 to begin the first part of the T8532 cali- bration start-up sequence. 8. After 70 ms, all 16 T8532 channels must be put into loopback mode (addresses 0x1508—0x151F and 0x1548—0x154F must be set to 0x8001). 9. The DSP engine RAM address 0x0002 must be set to 0x0720 to begin the second part of the T8532 calibration start-up sequence. 10. After 70 ms, both T8532s should be sent a soft reset (addresses 0x1517 and 0x1557 set to 0x8000) and the all channel test register should be set for normal operation (addresses 0x1510 and 0x1550 set to 0x0004). Normal T8531 operation commences with the next SFS frame sync. The chips are now ready for channels to be enabled and filter coefficients to be set.

2222 Lucent Technologies Inc. Preliminary Data Sheet November 2000Codec Chip Set T8531/T8532 Multichannel Programmable Chip Set Functional Description (continued) Start-Up After Internal Reset (continued) Autocalibration Autocalibration is an analog self-test and trimming pro- cedure controlled by the DSP core. Sine wave signals are generated in the receive direction. These signals are looped back at the analog side of the T8532, and the return signal amplitudes are measured in the trans- mit path. This procedure provides on-the-spot fault coverage of the transmit and receive paths. It also cali- brates the octal devices by modifying the gain on each channel. Channel four of the T8532 is the only channel trimmed at the factory for absolute gain accuracy. When autocalibration is run, all channels are trimmed with reference to channel four. That is, the gain on each channel is adjusted so that its absolute gain is equivalent to that of the trimmed channel. Performing trimming in this manner provides channel-to-channel gain matching of better than 0.01 dB. This is a much better performance than could be achieved using con- ventional trimming. Trimmed values are placed in data storage, and absolute gain values are then modified accordingly any time the absolute gain register is changed. The calibration sequence measures the looped-back power result and compares it to the calibrated channel. The trim window is ±0.2 dB. If any channel exhibits a power value which is greater than ±0.2 dB, the calibra- tion procedure sets a failure flag for that channel. Trim- ming will not be performed on the failed channel, and the channel’s trimmed gain will be left at 0 dB. The failed channel, therefore, is left in its previous state and can still be used. The results of calibration are held in RAM address 0x07F4 for transmit (pass 1) and 0x07F5 for receive (pass 2). A bit is set high for every failed channel. The preceding section discussed the sequence of instructions that must be followed in order to properly configure the T8531 for normal operation. The auto- calibration procedure is mandatory after hardware reset. Tone Plant The following tone plant functions are provided in ROM code in the T8531 device. DTMF Transceiver DTMF generation and detection satisfies LSSGR Sig- naling for Analog Interfaces GR-506 CORE, section 15. Caller Line Identification Called ID transmission is performed as specified in TR- NWT-000031 (CLASS feature: calling number deliv- ery). Call Progress Tones A call progress tone generator is provided. This tone generator complies with Telcordia* GR-506-CORE requirements. * Telcordia is a trademark of Bell Communications Research, Inc.

Lucent Technologies Inc. 23 Preliminary Data Sheet November 2000 Codec Chip Set T8531/T8532 Multichannel Programmable Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational section of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Handling Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (ESD) during handling and mounting. Lucent Technologies employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide stan- dard has been adopted for the CDM. A standard HBM (resistance = 1500 Ω , capacitance = 100 pF) is widely accepted and can be used for comparison. The HBM ESD threshold presented here was obtained by using these circuit parameters: Parameter Symbol Min Max Unit Ambient Operating Temperature T A –40 85 °C Operating Junction Temperature T J –40 125 °C Thermal Resistance, Junction to Case R Θ JC —3 5 °C/W Storage Temperature Range T stg –55 150 °C Power Supply Voltage V DD 4.75 5.25 V Voltage on Any Pin with Respect to Ground V SS –0.25 5.25 V Package Power Dissipation P D —1W HBM ESD Threshold Device Voltage (V) T8531 >1000 T8532 >1000

24 Lucent Technologies Inc. Preliminary Data Sheet November 2000Codec Chip Set T8531/T8532 Multichannel Programmable

Electrical Characteristics

For all specifications: TA = –40 °C to +85 °C, VDD = 5 V ± 5%, unless otherwise noted. Typical values are for TA = 25 °C and VDD = 5 V. Input signal frequency is 1020 Hz, unless otherwise noted. DSP clock frequency is 49.152 MHz. dc Characteristics Table 8. Digital Interface Table 9. Analog Interface

Table 10. T8532 Power Dissipation Table 11. T8531 Power Dissipation

• Powerup current exhibits a negative temperature coefficient.

Table 12. Gain and Dynamic Range

Table 12. Gain and Dynamic Range (continued)

Table 13. Noise (per Channel)

• Measured with a –50 dBm0 activation signal applied to VFXI input of channel under test.

4600 Hz to 7600 Hz

7600 Hz to 8400 Hz

8400 Hz to 50 kHz

Table 14. Distortion and Group Delay

• Varies as a function of bit offset. See Appendix A.

Table 15. Crosstalk

200 Hz ≤ fIN ≤ 3400 Hz; measure at

■ All input signals are defined as VIL = 0.4 V, VIH = 2.7 V, tR < 10 ns, tF < 10 ns. ■ tR is measured from VIL to VIH. tF is measured from VIH to VIL. ■ Delay times are measured from the input signal valid to the output signal valid. ■ Setup times are measured from the data input valid to the clock input invalid. ■ Hold times are measured from the clock signal valid to the data input invalid. ■ Pulse widths are measured from VIL to VIL or from VIH to VIH. Table 16. PCM Interface Timing (See Figure 9.)

2.048 MHz

4.096 MHz

• Card address 0, bit offset 0 assumed.

A is the position of the frame sync pulse in the delayed mode. B is the position of the frame sync pulse in the nondelayed mode. Figure 9. Timing Characteristics of PCM Interface Assuming 2.048 MHz SCK Rate

Table 17. Serial Control Port Timing (See Figure 10.) UPDI and UPCS change at the rising edge of UPCK by the microprocessor and are sampled at the falling edge of UPCK by the DSP. UPDO changes at the rising edge of UPCK by the DSP and is sampled at the falling edge of UPCK by the microprocessor. Figure 10. Timing Diagram for Microprocessor Write/Read to/from the DSP on the Control Interface

processor interface can read any address in the DSP engine RAM space. Table 18. DSP Engine RAM Memory Map

1. This address can address ROM code.

2.For time slots 1—15, the address shown is the first address. Refer to time slot 0 for range information.

1. For channels 1—15, the address shown is the first address. Refer to channel 0 for range information.

Table 18. DSP Engine RAM Memory Map (continued)

1. This address can address ROM code.

2.For time slots 1—15, the address shown is the first address. Refer to time slot 0 for range information.

1. For channels 1—15, the address shown is the first address. Refer to channel 0 for range information.
2. Per-board refers to a function that is common to all 16 channels in a single chip set.

Table 19. T8531 Time-Slot Assignment Memory Map All registers can be written by the microprocessor interface. Bits 4 and 5 default to 1 upon reset.

0 X Enables CTZ

1 X Disables CTZ

Lucent Technologies Inc. 35 Codec Chip Set T8531/T8532 Multichannel Programmable Software Interface (continued) Table 21. T8531 Channel Register Memory Map for Table 22. T8531 Channel Register Memory Map for PWR = 1: powerup—normal operation.

Contents

0x1500 Channel 0 powerup/powerdown register 0x1501 Channel 1 powerup/powerdown register 0x1502 Channel 2 powerup/powerdown register 0x1503 Channel 3 powerup/powerdown register 0x1504 Channel 4 powerup/powerdown register 0x1505 Channel 5 powerup/powerdown register 0x1506 Channel 6 powerup/powerdown register 0x1507 Channel 7 powerup/powerdown register 0x1508 Channel 0 control register 1 0x1509 Channel 1 control register 1 0x150A Channel 2 control register 1 0x150B Channel 3 control register 1 0x150C Channel 4 control register 1 0x150D Channel 5 control register 1 0x150E Channel 6 control register 1 0x150F Channel 7 control register 1 0x1510 All channel test register 0x1517 Single-byte soft reset (no data word) 0x1518 Channel 0 control register 2 0x1519 Channel 1 control register 2 0x151A Channel 2 control register 2 0x151B Channel 3 control register 2 0x151C Channel 4 control register 2 0x151D Channel 5 control register 2 0x151E Channel 6 control register 2 0x151F Channel 7 control register 2 Address Range Memory 0x1540 Channel 8 powerup/powerdown register 0x1541 Channel 9 powerup/powerdown register 0x1542 Channel 10 powerup/powerdown register 0x1543 Channel 11 powerup/powerdown register 0x1544 Channel 12 powerup/powerdown register 0x1545 Channel 13 powerup/powerdown register 0x1546 Channel 14 powerup/powerdown register 0x1547 Channel 15 powerup/powerdown register 0x1548 Channel 8 control register 1 0x1549 Channel 9 control register 1 0x154A Channel 10 control register 1 0x154B Channel 11 control register 1 0x154C Channel 12 control register 1 0x154D Channel 13 control register 1 0x154E Channel 14 control register 1 0x154F Channel 15 control register 1 0x1550 All channel test register 0x1557 Single-byte soft reset (no data word) 0x1558 Channel 8 control register 2 0x1559 Channel 9 control register 2 0x155A Channel 10 control register 2 0x155B Channel 11 control register 2 0x155C Channel 12 control register 2 0x155D Channel 13 control register 2 0x155E Channel 14 control register 2 0x155F Channel 15 control register 2 Bit Number and Function 15 14—0 PWR Not used

Table 24. Bit Map for T8532 Channel Control Register 1 at 0x1508—0x150F and 0x1548—0x154F Table 25. T8532 Control Register 1: Transmit Gain Table 26. T8532 Control Register 1: Analog Termination Impedance

Table 27. T8532 Control Register 1: Digital Loopback Table 28. Bit Map for T8532 All Channel Test Register at 0x1510 and 0x1550 Table 29. Bits 3:0 of T8532 All Channel Test Register at 0x1510 and 0x1550 Read out address provides the previous read or write address to CDO whenever a new address is being written into the register. gated to VRN/VRP, but any transmit signal from VTX is disconnected. A reference voltage on VRTX is still required in this mode.

0 Normal operation

1 Digital loopback

Table 30. Bit Map for T8532 Channel Control Register 2 at 0x1518—0x151F and 0x1558—0x155F SUSEQ = 0: normal operation. SUSEQ = 1: start-up calibration sequence. Table 31. T8532 Control Register 2: Receive Gain Table 32. T8531 Control Register Map Note: A board control word controls a function that is common to all 16 channels of a given chip set.

Table 33. Bits 15:8 of T8531 Board Control Word 1 at 0x1FFE Table 34. Bits 7:0 of T8531 Board Control Word 1 at 0x1FFE All bits in board control register 1 will be zeros upon hardware reset. OSDX2, and OSDX3, respectively. Test modes are for production testing only. output of 3 dBm0. Negative values are two’s complement of positive values.

0 X —————— D e l a y e d d a t a t i m i n g

1 X —————— N o n d e l a y e d d a t a t i m i n g

Table 35. Bits 15:9 of T8531 Board Control Word 2 at 0x1FFC Table 36. Bits 8:0 of T8531 Board Control Word 2 at 0x1FFC ister must still be written after reset. Table 37. Bits 15:0 of T8531 Board Control Word 3 at 0x1FFA Note: For test use only, do not use in normal operation. The default value after hardware reset or powerup is 0. Table 38. Bits 15:0 of T8531 Board Control Word 4 at 0x1FF8 Note: The default value after hardware reset or powerup is A4. Table 39. Bits 15:0 of T8531 Board Control Word 5 at 0x1FF6 Note: The default value after hardware reset or powerup is 0. Table 40. Bits 15:0 of T8531 Reset of Microprocessor Commands at 0x7FFF

1111111111111111 C l e a r a d d r e s s a n d d a t a w o r d s

processor. The total ROM size is 8 Kwords. Table 41. DSP Engine ROM Memory Map

4242 Lucent Technologies Inc. Preliminary Data Sheet November 2000Codec Chip Set T8531/T8532 Multichannel Programmable

Applications

Figure 11 shows a full line card implementation using the T8531/T8532 codec and the L7585 SLIC with inte- grated relays. One T8531 and two T8532 devices sup- port 16 SLIC devices (only one L7585 SLIC is illustrated). Figure 11 portrays only the transmission paths inside the L7585 SLIC. L7585 functionality includes eight solid-state relays, performing ring, test, and break functions, a ring-trip detector, quiet polarity reversal, 14 operating states, and more. For complete functionality of this SLIC, refer to the L7585 data sheet. The analog connection between the SLIC and the codec is direct; no external components are required. The transfer of control data on the octal interface between the T8531 and T8532 devices is also direct. Data is synchronous with OSCK and transmits at a 4.096 MHz rate. The microprocessor control interface is a standard 4-wire serial port connection, micropro- cessor clock (UPCK), chip select (UPCS ), data input (UPDI), and output (UPDO). The T8531 generates a 16 MHz clock for microprocessor use. This clock is always present. The PCM interface consists of a system clock (SCK) input of either 2.048 MHz or

4.096 MHz, an 8 kHz system frame sync (SFS) input,

a system data transmit port (DX), and a system data receive (DR) port. The only external components required by the codec chip set are the power supply decoupling. Decouple as many power supply pins as possible; at a minimum, use one capacitor per device side. 12-3351J(F) * Optional for quiet reverse battery. † 4.096 MHz operation; for 2.048 MHz operation, tie SCKSEL to VSS . Figure 11. Line Card Solution Using the L7585 SLIC

1 MHz

0 VRN0

REF can be replaced by a common voltage reference circuit (see Figure 14). Figure 12. Line Card Solution Using the L9215G SLIC

0.5 Vrms

current limit and loop closure threshold. Figure 13. Line Card Solution Using the L9310G SLIC

100 V—130 V

180 V—330 V

0.7 Vrms for

2.2 Vrms at T/R

46 Lucent Technologies Inc. Preliminary Data Sheet November 2000Codec Chip Set T8531/T8532 Multichannel Programmable Outline Diagrams 64-Pin MQFP 5-5202(F) 14.00 ± 0.20 17.20 ± 0.25 DETAIL A DETAIL B

3.00 MAX

0.80 TYP

0.10 2.55/2.75

0.25 MAX

PIN #1 IDENTIFIER ZONE 17.20 ± 0.25 14.00 ± 0.20 3217 0.30/0.45 0.16 M 0.13/0.23 DETAIL B 0.25 0.73/1.03

1.60 REF

Lucent Technologies Inc. 47 Preliminary Data Sheet November 2000 Codec Chip Set T8531/T8532 Multichannel Programmable Outline Diagrams (continued) 64-Pin TQFP 5-3080 (F) DETAIL A

0.50 TYP

1.60 MAX

0.08 DETAIL B 0.05/0.15 1.40 ± 0.05 10.00 ± 0.20 12.00 ± 0.20 64 49 17 32 10.00 ± 0.20 12.00 ± 0.20 PIN #1 IDENTIFIER ZONE DETAIL A 0.45/0.75 GAGE PLANE SEATING PLANE

1.00 REF

0.25 DETAIL B 0.19/0.27 0.08 M 0.106/0.200

November 2000Codec Chip Set T8531/T8532 Multichannel Programmable Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. N o liability is assum ed as a result of their use or application. No rights under any patent accompa ny the sale of any such product(s) or information. Co pyright © 2000 Lucent Technologies Inc. All Rights Reserved Novem ber 2000 DS01 -028ALC (Replaces D S00-379ALC) For additional information, contact your M icroelectronics Group Account M anager or the following: IN TERNE T: http://www .lucent.com/micro E-M AIL: docm aster@mi cro.lucent.com N . AM ER ICA: M icroelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown , PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CAN AD A: 1-800-553-2448, FAX 610-712-4106) AS IA PACIFIC :M icroelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 C intech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 C HIN A: M icroelectronics Group, Lucent Technologies (C hina) C o., Ltd., A-F2, 23/F, Zao Fong U niverse Building, 1800 Zhong Shan Xi R oad, Shanghai 200233 P. R. Ch ina Tel. (86) 21 6440 0468, ext. 325, FAX (86) 21 6440 0652 JAPAN: M icroelectronics Group, Lucent Technologies Japan Ltd., 7-18, H igashi-Gotanda 2-chom e, Shinagaw a-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EU R OP E: D ata Requests: M ICR O ELECT R ONIC S GR OU P D ATALIN E: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries:G ER MA N Y: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FR AN CE: (33) 1 40 83 68 00 (Paris), SWE D EN : (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN : (34) 1 807 1441 (Madrid)

Ordering Information

Appendix A. Transmit Path Group Delay vs. Bit Offset Receive path group delay is a fixed value and is specified in the data sheet. Note: Bit offset values for partial tim e segm ents w ould increme ntally add to the base data delay value by 488 ns per bit offset for an SC K of 2.048 M Hz and in increm ents of 244 ns per bit offset for an SCK of 4.096 MHz. Table 42. Transm it Path Group Delay vs. Bit Offset