T8302

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T8302 Internet Protocol Telephone Advanced RISC Machine (ARM ® ) Ethernet QoS Using IEEE® 802.1q

Description

The Agere Systems, Inc. Voice over Internet Protocol (VoIP) Phone-On-A-Chip™ solution currently imple- ments a quality of service (QoS) strategy that uses a proprietary voice packet prioritization scheme called Ethernet Quality of Service using BlackBurst (EQuB). This scheme uses an algorithm (implemented in hard- ware) to ensure that voice packets transmitted from the device are given the highest priority on their collision domain. The Phone-On-A-Chip solution will now become more standards based by implementing a QoS strategy that incorporates a software-based IEEE 802.1q tagging protocol for outgoing Ethernet frames. This QoS imple- mentation will utilize an IEEE 802.1q protocol stack from Wind River Systems® and will be integrated into the VxWorks® board support package (BSP) for the T8302 as part of our standard software solution. Virtual local area network (VLAN) tag insertion will be supported on a per-port, per-socket, and global basis. Note: As a result of migrating to this software/standards-based priority scheme, Agere will no longer support its current proprietary hardware-based EQuB scheme. Customers using the Phone-On-A-Chip IP Solution Development Design Kit should be aware of this enhance- ment and should structure their application software accordingly (to incorporate the features provided by the IEEE 802.1q stack). It is hoped that this migration will aid customers of Agere in implementing their own systemwide QoS mecha- nism when designing their end product into an IP network. Additional information may be obtained at the T8300 Phone-On-A-Chip website: http://www.agere.com/phone_chip

Agere Systems Inc. reserves the right to make changes to the product(s) or inform ation contained herein without notice. No liability is assume d as a result of their use or application. Phone-On-A-Chip is a trademark of Agere Systems, Inc. Co pyright © 2001 Agere Systems Inc. All Rights Reserved July 2001 AY01-026IPT (M ust accom pany D S01-213IPT) For additional information, contact your Agere Systems Account Manager or the following: IN TERNE T: http://www .agere.com E-M AIL: docm aster@mi cro.lucent.com N. AM ERIC A: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentow n, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CAN AD A: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC :Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHIN A: Agere Systems (Shanghai) Co ., Ltd., 33/F Jin Mao Towe r, 88 Century Boulevard Pudong, Shanghai 200121 PRC Tel. (86) 21 50471212, FAX (86) 21 50472266 JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chom e, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EU R OP E: D ata Requests: D ATALIN E: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries:G ER MA N Y: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FR AN CE: (33) 1 40 83 68 00 (Paris), SWE D EN : (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN : (34) 1 807 1441 (Madrid) ARM is a registered trademark of Advanced R ISC M achines Limited. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. Wind River Systems and VxWorks are registered trademarks of Wind River Systems, Inc.

T8302 Internet Protocol Telephone Advanced RISC Machine (ARM *)

1 Introduction

Agere Systems’ Phone-On-A-Chip™ IP Solution is a highly-integrated device set that forms the basic building blocks for an internet protocol telephone (IPT), residing on a local area network (LAN). At this time, the IPT consists of two individual ICs, the T8302 IPT_ARM (advanced RISC machine) and the com- panion T8301 IPT_DSP (digital signal processor). This two-device solution comprises the basis for a single-IC integration of the system in the near future. The single-IC implementation will contain the functions of both IPT ICs. For conceptual objectives, features for both ICs are listed in this document. The general-purpose processor IC (IPT_ARM ) controls the system I/O (Ethernet, USB, IrDA, etc.) and provides general telephone control features (LED control, keypad button scanning, LCD module interface, etc.). A block diagram of the IPT_ARM can be found in Figure 2 on page 27. At the heart of the IPT_DSP integrated circuit is Agere Systems’ DSP1627 digital signal processor core. The DSP1627’s high-performance (80 MIPS) and single-cycle multiply accumulate instruction provide excellent support for execution of voice compression/decompression and echo cancellation algorithms. The DSP1627 core and the digital-to-analog (D/A), analog-to-digital converters (A/D), low-pass filters, and audio amplifier circuitry drive stan- dard business telephone handsets and speakerphone hardware. This document describes the general-purpose processor IC T8302 for the IP phone. Throughout this discussion the IC will be referred to simply as IPT_ARM . * ARM is a registered trademark of Advanced RISC Machines Limited.

2 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001

Table of Contents (continued) Contents Page Agere Systems Inc. 3 Data Sheet T8302 Internet Protocol Telephone July 2001 Advanced RISC Machine ( ARM )

Table of Contents (continued) Contents Page 4 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001

Table of Contents (continued) Contents Page Agere Systems Inc. 5 Data Sheet T8302 Internet Protocol Telephone July 2001 Advanced RISC Machine ( ARM )

Table of Contents (continued) Contents Page 6 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001

Table of Contents (continued) Contents Page Agere Systems Inc. 7 Data Sheet T8302 Internet Protocol Telephone July 2001 Advanced RISC Machine ( ARM )

Table of Contents (continued) Contents Page 8 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001

Agere Systems Inc. 15 Data Sheet T8302 Internet Protocol Telephone July 2001 Advanced RISC Machine ( ARM )

1 Introduction (continued)

1.1 PT_ARM Features

The IPT_ARM is a high-performance communications processor; it supports 100 Mbits/s Ethernet, USB, and IrDA, and provides all general system processing functions. The features of the IPT_ARM are as follows: I ARM 940T with ARM 9TDMI 32-bit core processor. I Processor clock speeds up to 57.6 MHz. I Instruction cache, 1K x 32. I Data cache, 1K x 32. I Internal SRAM, 1K x 32. I Two 10/100Base-T Ethernet PHYs. I Ethernet 10/100 repeater capabilities for in-line Ethernet connection from network to PC. I USB host bus interface including isochronous support. I IrDA infrared communications interface. I Asynchronous communications interface. I Serial communications controller and interface. I Parallel I/O up to 16 bits. I LED control interface. I Keyboard scan circuitry. I DMA control for up to four channels. I Four general-purpose timer counters for flexible timing control. I Real-time clock. I SDRAM external memory interface. I FLASH external memory interface. I Interprocessor communication memories for data transfer to the IPT_DSP . I Interprocessor token and interrupt registers for control and communication between the IPT_ARM and the IPT_DSP . I JTAG control for test and debugging. I Implementation in 0.25 µm, 3 V silicon technology. I Packaged in a 272-pin PBGA.

16 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001

1.2 IPT_DSP Features

The IPT_ARM is intended to be used with its companion IC, the audio digital signal-processor integrated circuit (IPT_DSP). The combination of the IPT_ARM and the IPT_DSP provides a powerful solution for the implementa- tion of the IP exchange business phone. The features of the IPT_DSP are as follows: I DSP1627 core with bit manipulation unit. I DSP clock speeds up to 80 MHz. I Instruction ROM, 32K x 16 (zero wait-state at 80 MHz). I Dual-port RAM, 6K x 16 (zero wait-state at 80 MHz). I Internal SRAM, 16K x 16 (single wait-state at 80 MHz). I 16-bit analog-to-digital converter. I Programmable gain amplifier on audio input. I Fixed gain differential microphone input. I Analog input SRAM buffer, 512 x 16. I Timed DMA for analog input SRAM. I Two 16-bit digital-to-analog converters. I Independent simultaneous speaker and handset outputs. I Two integrated differential speaker driver outputs. I Two analog output SRAM buffers, 512 x 16 each. I Two timed DMA outputs for simultaneous handset and speaker audio output. I Low-pass filtering on audio inputs and outputs. I Serial I/O interface. I General-purpose timer counter. I Bit I/O interface. I JTAG test and debugging control. I Implementation in 0.35 µm, 5 V silicon technology. I Packaged in 100-pin TQFP .

2 Pinout Information

Figure 1. 272-Pin PBGA Pin Diagram

19 SPACES

2 Pinout Information (continued)

2.2 Pin List

Table 1. PBGA-272 Package

Table 1. PBGA-272 Package (continued)

26 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001

3 Overview

The IPT_ARM contains several system-level functions that would typically require separate ICs. The following func- tions are implemented on a single IC: a full 32-bit microprocessor with integrated cache, a complete two-port Ether- net subsystem including a two-port repeater, a host USB, IrDA, UART , and SSI communications controllers. In addition, there are general peripheral controllers including parallel I/O, key scanning, and LED control circuitry. The IPT_ARM processor communicates with memory through the AMBA * ASB bus. This bus supports 32-bit word accesses as well as half-word and byte accesses. The AMBA APB bridge provides a flexible interface for communi- cating with the on-chip peripheral devices. The IPT_ARM can be used in a system that meets European Class B emissions requirements. The IPT_ARM block diagram in Figure 2 on page 27 shows the following system blocks: I ARM 940T 32-bit CPU. I AMBA ASB bus for high-performance memory access. I AMBA APB bridge for communication with and control of IPT_ARM peripherals. I Four-channel DMA controller to move data from memory to memory or to/from memory from/to IPT_ARM peripherals. I Interrupt controller with programmable priority for efficient system operation. I Reset/clock management controller with internal PLL circuitry to provide programmable clock frequencies, including a one-second real time clock. I General timer unit with four interval timers and a watchdog timer. I External memory interface with support for SDRAM, FLASH, and SRAM memories. I DSP communications controller with interrupts, token registers, and buffer memories for efficient interprocessor communications. I 1K x 32 internal SRAM for general-purpose storage. I Ethernet MAC. I Two-port Ethernet repeater. I T wo Ethernet PHYs. I USB host controller. I IrDA communications controller. I UART communications controller. I SSI communications controller. I 16-bit parallel port interface. I Key and lamp controller (KLC). I JT AG. * AMBA is a trademark of ARM Limited.

3 Overview (continued)

Figure 2. IPT_ARM Block Diagram

4 INTERVAL TIMERS

1 WATCHDOG TIMER

16 I/O

4 WIRE

125 MHz

3.1 ARM 940T and AMBA Bridge

3.2 IPT_ARM Memory and I/O Map

Table 2. ARM Processor Memory and I/O Map CS2, CS3, and internal SRAM with programmable base addresses.

4 Reset/Clock Management

management controller is shown below.

• Indicates the default position or setting.

Figure 3. Reset/Clock Management Controller Block Diagram as well as an input that can be divided for the system slow clock. The crystal is connected to XLO and XHI. as well as the system SLOW_CLK . dividing EXT_CLK , using the RTC external divider register in systems without a 32 kHz crystal.

57.6 MHz

4 Reset/Clock Management (continued)

I RTC external divider register to generate a slower system clock from EXT_CLK for reduced power dissipation. — PLL prescaler to generate a system FAST_CLK from PLL_CLK . —EXT prescaler to generate a system FAST_CLK from EXT_CLK . I USB prescaler for generating the 48 MHz USB_CLK from PLL_CLK . or from the SLOW_CLK source. I SLOW_CLK switch for selecting SLOW_CLK from either EXT_PROG_CLK or RTC_OSC_CLK . I RTC switch for selecting RTC_CLK from either EXT_PROG_CLK or RTC_OSC_CLK . I FAST_CLK switch for selecting FAST_CLK from either PRESCALE_PLL_CLK or PRESCALE_EXT_CLK . I USB_CLK switch for selecting USB_CLK from either USB_ALT_CLK or PRESCALE_USB_CLK . I External reset output RSTN maintained until released by software. Table 3. Reset/Clock Management Controller Signals RTC_CLK This is the clock output to real-time clock block. BCLK This is the main system clock. KLC_CLK This is the clock that times the KLC block. SDRCK This is the SDRAM clock. a clock source for system and peripheral clocks. USB_AL T_CLK This is an external clock source for USB_CLK . USB_CLK This signal goes to the USB block to clock it. These two signals go to a 32.768 kHz crystal oscillator buffer and generate RTC_OSC_CLK . EXTRTC This signal switches between either EXT_PROG_CLK or RTC_OSC_CLK for RTC_CLK . EN_SDRCK This signal enables the SDRAM clock signal. CMRT This signal is used to switch between FAST_CLK and SLOW_CLK for SYS_CLK .

4.1 Reset/Clock Management Controller Theory of Operation

the clock management register (see Table 7 on page 37) and clock control registers (see T able 10 on page 38).

4.1.1 Reset Operation

There are four reset signals that reset the IPT_ARM core and its peripherals.

1. External reset (EXT_RST )
2. Watchdog timer reset (WDG_RST )
3. Software reset (SOFT_RST )

I POR indicates that the device is reset due to assertion of the powerup reset. I ER indicates that the external reset pin was activated. I SFT indicates a software reset (see Table 11 on page 39). SOFT_RST This is a soft reset input to the reset controller. WDG_RST This is the watchdog timer reset coming from the timer block. EXT_RST This is the external hardware reset. INT_RST This signal resets internal circuitry. RTS0N This signal is used as the external reset output. external interrupt registers in the PIC (programmable interrupt controller) are made. Table 3. Reset/Clock Management Controller Signals (continued)

32 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001 The four conditions are mutually exclusive, and appropriate actions can be taken within the boot code depending on which bit is set. When one of these reset sources becomes active, the appropriate reset source is recorded in the reset status (control/clear) register (see Table 13 on page 40). A reset signal is sent to the ARM 940T core and all of the peripheral blocks are reset. The internal resets are deasserted synchronously with the falling edge of the system clock after the source of the reset is deasserted. The RTS0N pin is maintained active-low until released by software via the reset peripheral control (read, clear, set) register (see T able 14 on page 41). A reset from any of the four sources previously mentioned immediately causes the following: I The clock source is switched to the 11.52 MHz external input with the clock divider set to 1. I The PLL is powered up and its programmable registers are preset. I The EMI (external memory interface) and the peripheral devices are powered up in their default power-on state. (In general, most register bits in the reset/clock management controller are set to a default on state, whereas most peripheral registers are reset to 0. Any exceptions to this will be specifically noted when the register bits are discussed.) I The internal reset signal (INT_RST), as well as the external reset (RTS0N) signal, is asserted immediately when- ever any of the four reset sources are asserted. The external RTS0N signal remains active until cleared in the reset peripheral control register (read, clear, set); see T able 14 on page 41. Deasserting RTS0N is accom- plished by writing 0 to the ERS bit in the reset peripheral control clear register.

4.1.2 Operation of the Clock Switching Logic

The clock switching logic is controlled by software. For example, when switching from the external clock to the PLL clock, the PLLE enable bit in the clock control register (see T able 10 on page 38) is set to 1 to enable the PLL, then the PLLC bit in the clock management register (see T able 7 on page 37) is set to 1. The PLL can be shut down to conserve power by resetting the enable bit (PLLE ).

4.1.2.1 PLL Operation

The PLL oscillator is controlled by PLLE of the clock control register (see Table 10 on page 38). The PLL gener- ates a clock signal when PLLE is set to 1. It typically takes about 30 µs for the PLL oscillator to restart and lock in from the inactive state (with a maximum of 250 µs). The input to the PLL comes from the input clock EXT_CLK . The PLL cannot operate without this external input clock. T o use the PLL clock, first stabilize the clock output and then lock it to the programmed frequency. The clock switch- ing logic waits until lock occurs before switching to the PLL clock. The frequency of the PLL output clock (PLL_CLK ) is determined by the values loaded into the 3-bit N divider and the 5-bit M divider (see Table 12 on page 39). When the PLL clock is selected and locked (by setting PLLC in the clock management register) the frequency of PLL_CLK is related to the frequency of EXT_CLK by the following equation: PLL_CLK = EXT_CLK x (MBITS + 1)/(NBITS + 1) The coding of the Mbits and Nbits is described in T able 12 on page 39. For example: The frequency of PLL_CLK is designed to be 288 MHz in this application. 288 MHz = 11.52 MHz x (24 + 1)/(0 + 1)

Agere Systems Inc. 33 Data Sheet T8302 Internet Protocol Telephone July 2001 Advanced RISC Machine ( ARM ) The default values for MBITS and NBITS in this design are: MBITS = 24 (0x18) and NBITS = 0 (0x0). To use the PLL clock the following steps should be taken by software: I Program MBITS and NBITS . Choose the MBITS and NBITS values in the PLL control register (see Table 12 on page 39) by selecting the lowest value for NBITS and the appropriate value of MBITS required to obtain the desired frequency of the internal clock. I The clock switching logic waits for the PLL to lock before switching to the PLL as the system clock. Any write to the PLL control register (see T able 12 on page 39) resets the lock flag and causes the clock switching logic to switch to EXT_CLK . I The lock-in time depends on the operating frequency and the values programmed for MBITS and NBITS . I The frequency of the PLL output clock (PLL_CLK ) should fall within the range defined in the data sheet. Change the bits in the PLL control register (see T able 12 on page 39) only while the PLL is not providing the internal clock source. I To select PLL as the SYS_CLK , set PLLC in the clock management register (see Table 7 on page 37) to 1. I To deselect PLL as the SYS_CLK , select another clock in the clock management register by setting either CMRT or CMEC to 1. When an external interrupt is encountered while in WFI mode (see Section 4.2.1 on page 35), the system automat- ically switches back to the last fast clock.

4.1.3 Latency

The switch between the EXT_CLK and PLL_CLK is synchronous. This causes the actual switching to take place several cycles after the PLLC or the CMEC bit is changed. During this time, actual code is executed. The PLL is not disabled until the PLLE bit in the clock control register (see T able 10 on page 38) is set to 0. To find out when the switching is complete, poll the clock status register (see Table 8 on page 37).

4.1.4 Real-Time Clock (RTC)

The real-time clock (RTC_CLK ) defaults to a 32.768 kHz clock generated by a crystal oscillator connected at XRTC0 and XRTC1 . The input clock is divided by 32,768 to generate a clock with a one-second period that incre- ments a 29-bit seconds counter. In addition, it can generate interrupts at a programmed time. Some features of the RTC are: I 17-year time interval with 1 second resolution. I Programmed time alarm interrupt. I Clock source selectable between RTC_OSC_CLK and EXT_PROG_CLK . To use a real-time alarm interrupt, the following steps have to take place: 1. The clock source is selected. Either RTC_OSC_CLK or EXT_PROG_CLK . 2. The appropriate seconds value is loaded into the RTC seconds alarm register (see Table 18 on page 44). 3. The RTC clock interrupt is enabled in the RTC interrupt enable register (bit 0 AI ENA) (see T able 22 on page 45). 4. The RTC interrupt status register bit AI (see Table 21 on page 45) is set to 1 when the timer RTC alarm expires.

power is turned off to the IPT_ARM . but this register is not affected by the other reset sources. A block diagram of the real-time clock is shown in Figure 4 below. Figure 4. Real-Time Clock Block Diagram

4.2 Reset/Clock Management Registers

4.2.1 Pause Register

active memory requests. WFI mode is used to conserve power by turning the clocks off. Table 10 on page 38) the SDRAM will not refresh. Valid data must be preserved in the SDRAM. Table 4. Reset/Clock Controller Register Map

T able 5 shows the format of the pause register.

4.2.2 Version ID Register

only. The format of the version ID register is shown in Table 6.

4.2.3 Clock Management Register

the PLL clock or the external 11.52 MHz crystal. T able 7 shows the format of the clock management register. Table 5. Pause Register 0 PAU SE Specifies if the system is in wait-for-interrupt (WFI) mode. If 1, the system is in WFI mode. If 0, the system is in normal mode. Table 6. Version ID Register 0xE000 0010 31:16 Device ID These bits will always contain 0x8302.

4.2.4 Clock Status Register

Table 8. Clock Status Register Table 7. Clock Management Register 5 USBEXT Switches USB clock source (USB_CLK ) to USB_ALT_CLK . If 0, the clock switching logic is not activated. 4 USBPLL Switches USB clock source (USB_CLK ) to the PRESCALE_USB_CLK . If 0, the clock switching logic is not activated. 3 EXTRTC Controls the source of the real-time clock (RTC_CLK ). If 1, the RTC_CLK is driven by the RTC_OSC_CLK . If 0, the RTC_CLK is driven off of the RTC external divider register on EXT_CLK . 2 CMRT CMRT switches the system clock source (SYS_CLK ) to the slow clock (SLOW_CLK ). SLOW_CLK , and then clears this register. If 0, the logic to switch to the SLOW_CLK is not activated. 1 PLLC PLLC switches the system clock source (SYS_CLK ) to the PLL clock. If 0, the logic to switch to the PLL is not activated. 0 CMEC CMEC switches the system clock source (SYS_CLK ) to the external clock (EXT_CLK ). If 0, the logic to switch to EXT_CLK is not activated. 3:2 PFSC Identifies the previous fast clock source (FAST_CLK ); see T able 9 below. (SYS_CLK ); see Table 9 below.

4.2.5 System Clock Source Encoding

T able 9 shows the encoding of the clock sources for the clock status register (T able 8).

4.2.6 Clock Control Register

Table 10. Clock Control Register

4.2.7 Soft Reset Register

Note: Soft reset has no effect on the RTC block. Table 9. System Clock Source Encoding 00 External clock (PRESCALE_EXT_CLK ). 01 Phase-locked loop clock (PRESCALE_PLL_CLK ). 3 ESCE External slow clock enable. external divider register (see Table 15 on page 42). If 0, the real-time clock crystal (RTC_OSC_CLK ) is the SLOW_CLK source. 2 PLLE Enables the PLL. This bit is reset to 1. If 1, CLKOFF mode is active. If 0, CLKOFF mode is not active. Note: CLKOFF should always be set to 1 when using WFI mode.

Table 11 shows the format of the soft reset register.

4.2.8 PLL Control Register

The PLL control register configures the PLL. Table 12 shows the format of the PLL control register. Table 12. PLL Control Register Table 11. Soft Reset Register 31:0 SOFT RESET Writing any value to this register causes a soft reset. 31:12 RSVD Reserved. Tied to 0. 11 BYP ASS Active-high, reset to 0. If 1, PLL output = PLL input. 10:8 NBITS Encodes NBITS. 0 ≤ NBITS ≤ 7. This value is used as a divisor to set the PLL frequency. Actual divisor used is NBITS + 1. 7:6 RSVD Reserved. Tied to 0. If PLL output is 100 MHz—400 MHz then set to 0. If PLL output is 400 MHz—500 MHz then set to 1. 4:0 MBITS Encodes MBITS. 0 ≤ MBITS ≤ 31. This value is used as a multiplier to set the PLL frequency. Actual multiplier used is MBITS + 1.

4.2.9 Reset Status (Control/Clear) Registers

Table 13. Reset Status (Control/Clear) Registers

4.2.10 Reset Peripheral Control (Read, Clear, Set) Registers

eral (clear) register. Table 14 shows the format of the reset peripheral control (read, clear, set) register. 3 SFT SFT identifies the last reset as a soft reset. If 1, a soft reset has occurred. If 0, the last reset was not a soft reset, or the bit was cleared. 2 WR Identifies the last reset as a warm reset (caused by the watchdog timer). If 1, a warm reset has occurred. If 0, the last reset was not a warm reset, or the bit was cleared. 1 POR Identifies the last reset as a powerup reset. If 1, a powerup reset has occurred. If 0, the last reset was not a powerup reset, or the bit was cleared. 0 ER Identifies the last reset as an external reset. If 1, an external reset has occurred. If 0, the last reset was not an external reset, or the bit was cleared.

Table 14. Reset Peripheral Control (Read, Clear, Set) Registers Note: This register is initialized to all zeros on reset except for the ERS (bit 0), which is set to 1 upon reset.

4.2.11 RTC External Divider Register

EXT_PROG_CLK = EXT_CLK/ECD/2. For a pseudo real-time clock of 32727.27 Hz the programmed value for ECD becomes 176 (0xB0). Table 15 shows the format of the RTC external divider register. 17 EREP Ethernet repeater circuit. 14 DCC DSP communications controller. 13 KLC Key and lamp controller. 12 RTC Real-time clock controller. 11 UART Asynchronous communications controller channel 1 to UART adjunct. 10 IrDA Asynchronous communications controller channel 0 to IrDA receiver. 9 USB Universal serial bus controller. 8 PIO Parallel input output controller. 7 SSI Synchronous serial input output controller. 6 DMA Direct memory access controller. 5 INTC Interrupt controller. 2 ITIMR Interval and watchdog timer. 0 ERS External reset bit, (RTS0N ).

Table 15. RTC External Divider Register

4.2.12 RTC Clock Prescale Registers

isters may be set at one time. If more than one bit is set, the lowest order bit set will determine the divisor. Table 16. RTC Clock Prescale Registers 6 D16 Indicates that the prescaler input is divided by 16. If 1, divide the clock by 16. If 0, do not divide the clock by 16. 5 D8 Indicates that the prescaler input is divided by 8. If 1, divide the clock by 8. If 0, do not divide the clock by 8. 4 D6 Indicates that the prescaler input is divided by 6. If 1, divide the clock by 6. If 0, do not divide the clock by 6. 3 D5 Indicates that the prescaler input is divided by 5. If 1, divide the clock by 5. If 0, do not divide the clock by 5. 2 D4 Indicates that the prescaler input is divided by 4. If 1, divide the clock by 4. If 0, do not divide the clock by 4.

Table 16. RTC Clock Prescale Registers (continued)

4.2.13 RTC Control Register

format of the RTC control register. Table 17. RTC Control Register 1 D3 Indicates that the prescaler input is divided by 3. If 1, divide the clock by 3. If 0, do not divide the clock by 3. 0 D2 Indicates that the prescaler input is divided by 2. If 1, divide the clock by 2. If 0, do not divide the clock by 2. 7 ENA Crystal oscillator enable. Enables the analog portion of the crystal oscillator. If 1, the analog portion of the crystal oscillator is active and using current. If 0, the analog portion of the crystal oscillator is not active and is not using current. This bit is set to 0 if the RTC is not being used or bypass mode is set. This bit is set to 1 on reset. 6:5 RSVD These bits are set to 11 on reset. 4 BYP Bypass mode. Bypasses the crystal oscillator circuit. If 1, a crystal is connected between pins XRTC0 and XRTC1 . If 0, the CMOS clock on pin XRTC0 is used directly as the clock input. This bit is set to 0 on reset. If 1, increment of the RTC divider register is enabled. If 0, increment of the RTC divider register is disabled. This bit is reset to 0 on powerup. If 1, the clock is from the crystal, or an external CMOS clock. If 0, the clock is the divided SYSTEM_CLK . This bit is reset to 1 on powerup.

4.2.14 RTC Seconds Alarm Register

the RTC seconds alarm register. Table 18. RTC Seconds Alarm Register

4.2.15 RTC Seconds Count Register

the RTC seconds count register. Table 19. RTC Seconds Count Register

4.2.16 RTC Divider Register

an interrupt illegal write error is generated. Table 20 shows the format of the RTC divider register. 28:0 SA Represents time in clock ticks. 31 UCP Update cycle occurred. If 1, an update cycle occurred during a read access. If 0, the value returned was stable. 28:0 SC Represents time in clock ticks.

Table 20. RTC Divider Register

4.2.17 RTC Interrupt Status Register

4.2.18 RTC Interrupt Enable Register

Table 21. RTC Interrupt Status Register and an update to the seconds counter is about to be made. T o reset this bit write a 1 to it. 0 AI Alarm interrupt. Set when seconds count = alarm register. T o clear this bit write a 1 to it. Table 22. RTC Interrupt Enable Register 1 IWI ENE Illegal write interrupt enable. If this bit and the IWI bit is set, IRQ_RTC will be active.

46 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001

4.3 Operation on Reset

Upon all resets, the reset/clock management controller performs the following: I The PLL is enabled with its default values. I All status register bits are reset to 0, except the reset status (control, clear) register (see Table 13 on page 40) that is set to the appropriate source and the exceptions specifically noted in the register descriptions. I The source clock is set to the external input clock.

Agere Systems Inc. 47 Data Sheet T8302 Internet Protocol Telephone July 2001 Advanced RISC Machine ( ARM )

5 Programmable Interrupt Controller (PIC)

The PIC receives signals from 15 interrupt sources. The PIC groups and prioritizes these signals, and drives the two interrupt signals at the interface to the core. Features of the PIC are as follows: I 15 maskable interrupt inputs. I Two programmable priority groups (IRQ and FIQ). I 15 programmable priority levels.

5.1 Interrupt Controller Operation

The interrupt controller receives 15 interrupt request signals, IRQ[15:1] as input. The ordering of the IRQ signals is purely arbitrary and does not imply any relative priority. The interrupt request enable register, IRER (see T able 27 on page 51) provides a central point where the interrupts are enabled or disabled for the interrupt request status path. In particular, the interrupt signals on input lines IRQ[15:1] are logically ANDed with IRER[15:1], and the results are transferred to the interrupt request status register IRSR (see Table 26 on page 51). At any time, the core can read the IRSR in order to check for pending interrupts. The interrupt priority control registers IPCR[15:1] (see Table 29 on page 52) provide a means by which the rel- ative priority of the interrupts are assigned programmatically. Each IPCR has an index field that contains the num- ber of the interrupt assigned to that particular priority level. The IPCRs have an implicit priority ordering, where IPCR1 has the highest priority, and IPCR15 has the lowest priority. At reset, all of the IPCRs are disabled. The IPT_ARM core interface includes two maskable interrupt request inputs, IRQ and FIQ, where an active FIQ request pre-empts an active IRQ request. Each interrupt is assigned to either the IRQ group or the FIQ group by assigning a 1 (FIQ) or a 0 (IRQ) to TYP of the corresponding interrupt priority control register (see Table 29 on page 52). Each group is handled independently. These inputs are referred to as core IRQ and core FIQ. The following shows a typical setup method for interrupts: I Enable the interrupt in the desired peripheral's interrupt enable register. I Enable the specific peripheral interrupt in the interrupt request enable register IRER (Set); see T able 27 on page 51. I Enable the specific interrupt priority in the interrupt priority enable register IPER (Set); see Table 33 on page 54. I Assign IRQs from the desired peripheral to a priority level (IS) and type (TYP ) using the interrupt priority con- trol register N (see T able 29 on page 52). I When active the interrupt will be displayed in the interrupt request status register. The interrupt in-service register (ISRI or ISRF) contains the encoded value of the current highest priority interrupt. I To get the ARM core to process the interrupt, clear the F or I bit in the ARM current program status register (CPSR). See the ARM 940T T echnical Reference Manual for a register description. I To clear interrupts 3 through 15, remove the source of the interrupt in the peripheral registers. To clear interrupt 1 or 2, write to the C1 or C2 bit in the interrupt request source clear register IRQESCR (see Table 32 on page 54).

5 Programmable Interrupt Controller (PIC) (continued)

Figure 5. Interrupt Controller Block Diagram

5.1.1 Interrupt Registers

responding bit in the IRSR register is reset to 0. Prior to returning from the interrupt service routine, software must clear the interrupt from the block that sources it. interrupt generating level, the interrupt will persist in the IRSR . Table 23. Interrupt Registers IRSR Interrupt request status register (see T able 26 on page 51). IRER Interrupt request enable register (see T able 27 on page 51). IRQSR Interrupt request soft register (see Table 28 on page 52). IPCR Interrupt priority control register (see Table 29 on page 52). ISRI Interrupt in-service register for core IRQ (see Table 30 on page 53). ISRF Interrupt in-service register for core FIQ (see T able 30 on page 53). IRQESCR Interrupt request source clear register (see Table 32 on page 54). IPER Interrupt priority enable register (see T able 33 on page 54). EICR External interrupt control register (see Table 34 on page 55).

The IRQ request signals (for interrupt in-service) are shown in Table 24 below. Table 24. Interrupt Request Signals (IRQ) IRQ3 PPIO software interrupt. IRQ10 Ethernet MAC interrupt. IRQ15 Real-time clock interrupt.

5.2 Programmable Interrupt Controller Registers

Table 25. Programmable Interrupt Controller Register Map

5.2.1 Interrupt Request Status Register IRSR

Table 26. Interrupt Request Status Register IRSR

5.2.2 Interrupt Request Enable Registers IRER (Set, Clear)

IRER bit, the corresponding bit in the interrupt request status register IRSR is cleared. The interrupt request enable registers IRER have a dual mechanism for setting and clearing the enable bits. request enable register IRER. are set to 0 on all reset conditions. T able 27 shows the format of interrupt request enable registers IRER. Table 27. Interrupt Request Enable Registers IRER (Set = IRESR, Clear = IRECR) n* In* IRQn status. Indicates that an interrupt is active from interrupt request n. If 1, there is an active interrupt from interrupt source n. If 0, there is no interrupt pending from interrupt source n. by clearing the interrupt in their corresponding peripheral interrupt registers. n* En Interrupt n enable. Indicates if interrupt n is enabled or disabled. If 1, interrupt n is enabled. If 0, interrupt n is disabled.

5.2.3 Interrupt Request Soft Register IRQSR

Table 28. Interrupt Request Soft Register IRQSR

5.2.4 Interrupt Priority Control Registers IPCR[15:1]

Address 0xE000 1018 corresponds to IPCR1. Addresses follow in order thereafter. These registers are set to 0 on reset. Table 29. Interrupt Priority Control Registers IPCR[15:1] 0 SOFT INTERRUPT If 1, a soft interrupt is active. If 0, a soft interrupt is not active. If 1, the interrupt will be mapped to FIQ. If 0, the interrupt will be mapped to IRQ. 4:0 IS Interrupt source. Assigns an interrupt to the interrupt priority control register. If 00000, there is no interrupt assigned to this priority level. If 00001, IRQ1 is assigned to this priority level. If 01111, IRQ15 is assigned to this priority level.

5.2.5 Interrupt In-Service Registers ISR (ISRI, ISRF)

on page 54) is set. Table 30 shows the format of interrupt in-service registers ISR. Table 30. Interrupt In-Service Registers ISR (ISRI, ISRF)

5.2.6 Interrupt Request Source Clear Register IRQESCR

source clear register IRQESCR. Note: This register reverts back to 0 upon completion of the write. Table 31. Interrupt Source Encoding for Interrupt In-Service Registers

0000000 No Interrupt

0000100 IRQ1

0001000 IRQ2

0001100 IRQ3

0010000 IRQ4

0010100 IRQ5

0011000 IRQ6

0011100 IRQ7

0100000 IRQ8

0100100 IRQ9

0101000 IRQ10

0101100 IRQ11

0110000 IRQ12

0110100 IRQ13

0111000 IRQ14

0111100 IRQ15

Table 32. Interrupt Request Source Clear Register IRQESCR

5.2.7 Interrupt Priority Enable Registers IPER (Set, Clear)

tive to the current interrupt. dently, with no knowledge of the other bits in the IPER. shows the format of the interrupt priority enable registers IPER. Table 33. Interrupt Priority Enable Registers IPER (Set = IPESR, Clear = IPECR) 2 C2 Clear external interrupt 2. Writing a 1 to this bit clears interrupt 2. 1 C1 Clear external interrupt 1. Writing a 1 to this bit clears interrupt 1. n* En Interrupt n enable. Indicates if interrupt at priority n is enabled or disabled. If 1, interrupt at priority n is enabled. If 0, interrupt at priority n is disabled. 0 FRZ Freeze the IRSR (see Table 26 on page 51). If 0, the IRSR value is not frozen and can change if a higher priority IRQ occurs.

5.2.8 External Interrupt Control Registers

mat of the external interrupt control registers. Table 34. External Interrupt Control Registers 4 DAT Interrupt data. A read-only copy of the data on the interrupt pin delayed by three clock cycles. always synchronized when not in this mode. If 1, the external interrupt is asynchronous. If 0, the external interrupt is synchronous. 2 POL Interrupt polarity. Determines the polarity of the external interrupt. If 1, the external interrupt detects a low-to-high transition or high level. If 0, the external interrupt detects a high-to-low transition or low level. 1 SEN Interrupt sense. Determines the sense of the interrupt. If 1, the external interrupt is transition-detect. If 0, the external interrupt is level-sensitive. Reset value is 0. ble I/O functionality on the pin if it is MUXed. If 1, the external interrupt is enabled. If 0, the external interrupt is disabled.

6 Programmable Direct Memory Access (DMA) Controller

The programmable direct memory access (DMA) controller provides four independent high-speed DMA channels. I 32-bit source and destination address pointers. I Up to 64K [bytes/half-words/words] transferred at a time. I Interrupt generation on DMA transfer completion. I Four external DMA request input signals to regulate transfers. I Operates in three modes (explained below). Figure 6. DMA Controller Block Diagram 1

6.1 DMA Operation

Agere Systems Inc. 57 Data Sheet T8302 Internet Protocol Telephone July 2001 Advanced RISC Machine ( ARM )

6 Programmable Direct Memory Access (DMA) Controller (continued)

6.1.1 DMA Transfer Setup Procedure

All DMA transfers are set up by doing the following: I Program the source address through the DMA source address register (see T able 37 on page 64). This is the beginning address where the DMA controller will start the transfer. I Program the destination address through the DMA preload destination start address register (see T able 38 on page 64). This is the beginning address where the source data will be transferred. I Program the transfer count through the DMA preload transfer count register (see Table 40 on page 65). I Program the burst size and number of hold states in the DMA burst and hold count register (see T able 42 on page 66). The DMA releases the bus to allow other masters access to it after each burst by the number of hold states programmed in the DMA burst and hold count register. I Program the appropriate control codes into the DMA control register (see Table 36 on page 62). This includes setting the following: — Peripheral select (PS )—selects Ethernet, IrDA, UART, or SSI for modes 1 and 2. — Circular buffer mode (CBM )—specifies buffer wrapping for mode 1. — Channel mode (CMODE )—selects memory-to-memory (mode 0), peripheral-to-memory (mode 1), or mem- ory-to-peripheral (mode 2). — Software DMA request enable (SDRQ_E )—enables software trigger used in modes 1 and 2. — Software trigger DMA request (SDRQ )—software trigger used in modes 1 and 2. — Channel transfer size (CTS )—selects 8-bit, 16-bit, or 32-bit transfers. — Channel increment source address (CIS)—selects auto source address increment during burst read. — Channel increment destination source address (CID)—selects auto destination address increment during burst write. — Channel start (CS )—begin the transfer. Channel Priority: The DMA controller has the highest priority for accessing the system bus. When bursts are transferred, the DMA channel gets uninterrupted access to the system bus. If hold states are specified, the DMA channel deasserts its bus request signal for one or more cycles following each write access to relinquish control of the system bus to the ARM . DMA channels have a fixed priority, with channel 0 having the highest priority and channel 3 having the lowest pri- ority. Operational Comments: To prepare for a DMA transfer, the required values are to be stored in the registers of one of the DMA channels, but with the start bit (CS ) of the DMA control register (see Table 36 on page 62) set to 0. The transfer begins when the start bit is set to 1. If the transfer completes, the start bit is automatically set to 0. In memory-to-memory mode (mode 0), the core is stalled for the duration of the transfer burst. The maximum burst size is 256 words. For a DMA transfer to or from a FIFO, writing 0 to the start bit prematurely terminates the transfer. When the DMA channel is active, the address and count registers are read but not written. The source and destination addresses satisfy alignment restrictions. If a word is being transferred, address bits 1:0 of the address are 0; if a half-word is transferred, address bit 0 is zero. Failure to follow alignment restrictions causes the transfer to be terminated and an exception fault recorded in the DMA status register (see Table 43 on page 66). The DMA controller transfers up to 64 k-1 [bytes/half-words/words] at a time. Byte transfer to or from internal RAM is available to support data transfer to or from peripheral modules. Mixed size transfers are not supported.

58 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001 6.1.2 DMA Mode 0. Memory-to-Memory in Blocks of Burst Count Size DMA mode 0 (memory-to-memory) is selected by setting CMODE[2:0] of the DMA control register (see Table 36 on page 62) to 000. Memory-to-memory transfers are set up as specified in 6.1.1 DMA T ransfer Setup Procedure. Note: When SDRAM is one of the memory sources, the DMA transfer may be less efficient than ARM controlled transfers utilizing cache because only one word is transferred at a time. I When the start bit (CS ) in the DMA control register (see Table 36 on page 62) is set to 1, the DMA transfer will start immediately in memory-to-memory mode as soon as the DMA ready signal is asserted. I The DMA will start to read, beginning at the address programmed in the DMA source address register (see Table 37 on page 64). Transfers will be made to the address in the DMA destination address register (see Table 39 on page 64), which is preset by writing to the DMA preload destination start address register (see Table 38 on page 64). I The number of items to be transferred is specified in the DMA preload transfer count register (see Table 40 on page 65). I The DMA releases the bus to allow other masters access to it after each programmed burst by the number of hold states (also programmed). Burst count (BCNT[7:0]) and hold count (HCNT[7:0]) are programmed in the DMA burst and hold count register (see Table 42 on page 66). Please note when using DMA to SSI, BCNT[7:0] must be set to 0. I Reads and writes in mode 0 (memory-to-memory) are performed with a data size programmed in the transfer word size bits (CTS ) in the DMA control register (see Table 36 on page 62). Available sizes are 8 bits, 16 bits, or 32 bits. Note: Care should be taken when setting up memory-to-memory (mode 0) transfers to allow for other, needed bus traffic. 6.1.3 Mode 1. Peripheral-to-Memory in Blocks of Burst Count Size DMA mode 1 (peripheral-to-memory) is selected by setting CMODE[2:0] of the DMA control register (see T able 36 on page 62) to 001. Peripheral-to-memory transfers are set up as specified in 6.1.1 DMA Transfer Setup Procedure. I In general, all transfers to/from peripherals should be 32-bit transfers. Valid data should be written into or read from memory from the lower 8 bits, 16 bits or all 32 bits as controlled by the peripheral’s register or buffer size. The supported peripherals for DMA are Ethernet, SSI, IrDA, and UART . The ARM 2DSP and DSP2 ARM buffers may also be treated as peripherals while using the software triggered DMA mode (see Section 6.1.4.1 on page 60). I When the start bit (CS ) in the DMA control register (see Table 36 on page 62) is set to 1, the DMA transfer will start immediately in peripheral-to-memory mode (mode 1) as soon as the DMA ready signal is asserted. In the mixed memory peripheral modes (modes 1 and 2), a software trigger (SDRQ ) can be used to force the DMA to see DMA ready. Circular Buffer Mode (CBM): T wo transfer options are available in mode 1 and they are as follows: I The DMA will transfer until the transfer count, programmed through the DMA preload transfer count register (see T able 40 on page 65), is reached.

Agere Systems Inc. 59 Data Sheet T8302 Internet Protocol Telephone July 2001 Advanced RISC Machine ( ARM ) I Or, the DMA will transfer indefinitely in circular buffer mode until software resets the DMA start bit (CS ) in the DMA control register (see Table 36 on page 62). In circular buffer mode, the transfer will continue as data becomes available from the peripheral as indicated by the DMA ready signal from the peripheral. Circular buffer mode is selected by setting the CBM bit in the DMA control register (see Table 36 on page 62) to 1. CBM Operation: I The buffer size is set by writing to the DMA preload transfer count register (see Table 40 on page 65). I The DMA will then transfer data to the memory as data becomes available from the peripheral until the transfer count TCNT (see Table 41 on page 65) is reached. I The DMA destination address register (see Table 39 on page 64) and the DMA transfer count register (see Table 41 on page 65) will then be rewritten with the preset values stored in their respective preload registers. I The circular buffer reload counter (PCNTx ) in the DMA status register (see T able 43 on page 66) will be incre- mented whenever the transfer loops back to the preset values. I This DMA is gated by the DMA ready signal from the peripheral selected for the transfer. If the DMA ready signal is deasserted before the number of words programmed into the DMA burst and hold count register (see T able 42 on page 66), the burst will halt and the DMA will relinquish the bus for the programmed number of hold states before it will monitor the DMA ready signal again. When the DMA ready signal is reasserted the DMA will request the bus, and will transfer up to burst count again when it receives its bus grant. There is a software controlled DMA mode that does not use the DMA ready signal from the peripheral. This mode is selected by setting the software trigger enable bit (SDRQ_E ) in the DMA control register (see T able 36 on page 62). When the user is sure the number of words set up to be transferred is available in the peripheral's buffer, the DMA is triggered by setting the software trigger DMA request bit (SDRQ ) in the DMA control register (see Table 36 on page 62).The DMA ready signal is not monitored in this mode. If the DMA attempts to transfer more data than can be buffered in the peripheral, data will be lost and questionable results will occur. Notes: Data transfers to memory from the DSP2ARM/ARM 2DSP buffer in the DCC block are much more efficient in this mode, using the peripheral bus address of the DSP2ARM/ARM 2DSP buffer, as opposed to using the memory-to-memory mode (mode 0) and the system bus address of the DSP2ARM/ARM 2DSP buffer. The memory write and buffer read can occur at the same time since they are on different busses in the IPT_ARM , instead of the sequential read-then-write, that occur in the memory-to-memory mode. 6.1.4 Mode 2. Memory-to-Peripheral in Blocks of Burst Count Size DMA mode 2 (memory-to-peripheral) is selected by setting CMODE[2:0] of the DMA control register (see Table 36 on page 62) to 010. Memory-to-peripheral transfers are set up as specified in 6.1.1 DMA Transfer Setup Procedure. I In general, all transfers to/from peripherals should be 32-bit transfers and valid data should be written into or read from memory from the lower 8 bits, 16 bits or all 32 bits as controlled by the peripheral’s register or buffer size. The supported peripherals for DMA are Ethernet, SSI, IrDA, and UART . The ARM 2DSP and DSP2 ARM buffers may also be treated as peripherals while using the software triggered DMA mode (see Section 6.1.4.1 on page 60). I When the start bit (CS ) in the DMA control register (see Table 36 on page 62) is set to 1, the DMA transfer will start immediately in memory-to-peripheral mode (mode 2) as soon as the DMA ready signal is asserted. In the mixed memory peripheral modes (modes 1 and 2), a software trigger (SDRQ ) can be used to force the DMA to see DMA ready . The DCC block does not supply a DMA ready signal to trigger the DMA transfers so the software-triggered DMA mode must always be used for these transfers.

(see T able 40 on page 65), is reached. I Mode 2 does not support circular buffer mode.

6.1.4.1 Software-Triggered DMA Mode

peripheral, data will be lost and questionable results will occur. the memory-to-memory mode (mode 0) and the system bus address of the DSP2ARM/ARM 2DSP buffer. IPT_ARM , instead of the sequential read-then-write, that occur in the memory-to-memory mode. Figure 7. DMA Controller Block Diagram 2

6.2 DMA Registers

Table 35. DMA Controller Register Map

6.2.1 DMA Control Registers for Channels [0:3]

Table 36. DMA Control Registers for Channels [0:3] 14:12 PS[2:0] DMA peripheral select. DMA peripheral select bit encoding.

000 Ethernet

001 IRDA

010 UART

011 SSI*

These hardware ready selects are only valid when SDRQ_E = 0 . grammed as 0) for DMA to SSI. ignored in other modes. A CH_DONEx interrupt will not be generated when CBM is active. If set to 1, CBM is enabled. If set to 0, CMB is disabled. FIFO is emptied, the data will be unknown. 10:8 CMODE[2:0] Channel mode.

000 Memory-to-memory (mode 0)

001 Peripheral-to-memory (mode 1)

010 Memory-to-peripheral (mode 2)

(mode 1) and memory-to-peripheral modes (mode 2). eral-to-memory (mode 1) and memory-to-peripheral modes (mode 2), when SDRQ_E = 1. This bit is automatically cleared by hardware when the transfer is completed.

Table 36. DMA Control Registers for Channels [0:3] (continued)

6.2.2 DMA Source Address Registers for Channels [0:3]

5:4 CTS[1:0] Channel transfer size.

00 Byte

01 Half word (16-bit)

10 Word (32-bit)

11 Reserved

size transfers are not supported. 2 CIS Channel increment source address. If 1, autoincrement source address is active. If 0, autoincrement source address is inactive. burst, the CIS bit should be set to 1. 1 CID Channel increment destination address. If 1, autoincrement destination address is active. If 0, autoincrement destination address is inactive. the burst, the CID bit should be set to 1 especially if CBM = 1.

Table 37. DMA Source Address Registers for Channels [0:3]

6.2.3 DMA Preload Destination Start Address Registers for Channels [0:3]

Table 38. DMA Preload Destination Start Address Registers for DMA Channels [0:3] Table 39. DMA Destination Address Registers for DMA Channels [0:3] This register in not initialized by hardware. This register is not initialized or updated by hardware. This register is not initialized by hardware.

6.2.4 DMA Preload Transfer Count Registers for Channels [0:3]

conditions, the DMA preload transfer count register is set to 0. Table 40 shows the format of the DMA preload transfer count registers. Table 40. DMA Preload Transfer Count Registers for Channels [0:3]

6.2.5 DMA Transfer Count Registers for Channels [0:3]

Table 41. DMA Transfer Count Registers for Channels [0:3]

6.2.6 DMA Burst and Hold Count Registers

the format of the DMA burst and hold count registers. This register is not initialized or updated by hardware. will not occur, however, a CH_DONE x will be generated in response to the start.

Table 42. DMA Burst and Hold Count Registers for Channel [0:3]

6.2.7 DMA Status Register

buffer restart counters. Table 43 shows the format of the DMA status register. Table 43. DMA Status Register nels) arbitrate for control of the ASB. 7:0 BCNT[7:0] Burst count. Specifies the size of the bursts in which the DMA transfer will take place. specified by the CTS bits in the DMA control register (see T able 36 on page 62). Cleared by reset or writing a 1 to this bit. Cleared by reset or writing a 1 to this bit. Cleared by reset or writing a 1 to both bits.

Table 43. DMA Status Register (continued) Cleared by reset or writing a 1 to this bit. Cleared by writing a 1 to this bit. Cleared by reset or writing a 0x11 to these bits. Cleared by reset or writing a 1 to this bit. Cleared by reset or writing a 1 to this bit. Cleared by reset or writing a 0x11 to these bits. Cleared by reset or writing a 1 to this bit. Cleared by reset or writing a 1 to this bit. Cleared by reset or writing a 0x11 to these bits.

6.2.8 DMA Interrupt Register

tions, the DMA interrupt register is set to 0. T able 44 shows the format of the DMA interrupt register. Table 44. DMA Interrupt Register

6.2.9 DMA Interrupt Enable Register

The DMA interrupt enable register contains an 8-bit value that enables the DMA interrupts from each channel. 7 CH_ERR3 DMA channel 3 error interrupt. Set to 1 by hardware on a read or write fault. Cleared by reset or writing 1 to this bit. 6 CH_DONE3 DMA channel 3 transfer interrupt complete. Set to 1 by hardware on transfer complete. Cleared by reset or writing 1 to this bit. 5 CH_ERR2 DMA channel 2 error interrupt. Set to 1 by hardware on a read or write fault. Cleared by reset or writing 1 to this bit. 4 CH_DONE2 DMA channel 2 transfer interrupt complete. Set to 1 by hardware on transfer complete. Cleared by reset or writing 1 to this bit. 3 CH_ERR1 DMA channel 1 error interrupt. Set to 1 by hardware on a read or write fault. Cleared by reset or writing 1 to this bit. 2 CH_DONE1 DMA channel 1 transfer interrupt complete. Set to 1 by hardware on transfer complete. Cleared by reset or writing 1 to this bit. 1 CH_ERR0 DMA channel 0 error interrupt. Set to 1 by hardware on a read or write fault. Cleared by reset or writing 1 to this bit. 0 CH_DONE0 DMA channel 0 transfer interrupt complete. Set to 1 by hardware on transfer complete. Cleared by reset or writing 1 to this bit.

Table 45. DMA Interrupt Enable Register 7 CH_ERR3_E Enable DMA channel 3 interrupt. If set to 1, interrupts are enabled. If set to 0, interrupts are disabled. 6 CH_DONE3_E Enable DMA channel 3 transfer complete. If set to 1, interrupts are enabled. If set to 0, interrupts are disabled. 5 CH_ERR2_E Enable DMA channel 2 interrupt. If set to 1, interrupts are enabled. If set to 0 interrupts are disabled. 4 CH_DONE2_E Enable DMA channel 2 transfer complete. If set to 1, interrupts are enabled. If set to 0, interrupts are disabled. 3 CH_ERR1_E Enable DMA channel 1 interrupt. If set to 1, interrupts are enabled. If set to 0, interrupts are disabled. 2 CH_DONE1_E Enable DMA channel 1 transfer complete. If set to 1, interrupts are enabled. If set to 0, interrupts are disabled. 1 CH_ERR0_E Enable DMA channel 0 interrupt. If set to 1, interrupts are enabled. If set to 0, interrupts are disabled. 0 CH_DONE0_E Enable DMA channel 0 transfer complete. If set to 1, interrupts are enabled. If set to 0, interrupts are disabled.

7 Programmable Timers

7.1 Timers Operation

rate. The interval timer and the watchdog timer functions independently select a count rate. Figure 8 shows the programmable timer architecture. Figure 8. Programmable Timer Architecture Block Diagram

7.2 Interval Timer (IT)

(see Table 53 on page 77) that determines the interval. count rate is selected by programming the interval timer count rate field (ITR) with an index between 0 and 11. (see T able 53 on page 77) is loaded with the IT maximum count register value. enabled, the IT count rate register begins decrementing.

7 Programmable Timers (continued)

the interrupt request enable register (see T able 27 on page 51). I Write 1 to the IxS bit in the timer status register (see T able 50 on page 75) to clear the interval timer status bit. registers are free-running counters that maintain the time-base of the interval measurements. Figure 9. Interval Timer Block Diagram I The IT maximum count register (see Table 53 on page 77) may be read at any time. I Writing the IT maximum count register will cause the IT count register to reset to 0. maximum count register. The status bit will be set every COUNTVALUE + 1 counts of the IT count register.

7.3 Watchdog Timer

within a specified time interval. the watchdog timer is configured to divide the 32 kHz RTC crystal or the system clock.

rate is selected by programming the watchdog timer count rate field (WTR ) with an index of between 0 and 11. trol register (see T able 52 on page 76). This must be done before WTE is set. I Set the watchdog timer WTR bit in the timer control register for the desired reset mode. I Enable the timer by setting the WTE bit in the timer control register. 0xFADE to the WT count register will reset the timer and the count will start counting from 0 again. ister (see Table 27 on page 51). The watchdog timer function is illustrated below. Figure 10. Watchdog Timer Block Diagram count register will also clear the WT status bit.

dog timer count rate field (WTR ) of the count rate register cannot be modified. agement function is set after the microcontroller restarts, if a watchdog timer reset occurred. affected by the external reset pin. If WTR is 0, the watchdog timer resets for all three reasons. 32 kHz clock. If 0, the clock source is the system clock. Note: The watchdog timer functionality should be completely set up before switching to the 32 kHz clock.

7.4 Timer Registers

status, mask , and count rate registers. Table 46. Timer Controller Register Map

7.4.1 Count Rate Register

Table 47. Count Rate Register

7.4.2 Encoding of Interval Timer Count Rates (ITR) and Watchdog Timer Count Rates (WTR)

These values are used to encode the count rate for the watchdog and interval timers. Table 48. Encoding of Interval Timer and Watchdog Timer Count Rates 11:8 ITR Interval timer count rate; see Table 48 below.

7.4.3 WT Timer Count Register

Table 49. WT Count Register

7.4.4 Timer Status Register

ers. Table 50 shows the format of the timer status register. Table 50. Timer Status Register

7.4.5 Timer Interrupt Mask Register

be asserted. T able 51 shows the format of the timer interrupt mask register. based on the programmed count rate value. The value is reset by writing 0xFADE to this register. 11 WTS Watchdog timer interrupt status. register) and the time-out signal is asserted. Write a 1 to this bit to clear it. 3:0 I3S:I0S Interval timer channel status. If 1, the IT count register for the channel has reached 0. Writing a 1 to each of these bits clears the bit.

Table 51. Timer Interrupt Mask Register

7.4.6 Timer Control Register

The timer control register affects the functionality of both the watchdog timer (WT) and the interval timers (IT). T able 52 shows the format of the timer control register. Table 52. Timer Control Register 11 WTM Watchdog timer interrupt enable. If 1, the watchdog timer interrupt is enabled. If 0, the watchdog timer interrupt is disabled. 3:0 I3M:I0M Interval timer channel interrupt enable. If 1, the interrupt is enabled for the interval timer channel. If 0, the interrupt is disabled for the interval timer channel. 14:11 ITE3:ITE0 Interval timer channel enable. If 1, the channel is enabled. If 0, the channel is disabled. 10:9 RSVD Reserved. Must be written with 0s. 8 WTI Watchdog timer interrupt mode. If 1, the watchdog timer generates an interrupt. If 0, the watchdog timer generates a reset. 7:6 RSVD Reserved. Must be written with 0s. If 1, the timer runs off of the 32 KHz clock. If 0, the timer runs off of the system clock. This bit is reset to 1 on powerup reset but is not affected by other resets. This bit can’t be changed once WTE is set.

Table 52. Timer Control Register (continued)

7.4.7 IT Count Registers

the IT count register immediately after programming and again after the timer expires. The bit description in Table 53 is the same for all eight registers listed below. 4 WTR Watchdog timer reset mode. If 1, the timer resets only on powerup or watchdog reset. If 0, the timer resets on all sources of reset. This bit resets to 0 on powerup but is not affected by other types of reset. This bit can't be changed once WTE is set. 3 WTE Watchdog timer enable. Once enabled, the watchdog timer cannot be disabled. If 0, the timer is not enabled. 2:0 RSVD Reserved. Must be written with zeros. Table 53. IT Count Registers 15:0 COUNTVALUE Count value.

8 External Memory Interface (EMI)

desired starting address (base address) and size (up to 64 Mbytes).

8.1 IPT_ARM Processor Memory Map

8.2 External FLASH/SRAM Memory Interface (EMI FLASH)

ing process or full-word reads. I Support for in-circuit reprogramming of external FLASH memory. I One FLASH chip select (FLASH_CS ) for external program memory. I Three general-purpose chip selects (CS1 , CS2 , CS3 ) for external SRAM or I/O peripherals. I Configurable memory maps for FLASH_CS , CS1 , CS2 , CS3 , internal SRAM and SDRAM. I Optional setup cycle, wait-states, and hold-states for each device. I External WAIT pin (EXWAIT ) for slow I/O peripherals. I Supports 8-bit and 16-bit devices on the external bus (FLASH memory must be 16-bit). I Supports ROM/RAM remapping to allow the RAM to be placed at address 0x00000000. setup, wait, and hold state generation.

8.3 EMI FLASH Memory Access

8.3.1 External Write

write data (D[15:0]) goes active during the second cycle. Table 54. IPT_ARM Processor Memory Map pose chip selects CS1 , CS2 , CS3 , and internal 1K x 32 SRAM. 0xC000 0000:0xCFFF FFFF Reserved (for ARM 940T processor). 0xD000 0000:0xDFFF FFFF Reserved. 0xE000 0000:0xEFFF FFFF Peripheral address space. 0xF000 0000:0xFFFF FFFF Reserved.

Agere Systems Inc. 79 Data Sheet T8302 Internet Protocol Telephone July 2001 Advanced RISC Machine ( ARM )

8 External Memory Interface (EMI) (continued)

8.3.2 External Read

During the first cycle of the system clock, the A[23:0] and BE1N signals become valid. If SET (bit 7) of the corre- sponding chip select configuration register is 0, the appropriate chip select (FLASH_CS , CS1 , CS2 , CS3 ) and RDN also go active during this cycle. If an additional cycle of address setup with respect to the chip select RDN is desired, the SET bit can be set to 1, and the chip select and RDN will go active during the second cycle of the sys- tem clock.

8.3.3 Wait-States

During an external read or write, the number of active cycles during each access is determined by the number of wait-states (WS[3:0]) and EXWAIT pin, if it is used. A minimum of 2 wait-states must be programmed for external reads and writes to work properly. WS = 0000 or WS = 0001 are not valid values. Use of the EXWAIT pin (for slow devices) is enabled by setting the WT bit (bit 8) of the appropriate chip select configuration register. The polarity of the EXWAIT pin is programmed by the value of WP [bit 0] in the options register (see T able 65 on page 89).

8.3.4 Hold State

If additional hold time is needed between the chip select going inactive and the start of the next access, one, two, or three hold states may be added by setting HS (bits 5:4) of the corresponding chip select configuration regis- ter to the appropriate value.

8.3.5 Hold Disable

For multiaccess read transactions to a device that requires hold states, it is only necessary to have hold states at the end of the last access and not on each intermediate access. These intermediate hold states are suppressed by setting HD (bit 10) of the appropriate chip select configuration register.

8.3.6 Error Conditions

The following errors are recorded in the status register (see Table 64 on page 88): I MAC register error. If an attempt is made to read/write the Ethernet MAC registers in the 0xE001 0800:0xE001 FFFF range when the PHY is not active (i.e., when the MAC is not receiving its Tx/Rx clocks), a MAC register error occurs, and is recorded in MACRE (bit 15) of the status register. I Alignment error. If a nonaligned word access (with address bits 1:0 being nonzero) or a nonaligned half-word access (with address bit 0 being nonzero) is attempted, an alignment error occurs and is recorded in AE (bit 13) of the status register. I Peripheral subword access error. If a half-word or byte access attempt is made to the peripheral address space (0xE000 0000:0xEFFF FFFF), a peripheral subword access error occurs, and is recorded in PSWE (bit 12) of the status register. I Peripheral code access error. If an opcode fetch is attempted from peripheral address space (0xE000 0000:0xEFFF FFFF), a peripheral code access error occurs and is recorded in the PCAE bit (bit 10) of the status register. I DCC read error. If the ARM processor/DMA controller attempts to read from the ARM 2DSP data buffer (0xE004 0000:0xE004 07FF), a DCC read error occurs and is recorded in the DCCRE bit (bit 9) of the status register.

80 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001 I DCC write error. If the ARM processor/DMA controller attempts to write to the DSP2ARM data buffer (0xE006 0000:0xE006 07FF), a DCC write error occurs and is recorded in the DCCWE bit (bit 8) of the status register. In all of the above cases, the access is aborted. If the ARM processor was making the request, it jumps to the error vector in the vector table and begins executing code from there (refer to the ARM 940T documentation for informa- tion on how the ARM 940T handles errors). If the DMA controller was making the request, a read/write fault is recorded in the DMA status register (see T able 43 on page 66).

Figure 11. EMI FLASH/SRAM Read Interface Timing Diagram CS refers to FLASH_CS/CS1/CS2/CS3. HD = hold disable (HD ) bit 1 in chip select configuration register. HS = hold states (HS [1:0]) bits 5:4 in chip select configuration register, allowed values of HS = 0, 1, 2, and 3. SET = setup bit (SET ) bit 7 in chip select configuration register, allowed values of SET = 0 and 1. WS = wait-states (WS [3:0]) bits 3:0 in chip select configuration register, allowed values of WS = 2, 3, 4—15. 32-bit reads/writes with a bus size of 16 bits/8 bits. 16-bit reads/writes with a bus size of 8 bits. Single access read/write timing looks the same as the last access in a multicycle access. All output parameters assume a 15 pF load. Table 55. EMI FLASH/SRAM Read Access Timing Parameters

Figure 12. EMI FLASH/SRAM Write Interface Timing Diagram CS refers to FLASH_CS/CS1/CS2/CS3. HD = hold disable (HD) bit 1 in chip select configuration register. HS = hold states (HS[1:0]) bits 5:4 in chip select configuration register. Allowed values of HS are 0, 1, 2, and 3. SET = setup bit (SET) bit 7 in chip select configuration register. Allowed values of SET are 0 and 1. WS = wait-states (WS[3:0]) bits 3:0 in chip select configuration register. Allowed values of WS are 2, 3, 4, 5—15. 32-bit reads/writes with a bus size of 16 bits/8 bits. 16-bit reads/writes with a bus size of 8 bits. Single access read/write timing looks the same as the last access in a multicycle access. All output parameters assume a 15 pF load. Table 56. EMI FLASH/SRAM Write Access Timing Parameters Last Access in a Multicycle Write).

8.4 ROM/RAM Remapping

processor exceptions through the vector table. Also, if the vector table is in ROM, it cannot be modified by the code. For these reasons it is preferable to have RAM with the vector table and exception handlers at address 0x0. REMAP bit (bit 12) of the chip select configuration register FLASH_CS (see T able 58 on page 84). aliased copy of ROM to be present at the chip select base address register FLASH_CS . 3:0) of the chip select base address register FLASH_CS . Figure 13. ROM/RAM Remapping

8.4.1 Programmable Addresses

Note: FLASH_CS is active-low..

8.5 EMI FLASH Registers

tem bus errors, and an options register common to all chip selects (FLASH_CS , CS1 , CS2 , and CS3 ).

8.5.1 Chip Select Configuration Register FLASH_CS

Table 58. Chip Select Configuration Register FLASH_CS Table 57. EMI FLASH Register Map writes to these devices are illegal if this bit is not set. If 1, byte enables are used by the device. If 0, no byte enables are used by the device. register FLASH_CS (see Table 62 on page 87). chip select base register FLASH_CS .

Table 58. Chip Select Configuration Register FLASH_CS (continued)

8.5.2 Chip Select Configuration Registers CS1, CS2, CS3

Table 59. Chip Select Configuration Registers CS1, CS2, CS3 10 HD Hold disable. Disables the hold states between accesses in a multicycle read transaction. If 1, hold states are suppressed between the access. If 0, each access is followed by the specified number of hold states. Note: The hold states at the end of the transaction are not suppressed by this bit. 8 WT Enable or disable EXWAIT pin. If 1, the extra setup cycle is added. If 0, the extra setup cycles is not added. writes to these devices are illegal if this bit is not set. If 1, byte enables are used by the device. If 0, no byte enables are used by the device. If 1, the chip select is enabled. If 0, the chip select is disabled.

Table 59. Chip Select Configuration Registers, (CS1, CS2, CS3) (continued) 10 HD Hold disable. Disables the hold states between accesses in a multicycle read transaction. If 1, hold states are suppressed between the access. If 0, each access is followed by the specified number of hold states. Note: The hold states at the end of the transaction are not suppressed by this bit. 8 WT Enable or disable EXWAIT pin. If 1, the extra setup cycle is added. If 0, the extra setup cycles is not added. 6 BS Bus size. The data bus size of the device. If 1, the device supports 16-bit transfers and all 16 bits of the data bus are connected to it. If 0, the device supports 8-bit transfers and bits 7:0 of the data bus are connected to it.

8.5.3 Hold and Wait-States Encoding

Table 60. Hold States Encoding Table 61. Wait-States Encoding

8.5.4 Chip Select Base Address Registers FLASH_CS, CS1, CS2, CS3, Internal SRAM

Table 62. Chip Select Base Address Registers FLASH_CS, CS1, CS2, CS3, Internal SRAM

0000 Illegal Illegal

0001 Illegal Illegal

against the address of the request. Table 63 shows the encoding of the block size field. For CS1 , CS2 , CS2 , and internal SRAM = 0000.

8.5.5 Block Size Field Encoding

Table 63. Block Size Field Encoding

8.5.6 Status Register

Table 64. Status Register the MAC is not receiving its Tx/Rx clocks). Cleared by writing a 1 to this bit. Cleared by writing a 1 to this bit. peripheral address space (0xE000 0000:0xEFFF FFFF). Cleared by writing a 1 to this bit. peripheral address space (0xE000 0000:0xEFFF FFFF). Cleared by writing a 1 to this bit. from the ARM 2DSP data buffer (0xE004 0000:0xE004 07FF).

Table 64. Status Register (continued)

8.5.7 Options Register

Table 65. Options Register

8.6 External SDRAM Memory Interface

I Programmable address shifting to support a variety of SDRAM sizes. I Block or fast-page mode SDRAM accesses. I One external SDRAM memory range.

8.6.1 External SDRAM Memory Map

Table 66. External SDRAM Memory Map to the DSP2ARM data buffer (0xE006 0000:0xE006 07FF). If 1, EXWAIT is active-high.

8.6.2 SDRAM Memory Range Base Address Register

Table 67. SDRAM Memory Range Base Address Register

8.6.3 SDRAM Control Register

Table 68. SDRAM Control Register

8.6.4 SDRAM Timing and Configuration Register

I RAS to CAS delay—set to 1. I CAS to precharge—set to 3. I Precharge to RAS—fixed at 4. Table 69. SDRAM Timing and Configuration Register must be a multiple of the block size. 3:0 BSZ Block size (see Table 63 on page 88). 1 SDRE SDRAM enable. If 1, the SDRAM auto process is enabled.

Table 69. SDRAM Timing and Configuration Register (continued)

8.6.5 SDRAM Manual Access Register

Table 70. SDRAM Manual Access Register 4:3 CCPD Clocks CAS to precharge delay. 11—3, 00—4. Note: Values 01 and 10 are not supported. 1:0 CAB Column address bits: 00—8 column address bits, 0—9 column address bits, 1x—reserved. 18 RAS SDRAM RAS value for manual access. 17 CAS SDRAM CAS value for manual access. 16 WE SDRAM WE value for manual access. 14:0 ADDR SDRAM address bus value for manual access.

8.7 SDRAM Timing

Figure 14. SDRAM Read Timing Diagram

Figure 15. SDRAM Write Timing Diagram

94 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001

8.8 Signals

The EMI controls all the signals needed to access external devices. For transactions that are larger than the width of the device, the EMI creates multiple accesses to read from or write to the device. For example, a 32-bit read from an 8-bit device requires four read accesses. SDRAM, FLASH, and SRAMs share the same address and data bus.

8.8.1 Address, A[23:0]

For FLASH_CS , CS1 , CS2 , and CS3 devices, the address bus signals A[23:0] define the address of the least sig- nificant byte transferred during a memory cycle. The address becomes valid during phase 1 of the first cycle of an access and remains valid until phase 1 of first cycle of the next access. Note: For FLASH and SRAM accesses, A[23:0] is used to access memory in units of bytes. If a 16-bit wide SRAM/ FLASH memory device is used, A[1] should be connected to the least significant address input pin of the memory device. For 8-bit wide FLASH/SRAM devices, A[0] should be connected to the least significant address input.

8.8.2 Data, D[15:0]

Data bus signals D[15:0] are bidirectional signals that transfer data to and from the chip. Use of the upper 8 bits of the data bus is controlled on a per-device basis by BS (bit 6) of the chip select configuration register. Note: The program memory that is accessed by FLASH_CS always uses a 16-bit data bus. During a read access, the data on the data bus is latched at the end of phase 1 of the last active cycle of the access. For a write access, the data becomes valid during phase 1 of the second cycle of the access. If there is no valid transac- tion on the EMI, the data bus stays in input mode.

8.8.3 Byte Enable, BE1N

BE1N is used as a byte write enable for 16-bit devices that use byte enables. This signal is active-low and goes active when an odd byte is to be written. The UBE bit (bit 13) of the chip select configuration register must be set to 1 before attempting byte writes to 16-bit devices.

8.8.4 Read/Write Signals, RDN, WRN

RDN and WRN are active-low signals that indicate whether a read or a write access is taking place. During a read access, RDN goes low and WRN stays high. During a write access, RDN stays high am WRN goes low. If the EMI flash is not being accessed, RDN and WRN stay high.

8.8.5 Chip Selects, FLASH_CS, CS1, CS2, CS3

The chip select signals FLASH_CS , CS1 , CS2 , and CS3 indicate which of the external devices is accessed. The appropriate chip select becomes active during phase 1 of the first cycle of an access if no setup cycle is used and goes inactive after the last active cycle of the access. FLASH_CS is active-low. CS1 , CS2 , and CS3 have program- mable polarities and are active-low at reset.

8.8.6 External WAIT, EXWAIT

This signal can be driven by the external device to add additional wait-states to the memory access cycle, if required. The use of the EXWAIT signal by a particular device is enabled by setting the WT bit (bit 8) of the appro- priate chip select configuration register. The polarity of EXWAIT is programmable, and is determined by the WP bit (bit 0) of the options register; see Table 65 on page 89.

8.8.7 EMI SDRAM, Synchronous DRAM Memory Interface

should be tied off to active.

8.8.8 SDRAM Address Functionality

access cycle, e.g., when used with a 64 Mbit 16-bit wide SDRAM device.

8.8.9 SDRAM Clock, SDRCK

8.8.10 SDRASN, SDCASN, SDWEN

that is to be performed on SDRAM.

8.8.11 SDUDQM, SDLDQM

allow the corresponding byte to be written. (>15 pF) for all the EMI pins. Table 71. SDRAM Access Cycles, Using a 64 Mbit SDRAM Row address strobe (RAS ) A[13: 0] = row address, where A[13:12] = bank select. Column address strobe (CAS ) A[7:0] = column address. Precharge A[10] = precharge mode. If A[10] = 1, all banks are precharged.

9 DSP Communications Controller (DCC)

I ARM (write only) DSP (read-only) 512 x 32 bit internal SRAM for use as a communications mailbox. I ARM (read-only) DSP (write only) 512 x 32 bit internal SRAM for use as a communications mailbox. I Token register to support single owner of memory segments or message headers. I ARM 2DSP interrupt register. I DSP2 ARM interrupt register. I Dedicated I/O pins for single wait-state DSP accesses. I DSP communications controller address map. I IPT_ARM peripheral controller circuits. Figure 16. DSP Communications Controller Block Diagram

9.1 ARM Processor Memory and I/O Map

Table 72. ARM Processor Memory and I/O Map

9 DSP Communications Controller (DCC) (continued)

9.2 DCC Token Register

writable only through the ARM APB bus. The entire 16-bit token register can be read by either interface. Table 73. Token Register

9.3 DCC Interrupt Registers

active-low interrupt output. This interrupt output is to be connected to the IPT_DSP interrupt input (DSP_INT0 ). be set by the IPT_ARM processor. DSP2 ARM _INT and ARM 2DSP_INT can read by both processors. 0 to indicate that it has completed the operation, or freed up the memory. ers where a message, or data, is stored. processor has finished accessing it. they are readable by both the DSP and the ARM . readable by both the DSP and the ARM .

9.3.1 DSP2ARM Interrupt Register

Table 74. DSP2ARM Interrupt Register

9.3.2 ARM 2DSP Interrupt Register

Table 75. ARM 2DSP Interrupt Register 15 DSP2 ARM _INT DSP to ARM interrupt. Interrupt from the DSP to the ARM . 14 INT_CLR Interrupt clear. This will clear the interrupt signal. This is controlled only by the ARM . This is read-only from the DSP . 12:0 INT_MSG Interrupt message. Interrupt message from the DSP . This is read-only from the ARM . 15 ARM 2DSP_INT ARM to DSP interrupt. Interrupt from the ARM to the DSP . 14 INT_CLR Interrupt clear. Interrupt clear will clear the interrupt signal. This is controlled only by the DSP . This is read-only from the ARM . 12:0 INT_MSG Interrupt message. Interrupt message from the ARM . This is read-only from the DSP .

9.4 DCC Controller I/O Signals

The DCC controller has several I/O signals used to support interprocessor communications.

9.5 DSP Read/Write Timing Diagrams

Figure 17. DSP Read Interface Timing Diagram Table 76. DCC Controller I/O Signals tokens, or interrupt registers. DSP_D[15:0] DSP data bus[15:0]. This is the interprocessor data bus. DSP_RWN DSP read/write not strobe. DSP_MCSN DSP chip select. Used to indicate a DSP access of the buffer memories. If A[10] is low the ARM to DSP memory is accessed. If [A10] is high the DSP to ARM memory is accessed. DSP_ICSN DSP chip select. Used to indicate an access of the token or interrupt registers. If A[3] = 0 then it is a token register access. If A[3], A[2] = 10 then it is an ARM interrupt register access. If A[3], A[2] = 11 then it is a DSP interrupt register access. DSP_INTN0 DSP interrupt. Indicates an external interrupt signal to the DSP from the ARM processor.

Figure 18. DSP Write Interface Timing Diagram

10 Ethernet 10/100 MAC

Please refer to Agere’s DNCM01 10/100 Ethernet MAC ASIC Macrocell Data Sheet for references. All the registers inside the MAC controller are read/write through the ARM AMBA peripheral bus interface. address matching on received packets, byte counters, and status bits. Figure 19. Ethernet 10/100 MAC Block Diagram

102 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001

10 Ethernet 10/100 MAC (continued)

10.1 Features

The Ethernet 10/100 MAC provides the following features: I Compliant with ISO* 8802.3 1993, IEEE † 802.3u 1995, and IEEE 802.3x 1995 standards for media access con- trol. I Data transmission and reception rates of 10 Mbits/s at a clock speed of 2.5 MHz or 100 Mbits/s at a clock speed of 25 MHz. I Transmits or receives at full- or half-duplex. I Supports flow control. I Supports both VLAN type1 and VLAN type2 frame recognition. I Extensive network management signals are provided. I Transmit and receive functions can be asynchronously reset with no clocks present. I Supports full internal scan test methodology. I Retransmit capability on early collision detection. I Flexible arithmetic or logical physical address matching. I Queued storage of packet reception status and byte counts for relaxed real-time interrupt latency requirements. I 128 bytes of FIFO buffering in both the transmit and receive directions. I Easy setup of control or pause frame transmission for network control.

10.2 General MAC Information

The IPT_ARM contains an AMBA peripheral bus interface (APB) to the status and control registers contained in the MAC controller. This interface also has a reset signal that will reset the state machines, counters, and critical logic in the MAC and its controller. The MAC contains the MAC transmit status register, the MAC collision counter, and the MAC control frame registers. The MAC transmit status register (see Table 96 on page 116) provides access to output signals that describe the results of the last transmitted or received frame. The MAC collision counter (see Table 97 on page 118) is a 16-bit counter that reports the number of collisions on a transmit attempt. Valid counts are 0 through 15. When the number of collisions is equal to the retry attempt value, RETRY[1:0], an excessive collision error occurs. The MAC collision counter is cleared before each new packet transmission.The MAC control frame registers hold the reserved multicast destination address, source address, reserved length/type field, control opcode, and data. Flow control is implemented by receiving and sending pause (control) frames. The MAC handles the transfer of data from the control registers to the transmit data bus of the MAC. * ISO is a registered trademark of the International Organization for Standardization. † IEEE is a registered trademark of the Institute of Electrical and Electronics Engineers, Inc.

Agere Systems Inc. 103 Data Sheet T8302 Internet Protocol Telephone July 2001 Advanced RISC Machine ( ARM )

10.3 MAC Transmitter

The transmit path consists of a 32x32 FIFO and transmit state machine.The programmer initiates a packet trans- mission by first setting up the DMA to transfer packet data from memory to the transmit FIFO, excluding the pream- ble, SFD , and CRC . The START bit (see Table 95 on page 116) is asserted and packet byte count is loaded into the MAC controller transmit start register (see T able 95 on page 116). It is the responsibility of the host system to keep the transmit FIFO from underrunning. In half-duplex mode, the MAC handles the collisions in accordance with IEEE 802.3u. The MAC controller pre- serves the first 64 bytes of data in the transmit FIFO so that, if there is a collision during the transmission of these bytes, the MAC can retransmit the frame without the host system having to reload the FIFO. If a collision occurs after 64 bytes have been transmitted, the transmission is aborted due to a late collision and an interrupt is gener- ated if it is not masked. The CRC is automatically appended at the end of the data packet and transmitted. An interrupt will be generated at the end of a packet transmission to notify the processor about the successful or unsuccessful packet transmission. If the interrupt is masked, then the host should monitor the MAC transmit status register (see Table 96 on page 116) to determine when the transmitter is finished with the packet transmission.

10.4 MAC Receiver

The programmer sets up the IPT_ARM to receive Ethernet packets by programming the MAC controller setup register (see T able 78 on page 106) and address matching registers to determine which packets to accept and to set up the circular input buffer in the IPT_ARM DMA block. If the receiver is enabled the incoming packets are accepted and stored if they match the receive criteria. The MAC can operate in a hardware flow control environment. When operating in full-duplex mode, if a pause frame is received, the MAC controller waits for the time the sender wishes the MAC not to transmit. In addition, the MAC controller also monitors the presence of VLAN type1 and type2 fields. If one of them is present, the maximum legal frame length is extended. An interrupt will be generated (if enabled) on a successful or unsuccessful packet reception and the status and byte count of the received packet will be placed in the receive control FIFO. This information can be used by the programmer to determine the amount of data written into the DMA input circular buffer and to determine the validity of this data.

10.4.1 Address Matching Registers

The IPT_ARM has the capability of storing only those packets that meet predefined destination address criteria programmed in 32 pairs of address match memory locations. Address match memory location 0 (memory loca- tions 0XE001 0B00 and 0XE001 0B04) should be programmed with the endpoint's MAC address (the low-order 32 bits of the MAC address go in 0XE001 0B00 and the high-order 16 bits go in the least significant 16 bits of 0XE001 0B04). When the MAC receiver is not in promiscuous mode (PROMM = 0), received unicast packets will only be written to the MAC receive FIFO if their destination addresses match the 48-bit value stored in address match memory location 0. Address match memory locations 1 to 31 (locations 0XE001 0B08 to 0XE001 0BFC) can be used to store up to 31 multicast addresses. These locations are paired in the same way that address match memory location 1 is; the low-order 32 bits of the multicast address go in the first memory location of the pair and the high-order 16 bits go in the least significant 16 bits of the second memory location of the pair. When the MAC receiver is not in the store-all multicast packets mode (SAMUL = 0, see T able 78 on page 106), received multicast packets will only be written to the MAC receive FIFO if their destination addresses match one of the thirty-one 48-bit values.

104 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001

10.5 MAC Controller, Registers, and Counters

There are several registers and counters in the MAC controller. The registers include control setup registers, control registers, and status registers. There are thirty-two 48-bit address matching registers that are used to determine whether received multicast packets are stored. Location 0 in the address match memory registers is always reserved for the MAC’s physical address. The remaining registers are used to store multicast addresses that are compared against received packet destination addresses. If there is a match, the packet is stored. If store-all multicast packets mode is selected (SAMUL set to 1 in the MAC controller setup register; see T able 78 on page 106) all multicast packets will be stored without regard to values in the address match registers. If promiscuous mode is selected (PROMM set to 1 in the MAC controller setup register), all packets are stored (no address matching is performed). The counters are used to control the MDIO interface to the PHYs, assemble and send pause control frames, and recognize VLAN packets.

10.6 Control Frame Operation

The MAC supports control frame transmission and automatic pause control frame response for use in flow-control of full-duplex networks. In the transmit direction, the MAC can transmit control frames to the far end without having to go through the process of writing to the transmit FIFO. This is done by programming register addresses 0XE001 000C to 0XE001 002C with the control frame information and then setting the CNTLXMIT bit (in the MAC controller transmit control register) to initiate transmission. In the receive direction, the MAC will respond to the reception of pause commands by pausing the MAC transmitter for the requested number of bit times. T o enable this automatic pause response, register addresses 0XE001 000C to 0XE001 0028 must be programmed with the proper values for a pause command. See Tabl e 8 1— Tabl e 8 5 for more information.

Table 77. MAC Register Map Address match memory locations 1 through 31 (multicast address). bits hold the high-order 16 bits of the multicast address.

10.7 Register Descriptions

10.7.1 MAC Controller Setup Register

send or receive data from the MAC and FIFOs. Table 78. MAC Controller Setup Register (SPEED_SEL = 11) is an invalid setting and SPEED_SEL = 00, 01 or 10 should be used.

00 MDC = PCLK/64

01 MDC = PCLK/32

10 MDC = PCLK/16

11 MDC = PCLK/8

13 SBCSTP Store broadcast packets. If 1, all broadcast packets are stored. If 0, no broadcast packets are stored. 12 SAMUL Store all multicast packets. Indicates that all multicast packets should be stored. 10 TMODE Reserved for factory testing. This should be programmed to 0. mal CRC is inverted prior to transmission. If INVCRC is high, the normal CRC is reinverted prior to sending, forcing a CRC error. cycles and attempts to retransmit after 96 bit times (normal IFG). If DEFER is low, the transmitter defers indefinitely.

Table 78. MAC Controller Setup Register (continued) If high, the SQE error flag will not be set. 5 MFDUP MAC full duplex (active-high). Used to control half- or full-duplex operation. employed if collisions occur during transmission. the end of transmitted packet. If high, the CRC is appended. the start of frame delimiter.

10.7.2 MAC Packet Delay Alarm Value Register

Table 79. MAC Packet Delay Alarm Value Register

10.7.3 MAC Controller Interrupt Enable Register

Table 80. MAC Controller Interrupt Enable Register ter (see T able 94 on page 115). An interrupt will be generated when the late status bit is set, if enabled. 15 RSGPI Good packet interrupt enable. Received and stored good packet interrupt enable. 14 RSBPI Bad packet interrupt enable. Received and stored bad packet interrupt enable. 11 DFOVR Data FIFO overflow. Receive data FIFO overflow interrupt enable. 10 CFOVR Control FIFO overflow. Receive control FIFO overflow interrupt enable. 9 CFF Control FIFO full. Receive control FIFO full interrupt enable. 8 CFNE Control FIFO not empty. Receive control FIFO not empty. 7 TGPI Transmitted good packet interrupt. T ransmitted good packet interrupt enable. 5 TPLI Transmit packet late interrupt. Transmit packet late interrupt enable. 4 ECI Early collision. Early collision detect interrupt enable. 3 LCI Late collision. Late collision detect interrupt enable. 2 EXDEFI Excess deferral. Excess deferral interrupt enable. 1 EXCOLI Excess collision. Excess collision interrupt enable. 0 DFUND Transmit data FIFO. Transmit data FIFO data underrun interrupt enable.

10.7.4 MAC Control Frame Destination Address Registers

Table 81. MAC Control Frame Destination Address Registers

10.7.5 MAC Control Frame Source Address Registers

Table 82. MAC Control Frame Source Address Registers These bits are only valid for full-duplex mode. field of the outgoing frame. See the CNTLXMIT bit description in T able 95 on page 116.

10.7.6 MAC Control Frame Length/Type Register

Table 83. MAC Control Frame Length/Type Register

10.7.7 MAC Control Frame Opcode Register

Table 84. MAC Control Frame Opcode Register the outgoing frame. See the CNTLXMIT bit description in Table 95 on page 116. values for automatic pause response are: 0xE001 0024:0x8808. outgoing frame. See the CNTLXMIT bit description in T able 95 on page 116. automatic pause response are: 0xE001 0028:0x0001.

10.7.8 MAC Control Frame Data Register

Table 85. MAC Control Frame Data Register

10.7.9 VLAN Type1 Type/Length Field Register

Table 86. VLAN Type1 Type/Length Field Register

10.7.10 VLAN Type2 Type/Length Field Register

Table 87. VLAN Type2 Type/Length Field Register

10.7.11 MAC Transmit FIFO Register

Table 88. MAC Transmit FIFO Register 15:0 CP ARAM MAC control parameters. Two octets hold MAC control opcodes specific parameters. 15:0 TYPE[15:0] VLAN type1 (read/write). VLAN type1 type/length field value. 15:0 TYPE[15:0] VLAN type2 (read/write). VLAN type2 type/length field value. 31:0 DATA Data (Write only). 32-bit data written to this FIFO is transmitted out, LSB first.

10.7.12 MAC Receive FIFO Register

Table 89. MAC Receive FIFO Register

10.7.13 MAC Receive Control FIFO Register

Table 90. MAC Receive Control FIFO Register 31:0 DATA Data (read-only). Data received into this register, LSB first. Valid on the positive edge of RX_CLK . 1518 bytes, and that the packet had a bad CRC or FAE . Valid on the positive edge of RX_CLK . the positive edge of RX_CLK . Dribble bits have no effect. remainder equal to 0 (integral number of octets), and that the packet had an incorrect CRC . Valid on the positive edge of RX_CLK . (including CRC ) <64, and the packet had a good CRC . Valid on the positive edge of RX_CLK . (including CRC ) <64, and the packet had a bad CRC or FAE . Valid on the positive edge of RX_CLK .

Table 90. MAC Receive Control FIFO Register (continued) 1518 bytes, and the packet had good CRC . Valid on the positive edge of RX_CLK . was 0, and that at least 6 bytes of data were received. Valid on the positive edge of RX_CLK . address bits were not 1, and that at least 6 bytes of data were received. Valid on the positive edge of RX_CLK . 22 BROAD Received broadcast address. Indicates that all 48 address bits of a received frame are 1. Valid on the positive edge of RX_CLK . Valid on the positive edge of RX_CLK . Valid on the positive edge of RX_CLK . address, length/type field, and opcode for the pause operation. Valid on the positive edge of RX_CLK . This signal is set if there is a nonzero match. This signal is set if there is a nonzero match. the next frame, synchronous with RXC . RXEOP can be used to strobe RXEROUT . 15:0 RXCOUNT Receive byte count. Receive byte count at end of packet.

10.7.14 MDIO Address Register

Table 91. MDIO Address Register

10.7.15 MDIO Data Register

Table 92. MDIO Data Register 15:11 PHY[4:0] PHY address. These bits tell which of the 32 possible PHY devices are being accessed. 10:6 REG[4:0] MII register. These bits select the desired MII register in the selected PHY device. 5:2 RSVD Reserved. These bits are reserved and must be set to 0. value to be written to the PHY before a MDIO write operation.

10.7.16 MAC PHY Powerdown Register

Table 93. MAC PHY Powerdown Register

10.7.17 MAC Controller Transmit Control Register

Table 94. MAC Controller Transmit Control Register 1 PHY1 PHY1. Read/write. If 1, power down. 15 RXMT Reset transmit. Must be written to 0 before attempting to use transmitter. 14 RRND Reset random counter (write 1, then write 0). 5 TRME Transmitter enable. Set to 1 to enable transmission of packets. register addresses 0xE001 0014 to 0XE001 002C will be transmitted. APNDCRC and INVCRC inputs are followed. This bit is held high for two TX_CLK cycles, then self-clears. 1 REST ARTFIFO Restart FIFO. This bit only resets the read pointer of the transmit FIFO. 0 RSTFIFO Reset FIFO. This bit resets both the read and write pointers of the transmit FIFO.

10.7.18 MAC Controller Transmit Start Register

Table 95. MAC Controller Transmit Start Register

10.7.19 MAC Transmit Status Register

Table 96. MAC Transmit Status Register reset by the MAC controller when packet transmission is terminated. more than 24,288 bit times for the medium to become not busy. Valid on the positive edge of TX_CLK . The assertion of this bit is temporary. 24,288 bit times during transmission. Valid on the positive edge of TX_CLK . Valid on the positive edge of TX_CLK . the transmission of the previous packet. Valid on the positive edge of TX_CLK . are also valid if CERR is active. Valid on the positive edge of TX_CLK . is temporary; it may not be held long. Valid on the positive edge of TX_CLK .

Table 96. MAC Transmit Status Register (continued) bit times while the transmitter is active and in half-duplex. Valid on the positive edge of TX_CLK . before completion. This signal is cleared prior to the start of the next packet. Valid on the positive edge of TX_CLK . sion of the first bit of preamble. Valid on the positive edge of TX_CLK . Valid on the positive edge of TX_CLK . input is high. This signal is only useful during test. Valid on the positive edge of TX_CLK . after the reception of a pause command. This output is synchronous with TXC . VLAN type2 type/length field register. This signal is set if there is a nonzero match. VLAN type1 type/length field register. This signal is set if there is a nonzero match. the following frame, synchronous with TXC. TXEOP can be used to strobe TXBROAD . TXBROAD is active if the transmitted frame has a destination address of all ones. the following frame, synchronous with TXC . TXEOP can be used to strobe TXMULT . mitted address bit a 1, and at least one of the following 47 address bits a 0.

10.7.20 MAC Collision Counter

Table 97. MAC Collision Counter

10.7.21 MAC Packet Delay Counter

Table 98. MAC Packet Delay Counter

10.7.22 MAC Transmitted Packet Counter

Table 99. MAC Transmitted Packet Counter

10.7.23 MAC Transmitted Single Collision Counter

Table 100. MAC Transmitted Single Collision Counter This counter is reset to 0 when the transmit start bit is set. 15:0 TXPCOUNT TX packet count value. The 16-bit value is a running counter of all packets transmitted. transmitted with a single collision.

10.7.24 MAC Transmitted Multiple Collision Counter

Table 101. MAC Transmitted Multiple Collision Counter

10.7.25 MAC Excess Collision Counter

Table 102. MAC Excess Collision Counter

10.7.26 MAC Packet Deferred Counter

Table 103. MAC Packet Deferred Counter

10.7.27 MAC Controller Receive Control Register

Table 104. MAC Controller Receive Control Register ets transmitted with multiple collisions. are terminated due to excess collisions. are terminated due to excess deferral. 1 RRCV Reset receive. Resets MAC receiver state machines. Must be written to 0 to remove reset. 0 RCVE Receiver enable. Set to 1 to enable reception and storage of packets.

10.7.28 MAC FIFO Status Register

Table 105. MAC FIFO Status Register

10.7.29 MAC Controller Interrupt Status Register

Table 106. MAC Controller Interrupt Status Register 8 CFOVR Control FIFO overflow. 7 RFF Receive data FIFO full. 6 RFHF Receive data FIFO half full. 5 RFE Receive data FIFO empty. 4 RFOVR Receive data FIFO overflow. 3 TFF T ransmit data FIFO full. 2 TFHF T ransmit data FIFO half full. 1 TFE T ransmit data FIFO empty. 0 TFUND T ransmit data FIFO underrun. 15* RSGPI Good packet interrupt. Received and stored good packet interrupt. 14* RSBPI Bad packet interrupt. Received and stored bad packet interrupt. 11* DFOVR Data FIFO overflow. Receive data FIFO overflow. 10* CFOVR Control FIFO overflow. Receive control FIFO overflow. 9 CFF Control FIFO full. Receive control FIFO full. 8 CFNE Control FIFO not empty. Receive control FIFO not empty. 7* TGPI Good packet interrupt. Transmitted good packet interrupt.

Table 106. MAC Controller Interrupt Status Register (continued) both Ethernet ports are down or when the repeater is disabled will generate an ARM data abort. the Ethernet ports, the repeater should first be enabled.

10.8 Signal Information

10.8.1 MII MAC I/O Signals

5* TPLI Packet late interrupt. Transmit packet late interrupt. 4* ECI Early collision detect. Early collision detect interrupt. 3* LCI Late collision. Late collision detect interrupt. 2* EXDEFI Excess deferral. Excess deferral interrupt. 1* EXCOLI Excess collision. Excess collision interrupt. 0* DFUND FIFO data underrun. Transmit data FIFO data underrun interrupt. to a ROL has no effect at all. Table 107. MII MAC I/O Signals RX_DV I Receive data valid. Used to indicate that the data on RXD is valid. transmitter and timer logic. TXD[3:0] O T ransmit data. 4-bit nibble with data to be transmitted. TX_ERR O T ransmit error. Indicates a transmit error. TX_EN O T ransmit enable. Indicates that the data on the TXD[3:0] lines is valid. MDIO BI Management data. This is bidirectional management data for an external device.

Table 108. DMA Interface Signals TX_DMA_RDY O T ransmit DMA ready. This signal is asserted when the TX FIFO is less than half-full. When it is asserted, DMA will transfer data from memory to the MAC TX FIFO. This signal is deasserted when the TX FIFO becomes full. half-full. MAC will transfer data from RX FIFO to memory when this signal is asserted. at the end of packet indication.

matic speed mismatch protection. I An ARM AMBA peripheral interface to configure the internal registers. I Supports 802.3u 1995 class I repeater specifications for 100Base-TX, -FX, and -T4. I On-chip receive FIFO retimes data for single-clock synchronous systems. directly to the MAC, then places the repeater and PHY1 in sleep or low-power mode. Figure 20. Repeater Slice and Backplane Segment Block

124 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001 11 10/100 2-Port Repeater and Backplane Segment Controller (continued)

11.1 MII Transmit and Receive Interface

The transmit and receive interface has three major sections: the repeater slice, the PHY interface, and the back- plane interface.

11.1.1 Repeater Slice Interface

There is a 2-channel repeater slice: slice 0 and slice 1. Slice 0 is connected to the master PHY going to the net- work. The master clocks are generated from PHY 0. Slice 1 is connected to the slave PHY going to the personal computer. The repeater provides a centralized hub that retransmits incoming data simultaneously upon reception while retiming and strengthening the signal. Management software or hardware will need to ensure that the ports that feed a segment have the same speed. The repeater core, that includes the repeater state machine, the partition state machine, and the event generator, controls data flow in both directions. I The repeater state machine enables the device to operate properly according to the IEEE Standard 802.3u 1995 including collision detection and fragment extension. I The partition state machine monitors the receive data stream for excessive and long collisions and disables receipt from the port if collision count or length thresholds are exceeded. Partitioning can be disabled by setting DAP of the port configuration register 0 to 1 (see Table 117 on page 136).

11.1.2 PHY Interface

In 100 Mbits/s mode, the PHY interface conforms to the IEEE 802.3 media-independent interface definition. On the receive side, RXDx is clocked onto the repeater slice using the recovered clock from the PHY , RX_CLK , when RX_DVx is asserted. It also accepts and forwards RX_ERx as part of the data stream to the backplane. On the transmit side, TXDx, TX_DVx , and TX_ERx are clocked out using the 25 MHz TX_CLK clock. Alternatively, an internal 25 MHz clock can be used to transfer data and control to the PHY via a register bit in the global configuration register (see T able 115 on page 135). The COL signal from the PHY (see Table 110 on page 129) is monitored for collisions on the link, and the CRS signal is monitored for the presence of a received carrier. In 10 Mbits/s mode, data is transferred to and from the PHY using a 7-pin serial data interface. Data and envelope information are received from the PHY on RXD[0] and CRS in combination with RX_CLK , respectively. Data and envelope information are transmitted to the PHY on TXD[0 ] and TX_EN with TX_CLK , respectively. The 10 Mbits/s mode will always use the TX_CLK input to transfer data to the PHY . The COL pin is monitored by the repeater slice for collision presence. The repeater slice interfaces to 10 Mbits/s PHYs with a 7-pin serial interface, and to 100 Mbits/s PHYs with the standard MII interface. As previously mentioned, there is an option in 100 Mbits/s mode to use an internal 25 MHz clock to transfer data and control to the PHY . This is controlled via TXCPIN in the global configuration register (see T able 115 on page 135).

Agere Systems Inc. 125 Data Sheet T8302 Internet Protocol Telephone July 2001 Advanced RISC Machine ( ARM ) 11 10/100 2-Port Repeater and Backplane Segment Controller (continued) Port configuration register bit CRSDELA Y (see Table 117 on page 136), sets a delay for the start of preamble regeneration from the receipt of CRS from the PHY . CRSDELA Y should be set to its default value of 0x4, except for T4 applications. Due to the variability of T4 receivers and the requirement for accurate preamble regeneration on the transmit side, the CRSDELA Y value sets up a count between 0 and 7 for use in tweaking the start of preamble. Depending on the phase relationship between MAINCLK and RX_CLK , simulation may show the repeater working with a value of one less than this calculated value. This is the worst case and therefore is a proper calculation. The following formula should be used to calculate the proper value for CRSDELAY : CRSDELAY value = [(Maximum number of preamble nibbles received from PHY) – 11] + (CRS to RX_DV delay/40 ns rounded up) Example 1: All 14 possible preamble nibbles are received from the PHY . The maximum delay from CRS active to RX_DV active is 41 ns. CRSDELAY value = (14 – 11) + 1 = 4 Example 2: A maximum of 10 of the 14 possible preamble nibbles are received from the PHY . The maximum delay from CRS active to RX_DV active is 40 ns. CRSDELAY value = (10 – 11) + 1 = 0 If the above calculation results in a negative number, use zero for CRSDELAY . If all 14 preamble nibbles are received from the PHY , the maximum CRS active to RX_DV active allowable delay is 160 ns.

11.1.3 Backplane Interface

The architecture of the repeater slice requires the use of external interconnection circuitry (backplane) that must include at least a switch matrix to form a complete repeater unit. The receive path of each port of the chip is in no way coupled to the transmit path of any port as far as the data path is concerned. It is assumed that the repeater slice will interface to an external device, which in turn will be responsible for creating the collision domains to which the repeater slice repeater ports attach. The backplane segment provides this switch function. The backplane segment contains one 10 Mbits/s internal segment and one 100 Mbits/s segment. Each repeater slice port feeds the 10 Mbits/s or the 100 Mbits/s data to the backplane segment. Optionally, the backplane seg- ment 10 Mbits/s can be converted to a 100 Mbits/s segment, so that two 100 Mbits/s segments exist. When the 10/100 Mbits/s segment is configured for 100 Mbits/s operation, there can be no 10 Mbits/s segment connections since only two segments exist. Regardless of which operating mode is selected, it is assumed that data will be looped back to all ports on the same segment, including the port that is sourcing the data. It also provides a nibble mode MAC interface for both 10 Mbits/s and 100 Mbits/s operations. The assignment of the port to a segment depends on the per-port SPD_SEL pin.

11.1.3.1 MAC Interface

The backplane segment MAC interface provides a connection to the repeater slice and backplane. In 100 Mbits/s mode, the MAC interface is the nibble-wide MII interface running at 25 MHz as described in IEEE 802.3u 1995, section 22. The backplane segment MAC interface looks like the PHY interface to the attached MAC device. In 10 Mbits/s mode, the MAC interface is a serial NRZ interface running at 10 MHz or a nibble-wide MII interface at 2.5 MHz. The NIB10 pin (see Figure 20 on page 123) selects the option of serial or nibble for the 10 Mbits/s MAC port.

126 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001 11 10/100 2-Port Repeater and Backplane Segment Controller (continued)

11.1.4 Receive Path

The following are the two functional blocks between the PHY MII and backplane interfaces in the receive path: I Elasticity buffer (EB). The elasticity buffer is used to retime the data before it is sent to the backplane. In 100 Mbits/s mode, the data exiting the EB is synchronous to the MSTCLK . In 10 Mbits/s mode, data is synchro- nized to CLK10 . I Receive control interface. The receive control interface provides a point of control for the repeater state machine over the received data stream.

11.1.5 Transmit Path

The transmit path consists of the transmit control interface that provides a point of control for the repeater state machine over the transmitted data stream. TX_CLK from the PHY , or optionally an internally generated 25 MHz clock, is used to clock out data to the PHY .

11.2 Input Clocks

T wo clocks are required to operate the backplane segment. These clocks are also required to operate the repeater slice. I The 10 MHz clock should be phase-aligned to the repeater slice’s 10 MHz clock within ±1 ns. I The 25 MHz clock’s input must be phase-aligned to the repeater slice’s 25 MHz input. The rising edge of the 25 MHz clock should not be skewed by more than ±1 ns between the repeater slice and the backplane segment devices.

11.3 Repeater Slice Theory of Operation

11.3.1 Repeater Core

IEEE 802.3 clause 27, defines seven applicable state diagrams that describe the intended behavior of a 100Base-X repeater. They are the repeater core, receive, transmit, carrier integrity monitor, receive timer, partition, and repeater data handler. The repeater slice, in conjunction with the PHY and an external switch matrix, provides a complete implementation of the functionality described by these state machines. 11.3.2 10/100 Mbits/s Operation The repeater core of the repeater slice has been designed to work at both 25 MHz and 10 MHz under control of the SPD_SEL input pin (see T able 110 on page 129). Whenever the value of this pin changes, the repeater core is automatically reset and resynchronized to the new clock. This ensures that the logic returns to a known state before the start of operation at the new frequency. The repeater slice also checks the frequency of RX_CLK (receive clock) to verify that it is correct for the selected speed. The detected speed is reflected in the DS bit of the global port status register (see T able 121 on page 141). The repeater slice can be configured via the ASMP bit of the port configuration register 1 (see Table 118 on page 138) so that if a speed mismatch is detected, (i.e., the DS bit and the SPD_SEL are different), the port will be isolated from the repeater.

Agere Systems Inc. 127 Data Sheet T8302 Internet Protocol Telephone July 2001 Advanced RISC Machine ( ARM ) 11 10/100 2-Port Repeater and Backplane Segment Controller (continued)

11.3.3 Collisions

In the transmit collision state, the repeater sends JAM. Transmit collision is entered because two or more ports on the repeater slice are active at the same time. The repeater slice enters transmit collision state when collision is asserted from the backplane. It is the responsibility of the external switch matrix to determine if two or more repeater slice ports on a segment are active and drive the collision signal. The receive collision state is entered due to a remote collision outside the repeater slice in question, causing a signal quality error (SQE) at the repeater slice without any other ports being active. In other words, the repeater slice has only one port active and it is receiving the COL from the PHY .

11.3.4 Partition and Isolate

The repeater slice has been designed to conform to the IEEE 802.3 standard in terms of when a port is isolated or partitioned. The device also has two optional features that may be used to enhance the basic functionality. These features are isolated due to speed mismatch and unpartition on link invalid.

11.3.4.1 Partitioning

In both 10 Mbits/s and 100 Mbits/s modes, the partitioning will occur when 64 consecutive collisions have occurred. Note: The repeater slice will not count late collisions as consecutive collisions. In 10 Mbits/s mode, T w6 is 1050—1125 bit times in duration. If a collision lasts longer than the T w6 timer, the port will be partitioned in 10 Mbits/s mode. Once partitioned, the port will not pass data onto the backplane. The port will continue to transmit data it sees on the backplane. Tw6 is not implemented for 100 Mbits/s. A port will unpartition when a packet has been received or transmitted from the port for Tw5 = 512 bit times without colliding. The partitioning state machine will be reset when the DAP bit in the port configuration register0 (see Table 117 on page 136) is set to 1.

11.3.4.2 MAU Jabber Lockup Protection (MJLP)

In 10 Mbits/s mode only, the repeater will interrupt an excessively long input by putting silence onto the backplane for a short duration. The length of the excessive input must exceed the Tw3 timer value of 4 ms—7.5 ms for the silence to be inserted. The silence is inserted for Tw4 = 97 bit times and the backplane is again driven if the exces- sively long packet is still present. The cycle is repeated until the receive event stops. For example, if a packet lasts for 25 ms, a single MJLP will be tallied in the event counter, but the backplane will have three idle periods of T w4 bit times inserted into the data. The repeater slice does not implement MJLP from the backplane to the PHY interface. It is the responsibility of the PHY to implement a watchdog timer (jabber timer) in the transmit direction.

11.3.4.3 Receive Jabber

MJLP is not implemented for 100 Mbits/s mode. Instead, the 100 Mbits/s mode implements a receive jabber (such as the repeater slice device has implemented). The receive jabber handles an excessively long receive event by simply cutting off the output to the backplane after 0.4 ms—0.75 ms. The repeater continues to keep the backplane output for that port silent until the input has gone silent (CRS = RX_DV = 0) at which time it will again allow a new receive event to pass on to the backplane. Note: The port does not repeat transmit data from the backplane when the receive jabber becomes active.

128 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001 11 10/100 2-Port Repeater and Backplane Segment Controller (continued)

11.3.4.4 Isolate on an Incorrect Clock Frequency

The repeater slice continuously checks the frequency of the clock received from the PHY (RX_CLK ) using the internally generated 50 MHz clock as a timebase. The result is reflected in the DS and SM bits in the global port status register (see Table 121 on page 141). If the clock frequency is incorrect for the selected speed, the repeater slice can be programmed to isolate the port from the repeater slice by setting the automatic speed mis- match protection bit (ASMP ) in the port configuration register 1 to one (see Table 118 on page 138).

11.3.4.5 Automatic Speed Mismatch Protection

Once the port has been isolated due to improper speed setting, the ARM can be alerted by an interrupt. When the PHY returns to the selected speed, the port will return without ARM intervention. The speed mismatch circuit comes up from reset for proper operation based on the SPD_SEL pin and assumes that the RX_CLK is correct. The detection logic looks at the RX_CLK frequency (and not the data to determine if the clock is correct or not), using the criteria listed below. I An RX_CLK with a period of 60 ns or less will be detected as being a valid 25 MHz clock. I An RX_CLK with a period of 80 ns or more will be detected as being a valid 10 MHz clock. This includes an RX_CLK at a dc value of 1 V or 0 V , and everything in between. I An RX_CLK with a period between 60 ns and 80 ns will result in the detection logic holding the indication for the last clock speed that was detected. There is a 620 ns window of hysteresis in switching between indicating a valid 25 MHz clock to invalid, and from switching between indicating a valid 10 MHz clock to invalid. The repeater slice must see the newly detected clock speed for at least 620 ns before the switch is made. If the detection logic indicates an invalid RX_CLK for the mode selected and the mode is changed to agree with the detected clock, the invalid indication will change immediately to valid. Unpartition when LINK_STA TUS = FAIL In an IEEE 802.3 compliant system, the partition state machine for the port will not reconnect once it has parti- tioned unless LINK_STATUS = OK were being reported. However, it is often the case that a port has partitioned because the attached cable has had its receive pair shorted to its transmit pair. In such a case, it is convenient to have the partition clear as soon as the condition is corrected, i.e., the cable is removed. To clear the partition the repeater slice has an optional mode where the partition state machine will be independent of LINK_STATUS = FAIL. To enable this mode, the ULF bit in the port configuration register 1 (see T able 118 on page 138) must be set to 1.

11.3.5 Carrier Integrity Monitor

The repeater slice contains a carrier integrity monitor (CIM) state machine that monitors CARRIER_STATUS , RXERROR_STATUS , and LINK_STATUS variables via the CRS , RX_ER, LIS, and RX_DV inputs from the PHY . The CIM will isolate the port from the repeater if two consecutive false carriers (CARRIER_STATUS = ON with no subsequent SSDs detected) or a single false carrier in excess of the 468—484 bit time FALSE_CARRIER_TIMER that is implemented are received. In some applications, the PHY will contain the CIM state machine in which case the mode may be disabled by set- ting CIMD in the port configuration register 1 to one (see Table 118 on page 138). In cases where the PHY does not contain the CIM, it must supply the proper signaling for false carrier indication as described in IEEE 802.3u Table 22-2 (RX_DV = 0, RX_ER = 1, RXD[3:0] = 1110). The port will reconnect per

11.4 Repeater Slice Interfaces

11.4.1 Repeater Slice ARM Interface

Table 109. Repeater Slice ARM Interface

11.4.2 Repeater Slice Interface

P_CLK I Peripheral clock. ARM peripheral bus clock. signal should be driven high when reading a register and low when writing a register. write cycle and has placed valid data onto the bus during a read cycle. P_WD I ARM write data bus. This data bus is used by the ARM to write to registers. P_RD O ARM read data bus. This data bus is used by the ARM to read from registers. Table 110. Repeater Slice Interface RXD(1, 0)[3:0] I Receive data. must be asserted for data to be accepted. RXD[3:1] is ignored in 10 Mbits/s mode. In 100 Mbits/s mode, RXD[3:0] represent the 4-bit data being received by the PHY . slice with the rising edge of RX_CLK . RXD[0] is the least significant bit of the nibble. RX_DV(1,0) I Receive data valid. lope. If RXDVAV is set high, the repeater uses it to qualify RXD .

RX_CLK(1,0) I Receive clock. RX_CLK can be applied to this pin because RX_DV will be used to qualify RXD[0]. The repeater slice will not clock in RXD[0] when CRS is deasserted. reference for the transfer of RX_DV , RXD [3:0], and RX_ER into the repeater slice. clock. This means narrow clock slivers must never be applied to RX_CLK . In 10 Mbits/s mode, RX_ER is ignored. IEEE 802.3 when it is enabled via the CIMD bit of each port configuration register. COL(1,0) I Collision detect. tion exists. COL can be asynchronously applied to the repeater slice. PHY for 16 bit times in 100 Mbits/s mode and 4 bit times in 10 Mbits/s mode. TXD(1,0)[3:0] O Transmit data. In 100 Mbits/s mode, TXD[3:0] represent the 4-bit data to be transmitted by the PHY . TX_CLK must be 25 MHz in 100 Mbits/s mode and 10 MHz in 100 Mbits/s mode. Table 110. Repeater Slice Interface (continued)

11.4.3 Repeater Slice Input Clocks

Table 111. Repeater Slice Input Clocks TX_EN(1,0) O Transmit enable. 10 Mbits/s data on TXD [0]. It is clocked out on the rising edge of the TX_CLK . 115 on page 135) data is clocked out with an internal 25 MHz clock. TX_ER(1,0) O Transmit error. In 10 Mbits/s mode, TX_ER is not asserted. TX_CLK clock (or 25 MHz system clocks if the TXCPIN bit is set low). LIS(1,0) Static Link integrity status. If RX_DV is true, LIS is a 1, indicating that the link is OK. If RX_DV is false, LIS is a 0, indicating that there is no link. SPD_SEL (1,0) I Speed select. If SPD_SEL is set to a 1, the 100 Mbits/s mode is asserted. If SPD_SEL is set to a 0, the 10 Mbits/s mode is asserted. CLK10C I Clock. This is a 10 MHz 100 ns clock ± 0.01 ns. The duty cycle high time = 35/65 ns. RX_CLK(1,0) I Receive clock. This is a 10 MHz or a 25 MHz MII receive clock. In 10 Mbits/s mode: 10 MHz period 100 ns ±.01 ns. The duty cycle high time = 35/65 ns. In 100 Mbits/s mode: 25 MHz period 40 ns ±.004 ns duty cycle high time = 14/26 ns. TX_CLK(1,0) I Transmit clock. This is a 10 MHz or a 25 MHz MII transmit clock. In 10 Mbits/s mode: 10 MHz period 100 ns ±.01 ns duty cycle high time = 35/65 ns. In 100 Mbits/s mode: 25 MHz period 40 ns ±.004 ns duty cycle high time = 14/26 ns. CLK25 I Clock. This is a 25 MHz 40 ns clock ± 0.01 ns. MSTCLK NA Master clock. This is a buffered version of CLK10 or CLK25 .

11.4.4 Backplane Segment 10/100 Mbits/s Serial Mac Interface Port B

Table 112. Backplane Segment 10/100 Mbits/s Serial Mac Interface Port B MIITXD[3:0] I MII transmit data. clocked into the repeater slice with MIICLK. clocked into the backplane segment with MIICLK. MIITX_EN I MII transmit enable. MIITX_ER I MII transmit error. In 10 Mbits/s mode, MIITX_ER is not monitored. transmit a coding error. MIITX_ER will be clocked with the rising edge of MIICLK . MIICLK O MII transmit/receive clock. In 100 Mbits/s mode, the 25 MHz clock is used to transfer data to or from the MAC. MAC. MIRXD is clocked out of the backplane segment with the falling edge of MIICLK . MIIRXD [0] is the least significant bit of the nibble.

11.5 Repeater Slice Register Map

Table 113. Repeater Slice Register Map MIIRX_DV O MII receive data valid. data from the MAC. MIIRX_DV will transition synchronously with respect to the MIICLK . the last nibble and will be gated to the first MIICLK that follows the final nibble. either repeater slice ports being active or the expansion port being the source of data. looped back on a transmit from the MAC. MIIRX_ER O MII receive error. In 10 Mbits/s mode, MIIRX_ER is driven low. remain asserted for the duration of the error being sensed. MIICOL O MII collision or serial 10 Mbits/s MAC collision. condition exists. MIICOL is clocked out with MIICLK. Table 112. Backplane Segment 10/100 Mbits/s Serial Mac Interface Port B (continued)

134 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001 11 10/100 2-Port Repeater and Backplane Segment Controller (continued)

11.5.1 Global Maximum Frame Size Register

The global maximum frame size register is intended to be programmed with the maximum valid frame size in bytes. The register defaults to 1518 at reset. Table 114. Global Maximum Frame Size Register 31:12 RSVD NA Reserved. These bits are reserved. Their value is undetermined on reads and will be ignored on writes. 11:0 MAX_FS[11] MAX_FS[10] MAX_FS[9] MAX_FS[8] MAX_FS[7] MAX_FS[6] MAX_FS[5] MAX_FS[4] MAX_FS[3] MAX_FS[2] MAX_FS[1] MAX_FS[0] (X) 0 (X) 1 (X) 0 (X) 1 (1) 1 (1) 1 (1) 1 (0) 0 (1) 1 (1) 1 (1) 1 (1) 0 Max frame size. Binary value representing the maximum size frame that will be considered valid by the statistical event generator. These bits default to 0x5EE for 1518 bytes per frame. The value should only be changed when the port configuration register 0 bit 7, RCVE = 0. Oper- ation is unspecified if MAX_FS is set below 1024 byte times or to 4095 byte times.

11.5.2 Global Configuration Register

Table 115. Global Configuration Register 31:6 RSVD (0) Reserved. All bits should be written to 0.

00 PHY0 ↔ MAC

01 PHY1 ↔ MAC

10 Reserved

11 Repeater is in normal mode of operation

3 RSVD — Reserved. Should be written to 0. 2 TXCPIN (0) MII 100 Mbits/s mode TXCPIN enable. data and control for both slices of the repeater slice. 1 GSPS (1) Global speed select. This bit selects the speed of the repeater. 0 RSVD — Reserved. Should be written to 0.

11.5.3 Port Control Registers, for Port 0, 1

Table 116. Port Control Registers for Port 0, 1

11.5.4 Port Configuration Register 0 for Port 0, 1

Table 117. Port Configuration Register 0 for Port 0, 1 cuits are reset to the power-on state. Write 0 to get out of reset.

Table 117. Port Configuration Register 0 for Port 0, 1 (continued) erate RX_DV in 10 Mbits/s mode RXDVAV should be set low. 8 XMTE (0) T ransmit enable. delayed until activity on the port has ended. If 1, data transfer from the PHY to the backplane interface is enabled. delayed until activity on the port has ended. 6 DAP (0) Disable autopartition. If 1, this bit will disable the autopartition state machine. If 0, the autopartition state machine operates normally.

11.5.5 Port Configuration Register 1, for Port 0, 1

This register is used to configure the repeater port and defaults to the values in parenthesis after reset. Table 118. Port Configuration Register 1, for Port 0, 1 4 CIMD (0) Carrier integrity monitor disable. there is a single excessively long false carrier. 2 ASMP (0) Automatic speed mismatch protection. register bit SM is set to 1 to indicate a speed mismatch. If 0, the port will not be isolated when a speed mismatch is detected. speed via the DS bit in the global port status register. 1:0 RSVD (0) Reserved. These bits must always be set to 0.

11.5.6 Global Interrupt Enable Register

Table 119. Global Interrupt Enable Register interrupt if the ISO bit in the global interrupt status register is set. interrupt if the SM bit in the global interrupt status register is set. 11 PHY_INT1 — PHY1 interrupt enable. interrupt if the ISO bit in the global interrupt status register is set. interrupt if the SM bit in the global interrupt status register is set. 3 PHY_INT0 — PHY0 interrupt enable.

140 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001 11 10/100 2-Port Repeater and Backplane Segment Controller (continued)

11.5.7 Global Interrupt Status Register

The global interrupt enable register is used to disable/enable a particular bit in the global interrupt status reg- ister. If any bit of the global interrupt status register is set and the corresponding global interrupt enable regis- ter bit is enabled, the device will drive the repeater interrupt. Reading the global interrupt status register does not clear the interrupt. The interrupt condition will persist unless the processor writes a 1 to the corresponding bit in the global interrupt status register. The processor must decide the priority of simultaneous interrupt conditions. This register will default to the values in parenthesis after reset. Table 120. Global Interrupt Status Register 31:16 RSVD (0) Reserved. 15 ISO1 (1) Isolation status. Change in isolation status of port 1. 14 CLIS1 (1) Link integrity status. Change in link integrity status of port 1. 13 SM1 (1) Port 1 error interrupt. Symbol error interrupt setting register of port 1. 12 RSVD (0) Reserved. 11 PHY_INT1 — PHY1 interrupt status. These interrupts are coming from PHY1. Even if the repeater is in bypass mode, all the registers will be active and interrupt condi- tion on PHY could be read from this register. 10 VLE1 (1) Very long event 1. Very long event interrupt setting register of port 1. 9 CAS1 (1) CAS1 interrupt setting register. Change in autopartitioning status of port 1. 8 RSVD (0) Reserved. 7 ISO0 (1) Isolation status. Change in isolation status of port 0. 6 CLIS0 (1) Link integrity status. Change in link integrity status of port 0. 5 SM0 (1) Port 2 error interrupt. Symbol error interrupt setting register of port 0. 4 RSVD — Reserved. 3 PHY_INT0 — PHY0 interrupt status. These interrupts are coming from PHY0. Even if the repeater is in bypass mode all the registers will be active and interrupt condi- tion on PHY could be read from this register. 2 VLE0 (1) Very long event 0. Very long event interrupt setting register of port 0. 1 CAS0 (1) CAS0 interrupt setting register. Change in autopartitioning status of port 0. 0 RSVD (0) Reserved.

11.5.8 Global Port Status Register, for Port 0, 1

alter the contents of this register. All status bits are valid with RCVE = 0 or 1 (see Table 117 on page 136). Table 121. Global Port Status Register, for Port 0, 1 31:8 RSVD (0) Reserved. These bits are reserved and will return 0s on being read. has occurred. Once set, the user must read this register to clear this bit. the LIS inputs from the PHY . A 1 indicates LINK_STATUS = OK. A 0 indicates LINK_STATUS = FAIL. A 1 indicates that the port has been isolated. A 0 indicates a nonisolated condition. RX_CLK clock is correct for the selected speed. A 1 indicates the incorrect frequency. A 0 indicates a correct frequency. is valid even when the port is disabled. stream. Under normal conditions, the following is true. A 1 indicates a frequency of 10 MHz or 10 Mbits/s. A 0 indicates 25 MHz or 100 Mbits/s. In 10 Mbits/s mode, it indicates MJLP has expired. excessively long CRS currently being applied.

142 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001

12 Ethernet 10/100 PHY(s)

Please refer to Agere’s DNC3X3225 Ethernet T ransceiver Macrocell Data Sheet for references. A twisted pair 10/100 Ethernet transceiver macrocell supports transmission and reception over category three unshielded twisted pair (UTP) cable and category 5 UTP . It has been designed specifically for applications that sup- port both 10Base-T and 100Base-X, such as network interface cards (NICs), and switches. The features of the 10/100 Ethernet transceiver macrocell are listed below. 12.1 10 Mbits Transceiver Features I DSP based. I Compatible with IEEE 802.3u 1995 10Base-T standard for twisted pair cable. I Half-duplex and full-duplex operations. I Autopolarity detection and correction. I Adjustable squelch level for extended wire-length capability (2 levels). I Interfaces with IEEE 802.3u media independent interface (MII) or a serial 10 Mbits/s 7-pin interface. I On-chip filtering eliminates the need for external filters. 12.2 100 Mbits/s Transceiver Features I Compatible with IEEE 802.3u 1995 MII (clause 22). PCS/PMA (clause 24), PMD (clause 25), Mll management, and autonegotiation (clause 28) specifications. I Selectable 5-bit code-group (PDT/PDR interface) or 4-bit data nibbles (Mll interface) input/output. I Full or half-duplex operations. I Optional carrier integrity monitor (CIM). I Selectable carrier sense signal generation (MCRS) asserted during either transmission or reception in half-duplex (MCRS asserted during reception only in full-duplex). I Adaptive equalization and baseline wander correction. I On-chip filtering eliminates the need for external filters. I 100 Mbits/s FX transceiver. I Compatible with IEEE 802.3u 100Base-FX standard. I Disables autonegotiation and 10Base-T. I Enables 100Base-FX remote fault signaling. I Disables MLT -3 encoder/decoder. I Disables scrambler/descrambler. I FX mode enable is pin or register selectable.

12 Ethernet 10/100 PHY(s) (continued)

12.3 General Features

I Autonegotiation and management. I Fast link pulse (FLP) burst generator. I Accepts preamble suppression. I Supports the MII station management protocol and frame format (clause 22): basic and extended register set. I Powerdown mode for 10 Mbits/s and 100 Mbits/s operation. I Loopback testing for 10 Mbits/s and 100 Mbits/s operation. I .25 µm low power CMOS technology. I 25 MHz XTAL oscillator input or 25 MHz/50 MHz/125 MHz clock input. I Compatible with RMII (standard version) and SMII (standard version).

12.4 Signal Information

12.4.1 MII/5-Bit Serial Interface Signals

Table 122. MII/5-Bit Serial Interface Signals cates the jabber timer has expired. is set via the MII management interface or the CRS_SEL signal. used in serial 10 Mbits/s mode.

Packet errors: ERROR_CODES = 2h. Premature end errors: ERROR_CODES = 4h. Code errors: ERROR_CODES = 5h. for data output and MRXD[3:1] are 3-stated. active-high and 10 Mbits/s mode is selected, only MTXD[0 ] is valid. encoder/decoder bypass bit is set, this input serves as the MTXD[4] input. When in 10 Mbits/s mode, this signal is ignored. clock rate is 25 MHz. This is driven from the repeater. chronous with MDC , onto this input. ceiver macrocell, synchronous with MDC , onto this output. MDIO bidirectional buffer (external to the 10/100 Ethernet transceiver macrocell). Table 122. MII/5-Bit Serial Interface Signals (continued)

Table 123. 10/100 Mbits/s Twisted Pair (TP) Interface Signals When set high, no interrupt is generated under any condition. When set low, interrupts are generated according to INT_CONF . This signal is ORed with FULL_DUP . INT_R31 O Maskable status interrupt. This signal will go high whenever there is a change in status. ground to set the 10 Mbits/s TP driver transmit output level. ground to set the 100 Mbits/s TP driver transmit output level. to ground. The parasitic load capacitance should be less than 15 pF .

12.4.3 Status Signals

The signals listed in the following table are accessible via package pins and are described for clarity. Table 124. Status Signals

12.4.4 Clock and Reset Signals

The signals listed in the following table are accessible via package pins and are described for clarity.

12.5 MII Station Management

input that has a maximum frequency of 25 MHz, and with the MDIO signal. and the MII station management entity. MDIO_IN is the information coming from the MAC and is ignored during the TA and DATA fields for MDIO reads. LS10_OK O Link10. This signal indicates good link status for 10 Mbits/s. LS100_OK O Link100. This signal indicates good link status for 100 Mbits/s. Table 125. Clock and Reset Signals RMCLK I RMCLK is internally tied low, and is unused. It should be left open to avoid possible EMI issues. XLO I Crystal oscillator input. A 25 MHz crystal ±25 ppm should be connected across XLO and XHI. Alternately, a 25 MHz external CMOS oscillator can be connected to this input. XHI O Crystal oscillator output.

frame structure shown in Table 126 below. The order of bit transmission is from left to right. Note: Reading and writing the MII management register must be completed without interruption.

12.5.1 MII Management Frame Format

Table 126. MII Management Frame Format indicated by a 1 in MR1 status register, bit 6 (NO_PA_OK ). ST Start of frame. The start of frame is indicated by a 01 pattern. multiple PHY entities must have prior knowledge of the appropriate PHY address for each entity. REGAD Register address. The register address is 5 bits, allowing for 32 unique registers within each PHY . The first register address bit transmitted and received is the MSB of the address. macrocell during the second bit time. disabled and the PHY’s pull-up resistor will pull the MDIO line to a logic 1.

12.5.2 Summary of Management Registers

Table 127. Summary of Management Registers (MR)

5 MR5 Autonegotiation link partner ability (base page)

(see Table 132 on page 151).

5 MR5 Autonegotiation link partner (LP) ability

(see Table 133 on page 152).

17 MR17 Autonegotiation (read register A)

(see Table 137 on page 154).

18 MR18 Autonegotiation (read register B)

(see Table 138 on page 154).

12.5.3 MR0 Control Register Bit Description

Table 128. MR0 Control Register Bit Description cell. All registers will be set to their default state. This bit is self-clearing. contain all circuitry up to, but not including, the PMD. ignored when autonegotiation is enabled (MR0, bit 12). This bit is ANDed with the SPEED_PIN signal. powerup. The process may be restarted by setting this bit to 1. when autonegotiation restarts. duplex). This bit is ignored when quick status NWA Y_ENA in MR0 is enabled. This bit is ORed with the F_DUP pin. rocell will assert the MCOL signal in response to MTX_EN . 6:0 RESERVED NA Reserved. All bits will read 0.

12.5.4 MR1 Status Register Bit Description

Table 129. MR1 Status Register Bit Description

12.5.5 MR2 MR3 PHY Identifier Registers (1 and 2) Bit Description

10:7 RESERVED R Reserved. All bits will read as a 0. detected. This bit will remain set until cleared by reading the register. tion. The value of this bit is always a 1. and stay cleared until it has been read via the management interface. will remain set until it is read, and the jabber condition no longer exists. Table 130. MR2 MR3 PHY Identifier Registers (1 and 2) Bit Description bits 15:0 (MR2) and 15:10 (MR3). This value is all ones. value for bits 24:19 is all ones.

12.5.6 MR4 Autonegotiation Advertisement Register Bit Description

12.5.7 MR5 Autonegotiation Link Partner Ability (Base Page) Register Bit Description

Table 132. MR5 Autonegotiation Link Partner Ability (Base Page) Register Bit Description Table 131. MR4 Autonegotiation Advertisement Register Bit Description 14 ACK R/W Acknowledge. This bit is the acknowledge bit from the link code word. cates to the link partner a remote fault condition. control information with its link partner. 9 100BASET4 R/W 100Base-T4. This bit should always be set to 0. 10/100 Ethernet transceiver macrocell is capable of 100Base-TX operation. net transceiver macrocell is capable of 10Base-T operation. 4:0 SELECT R/W Selector field. Reset with the value 00001 for IEEE 802.3. link partner wishes to engage in next page exchange. and consistent FLP (fast link pulse) bursts. register (see Table 131 on page 151).

12.5.8 MR5 Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Description

Table 133. MR5 Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Description

12.5.9 MR6 Autonegotiation Expansion Register Bit Description

15 LP_NEXT_P AGE R Next page. A logic 0 indicates that this is the last page to be transmitted. A logic 1 indicates that additional pages will follow. partner has successfully received its partner’s link code word. ate a message page (logic 1) from an unformatted page (logic 0). tion with the link partner during next-page exchange. 28C of the IEEE 802.3u 1995 standard. Table 134. MR6 Autonegotiation Expansion Register Bit Description This bit can only be cleared by reading this register. that the link partner supports the next page function. ports the NEXT_P AGE function. indicates that the link partner is autonegotiation capable.

12.5.10 MR7 Next Page Transmit Register Bit Description

12.5.11 MR16 PCS Control Register Bit Description

Table 136. MR16 PCS Control Register Bit Description Table 135. MR7 Next Page Transmit Register Bit Description If 0, it indicates that this is the last page. If 1, it indicates there is an additional next page. 14 ACK R Acknowledge. This bit is the acknowledge bit from the link code word. If 0, it indicates an unformatted page. If 1, it indicates a formatted page. If 0, it indicates the device cannot comply with the message. If 1, it indicates the device will comply with the message. value of the toggle bit in the previously exchanged link code word. 15 LOCKED R Locked. Locked pin from descrambler block. 14:12 RSVD R Reserved. Will always be read back as 0. should be written to these bits. 3 LOOPBACK R/W Loopback configure. If high, the entire loopback is performed in the PCS macro. If low, only the collision pin is disabled in loopback. mit side or disabling the collision pin.

12.5.12 MR17 Autonegotiation (Read Register A)

12.5.13 MR18 Autonegotiation (Read Register B)

Table 137. MR17 Autonegotiation (Read Register A) 15:13 RSVD — Reserved. Always 0. 11 WL R Wait Link_Fail_Inhibit_Wait_Timer (link status check). 10 WA R Wait Autoneg_Wait_Timer (link status check). 9 WB R Wait Break_Link_Timer (transmit disable). 8 PDF R Parallel detection fault. 7 AE R Autonegotiation enable. 6 FLPL R FLP link good check. 5 CA R Complete acknowledge. Table 138. MR18 Autonegotiation (Read Register B) 15 RFLP R Receiving FLPs. Any of FLP capture, clock, DA TA_0, or DA TA_1. 14 FP ASS R FLP pass (FLP Rcv). 13 LPC R Link pulse count (FLP Rcv). 12 LPD R Link pulse detect (FLP Rcv). 11 TP R T est pass (NLP receive). 10 TFC R Test fail count (NLP receive). 9 TFE R Test fail extend (NLP receive). 8 WMT R Wait max timer ack (NLP receive). 7 DF R Detect freeze (NLP receive). 6 TF R Test fail (NLP receive). 5 TC R Transmit count ack (FLP transmit). 4 TDB R Transmit data bit (FLP transmit). 3 TCB R Transmit clock bit (FLP transmit). 2 TA R Transmit ability (FLP transmit). 1 TR R Transmit remaining acknowledge (FLP transmit).

12.5.14 MR21 RXER Counter

12.5.15 MR28 Device-Specific Register 1 (Status Register) Bit Description

Table 139. MR21 RXER Counter 16-bit or 8-bit counter mode and the indicated register map shown below is used. 0 MCWO W 16-bit, 8-bit counter mode. If 1, the register is put in an 8-bit counter mode. If 0, the register is put in a 16-bit counter mode. This bit is reset to 0 and can’t be read (write only). This bit is reset on a read operation. count of disconnect events, (link unstable 6). This bit is reset on a read operation. This bit is reset on a read operation. This bit is reset on a read operation. Table 140. MR28 Device-Specific Register 1 (Status Register) Bit Description 15:9 RSVD R Reserved. Read as 0. or the device has been reset. This bit is only valid in 10 Mbits/s mode. This bit is only valid in 100 Mbits/s mode. This bit is only valid in 100 Mbits/s mode.

12.5.16 MR29 Device-Specific Register 2 (100 Mbits/s Control) Bit Description

3 RXERR_ST R/LH* RX error status. Indicates a false carrier. This bit will latch high until read. This bit is only valid in 100 Mbits/s mode. 2 FRC_JAM R/LH* Force jam. This bit will latch high until read. This bit is only valid in 100 Mbits/s mode. ceiver is up and operational. ceiver is up and operational. Table 141. MR29 Device-Specific Register 2 (100 Mbits/s Control) Bit Description and MR29 to be reset to their default values. 14 RST1 R/W Generic reset 1. This register is used for manufacture test only. 13 RST2 R/W Generic reset 2. This register is used for manufacture test only. 12 100_OFF R/W 100 Mbits/s transmitter off. If set to 0, it forces TPI low and TPIN high. Default = 1. used, and cleared to zero when the repeater is bypassed. This bit is ORed with the CRS_SEL pin. 9 LINK_ERR R/W Link error indication. the MII. The specific error codes are listed in the MRXD pin description. If it is 0, it will disable this function. 8 PKT_ERR R/W Packet error indication enable. rocell when MRX_ER is asserted on the MII. If 0, it will disable this function. Table 140. MR28 Device-Specific Register 1 (Status Register) Bit Description (continued)

12.5.17 MR30 Device-Specific Register 3 (10 Mbits/s Control) Bit Description

6 EDB R/W Encoder/decoder bypass. If 1, the 4B/5B encoder and 5B/4B decoder function will be disabled. 5 SAB R/W Symbol aligner bypass. If 1, the aligner function will be disabled. 4 SDB R/W Scrambler/descrambler bypass. If 1, the scrambling/ descrambling functions will be disabled. This bit is ORed with the SDBT pin. 3 CARIN_EN R/W Carrier integrity enable. If 1, carrier integrity is enabled. This bit is ORed with the CARIN_EN pin. end fault detection, and logic 0 will disable the function. 0 RSVD R/W Reserved, should be programmed to 0. Table 142. MR30 Device-Specific Register 3 (10 Mbits/s Control) Bit Description 15:14 RSVD R/W Reserved. Read as 0. 13 JAB_DIS R/W Jabber disable. If 1, disables the jabber function of the 10Base-T receive. 12:6 RSVD R/W Reserved. Read as 0. 5 HBT_EN R/W Heartbeat enable. If 1, the heartbeat function will be enabled. Valid in 10 Mbits/s mode only. Table 141. MR29 Device-Specific Register 2 (100 Mbits/s Control) Bit Description (continued)

12.5.18 MR31 Device-Specific Register 4 (Quick Status) Bit Description

4 ELL_EN R/W Extended line length enable. 350 mV , allowing reception of signals with a lower amplitude. Valid in 10 Mbits/s mode only. 3 APF_EN R/W Autopolarity function disable. 1 SERIAL _SEL R/W Serial select. If set to a 1, the 10 Mbits/s serial mode will be selected. used, and cleared to zero when the repeater is bypassed. Table 143. MR31 Device-Specific Register 4 (Quick Status) Bit Description

14 RXERR_ST

cates that the carrier detect state machine has found a false carrier. cleared by reading the register. ever there is a change in link status (LSTAT_OK changes state). remain set until cleared by reading the register. Table 142. MR30 Device-Specific Register 3 (10 Mbits/s Control) Bit Description (continued)

12 UNLOCKED/JABBER R Unlocked/jabber. the TX descrambler has lost lock. ber condition has been detected. This bit will remain set until cleared by reading the register. and stay cleared until it has been read via the management interface. 10 P AUSE R Link partner pause. If 1, it indicates that the link has negotiated to 100 Mbits/s. If 0, it indicates that the link is operating at 10 Mbits/s. If 1, it indicates that the link has negotiated to full-duplex mode. If 0, it indicates that the link has negotiated to half-duplex mode. 7 INT_CONF R/W Interrupt configuration. whenever any of bits [31.15:12] go high or LSA T_OK goes low. goes high only when the link status changes (bit 14 goes high). 6 INT_MASK R/W Interrupt mask. When set low, interrupts are generated according to INT_CONF . Table 143. MR31 Device-Specific Register 4 (Quick Status) Bit Description (continued)

000: Autonegotiation enable. 001: Transmit disable or ability detect. defined above for LOW_AUTO_STA TE .

Agere Systems Inc. 161 Data Sheet T8302 Internet Protocol Telephone July 2001 Advanced RISC Machine ( ARM )

13 USB Host Controller

I Full compliance with Universal Serial Bus Specification Revision 1.0. I OpenHCI open-host controller interface specification for USB release 1.0 compatible. I Integrated dual-speed USB transceiver. I Supports all USB compliant devices and hubs. I Integrated dual-speed USB transceivers enable a single-chip USB solution. Note: The legacy peripherals feature, as defined in OpenHCI specification version 1.0, is not supported.

13.1 Description

The USB host controller provides a downstream USB port to connect to any USB compliant device on hub. Full- speed or low-speed peripherals are supported along with all of the USB transfer types: control, interrupt, bulk, or isochronous. The USB host controllers OpenHCI compliance offers significant USB performance benefits and reduced ARM overhead. The USB APB interface requires that the system clock frequency be equal to or greater than the 48 MHz USB clock to function correctly. The USB host controller is a master on the IPT_ARM system bus (ASB). A complete explanation of the USB oper- ation is beyond the scope of this document. The user should refer to the OpenHCI Specification version 1.0 for an explanation of how to set up and use the USB. Every device on the USB bus is specified to the USB host controller by one or more endpoint descriptors (ED). These endpoint descriptors are placed on the interrupt list, the control list, or the bulk list by software. Isochronous end points are placed on the interrupt list at the end of all interrupt endpoints. Each item placed on a list is linked to all the other items on that list. Interrupt endpoints, depending on where they are linked on the list, can be checked every 1, 2, 4, 8, 16, or 32 ms. Each endpoint descriptor can be linked to zero or more transfer descriptors. When an endpoint is checked, and if there is a valid transfer descriptor linked to it, the host controller will execute one trans- fer. The executed transfer has its descriptor removed from the endpoint list and moved to a done linked list. The Hc HCCA register points to a memory structure that defines the start and end of all interrupt endpoint lists. The control and bulk lists are pointed to by their own address pointer registers.

13 USB Host Controller (continued)

Figure 21. USB Block Diagram

13.2 USB Registers

frame counter, and root hub. All of the registers should be read and written as 32-bit words. ister is written, bits written to reserved fields should be 0.

13.2.1 USB Operational Registers Summary

Table 144. USB Operational Register Map

13.3 The Control and Status Partition

13.3.1 Hc Revision Register

Table 145. Hc Revision Register specification will have a value of 10h.

13.3.2 Hc Control Register

modified only by the host controller driver, except host controller functional state and remote wake-up connected. Table 146. Hc Control Register has no impact on the generation of hardware interrupt. not described in this specification. generated by events registered in Hc interrupt status register. a tag to indicate the ownership of HC. 7:6 HCFS 00b R/W R/W Host controller functional state for USB. subsequent reset signaling to downstream ports.

Table 146. Hc Control Register (continued) must check this bit whenever it determines to process the list. ister before re-enabling processing of the list. teed to take effect in the next frame (not the current frame). check this bit before it starts processing the list. HCD is responsible for restoring this value.

13.3.3 Hc Command Status Register

mal read access to all bits. tus register (see T able 148 on page 167). Table 147. Hc Command Status Register until the next request from OS HCD.

Table 147. Hc Command Status Register (continued)

13.3.4 Hc Interrupt Status Register

cleared. The host controller driver may not set any of these bits. The host controller will never clear the bit. Table 148. Hc Interrupt Status Register trol list processing will stop. the IR field of Hc Control; no host bus accesses are allowed. ownership change request field in Hc command status register. the SMI pin is not implemented.

Table 148. Hc Interrupt Status Register (continued) register [number of downstream port] has changed. rected. HCD clears this bit after HC has been reset. set. This bit is not set when HCD sets the USB resume state. ates an SOF token at the same time. of Hc command status register to be incremented.

13.3.5 Hc Interrupt Enable Register

enable register is set and the MIE bit is set, then a hardware interrupt is requested on the host bus. corresponding bit unchanged. On read, the current value of this register is returned. Table 149. Hc Interrupt Enable Register 31 MIE 0b R/W R Master interrupt enable. A 0 written to this field is ignored by HC. 30 OC 0b R/W R Ownership change. If 1 = Enable interrupt generation due to ownership change. 6 RHSC 0b R/W R Root hub status change. 1 = Enable interrupt generation due to root hub status change. 5 FNO 0b R/W R Frame number overflow. If 1 = Enable interrupt generation due to frame number overflow. 4 UE 0b R/W R Unrecoverable error. If 1 = Enable interrupt generation due to unrecoverable error. 3 RD 0b R/W R Resume detect. If 1 = Enable interrupt generation due to resume detect. 2 SF 0b R/W R Start of frame. If 1 = Enable interrupt generation due to start of frame. 1 WDH 0b R/W R Writeback done head. If 1 = Enable interrupt generation due to HcDoneHead writeback. 0 SO 0b R/W R Scheduling overrun. If 1 = Enable interrupt generation due to scheduling overrun.

13.3.6 Hc Interrupt Disable Register

Hc interrupt status register. The Hc interrupt disable register is coupled with the Hc Interrupt enable register. read, the current value of the Hc interrupt enable register is returned. Table 150. Hc Interrupt Disable Register 31 MIE 0b R/W R Master interrupt enable. A 0 written to this field is ignored by HC. 30 OC 0b R/W R Ownership change. If 1 = Disable interrupt generation due to ownership change. 6 RHSC 0b R/W R Root hub status change. If 1 = Disable interrupt generation due to root hub status change. 5 FNO 0b R/W R Frame number overflow. If 1 = Disable interrupt generation due to frame number overflow. 4 UE 0b R/W R Unrecoverable error. If 1 = Disable interrupt generation due to unrecoverable error. 3 RD 0b R/W R Resume detect. If 1 = Disable interrupt generation due to resume detect. 2 SF 0b R/W R Start of frame. If 1 = Disable interrupt generation due to start of frame. 1 WDH 0b R/W R Writeback done head. If 1 = Disable interrupt generation due to HcDoneHead writeback. 0 SO 0b R/W R Scheduling overrun. If 1 = Disable interrupt generation due to scheduling overrun.

13.4 Memory Pointer Partition

13.4.1 Hc HCCA Register

tent of the Hc HCCA register. The alignment is evaluated by examining the number of zeros in the lower order bits. Table 151. Hc HCCA Register

13.4.2 Hc Period Current ED Register

Table 152. Hc Period Current ED Register controller communication area.

13.4.3 Hc Control Head ED Register

The Hc Control head ED register contains the physical address of the first endpoint descriptor of the control list. Table 153. Hc Control Head ED Register

13.4.4 Hc Control Current ED Register

Table 154. Hc Control Current ED Register HCCA during the initialization of HC. allowed to modify this register only when the CLE is cleared.

13.4.5 Hc Bulk Head ED Register

The Hc bulk head ED register contains the physical address of the first endpoint descriptor of the bulk list. Table 155. Hc Bulk Head ED Register

13.4.6 Hc Bulk Current ED Register

bulk list is served in a round-robin fashion, the endpoints will be ordered according to their insertion to the list. Table 156. Hc Bulk Current ED Register rent ED register and clears the bit. If it is not set, it does nothing. cate the end of the bulk list.

13.4.7 Hc Done Head Register

tent is periodically written to the HCCA. Table 157. Hc Done Head Register

13.5 Frame Counter Partition

13.5.1 Hc Fm Interval Register

Hc interrupt status register.

Table 158. Hc Fm Interval Register

13.5.2 Hc Fm Remaining Register

The Hc Fm remaining register is a 14-bit down counter showing the bit time remaining in the current frame. Table 159. Hc Fm Remaining Register value is calculated by the HCD. 13:0 FR 0h R R/W Frame remaining. This counter is decremented at each bit time. updated value from the next SOF .

13.5.3 Hc Fm Number Register

and generate a 32-bit frame number without requiring frequent access to the register. Table 160. Hc Fm Number Register

13.5.4 Hc Periodic Start Register

processing the periodic list. Table 161. Hc Periodic Start Register

13.5.5 Hc LS Threshold Register

driver are allowed to change this value. set the start of frame in the Hc interrupt status register.

Table 162. Hc LS Threshold Register

13.6 Root Hub Partition

well as some static fields of the class descriptor. bit organization and operation to typical hubs that are found in the system. I Hc Rh descriptor A register. I Hc Rh descriptor B register. I Hc Rh port status register [1:NDP], (NDP = number of data ports). with the system implementation.

13.6.1 Hc Rh Descriptor A Register

descriptor A register and Hc Rh descriptor B register.

Table 163. Hc Rh Descriptor A Register ms. The duration is calculated as POTPGT x 2 ms. This field should always read/write 0. If 0, all ports are powered at the same time. If 1, each port is powered individually. the global power switch, set/clear global power.

Table 163. Hc Rh Descriptor A Register (continued) Note: IS denotes an implementation-specific reset value for that field. switching. If 0, ports are power switched. mum number of ports supported by OpenHCI is 15.

13.6.2 Hc Rh Descriptor B Register

Table 164. Hc Rh Descriptor B Register Bit 17: Ganged-power mask on port #17. Bit 18: Ganged-power mask on port #18. Bit 31: Ganged-power mask on port #31. When cleared, the attached device is removable. When set, the attached device is not removable. Bit 1: Device attached to port 1. Bit 2: Device attached to port 2. bit 15: Device attached to port 15.

13.6.3 Hc Rh Status Register

and the upper word represents the hub status change field. Reserved bits should always be written 0. Table 165. Hc Rh Status Register 31 CRWE — W R Clear remote wake-up enable, (write). a change has occurred to the OCI field of this register. The HCD clears this bit by writing a 1. state transition and setting the resume detected interrupt. 0 = CSC is not a remote wake-up event. 1 = CSC is a remote wake-up event. (Write) set remote wake-up enable: writing a 1 sets DRWE . when the global reporting is implemented. is implemented this bit is always 0. local power status feature; thus, this bit is always read as 0. tus only on ports whose PPCM bit is not set.

13.6.4 Hc Rh Port Status [1:NDP] Register

ware. The lower word is used to reflect the port status, whereas the upper word reflects the status change bits. poned until the transaction completes. Reserved bits should always be written 0. Table 166. Hc Rh Port Status Register [1:NDP] port reset signal. The HCD writes a 1 to clear this bit. 0 = port reset is not complete. tieth resume pulse, LS , EOP , and a 3 ms resynchronization delay. 0 = resume is not completed.

Table 166. Hc Rh Port Status Register [1:NDP] (continued) set this bit.The HCD writes a 1 to clear this bit. The HCD writes a 1 to clear this bit. occur if the port is disconnected. reset to inform the system that the device is attached. the device attached to this port. When set, a low-speed device is attached to this port. When clear, a full-speed device is attached to this port. This field is valid only when the CCS is set. If 0 = full-speed device attached. If 1 = low-speed device attached. (Write) CPP . The HCD clears the PPS bit by writing a 1 to this bit.

CCS , PES , PSS , and PRS should be reset. (Write) SPP . The HCD writes a 1 to set the PPS bit. Note: This bit always reads 1b if power switching is not supported. 0 = port reset signal is not active. 1 = port reset signal is active.

this port. This bit always reflects the overcurrent input signal. 0 = no overcurrent condition. 1 = overcurrent condition detected. resume. A resume is initiated only if this bit is set. the port reset or when the HC is placed in the USB resume state. enable and clears it by writing clear port enable. informs the driver that it attempted to enable a disconnected port.

the PES bit. The CCS is not affected by any write. removable (DR[NDP] ) (see T able 164 on page 180).

14 IrDA_ACC and UART_ACC

I Full-duplex asynchronous communication. I Each ACC has 10 x 32 FIFOs for both receive and transmit. I One start bit, eight data bits, one optional ninth data bit, one optional parity bit, one stop bit. I Separate programmable baud rates. I Complete status reporting capabilities. I Support for DMA transfers. I IrDA input/output pulse formatter option (IrDA_ACC only).

14.1 ACC Operation

Table 176 on page 193). The status of the transmitter and receiver FIFOs are used to generate interrupts. bit 9 is used to control the extended character support. Figure 22. ACC Block Diagram

14 IrDA_ACC and UART_ACC (continued)

14.1.1 Transmit and Receive Operation

does not vary. The optional parity bit is then generated, followed by stop bit(s). ACC interrupt enable register (see Table 180 on page 196) was set to enable the corresponding interrupt. from one of the ACCs, the interrupt type is read from the respective ACC’s interrupt register.

14.1.2 Transfer Operating Modes

transmitter can operate in different parity modes but use the same number of data bits. Table 167. ACC Transfer Modes

14.1.3 Programming the Baud Rate

clocks per bit for the desired baud rate. 0 00 1 start, 8 data, 1 stop bit. 0 01 1 start, 8 data, 2 stop bits. 0 10 1 start, 8 data, 1 even parity, 1 stop bit. 0 11 1 start, 8 data, 1 odd parity, 1 stop bit. 1 00 1 start, 9 data, 1 stop bit. 1 01 1 start, 9 data, 2 stop bits. 1 10 1 start, 9 data, 1 even parity, 1 stop bit. 1 11 1 start, 9 data, 1 odd parity, 1 stop bit.

Where BRD is programmed as 0x13 and SM is programmed as 0x9. count of 23, the next bit 22, then 23, and so on. Using this mode reduces the error for some baud rate choices.

14.1.4 Extended Characters

data value to the transmit FIFO according to Table 168. Idle characters have no effect on the receiver. Table 168. Extended Characters

14.2 ACC Registers

Table 169. IrDA_ACC and UART_ACC Communication Controller Register Map 0x000:0x1FF Normal 9-bit character. 0x20:0x3FE Do not write these values.

14.2.1 Baud Rate Register

rate register + 1. The format of the baud rate register is shown below. Table 170. Baud Rate Register

14.2.2 Baud Rate Counter Register

counter register is written. Table 171. Baud Rate Counter Register rate divisor is 1. For a value of 0xFFFF , the resulting baud rate divisor is 65,536. 15:0 BRC Baud rate counter. Current value of the baud rate counter.

14.2.3 FIFO Status Register

Table 172. FIFO Status Register If 0, the receiver is not idle. If 1, the transmitter shift register is empty . If 0, the transmitter shift register is not empty. 5 TFF T ransmitter FIFO full. If 1, the transmitter FIFO is full. If 0, the transmitter FIFO is not full. 4 TFHF T ransmitter FIFO half full. If 1, the transmitter FIFO is at least half full. If 0, the transmitter FIFO is not at least half full. 3 TFE T ransmitter FIFO empty. If 1, the transmitter FIFO is empty. If 0, the transmitter FIFO is not empty. If 1, the receiver FIFO is full. If 0, the receiver FIFO is not full. 1 RFHF Receiver FIFO half full. If 1, the receiver FIFO is at least half full. If 0, the receiver FIFO is not at least half full. If 1, the receiver FIFO is empty. If 0, the receiver FIFO is not empty.

14.2.4 Receiver Control Register

receiver control register is set to all zeros. Table 173. Receiver Control Register

14.2.5 ACC Parity Bit Encoding

Table 174. ACC Parity Bit Encoding

14.2.6 Transmitter Control Register

transmitter control register is set to all zeros. T able 175 shows the transmitter control register. 7 RD Receiver disable. Disables the receiver. Writing a 1 to this bit will disable the receiver. 4:3 PC Parity check. Controls receiver parity checking. Table 174 below shows the encoding for this field. Parity checking is disabled upon any reset. 0 FR FIFO reset. Resets the receiver FIFO. Writing 0 to this bit causes the FIFO to accept new data. The receiver FIFO is reset upon a reset to the IrDA_ACC. 01 Mark parity (always send a 1).

Table 175. Transmitter Control Register

14.2.7 Mode Control Register

zeros. The mode control register is shown below. Table 176. Mode Control Register 5 TOD T ransmitter open drain. Puts the transmit output into open-drain mode. encoding for this field. Parity generation is disabled upon any reset. empty status bit can be disabled and masked when the transmitter is not in use. 0 FR FIFO reset. Resets the transmitter FIFO. If 1, the transmitter FIFO is reset, discarding remaining data and marking it as empty. If 0, the FIFO can accept new data. The transmitter FIFO is reset upon resetting the ACC. 3 AL/CO Alternate/constant. Controls the special alternate mode. If 1, the least significant bit of the sample count is toggled for each new bit of a transfer. If 0, the sample count remains constant for each bit. 2 ECE Extended character enable. Enables the extended characters in 9-bit mode. If 1, the extended characters are available. If 0, the extended characters are not available. 0 9BM 9-bit mode. Indicates if the transfers are 8 or 9 bits. If 1, all transfers consist of 9 data bits. If 0, all transfers consist of 8 data bits.

14.2.8 Tx/Rx FIFO Register

are reset upon all system resets. not change the status of the Rx FIFO. Table 177. Tx/Rx FIFO Register

14.2.9 IrDA Feature Register

Table 178. IrDA Feature Register 11 baud intervals). In 8-bit data mode, this bit is ignored on writes and always read as zeros. If 1, the character is an extended character. If 0, the character is a normal character. on writes and always reads as zeros. 7:0 CHA Character. Character to transmit if written to. Character received if read from. 8 IDE IrDA enable. Enables the IrDA. If 1, the IrDA is active and the IrDA Tx and IrDARx pins are driven by the IrDA feature. If 0, the IrDA is disabled and the IrDA Tx and IrDARx pins are driven without the IrDA I/O formatter. 7:0 PWC Pulse width count. Pulse width count value.

Table 179. ACC Interrupt Register 1, an interrupt will be generated. shift register to re-enable this bit to transition to 1 again. This bit is masked and will be a 0 if the TXON bit is not set to a 1. more data to place in the transmitter to prevent an interrupt from always being asserted. This bit is masked and will be a 0 if the TXON bit is not set to a 1. this bit is cleared, it must go idle and then not idle again for a new interrupt to be generated. the RFE bit in the FIFO status register (see Table 172 on page 191). the parity error interrupt enable bit is set while this bit is 1, an interrupt will be generated. This bit is cleared by writing a 1 to this bit location. 3 RXFEI Receive data framing error. This bit is set when a framing error is detected in the received data. If the framing error enable bit is set while this bit is 1, an interrupt will be generated. This bit is cleared by writing a 1 to this bit location.

Table 179. ACC Interrupt Register (continued) Table 180. ACC Interrupt Enable Register interrupt enable bit is set while this bit is 1, an interrupt will be generated. This bit is cleared by writing a 1 to this bit location. full. The receiver FIFO must be read or reset to remove this condition. caused this interrupt must be removed (i.e., by writing the FIFO to remove this bit). 11 TXNDIE Transmitter no data interrupt enable. If 1, the transmitter no data interrupt is enabled. If 0, no transmitter no data interrupt will be generated. 10 TXSREE Transmitter shift register empty interrupt enable. If 1, the transmitter shift register empty interrupt is enabled. If 0, no transmitter shift register empty interrupt will be generated. 9 TXFHE Transmitter FIFO half-empty interrupt enable. If 1, the transmitter FIFO half-empty interrupt is enabled. If 0, no transmitter FIFO half-empty interrupt will be generated. 8 TXFEI Transmitter FIFO empty interrupt enable. If 1, the transmitter FIFO empty interrupt is enabled. If 0, no transmitter FIFO empty interrupt will be generated. 6 RXFNFEI RXFNFEI receiver FIFO not empty interrupt enable. If 1, the receiver FIFO not empty interrupt is enabled. If 0, the receiver FIFO not empty interrupt is disabled. 5 RXNIE Receiver not idle interrupt. If 1, the receiver not idle interrupt is enabled. If 0, no receiver not idle interrupt will be generated. 4 RXPEI Received data parity error interrupt enable. If 1, the received data parity error interrupt is enabled. If 0, no received data parity error interrupt will be generated.

Table 180. ACC Interrupt Enable Register (continued)

14.3 IrDA Formatter

I Operates at speeds of up to 115.2 kbits/s. I Programmable pulse width to the IrDA transceiver.

14.3.1 IrDA Formatter Operation

required by the transceiver being used. 3 RXFEI Received data framing error interrupt enable. If 1, the received data framing error interrupt is enabled. If 0, no received framing error interrupt will be generated. 2 RXOE Received data overrun error interrupt enable. If 1, the received data overrun error interrupt is enabled. If 0, no received overrun error interrupt will be generated. 1 RXFHI Receiver FIFO half-full interrupt enable. If 1, the receiver FIFO half-full interrupt is enabled. If 0, no Receiver FIFO half-full interrupt will be generated. 0 RXFFI Receiver FIFO full interrupt enable. If 1, the receiver FIFO full interrupt is enabled. If 0, no receiver FIFO full interrupt will be generated.

Figure 23. IrDA Transmit Data Timing Diagram and Width Programmability Figure 24 shows how the IrDA formatting feature converts the IrDA pulse back into data compatible with ACC. counter clock output for it to be detected by the IrDA formatter.

Figure 24. IrDA Receive Data Timing Diagram, Minimum Pulse Width

14.4 DMA Support for ACC I/O Data

9-bit data bit mode, the lower 9 bits of the DMA transfer are valid.

14.5 Operation on Reset

I All ongoing transfers are aborted. I Both transmitter and receiver FIFOs are reset. I The transmitter control register is reset to all zeros to disable transmitter parity generation. I The receiver control register is reset to all zeros to disable receiver parity checking. I The FIFO status register is set to reflect the current status of both transmitter and receiver FIFOs (empty). I The baud rate register is reset to all zeros.

200 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001

15 Synchronous Serial Interface (SSI)

The SSI unit is compatible with the SPI interface of the Motorola* 68HC11 microcontroller. The following features of the SPI interface are supported by the SSI interface: I Four-wire synchronous serial interface clock, data in, data out, slave select control. I Clock polarity selection. I Data phase selection. I Outputs can be programmed to be open-drain or direct-drive. I Four-wire full-duplex transfers. I Three-wire half-duplex or unidirectional transfers. I Detection of multiple-master bus contention faults and slave-mode write-collisions. I Support for DMA transfers.

15.1 Description

The SSI unit operates in either the master mode or the slave mode. Figure 25 on page 202 shows a functional block diagram of the SSI. The master unit in an SSI cluster enables slave units to receive and transmit data, and ini- tiates transmissions by broadcasting a clock signal, called SCK , to all other units. A data register in each unit oper- ates as an 8-bit shift register clocked by SCK . The master unit configures a data path between its data register and the data register of one other slave unit, so that a 16-bit circular shift register is formed. Communication between the master and slave units then occurs if eight SCK cycles cause the data values, stored in each register, to be exchanged. This mode of operation is suitable for bidirectional communication between a master and slave unit. It utilizes the four-wire interface consisting of clock, data in, data out, and slave select control. Other possible modes of operation are as follows. I A master unit broadcasts a byte (or longer multibyte message) to several slave units simultaneously , provided that only one slave is enabled to drive data back to the master. I A multimaster, multislave network may be constructed where a software protocol allows all units to share the two data transmit/receive wires without data loss. I Slave units are capable of receiving data and returning data when only one data wire is connected in the system. Pins MDISDO and MDOSDI are tied together to form a single bidirectional data line. The MDISDO , MDOSDI , and SCK pins are configured as open-drain outputs to minimize contention from several drivers that is possible in some of these configurations. An external pull-up resistor is required on all open-drain pins.

15.1.1 Clocks

SCK is provided by the master unit and in the SSI. Seven different SCK rates derived from the system clock are supported. If configured as a slave unit, SCK is obtained from outside of the device, and is assumed to be asyn- chronous with respect to the slave’s system clock. Consequently, data transfers and error conditions also occur asynchronously with respect to the slave’s system clock. A special register access sequence is defined for the ARM core to obtain data and status information from the slave SSI. Depending on the polarity of the shift clock and the phase of the data relative to the shift clock, the SSI interface supports four different modes of transfer. These modes are under program control, and master and slave units communicate in a common mode. * Motorola is a registered trademark of Motorola Inc.

Agere Systems Inc. 201 Data Sheet T8302 Internet Protocol Telephone July 2001 Advanced RISC Machine ( ARM )

15 Synchronous Serial Interface (SSI) (continued)

The 8-bit data register shifts out a byte, one bit at a time (MSB first), synchronously with the shift clock SCK . If run- ning as a master, the SSI derives SCK from its system clock using a prescaling value determined by the SCLK[2:0] bits of SSI control register 1 (see T able 183 on page 204). Before being output to the pin, the pre- scaled clock is conditioned in the clock control block in accordance with the SPOL and SPHA bits in SSI control register 1. As a slave, the shift clock is supplied by an external master through the SCK pin and is modified in accordance with the SPOL and SPHA bits in the slave’s SSI control register 1.

15.1.2 Date Transfer

The data register loads data from the lower byte of the peripheral bus. The received data is double buffered and is read on the lower byte of the peripheral bus. The status and shift control logic directs the transfer of data and generates status flags for end-of-transfer (SDONE ) and detectable error conditions (WCOLL and MODF ). The bits from the SSI control registers are used by the clock divide, clock control, status/shift/control, and the I/O control logic for proper operation. The I/O control logic routes the data to and from the I/O pins as shown below.

15.1.3 Pin Configuration

Because a master MDISDO is the data input, MDOSDI is the data output and SCK is the serial clock output. SSN is the slave select signal and is always an input to the SSI unit, whether the unit is a master or a slave. If a master, the SSN input pin detects bus contention with another master in a multimaster system. Because a slave MDISDO is the data output, MDOSDI is the data input, SCK is the serial clock input, and SSN is the slave select input. The I/O control logic is directly controlled by the MSTR bit of SSI control register 1.

15.1.4 SSN Input

If SSN is low in a slave unit, the slave SSI is selected by the master for operation. If low in a master unit, this pin indicates that there is contention with another master in the system, and this will be detected as a mode fault error if SSNEN of SSI control register 1 is set to 1. The SSN pin is used by the SSI hardware (as long as SSNEN of SSI control register 1 is one) but can also be read by master or slave software from SSN of SSI control register 2. Bit 0 of SSI control register 2 reflects the state of the SSN pin, regardless of the state of SSNEN of SSI control register 1.

15.1.5 Configurations

Multimaster: in a multiple-master system, all SCK pins are tied together, all MDOSDI pins are tied together, and all MDISDO pins are tied together. Master—slave: a single SSI device is configured as a master and all other SSI devices on the SSI bus are config- ured as slaves. The master drives data onto its SCK and MDOSDI pins to the SCK and MDOSDI pins of the slaves. The slave, whose SSN input pin is low, optionally drives data out onto its MDISDO pin to the MDISDO pin of the master. The SCK, MDOSDI , and MDISDO pins are configured to behave as open-drain drivers using bits in SSI control register 1. This prevents contention on these signals if more than one SSI device tries to simultaneously drive the line. An external pull-up resistor is required on all open-drain pins.

15.1.6 Slave Chip Select

output pins for the slave select signals it sends to the SSI slaves. A—SSI control register 1, bits MSTR, SPHA. B—SSI control register 1, bit MSTR. C—SSI control register 1, bits SCLK [2:0]. D—SSI control register 1, bits EN, MSTR, SPOL, SPHA. E—SSI control register 1, bits EN, MSTR, SPOL, SPHA, SDOEN, SSNEN. F—SSI interrupt register, bits SDONE, WCOLL, MODF . Figure 25. SSI Functional Block Diagram

15.2 SSI Registers

play and enable interrupts, respectively. T able 181 below shows the register map of the SSI. Table 181. SSI Register Map

15.2.1 SSI Data Register

serves as the shift register for clocking out the bits with SCK . ering on the receive side allows a new data byte to be shifted in while the previous one is read. (in SSI control register 1) before writing the slave’s SSI data register. Table 182. SSI Data Register On reset, all SSI data register bits are set to 0. 31:8 RSVD Reserved. Must be written with zeros. 7:0 TDWR Transmit/receive data. Transmit data on write, receive data on read.

15.2.2 SSI Control Register 1

Table 183. SSI Control Register 1 15 EN Enable. Enables or disables the SSI. 14 MSTR Master mode. Configures the SSI in master or slave mode. If 1, the SSI is configured in master mode. If 0, it is configured in slave mode. 13 SPOL Idle state. Determines the idle state of the SCK clock. If 1, the SCK clock is idle at logic 1. If 0, it is idle at logic 0. 12 SPHA Data change. Determines when the data changes in each SCK cycle. 11 SDOEN Output enable. Enables output from the MDISDO pin if the SSI is configured as a slave. If 1, output from the MDISDO pin is enabled if the SSI is configured as a slave. If 1 in master mode, the SSN input is enabled and causes a mode fault. If 0 in master mode, the SSN input is disabled. If 1 in slave mode, the slave uses the SSN input to determine if it is selected for operation. If 0 in slave mode, the slave is not selected for operation. 9 MDOEN MDOSDI enable. Enables output from the MDOSDI pin if the SSI is configured as master. If 1, output from the MDOSDI pin is enabled if the SSI is configured as master.

Table 183. SSI Control Register 1 (continued) Table 184. SSI Clock Divide Bit Encoding

15.2.3 SSI Control Register 2 Bit Descriptions

several outputs as open-drain.

15.2.3.1 SSN

has been selected for operation. The slave is selected for operation if bit 0 (SSN) of SSI control register 2 is 0. SSN pin indicates whether a byte transfer is in progress since SSN is taken high between transfers. bit 0 of SSI control register 2.

15.2.3.2 FASTCLEAR

SDONE and MODF bits of the SSI interrupt register are cleared upon a read/write of the SSI data register.

15.2.3.3 MDOD

(slave) is direct-drive. If bit 3 is 1, MDOSDI (master) or MDISDO (slave) is open-drain. 8:3 RSVD Reserved. Must be set to 1.

111 Reserved

15.2.3.4 SCOD

from SCK when in master mode. If bit 4 is 0, SCK is direct-drive. If bit 4 is 1, SCK is open-drain. Table 185. SSI Control Register 2 Note: On all resets, bit 0 of SSI control register 2 is set to 1 all other bits are set to 0. Table 186. SSI Interrupt Register If bit 4 is 0 when in master mode, SCK is direct-drive. If bit 4 is 1, SCK is open-drain. MDOSDI and MDISDO when they are outputs. If bit 3 is 0, MDOSDI (master) or MDISDO (slave) is direct-drive. If bit 3 is 1, MDOSDI or MDISDO are open-drain. drain, regardless of the state of bit 3. the MODF and SDONE bits of the interrupt register. This bit is set for DMA operations with the SSI. regardless of whether SSNEN is 0 or 1. 7 SDONE Serial transfer complete interrupt. If 1, the serial transfer is completed. If 0, no transfer pending or a transfer is in progress. 6 WCOLL Write collision error interrupt. If 1, a write to the SSI data register occurred while a serial transfer was in progress. If 0, no error was detected.

Table 186. SSI Interrupt Register (continued) Table 187. SSI Interrupt Enable Register

15.3 SSI Operation

are now considered in detail. 5 MODF Mode fault error interrupt. If 1, the SSN input was asserted while the unit was in master mode and SSNEN was enabled. 4 RD_ORUN Read overrun error interrupt. This bit can only be set if the SSI is in master mode. previous byte from the slave had been read from that buffer. 7 SDONEE Serial transfer complete interrupt enable. If 1, the serial transfer interrupt is enabled. If 0, no serial transfer interrupt will occur. 6 WCOLLE Write collision error interrupt enable. If 1, the write collision interrupt is enabled. If 0, no write collision interrupt will occur. 5 MODFE Mode fault error interrupt enable. If 1, the mode fault interrupt is enabled. If 0, no mode fault interrupt will occur. 4 RD_ORUNE Read overrun error interrupt enable. If 1, the read overrun interrupt is enabled. If 0, no read overrun interrupt will occur.

15.3.1 SPHA = 0 Format

the SSN line is pulled low. For the master, transfer begins when data is written into its data register. Figure 26. SSI Transfer Timing Diagram, (SPHA = 0)

Agere Systems Inc. 209 Data Sheet T8302 Internet Protocol Telephone July 2001 Advanced RISC Machine ( ARM )

15.3.1.1 Master Operation

In the master, the data is sampled from MDISDO at the rising edge of SCK and shifted onto MDOSDI at the falling edge if SPOL = 0. If SPOL = 1, the sampling and shifting edges are reversed. At the end of eight cycles, the trans- fer is completed for the master. On the eighth sampling SCK edge, the received byte is transferred to the read data buffer, the SDONE status flag is set, and an interrupt, if enabled, is generated. The MDOSDI line stays high before the transfer begins and after it ends. This is useful in multiple master systems where the MDOSDI line is always at a known state whenever the control of the bus is relinquished to another master.

15.3.1.2 Slave Operation

On the slave side, data is sampled from MDOSDI at the rising edge of SCK and shifted onto MDISDO at the falling edge if SPOL = 0. If SPOL = 1, the sampling and shifting edges are reversed. The received data is buffered on the eighth sampling SCK edge, the SDONE flag is set, and the interrupt, if enabled, is generated. The end of transfer, however, is indicated only if the SSN signal is deasserted. At that time, the MDISDO output pin stops driving. Note: In multiple byte transfers, the SSN line is asserted and deasserted between successive bytes if SPHA = 0. If the master sends another byte before deasserting and reasserting the SSN line, then the transfer is not guaran- teed to be correct.

15.3.2 SPHA = 1 Format

Figure 27 shows the timing diagram of the serial byte transfer if SPHA = 1. SCK is shown for both cases of SPOL , i.e., SPOL = 0 and SPOL = 1. The MDOSDI signal is the output of the master and input to the slave. The MDISDO signal is the output from the slave and input to the master. The timing diagrams are interpreted either from the master’s or the slave’s side. The SSN line is the slave select line. The slave output is enabled as long as SSN is held low. Note: In multiple byte transfers, the SSN line is held asserted (low) between successive bytes if SPHA = 1. The SSN line can be tied low if SPHA = 1.

Figure 27. SSI Transfer Timing Diagram, (SPHA = 1)

15.3.2.1 Master

Agere Systems Inc. 211 Data Sheet T8302 Internet Protocol Telephone July 2001 Advanced RISC Machine ( ARM ) flag is set, and an interrupt, if enabled, is generated. The MDOSDI line stays high before the transfer begins and after it ends. This is useful in multiple master systems where the MDOSDI line is always at a known state whenever the control of the bus is relinquished to another master.

15.3.2.2 Slave

On the slave side, the data is sampled from MDOSDI at the falling edge of SCK and shifted onto MDISDO at the rising edge if SPOL = 0. If SPOL = 1, the sampling and shifting edges are reversed. The received data is buffered at the end of seven and a half shift clock cycles (i.e., on the eighth sampling SCK edge), the SDONE flag is set, the interrupt, if enabled, is generated, and the end of transfer is indicated. The output, however, remains valid until SSN is deasserted. At that time, the MDISDO pin stops driving.

15.3.3 Transfer Start

Every SSI transfer consists of an initiation period, followed by eight SCK cycles if the 8-bit data transfer takes place, and finally the ending period. The details for the data transfer were considered in the previous section. Here the initiation period is discussed for each of the different formats selected for the master and slave modes of oper- ation. If the SSI is configured as a master, all transfers are initiated by a write to the SSI data register. Such a write is necessary even if the master is only interested in receiving data from the slave. There is a delay of three system clock cycles after the write access before the start of the serial transfer. If SPHA = 0, SCK remains at its idle state for the first half of the cycle following the write to the SSI data register. If SPHA = 1, the transfer cycle begins immediately with the SCK going from its inactive level to the active level. If the SSI is configured as a slave and SPHA = 0, a transfer begins if the SSN line is pulled low. The MSB of the data written in the slave SSI data register initially appears on the MDISDO line. If the SSI is configured as a slave and SPHA = 1, a transfer begins with the first active edge of SCK , provided that the slave is selected (SSN asserted).

15.3.4 Transfer End

A transfer is complete if all 8 bits are shifted in serially, the data is transferred to the read data buffer, and the SDONE flag is set. The interrupt signal (IRQ ) will be active if SDONEE is set in the SSI interrupt enable register.

15.3.4.1 Master Operation

If the SSI is configured as a master, the received byte is transferred to the read-buffer at the end of eight SCK clock cycles. The SDONE flag is set after a delay (independent of the SCK rate) of one system clock cycle.

15.3.4.2 Slave Operation

If the SSI is configured as a slave, the ending period depends on the value of SPHA . If SPHA = 0, SDONE is set at the end of the eighth SCK cycle (one-half SCK cycle after the last bit is sampled by the slave). If SPHA = 1, SDONE is set in the middle of the eighth SCK cycle (at the time the last bit is sampled). Since the master always ends the transfer at the end of the eighth SCK cycle, the SDONE bit in the slave completes the transfer if SPHA = 1.

212 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001

15.3.5 Interrupt Generation

If the SSI interrupt is enabled in the interrupt controller’s SSI interrupt enable register, the SSI asserts its interrupt request whenever a byte is successfully shifted in and copied to the read data buffer (i.e., if the SDONE bit is true, or if a mode fault or read overrun occurs). The interrupt is cleared if SDONE , MODF , and RD_ORUN are cleared.

15.3.6 Status Flags and Error Conditions

The SSI interrupt register contains four read-only status bits, SDONE, WCOLL, MODF , and RD_ORUN . There is another error condition that occurs if the SSI is configured as a slave and a transfer is aborted by the mas- ter unit pulling SSN high or the slave software writing SSI control register 1 bit 10:0 before the transfer is com- plete. This error condition is not indicated by the status flags and is detected by a software protocol. The status and error conditions are described below.

15.3.6.1 SDONE

SDONE is a status flag that indicates the end of a transfer. At the end of a transfer, the SDONE bit of SSI interrupt register is set. If the FASTCLEAR bit of SSI control register 2 = 1, the SDONE flag is cleared by a read or write of the SSI data register. If FASTCLEAR of SSI control register 2 = 0, the SDONE flag is cleared by writing to the SDONE bit in the SSI interrupt register to clear the SSI interrupt.

15.3.6.2 WCOLL Flag

The WCOLL bit of SSI interrupt register indicates that a write collision error occurred. A write collision error is detected if a write to the SSI data register is attempted while a transfer is in progress. The transfer continues but the data that caused the error may or may not be written to the transmit buffer. Because of this uncertainty, a trans- fer that experiences a write collision error is aborted and should be tried later. If the SSI is configured as a master, a transfer begins when data is written to the SSI data register and ends when the received data is transferred to the read data buffer, at which time SDONE is set. Note: A write collision error should not occur in master mode if the driver software is structured correctly. If the SSI is configured as a slave, it has no way to predict when the master will initiate a transfer. However, if SPHA = 0, the true end of the transfer does not occur until the SSN signal is deasserted. In this case, the user determines both the beginning and the end of transfer by polling the SSN line using bit 0 of SSI control register 2. The SPHA = 1 mode is more problematic since SSN is held low constantly or between transfers so SSN cannot always be used to tell whether a transfer is in progress. The end of transfer is determined via the SDONE flag in the SSI interrupt register, but there is no satisfactory way of determining the beginning of transfer. Therefore, write collisions are possible for this mode. However, these write collisions in the slave are avoided by writing SSNEN of SSI control register 1 to zero before writing the slave’s SSI data register. If SSNEN of SSI control register 1 is written to 0 during a transfer, the transfer terminates. The WCOLL flag, once set, is cleared by writing a 1 to the WCOLL field in the SSI interrupt register, followed by a read or write of the SSI data register.

15.3.6.3 MODF

The MODF bit indicates a mode fault. A mode fault error occurs when the SSI is configured as a master and the SSN line is asserted. The SSNEN bit of SSI control register 1 (see Table 183 on page 204) is enabled for the SSN line to be recognized in master mode. If a mode fault is detected, the master SSI immediately disables its SCK clock and MDOSDI data output pins in order to eliminate any bus contention.

Agere Systems Inc. 213 Data Sheet T8302 Internet Protocol Telephone July 2001 Advanced RISC Machine ( ARM ) If the SSN signal is asserted by another master some considerable time after the master enables its SCK and MDOSDI drivers, the following events occur: I The SSI is disabled. The EN bit of SSI control register 1 is set to 0. I The SSI is reconfigured as a slave. The MSTR and SDONE bits are cleared to 0. I The master data output is disabled. I The SCK output pin is disabled. I MODF flag of SSI interrupt register is set to 1. Note: The MDOEN bit of SSI control register 1 remains set although this is harmless, since the SSI is reconfig- ured as a slave after the mode fault so the MDOEN bit has no effect. The MODF interrupt is asserted if MODFE is enabled in the SSI interrupt enable register. If the FASTCLEAR bit of SSI control register 2 is 1, the MODF flag is cleared by a read/write of the SSI data register. If the FASTCLEAR bit of SSI control register 2 is zero, the MODF flag is cleared by writing a 1 to the SSI interrupt register’s MODF .

15.3.6.4 RD_ORUN

If the SSI is configured as a master, a read overrun error can occur if the RD_ORUN bit is set in the SSI interrupt enable register. The RD_ORUN bit in SSI interrupt register indicates the error. If RD_ORUN is 1 and the SSI is a master, a read overrun error occurs when the master’s SSI data register is overwritten with new data from the slave before the prior data from the slave is read from the register. The SSI data register is written with new data from the slave at the end of each byte transfer. It is anticipated that the read overrun error will be enabled (i.e., RD_ORUN will be 1) only when the DMA is being used to transfer data from the SSI data register to memory. A read overrun error can occur when the firmware writes a new data byte (e.g., byte number 2) to the SSI data register (that starts a new transfer) before the DMA reads the byte (e.g., byte number 1) previously received from the slave. The SSI data register is double-buffered on the read side, so byte number 1 is not overwritten in the SSI data reg- ister with the new data received from the slave (byte number 3) until the end of the transfer of byte number 2. This means that in order to avoid a read overrun error, the DMA must read byte number 1 from the SSI data register before the transfer of byte number 2 is complete. If a read overrun error does occur, the RD_ORUN bit will be set in SSI interrupt register and an interrupt will be generated from the SSI. The RD_ORUN bit and the interrupt are automatically cleared by writing a 1 to the RD_ORUN field in the SSI interrupt register.

15.3.7 SSI Transfer Abort

An ongoing transfer to a slave is aborted by the master by deasserting the SSN signal to the slave or by the slave software writing a 0 to SSI control register 1 bit 10 in the slave. If the SSI is configured as a slave and the SSN line is pulled high, or SSI control register 1 bit 10 goes to 0 during transmission, all counters are reset. The state of the SSI data register is frozen at the time of the occurrence of the error. New data has to be written to the slave’s SSI data register to have a meaningful transmission following the error. There are no flags to indicate an aborted transfer. This condition is detected by software protocol.

214 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001

15.3.8 SSNEN Control Register Bit

The SSNEN bit in SSI control register 1 enables the SSN signal in both the master and slave modes. SSI control register 1, bit 14, determines whether the SSI is a master or slave. When the SSI is a master, setting SSNEN allows a mode fault (SSI interrupt register, bit 5 MODF ) to occur if the SSN input pin is asserted, meaning that some other unit in the SSI system is erroneously trying to select this mas- ter as a slave. When the SSI is a slave, setting SSNEN causes the slave to use the SSN input pin to determine whether it is selected. (If SSN is low, the slave is selected for operation, and if high, the slave is not selected for operation.) Clearing SSNEN prevents the slave from being selected for operation. It is sometimes necessary to write SSNEN to 0 before writing the slave’s SSI data register. For both master and slave SSI configurations, the status of the SSN input pin is always readable from bit 0 of SSI control register 2, regardless of the state of the SSNEN bit.

16 Parallel Peripheral Interface (PPI)

I Each bit is programmed as either an input or an output. I Inputs are programmed to be level-sensitive. I Outputs are programmed to be open-drain or direct-drive. I Programmable polarity (inverted or not) for inputs and outputs. I An interrupt request can be generated when a desired level occurs on any general purpose input pin. I Each I/O can be programmed to have an internal pull-up connected.

16.1 PPI Operation

(see T able 190 on page 219) is used to read input pins and to write output pins. enable register (see Table 194 on page 221) allows an internal pull-up resistor to be connected to the pins. Figure 28. Parallel Peripheral Interface (PPI) Block Diagram

216 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001

16 Parallel Peripheral Interface (PPI) (continued)

16.1.1 PPI Pin Configuration on Reset

After reset, all PPI pins are configured as inverting inputs with pull-ups enabled.

16.1.2 Procedure for Writing to an Output Pin

1. Program the PPI data direction register for the pin as an output. 2. Program the PPI port sense register for the output as open-drain or direct-drive. 3. Program the PPI port polarity register for the output as inverted or noninverted (relative to the PPI port data register). 4. Write a value in the PPI port data register, PPI port data clear register, or PPI port data set register to specify the output level. If the corresponding PPI port polarity register bit is 1, a 1 in the PPI port data reg- ister causes the output pin to drive high if it is programmed as a direct-drive output or causes the output pin to go to high impedance if it is programmed as an open-drain output. Conversely, if the corresponding port polarity register bit is 0, a 1 in the PPI port data register causes both direct-drive and open-drain output pins to drive low.

16.1.3 Procedure for Reading from an Input Pin

1. Program the PPI port data direction register for the pin as an input. 2. Set the PPI port sense register to 0. 3. Program the PPI pull-up enable register if a pull-up resistor is desired on the I/O. 4. Program the PPI port polarity register to indicate whether the level on the pin is inverted before going to the PPI port data register. 5. Read the PPI port data register. Note: Reading the PPI port data clear register or the PPI port data set register has the same effect as reading the PPI port data register.

16.1.3.1 Additional Read/Write Notes

I If the PPI bit is configured as an input, a high value on the pin is read as 1 in the PPI port data register if the cor- responding bit of the PPI port polarity register is 1. Conversely, a low value on the input is read as 1 if the cor- responding bit of the PPI port polarity register is 0. I When the PPI port data register is written, only the chip pins configured as outputs are modified; those config- ured as inputs are unaffected. I Input pins are asynchronous and are sampled at the system clock rate. In order for an input signal to be regis- tered, it must have a minimum pulse-width of two system clock periods; see Figure 29 below. The CLK in this fig- ure is the SYSTEM_CLK as defined by the clock selected in the reset/cock management section (see Reset/ Clock Management on page 29).

Figure 29. Minimum Data Input Pulse Width

16.1.4 PPI Port Interrupts

enabled in the PPI port interrupt enable register (see Table 191 on page 219) do not result in PPI interrupts. data register reflects the inverse of the level on the pin. PPI port data register, the write to the register is ignored and the port’s interrupt request remains active. inputs occurs in the window between interrupt generation and clearing of the port’s interrupt request.

16.2 PPI Registers

Table 188. PPI Parallel I/O Controller Register Map

16.2.1 PPI Data Direction Register

tion register are cleared to zeros, indicating inputs. Table 189. PPI Data Direction Register

16.3 PPI Port Data Register

bits configured as inputs reflect the (possibly inverted) level on the input pin. 15:0 PD[15:0] Data direction bits. If 1, it indicates an output. If 0, it indicates an input.

Table 190. PPI Port Data Register tion must be performed on the PPI port data register in order to avoid changing other bits. bits of the PPI port data register using only one operation.

16.3.1 PPI Interrupt Enable Register

ured in the PPI port polarity register. On reset, bits of this register are set to 0. Table 191. PPI Interrupt Enable Register

16.3.2 PPI Port Sense Register

the PPI port sense register. On all resets, all bits in the register are cleared to 0. 15:0 P[15:0] Port data bits. Bits configured as outputs reflect the value previously written to the register. Bits configured as inputs reflect the (possibly inverted) level on the input pin. generates interrupts based on how it is configured in the PPI port polarity register.

Table 192. PPI Port Sense Register

16.3.3 PPI Port Polarity Register

described in the following paragraphs. (inverted, direct-drive output). in the PPI port data register (inverted, open-drain output). On reset, all bits of the PPI port polarity register are cleared to 0, indicating inversion. Table 193. PPI Port Polarity Register sponding bit in the PPI port sense register must be set to 0. bit is set to 0, the corresponding input/output signal is inverted.

16.3.4 PPI Pull-Up Enable Register

PPI port pull-up enable register. On reset, all bits of this register are set to 1. to the I/O pins even if the pins are being used for non-PPI functions. inactive on all inputs. Immediately after reset, the pull-ups are active on all inputs. Table 194. PPI Pull-Up Enable Register

16.3.5 PPI Port Data Clear Register

PPI I/O pin. Each of the bits corresponds to a bit in the PPI port data register. A read of the PPI port data clear register address returns the data in the PPI port data register. Table 195. PPI Port Data Clear Register

16.3.6 PPI Port Data Set Register

I/O pin. Each of the 16 bits corresponds to a bit in the PPI port data register. pin is connected to an internal pull-up. PPI port data register remain unchanged.

A read of the PPI port data set register address returns the data in the PPI port data register. Table 196. PPI Port Data Set Register

16.4 Summary of Programming Modes

Table 197. PPI Programming Modes data register remain unchanged. 0 0 0 Inverted, level sensitive input. 0 0 1 Noninverted, level sensitive input. 1 0 0 Inverted, direct drive output. 1 0 1 Noninverted, direct drive output. 1 1 0 Inverted, open drain output. 1 1 1 Noninverted, open drain output.

17 Key and Lamp Controller (KLC)

up to 56 LEDs and scan up to 56 keys. The KLC also contains two direct LED connections for a total of 58 LEDs. I OFF—default state All LEDs are placed in this state by a reset. I WINK—200 ms on then 50 ms off. I INVERSE WINK—200 ms off then 50 ms on. I FLASH—500 ms on then 500 ms off. I INVERSE FLASH—500 ms off then 500 ms on. I FLUTTER—50 ms on then 50 ms off. I BROKEN FLUTTER—500 ms of flutter then 500 ms off. I STEADY ON—continuously on. Figure 30. KLC Interface Matrix

224 Agere Systems Inc. T8302 Internet Protocol Telephone Data Sheet Advanced RISC Machine (ARM ) July 2001

17 Key and Lamp Controller (KLC) (continued)

17.1 KLC Operation

A schematic of the KLC interface matrix is shown in Figure 30. The KLC uses a time-division multiplexed scheme for sampling the keyboard matrix and driving the LED matrix. The keyboard matrix is sampled once every 12.5 ms and the LED matrix is driven between key samples. The values stored in the lamp rate registers determine the flash patterns for all LED's in the matrix. The key scan status register contains information about what keys are pressed and the current state of the switch-hook at the end of the key scan cycle. The KLC noscan control regis- ter contains the reset bit for the KLC and allows control over the amount of time the KLC will wait to sample the key matrix after detecting a key press or release. Interrupts generated by key-presses, key releases, or the switch-hook will be noted in the KLC interrupt register if the specific type of KLC interrupt is enabled in the KLC interrupt enable register.

17.1.1 LED Drive Matrix Operation

The KLC drives the LEDs in its matrix in a time division multiplexed scheme. Each LED row is activated (driven low) one at a time. While that row is activated, all LEDs in that row that are programmed to be on at that time will be illu- minated by activating those LED’s columns (driving them high). LEDs that are not programmed to be illuminated will have their columns deactivated. In order for LEDs to be activated, the LCNTRL output must be high. While the KLC is transitioning between LED rows, the LCNTRL signal turns off power to the LED matrix for a short time. This allows time for the column outputs to change for the new row. Upon completion of the LED drive time for all rows LCNTRL will deactivate the LED matrix, and the key matrix will be sampled. Then the LED rows will be driven again in the same order starting with row 0 and ending with row 6. The KLC contains 29 LED rate registers. Each of these registers controls two LEDs. The first 28 registers control the LEDs in the LED matrix. The twenty-ninth register controls the message and speaker LED direct-drive output pins. All LED rate registers are set to all zeros (LEDs off) during reset. The KLC will generate the rate patterns for the LED drive from the 32.768 kHz input clock (RTC). Each of the LEDs will be driven by one of these patterns. This means that every LED, set to the same pattern, will turn on and off at the same time and will remain in syn- chronization with each other. The LED drive matrix elements must be designed to handle the current needed by the LED drive matrix. The exter- nal row PNP transistors must be capable of driving all LEDs in its respective row. At higher currents, the forward current gain of most transistors must be derated from their typical values. In addition, as these transistors are driven into saturation, the current gain is also reduced. The KLC row outputs are designed with an 8 mA output driver to provide adequate low-level current output capacity. The LCNTRL external NPN transistor must be able to handle as much current as any row transistor. Its output is designed with an 8 mA output driver that provides at least 8 mA of high-level current output capacity that will adequately drive a properly selected transistor into satura- tion. Each external column NPN transistor handles at most a single LED’s current at any one time. The column output pins are designed with 4 mA output buffers. These buffers can provide an output high-level current capacity of 4 mA that is more than sufficient to drive the external matrix transistors. The message and speaker LED output pins MSGLED and SPKRLED are designed with an 8 mA output buffer that will handle either a red or a green LED.

17.1.2 Key Scan Matrix Operation

The KLC scans its key matrix by asserting the row outputs and checking for connections to any column inputs (indi- cating a pressed key). The KLC turns off all LEDs by driving its master LCNTRL output to an inactive state, dis- abling all LED columns. The KLC then 3-states the column inputs leaving their internal 50 kΩ pull-down resistor connected, asserting all row outputs simultaneously. Any key that is depressed will connect its column pin to its row pin via a low-impedance path and will pull the column pin high. If no keys are pressed, the column inputs remain low (due to their internal pull-down resistors) and the KLC precedes with its next LED drive cycle.

Agere Systems Inc. 225 Data Sheet T8302 Internet Protocol Telephone July 2001 Advanced RISC Machine ( ARM ) However, if any column inputs are found to be high indicates that a key must be pressed and the KLC will deter- mine its location. When a user depresses keys on the keypad, the keys often bounce before settling into the on state. To avoid this problem, a debounce interval has been incorporated into the design. The debounce interval is the period between detecting that a key has been pressed, and the time it scans the matrix to detect which specific key has been pressed. During this interval of roughly 2.5 ms, the KLC switches to LED drive mode and drives the first three rows of the LED matrix. After finishing the third LED row's time slice, the KLC disables the LED matrix and scans the key matrix to determine which key has been pressed. This process involves asserting each row output individually for roughly 125 ns and checking the column inputs. When a certain row causes a certain column to be asserted, the location of the key has been determined. At the end of this interval, the key scan status register is set with the row and column of the pressed key (see Table 204 on page 230) and any enabled interrupts corresponding to the key-press are asserted. The remaining four LED rows are driven after locating the key to finish the LED drive cycle that was interrupted by the key location process. The KLC provides a programmable delay interval after it detects a key transition. During this noscan interval the key matrix will not be scanned. The KLC will not scan the key matrix for 0, 1, 2, or 3 LED drive cycles depending on the programmed noscan code residing in the noscan control register, see Table 202 on page 229. After this nos- can delay interval, the KLC begins waiting for the key to be released. During these key scan intervals, the KLC asserts the row containing the pressed key and checks the column containing the pressed key. If the column is still pulled high, the key is still depressed. If the column stays low, the key has been released and again the key scan status register and interrupt registers are updated. A noscan period is also inserted after the key is released before any new key presses can be noted. The process for detecting a key press and release is summarized in the following state description: I Ready to detect key depression: the KLC is looking for a key depression and upon completion of driving the last LED row (ROW8 ) it will sample all the rows of the key matrix. If it detects a key depression, it will enter the next state. I Detected key depression: the KLC detected a key depression during the last key sample cycle. It waits 2.5 ms as a key debounce time and then scans each row in the key matrix. The row/column address of the first key it finds depressed will be recorded in the key scan status register. The press bit will also be set to 1 on the following clock, setting the row/column address. This will generate an interrupt to the processor if the corresponding bit is enabled in the interrupt controller. After recording the key depression in the key scan status register, the KLC will enter the next state. I Detected key wait: after recording a key depression in its register, the KLC will not sample the key matrix at the end of the cycle during which it scanned the matrix. In addition, the KLC will not scan the key matrix again for the time set in the noscan control register. I Wait for key release: when the noscan interval has expired the KLC will enter this state. The KLC will sample the key matrix looking only for the key recorded in its key scan status register. When the KLC detects that key as not being depressed, it will reset the press bit in its key scan status register to 0. I Key released wait: the KLC detected that the key it recorded as pressed has now been released. The KLC will wait the number of LED drive cycles programmed into its noscan control register before acting on any new key depressions. When the noscan interval has expired, the KLC will enter the first state. The circuit interface to the KLC should be designed so that the red and green LEDs associated with a key are placed in the same row and adjacent columns. This would place both LEDs in the same register with the red LED in the low nibble and the green LED in the high nibble. If more than one key is depressed at a time, the KLC detects the first key that is registered as being pressed. If multiple keys are pressed in one column of the key matrix during the keyboard scanning cycle, one row will attempt to pull the column high while the other rows will pull the column low. To avoid a short in this situation, diodes have been placed in the KLC interface matrix, see Figure 30 on page 223.

17.1.3 KLC Interrupts

register. This action will clear the KLC interrupt register bit and will remove the interrupt.

17.1.4 Timing and Reset

notifying the user of the reset.

17.2 KLC LED Drive and Key Scan Matrix Pins

I Seven row-output pins K_ROW6:0 . I Eight column-output pins K_COL7:0 . I The signal to enable or disable current in the LED drive matrix LCNTRL . I Two outputs used to drive the speaker and message LEDs. I Switch hook sampling input. Table 198. KLC Matrix Pins Low active for LED drive matrix. High active for key scan matrix.

driven active-high to enable the entire LED drive matrix.

17.3 KLC Register

17.3.1 Lamp Rate Registers

eration to the speaker and message LEDs. There are 56 LEDs; one register for two LEDs. Table 199. KLC Register Map Table 198. KLC Matrix Pins (continued)

17.3.2 KLC Noscan Control Register

will exit reset at the next low to high transition of its 32 kHz clock and start its lamp timing cycle from the beginning. puts, turning off the two LEDs. as soon as the reset pin is low and the clock is present. Table 200. Lamp Rate Registers Table 201. Lamp Rate Bit Encoding 0 1 0 Inverse wink (200 ms off, 50 ms on). 0 1 1 Inverse flash (500 ms off, 500 ms on). 1 1 0 Broken flutter (500 ms of flutter, 500 ms off).

Table 202. Noscan Control Register Table 203. Noscan Delay Interval Encoding executed before the key is located. After the key is located, the KLC must finish the suspended LED drive period. This takes roughly 10 ms, that accounts for the difference in key depression and key release noscan intervals.

17.3.3 Key Scan Status Register

interval has elapsed, the KLC will check that key once every 12.5 ms to determine if that key has been released. grammed noscan interval again before it will act on any new key depressions found during its sampling interval. enable register are left unchanged. If 0, then the KLC will start (or continue) operation. default interval) by a hardware reset.

17.3.4 KLC Interrupt Register

this register will be left unchanged. Table 205. KLC Interrupt Register

17.3.5 KLC Interrupt Enable Register

page 51). For a software reset (setting RESET in T able 202 on page 229), this register will be left unchanged. Table 204. Key Scan Status Register 7 KEYPRESS 1 = key press; 0 = no key press. 6 SWHOOKON/OFF Switch hook on/off. 5 K_ROW bit 2 Press key row number (MSB). 4 K_ROW bit 1 Press key row number. 3 K_ROW bit 0 Press key row number (LSB). 2 K_COL bit 2 Press column row number (MSB). 1 K_COL bit 1 Press column row number. 0 K_COL bit 0 Press column row number (LSB). 2 SWHK Switch hook status change interrupt. 1 KEYR Key release interrupt. Table 206. KLC Interrupt Enable Register 2 SWHRE Switch hook status change interrupt enable. 1 KEYRE Key release interrupt enable. 0 KEYPE Key press interrupt enable.

18 JTAG/Boundary Scan

I Refer to the ARM 940T documentation for additional information about JT AG and T AP controller signals.

18.1 Debug Support

I Breakpointing on two watchpoints or breakpoints. I Single-stepping or step-by-N through code. I Inspection and modification of ARM accessible registers. I Inspection and modification of ARM memory. I Device reset through JT AG.

18.2 The Principle of Boundary Scan Architecture

referred to as output cells. Input and output is relative to the core logic of the device. Table 207. Boundary Scan Pin Functions Debug mode, or boundary scan mode is selected via the JMODE pin (V18) as shown below. V18 JMODE When 0 = boundary scan.

18 JTAG/Boundary Scan (continued)

Figure 31. Boundary Scan Architecture boundary scan register (boundary scan). I A finite-state machine TAP controller with inputs JTCK and JTMS. I An n-bit (n = 4) instruction register (IR), holding the current instruction. I A 1-bit bypass register (BYP ASS).

Figure 32. JTAG Interface Timing Diagram

18.2.1 Instruction Register

The instruction register is 4 bits long and the capture value is 0001.

• Output all specified with 20 pF load.

Table 208. Instruction Register EXTEST 0000 Places the boundary scan register in EXTEST mode. SAMPLE 0010 Places the boundary scan register in sample mode. IDCODE 1110 Identification code. BYP ASS 1111 Places the bypass register in the scan chain.

18.3 Boundary Scan Register

Note: The control column of the following table indicates the value for boundary scan control of this pin. Table 209. Boundary Scan Register Description

0 DSP_D_E — Controller— 0 —

1 DSP_D(0) B1 I/O DSP_D_E 0 50 kW pull-up

2 DSP_D(5) C1 I/O DSP_D_E 0 50 kW pull-up

3 DSP_D(6) D1 I/O DSP_D_E 0 50 kW pull-up

4 DSP_D(9) E1 I/O DSP_D_E 0 50 kW pull-up

5 DSP_D(13) F1 I/O DSP_D_E 0 50 kW pull-up

6 DSP_RWN_E — Controller— 0 —

7 DSP_RWN G1 I/O DSP_RWN_E 0 High impedance

8 DSP_A_E — Controller— 0 —

9 DSP_A(0) H1 I/O DSP_A_E 0 High impedance

10 DSP_A(4) J1 I/O DSP_A_E 0 High impedance

11 DSP_A(7) K1 I/O DSP_A_E 0 High impedance

12 DSP_A(8) L1 I/O DSP_A_E 0 High impedance

13 RESETN N1 I — — —

14 T_REQB U1 I — — 50 kΩ pull-down

15 MDOSDI_E — Controller— 0 50 kΩ pull-up

16 MDOSDI W1 I/O MDOSDI_E 0 50 kΩ pull-up

17 USBAL TCK_E Controller— 0 50 kΩ pull-up

18 USBAL TCK Y1 I/O BAL TCK_E 0 High impedance

19 K_ROW_E(5) — Controller— 0 —

20 K_ROW(5) Y2 I/O K_ROW_E(5) 0 High impedance

21 K_ROW_E(1) — Controller— 0 —

22 K_ROW(1) Y3 I/O K_ROW_E(1) 0 High impedance

23 K_ROW_E(0) — Controller— 0 —

24 K_ROW(0) Y4 I/O K_ROW_E(0) 0 High impedance

25 K_COL_E — Controller— 0 —

26 K_COL(5) Y5 I/O K_COL_E 0 50 kΩ pull-down

27 K_COL(1) Y6 I/O K_COL_E 0 50 kΩ pull-down

28 MSGLED_E — Controller— 0 —

29 MSGLED Y7 I/O MSGLED_E 0 High impedance

30 TMODE(0) Y8 I — — 50 kΩ pull-up

31 SC_MODEN_E — Controller— 0 —

32 SC_MODEN Y9 I/O SC_MODEN_E 0 50 kΩ pull-up

33 TESTPT_E(16) — Controller— 0 —

34 TESTPT(16) Y13 I/O TESTPT_E(16) 0 High impedance

35 TESTPT_E(13) — Controller— 0 —

36 TESTPT(13) Y14 I/O TESTPT_E(13) 0 High impedance

37 TESTPT_E(11) — Controller— 0 —

38 TESTPT(11) Y15 I/O TESTPT_E(11) 0 High impedance

39 TESTPT_E(8) — Controller— 0 —

40 TESTPT(8) Y16 I/O TESTPT_E(8) 0 High impedance

41 TESTPT_E(4) — Controller— 0 —

42 TESTPT(4) Y17 I/O TESTPT_E(4) 0 High impedance

43 TESTPT_E(1) — Controller— 0 —

44 TESTPT(1) Y18 I/O TESTPT_E(1) 0 High impedance

45 OMUXSEL(2) Y19 I — — 50 kΩ pull-up

46 XS_E(1) Controller— 0 —

47 XS(1) Y20 I/O XS_E(1) 0 High impedance

48 LS10_OK_E(1) — Controller— 0 —

49 LS10_OK(1) J20 I/O LS10_OK_E(1) 0 High impedance

50 PPI_E(12) — Controller— 0 —

51 PPI(12) H20 I/O PPI_E(12) 0 High impedance

52 PPI_E(9) — Controller— 0 —

53 PPI(9) G20 I/O PPI_E(9) 0 High impedance

54 PPI_E(7) — Controller— 0 —

55 PPI(7) F20 I/O PPI_E(7) 0 High impedance

56 PPI_E(4) — Controller— 0 —

57 PPI(4) E2 I/O PPI_E(4) 0 High impedance

58 PPI_E(0) — Controller— 0 —

59 PPI(0) D20 I/O PPI_E(0) 0 High impedance

60 TX1 B20 Out2 — — —

61 RDARX0 A20 I — — —

62 A_E — Controller— 0 —

63 A(23) A19 I/O A_E 0 High impedance

64 A(18) A18 I/O A_E 0 High impedance

65 A(17) A17 I/O A_E 0 High impedance

66 A(14) A16 I/O A_E 0 High impedance

67 A(10) A15 I/O A_E 0 High impedance

68 A(7) A14 I/O A_E 0 High impedance

69 A(4) A13 I/O A_E 0 High impedance

70 A(0) A12 I/O A_E 0 High impedance

71 WRN_E — Controller— 0 —

72 WRN A11 I/O WRN_E 0 High impedance

73 CS1_E — Controller— 0 —

74 CS1 A10 I/O CS1_E 0 High impedance

75 EXWAIT_E — Controller— 0 —

76 EXWAIT A9 I/O EXWAIT_E 0 High impedance

77 SDCASN_E — Controller— 0 —

78 SDCASN A8 I/O SDCASN_E 0 High impedance

Table 209. Boundary Scan Register Description (continued)

79 SDLDQM_E — Controller— 0 —

80 SDLDQM A7 I/O SDLDQM_E 0 High impedance

81 DH_E v Controller— 0 —

82 D(15) A6 I/O DH_E 0 50 kΩ pull-up

83 D(12) A5 I/O DH_E 0 50 kΩ pull-up

84 D(8) A4 I/O DH_E 0 50 kΩ pull-up

85 DL_E — Controller— 0 —

86 D(5) A3 I/O DL_E 0 50 kΩ pull-up

87 D(0) A2 I/O DL_E 0 50 kΩ pull-up

88 D(1) B2 I/O DL_E 0 50 kΩ pull-up

89 DSP_D(1) C2 I/O DSP_D_E 0 50 kΩ pull-up

90 DSP_D(2) D2 I/O DSP_D_E 0 50 kΩ pull-up

91 DSP_D(8) E2 I/O DSP_D_E 0 50 kΩ pull-up

92 DSP_D(12) F2 I/O DSP_D_E 0 50 kΩ pull-up

93 DSP_D(15) G2 I/O DSP_D_E 0 50 kΩ pull-up

94 DSP_ICSN_E — Controller— 0 High impedance

95 DSP_ICSN H2 I/O DSP_ICSN_E 0 High impedance

96 DSP_A(3) J2 I/O DSP_A_E 0 High impedance

97 DSP_A(5) K2 I/O DSP_A_E 0 High impedance

98 DSP_A(9) L2 I/O DSP_A_E 0 High impedance

99 CLKREF_E — Controller— 0 —

100 CLKREF M2 Out3 CLKREF_E 0 High impedance

101 RSTON_E — Controller— 0 —

102 RSTON N2 Out3 RSTON_E 0 High impedance

103 T_ACK_E — Controller— 0 —

104 T_ACK T2 Out3 T_ACK_E 0 High impedance

105 SCK_E — Controller— 0 —

106 SCK V2 I/O SCK_E 0 High impedance

107 SSN_E — Controller— 0 —

108 SSN W2 I/O SSN_E 0 High impedance

109 K_ROW_E(6) — Controller— 0 —

110 K_ROW(6) W3 I/O K_ROW_E(6) 0 High impedance

111 K_ROW_E(4) — Controller— 0 —

112 K_ROW(4) W4 I/O K_ROW_E(4) 0 High impedance

113 K_COL(6) W5 I/O K_COL_E 0 50 kΩ pull-down

114 K_COL(2) W6 I/O K_COL_E 0 50 kΩ pull-down

115 LCNTRL_E — Controller— 0 —

116 LCNTRL W7 I/O LCNTRL_E 0 High impedance

117 SWHOOK_E — Controller— 0 —

118 SWHOOK W8 I/O SWHOOK_E 0 High impedance

119 TMODE(3) W9 I X — 50 kΩ pull-up

120 SC_ENAN_E — Controller— 0 —

121 SC_ENAN W10 I/O SC_ENAN_E 0 50 kΩ pull-up

122 TESTPT_E(19) — Controller— 0 High impedance

123 TESTPT(19) W12 I/O TESTPT_E(19) 0 High impedance

124 TESTPT_E(15) — Controller— 0 —

125 TESTPT(15) W13 I/O TESTPT_E(15) 0 High impedance

126 TESTPT_E(12) — Controller— 0 —

127 TESTPT(12) W14 I/O TESTPT_E(12) 0 High impedance

128 TESTPT_E(9) — Controller— 0 —

129 TESTPT(9) W15 I/O TESTPT_E(9) 0 High impedance

130 TESTPT_E(5) — Controller— 0 —

131 TESTPT(5) W16 I/O TESTPT_E(5) 0 High impedance

132 TESTPT_E(2) — Controller— 0 —

133 TESTPT(2) W17 I/O TESTPT_E(2) 0 High impedance

134 OMUXSEL(1) W18 I X — 50 kΩ pull-up

135 XS_E(0) — Controller— 0 —

136 XS(0) W19 I/O XS_E(0) 0 High impedance

137 LS100_OK_E(0) — Controller0 0 —

138 LS100_OK(0) K19 I/O LS100_OK_E(0) 0 High impedance

139 PPI_E(15) — Controller— 0 —

140 PPI(15) J19 I/O PPI_E(15) 0 High impedance

141 PPI_E(11) — Controller— 0 —

142 PPI(11) H19 I/O PPI_E(11) 0 High impedance

143 PPI_E(8) — Controller— 0 —

144 PPI(8) G19 I/O PPI_E(8) 0 High impedance

145 PPI_E(5) — Controller— 0 —

146 PPI(5) F19 I/O PPI_E(5) 0 High impedance

147 PPI_E(1) — Controller— 0 —

148 PPI(1) E19 I/O PPI_E(1) 0 High impedance

149 PWRFL TN D19 I X — 50 kΩ pull-up

150 IRDA TX0_E — Controller— 0 —

151 IRDA TX0 B19 out3 IRDA TX0_E 0 High impedance

152 A(22) B18 I/O A_E 0 High impedance

153 A(21) B17 I/O A_E 0 High impedance

154 A(15) B16 I/O A_E 0 High impedance

155 A(11) B15 I/O A_E 0 High impedance

156 A(8) B14 I/O A_E 0 High impedance

157 A(5) B13 I/O A_E 0 High impedance

158 A(1) B12 I/O A_E 0 High impedance

159 FLASH_CS_E — Controller— 0 —

160 FLASH_CS B11 I/O FLASH_CS_E 0 High impedance

161 CS2_E — Controller— 0 —

162 CS2 B10 I/O CS2_E 0 High impedance

163 EXINT B9 I — — —

164 SDWEN_E — Controller— 0 —

165 SDWEN B8 I/O SDWEN_E 0 High impedance

166 SDUDQM_E — Controller— 0 —

167 SDUDQ B7 I/O SDUDQM_E 0 High impedance

168 D(13) B6 I/O DH_E 0 50 kΩ pull-up

169 D(9) B5 I/O DH_E 0 50 kΩ pull-up

170 D(6) B4 I/O DL_E 0 50 kΩ pull-up

171 D(2) B3 I/O DL_E 0 50 kΩ pull-up

172 DSP_D(3) D3 I/O DSP_D_E 0 50 kΩ pull-up

173 DSP_D(7) E3 I/O DSP_D_E 0 50 kΩ pull-up

174 DSP_D(10) F3 I/O DSP_D_E 0 50 kΩ pull-up

175 DSP_D(14) G3 I/O DSP_D_E 0 50 kΩ pull-up

176 DSP_MCSN_E — Controller— 0 —

177 DSP_MCSN H3 I/O DSP_MCSN_E 0 High impedance

178 DSP_A(2) J3 I/O DSP_A_E 0 High impedance

179 DSP_A(6) K3 I/O DSP_A_E 0 High impedance

180 DSP_A(10) L3 I/O DSP_A_E 0 High impedance

181 T_REQA T3 I X — 50 kΩ pull-down

182 MDISDO_E — Controller— 0 —

183 MDISDO V3 I/O MDISDO_E 0 High impedance

184 K_ROW_E(3) — Controller— 0 —

185 K_ROW(3) V4 I/O K_ROW_E(3) 0 High impedance

186 K_COL(7) V5 I/O K_COL_E 0 50 kΩ pull-down

187 K_COL(4) V6 I/O K_COL_E 0 50 kΩ pull-down

188 K_COL(0) V7 I/O K_COL_E 0 50 kΩ pull-down

189 SPKRLED_E — Controller— 0 —

190 SPKRLED V8 I/O SPKRLED_E 0 High impedance

191 TMODE(2) V9 I X — 50 kΩ pull-up

192 TESTPT_E(18) — Controller— 0 —

193 TESTPT(18) V12 I/O TESTPT_E(18) 0 High impedance

194 TESTPT_E(14) — Controller— 0 —

195 TESTPT(14) V13 I/O TESTPT_E(14) 0 High impedance

196 TESTPT_E(10) — Controller— 0 —

197 TESTPT(10) V14 I/O TESTPT_E(10) 0 High impedance

198 TESTPT_E(6) — Controller— 0 —

199 TESTPT(6) V15 I/O TESTPT_E(6) 0 High impedance

200 TESTPT_E(3) — Controller— 0 —

201 TESTPT(3) V16 I/O TESTPT_E(3) 0 High impedance

202 OMUXSEL(0) V17 I X — 50 kΩ pull-up

203 LS100_OK_E(1) — Controller— 0 —

204 LS100_OK(1) K18 I/O LS100_OK_E(1) 0 High impedance

205 PPI_E(14) — Controller— 0 —

206 PPI(14) J18 I/O PPI_E(14) 0 High impedance

207 PPI_E(10) — Controller— 0 —

208 PPI(10) H18 I/O PPI_E(10) 0 High impedance

209 PPI_E(6) — Controller— 0 —

210 PPI(6) G18 I/O PPI_E(6) 0 High impedance

211 PPI_E(2) — Controller— 0 —

212 PPI(2) F18 I/O PPI_E(2) 0 High impedance

213 PRTPWR_E — Controller— 0 —

214 PRTPWR E18 I/O PRTPWR_E 0 High impedance

215 RX1 C18 I X — 50 kΩ pull-up

216 A(20) C17 I/O A_E 0 High impedance

217 A(16) C16 I/O A_E 0 High impedance

218 A(13) C15 I A_E 0 High impedance

219 A(9) C14 I/O A_E 0 High impedance

220 A(6) C13 I/O A_E 0 High impedance

221 A(2) C12 I/O A_E 0 High impedance

222 RDN_E — Controller— 0 —

223 RDN C11 I/O RDN_E 0 High impedance

224 CS3_E — Controller— 0 —

225 CS3 C10 I/O CS3_E 0 High impedance

226 EXINT2 C9 I — — —

227 SDRCK_E — Controller— 0 —

228 SDRCK C8 I/O SDRCK_E 0 High impedance

229 SDRCK2_E — Controller— 0 —

231 D(14) C7 I/O DH_E 0 50 kΩ pull-up

232 D(10) C6 I/O DH_E 0 50 kΩ pull-up

233 D(7) C5 I/O DL_E 0 50 kΩ pull-up

234 D(3) C4 I/O DL_E 0 50 kΩ pull-up

235 DSP_D(4) E4 I/O DSP_D_E 0 50 kΩ pull-up

236 DSP_D(11) G4 I/O DSP_D_E 0 50 kΩ pull-up

237 DSP_A(1) J4 I/O DSP_A_E 0 High impedance

238 DSP_INTN0_E — Controller— 0 —

239 DSP_INTN0 L4 I/O DSP_INTN0_E 0 High impedance

240 K_ROW_E(2) — Controller— 0 —

241 K_ROW(2) U5 I/O K_ROW_E(2) 0 High impedance

242 K_COL(3) U7 I/O K_COL_E 0 50 kΩ pull-down

243 TMODE(1) U9 I 0 — 50 kΩ pull-up

244 TESTPT_E(17) — Controller— 0 —

245 TESTPT(17) U12 I/O TESTPT_E(17) 0 High impedance

246 TESTPT_E(7) — Controller— 0 —

247 TESTPT(7) U13 I/O TESTPT_E(7) 0 High impedance

248 TESTPT_E(0) — Controller— 0 —

249 TESTPT(0) U16 I/O TESTPT_E(0) 0 High impedance

250 LS10_OK_E(0) — Controller— 0 —

251 LS10_OK(0) K17 I/O LS10_OK_E(0) 0 High impedance

252 PPI_E(13) — Controller— 0 —

253 PPI(13) J17 I/O PPI_E(13) 0 High impedance

254 PPI_E(3) — Controller— 0 —

255 PPI(3) H17 I/O PPI_E(3) 0 High impedance

256 A(19) D16 I/O A_E 0 High impedance

257 A(12) D14 I/O V 0 High impedance

258 A(3) D12 I/O A_E 0 High impedance

259 BE1N_E — Controller— 0 —

260 BE1N D11 I/O BE1N_E 0 High impedance

261 SDRASN_E — Controller— 0 —

262 SDRASN D9 I/O SDRASN_E 0 High impedance

263 D(11) D7 I/O DH_E 0 50 kΩ pull-up

264 D(4) D5 I/O DL_E 0 50 kΩ pull-up

19.1 Absolute Maximum Ratings

adversely affect device reliability.

19.2 Handling Precautions

thresholds are dependent on the circuit parameters used to define the model. The following table shows voltage ratings for CDM and HBM.

19.3 Crystal Specifications

19.3.1 System Clock Crystal

The T8302 requires an 11.52 MHz clock source (derived from an oscillator or a crystal) for the system clock source. If a crystal is used it must be connected between XT AL0 and XT AL1. The crystal specifications are shown below. Table 210. Absolute Maximum Ratings Table 211. System Clock (XTAL0, XTAL1) Specifications

19.4 PHY Clock Crystal

used, it must be connected between XLO and XHI. The crystal specifications are shown below.

19.5 Real-Time Clock Crystal

is used, it must be connected between XRTC0 and XRTC1. The crystal specifications are shown below. VDD = 3.3 V and Vss = 0.0 V unless otherwise specified. Table 212. PHY Clock (XLO, XHI) Crystal Specifications Table 213. Real-Time Clock (XRTC0, XRTC1) Specifications Table 214. Reset Pulse Table 215. dc Electrical Characteristics

19.7 Power Consumption

Table 216. Power Consumption gram instructions. System clock is 57.6 MHz. PHYs are in use. System clock is 57.6 MHz. Table 215. dc Electrical Characteristics (continued)

20 Change History

changes, the EQuB sections has been eliminated. been tabulated in the table below. Any references to tables, figures, sections, or pages have been highlighted in magenta. the reader back to the starting point. For example: clicking on the 1 below, will bring the reader to page 1, which is the first change of this document. Clicking on the back arrow (in Acrobat Reader) will bring the reader back to this page (page 245).

21 Contact Us

Table 217. Change History of DS01-213IPT

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Phone-On- A-Chip is a trademark of Agere Systems Inc. Copyright © 2001 Agere Systems Inc. All Rights Reserved Printed in U.S.A. July 2001 DS01-213IPT (Replaces DS00-338IPT and DA01-008IPT and must accompany A Y01-026IPT) For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, P A 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA P ACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao T ower, 88 Century Boulevard Pudong, Shanghai 200121 PRC Tel. (86) 21 50471212, FAX (86) 21 50472266 JAP AN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, T okyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: DA TALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), IT AL Y: (39) 02 6608131 (Milan), SP AIN: (34) 1 807 1441 (Madrid)