T8301

T8301 AGERE | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 190

Technical content

T8301 Internet Protocol Telephone Phone-On-A-Chip™ IP Solution DSP

1 Introduction

Lucent T echnologies’ Phone-On-A-Chip IP Solution is a highly integrated set of IC chips that form the basic building blocks for an internet protocol tele- phone (IPT), residing on a local area network (LAN). The IPT presently consists of two ICs—the T8301 (IPT_DSP) and the T8302 (IPT_ARM *). The T8301 provides the audio processing engine for voice compression and decompression, speaker- phone echo cancellation, digital-to-analog and ana- log-to-digital converters, low-pass filters, and amplifiers to drive standard business telephone handsets and speakerphone hardware. The general-purpose processor chip T8302 controls system I/O (Ethernet, USB, IrDA, etc.) and provides general telephone control features (LED control, key- pad button scanning, LCD module interface, etc.). A block diagram of the T8301 can be found in Figure 3 on page 8. Since the DSP1627 is an integral part of the T8301, we will refer to the DSP1627 Digital Signal Processor Data Sheet throughout this discussion.

1.1 Features

I DSP1627 core with bit manipulation unit. I DSP clock speeds up to 80 MHz. I Instruction ROM, 32K x 16 (zero wait-state at 80 MHz). * ARM is a registered trademark of Advanced RISC Machines Lim- ited. I Dual-port RAM, 6K x 16 (zero wait-state at 80 MHz). I Internal SRAM, 16K x 16 (single wait-state at 80 MHz). I 16-bit analog-to-digital converter. I Programmable gain amplifier on audio input. I Fixed gain differential microphone input. I Analog input SRAM buffer, 512 x 16. I Timed DMA for analog input SRAM. I T wo 16-bit digital-to-analog converters. I Independent simultaneous speaker and handset outputs. I T wo integrated differential speaker driver outputs. I T wo analog output SRAM buffers, 512 x 16 each. I T wo timed DMA outputs for simultaneous handset and speaker audio output. I Low-pass filtering on audio inputs and outputs. I Serial I/O interface. I General-purpose timer counter. I Bit I/O interface. I JTAG test and debugging control. I Implementation in 0.35 µm, 5 V silicon technology. I Packaged in 100-pin TQFP .

9 JTAG and Hardware

9.1 TMODE Control for JCS/Boundary-Scan

9.2 The Principle of Boundary-Scan

9.2.1 Boundary-Scan

Table 4. T8301 Instruction/Coefficient Table 6. Data Memory Area: I/O, Table 9. Tone Ringer Amplitude Table 12. Audio Codec Clock Table 15. DMA Starting Address Table 16. DMA Transfer Count Table 17. DMA Address Increment Table 18. DMA Transfer Decrement Register Table 30. Digital-to-Analog Converter Table 31. Analog-to-Digital Converter

2 Pin Information

2.1 T8301 100-Pin TQFP Pin Diagram

Figure 1. T8301 TQFP Pin Diagram

2 Pin Information (continued)

2.2 Pinout Information

to sections in the DSP1627 data sheet. Table 1. Pin Description

11 V DD —— —

17 V DD PLL OSC and PLL V DD ——

26 V DD —— —

36 V DD —— —

46 V DD —— —

56 V DD —— —

66 V DD —— —

68 STCK Serial test clock* — —

69 STO1 Serial test out 1* — —

70 STI1 Serial test in 1* — —

72 V SS GB — — —

76 GNDA — — —

• Leave open, this is for test purposes only.

Table 1. Pin Description (continued)

79 SV DD —— —

83 SV SS —— —

87 V SS GB — — —

88 V DD GB — — —

3 Overview

phone (IPT), residing on a local area network (LAN); see Figure 2. provide excellent support for execution of voice compression/decompression and echo cancellation algorithms. gral hardware development system support. The DSP1627 peripherals communicate with the DSP1627 core through the (D-IDB bus), which is 16 bits wide. essary, comments are made which reflect differences between the operation of the DSP1627 and the T8301. Please refer to the DSP1627 data sheet for further explanation. Figure 2. DSP/ARM Interface Block Diagram

12.288 MHz CLOCK

3 Overview (continued)

Figure 3. T8301 Block Diagram

2.5 Vp-p

4 DSP1600 Core

resources, please refer to the DSP1627 Digital Signal Processor Data Sheet. bination, these elements support a diverse instruction set for implementing users’ algorithms.

4.1 Bit Manipulation Unit (BMU)

4.2 Timer

frequencies. This timer provides flexibility in timing events.

4.3 Clock PLL Control

The DSP1627 powers up with the input clock (CKI1/CKI2 in the T8301 IC) as the source for the processor clock. thesizer will continue to run. filtering requirements on the clock synthesizer power and ground leads. Note: The 12,288 KHz is required as shown. Variations from this crystal frequency will cause detrimental effects to speech quality. Figure 4. Crystal Oscillator

4 DSP1600 Core (continued)

4.4 Bit Input/Output (BIO)

4.5 Serial Input/Output (SIO)

prise the T8301 SIO interface. IOCK is analogous to IOLD. Input clock 1 can be configured as an output, which would then drive IOCK and OCK1 .

4.6 Interrupts and Traps

data sheet for more information. The use of the two external DSP1627 core interrupts is shown in Table 3 and in Figure 2. Table 2. SIO Interface Signals IOLD* I/O Input/output load for SIO 1. IOCK I/O Input/output clock for SIO 1. SYNC I/O Sync for SIO 1 and 2.

concerning these registers and their usage.

4.8 External Memory Interface (EMI)

sor communication memories contained in the IPT_ARM integrated circuit. access 15 ns or faster off-chip resources when operating at 80 MHz.

4.9 T8301 Memory Mapping

map location. As a Harvard architecture, the device has two address/data buses; these are referred to as X and Y . mapped I/O. Memory is 16 bits wide. reset vector (0x0000). MAP1 has ROM at 0x0000, and MAP3 has RAM at 0x0000. The Y map is fixed. protocol must be instituted to allow the ARM to successfully load code into the DSP . Note: All X memory references are MAP 3. Table 3. DSP1627 INT0N and INT1N

12 Lucent Technologies Inc. Phone-On-A-Chip IP Solution DSP T8301 Internet Protocol Telephone Advance Data Sheet December 2000 I Dual-port (core) RAM, DPRAM—6K x 16: — This block is a true dual-port memory and is accessible simultaneously by both the X and Y bus system. T wo locations can be either read or written in the same instruction execution. This memory block resides at loca- tions 0x0000—0x17FF on both the X and Y maps. This block will operate with zero wait states. The DPRAM contains 6K x 16-bit words of zero wait-state memory, which is organized into six banks of 1K x 16-bit words. Each bank has separate ports to the instruction/coefficient and data memory spaces. Dual accesses to both memory spaces in separate banks incur no wait-states; however, accesses to the same bank from both spaces will add one wait-state to the total access time. I Internal SRAM, ISRAM—16K x 16: — Although this is a dual-port RAM, there is only one bus system to the RAM itself. The X and Y bus is multi- plexed before the RAM and is actually addressed via the external memory interface (EMI). T wo locations can be either read or written in the same instruction execution, but will require two clock cycles. The X memory location is at 0xC000—0xFFFF and the Y memory location is at 0x8000—0xBFFF , and also at 0xC000— 0xFFFF . (Referred to as mirrored. A write to 0x8000 on the Y map will also write to 0xC000). There is only one block of 16K; however, it appears twice on the Y map. There is one wait-state required for both the X and Y bus to access this RAM. I External SRAM, XSRAM—12K x 16: — Responds only to the Y data bus. The T8301 generates a chip select called X_CSN (active-low), pin 43. It uses the EMI to generate the address and data. There is one wait-state required for both the X and Y bus to access this RAM.

Table 4. T8301 Instruction/Coefficient Memory Map

Table 5. T8301 Memory-Mapped Peripherals

4.10 Y Space Memory Map

R2, and R3 registers, and also by direct (Y -based) addressing. Table 6. Data Memory Area: I/O, Register, and Memory

RAM (in the T8302 IPT_ARM chip). RAM (in the T8302 IPT_ARM chip). Table 6. Data Memory Area: I/O, Register, and Memory (continued)

5 Audio Input/Output Circuitry

The discussions in this section pertain to circuitry that is outside of the dotted outline in Figure 3 on page 8.

5.1 Analog Audio Input Channels

audio codec block to be digitized. Each of the input signals AINAN , AINCP, and AINCN are ac-coupled to their T8301 inputs by a 0.2 µF capacitor. a larger signal than 2.5 Vp-p, the audio codec will saturate and clip the input waveform. phone input is not supported for PGA settings of 0 dB and 3 dB.

5.2 Programmable Gain Amplifier (PGA)

Table 7. Programmable Gain Amplifier Maximum

5 Audio Input/Output Circuitry (continued)

5.3 Analog Audio Output Channels

ringer output into its audio path. two digital input streams to analog signals. signal. The signals should be biased such that, when power is re-enabled, no audible noises occur. exhibit a flattening or clipping characteristic at the output. SPKDRV1B and SPKDRV2A , SPKDRV2B ) are direct coupled to 45 Ω speakers.

5.4 Tone Ringer

ing tone output is added to the current analog speaker signal and output through the differential speaker driver. Custom tones may be generated by modifying the T8301 firmware. Table 8. Tone Ringer Control Register (trc_reg) 12 TR_EN T one ringer output enable. If 1, the tone ringer’s output is added into the speaker output path. If 0, the tone ringer’s output is disconnected from the speaker output path. 11:8 TR_AC[3:0] T one ringer amplitude control, see T able 9.

Table 9. Tone Ringer Amplitude Control Encoding Table 10. Tone Ringer Frequency Encoding

5.5 Audio Codec Block

Figure 5. Audio Codec Block Diagram Table 10. Tone Ringer Frequency Encoding (continued)

1 Mbit/s 64 kS/s 16 kS/s 8 kS/s

1 Mbit/s 16 kS/s 8 kS/s

Lucent Technologies Inc. 21 Advance Data Sheet December 2000 Phone-On-A-Chip IP Solution DSP T8301 Internet Protocol Telephone

5.6 Audio Codec Control Registers

The analog audio input and output control register (aioc_reg) is used to select the active and enabled inputs and outputs. Through this register the input and output channels can also have the clocks shut down to conserve power. Table 11. aioc_reg Analog Audio I/O Control

Description

15 MPWRD 1 Main powerdown. If 1, powerdown. If 0, powerup. 14 SPKFB 0* Speaker #1 output filter bypass. If 1, the transmit LPF is bypassed in the speaker path; set the correspond- ing DMA clock to 16 kHz. If 0, the transmit LPF is enabled in the speaker path. Note: The SOC bits in the audio codec clock control register should also be modified. 13 HNDFB 0* Handset output filter bypass. If 1, the transmit LPF is bypassed in the handset path; set the correspond- ing DMA clock to 16 kHz. If 0, the transmit LPF is enabled in the handset path. Note: The HOC bits in the audio codec clock control register should also be modified. 12 AINFB 0* Analog input filter bypass. If 1, the receive BPF is bypassed in the audio input path; set the corre- sponding DMA clock to 16 kHz. If 0, the receive BPF is enabled in the audio input path. Note: The AINC bits in the audio codec clock control register should also be modified. 11 SPK2EN 0 Enables speaker #2 output channel. If 1, the speaker’s output driver is enabled. If 0, the output driver for the speaker output channel is disabled. 10 OLE 0 Output limit enable. When set, this bit causes the nominal full-scale output for the analog outputs to be limited to approximately half the normal value of 2.5 Vp-p Setting this bit has no effect on the receive gain. 9:7 RSVD Reserved. * If the BPF is bypassed, output from the decimator must be shifted right by 2 bits (6 dB attenuation) to avoid saturation going into the com- pander. Similarly, if the LPF is bypassed in the speaker or handset path, input into the interpolator must be shifted left by 2 bits.

22 Lucent Technologies Inc. Phone-On-A-Chip IP Solution DSP T8301 Internet Protocol Telephone Advance Data Sheet December 2000 Table 11. aioc_reg Analog Audio I/O Control (continued) 6:4 PGAS[2:0] 000 PGA gain select. Selects the gain for the programmable gain amplifier. See T able 7 on page 17 for an explanation of the coding. 3 SPKEN 0 Enables the speaker output channel. If 1, the speaker’s output driver is enabled. If 0, the output driver for the speaker output channel is disabled. 2 AOUT AEN 0 Enables the handset output channel. If 1, the handset output driver is enabled. If 0, the output driver for the handset output channel is disabled. 1:0 AINSS 00 Analog input source select. If 11, reserved. If 10, analog input source is from the microphone (AINCN, AINCP ). If 01, analog input source is from the handset (AINAN ). If 00, mute (default after reset or powerup). Table 12. Audio Codec Clock Control Register (aclkc_reg) 8:6 SOC(2:0) Please refer to T able 13 for bit field description. 5:3 HOC(2:0) Please refer to T able 13 for bit field description. 2:0 AINC(2:0) Please refer to T able 13 for bit field description. Table 13. Audio Clock Encoding 000 0 Hz. The clock for the channel is stopped. 001 8 kHz clock is used for all audio codes except G.722. 010 16 kHz clock is used for G.722 (must bypass filters). 111 Supplies 1 MHz clock to DMA. Reserved for testing only.

Lucent Technologies Inc. 23 Advance Data Sheet December 2000 T8301 Internet Protocol Telephone Phone-On-A-Chip IP Solution DSP

6 DMA Input/Output Channels

The discussions in this section pertain to circuitry that is outside of the dotted outline in Figure 3 on page 8. There are three timed DMA transfer blocks, each of which transfers data to/from the audio codec block from/to a 512 x 16-bit SRAM. These SRAMs are two-port devices. One port is connected to the DSP1627 address and data bus, and the other is accessed by the DMA controller. These memories transfer data to/from the audio codec block or AOUTA , AIN, and SOUT . These DMA blocks are capable of transferring a 16-bit word to/from the device’s A/D or D/A at the following rates, which are set up by programming the audio codec clock control register: I 8 kHz I 16 kHz Each channel initiates a transfer between the audio codec block and its respective SRAM on the rising edge of the selected transfer clock.

6.1 DMA Operation

The T8301 has three timed DMA transfer channels. The DSP sets up a DMA channel by writing a starting address and a transfer count into the setadr_reg (see T able 15) and setcnt_reg (see T able 16). The DSP then sets the channel’s GO bit in the dmac_reg (see T able 14). When the DMA finishes its current transfer operation, indicated by the BSY bit in the dmac_reg going low, the DMA will transfer the contents of the setadr_reg (see Table 15) to the adrinc_reg (see T able 17) and the cntdec_reg (see T able 18) respectively. The GO bit will be reset to zero and the BSY bit will be set to one, in the dmac_reg on completion of this transfer. When the rising edge of the transfer clock is detected, the DMA controller will transfer a single word to/from memory and the audio codec block. The DMA channel will then increment its address pointer adrinc_reg and decrement its counter cntdec_reg. At the completion of the number of transfers written into the transfer counter (cntdec_reg = 0), the DMA block will set its ION bit in the dmac_reg to 1 and reset its BSY bit to zero. If its IEN bit is set, an interrupt to the DSP will occur. If the DSP has set the GO bit which indicates that it has set up a new transfer or if the DSP responds (sets up a new transfer count and re-enables transfers) before the next rising edge of the transfer clock, data can be continuously transferred at the clocked rate. If the DSP is reading or writing to the memory that a timed DMA is transferring to/from, the DMA can be delayed by a clock cycle to allow the DSP to finish its access.

6.2 DMA Registers

Each DMA channel has the following four registers: I Starting address register I T ransfer count register I Working address increment register (read only) I Working count decrement register (read only) In addition, there is a control and status register that supports all three DMA channels.

6 DMA Input/Output Channels (continued)

Table 14. DMA Control Register dmac_reg 14 IENSPK Interrupt enable speaker output channel. 13 IENHND Interrupt enable handset output channel. 12 IENAIN Interrupt enable analog input channel. cleared by a read operation. cleared by a read operation. cleared by a read operation. 6 SPKBSY Speaker DMA channel busy (read only). 5 HNDBSY Handset DMA channel busy (read only). 4 AINBSY Analog input DMA channel busy (read only). count of zero is reached by the DMA transfer counter. count of zero is reached by the DMA transfer counter. count of zero is reached by the DMA transfer counter. Table 15. DMA Starting Address Register setadr_reg Table 16. DMA Transfer Count Register setcnt_reg

Table 17. DMA Address Increment Register adrinc_reg Table 18. DMA Transfer Decrement Register cntdec_reg

7 Hardware Compander

The discussions in this section pertain to circuitry that is outside of the dotted outline in Figure 3 on page 8. DSP from performing the functions in firmware. The compander supports both µ-law and A-law operations. companded to linear is done by write_companded then read_linear. Table 19. config_compander Register Table 20. write_linear Register Table 21. write_companded Register Table 22. read_linear Register Table 23. read_companded Register

7 Hardware Compander (continued)

Figure 6. Hardware Compander Block Diagram register defaults to µ-law, see Table 19 on page 26.

8 Electrical Specifications

8.1 Operating Range Specifications

8.2 Analog and Codec Specifications

• Parameter supplied for reference purposes.
• Parameter supplied for reference purposes.

Table 24. Operating Range Specifications Table 25. AINAN Specifications Table 26. AINCP , AINCN Specifications Table 27. AOUTA Specifications

8 Electrical Specifications (continued)

8.3 Crystal Specification

See the DSP1627 Digital Signal Processor Data Sheet for further information. Table 28. Speaker#1, Speaker#2 Specifications Table 29. Digital Low-Pass Filters Specifications Table 30. Digital-to-Analog Converter Specifications Table 31. Analog-to-Digital Converter Specifications

30 Lucent Technologies Inc. Phone-On-A-Chip IP Solution DSP T8301 Internet Protocol Telephone Advance Data Sheet December 2000

9 JTAG and Hardware Development System (HDS)

The JTAG block contains logic for implementing the JTAG/IEEE* P1149.1 standard. A four-signal test port provides a mechanism for accessing the DSP1627 core from remote test equipment or a remote hardware development system. The on-chip HDS performs instruction breakpointing and branch tracing at full speed. Using the JT AG port, the breakpointing is set up and the trace history is read back.

9.1 TMODE Control for JCS/Boundary-Scan Operation

TMODEN0, TMODEN1, and TMODEN2 are inputs used to determine test mode operation. Of the eight possible combinations, modes 6 and 7 are significant during the development and production phases.

9.1.1 Mode 7 Operation (TMODE = 7)

This is the production mode. Internal pull-up resistors (approximately 50 kΩ ) will provide the logic level required. The three pins can be left floating (no external resistors are required). In this mode, boundary-scan is active. The CK8KHz (pin 67), the CK2MHz (pin 98), and the CKO (pin 99) are all dormant (high).

9.1.2 Mode 6 Operation (TMODE = 6)

The JCS tools (JTAG communications system) are used in this mode. TMODEN0 must be pulled low externally, TMODEN1, and TMODEN2 can both be left floating to enter this mode. The CK8KHz (pin 67), the CK2MHz (pin 98), and the CKO (pin 99) are active. Should the user require access to any or all of the three clocks in production and still require boundary-scan capa- bilities for production test, a strong (external) pull-down resistor would be required on TMODEN0 (1 kΩ ). The pro- duction test must be able to pull TMODEN0 high to allow access to the boundary-scan test. After the test is complete, the pin would normally be low (TMODE 6) allowing the clocks to be active.

9.2 The Principle of Boundary-Scan Architecture

Each primary input signal and primary output signal is supplemented with a multipurpose memory element called a boundary-scan cell. Cells on device primary inputs are referred to as input cells and cells on primary outputs are referred to as output cells. Input and output is relative to the core logic of the device. At any time, only one register can be connected from TDI to TDO, e.g., the instruction register (IR), BYP ASS, boundary-scan, IDENT , or even some appropriate register internal to the core logic; see Figure 7. The selected register is identified by the decoded output of the instruction register. Certain instructions are mandatory, such as EXTEST (boundary-scan register selected), whereas others are optional, such as the IDCODE instruction (IDENT register selected). * IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.

9 JTAG and Hardware Development System (HDS) (continued)

Figure 7. Boundary-Scan Architecture boundary-scan register (boundary-scan). I A finite-state machine T AP controller with inputs TCK and TMS. I An n-bit (n = 4) instruction register (IR), holding the current instruction. I A 1-bit bypass register (BYP ASS).

pins. The pin definitions are as follows. Debug mode, or boundary-scan mode is selected via the TMODE pins as shown below.

9.2.1 Boundary-Scan Instruction Register

The boundary-scan instruction register is 4 bits long and the capture value is 0001. Table 32. Boundary-Scan Pin Functions

94 TDO (bscan) TDO (debug) —

95 TCK (bscan) TCK (debug) Pulled high internally

96 TMS (bscan) TMS (debug) Pulled high internally

97 TDI (bscan) TDI (debug) —

89 TRSTN (bscan) TRSTN (debug) Pulled high internally

Table 33. Debug Mode

90 TMODEN0 If 7 = boundary-scan

91 TMODEN1 Pulled high internally

92 TMODEN2 Pulled high internally

Table 34. Boundary-Scan Instruction Register EXTEST 0000 Places the boundary-scan register in EXTEST mode. SAMPLE 0001 Places the boundary-scan register in sample mode. IDCODE 0101 Identification code. BYP ASS 1111 Places the bypass register in the scan chain.

Table 35. Boundary-Scan Register Description

0 BIO_E(0) — Controller — — —

1 BIO(0) 2 I/O BIO_E(0) 0 High Impedance

2 BIO_E(1) — Controller — — —

3 BIO(1) 3 I/O BIO_E(1) 0 High Impedance

4 BIO_E(2) — Controller — — —

5 BIO(2) 4 I/O BIO_E(2) 0 High Impedance

6 BIO_E(3) — Controller — — —

7 BIO(3) 5 I/O BIO_E(3) 0 High Impedance

8 INT0N 6 Input — — —

9 INT1N 7 Input — — —

10 STOPN 8 Input — — —

11 DI1 9 Input — — —

12 DO1_E — Controller — — —

13 DO1 12 I/O DO1_E 0 High Impedance

14 SYNC_E — Controller — — —

15 SYNC 13 I/O SYNC_E 0 High Impedance

16 IOLD_E — Controller — — —

17 IOLD 14 I/O IOLD_E 0 High Impedance

18 IOCK_E — Controller — — —

19 IOCK 15 I/O IOCK_E 0 High Impedance

21 A(15) 21 I/O A_E 0 High Impedance

22 A(14) 22 I/O A_E 0 High Impedance

23 A(13) 23 I/O A_E 0 High Impedance

24 A(12) 24 I/O A_E 0 High Impedance

25 A(11) 27 I/O A_E 0 High Impedance

26 A(10) 28 I/O A_E 0 High Impedance

27 A(9) 29 I/O A_E 0 High Impedance

28 A(8) 30 I/O A_E 0 High Impedance

29 A(7) 31 I/O A_E 0 High Impedance

30 A(6) 32 I/O A_E 0 High Impedance

31 A(5) 33 I/O A_E 0 High Impedance

32 A(4) 34 I/O A_E 0 High Impedance

33 A(3) 37 I/O A_E 0 High Impedance

34 A(2) 38 I/O A_E 0 High Impedance

35 A(1) 39 I/O A_E 0 High Impedance

36 A(0) 40 I/O A_E 0 High Impedance

37 I_CSN 41 I/O A_E 0 High Impedance

38 M_CSN 42 I/O A_E 0 High Impedance

39 X_CSN 43 I/O A_E 0 High Impedance

40 RWN 44 I/O A_E 0 High Impedance

41 D_E — Controller — — —

42 D(15) 47 I/O D_E 0 High Impedance

43 D(14) 48 I/O D_E 0 High Impedance

44 D(13) 49 I/O D_E 0 High Impedance

45 D(12) 50 I/O D_E 0 High Impedance

46 D(11) 51 I/O D_E 0 High Impedance

47 D(10) 52 I/O D_E 0 High Impedance

48 D(9) 53 I/O D_E 0 High Impedance

49 D(8) 54 I/O D_E 0 High Impedance

50 D(7) 57 I/O D_E 0 High Impedance

51 D(6) 58 I/O D_E 0 High Impedance

52 D(5) 59 I/O D_E 0 High Impedance

53 D(4) 60 I/O D_E 0 High Impedance

54 D(3) 61 I/O D_E 0 High Impedance

55 D(2) 62 I/O D_E 0 High Impedance

56 D(1) 63 I/O D_E 0 High Impedance

57 D(0) 64 I/O D_E 0 High Impedance

58 CLK_E — Controller — — —

59 CK8KHZ 67 I/O CLK_E 0 High Impedance

60 STCK_E — Controller — — —

61 STCK 68 I/O STCK_E 0 High Impedance

62 STI_E — Controller — — —

63 STI1 70 I/O STI_E 0 High Impedance

64 STO_E — Controller — — —

65 STO1 69 I/O STO_E 0 High Impedance

66 RESETN_E — Controller — — —

67 RESETN 93 I/O RESETN_E 0 High Impedance

68 CK2MHZ 98 I/O CLK_E 0 High Impedance

69 CKO 99 I/O CLK_E 0 High Impedance

Table 35. Boundary-Scan Register Description (continued)

Lucent Technologies Inc. 35 Advance Data Sheet December 2000 T8301 Internet Protocol Telephone Phone-On-A-Chip IP Solution DSP Notes

Lucent T echnologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Phone-On-A-Chip is a trademark of Lucent T echnologies Inc. Copyright © 2000 Lucent Technologies Inc. All Rights Reserved Printed in U.S.A. December 2000 DS01-025IPT (Replaces DS00-030IPT -3) For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent T echnologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, P A 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA P ACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent T echnologies (China) Co., Ltd., A-F2, 23/F , Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P . R. China Tel. (86) 21 6440 0468, ext. 325, FAX (86) 21 6440 0652 JAP AN: Microelectronics Group, Lucent T echnologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, T okyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DA T ALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 T echnical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), IT AL Y: (39) 02 6608131 (Milan), SP AIN: (34) 1 807 1441 (Madrid)

DSP1627 Digital Signal Processor

1 Features

■ Optimized for digital cellular applications with a bit manip- ulation unit for higher coding efficiency. ■ On-chip, programmable, PLL clock synthesizer. ■ 14 ns and 11 ns instruction cycle times at 5 V, 10 ns in- struction cycle time at 3.0 V, and 20 ns and 12.5 ns in- struction cycle times at 2.7 V, respectively. ■ Mask-programmable memory map option: The DSP1627x36 features 36 Kwords on-chip ROM. The DSP1627x32 features 32 Kwords on-chip ROM and ac- cess to 16 Kwords external ROM in the same map. Both feature 6 Kwords on-chip, dual-port RAM and a secure option for on-chip ROM. ■ Low power consumption: — <5.5 mW/MIPS typical at 5 V. — <1.5 mW/MIPS typical at 2.7 V. ■ Flexible power management modes: — Standard sleep: 0.5 mW/MIPS at 5 V. 0.12 mW/MIPS at 2.7 V. — Sleep with slow internal clock: 1.4 mW at 5 V. 0.4 mW at 2.7 V. — Hardware STOP (pin halts DSP): <20 µA. ■ Mask-programmable clock options: crystal oscillator, small signal, and CMOS. ■ Low-profile TQFP package (1.5 mm) available. ■ Sequenced accesses to X and Y external memory. ■ Object code compatible with the DSP1617. ■ Single-cycle squaring. ■ 16 x 16-bit multiplication and 36-bit accumulation in one instruction cycle. ■ Instruction cache for high-speed, program-efficient, zero- overhead looping. ■ Dual 25 Mbits/s serial I/O ports with multiprocessor capa- bility—16-bit data channel, 8-bit protocol channel. ■ 8-bit parallel host interface: — Supports 8- or 16-bit transfers. — Motorola* or Intel † compatible. ■ 8-bit control I/O interface. ■ 256 memory-mapped I/O ports. ■ IEEE‡ P1149.1 test port (JTAG boundary scan). ■ Full-speed in-circuit emulation hardware development system on-chip. ■ Supported by DSP1627 software and hardware develop- ment tools.

2 Description

The DSP1627 is Lucent Technologies Microelectronics Group first digital signal processor offering 100 MIPS oper- ation at 3.0 V and 80 MIPS operation at 2.7 V with a reduc- tion in power consumption. Designed specifically for applications requiring low power dissipation in digital cellu- lar systems, the DSP1627 is a signal-coding device that can be programmed to perform a wide variety of fixed-point sig- nal processing functions. The device is based on the DSP1600 core with a bit manipulation unit for enhanced sig- nal coding efficiency. The DSP1627 includes a mix of pe- ripherals specifically intended to support processing- intensive but cost-sensitive applications in the area of digital wireless communications. The DSP1627x36 contains 36 Kwords of internal ROM (IROM), but it doesn’t support the use of IROM and external ROM (EROM) in the same memory map. The DSP1627x32 supports the use of 32 Kwords of IROM with 16 Kwords of EROM in the same map. Both devices contain 6 Kwords of dual-port RAM (DPRAM), which allows simultaneous ac- cess to two RAM locations in a single instruction cycle. The DSP1627 is object code compatible with the DSP1617, while providing more memory and architectural enhance- ments including an on-chip clock synthesizer and an 8-bit parallel host interface for hardware flexibility. The DSP1627 supports 2.7 V, 3.0 V, and 5 V operation and flexible power management modes required for portable cellular terminals. Several control mechanisms achieve low- power operation, including a STOP pin for placing the DSP into a fully static, halted state and a programmable power control register used to power down unused on-chip I/O units. These power management modes allow for trade-offs between power reduction and wake-up latency require- ments. During system standby, power consumption is re- duced to less than 20 µA. The on-chip clock synthesizer can be driven by an external clock whose frequency is a fraction of the instruction rate. The device is packaged in a 100-pin BQFP or a 100-pin TQFP and is available with 14 ns and 11 ns instruction cycle times at 5 V, 10 ns instruction cycle times at 3.0 V, and 20 ns and 12.5 ns instruction cycle times at 2.7 V, respec- tively. * Motorola is a registered trademark of Motorola, Inc. † Intel is a registered trademark of Intel Corp. ‡ IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.

DSP1627 Digital Signal Processor March 2000 2 Lucent Technologies Inc. Table of Contents Contents Page Contents Page 4.2 DSP1600 Core Architectural Overview .. 10

6.4 Parallel Host Interface or Serial

Interface #2 and Control I/O Interface .... 65 9 Electrical Characteristics and Requirements .... 70

13 Crystal Electrical Characteristics and

13.1 External Components for the Crystal

13.3 LC Network Design for Third

14.1 100-Pin BQFP (Bumpered Quad 14.2 100-Pin TQFP (Thin Quad Flat Pack)... 153

3 Pin Information

Figure 1. DSP1627 BQFP Pin Diagram

3 Pin Information (continued)

Figure 2. DSP1627 TQFP Pin Diagram

all I and I/O type pins are designed to remain at full CMOS levels when not driven by the DSP.

• 3-states when RSTB = 0, or by JTAG control.

† 3-states when RSTB = 0 and INT0 = 1. Output = 1 when RSTB = 0 and INT0 = 0, except CKO which is free-running. ** See Section 7, Mask-Programmable Options. †† For SIO multiprocessor applications, add 5 kΩ external pull-up resistors to SADD1 and/or SADD2 for proper initialization. Table 1. Pin Descriptions DB[15:0] I/O* External Memory Data Bus DB[15:0]. † Data Address 0x4000 to 0x40FF I/O Enable. 21 8 ERAMHI O † Data Address 0x8000 to 0xFFFF External RAM Enable. 23 10 ERAMLO O † Data Address 0x4100 to 0x7FFF External RAM Enable. 24 11 EROM O † Program Address External ROM Enable. 25 12 RWN O † Read/Write Not. 27 14 EXM I External ROM Enable. AB[15:0] O* External Memory Address Bus 15—0. 47 34 INT1 I Vectored Interrupt 1. 48 35 INT0 I Vectored Interrupt 0. 50 37 IACK O* Interrupt Acknowledge. 51 38 STOP I STOP Input Clock. 52 39 TRAP I/O* Nonmaskable Program Trap/Breakpoint Indication. 56 43 TCK I JTAG Text Clock. 57 44 TMS I‡ JTAG Test Mode Select. 58 45 TDO O § JTAG Test Data Output. 59 46 TDI I‡ JTAG Test Data Input. 65 52 VEC0/IOBIT7 I/O* Vectored Interrupt Indication 0/Status/Control Bit 7. 66 53 VEC1/IOBIT6 I/O* Vectored Interrupt Indication 1/Status/Control Bit 6. 67 54 VEC2/IOBIT5 I/O* Vectored Interrupt Indication 2/Status/Control Bit 5. 68 55 VEC3/IOBIT4 I/O* Vectored Interrupt Indication 3/Status/Control Bit 4.

Functional descriptions of pins 1—100 are found in Section 6, Signal Descriptions.

• 3-states when RSTB = 0, or by JTAG control.

† 3-states when RSTB = 0 and INT0 = 1. Output = 1 when RSTB = 0 and INT0 = 0. ** See Section 7, Mask-Programmable Options. †† For SIO multiprocessor applications, add 5 kΩ external pull-up resistors to SADD1 and/or SADD2 for proper initialization. Table 1. Pin Descriptions (continued) 69 56 IOBIT3/PB7 I/O* Status/Control Bit 3/PHIF Data Bus Bit 7. 70 57 IOBIT2/PB6 I/O* Status/Control Bit 2/PHIF Data Bus Bit 6. 71 58 IOBIT1/PB5 I/O* Status/Control Bit 1/PHIF Data Bus Bit 5. 72 59 IOBIT0/PB4 I/O* Status/Control Bit 0/PHIF Data Bus Bit 4. †† I/O* SIO2 Multiprocessor Address/PHIF Data Bus Bit 3. 75 62 DOEN2/PB2 I/O* SIO2 Data Output Enable/PHIF Data Bus Bit 2. 77 64 DI2/PB1 I/O* SIO2 Data Input/PHIF Data Bus Bit 1. 78 65 ICK2/PB0 I/O* SIO2 Input Clock/PHIF Data Bus Bit 0. 79 66 OBE2/POBE O* SIO2 Output Buffer Empty/PHIF Output Buffer Empty. 80 67 IBF2/PIBF O* SIO2 Input Buffer Full/PHIF Input Buffer Full. 81 68 OLD2/PODS I/O* SIO2 Output Load/PHIF Output Data Strobe. 82 69 ILD2/PIDS I/O* SIO2 Input Load/PHIF Input Data Strobe. 83 70 SYNC2/PBSEL I/O* SIO2 Multiprocessor Synchronization/PHIF Byte Select. 84 71 DO2/PST A T I/O* SIO2 Data Output/PHIF Status Register Select. 85 72 OCK2/PCSN I/O* SIO2 Output Clock/PHIF Chip Select Not. 86 73 DOEN1 I/O* SIO1 Data Output Enable. †† I/O* SIO1 Multiprocessor Address. 90 77 SYNC1 I/O* SIO1 Multiprocessor Synchronization. 91 78 DO1 O* SIO1 Data Output. 92 79 OLD1 I/O* SIO1 Output Load. 93 80 OCK1 I/O* SIO1 Output Clock. 94 81 ICK1 I/O* SIO1 Input Clock. 95 82 ILD1 I/O* SIO1 Input Load. 96 83 DI1 I SIO1 Data Input. 98 85 IBF1 O* SIO1 Input Buffer Full. 99 86 OBE1 O* SIO1 Output Buffer Empty. 60 47 V DDA P Analog Power Supply. 63 50 V SSA P Analog Ground.

March 2000 DSP1627 Digital Signal Processor Lucent Technologies Inc. 7

4 Hardware Architecture

The DSP1627 device is a 16-bit, fixed-point program- mable digital signal processor (DSP). The DSP1627 consists of a DSP1600 core to gether with on-chip mem- ory and peripherals. Added architectural features give the DSP1627 high program efficiency for signal coding applications.

4.1 DSP1627 Architectural Overview

Figure 3 shows a block diagram of the DSP1627. The fol- lowing modules make up the DSP1627. DSP1600 Core The DSP1600 core is the heart of the DSP1627 chip. The core contains data and address arithmetic units, and control for on-chip memory and peripherals. The core provides support for external memory wait-states and on- chip, dual-port RAM and features vectored interrupts and a trap mechanism. Dual-Port RAM (DPRAM) This module contains six banks of zero wait-state mem- ory. Each bank consists of 1K 16-bit words and has sep- arate address and data ports to the instruction/coefficient and data memory spaces. A program can reference memory from either space. The DSP1600 core automat- ically performs the required multiplexing. If references to both ports of a single bank are made simultaneously, the DSP1600 core automatically inserts a wait-state and per- forms the data port access first, followed by the instruc- tion/coefficient port access. A program can be downloaded from slow, off-chip mem- ory into DPRAM, and then executed without wait-states. DPRAM is also useful for improving convolution perfor- mance in cases where the coefficients are adaptive. Since DPRAM can be downloaded through the JTAG port, full-speed remote in-circuit emulation is possible. DPRAM can also be used for downloading self-test code via the JTAG port. Read-Only Memory (ROM) The DSP1627x36 contains 36K 16-bit words of zero wait-state mask-programmable ROM for program and fixed coefficients. Similarly, the DSP1627x32 has 32K 16-bit words of ROM and access to 16 Kwords of exter- nal ROM. External Memory Multiplexer (EMUX) The EMUX is used to connect the DSP1627 to external memory and I/O devices. It supports read/write opera- tions from/to instruction/coefficient memory (X memory space) and data memory (Y memory space). The DSP1600 core automatically controls the EMUX. Instruc- tions can transparently reference external memory from either set of internal buses. A sequencer allows a single instruction to access both the X and the Y external mem- ory spaces. Clock Synthesis The DSP powers up with a 1X input clock (CKI/CKI2) as the source for the processor clock. An on-chip clock syn- thesizer (PLL) can also be used to generate the system clock for the DSP, which will run at a frequency multiple of the input clock. The clock synthesizer is deselected and powered down on reset. For low-power operation, an internally generated slow clock can be used to drive the DSP. If both the clock synthesizer and the internally gen- erated slow clock are selected, the slow clock will drive the DSP; however, the synthesizer will continue to run. The clock synthesizer and other programmable clock sources are discussed in Section 4.12. The use of these programmable clock sources for power management is discussed in Section 4.13. Bit Manipulation Unit (BMU) The BMU extends the DSP1600 core instruction set to provide more efficient bit operations on accumulators. The BMU contains logic for barrel shifting, normalization, and bit field insertion/extraction. The unit also contains a set of 36-bit alternate accumulators. The data in the al- ternate accumulators can be shuffled with the data in the main accumulators. Flags returned by the BMU mesh seamlessly with the DSP1600 conditional instructions. Bit Input/Output (BIO) The BIO provides convenient and efficient monitoring and control of eight individually configurable pins. When configured as outputs, the pins can be individually set, cleared, or toggled. When configured as inputs, individu- al pins or combinations of pins can be tested for patterns. Flags returned by the BIO mesh seamlessly with condi- tional instructions. Serial Input/Output Units (SIO and SIO2) SIO and SIO2 offer asynchronous, full-duplex, double- buffered channels that operate at up to 25 Mbits/s (for 20 ns instruction cycle in a nonmultiprocessor configura- tion), and easily interface with other Lucent Technologies fixed-point DSPs in a multiple-processor environment. Commercially available codecs and time-division multi- plex (TDM) channels can be interfaced to the serial I/O ports with few, if any, additional components. SIO2 is identical to SIO. An 8-bit serial protocol channel may be transmitted in ad- dition to the address of the called processor in multipro- cessor mode. This feature is useful for transmitting high- level framing information or for error detection and cor- rection. SIO2 and BIO are pin-multiplexed with the PHIF.

4 Hardware Architecture (continued)

• These registers are accessible through the pins only.

Figure 3. DSP1627 Block Diagram

Table 2. DSP1627 Block Diagram Legend aa<0—1> Alternate Accumulators. ar<0—3> Auxiliary BMU Registers. BREAKPOINT Four Instruction Breakpoint Registers. BYP ASS JTAG Bypass Register. cbit Control Register for BIO. EMUX External Memory Multiplexer. HDS Hardware Development System. ID JTAG Device Identification Register. ioc I/O Configuration Register. JCON JTAG Configuration Registers. jtag 16-bit Serial/Parallel Register. pdx0(in) Parallel Data Transmit Input Register 0. pdx0(out) Parallel Data Transmit Output Register 0. PHIF Parallel Host Interface. phifc Parallel Host Interface Control Register. pllc Phase-Locked Loop Control Register. powerc Power Control Register. PST A T Parallel Host Interface Status Register. ROM Internal ROM (36 Kwords for DSP1627x36, 32 Kwords for DSP1627x32). saddx Multiprocessor Protocol Register. saddx2 Multiprocessor Protocol Register for SIO2. sbit Status Register for BIO. sdx(in) Serial Data Transmit Input Register. sdx2(in) Serial Data Transmit Input Register for SIO2. sdx(out) Serial Data Transmit Output Register. sdx2(out) Serial Data Transmit Output Register for SIO2. SIO Serial Input/Output Unit. SIO2 Serial Input/Output Unit #2. sioc Serial I/O Control Register. sioc2 Serial I/O Control Register for SIO2. srta Serial Receive/Transmit Address Register. srta2 Serial Receive/Transmit Address Register for SIO2. tdms Serial I/O Time-division Multiplex Signal Control Register. tdms2 Serial I/O Time-division Multiplex Signal Control Register for SIO2. timer0 Timer Running Count Register. timerc Timer Control Register. TRACE Program Discontinuity Trace Buffer. XAB Program Memory Address Bus. XDB Program Memory Data Bus. YAB Data Memory Address Bus.

DSP1627 Digital Signal Processor March 2000 10 Lucent Technologies Inc. Parallel Host Interface (PHIF) The PHIF is a passive, 8-bit parallel port which can in- terface to an 8-bit bus containing other Lucent Technol- ogies DSPs (e.g., DSP1620, DSP1627, DSP1628, DSP1629, DSP1611, DSP1616, DSP1617, DSP1618), microprocessors, or peripheral I/O devices. The PHIF port supports either Motorola or Intel protocols, as well as 8-bit or 16-bit transfers, configured in software. The port data rate depends upon the instruction cycle rate. A 25 ns instruction cycle allows the PHIF to support data rates up to 11.85 Mbytes/s, assuming the external host device can transfer 1 byte of data in 25 ns. The PHIF is accessed in two basic modes: 8-bit or 16-bit mode. In 16-bit mode, the host determines an ac- cess of the high or low byte. In 8-bit mode, only the low byte is accessed. Software-programmable features al- low for a glueless host interface to microprocessors (see Section 4.8, Parallel Host Interface). Timer The timer can be used to provide an interrupt at the ex- piration of a programmed interval. The interrupt may be single or repetitive. More than nine orders of magnitude of interval selection are provided. The timer may be stopped and restarted at any time. Hardware Development System (HDS) Module The on-chip HDS performs instruction breakpointing and branch tracing at full speed without additional off- chip hardware. Using the JTAG port, the breakpointing is set up, and the trace history is read back. The port works in conjunction with the HDS code in the on-chip ROM and the hardware and software in a remote com- puter. The HDS code must be linked to the user's appli- cation code and reside in the first 4 Kwords of ROM. The on-chip HDS cannot be used with the secure ROM masking option (see Section 7.3, ROM Security Op- tions). Four hardware breakpoints can be set on instruction ad- dresses. A counter can be preset with the number of breakpoints to receive before trapping the core. Break- points can be set in interrupt service routines. Alternate- ly, the counter can be preset with the number of cache instructions to execute before trapping the core. Every time the program branches instead of executing the next sequential instruction, the addresses of the in- structions executed before and after the branch are caught in circular memory. The memory contains the last four pairs of program discontinuities for hardware tracing. In systems with multiple processors, the processors may be configured such that any processor reaching a breakpoint will cause all the other processors to be trapped (see Section 4.3, Interrupts and Trap). Pin Multiplexing In order to allow flexible device interfacing while main- taining a low package pin count, the DSP1627 multi- plexes 16 package pins between BIO, PHIF, VEC[3:0], and SIO2. Upon reset, the vectored interrupt indication signals, VEC[3:0], are connected to the package pins while IOBIT[4:7] are disconnected. Setting bit 12, EBIOH, of the ioc register connects IOBIT[4:7] to the package pins and disconnects VEC[3:0]. Upon reset, the parallel host interface (PHIF) is con- nected to the package pins while the second serial port (SIO2) and IOBIT[3:0] are disconnected. Setting bit 10, ESIO2, of the ioc register connects the SIO2 and IOBIT[3:0] and disconnects the PHIF. Power Management Many applications, such as portable cellular terminals, require programmable sleep modes for power manage- ment. There are three different control mechanisms for achieving low-power operation: the powerc control reg- ister, the STOP pin, and the AWAIT bit in the alf register. The AWAIT bit in the alf register allows the processor to go into a power-saving standby mode until an interrupt occurs. The powerc register configures various power- saving modes by controlling internal clocks and periph- eral I/O units. The STOP pin controls the internal pro- cessor clock. The various power management options may be chosen based on power consumption and/or wake-up latency requirements.

4.2 DSP1600 Core Architectural Overview

Figure 4 shows a block diagram of the DSP1600 core. System Cache and Control Section (SYS) This section of the core contains a 15-word cache mem- ory and controls the instruction sequencing. It handles vectored interrupts and traps, and also provides decod- ing for registers outside of the DSP1600 core. SYS stretches the processor cycle if wait-states are required (wait-states are programmable for external memory ac- cesses). SYS sequences downloading via JTAG of self- test programs to on-chip, dual-port RAM. The cache loop iteration count can be specified at run time under program control as well as at assembly time.

March 2000 DSP1627 Digital Signal Processor Lucent Technologies Inc. 11 Data Arithmetic Unit (DAU) The data arithmetic unit (DAU) contains a 16 x 16-bit parallel multiplier that generates a full 32-bit product in one instruction cycle. The product can be accumulated with one of two 36-bit accumulators. The accumulator data can be directly loaded from, or stored to, memory in two 16-bit words with optional saturation on overflow. The arithmetic logic unit (ALU) supports a full set of arithmetic and logical operations on either 16- or 32-bit data. A standard set of flags can be tested for condition- al ALU operations, branches, and subroutine calls. This procedure allows the processor to perform as a power- ful 16- or 32-bit microprocessor for logical and control applications. The available instruction set is fully com- patible with the DSP1617 instruction set. See Section 5.1 for more information on the instruction set. The user also has access to two additional DAU regis- ters. The psw register contains status information from the DAU (see Table 26, Processor Status Word Regis- ter). The arithmetic control register, auc, is used to con- figure some of the features of the DAU (see Table 27) including single-cycle squaring. The auc register align- ment field supports an arithmetic shift left by one and left or right by two. The auc register is cleared by reset. The counters c0 to c2 are signed, 8 bits wide, and may be used to count events such as the number of times the program has executed a sequence of code. They are controlled by the conditional instructions and pro- vide a convenient method of program looping. Y Space Address Arithmetic Unit (YAAU) The YAAU supports high-speed, register-indirect, com- pound, and direct addressing of data (Y) memory. Four general-purpose, 16-bit registers, r0 to r3, are available in the YAAU. These registers can be used to supply the read or write addresses for Y space data. The YAAU also decodes the 16-bit data memory address and out- puts individual memory enables for the data access. The YAAU can address the six 1 Kword banks of on- chip DPRAM or three external data memory segments. Up to 48 Kwords of off-chip RAM are addressable, with 16K addresses reserved for internal RAM. Two 16-bit registers, rb and re, allow zero-overhead modulo addressing of data for efficient filter implemen- tations. Two 16-bit signed registers, j and k, are used to hold user-defined postmodification increments. Fixed increments of +1, –1, and +2 are also available. Four compound-addressing modes are provided to make read/write operations more efficient. The YAAU allows direct (or indexed) addressing of data memory. In direct addressing, the 16-bit base register (ybase) supplies the 11 most significant bits of the ad- dress. The direct data instruction supplies the remaining 5 bits to form an address to Y memory space and also specifies one of 16 registers for the source or destina- tion. X Space Address Arithmetic Unit (XAAU) The XAAU supports high-speed, register-indirect, in- struction/coefficient memory addressing with postmodi- fication of the register. The 16-bit pt register is used for addressing coefficients. The signed register i holds a user-defined postincrement. A fixed postincrement of +1 is also available. Register PC is the program counter. Registers pr and pi hold the return address for subroutine calls and interrupts, respectively. The XAAU decodes the 16-bit instruction/coefficient ad- dress and produces enable signals for the appropriate X memory segment. The addressable X segments are internal ROM (up to 36 Kwords for the DSP1627x36, up to 32 Kwords for the DSP1627x32), six 1K banks of DPRAM, and external ROM. The locations of these memory segments depend upon the memory map selected (see Table 5). A security mode can be selected by mask option. This prevents unauthorized access to the contents of on-chip ROM (see Section 7, Mask-Programmable Options).

4.3 Interrupts and Trap

The DSP1627 supports prioritized, vectored interrupts and a trap. The device has eight internal hardware sources of program interrupt and two external interrupt pins. Additionally, there is a trap pin and a trap signal from the hardware development system (HDS). A soft- ware interrupt is available through the icall instruction. The icall instruction is reserved for use by the HDS. Each of these sources of interrupt and trap has a unique vector address and priority assigned to it. DSP16A in- terrupt compatibility is not maintained. The software interrupt and the traps are always enabled and do not have a corresponding bit in the ins register. Other vectored interrupts are enabled in the inc register (see Table 29, Interrupt Control (inc) Register) and monitored in the ins register (see Table 30, Interrupt Status (ins) Register). When the DSP1627 goes into an interrupt or trap service routine, the IACK pin is assert- ed. In addition, pins VEC[3:0] encode which interrupt/ trap is being serviced. Table 4 details the encoding used for VEC[3:0].

Figure 4. DSP1600 Core Block Diagram

Table 3. DSP1600 Core Block Diagram Legend 16 x 16 MPY 16-bit x 16-bit Multiplier. a0—a1 Accumulators 0 and 1 (16-bit halves specified as a0, a0l, a1, and a1l)*.

• F3 ALU instructions with immediates require specifying the high half of the accumulators as a0h and a1h.

ALU/SHIFT Arithmetic Logic Unit/Shifter. auc Arithmetic Unit Control. DAU Digital Arithmetic Unit. i Increment Register for the X Address Space. j Increment Register for the Y Address Space. k Increment Register for the Y Address Space. mwait External Memory Wait-states Register. p Product Register (16-bit halves specified as p, pl). pi Program Interrupt Return Register. r0—r3 Y Address Space Pointers. rb Modulo Addressing Register (begin address). re Modulo Addressing Register (end address). SYS System Cache and Control Section. x Multiplier Input Register. XAAU X Space Address Arithmetic Unit. YAAU Y Space Address Arithmetic Unit. ybase Direct Addressing Base Register. y DAU Register (16-bit halves specified as y, yl).

DSP1627 Digital Signal Processor March 2000 14 Lucent Technologies Inc. Vectored interrupts are serviced only after the execution of an interruptible instruction. If more than one vectored interrupt is asserted at the same time, the interrupts are serviced sequentially according to their assigned priori- ties. See Table 4 for the priorities assigned to the vec- tored interrupts. Interrupt service routines, branch and conditional branch instructions, cache loops, and in- structions that only decrement one of the RAM pointers, r0 to r3 (e.g., *r3− −), are not interruptible. A trap is similar to an interrupt, but it gains control of the processor by branching to the trap service routine even when the current instruction is noninterruptible. It may not be possible to return to normal instruction execution from the trap service routine since the machine state cannot always be saved. In particular, program execu- tion cannot be continued from a trapped cache loop or interrupt service routine. While in a trap service routine, another trap is ignored. When set to 1, the status bits in the ins register indicate that an interrupt has occurred. The processor must reach an interruptible state (completion of an interrupt- ible instruction) before an enabled vectored interrupt will be acted on. An interrupt will not be serviced if it is not enabled. Polled interrupt service can be implemented by disabling the interrupt in the inc register and then polling the ins register for the expected event. Vectored Interrupts Tables 29 and 30 show the inc and ins registers. A logic 1 written to any bit of inc enables (or unmasks) the as- sociated interrupt. If the bit is cleared to a logic 0, the in- terrupt is masked. Note that neither the software interrupt nor traps can be masked. The occurrence of an interrupt that is not masked will cause the program execution to transfer to the memory location pointed to by that interrupt's vector address, as- suming no other interrupt is being serviced (see Table 4, Interrupt Vector Table). The occurrence of an inter- rupt that is masked causes no automatic processor ac- tion, but will set the corresponding status bit in the ins register. If a masked interrupt occurs, it is latched in the ins register, but the interrupt is not taken. When un- latched, this latched interrupt will initiate automatic pro- cessor interrupt action. See the DSP1611/17/18/27 Digital Signal Processor Information Manual for a more detailed description of the interrupts. Signaling Interrupt Service Status Five pins of DSP1627 are devoted to signaling interrupt service status. The IACK pin goes high while any inter- rupt or user trap is being serviced, and goes low when the ireturn instruction from the service routine is issued. Four pins, VEC[3:0], carry a code indicating which of the interrupts or trap is being serviced. Table 4 contains the encodings used by each interrupt. Traps due to HDS breakpoints have no effect on either the IACK or VEC[3:0] pins. Instead, they show the inter- rupt state or interrupt source of the DSP when the trap occurred. Clearing Interrupts The PHIF interrupts (PIBF and POBE) are cleared by reading or writing the parallel host interface data trans- mit registers pdx0[in] and pdx0[out], respectively. The SIO and SIO2 interrupts (IBF, IBF2, OBE, and OBE2) are cleared by reading or writing, as appropriate, the se- rial data registers sdx[in], sdx2[in], sdx[out], and sdx2[out]. The JTAG interrupt (JINT) is cleared by read- ing the jtag register. Three of the vectored interrupts are cleared by writing to the ins register. Writing a 1 to the INT0, INT1, or TIME bits in the ins will cause the corresponding interrupt sta- tus bit to be cleared to a logic 0. The status bit for these vectored interrupts is also cleared when the ireturn in- struction is executed, leaving set any other vectored in- terrupts that are pending. Traps The TRAP pin of the DSP1627 is a bidirectional signal. At reset, it is configured as an input to the processor. Asserting the TRAP pin will force a user trap. The trap mechanism is used for two purposes. It can be used by an application to rapidly gain control of the processor for asynchronous time-critical event handling (typically for catastrophic error recovery). It is also used by the HDS for breakpointing and gaining control of the processor. Separate vectors are provided for the user trap (0x46) and the HDS trap (0x3). Traps are not maskable.

Table 4. Interrupt Vector Table

• Traps due to HDS breakpoints have no effect on VEC[3:0] pins.

routine, the value of the pi register may be overwritten. service routine from a user trap (0x46) service routine. ing a cache loop is also not possible. the HDS code, if present, resides in the on-chip ROM. cessor's TRAP pin is configured to be an output. wakes up and continues executing. terrupt service routine is executed. completely entering the sleep state.

DSP1627 Digital Signal Processor March 2000 16 Lucent Technologies Inc. For additional power savings, set ioc = 0x0180 and tim- erc = 0x0040 in addition to setting alf = 0x8000. This will hold the CKO pin low and shut down the timer and pres- caler (see Table 38 and Table 31). For a description of the control mechanisms for putting the DSP into low-power modes, see Section 4.13, Pow- er Management.

4.4 Memory Maps and Wait-States

The DSP1600 core implements a modified Harvard ar- chitecture that has separate on-chip 16-bit address and data buses for the instruction/coefficient (X) and data (Y) memory spaces. Table 5 shows the instruction/coef- ficient memory space maps for both the DSP1627x36 and DSP1627x32. The differences between the x36 and x32 memory maps can be seen by comparing the respective MAP1 and MAP3. For instance, MAP1 of the x36 provides for

36 Kwords of IROM and 6 Kwords of dual-port RAM

(DPRAM), whereas MAP1 of the x32 provides for

32 Kwords of IROM, 6 Kwords of DPRAM, and

16 Kwords of EROM. The DSP1627 provides a multiplexed external bus which accesses external RAM (ERAM) and ROM (ER- OM). Programmable wait-states are provided for exter- nal memory accesses. The instruction/coefficient memory map is configurable to provide application flex- ibility. Table 6 shows the data memory space, which has one map. Instruction/Coefficient Memory Map Selection In determining which memory map to use, the proces- sor evaluates the state of two parameters. The first is the LOWPR bit (bit 14) of the alf register. The LOWPR bit of the alf register is initialized to 0 automatically at re- set. LOWPR controls the starting address in memory assigned to the six 1K banks of dual-port RAM. If LOW- PR is low, internal dual-port RAM begins at address 0xC000. If LOWPR is high, internal dual-port RAM be- gins at address 0x0. LOWPR also moves IROM from 0x0 in MAP1 to 0x4000 in MAP3, and EROM from 0x0 in MAP2 to 0x4000 in MAP4. The second parameter is the value at reset of the EXM pin (pin 27 or pin 14, depending upon the package type). EXM determines whether the internal 36 Kwords ROM (IROM) will be addressable in the memory map. The Lucent Technologies development system tools, together with the on-chip HDS circuitry and the JTAG port, can independently set the memory map. Specifi- cally, during an HDS trap, the memory map is forced to MAP1. The user's map selection is restored when the trap service routine has completed execution. MAP1 MAP1 has the IROM starting at 0x0 and six 1 Kword banks of DPRAM starting at 0xC000. Additionally, MAP1 for the x32 has 16 Kwords of EROM starting at 0x8000. MAP1 is used if DSP1627 has EXM low at re- set and the LOWPR parameter is programmed to zero. It is also used during an HDS trap. MAP2 MAP2 differs from MAP1 in that the lowest 48 Kwords reference external ROM (EROM). MAP2 is used if EXM is high at reset, the LOWPR parameter is programmed to zero, and an HDS trap is not in progress. MAP3 MAP3 has the six 1 Kword banks of DPRAM starting at address 0x0. In MAP3 of the x36, the 36 Kwords of IROM start at 0x4000. Similarly, for the x32, 32 Kwords of IROM start at 0x4000. Additionally, MAP3 for the x32 has 16 Kwords of EROM starting at 0xC000. MAP3 is used if EXM is low at reset, the LOWPR bit is pro- grammed to 1, and an HDS trap is not in progress. Note that this map is not available if the secure mask-pro- grammable option has been ordered. MAP4 MAP4 differs from MAP3 in that addresses above 0x4000 reference external ROM (EROM). This map is used if the LOWPR bit is programmed to 1, an HDS trap is not in progress, and, either EXM is high during reset, or the secure mask-programmable option has been or- dered. Whenever the chip is reset using the RSTB pin, the de- fault memory map will be MAP1 or MAP2, depending upon the state of the EXM pin at reset. A reset through the HDS will not reinitialize the alf register, so the previ- ous memory map is retained. Boot from External ROM After RSTB goes from low to high, the DSP1627 comes out of reset and fetches an instruction from address zero of the instruction/coefficient space. The physical location of address zero is determined by the memory map in effect. If EXM is high at the rising edge of RSTB, MAP2 is selected. MAP2 has EROM at location zero; thus, program execution begins from external memory. If EXM is high and INT1 is low when RSTB rises, the mwait register defaults to 15 wait-states for all external memory segments. If INT1 is high, the mwait register defaults to 0 wait-states.

Table 5. Instruction/Coefficient Memory Maps

• MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine.

† LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map. ‡ MAP3 is not available if the secure mask-programmable option is selected.

• MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine.

† LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map. ‡ MAP3 is not available if the secure mask-programmable option is selected.

1. Addresses from 0x4000 to 0x40FF reference a 256-

reference high external data RAM (ERAMHI). ured in the appropriate field of the mwait register.

4.5 External Memory Interface (EMI)

AB[15:0], and a 16-bit external data bus, DB[15:0]. memory segment to be addressed. low. IO is intended for memory-mapped I/O. addressed, EROM is asserted low. nal read cycle immediately follows. Table 6. Data Memory Map (Not to Scale)

March 2000 DSP1627 Digital Signal Processor Lucent Technologies Inc. 19 programmed in the mwait register. For example, let two instructions be executed: the first reads a coefficient from EROM and writes data to ERAM; the second reads a coefficient from EROM and reads data from ERAM. The sequencer carries out the following steps at the ex- ternal memory interface: read EROM, write ERAM, read EROM, and read ERAM. Each step is done in sequen- tial one-instruction cycle steps, assuming zero wait- states are programmed. Note that the number of in- struction cycles taken by the two instructions is four. Al- so, in this case, the write hold time is zero. The DSP1627 allows writing into external instruction/ coefficient memory. By setting bit 11, WEROM, of the ioc register (see Table 38), writing to (or reading from) data memory or memory-mapped I/O asserts the EROM strobe instead of ERAMLO, IO, or ERAMHI. Therefore, with WEROM set, EROM appears in both Y space (replacing ERAM) and X space, in its normal po- sition. Bit 14 of the ioc register (see Table 38), EXTROM, may be used with WEROM to download to a full 64K of ex- ternal memory. When WEROM and EXTROM are both asserted, address bit 15 (AB15) is held low, aliasing the upper 32K of external memory into the lower 32K. When an access to internal memory is made, the AB[15:0] bus holds the last valid external memory ad- dress. Asserting the RSTB pin low 3-states the AB[15:0] bus. After reset, the AB[15:0] value is undefined. The leading edge of the memory segment enables can be delayed by approximately one-half a CKO period by programming the ioc register (see Table 38). This is used to avoid a situation in which two devices drive the data bus simultaneously. Bits 7, 8, and 13 of the ioc register select the mode of operation for the CKO pin (see Table 38). Available op- tions are a free-running unstretched clock, a wait-stated sequenced clock (runs through two complete cycles during a sequenced external memory access), and a wait-stated clock based on the internal instruction cycle. These clocks drop to the low-speed internal ring oscilla- tor when SLOWCKI is enabled (see 4.13, Power Man- agement). The high-to-low transitions of the wait-stated clock are synchronized to the high-to-low transition of the free-running clock. Also, the CKO pin provides ei- ther a continuously high level, a continuously low level, or changes at the rate of the internal processor clock. This last option, only available with the crystal and small-signal input clock options, enables the DSP1627 CKI input buffer to deliver a full-rate clock to other devic- es while the DSP1627 itself is in one of the low-power modes.

4.6 Bit Manipulation Unit (BMU)

The BMU interfaces directly to the main accumulators in the DAU providing the following features: ■ Barrel shifting—logical and arithmetic, left and right shift ■ Normalization and extraction of exponent ■ Bit-field extraction and insertion These features increase the efficiency of the DSP in ap- plications such as control or data encoding and decod- ing. For example, data packing and unpacking, in which short data words are packed into one 16-bit word for more efficient memory storage, is very easy. In addition, the BMU provides two auxiliary accumula- tors, aa0 and aa1. In one instruction cycle, 36-bit data can be shuffled, or swapped, between one of the main accumulators and one of the alternate accumulators. The ar<0—3> registers are 16-bit registers that control the operations of the BMU. They store a value that de- termines the amount of shift or the width and offset fields for bit extraction or insertion. Certain operations in the BMU set flags in the DAU psw register and the alf register (see Table 26, Processor Status Word (psw) Register, and Table 35, alf Register). The ar<0—3> reg- isters can also be used as general-purpose registers. The BMU instructions are detailed in Section 5.1. For a thorough description of the BMU, see the DSP1611/17/ 18/27 Digital Signal Processor Information Manual.

4.7 Serial I/O Units (SIOs)

The serial I/O ports on the DSP1627 device provide a serial interface to many codecs and signal processors with little, if any, external hardware required. Each high- speed, double-buffered port (sdx and sdx2) supports back-to-back transmissions of data. SIO and SIO2 are identical. The output buffer empty (OBE and OBE2) and input buffer full (IBF and IBF2) flags facilitate the read- ing and/or writing of each serial I/O port by program- or interrupt-driven I/O. There are four selectable active clock speeds. A bit-reversal mode provides compatibility with either the most significant bit (MSB) first or least significant bit (LSB) first serial I/O formats (see Table 22, Serial I/O Control Registers (sioc and sioc2)). A multiprocessor I/O configuration is supported. This feature allows up to eight DSP161X devices to be connected together on an SIO port without requiring external glue logic.

DSP1627 Digital Signal Processor March 2000 20 Lucent Technologies Inc. The serial data may be internally looped back by setting the SIO loopback control bit, SIOLBC, of the ioc regis- ter. SIOLBC affects both the SIO and SIO2. The data output signals are wrapped around internally from the output to the input (DO1 to DI1 and DO2 to DI2). To ex- ercise loopback, the SIO clocks (ICK1, ICK2, OCK1, and OCK2) should either all be in the active mode, 16-bit condition, or each pair should be driven from one external source in passive mode. Similarly, pins ILD1 (ILD2) and OLD1 (OLD2) must both be in active mode or tied together and driven from one external frame clock in passive mode. During loopback, DO1, DO2, DI1, DI2, ICK1, ICK2, OCK1, OCK2, ILD1, ILD2, OLD1, OLD2, SADD1, SADD2, SYNC1, SYNC2, DOEN1, and DOEN2 are 3-stated. Setting DODLY = 1 (sioc and sioc2) delays DO by one phase of OCK so that DO changes on the falling edge of OCK instead of the rising edge (DODLY = 0). This re- duces the time available for DO to drive DI and to be val- id for the rising edge of ICK, but increases the hold time on DO by half a cycle on OCK. Programmable Modes Programmable modes of operation for the SIO and SIO2 are controlled by the serial I/O control registers (sioc and sioc2). These registers, shown in Table 22, are used to set the ports into various configurations. Both input and output operations can be independently configured as either active or passive. When active, the DSP1627 generates load and clock signals. When pas- sive, load and clock signal pins are inputs. Since input and output can be independently config- ured, each SIO has four different modes of operation. Each of the sioc registers is also used to select the fre- quency of active clocks for that SIO. Finally, these reg- isters are used to configure the serial I/O data formats. The data can be 8 or 16 bits long, and can also be input/ output MSB first or LSB first. Input and output data for- mats can be independently configured. Multiprocessor Mode The multiprocessor mode allows up to eight processors (DSP1629, DSP1628, DSP1627, DSP1620, DSP1618, DSP1617, DSP1616, DSP1611) to be connected to- gether to provide data transmission among any of the DSPs in the system. Either SIO port (SIO or SIO2) may be independently used for the multiprocessor mode. The multiprocessor interface is a four-wire interface, consisting of a data channel, an address/protocol channel, a transmit/receive clock, and a sync signal (see Figure 5). The DI1 and DO1 pins of all the DSPs are connected to transmit and receive the data channel. The SADD1 pins of all the DSPs are connected to trans- mit and receive the address/protocol channel. ICK1 and OCK1 should be tied together and driven from one source. The SYNC1 pins of all the DSPs are connected. In the configuration shown in Figure 5, the master DSP (DSP0) generates active SYNC1 and OCK1 signals while the slave DSPs use the SYNC1 and OCK1 signals in passive mode to synchronize operations. In addition, all DSPs must have their ILD1 and OLD1 signals in ac- tive mode. While ILD1 and OLD1 are not required externally for multiprocessor operation, they are used internally in the DSP's SIO. Setting the LD field of the master's sioc reg- ister to a logic level 1 will ensure that the active genera- tion of SYNC1, ILD1, and OLD1 is derived from OCK1 (see Table 22). With this configuration, all DSPs should use ICK1 (tied to OCK1) in passive mode to avoid con- flicts on the clock (CK) line (see the DSP1611/17/18/27 Digital Signal Processor Information Manual for more information). Four registers (per SIO) configure the multiprocessor mode: the time-division multiplexed slot register (tdms or tdms2), the serial receive and transmit address reg- ister (srta or srta2), the serial data transmit register (sdx or sdx2), and the multiprocessor serial address/protocol register (saddx or saddx2). Multiprocessor mode requires no external logic and uses a TDM interface with eight 16-bit time slots per frame. The transmission in any time slot consists of 16 bits of serial data in the data channel and 16 bits of address and protocol information in the address/proto- col channel. The address information consists of the transmit address field of the srta register of the transmit- ting device. The address information is transmitted con- currently with the transmission of the first 8 bits of data. The protocol information consists of the transmit proto- col field written to the saddx register and is transmitted concurrently with the last 8 bits of data (see Table 25, Multiprocessor Protocol Register). Data is received or recognized by other DSP(s) whose receive address matches the address in the address/protocol channel. Each SIO port has a user-programmable receive ad- dress and transmit address associated with it. The transmit and receive addresses are programmed in the srta register. In multiprocessor mode, each device can send data in a unique time slot designated by the tdms register trans- mit slot field (bits 7—0). The tdms register has a fully de- coded transmit slot field in order to allow one DSP1627 device to transmit in more than one time slot. This pro- cedure is useful for multiprocessor systems with less than eight DSP1627 devices when a higher bandwidth is necessary between certain devices in that system. The DSP operating during time slot 0 also drives SYNC1.

can be programmed to transmit in a particular time slot. (bits 15—8) determines which data will be received. multiplexing of BIO, PHIF, VEC[3:0], and SIO2. Figure 5. Multiprocessor Communication and Connections

4.8 Parallel Host Interface (PHIF)

trollers, microprocessors, or another DSP). the programmable options for this port. vice to recognize an interrupt. register. Setting PMODE selects 16-bit transfer mode. through bit 2, PSTRB, of the phifc register. scription of BIO, PHIF, VEC[3:0], and SIO2 pins. Table 7. PHIF Function (8-bit and 16-bit Modes) Table 8. pstat Register as Seen on PB[7:0]

4.9 Bit Input/Output Unit (BIO)

configured as an input, it can be read and/or tested. ister is cleared upon reset. ed for the associated IOBIT pin. description of BIO, PHIF, VEC[3:0], and SIO2 pins.

4.10 Timer

wide range of interrupt delay periods. the RELOAD bit in the timerc register. od register is not initialized on reset. Table 9. BIO Operations

4.11 JTAG Test Port

wire test port for self-test and hardware emulation. a device identification register have been implemented. shifted out during SHIFT-IR controller states. Table 10. JTAG Instruction Register

Note that the direction of shifting is from TDI to cell 104 to cell 103 . . . to cell 0 of TDO.

• Please refer to Pin Multiplexing in Section 4.1 for a description of pin multiplexing of BIO, PHIF, VEC[3:0], and SIO2.

† Note that shifting a zero into this cell in the mode to scan a zero into the chip will disable the processor clocks just as the STOP pin will. ‡ When the JTAG SAMPLE instruction is used, this cell will have a logic one regardless of the state of the pin. Table 11. JTAG Boundary-Scan Register

0 OE Controls cells 1, 27—31 69 B OCK2/PCSN*

1 O CKO 70 DC Controls cell 71

3 DC Controls cell 4 72 DC Controls cell 73

4 B TRAP 73 B SYNC2/PBSEL*

6 O IACK 75 B ILD2/PIDS*

7 I INT0 76 DC Controls cell 77

8 OE Controls cells 6, 10—25, 49, 50, 78, 79 77 B OLD2/PODS*

9 I INT1 78 O IBF2/PIBF*

26 I EXM 80 DC Controls cell 81

27 O RWN 81 B ICK2/PB0*

37 DC Controls cells 32—36, 38—48 84 DC Controls cell 85

49 O OBE1 86 DC Controls cell 87

50 O IBF1 87 B SADD2/PB3*

51 I DI1 88 DC Controls cell 89

52 DC Controls cell 53 89 B IOBIT0/PB4*

53 B ILD1 90 DC Controls cell 91

54 DC Controls cell 55 91 B IOBIT1/PB5*

55 B ICK1 92 DC Controls cell 93

56 DC Controls cell 57 93 B IOBIT2/PB6*

57 B OCK1 94 DC Controls cell 95

58 DC Controls cell 59 95 B IOBIT3/PB7*

59 B OLD1 96 DC Controls cell 97

60 OE Controls cell 61 97 B VEC3/IOBIT4*

61 O DO1 98 DC Controls cell 99

62 DC Controls cell 63 99 B VEC2/IOBIT5*

63 B SYNC1 100 DC Controls cell 101

64 DC Controls cell 65 101 B VEC1/IOBIT6*

65 B SADD1 102 DC Controls cell 103

66 DC Controls cell 67 103 B VEC0/IOBIT7*

67 B DOEN1 104 I CKI

68 DC Controls cell 69

4.12 Clock Synthesis

Figure 6. Clock Source Block Diagram clock synthesizer. Figure 6 is the clock source diagram. clock synthesizer and PLL are used interchangeably. written, the LOCK flag is reset.

March 2000 DSP1627 Digital Signal Processor Lucent Technologies Inc. 27 The frequency of the PLL output clock, fVCO , is deter- mined by the values loaded into the 3-bit N divider and the 5-bit M divider. When the PLL is selected and locked, the frequency of the internal processor clock is related to the frequency of CKI by the following equa- tions: f VCO = fCKI * M/N fINTERNAL CLOCK = fCKO = fVCO ÷ 2 The frequency of the VCO, fVCO , must fall within the range listed in Table 63. Also note that fVCO must be at least twice fCKI. The coding of the Mbits and Nbits is described as fol- lows: Mbits = M − 2 if (N == 1) Nbits = 0x7 else Nbits = N − 2 where N ranges from 1 to 8 and M ranges from 2 to 20. The loop filter bits LF[3:0] should be programmed ac- cording to Table 64. Two other bits in the pllc register control the PLL. Clear- ing the PLLEN bit powers down the PLL; setting this bit powers up the PLL. Clearing the PLLSEL bit deselects the PLL so that the DSP is clocked by a 1X version of the CKI input; setting the PLLSEL bit selects the PLL- generated clock for the source of the DSP internal pro- cessor clock. The pllc register is cleared on reset and powerup. Therefore, the DSP comes out of reset with the PLL deselected and powered down. M and N should be changed only while the PLL is deselected. The val- ues of M and N should not be changed when powering down or deselecting the PLL. As previously mentioned, the PLL also provides a user flag, LOCK, to indicate when the loop has locked. When this flag is not asserted, the PLL output is unstable. The DSP should not be switched to the PLL-based clock without first checking that the lock flag is set. The lock flag is cleared by writing to the pllc register. When the PLL is deselected, it is necessary to wait for the PLL to relock before the DSP can be switched to the PLL- based clock. Before the input clock is stopped, the PLL should be powered down. Otherwise, the LOCK flag will not be reset and there may be no way to determine if the PLL is stable, once the input clock is applied again. The lock-in time depends on the frequency of operation and the values programmed for M and N (see Table 64).

The device would come out of reset with the PLL disabled and deselected. the DSP, and thus, this clock should not be used as an input to jitter-sensitive devices in the system. Table 12. Latency Times for Switching Between CKI and PLL-Based Clocks

March 2000 DSP1627 Digital Signal Processor Lucent Technologies Inc. 29

4.13 Power Management

There are three different control mechanisms for putting the DSP1627 into low-power modes: the powerc control register, the STOP pin, and the AWAIT bit in the alf reg- ister. The PLL can also be disabled with the PLLEN bit of the pllc register for more power saving. Powerc Control Register Bits The powerc register has 10 bits that power down vari- ous portions of the chip and select the clock source: XTLOFF: Assertion of the XTLOFF bit powers down the crystal oscillator or the small-signal input circuit, dis- abling the internal processor clock. Assertion of the XTLOFF bit to disable the crystal oscillator also pre- vents its use as a noninverting buffer. Since the oscilla- tor and the small-signal input circuits take many cycles to stabilize, care must be taken with the turn-on se- quence, as described later. SLOWCKI: Assertion of the SLOWCKI bit selects the ring oscillator as the clock source for the internal pro- cessor clock instead of CKI or the PLL. When CKI or the PLL is selected, the ring oscillator is powered down. Switching of the clocks is synchronized so that no par- tial or short clock pulses occur. Two nop s should follow the instruction that sets or clears SLOWCKI. NOCK: Assertion of the NOCK bit synchronously turns off the internal processor clock, regardless of whether its source is provided by CKI, the PLL, or the ring oscil- lator. The NOCK bit can be cleared by resetting the chip with the RSTB pin, or asserting the INT0 or INT1 pins. Two nop s should follow the instruction that sets NOCK. The PLL remains running, if enabled, while NOCK is set. INT0EN: This bit allows the INT0 pin to asynchronously clear the NOCK bit, thereby allowing the device to con- tinue program execution from where it left off without any loss of state. No chip reset is required. It is recom- mended that, when INT0EN is to be used, the INT0 interrupt be disabled in the inc register so that an unin- tended interrupt does not occur. After the program re- sumes, the INT0 interrupt in the ins register should be cleared. INT1EN: This bit enables the INT1 pin to be used as the NOCK clear, exactly like INT0EN previously described. The following control bits power down the peripheral I/O units of the DSP. These bits can be used to further reduce the power consumption during standard sleep mode. SIO1DIS: This is a powerdown signal to the SIO1 I/O unit. It disables the clock input to the unit, thus eliminat- ing any sleep power associated with the SIO1. Since the gating of the clocks may result in incomplete trans- actions, it is recommended that this option be used in applications where the SIO1 is not used or when reset may be used to reenable the SIO1 unit. Otherwise, the first transaction after reenabling the unit may be corrupt- ed. SIO2DIS: This bit powers down the SIO2 in the same way SIO1DIS powers down the SIO1. PHIFDIS: This is a powerdown signal to the parallel host interface. It disables the clock input to the unit, thus eliminating any sleep power associated with the PHIF. Since the gating of the clocks may result in incomplete transactions, it is recommended that this option be used in applications where the PHIF is not used, or when re- set may be used to reenable the PHIF. Otherwise, the first transaction after reenabling the unit may be corrupt- ed. TIMERDIS: This is a timer disable signal which disables the clock input to the timer unit. Its function is identical to the DISABLE field of the timerc control register. Writ- ing a 0 to the TIMERDIS field will continue the timer op- eration. Figure 7 shows a functional view of the effect of the bits of the powerc register on the clock circuitry. It shows only the high-level operation of each bit. Not shown are the bits that power down the peripheral units. STOP Pin Assertion (active-low) of the STOP pin has the same ef- fect as setting the NOCK bit in the powerc register. The internal processor clock is synchronously disabled until the STOP pin is returned high. Once the STOP pin is re- turned high, program execution will continue from where it left off without any loss of state. No chip reset is required. The PLL remains running, if enabled, during STOP assertion. The pllc Register Bits The PLLEN bit of the pllc register can be used to power down the clock synthesizer circuitry. Before shutting down the clock synthesizer circuitry, the system clock should be switched to either CKI using the PLLSEL bit of pllc, or to the ring oscillator using the SLOWCKI bit of powerc.

Deep sleep is the state arrived at either by a hardware or software stop of the internal processor clock. The switching of the multiplexers and the synchronous gate is designed so that no partial clocks or glitching will occur. PLL select is the PLLSEL bit of pllc; PLL powerdown is the PLLEN bit of pllc. Figure 7. Power Management Using the powerc and the pllc Registers

March 2000 DSP1627 Digital Signal Processor Lucent Technologies Inc. 31 Await Bit of the alf Register Setting the AWAIT bit of the alf register causes the pro- cessor to go into the standard sleep state or power-sav- ing standby mode. Operation of the AWAIT bit is the same as in the DSP1610, DSP1611, DSP1616, DSP1617, and DSP1618. In this mode, the minimum circuitry required to process an incoming interrupt re- mains active, and the PLL remains active if enabled. An interrupt will return the processor to the previous state, and program execution will continue. The action result- ing from setting the AWAIT bit and the action resulting from setting bits in the powerc register are mostly inde- pendent. As long as the processor is receiving a clock, whether slow or fast, the DSP may be put into standard sleep mode with the AWAIT bit. Once the AWAIT bit is set, the STOP pin can be used to stop and later restart the processor clock, returning to the standard sleep state. If the processor clock is not running, however, the AWAIT bit cannot be set. Power Management Sequencing There are important considerations for sequencing the power management modes. Both the crystal oscillator and the small-signal clock input circuits have start-up delays which must be taken into account, and the PLL requires a delay to reach lock-in. Also, the chip may or may not need to be reset following a return from a low- power state. Devices with a crystal oscillator or small-signal input clocking option may use the XTLOFF bit in the powerc register to power down the on-chip oscillator or small- signal circuitry, thereby reducing the power dissipation. When reenabling the oscillator or the small-signal cir- cuitry, it is important to bear in mind that a start-up inter- val exists during which time the clocks are not stable. Two scenarios exist here: 1. Immediate Turn-Off, Turn-On with RSTB: This sce- nario applies to situations where the target device is not required to execute any code while the crystal os- cillator or small-signal input circuit is powered down and where restart from a reset state can be tolerated. In this case, the processor clock derived from either the oscillator or the small-signal input is running when XTLOFF is asserted. This effectively stops the inter- nal processor clock. When the system chooses to re- enable the oscillator or small-signal input, a reset of the device will be required. The reset pulse must be of sufficient duration for the oscillator start-up interval to be satisfied. A similar interval is required for the small-signal input circuit to reach its dc operating point. A minimum reset pulse of 20 ms will be ade- quate. The falling edge of the reset signal, RSTB, will asynchronously clear the XTLOFF field, thus re-en- abling the power to the oscillator or small-signal cir- cuitry. The target DSP will then start execution from a reset state, following the rising edge of RSTB. 2. Running from Slow Clock While XTLOFF Active: The second scenario applies to situations where the de- vice needs to continue execution of its target code when the crystal oscillator or small-signal input is powered down. In this case, the device switches to the slow ring oscillator clock first, by enabling the SLOWCKI field before writing a 1 to the XTLOFF field. Two nop s are needed in between the two write operations to the powerc register. The target device will then continue execution of its code at slow speed, while the crystal oscillator or small-signal input clock is turned off. Switching from the slow clock back to the high-speed crystal oscillator clock is then accom- plished in three user steps. First, XTLOFF is cleared. Then, a user-programmed routine sets the internal timer to a delay to wait for the crystal's oscillations to become stable. When the timer counts down to zero, the high-speed clock is selected by clearing the SLOWCKI field, either in the timer's interrupt service routine or following a timer polling loop. If PLL opera- tion is desired, then an additional routine is neces- sary to enable the PLL and wait for it to lock.

DSP1627 Digital Signal Processor March 2000 32 Lucent Technologies Inc. Power Management Examples Without the PLL The following examples show the more significant options for reducing the power dissipation. These are valid only if the pllc register is set to disable and deselect the PLL (PLLEN = 0, PLLSEL = 0). Standard Sleep Mode. This is the standard sleep mode. While the processor is clocked with a high-speed clock, CKI, the alf register's AWAIT bit is set. Peripheral units may be turned off to further reduce the sleep power. powerc = 0X00F0 /* Turn off peripherals, core running with CKI */ sleep:a0 = 0x8000 /* Set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* Stop internal processor clock, interrupt circuits */ nop /* active */ nop /* Needed for bedtime execution. Only sleep power */ nop /* consumed here until.... interrupt wakes up the device */ cont: . . . /* User code executes here */ powerc = 0x0 /* Turn peripheral units back on */ Sleep with Slow Internal Clock. In this case, the ring oscillator is selected to clock the processor before the device is put to sleep. This will reduce the power dissipation while waiting for an interrupt to continue program execution. powerc = 0x40F0 /* Turn off peripherals and select slow clock */ 2*nop /* Wait for it to take effect */ sleep:a0 = 0x8000 /* Set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* Stop internal processor clock, interrupt circuits */ nop /* active */ nop /* Needed for bedtime execution. Reduced sleep power */ nop /* consumed here.... Interrupt wakes up the device */ cont: . . . /* User code executes here */ powerc = 0x00F0 /* Select high-speed clock */ 2*nop /* Wait for it to take effect */ powerc = 0x0000 /* Turn peripheral units back on */ Note that, in this case, the wake-up latency is determined by the period of the ring oscillator clock. Sleep with Slow Internal Clock and Crystal Oscillator/Small-Signal Disabled. If the target device contains the crystal oscillator or the small-signal clock option, the clock input circuitry can be powered down to further reduce power. In this case, the slow clock must be selected first. powerc = 0x40F0 /* Turn off peripherals and select slow clock */ 2*nop /* Wait for it to take effect */ powerc = 0xC0F0 /* Turn off the crystal oscillator */ sleep:a0 = 0x8000 /* Set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* Stop internal processor clock, interrupt circuits */ nop /* active */ nop /* Needed for bedtime execution. Reduced sleep power */ nop /* consumed here.... Interrupt wakes up the device */ powerc = 0x40F0 /* Clear XTLOFF, reenable oscillator/small-signal */ call xtlwait /* Wait until oscillator/small-signal is stable */ cont: powerc = 0x00F0 /* Select high-speed clock */ 2*nop /* Wait for it to take effect */ powerc = 0x0000 /* Turn peripheral units back on */ Note that, in this case, the wake-up latency is dominated by the crystal oscillator or small-signal start-up period.

March 2000 DSP1627 Digital Signal Processor Lucent Technologies Inc. 33 Software Stop. In this case, all internal clocking is disabled. INT0, INT1, or RSTB may be used to reenable the clocks. If the device uses the crystal oscillator or small-signal clock option, the power management must be done in correct sequence. powerc = 0x4000 /* SLOWCKI asserted */ 2*nop /* Wait for it to take effect */ powerc = 0xD000 /* XTLOFF asserted if applicable and INT0EN asserted */ inc = NOINT0 /* Disable the INT0 interrupt */ sopor:powerc = 0xF000 /* NOCK asserted, all clocks stop */ /* Minimum switching power consumed here */ 3*nop /* Some nops will be needed */ /* INT0 pin clears the NOCK field, clocking resumes */ cont: powerc = 0x4000 /* INT0EN cleared and XTLOFF cleared, if applicable*/ call waitxtl /* Wait for the crystal oscillator/small-signal to */ /* stabilize, if applicable*/ powerc = 0x0 /* Clear SLOWCKI field, back to high speed */ 2*nop /* Wait for it to take effect */ ins = 0x0010 /* Clear the INT0 status bit */ In this case also, the wake-up latency is dominated by the crystal oscillator or small-signal start-up period. The previous examples do not provide an exhaustive list of options available to the user. Many different clocking possibilities exist for which the target device may be programmed, depending on: ■ The clock source to the processor. ■ Whether the user chooses to power down the peripheral units. ■ The operational state of the crystal oscillator/small-signal clock input, powered or unpowered. ■ Whether the internal processor clock is disabled through hardware or software. ■ The combination of power management modes the user chooses. ■ Whether or not the PLL is enabled. An example subroutine for xtlwait follows: xtlwait: timer0 = 0x2710 /* Load a count of 10,000 into the timer */ timerc = 0x0010 /* Start the timer with a PRESCALE of two */ inc = 0x0000 /* Disable the interrupts */ loop1: a0 = ins /* Poll the ins register */ a0 = a0 & 0x0100 /* Check bit 8 (TIME) of the ins register */ if eq goto loop1 /* Loop if the bit is not set */ ins = 0x0100 /* Clear the TIME interrupt bit */ return /* Return to the main program */

DSP1627 Digital Signal Processor March 2000 34 Lucent Technologies Inc. Power Management Examples with the PLL The following examples show the more significant options for reducing power dissipation if operation with the PLL clock synthesizer is desired. Standard Sleep Mode, PLL Running. This mode would be entered in the same manner as without the PLL. While the input to the clock synthesizer, CKI, remains running, the alf register's AWAIT bit is set. The PLL will continue to run and dissipate power. Peripheral units may be turned off to further reduce the sleep power. powerc = 0x00F0 /* Turn off peripherals, core running with PLL */ sleep:a0 = 0x8000 /* Set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* Stop internal processor clock, interrupt circuits */ nop /* active */ nop /* Needed for bedtime execution. Only sleep power plus PLL */ nop /* power consumed here.... Interrupt wakes up the device */ cont: . . . /* User code executes here */ powerc = 0x0 /* Turn peripheral units back on */ Sleep with Slow Internal Clock, PLL Running. In this case, the ring oscillator is selected to clock the processor before the device is put to sleep. This will reduce power dissipation while waiting for an interrupt to continue program execution. powerc = 0x40F0 /* Turn off peripherals and select slow clock */ 2*nop /* Wait for slow clock to take effect */ sleep:a0 = 0x8000 /* Set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* Stop internal processor clock, interrupt circuits */ nop /* active */ nop /* Needed for bedtime execution. Reduced sleep power, PLL */ nop /* power, and ring oscillator power consumed here... */ /* Interrupt wakes up the device */ cont: . . . /* User code executes here */ powerc = 0x00F0 /* Select high-speed PLL based clock */ 2*nop /* Wait for it to take effect */ powerc = 0x0000 /* Turn peripheral units back on */

March 2000 DSP1627 Digital Signal Processor Lucent Technologies Inc. 35 Sleep with Slow Internal Clock and Crystal Oscillator/Small-Signal Disabled, PLL Disabled. If the target de- vice contains the crystal oscillator or the small-signal clock option, the clock input circuitry can be powered down to further reduce power. In this case, the slow clock must be selected first, and then the PLL must be disabled, since the PLL cannot run without the clock input circuitry being active. powerc = 0x40F0 /* Turn off peripherals and select slow clock */ 2*nop /* Wait for slow clock to take effect */ pllc = 0x29F2 /* Disable PLL (assume N = 1,M = 20, LF = 1001) */ powerc = 0xC0F0 /* Disable crystal oscillator */ sleep:a0 = 0x8000 /* Set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* Stop internal processor clock, interrupt circuits */ nop /* active */ nop /* Needed for bedtime execution. Reduced sleep power nop /* consumed here.... Interrupt wakes up device */ powerc = 0x40F0 /* Clear XTLOFF, leave PLL disabled */ call xtlwait /* Wait until crystal oscillator/small-signal is stable */ pllc = 0xE9F2 /* Enable PLL, continue to run off slow clock */ call pllwait /* Loop to check for LOCK flag assertion */ cont: powerc = 0x00F0 /* Select high-speed PLL based clock */ 2*nop /* Wait for it to take effect */ powerc = 0x0000 /* Turn peripherals back on */ Software Stop, PLL Disabled. In this case, all internal clocking is disabled. INT0, INT1, or RSTB may be used to reenable the clocks. If the device uses the crystal oscillator or small-signal clock option, the power management must be done in the correct sequence, with the PLL being disabled before shutting down the clock input buffer. powerc = 0x4000 /* SLOWCKI asserted */ 2*nop /* Wait for slow clock to take effect */ pllc = 0x29F2 /* Disable PLL (assume N = 1, M = 20, LF = 1001) */ powerc = 0xD000 /* XTLOFF asserted, if applicable and INT0EN /* asserted */ sopor:powerc = 0xF000 /* NOCK asserted, all clocks stop */ /* Minimum switching power consumed here */ 3*nop /* Some nops will be needed */ /* INT0 pin clears NOCK field, clocking resumes */ cont: powerc = 0x4000 /* INTOEN cleared and XTLOFF cleared, if applicable */ call xtlwait /* Wait until crystal oscillator/small-signal is stable */ /* if applicable */ pllc = 0xE9F2 /* Enable PLL, continue to run off slow clock */ call pllwait /* Loop to check for LOCK flag assertion */ powerc = 0x0 /* Select high-speed PLL based clock */ 2*nop /* Wait for it to take effect */ ins = 0x0010 /* Clear the INT0 status bit */

DSP1627 Digital Signal Processor March 2000 36 Lucent Technologies Inc.

5 Software Architecture

5.1 Instruction Set

The DSP1627 processor has seven types of instruc- tions: multiply/ALU, special function, control, F3 ALU, BMU, cache, and data move. The multiply/ALU instruc- tions are the primary instructions used to implement sig- nal processing algorithms. Statements from this group can be combined to generate multiply/accumulate, log- ical, and other ALU functions and to transfer data be- tween memory and registers in the data arithmetic unit. The special function instructions can be conditionally executed based on flags from the previous ALU or BMU operation, the condition of one of the counters, or the value of a pseudorandom bit in the DSP1627 device. Special function instructions perform shift, round, and complement functions. The F3 ALU instructions enrich the operations available on accumulators. The BMU in- structions provide high-performance bit manipulation. The control instructions implement the goto and call commands. Control instructions can also be executed conditionally. Cache instructions are used to implement low-overhead loops, conserve program memory, and decrease the execution time of certain multiply/ALU in- structions. Data move instructions are used to transfer data between memory and registers or between accu- mulators and registers. See the DSP1611/17/18/27 Digital Signal Processor Information Manual for a de- tailed description of the instruction set. The following operators are used in describing the in- struction set: ■ * 16 x 16-bit –> 32-bit multiplication or register-in- direct addressing when used as a prefix to an ad- dress register or denotes direct addressing when used as a prefix to an immediate ■ + 36-bit addition† ■ – 36-bit subtraction† ■ >> Arithmetic right shift ■ >>> Logical right shift ■ << Arithmetic left shift ■ <<< Logical left shift ■ | 36-bit bitwise OR† ■ & 36-bit bitwise AND† ■ ^ 36-bit bitwise EXCLUSIVE OR† ■ : Compound address swapping, accumulator shuffling ■ ~ One's complement † These are 36-bit operations. One operand is 36-bit data in an ac- cumulator; the other operand may be 16, 32, or 36 bits. Multiply/ALU Instructions Note that the function statements and transfer state- ments in Table 13 are chosen independently. Any func- tion statement (F1) can be combined with any transfer statement to form a valid multiply/ALU instruction. If ei- ther statement is not required, a single statement from either column also constitutes a valid instruction. The number of cycles to execute the instruction is a function of the transfer column. (An instruction with no transfer statement executes in one instruction cycle.) Whenever PC, pt, or rM is used in the instruction and points to ex- ternal memory, the programmed number of wait-states must be added to the instruction cycle count. All multi- ply/ALU instructions require one word of program mem- ory. The no-operation (nop ) instruction is a special- case encoding of a multiply/ALU instruction and exe- cutes in one cycle. The assembly-language representa- tion of a nop is either nop or a single semicolon. A single-cycle squaring function is provided in DSP1627. By setting the X = Y = bit in the auc register, any instruction that loads the high half of the y register also loads the x register with the same value. A subse- quent instruction to multiply the x register and y register results in the square of the value being placed in the p register. The instruction a0 = p p = x*y y = *r0++ with the X = Y = bit set to one will read the value pointed to by r0, load it to both x and y, multiply the previously fetched value of x and y, and transfer the previous prod- uct to a0. A table of values pointed to by r0 can thus be squared in a pipeline with one instruction cycle per each value. Multiply/ALU instructions that use x = X transfer statements (such as a0 = p p = x*y y = *r0++ x = *pt++) are not recommended for squaring because pt will be incremented even though x is not loaded from the value pointed to by pt. Also, the same conflict wait occurrenc- es from reading the same bank of internal memory or reading from external memory apply, since the X space fetch occurs (even though its value is not used).

5 Software Architecture (continued)

† The l in [ ] is an optional argument that specifies the low 16 bits of aT or y.

1. When an external memory access is made in X or Y space and wait-states are programmed, add the number of wait-states.
2. If an X space access and a Y space access are made to the same bank of DPRAM in one instruction, add one cycle.

sponding CLR bit in the auc register is zero. auc is cleared by reset. Table 13. Multiply/ALU Instructions Table 14. Replacement Table for Multiply/ALU Instructions aD, aS, aT a0, a1 One of two DAU accumulators. 0, +1, –1, or j, respectively. Z *rMzp, *rMpz, *rMm2, *rMjk Read/Write compound addressing. rM (M = 0, 1, 2, 3) is used twice. modified by +1, 0, +2, or k, respectively.

The above special function statements can be executed unconditionally by writing them directly, e.g., a0 = a1.

• This function is not available for the DSP16A.

Table 15. Replacement Table for Special Function Instructions a0, a1 One of two DAU accumulators. See Table 17 for definitions of mnemonics.

to the desired current page. ‡T h e icall instruction is reserved for development system use. Table 16. Replacement Table for Control Instructions See Table 17 for definitions of mnemonics. within the same 4 Kwords memory section.

Table 17 lists mnemonics used in conditional execution of special function and control instructions. Testing the state of the counters (c0 or c1) automatically increments the counter by one. Table 17. DSP1627 Conditional Mnemonics

• Result is not representable in the 36-bit accumulators (36-bit overflow).

† Bits 35—31 are not the same (32-bit overflow). mvc Mathematical overflow clear. c0ge Counter 0 greater than or equal to 0. c0lt Counter 0 less than 0. c1ge Counter 1 greater than or equal to 0. c1lt Counter 1 less than 0. heads Pseudorandom sequence bit set. tails Pseudorandom sequence bit clear. oddp Odd Parity, from BMU operation. evenp Even Parity, from BMU operation. mns1 Minus 1, result of BMU operation. nmns1 Not Minus 1, result of BMU operation. lock The PLL has achieved lock and is stable.

by programming two consecutive 16-bit immediate operations. The F3 ALU instructions are shown in Table 18. operations, i.e., bit test operations. † If PC points to external memory, add programmed wait-states. ‡ The h and l are required notation in these instructions. LLV, and LMV flags in the psw register. 27 Digital Signal Processor Information Manual for further discussion of the BMU instructions. Table 18. F3 ALU Instructions

aD = aS >> IM16 Arithmetic right shift by immediate (36-bit, sign filled in); 2-cycle, 2-word. aD = aS >> arM Arithmetic right shift by arM (36-bit, sign filled in); 1-cycle.

> aS Arithmetic right shift by aS (36-bit, sign filled in); 2-cycle.

aD = aS >>> IM16 Logical right shift by immediate (32-bit shift, 0s filled in); 2-cycle, 2-word. aD = aS >>> arM Logical right shift by arM (32-bit shift, 0s filled in); 1-cycle.

>> aS Logical right shift by aS (32-bit shift, 0s filled in); 2-cycle.

aD = aS << IM16 Arithmetic left shift† by immediate (36-bit shift, 0s filled in); 2-cycle, 2-word. aD = aS << arM Arithmetic left shift† by arM (36-bit shift, 0s filled in); 1-cycle. aD = aS << aS Arithmetic left shift† by aS (36-bit shift, 0s filled in); 2-cycle. aD = aS <<< IM16 Logical left shift by immediate (36-bit shift, 0s filled in); 2-cycle, 2-word. aD = aS <<< arM Logical left shift by arM (36-bit shift, 0s filled in); 1-cycle. <<< aS Logical left shift by aS (36-bit shift, 0s filled in); 2-cycle. † Not the same as the special function arithmetic left shift. Here, the guard bits in the destination accumulator are shifted into, not sign-extended. aD = exp(aS) Detect the number of redundant sign bits in accumulator; 1-cycle. aD = norm(aS, arM) Normalize aS with respect to bit 31, with exponent in arM; 1-cycle. aD = extracts(aS, IM16) Extraction with sign extension, field specified as immediate; 2-cycle, 2-word. aD = extracts(aS, arM) Extraction with sign extension, field specified in arM; 1-cycle. aD = extractz(aS, IM16) Extraction with zero extension, field specified as immediate; 2-cycle, 2-word. aD = extractz(aS, arM) Extraction with zero extension, field specified in arM; 1-cycle. aD = insert(aS, IM16) Bit field insertion, field specified as immediate; 2-cycle, 2-word. aD = insert(aS, arM) Bit field insertion, field specified in arM; 2-cycle. of the operand (immediate or arM), and the offset from the LSB is in the lower byte. aD = aS:aa0 Shuffle accumulators with alternate accumulator 0 (aa0); 1-cycle. aD = aS:aa1 Shuffle accumulators with alternate accumulator 1 (aa1); 1-cycle. Note:The alternate accumulator gets what was in aS. aD gets what was in the alternate accumulator. Table 19. Replacement Table for F3 ALU Instructions and F4 BMU Instructions aD, aT , aS a0 or a1 One of the two accumulators. IM16 immediate 16-bit data, sign-, zero-, or one-extended as appropriate. arM ar<0—3> One of the auxiliary BMU registers.

register. K is encoded as 0 in the instruction encoding to select cloop.

1. In the first pass, the instructions are fetched from program memory and the cycle times are the normal out-of-

cache values, except for the last instruction in the block of NI instructions. This instruction executes in two cycles.

1. During pass two through pass K – 1, each instruction is fetched from cache and the in-cache timings apply.
2. During the last (Kth) pass, the block of instructions is fetched from cache and the in-cache timings apply, except

that the timing of the last instruction is the same as if it were out-of-cache.

1. If any of the instructions access external memory, programmed wait-states must be added to the cycle counts.

The redo instruction treats the instructions currently in the cache memory as another loop to be executed K times. Using the redo instruction, instructions are reexecuted from the cache without reloading the cache. value of cloop is decremented to 0; hence, cloop needs to be written before each do cloop or redo cloop. Table 20. Replacement Table for Cache Instructions 1 to 127 Number of times the instructions to be executed is encoded in the instruction. N 1 to 15 1 to 15 instructions can be included.

sioc, sioc2, tdms, tdms2, srta, and srta2 registers are not readable. 16 bits wide are read, their contents are zero-extended to 16 bits. Loading an accumulator with a data move instruction does not affect the flags. Table 21. Replacement Table for Data Move Instructions Subset of registers accessible with direct addressing. aS, aT a0, a1 High half of accumulator. Y *rM, *rM++, *rM--, *rM++j Same as in multiply/ALU instructions. Z *rMzp, *rMpz, *rMm2, *rMjk Same as in multiply/ALU instructions. IM16 16-bit value Long immediate data. IM9 9-bit value Short immediate data for YAAU registers. SR r<0—3>, rb, re, j, k Subset of registers for short immediate.

5.2 Register Settings

Table 22. Serial I/O Control Registers

• See tdms register, SYNC field.

† See tdms register, SYNC field. ‡ The bit definitions of the sioc2 register are identical to the sioc register bit definitions. DO changes on the rising edge of OCK. time on DO by half a cycle of OCK. In active mode, ILD1 and/or OLD1 = ICK1/16, active SYNC1 = ICK1/[128/256*]. In active mode, ILD1 and/or OLD1 = OCK1/16, active SYNC1 = OCK1/[128/256*]. OLD1 is an input (passive mode). OLD1 is an output (active mode). ILD1 is an input (passive mode). ILD1 is an output (active mode). OCK1 is an input (passive mode). OCK1 is an output (active mode). ICK1 is an input (passive mode). ICK1 is an output (active mode).

Table 23. Time-Division Multiplex Slot Registers † See sioc register, LD field. ‡ Select this mode when in multiprocessor mode. § The tdms2 register bit definitions are identical to the tdms register bit definitions.

• See sioc register, LD field.

‡ Select this mode when in multiprocessor mode. MODE 0 Multiprocessor mode off; DOEN1 is an input (passive mode). 1 Multiprocessor mode on; DOEN1 is an output (active mode). TRANSMIT SLOT 1xxxxxx Transmit slot 7. SYNC 1 Transmit slot 0, SYNC1 is an output (active mode). 0 SYNC1 is an input (passive mode).

Table 24. Serial Receive/Transmit Address Registers † The srta2 field definitions are identical to the srta register field definitions. Table 25. Multiprocessor Protocol Registers ‡ The saddx2 field definitions are identical to the saddx register field definitions. RECEIVE ADDRESS 1xxxxxxx Receive address 7. TRANSMIT ADDRESS 1xxxxxxx Transmit address 7. x1xxxxxx Transmit address 6. xx1xxxxx Transmit address 5. xxx1xxxx Transmit address 4. xxxx1xxx Transmit address 3. xxxxx1xx Transmit address 2. xxxxxx1x Transmit address 1. xxxxxxx1 Transmit address 0.

compatible with future chip versions. The auc register is cleared at reset. Table 26. Processor Status Word (psw) Register

• The DAU flags can be set by either BMU or DAU operations.

Wxxx LMI — logical minus when set (bit 35 = 1). xWxx LEQ — logical equal when set (bit [35:0] = 0). xxWx LLV — logical overflow when set. xxxW LMV — mathematical overflow when set. a1[V] W Accumulator 1 (a1) overflow when set. a1[35:32] Wxxx Accumulator 1 (a1) bit 35. xWxx Accumulator 1 (a1) bit 34. xxWx Accumulator 1 (a1) bit 33. xxxW Accumulator 1 (a1) bit 32. a0[V] W Accumulator 0 (a0) overflow when set. a0[35:32] Wxxx Accumulator 0 (a0) bit 35. xWxx Accumulator 0 (a0) bit 34. xxWx Accumulator 0 (a0) bit 33. xxxW Accumulator 0 (a0) bit 32. Table 27. Arithmetic Unit Control (auc) Register only outside an interrupt service routine. PSG never reset by writing the pi register. ter, allowing single-cycle squaring with p = x * y. CLR 1xx Clearing yl is disabled (enabled when 0). x1x Clearing a1l is disabled (enabled when 0). xx1 Clearing a0l is disabled (enabled when 0). SA T 1x a1 saturation on overflow is disabled (enabled when 0). x1 a0 saturation on overflow is disabled (enabled when 0). 10 a0, a1 ← p x 4 (and zeros written to the two LSBs). 11 a0, a1 ← p x 2 (and zero written to the LSB).

Encoding: A 0 disables an interrupt; a 1 enables an interrupt. Encoding: A 0 indicates no interrupt. A 1 indicates an interrupt has been recognized and is pending or being serviced. If a 1 is written to bits 4, 5, or 8 of ins, the corresponding interrupt is cleared. Table 28. Parallel Host Interface Control (phifc) Register Intel protocol: PIDS and PODS data strobes. Motorola protocol: PRWN and PDS data strobes. When PSTROBE = 1, PODS pin (PDS) active-low. When PSTROBE = 1, PODS pin (PDS) active-high. In either mode, PBSEL pin = 0 → pdx0 low byte. See Table 7. If PMODE = 0, PBSEL pin = 1 → pdx0 low byte. If PMODE = 1, PBSEL pin = 0 → pdx0 high byte. PIBF and POBE pins active-high. PIBF and POBE pins active-low. changed (output buffer empty). POBE flag as read through PSTAT register is active-low. Table 29. Interrupt Control (inc) Register

• JINT is a JTAG interrupt and is controlled by the HDS. It may be made unmaskable by the Lucent Technologies development system tools.

Table 30. Interrupt Status (ins) Register

Table 31. timerc Register Timer and prescaler disabled. The period register and timer0 are not reset. Timer stops after counting down to 0. Timer automatically reloads and repeats indefinitely.

0000 CKO/2 1000 CKO/512

0001 CKO/4 1001 CKO/1024

0010 CKO/8 1010 CKO/2048

0011 CKO/16 1011 CKO/4096

0100 CKO/32 1100 CKO/8192

0101 CKO/64 1101 CKO/16384

0110 CKO/128 1110 CKO/32768

0111 CKO/256 1111 CKO/65536

Table 32. Phase-Locked Loop Control (pllc) Register DSP internal clock taken directly from CKI. DSP internal clock taken from PLL. ICP — Charge pump current selection (see Table 64 for proper value). 3 V operation (see Table 64 for proper value). 5 V operation (see Table 64 for proper value). LF[3:0] — Loop filter setting (see Table 64 for proper value). INTERNAL CLOCK = fCKI x (M/(2N)).

Table 33. sbit Register DIREC 1xxxxxxx IOBIT7 is an output (input when 0). x1xxxxxx IOBIT6 is an output (input when 0). xx1xxxxx IOBIT5 is an output (input when 0). xxx1xxxx IOBIT4 is an output (input when 0). xxxx1xxx IOBIT3 is an output (input when 0). xxxxx1xx IOBIT2 is an output (input when 0). xxxxxx1x IOBIT1 is an output (input when 0). xxxxxxx1 IOBIT0 is an output (input when 0). VALUE Rxxxxxxx Reads the current value of IOBIT7. xRxxxxxx Reads the current value of IOBIT6. xxRxxxxx Reads the current value of IOBIT5. xxxRxxxx Reads the current value of IOBIT4. xxxxRxxx Reads the current value of IOBIT3. xxxxxRxx Reads the current value of IOBIT2. xxxxxxRx Reads the current value of IOBIT1. xxxxxxxR Reads the current value of IOBIT0. Table 34. cbit Register

external memory). Otherwise, the mwait register is initialized to all 0s (0 wait-states) upon reset. Table 35. alf Register Power-saving standby mode or standard sleep enabled. The internal DPRAM is addressed beginning at 0x0000 in X space. The internal DPRAM is addressed beginning at 0xc000 in X space. Table 36. mwait Register Table 37. DSP1627 32-Bit JTAG ID Register Small-signal input clock option. Crystal oscillator input clock option. CMOS level input clock option. P ART ID 0x1C DSP1627x36 with 36K IROM and no EROM in MAP1 or MAP3. 0x2C DSP1627x32 with 32K IROM and 16K EROM in MAP1 and MAP3.

Table 38. ioc Register*

• The field definitions for the ioc register are different from the DSP1610.

EXTROM If 1, sets AB15 low during external memory accesses when WEROM = 1. CKO2 CKO configuration (see below). EBIOH If 1, enables high half of BIO, IOBIT[4:7], and disables VEC[3:0] from pins. WEROM If 1, allows writing into external program (X) memory. ESIO2 If 1, enables SIO2 and low half of BIO, and disables PHIF from pins. SIOLBC If 1, DO1 and DO2 looped back to DI1 and DI2. CKO[1:0] CKO configuration (see below). 0 0 0 CKI CKI x M/(2N) Free-running clock.

• The phase of CKI is synchronized by the rising edge of RSTB.

† When SLOWCKI is enabled in the powerc register, these options reflect the low-speed internal ring oscillator. sequenced external memory accesses, it completes one cycle. mwait register setting (see Table 36). 1 0 0 CKI CKI Output of CKI buffer.

Table 39. powerc Register Note: The reserved (RSVD) bits should always be written with zeros to make the program compatible with future chip versions. † If EXM is high and INT1 is low when RSTB goes high, mwait will contain all ones instead of all zeros. The powerc register configures various power management modes. XTLOFF 1 = powerdown crystal oscillator or small-signal clock input. SLOWCKI 1 = select ring oscillator clock (internal slow clock). NOCK 1 = disable internal processor clock. INT0EN 1 = INT0 clears NOCK field. INT1EN 1 = INT1 clears NOCK field. Table 40. Register Settings After Reset

March 2000 DSP1627 Digital Signal Processor Lucent Technologies Inc. 55

5.3 Instruction Set Formats

This section defines the hardware-level encoding of the DSP1627 device instructions. Multiply/ALU Instructions Special Function Instructions Format 1: Multiply/ALU Read/Write Group Field TD S F 1 X Y Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1a: Multiply/ALU Read/Write Group Field Ta T S F 1 X Y Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 2: Multiply/ALU Read/Write Group Field TD S F 1 X Y Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 2a: Multiply/ALU Read/Write Group Field Ta T S F 1 X Y Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 3: F2 ALU Special Functions Field TD S F 2 C O N Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 3a: F3 ALU Operations Field T D S F3 SRC2 aT 0 1 Immediate Operand (IM16) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 3b: BMU Operations Field T D S F4[3—1] 0 F4[0] AR Immediate Operand (IM16) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DSP1627 Digital Signal Processor March 2000 56 Lucent Technologies Inc. Note: A branch instruction immediately follows except for a software interrupt (icall). Data Move Instructions Cache Instructions Format 4: Branch Direct Group Field TJ A Bit 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Format 5: Branch Indirect Group Field TB R e s e r v e d 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 6: Conditional Branch Qualifier/Software Interrupt (icall) Field T SI Reserved CON Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 7: Data Move Group Field Ta T R Y / Z Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 8: Data Move (immediate operand—2 words) Field T D R Reserved Immediate Operand (IM16) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 9: Short Immediate Group Field T I Short Immediate Operand (IM9) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 9a: Direct Addressing Field T R/W DR 1 OFFSET Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 10: Do/Redo Field TN I K Bit 1 5 1 4 1 3 1 2 1 1 1 0 9876543210

Table 41. T Field Table 42. D Field Table 43. aT Field Table 44. S Field Table 45. F1 Field Table 46. X Field Specifies the type of instruction.

00010 Short imm j, k, rb, re 9

00011 Short imm r0, r1, r2, r3 9

00100 Y = a1[l] F1 1

00101 Z : aT[l] F1 2a

00110 Y F1 1

01000 Bit 0 = 0, aT = R 7

01000 Bit 0 = 1, aTl = R 7

01001 Bit 10 = 0, R = a0 7

01001 Bit 10 = 1, R = a0l 7

01010 R = IM16 8

01011 Bit 10 = 0, R = a1 7

01011 Bit 10 = 1, R = a1l 7

01100 Y = R 7

01101 Z : R 7

01111 R = Y 7

10100 Y = y[l] F1 1

10101 Z : y[l] F1 2

11000 Bit 0 = 0, branch indirect 5

11000 Bit 0 = 1, F3 ALU 3a

11100 Y = a0[l] F1 1

11101 Z : y x = X F1 2

11110 Bit 5 = 0, F4 ALU (BMU) 3b

11110 Bit 5 = 1, direct addressing 9a

Specifies a destination accumulator.

0 Accumulator 0

1 Accumulator 1

Specifies transfer accumulator.

0 Accumulator 1

1 Accumulator 0

Specifies a source accumulator. Specifies the multiply/ALU function.

Table 47. Y Field Table 48. Z Field Table 49. F2 Field Table 50. CON Field dressing with postmodification. Specifies the special function to be performed. tional control instructions.

Table 51. R Field Table 52. B Field Table 54. I Field Table 55. SI Field Specifies the register for data move instructions.

001111 Reserved 101111 Reserved

011110 Reserved 111110 Reserved

Table 53. DR Field

0 Not a software interrupt

1 Software interrupt

executed. Zero specifies use of value in cloop register. A zero specifies a write, *(O) = DR. A one specifies a read, DR = *(O). Table 56. F3 Field Table 57. SRC2 Field Specifies the operation in an F3 ALU instruction. Specifies operands in an F3 ALU instruction. Table 58. BMU Encodings

6 Signal Descriptions

Figure 8. DSP1627 Pinout by Interface

6.1 System Interface

and reset signals for the processor. Reset clears IACK, VEC[3:0]/IOBIT[4:7], IBF, and IBF2. The DAU condition flags are not affected by reset. (see Section 4.4, Memory Maps and Wait-States).

DSP1627 Digital Signal Processor March 2000 62 Lucent Technologies Inc.

6 Signal Descriptions (continued)

Input Clock: A mask-programmable option selects one of three possible input buffers for the CKI pin (see Sec- tion 7, Mask-Programmable Options, and Table 1, Pin Descriptions). The internal CKI from the output of the selected input buffer can then drive the internal proces- sor clock directly (1X) or drive the on-chip PLL (see Sec- tion 4.13). The PLL allows the CKI input clock to be at a lower frequency than the internal processor clock. CKI2 Input Clock 2: Used with mask-programmable input clock options which require an external crystal or small signal differential across CKI and CKI2 (see Table 1, Pin Descriptions). When the CMOS option is selected, this pin should be tied to V SSA . STOP Stop Input Clock: Negative assertion. A high-to-low transition synchronously stops all of the internal proces- sor clocks leaving the processor in a defined state. Re- turning the pin high will synchronously restart the processor clocks to continue program execution from where it left off without any loss of state. This hardware feature has the same effect as setting the NOCK bit in the powerc register (see Table 39). CKO Clock Out: Buffered output clock with options program- mable via the ioc register (see Table 38). The selectable CKO options (see Tables 38 and 29) are as follows: ■ A free-running output clock at the frequency of the in- ternal processor clock; runs at the internal ring oscilla- tor frequency when SLOWCKI is enabled. ■ A wait-stated clock based on the internal instruction cy- cle; runs at the internal ring oscillator frequency when SLOWCKI is enabled. ■ A sequenced, wait-stated clock based on the EMI se- quencer cycle; runs at the internal ring oscillator fre- quency when SLOWCKI is enabled. ■ A free-running output clock that runs at the CKI rate, in- dependent of the powerc register setting. This option is only available with the crystal and small-signal clock options. When the PLL is selected, the CKO frequency equals the input CKI frequency regardless of how the PLL is programmed. ■ A logic 0. ■ A logic 1. INT[1:0] Processor Interrupts 0 and 1: Positive assertion. Hardware interrupt inputs to the DSP1627. Each is en- abled via the inc register. When enabled and asserted, each cause the processor to vector to the memory loca- tion described in Table 4. INT1 is used in conjunction with EXM to select the desired reset initialization of the mwait register (see Table 36). When both INT0 and RSTB are asserted, all output and bidirectional pins (ex- cept TDO, which 3-states by JTAG control) are put in a 3-state condition. VEC[3:0] Interrupt Output Vector: These four pins indicate which interrupt is currently being serviced by the device. Table 4 shows the code associated with each interrupt condition. VEC[3:0] are multiplexed with IOBIT[4:7]. IACK Interrupt Acknowledge: Positive assertion. IACK signals when an interrupt is being serviced by the DSP1627. IACK remains asserted while in an interrupt service routine, and is cleared when the ireturn instruc- tion is executed. TRAP Trap Signal: Positive assertion. When asserted, the processor is put into the trap condition, which normally causes a branch to the location 0x0046. The hardware development system (HDS) can configure the trap pin to cause an HDS trap, which causes a branch to loca- tion 0x0003. Although normally an input, the pin can be configured as an output by the HDS. As an output, the pin can be used to signal an HDS breakpoint in a multi- ple processor environment.

March 2000 DSP1627 Digital Signal Processor Lucent Technologies Inc. 63

6.2 External Memory Interface

The external memory interface is used to interface the DSP1627 to external memory and I/O devices. It sup- ports read/write operations from/to program and data memory spaces. The interface supports four external memory segments. Each external memory segment can have an independent number of software-program- mable wait-states. One hardware address is decoded, and an enable line is provided, to allow glueless I/O in- terfacing. AB[15:0] External Memory Address Bus: Output only. This 16-bit bus supplies the address for read or write operations to the external memory or I/O. During exter- nal memory accesses, AB[15:0] retain the value of the last valid external access. DB[15:0] External Memory Data Bus: This 16-bit bidirectional data bus is used for read or write operations to the ex- ternal memory or I/O. RWN Read/Write Not: When a logic 1, the pin indicates that the memory access is a read operation. When a logic 0, the memory access is a write operation. EXM External Memory Select: Input only. This signal is latched into the device on the rising edge of RSTB. The value of EXM latched in determines whether the internal ROM is addressable in the instruction/coefficient mem- ory map. If EXM is low, internal ROM is addressable. If EXM is high, only external ROM is addressable in the instruction/coefficient memory map (see Table 5, In- struction/Coefficient Memory Maps). EXM chooses be- tween MAP1 or MAP2 and between MAP3 or MAP4. EROM External ROM Enable Signal: Negative assertion. When asserted, the signal indicates an access to external program memory (see Table 5, Instruction/Co- efficient Memory Maps). This signal's leading edge can be delayed via the ioc register (see Table 38). ERAMHI External RAM High Enable Signal: Negative asser- tion. When asserted, the signal indicates an access to external data memory addresses 0x8000 through 0xFFFF (see Table 6, Data Memory Map). This signal's leading edge can be delayed via the ioc register (see Table 38). ERAMLO External RAM Low Enable Signal: Negative asser- tion. When asserted, the signal indicates an access to external data memory addresses 0x4100 through 0x7FFF (see Table 6, Data Memory Map). This signal's leading edge can be delayed via the ioc register (see Table 38). IO External I/O Enable Signal: Negative assertion. When asserted, the signal indicates an access to external data memory addresses 0x4000 through 0x40FF (see Table 6, Data Memory Map). This memory segment is intended for memory-mapped I/O. This signal's leading edge can be delayed via the ioc register (see Table 38).

DSP1627 Digital Signal Processor March 2000 64 Lucent Technologies Inc.

6.3 Serial Interface #1

The serial interface pins implement a full-featured syn- chronous/asynchronous serial I/O channel. In addition, several pins offer a glueless TDM interface for multipro- cessing communication applications (see Figure 5, Mul- tiprocessor Communications and Connections). DI1 Data Input: Serial data is latched on the rising edge of ICK1, either LSB or MSB first, according to the sioc reg- ister MSB field (see Table 22). ICK1 Input Clock: The clock for serial input data. In active mode, ICK1 is an output; in passive mode, ICK1 is an input, according to the sioc register ICK field (see Table 22). Input has typically 0.7 V hysteresis. ILD1 Input Load: The clock for loading the input buffer, sdx[in], from the input shift register isr. A falling edge of ILD1 indicates the beginning of a serial input word. In active mode, ILD1 is an output; in passive mode, ILD1 is an input, according to the sioc register ILD field (see Table 22). Input has typically 0.7 V hysteresis. IBF1 Input Buffer Full: Positive assertion. IBF1 is asserted when the input buffer, sdx[in], is filled. IBF1 is negated by a read of the buffer, as in a0 = sdx. IBF1 is also ne- gated by asserting RSTB. DO1 Data Output: The serial data output from the output shift register (osr), either LSB or MSB first (according to the sioc register MSB field). DO1 changes on the rising edges of OCK1. DO1 is 3-stated when DOEN1 is high. DOEN1 Data Output Enable: Negative assertion. An input when not in the multiprocessor mode. DO1 and SADD1 are enabled only if DOEN1 is low. DOEN1 is bidirection- al when in the multiprocessor mode (tdms register MODE field set). In the multiprocessor mode, DOEN1 indicates a valid time slot for a serial output. OCK1 Output Clock: The clock for serial output data. In active mode, OCK1 is an output; in passive mode, OCK1 is an input, according to the sioc register OCK field (see Ta- ble 22). Input has typically 0.7 V hysteresis. OLD1 Output Load: The clock for loading the output shift reg- ister, osr, from the output buffer sdx[out]. A falling edge of OLD1 indicates the beginning of a serial output word. In active mode, OLD1 is an output; in passive, OLD1 is an input, according to the sioc register OLD field (see Table 22). Input has typically 0.7 V hysteresis. OBE1 Output Buffer Empty: Positive assertion. OBE1 is as- serted when the output buffer, sdx[out], is emptied (moved to the output shift register for transmission). It is cleared with a write to the buffer, as in sdx = a0. OBE1 is also set by asserting RSTB. SADD1 Serial Address: Negative assertion. A 16-bit serial bit stream typically used for addressing during multiproces- sor communication between multiple DSP16xx devices. In multiprocessor mode, SADD1 is an output when the tdms time slot dictates a serial transmission; otherwise, it is an input. Both the source and destination DSP can be identified in the transmission. SADD1 is always an output when not in multiprocessor mode and can be used as a second 16-bit serial output. See the DSP1611/17/18/27 Digital Signal Processor Informa- tion Manual for additional information. SADD1 is 3-stat- ed when DOEN1 is high. When used on a bus, SADD1 should be pulled high through a 5 kΩ resistor. SYNC1 Multiprocessor Synchronization: Typically used in the multiprocessor mode, a falling edge of SYNC1 indi- cates the first word (time slot 0) of a TDM I/O stream and causes the resynchronization of the active ILD1 and OLD1 generators. SYNC1 is an output when the tdms register SYNC field is set (i.e., selects the master DSP and uses time slot 0 for transmit). As an input, SYNC1 must be tied low unless part of a TDM interface. When used as an output, SYNC1 = [ILD1/OLD1]/8 or 16, depending on the setting of the SYNCSP field of the tdms register. When configured as described above, SYNC1 can be used to generate a slow clock for SIO operations. Input has typically 0.7 V hysteresis.

March 2000 DSP1627 Digital Signal Processor Lucent Technologies Inc. 65

6.4 Parallel Host Interface or Serial Interface

#2 and Control I/O Interface This interface pin multiplexes a parallel host interface with a second serial I/O interface and a 4-bit I/O inter- face. The interface selection is made by writing the ESIO2 bit in the ioc register (see Table 38 and Section 4.1). The functions and signals for the second SIO correspond exactly with those in SIO #1. Therefore, the pin descriptions below discuss only PHIF and BIO pin functionality. PB[7:0] Parallel I/O Data Bus: This 8-bit bidirectional bus is used to input data to, or output data from, the PHIF. Note that PB[3:0] are pin multiplexed with SIO2 func- tionality, and PB[7:4] are pin multiplexed with BIO unit pins IOBIT[3:0] (see Section 4.1). PCSN Peripheral Chip Select Not: Negative assertion. PCSN is an input. While PCSN is low, the data strobes PIDS and PODS are enabled. While PCSN is high, the DSP1627 ignores any activity on PIDS and PODS. PBSEL Peripheral Byte Select: An input pin, configurable in software. Selects the high or low byte of pdx0 available for host accesses. PSTAT Peripheral Status Select: PSTAT is an input. When a logic 0, the PHIF will output the pdx0[out] register on the PB bus. When a logic 1, the PHIF will output the con- tents of the PSTAT register on PB[7:0]. PIDS Parallel Input Data Strobe: An input pin, software con- figurable to support both Intel and Motorola protocols. In Intel mode: Negative assertion. PIDS is pulled low by an external device to indicate that data is available on the PB bus. The DSP latches data on the PB bus on the rising edge (low-to-high transition) of PIDS or PCSN, whichever comes first. In Motorola mode: PIDS(PRWN*) functions as a read/ write strobe. The external device sets PIDS(PRWN*) to a logic 0 to indicate that data is available on the PB bus (write operation by the external device). A logic 1 on PIDS(PRWN*) indicates an external read operation by the external device. PODS Parallel Output Data Strobe: An input pin, software configurable to support both Intel and Motorola proto- cols. In Intel mode: Negative assertion. When PODS is pulled low by an external device, the DSP1627 places the con- tents of the parallel output register, pdx0, onto the PB bus. In Motorola mode: Software-configurable assertion level. The external device uses PODS(PDS*) as its data strobe for both read and write operations. PIBF Parallel Input Buffer Full: An output pin with positive assertion; configurable in software. This flag is cleared after reset, indicating an empty input buffer pdx0[in]. PIBF is set immediately after the rising edge of PIDS or PCSN, indicating that data has been latched into the pdx0[in] register. When the DSP1627 reads the con- tents of this register, emptying the buffer, the flag is cleared. Configured in software, PIBF may become the logical OR of the PIBF and POBE flags. POBE Parallel Output Buffer Empty: An output pin with pos- itive assertion; configurable in software. This flag is set after reset, indicating an empty output buffer pdx0[out]. POBE is set immediately after the rising edge of PODS or PCSN, indicating that the data in pdx0[out] has been driven onto the PB bus. When the DSP1627 writes to pdx0[out], filling the buffer, this flag is cleared.

6.5 Control I/O Interface

This interface is used for status and control operations provided by the bit I/O unit of the DSP1627. It is pin mul- tiplexed with the PHIF and VEC[3:0] pins (see Section 4.1). Setting the ESIO2 and EBIOH bits in the ioc regis- ter provides a full 8-bit BIO interface at the associated pins. IOBIT[7:0] I/O Bits [7:0]: Each of these bits can be independently configured as either an input or an output. As outputs, they can be independently set, toggled, or cleared. As inputs, they can be tested independently or in combina- tions for various data patterns. * Motorola mode signal name.

DSP1627 Digital Signal Processor March 2000 66 Lucent Technologies Inc.

6.6 JTAG Test Interface

The JTAG test interface has features that allow pro- grams and data to be downloaded into the DSP via four pins. This provides extensive test and diagnostic capa- bility. In addition, internal circuitry allows the device to be controlled through the JTAG port to provide on-chip in-circuit emulation. Lucent Technologies provides hardware and software tools to interface to the on-chip HDS via the JTAG port. Note:The DSP1627 provides all JTAG/ IEEE 1149.1 standard test capabilities including boundary scan. See the DSP1611/17/18/27 Digital Signal Processor Information Manual for additional in- formation on the JTAG test interface. TDI Test Data Input: JTAG serial input signal. All serial- scanned data and instructions are input on this pin. This pin has an internal pull-up resistor. TDO Test Data Output: JTAG serial output signal. Serial- scanned data and status bits are output on this pin. TMS Test Mode Select: JTAG mode control signal that, when combined with TCK, controls the scan operations. This pin has an internal pull-up resistor. TCK Test Clock: JTAG serial shift clock. This signal clocks all data into the port through TDI, and out of the port through TDO, and controls the port by latching the TMS signal inside the state-machine controller.

7 Mask-Programmable Options

memory map option, and the hardware emulation or ROM security option, as summarized in Table 59.

7.1 Input Clock Options

CKI frequency is the internal clock frequency. buffer by supplying a CMOS level to the CKI pin and leaving the CKI2 pin open.

7.2 Memory Map Options

7.3 ROM Security Options

DSP1600 Support Tools Manual for more detailed information. Table 59. DSP1627 ROM Options 36 Kwords IROM, no EROM in MAP1 or MAP3. 32 Kwords IROM, 16 Kwords EROM in MAP1 and MAP3. Specify and link crc16.v#†, no emulation capability. and must reside in the first 4 Kwords of ROM. of ROM. See the DSP1600 Support Tools Manual for detailed information.

8 Device Characteristics

8.1 Absolute Maximum Ratings

periods can adversely affect device reliability. External leads can be bonded and soldered safely at temperatures of up to 300 °C.

8.2 Handling Precautions

1500 Ω are the most common and are the values used in the Lucent Technologies human-body model test circuit. The breakdown voltage for the DSP1627 is greater than 2000 V.

8.3 Recommended Operating Conditions

Table 60. Recommended Operating Conditions

March 2000 DSP1627 Digital Signal Processor Lucent Technologies Inc. 69

8 Device Characteristics (continued)

8.4 Package Thermal Considerations

The recommended operating temperature specified above is based on the maximum power, package type, and maximum junction temperature. The following equations describe the relationship between these parameters. If the applications' maximum power is less than the worst-case value, this relationship determines a higher maximum am- bient temperature or the maximum temperature measured at top dead center of the package. T A = TJ – P x Θ JA TTDC = TJ – P x Θ J-TDC where TA is the still-air ambient temperature and TTDC is the temperature measured by a thermocouple at the top dead center of the package. WARNING: Due to package thermal constraints, proper precautions in the user's application should be tak- en to avoid exceeding the maximum junction temperature of 125 °C. Otherwise, the device will be affected adversely.

9 Electrical Characteristics and Requirements

Recommended Operating Conditions. Table 61. Electrical Characteristics and Requirements Table 62. Electrical Requirements for Mask-Programmable Input Clock Options imately equal to the average value of CKI is applied to CKI2, as shown in the figure below. The maximum allowable ripple on CKI2 is 100 mV. † Duty cycle for a sine wave is defined as the percentage of time during each clock cycle that the voltage on CKI exceeds the voltage on CKI2.

9 Electrical Characteristics and Requirements (continued)

Table 63. PLL Electrical Specifications, VCO Frequency Ranges fINTERNAL CLOCK = fCKI x (M/(2N)) = fVCO /2. Table 64. PLL Electrical Specifications and pllc Register Settings indicated by assertion of the LOCK flag.

75 V ± 5% 1 1 0111 30

Figure 9. Plot of VOH vs. IOH Under Typical Operating Conditions Figure 10. Plot of VOL vs. IOL Under Typical Operating Conditions

9.1 Power Dissipation

• T = CKI clock cycle for 1X input clock option or T = CKI clock cycle divided by M/(2N) for PLL clock option (see Section 4.12).

† tL = PLL lock time (see Table 64). Table 65. Power Dissipation and Wake-Up Latency

5 V 3 V 5 V 3 V 5 V 3 V 5 V 3 V

• T = CKI clock cycle for 1X input clock option or T = CKI clock cycle divided by M/(2N) for PLL clock option (see Section 4.12).

† tL = PLL lock time (see Table 64). Table 65. Power Dissipation and Wake-Up Latency (continued)

March 2000 DSP1627 Digital Signal Processor Lucent Technologies Inc. 75 Power dissipation due to the input buffers is highly dependent on the input voltage level. At full CMOS levels, es- sentially no dc current is drawn. However, for levels between the power supply rails, especially at or near the thresh- old of V DD /2, high currents can flow. Although input and I/O buffers may be left untied (since the input voltage levels of the input and I/O buffers are designed to remain at full CMOS levels when not driven by the DSP), it is still rec- ommended that unused input and I/O pins be tied to V SS or VDD through a 10 kΩ resistor to avoid application am- biguities. Further, if I/O pins are tied high or low, they should be pulled fully to VSS or VDD . WARNING: The device needs to be clocked for at least six CKI cycles during reset after powerup. Otherwise, high currents may flow.

10 Timing Characteristics for 5 V Operation

The following timing characteristics and requirements are preliminary information and are subject to change. Timing characteristics refer to the behavior of the device under specified conditions. Timing requirements refer to conditions imposed on the user for proper operation of the device. All timing data is valid for the following conditions: T A = –40 °C to +85 °C (See Section 8.3.) VDD = 5 V ± 5%, VSS = 0 V (See Section 8.3.) Capacitance load on outputs (CL) = 50 pF, except for CKO, where CL = 20 pF. Output characteristics can be derated as a function of load capacitance (CL). All outputs: 0.03 ns/pF ≤ dt/dCL ≤ 0.06 ns/pF for 10 ≤ CL ≤ 100 pF at VIH for rising edge and at VIL for falling edge. For example, if the actual load capacitance is 30 pF instead of 50 pF, the derating for a rising edge is (30 – 50) pF x 0.06 ns/pF = 1.2 ns less than the specified rise time or delay that includes a rise time. Test conditions for inputs: ■ Rise and fall times of 4 ns or less ■ Timing reference levels for delays = VIH, VIL Test conditions for outputs (unless noted otherwise): ■ C LOAD = 50 pF; except for CKO, where CLOAD = 20 pF ■ Timing reference levels for delays = VIH, VIL ■ 3-state delays measured to the high-impedance state of the output driver For the timing diagrams, see Table 62 for input clock requirements. Unless otherwise noted, CKO in the timing diagrams is the free-running CKO.

10 Timing Characteristics for 5 V Operation (continued)

10.1 DSP Clock Generation

• See Table 62 for input clock electrical requirements.

‡ Wait-stated clock (see Table 38). § W = number of wait-states. Figure 11. I/O Clock Timing Diagram

• Device speeds greater than 50 MIPS do not support 1X operation. Use the PLL.

† Device is fully static, t1 is tested at 100 ns for 1X input clock option, and memory hold time is tested at 0.1 s.

• T = internal clock period, set by CKI or by CKI and the PLL parameters.

Table 66. Timing Requirements for Input Clock Table 67. Timing Characteristics for Input Clock and Output Clock

10.2 Reset Circuit

• See Table 60, Recommended Operating Condiitons.

See Table 62 for CKI electrical requirements and Table 71 for TCK timing requirements. TMS and TDI signals have internal pull-up devices. Figure 12. Powerup Reset and Chip Reset Timing Diagram

• With external components as specified in Table 62.

†T TCK = t12 = TCK period. See Table 71 for TCK timing requirements. Table 68. Timing Requirements for Powerup Reset and Chip Reset

10.3 Reset Synchronization

• See Table 62 for input clock electrical requirements.

Note: CKO1 and CKO2 are two possible CKO states before reset. CKO is free-running. Figure 13. Reset Synchronization Timing Table 69. Timing Characteristics for Powerup Reset and Chip Reset Table 70. Timing Requirements for Reset Synchronization Timing

10.4 JTAG I/O Specifications

Figure 14. JTAG Timing Diagram Table 71. Timing Requirements for JTAG Input/Output Table 72. Timing Characteristics for JTAG Input/Output

10.5 Interrupt

† IACK assertion is guaranteed to be enclosed by VEC[3:0] assertion. Figure 15. Interrupt Timing Diagram Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts. Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts. Table 73. Timing Requirements for Interrupt Table 74. Timing Characteristics for Interrupt

10.6 Bit Input/Output (BIO)

Figure 16. Write Outputs Followed by Read Inputs (cbit = Immediate; a1 = sbit) Figure 17. Write Outputs and Test Inputs (cbit = Immediate) Table 75. Timing Requirements for BIO Input Read Table 76. Timing Characteristics for BIO Output Table 77. Timing Requirements for BIO Input Test

10.7 External Memory Interface

detailed description of the external memory interface including other functional diagrams.

• W = number of wait-states.

Figure 18. Enable Transition Timing Table 78. Timing Characteristics for External Memory Enables (EROM, ERAMHI, IO, ERAMLO) Table 79. Timing Characteristics for Delayed External Memory Enables (ioc = 0x000F)

• W = number of wait-states.

Figure 19. External Memory Data Read Timing Diagram Table 80. Timing Characteristics for External Memory Access Table 81. Timing Requirements for External Memory Read (EROM, ERAMHI, IO, ERAMLO)

• W = number of wait-states.

Figure 20. External Memory Data Write Timing Diagram Table 82. Timing Characteristics for External Memory Data Write (All Enables)

• W = number of wait-states.

Figure 21. Write Cycle Followed by Read Cycle Table 83. Timing Characteristics for Write Cycle Followed by Read Cycle

10.8 PHIF Specifications

writes are identical to one-half of a 16-bit access. Figure 22. PHIF Intel Mode Signaling (Read and Write) Timing Diagram PODS, if PIDS or PODS is the controlling signal. PODS, if PIDS or PODS is the controlling signal. Table 84. Timing Requirements for PHIF Intel Mode Signaling Table 85. Timing Characteristics for PHIF

Figure 23. PHIF Intel Mode Signaling (Pulse Period and Flags) Timing Diagram or PIDS, whichever comes first. to the inverted levels as well as those shown. Table 86. Timing Requirements for PHIF Intel Mode Signaling Table 87. Timing Characteristics for PHIF Intel Mode Signaling

Figure 24. PHIF Motorola Mode Signaling (Read and Write) Timing Diagram should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction. the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown. should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction. the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown. Table 88. Timing Requirements for PHIF Motorola Mode Signaling Table 89. Timing Characteristics for PHIF

Figure 25. PHIF Motorola Mode Signaling (Pulse Period and Flags) Timing Diagram PDS going low, if PDS goes low after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first. be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown. Table 90. Timing Characteristics for PHIF Motorola Mode Signaling Table 91. Timing Requirements for PHIF Motorola Mode Signaling

• Motorola mode signal name.

Figure 26. PHIF Intel or Motorola Mode Signaling (Status Register Read) Timing Diagram † t45, t47, and t49 are referenced to the falling edge of PCSN or PODS(PDS), whichever occurs last. ‡ t46, t48, and t50 are referenced to the rising edge of PCSN or PODS(PDS), whichever occurs first. † t45, t47, and t49 are referenced to the falling edge of PCSN or PODS(PDS), whichever occurs last. ‡ t46, t48, and t50 are referenced to the rising edge of PCSN or PODS(PDS), whichever occurs first. Table 92. Timing Requirements for Intel and Motorola Mode Signaling (Status Register Read) Table 93. Timing Characteristics for Intel and Motorola Mode Signaling (Status Register Read)

Figure 27. PHIF, PIBF, and POBE Reset Timing Diagram may later invert the definition of the logic levels for POBE and PIBF. t57 and t58 continue to apply. the same as for active-high. Figure 28. PHIF, PIBF, and POBE Disable Timing Diagram Table 94. PHIF Timing Characteristics for PHIF, PIBF, and POBE Reset Table 95. PHIF Timing Characteristics for POBE and PIBF Disable

10.9 Serial I/O Specifications

Figure 29. SIO Passive Mode Input Timing Diagram † Device is fully static; t70 is tested at 200 ns. ‡ For Multiprocessor mode, see note in Section 10.10. Table 96. Timing Requirements for Serial Inputs Table 97. Timing Characteristics for Serial Outputs

• ILD goes high during bit 6 (of 0:15), N = 8 or 16.

Figure 30. SIO Active Mode Input Timing Diagram Table 98. Timing Requirements for Serial Inputs Table 99. Timing Characteristics for Serial Outputs

Figure 31. SIO Passive Mode Output Timing Diagram † Device is fully static; t80 is tested at 200 ns. ‡ For multiprocessor mode, see note in Section 10.10. Table 100. Timing Requirements for Serial Inputs Table 101. Timing Characteristics for Serial Outputs

• OLD goes high at the end of bit 6 of 0:15.

Figure 32. SIO Active Mode Output Timing Diagram Table 102. Timing Characteristics for Serial Outputs

• See sioc register, LD field.

Figure 33. Serial I/O Active Mode Clock Timing Table 103. Timing Characteristics for Signal Generation

10.10 Multiprocessor Communication

• Negative edge initiates time slot 0.

Figure 34. SIO Multiprocessor Timing Diagram multiprocessor mode, assuming 50% duty cycle, is calculated as (t77 + t116) x 2.

• With capacitance load on ICK, OCK, DO, SYNC, and SADD = 100 pF, add 4 ns to t116—t122.

Table 104. Timing Requirements for SIO Multiprocessor Communication Table 105. Timing Characteristics for SIO Multiprocessor Communication

DSP1627 Digital Signal Processor March 2000 98 Lucent Technologies Inc. 11 Timing Characteristics for 3.0 V Operation The following timing characteristics and requirements are preliminary information and are subject to change. Timing characteristics refer to the behavior of the device under specified conditions. Timing requirements refer to conditions imposed on the user for proper operation of the device. All timing data is valid for the following conditions: T A = –40 °C to +85 °C (See Section 8.3.) VDD = 3.0 V to 3.6 V, VSS = 0 V (See Section 8.3.) Capacitance load on outputs (CL) = 50 pF, except for CKO, where CL = 20 pF. Output characteristics can be derated as a function of load capacitance (CL). All outputs: 0.03 ns/pF ≤ dt/dCL ≤ 0.07 ns/pF for 10 ≤ CL ≤ 100 pF at VIH for rising edge and at VIL for falling edge. For example, if the actual load capacitance is 30 pF instead of 50 pF, the derating for a rising edge is (30 – 50) pF x 0.06 ns/pF = 1.2 ns less than the specified rise time or delay that includes a rise time. Test conditions for inputs: ■ Rise and fall times of 4 ns or less ■ Timing reference levels for delays = VIH, VIL Test conditions for outputs (unless noted otherwise): ■ C LOAD = 50 pF; except for CKO, where CLOAD = 20 pF ■ Timing reference levels for delays = VIH, VIL ■ 3-state delays measured to the high-impedance state of the output driver For the timing diagrams, see Table 62 for input clock requirements. Unless otherwise noted, CKO in the timing diagrams is the free-running CKO.

11.1 DSP Clock Generation

• See Table 62 for input clock electrical requirements.

‡ Wait-stated clock (see Table 38). § W = number of wait-states. Figure 35. I/O Clock Timing Diagram

• Device speeds greater than 50 MIPS do not support 1X operation. Use the PLL.

† Device is fully static, t1 is tested at 100 ns for 1X input clock option, and memory hold time is tested at 0.1 s.

• T = internal clock period, set by CKI or by CKI and the PLL parameters.

Table 106. Timing Requirements for Input Clock Table 107. Timing Characteristics for Input Clock and Output Clock

100 Lucent Technologies Inc.

11.2 Reset Circuit

• See Table 60, Recommended Operating Condiitons.

See Table 62 for CKI electrical requirements and Table 151 for TCK timing requirements. TMS and TDI signals have internal pull-up devices. Figure 36. Powerup Reset and Chip Reset Timing Diagram

• With external components as specified in Table 62.

†T TCK = t12 = TCK period. See Table 151 for TCK timing requirements. Table 108. Timing Requirements for Powerup Reset and Chip Reset

11.3 Reset Synchronization

• See Table 62 for input clock electrical requirements.

Note: CKO1 and CKO2 are two possible CKO states before reset. CKO is free-running. Figure 37. Reset Synchronization Timing Table 109. Timing Characteristics for Powerup Reset and Chip Reset Table 110. Timing Requirements for Reset Synchronization Timing

102 Lucent Technologies Inc.

11.4 JTAG I/O Specifications

Figure 38. JTAG Timing Diagram Table 111. Timing Requirements for JTAG Input/Output Table 112. Timing Characteristics for JTAG Input/Output

11.5 Interrupt

† IACK assertion is guaranteed to be enclosed by VEC[3:0] assertion. Figure 39. Interrupt Timing Diagram Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts. Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts. Table 113. Timing Requirements for Interrupt Table 114. Timing Characteristics for Interrupt

104 Lucent Technologies Inc.

11.6 Bit Input/Output (BIO)

Figure 40. Write Outputs Followed by Read Inputs (cbit = Immediate; a1 = sbit) Figure 41. Write Outputs and Test Inputs (cbit = Immediate) Table 115. Timing Requirements for BIO Input Read Table 116. Timing Characteristics for BIO Output Table 117. Timing Requirements for BIO Input Test

11.7 External Memory Interface

detailed description of the external memory interface including other functional diagrams.

• W = number of wait-states.

Figure 42. Enable Transition Timing Table 118. Timing Characteristics for External Memory Enables (EROM, ERAMHI, IO, ERAMLO) Table 119. Timing Characteristics for Delayed External Memory Enables (ioc = 0x000F)

106 Lucent Technologies Inc.

• W = number of wait-states.

Figure 43. External Memory Data Read Timing Diagram Table 120. Timing Characteristics for External Memory Access Table 121. Timing Requirements for External Memory Read (EROM, ERAMHI, IO, ERAMLO)

• W = number of wait-states.

Figure 44. External Memory Data Write Timing Diagram Table 122. Timing Characteristics for External Memory Data Write (All Enables)

108 Lucent Technologies Inc.

• W = number of wait-states.

Figure 45. Write Cycle Followed by Read Cycle Table 123. Timing Characteristics for Write Cycle Followed by Read Cycle

11.8 PHIF Specifications

writes are identical to one-half of a 16-bit access. Figure 46. PHIF Intel Mode Signaling (Read and Write) Timing Diagram referenced to PCSN apply to PIDS or PODS, if PIDS or PODS is the controlling signal. referenced to PCSN apply to PIDS or PODS, if PIDS or PODS is the controlling signal. Table 124. Timing Requirements for PHIF Intel Mode Signaling Table 125. Timing Characteristics for PHIF

110 Lucent Technologies Inc. Figure 47. PHIF Intel Mode Signaling (Pulse Period and Flags) Timing Diagram or PIDS, whichever comes first. to the inverted levels as well as those shown. Table 126. Timing Requirements for PHIF Intel Mode Signaling Table 127. Timing Characteristics for PHIF Intel Mode Signaling

Figure 48. PHIF Motorola Mode Signaling (Read and Write) Timing Diagram also be initiated and completed with the PDS signal. An input/output transaction is initiated by PCSN or PDS going low, whichever comes last. PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction. be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown. also be initiated and completed with the PDS signal. An input/output transaction is initiated by PCSN or PDS going low, whichever comes last. PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction. Table 128. Timing Requirements for PHIF Motorola Mode Signaling Table 129. Timing Characteristics for PHIF

112 Lucent Technologies Inc. Figure 49. PHIF Motorola Mode Signaling (Pulse Period and Flags) Timing Diagram PDS going low, if PDS goes low after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first. be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown. Table 130. Timing Characteristics for PHIF Motorola Mode Signaling Table 131. Timing Requirements for PHIF Motorola Mode Signaling

• Motorola mode signal name.

Figure 50. PHIF Intel or Motorola Mode Signaling (Status Register Read) Timing Diagram † t45, t47, and t49 are referenced to the falling edge of PCSN or PODS(PDS), whichever occurs last. ‡ t46, t48, and t50 are referenced to the rising edge of PCSN or PODS(PDS), whichever occurs first. † t45, t47, and t49 are referenced to the falling edge of PCSN or PODS(PDS), whichever occurs last. ‡ t46, t48, and t50 are referenced to the rising edge of PCSN or PODS(PDS), whichever occurs first. Table 132. Timing Requirements for Intel and Motorola Mode Signaling (Status Register Read) Table 133. Timing Characteristics for Intel and Motorola Mode Signaling (Status Register Read)

11.9 Serial I/O Specifications

Figure 53. SIO Passive Mode Input Timing Diagram † Device is fully static; t70 is tested at 200 ns. ‡ For multiprocessor mode, see note in Section 12.10. Table 136. Timing Requirements for Serial Inputs Table 137. Timing Characteristics for Serial Outputs

116 Lucent Technologies Inc.

• ILD goes high during bit 6 (of 0:15), N = 8 or 16.

Figure 54. SIO Active Mode Input Timing Diagram Table 138. Timing Requirements for Serial Inputs Table 139. Timing Characteristics for Serial Outputs

Figure 55. SIO Passive Mode Output Timing Diagram † Device is fully static; t80 is tested at 200 ns. ‡ For multiprocessor mode, see note in Section 12.10. Table 140. Timing Requirements for Serial Inputs Table 141. Timing Characteristics for Serial Outputs

118 Lucent Technologies Inc.

• OLD goes high at the end of bit 6 of 0:15.

Figure 56. SIO Active Mode Output Timing Diagram Table 142. Timing Characteristics for Serial Output

• See sioc register, LD field.

Figure 57. Serial I/O Active Mode Clock Timing Table 143. Timing Characteristics for Signal Generation

120 Lucent Technologies Inc.

11.10 Multiprocessor Communication

• Negative edge initiates time slot 0.

Figure 58. SIO Multiprocessor Timing Diagram multiprocessor mode, assuming 50% duty cycle, is calculated as (t77 + t116) x 2.

• With capacitance load on ICK, OCK, DO, SYNC, and SADD = 100 pF, add 4 ns to t116—t122.

Table 144. Timing Requirements for SIO Multiprocessor Communication Table 145. Timing Characteristics for SIO Multiprocessor Communication

March 2000 DSP1627 Digital Signal Processor Lucent Technologies Inc. 121 12 Timing Characteristics for 2.7 V Operation The following timing characteristics and requirements are preliminary information and are subject to change. Timing characteristics refer to the behavior of the device under specified conditions. Timing requirements refer to conditions imposed on the user for proper operation of the device. All timing data is valid for the following conditions: T A = –40 °C to +85 °C (See Section 8.3.) VDD = 3 V ± 10%, VSS = 0 V (See Section 8.3.) Capacitance load on outputs (CL) = 50 pF, except for CKO, where CL = 20 pF. Output characteristics can be derated as a function of load capacitance (CL). All outputs: 0.03 ns/pF ≤ dt/dCL ≤ 0.07 ns/pF for 10 ≤ CL ≤ 100 pF at VIH for rising edge and at VIL for falling edge. For example, if the actual load capacitance is 30 pF instead of 50 pF, the derating for a rising edge is (30 – 50) pF x 0.06 ns/pF = 1.2 ns less than the specified rise time or delay that includes a rise time. Test conditions for inputs: ■ Rise and fall times of 4 ns or less ■ Timing reference levels for delays = VIH, VIL Test conditions for outputs (unless noted otherwise): ■ C LOAD = 50 pF; except for CKO, where CLOAD = 20 pF ■ Timing reference levels for delays = VIH, VIL ■ 3-state delays measured to the high-impedance state of the output driver For the timing diagrams, see Table 62 for input clock requirements. Unless otherwise noted, CKO in the timing diagrams is the free-running CKO.

122 Lucent Technologies Inc.

12.1 DSP Clock Generation

• See Table 62 for input clock electrical requirements.

‡ Wait-stated clock (see Table 38). § W = number of wait-states. Figure 59. I/O Clock Timing Diagram

• Device speeds greater than 50 MIPS do not support 1 X operation. Use the PLL.

† Device is fully static, t1 is tested at 100 ns for 1X input clock option, and memory hold time is tested at 0.1 s.

• T = internal clock period, set by CKI or by CKI and the PLL parameters.

Table 146. Timing Requirements for Input Clock Table 147. Timing Characteristics for Input Clock and Output Clock

12.2 Reset Circuit

• See Table 60, Recommended Operating Condiitons.

See Table 62 for CKI electrical requirements and Table 151 for TCK timing requirements. TMS and TDI signals have internal pull-up devices. Figure 60. Powerup Reset and Chip Reset Timing Diagram

• With external components as specified in Table 62.

†T TCK = t12 = TCK period. See Table 151 for TCK timing requirements. Table 148. Timing Requirements for Powerup Reset and Chip Reset

124 Lucent Technologies Inc.

12.3 Reset Synchronization

• See Table 62 for input clock electrical requirements.

Note: CKO1 and CKO2 are two possible CKO states before reset. CKO is free-running. Figure 61. Reset Synchronization Timing Table 149. Timing Characteristics for Powerup Reset and Chip Reset Table 150. Timing Requirements for Reset Synchronization Timing

12.4 JTAG I/O Specifications

Figure 62. JTAG Timing Diagram Table 151. Timing Requirements for JTAG Input/Output Table 152. Timing Characteristics for JTAG Input/Output

126 Lucent Technologies Inc.

12.5 Interrupt

† IACK assertion is guaranteed to be enclosed by VEC[3:0] assertion. Figure 63. Interrupt Timing Diagram Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts. Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts. Table 153. Timing Requirements for Interrupt Table 154. Timing Characteristics for Interrupt

12.6 Bit Input/Output (BIO)

Figure 64. Write Outputs Followed by Read Inputs (cbit = Immediate; a1 = sbit) Figure 65. Write Outputs and Test Inputs (cbit = Immediate) Table 155. Timing Requirements for BIO Input Read Table 156. Timing Characteristics for BIO Output Table 157. Timing Requirements for BIO Input Test

128 Lucent Technologies Inc.

12.7 External Memory Interface

detailed description of the external memory interface including other functional diagrams.

• W = number of wait-states.

Figure 66. Enable Transition Timing Table 158. Timing Characteristics for External Memory Enables (EROM, ERAMHI, IO, ERAMLO) Table 159. Timing Characteristics for Delayed External Memory Enables (ioc = 0x000F)

• W = number of wait-states.

Figure 67. External Memory Data Read Timing Diagram Table 160. Timing Characteristics for External Memory Access Table 161. Timing Requirements for External Memory Read (EROM, ERAMHI, IO, ERAMLO)

130 Lucent Technologies Inc.

• W = number of wait-states.

Figure 68. External Memory Data Write Timing Diagram Table 162. Timing Characteristics for External Memory Data Write (All Enables)

• W = number of wait-states.

Figure 69. Write Cycle Followed by Read Cycle Table 163. Timing Characteristics for Write Cycle Followed by Read Cycle

132 Lucent Technologies Inc.

12.8 PHIF Specifications

writes are identical to one-half of a 16-bit access. Figure 70. PHIF Intel Mode Signaling (Read and Write) Timing Diagram referenced to PCSN apply to PIDS or PODS, if PIDS or PODS is the controlling signal. referenced to PCSN apply to PIDS or PODS, if PIDS or PODS is the controlling signal. Table 164. Timing Requirements for PHIF Intel Mode Signaling Table 165. Timing Characteristics for PHIF

Figure 71. PHIF Intel Mode Signaling (Pulse Period and Flags) Timing Diagram or PIDS, whichever comes first. to the inverted levels as well as those shown. Table 166. Timing Requirements for PHIF Intel Mode Signaling Table 167. Timing Characteristics for PHIF Intel Mode Signaling

134 Lucent Technologies Inc. Figure 72. PHIF Motorola Mode Signaling (Read and Write) Timing Diagram also be initiated and completed with the PDS signal. An input/output transaction is initiated by PCSN or PDS going low, whichever comes last. PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction. be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown. also be initiated and completed with the PDS signal. An input/output transaction is initiated by PCSN or PDS going low, whichever comes last. PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction. Table 168. Timing Requirements for PHIF Motorola Mode Signaling Table 169. Timing Characteristics for PHIF

Figure 73. PHIF Motorola Mode Signaling (Pulse Period and Flags) Timing Diagram PDS going low, if PDS goes low after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first. be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown. Table 170. Timing Characteristics for PHIF Motorola Mode Signaling Table 171. Timing Requirements for PHIF Motorola Mode Signaling

136 Lucent Technologies Inc.

• Motorola mode signal name.

Figure 74. PHIF Intel or Motorola Mode Signaling (Status Register Read) Timing Diagram † t45, t47, and t49 are referenced to the falling edge of PCSN or PODS(PDS), whichever occurs last. ‡ t46, t48, and t50 are referenced to the rising edge of PCSN or PODS(PDS), whichever occurs first. † t45, t47, and t49 are referenced to the falling edge of PCSN or PODS(PDS), whichever occurs last. ‡ t46, t48, and t50 are referenced to the rising edge of PCSN or PODS(PDS), whichever occurs first. Table 172. Timing Requirements for Intel and Motorola Mode Signaling (Status Register Read) Table 173. Timing Characteristics for Intel and Motorola Mode Signaling (Status Register Read)

138 Lucent Technologies Inc.

12.9 Serial I/O Specifications

Figure 77. SIO Passive Mode Input Timing Diagram † Device is fully static; t70 is tested at 200 ns. ‡ For multiprocessor mode, see note in Section 12.10. Table 176. Timing Requirements for Serial Inputs Table 177. Timing Characteristics for Serial Outputs

• ILD goes high during bit 6 (of 0:15), N = 8 or 16.

Figure 78. SIO Active Mode Input Timing Diagram Table 178. Timing Requirements for Serial Inputs Table 179. Timing Characteristics for Serial Outputs

140 Lucent Technologies Inc. Figure 79. SIO Passive Mode Output Timing Diagram † Device is fully static; t80 is tested at 200 ns. ‡ For multiprocessor mode, see note in Section 12.10. Table 180. Timing Requirements for Serial Inputs Table 181. Timing Characteristics for Serial Outputs

• OLD goes high at the end of bit 6 of 0:15.

Figure 80. SIO Active Mode Output Timing Diagram Table 182. Timing Characteristics for Serial Output

142 Lucent Technologies Inc.

• See sioc register, LD field.

Figure 81. Serial I/O Active Mode Clock Timing Table 183. Timing Characteristics for Signal Generation

12.10 Multiprocessor Communication

• Negative edge initiates time slot 0.

Figure 82. SIO Multiprocessor Timing Diagram multiprocessor mode, assuming 50% duty cycle, is calculated as (t77 + t116) x 2.

• With capacitance load on ICK, OCK, DO, SYNC, and SADD = 100 pF, add 4 ns to t116—t122.

Table 184. Timing Requirements for SIO Multiprocessor Communication Table 185. Timing Characteristics for SIO Multiprocessor Communication

144 Lucent Technologies Inc.

13 Crystal Electrical Characteristics and Requirements

If the option for using the external crystal is chosen, the following electrical characteristics and requirements apply.

13.1 External Components for the Crystal Oscillator

however, larger values allow for better frequency precision (see Section 13.4, Frequency Accuracy Considerations). signal at the CKI input pin is equal to the crystal frequency. Figure 83. Fundamental Crystal Configuration

1. Keep crystal and external capacitors as close to CKI and CKI2 pins as possible to minimize board stray capaci-
2. Keep high-frequency digital signals such as CKO away from CKI and CKI2 traces to avoid coupling.

13.2 Power Dissipation

Figures 86 and 87 indicate the typical power dissipation of the on-chip crystal oscillator circuit versus frequency. DDA pin should be less than that shown in the figures.

13 Crystal Electrical Characteristics and Requirements (continued)

Figure 84. Negative Resistance of Crystal Oscillator Figure 85. Negative Resistance of Crystal Oscillator

146 Lucent Technologies Inc. Figure 86. Typical Supply Current of Crystal Oscillator Circuit, VDD = 5.0 V, 25 °C Figure 87. Typical Supply Current of Crystal Oscillator Circuit, VDD = 2.7 V, 25 °C

13.3 LC Network Design for Third Overtone Crystal Circuits

For certain crystal applications, it is cheaper to use a third overtone crystal instead of a fundamental mode crystal. described below. Figure 88 shows the basic setup for third overtone operation. Figure 88. Third Overtone Crystal Configuration be chosen to be large compared to C1.

DSP1627 Digital Signal Processor March 2000 148 Lucent Technologies Inc. At the third overtone frequency, f3, it is desirable to have the net impedance of the trap circuit (XT) equal to the im- pedance of C2 (XC2 ), i.e., Selecting C3 so that XC3 << XL1 yields, For a capacitor, For an inductor, Solving for C1, and realizing that L1C 1 = 3/ω 32 yields, Hence, for C2 = 10 pF, C1 = 15 pF. Since the impedance of the trap circuit in this example would be equal to the impedance of a 10 pF capacitor, the negative resistance and supply current curves for C1 = C2 = 10 pF at 40 MHz would apply to this example. Finally, solving for the inductor value, For the above example, L1 is 3.2 µH. X T X C2 X C1 X C3 X L1+()||== X T X C2 X C1 X L1||== X C j– X L jω L= C 1 3 2---C 2= L1 1 4π2fT2C 1

13.4 Frequency Accuracy Considerations

For frequency accuracy implications of using the PLL, see Section 4.12, Clock Synthesis. should be consulted prior to specifying a crystal for a given application. oscillator. Figure 89 illustrates some of the sources of this variation. C ext = External load capacitor (one each required for CKI and CKI2). C D = Parasitic capacitance of the DSP1627 itself. C B = Parasitic capacitance of the printed-wiring board. C O = Parasitic capacitance of crystal (not part of CL, but still a source of frequency variation). Figure 89. Components of Load Capacitance for Crystal Oscillator 0 = parasitic capacitance of crystal in pF. C1 = motional capacitance of crystal in pF (usually between 1 fF to 25 fF, value available from crystal vendor). CL = total load capacitance in pF seen by crystal.

2 C 0 C L+()

DSP1627 Digital Signal Processor March 2000 150 Lucent Technologies Inc. Note that for a given crystal, the pullability can be reduced, and, hence, the frequency stability improved, by making CL as large as possible while still maintaining sufficient negative resistance to ensure start-up per the curves shown in Figures 86 and 87. Since it is not possible to know the exact values of the parasitic capacitance in a crystal-based oscillator system, the external capacitors are usually selected empirically to null out the frequency offset on a typical prototype board. Thus, if a crystal is specified to operate with a load capacitance of 10 pF, the external capacitors would have to be made slightly less than 20 pF each in order to account for strays. Suppose, for instance, that a crystal for which C L = 10 pF is specified is plugged into the system and it is determined empirical that the best frequency accuracy occurs with Cext = 18 pF. This would mean that the equivalent board and device strays from each leac to ground would be 2 pF. As an example, suppose it is desired to design a 23 MHz, 3.3 V system with ±100 ppm frequency accuracy. The parameters for a typical high-accuracy, custom, 23 MHz fundamental mode crystal are as follows: Initial Tolerance 10 ppm Temperature Tolerance 25 ppm Aging Tolerance 6 ppm Series Resistance 20 Ω max. Motional Capacitance (C 1) 15 fF max. Parasitic Capacitance (C0) 7 pF max. In order to ensure oscillator start-up, the negative resistance of the oscillator with load and parasitic capacitance must be at least twice the series resistance of the crystal, or 40 Ω . Interpolating from Figure 89, external capacitors plus strays can be made as large as 30 pF while still achieving 40 Ω of negative resistance. Assume for this example that external capacitors are chosen so that the total load capacitance including strays is 30 pF per lead, or 15 pF total. Thus, a load capacitance, C L = 15 pF would be specified to the crystal manufacturer. From the above equation, the pullability would be calculated as follows: If 2% external capacitors are used, the frequency deviation due to capacitor tolerance is equal to: (0.02)(15 pF)(15.5 ppm/pF) = 4.7 ppm Note:To simplify analysis, Cext is considered to be 30 pF. In practice, it would be slightly less than this value to account for strays. Also, temperature and aging tolerances on the capacitors have been neglected. Typical capacitance variation of the oscillator circuit in the DSP1627 itself across process, temperature, and supply voltage is ±1 pF. Thus, the expected frequency variation due to the DSP1627 is: (1 pF)(15.5 ppm/pF) = 15.5 ppm Approximate variation in parasitic capacitance of crystal = ±0.5 pF. Frequency shift due to variation in C0 = (0.5 pF)(15.5 ppm/pF) = 7.75 ppm Approximate variation in parasitic capacitance of printed-circuit board = ±1.5 pF. Frequency shift due to variation in board capacitance = (1.5 pF)(15.5 ppm/pF) = 23.25 ppm pullability C 1() 106() 2C 0 C L+()

March 2000 DSP1627 Digital Signal Processor Lucent Technologies Inc. 151 Thus, the contributions to frequency variation add up as follows: Initial Tolerance of Crystal 10.0 ppm Temperature Tolerance of Crystal 25.0 Aging Tolerance of Crystal 6.0 Load Capacitor Variation 4.7 DSP1627 Circuit Variation1 5.5 C 0 Variation 7.8 Board Variation 23.3 Total 92.3 ppm This type of detailed analysis should be performed for any crystal-based application where frequency accuracy is critical.

DSP1627 Digital Signal Processor March 2000 152 Lucent Technologies Inc.

14 Outline Diagrams

14.1 100-Pin BQFP (Bumpered Quad Flat Pack) All dimensions are in millimeters. 5-1970 (F)r.10 PIN #1 IDENTIFIER ZONE 89113 39 6 3 19.050 ± 0.405 22.350 ± 0.255 22.860 ± 0.305 22.350 ± 0.255 19.050 ± 0.405 22.860 ± 0.305 EDGE CHAMFER DETAIL A

4.570 MAXDETAIL B

0.760 ± 0.2550.635 TYP 0.10 SEATING PLANE 3.555 ± 0.255 DETAIL B 0.280 ± 0.075 0.150 M 0.175 ± 0.025 DETAIL A 0.255 0.91/1.17 GAGE PLANE SEATING PLANE

March 2000 DSP1627 Digital Signal Processor Lucent Technologies Inc. 153

14 Outline Diagrams (continued)

14.2 100-Pin TQFP (Thin Quad Flat Pack) All dimensions are in millimeters.

0.50 TYP

1.60 MAX

0.08 1.40 ± 0.05 0.05/0.15 DETAIL A DETAIL B 14.00 ± 0.20 16.00 ± 0.20 76100 26 50 14.00 ± 0.20 16.00 ± 0.20 PIN #1 IDENTIFIER ZONE DETAIL B 0.19/0.27 0.08 M 0.106/0.200 DETAIL A 0.45/0.75 GAGE PLANE SEATING PLANE

1.00 REF

0.25 5-2146 (F)r.14

Lucent T echnologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright © 2000 Lucent T echnologies Inc. All Rights Reserved March 2000 DS00-205WTEC (Replaces DS00-061WTEC) For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, P A 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA P ACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent T echnologies (China) Co., Ltd., A-F2, 23/F , Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P . R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAP AN: Microelectronics Group, Lucent T echnologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, T okyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DA T ALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries:GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), IT AL Y: (39) 02 6608131 (Milan), SP AIN: (34) 1 807 1441 (Madrid)