T8208

T8208 AGERE | Alldatasheet

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Technical content

1 Product Overview

1.1 Features

■ OC-12 data throughput on UTOPIA (16-bit) (independently on RX and TX UTOPIA) ■ Shared UTOPIA mode ■ UTOPIA Level 1 and 2 (8-bit/16-bit) cell-level handshake interface (ATM or PHY layers) ■ Multi-PHY (MPHY) operation ■ Programmable ATM layer supports up to 64 PHY ports ■ Egress SDRAM buffer support to extend UTOPIA output priority queues for 32K to 512K cells: — 128 queues configurable up to four queues per PHY with programmable sizes — Programmable number of UTOPIA output queues with four levels of priority ■ Support of ATM traffic management via partial packet discard (PPD), forward explicit congestion notification (FECN), and the cell loss priority (CLP) bit ■ Programmable slew rate GTL+ I/O: — Programmable as bus arbiter — 1.7 Gbits/s cell bus operation ■ Flexible per port cell counters ■ Cell header insertion with virtual path identifier (VPI) and virtual channel identifier (VCI) translation via external SRAM (up to 64K entries) ■ Support of network node interface (NNI) and user network interface (UNI) header types with optional generic flow-control (GFC) insertion ■ Optional sourcing of cell bus clocks from device ■ LUT bypass option ■ TX UTOPIA cell buffer increased to 256 cells for better queue management with SDRAM queue bypass option ■ Ability for cell bus arbiter to mask devices on the cell bus ■ Ability to modify cell bus priority based on RX PHY FIFO thresholds ■ Programmable priority for control/data cells trans- mission onto cell bus ■ Microprocessor access to all headers of control cell ■ Ability to clear counters on read ■ Simplified looping to any system device with a sin- gle register programming ■ UTOPIA clock sourcing with additional settings ■ Programmable operations and maintenance and resource management (OAM/RM) cell routing ■ Support of multicast and broadcast cells per PHY ■ Optional monitoring of misrouted cells ■ Counters for dropped cells per queue ■ Digital loopback before cell bus ■ Microprocessor interface, supporting both Motor- ola® and Intel® modes (multiplexed and nonmulti- plexed) ■ Control cell transmission and reception through microprocessor port ■ Single 3.3 V power supply ■ 3.3 V TTL I/O (5 V tolerant) ■ 272-pin plastic ball grid array (PBGA) package ■ Industrial temperature range (–40 °C to +85 °C) ■ Hot insertion capability ■ Eight GPIO pins ■ JTAG support ■ Compatible with Transwitch CellBus®

1.2 Applications

■ Asymmetric digital subscriber line (ADSL) digital subscriber line access multiplexers (DSLAMs) ■ Access gateways ■ Access multiplexers/concentrators ■ Multiservice platforms

2 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8208 Table of Contents Contents Page 6.3.2

Agere Systems Inc. 3 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8208 Table of Contents (continued) Contents Page

Table 21. Queue Organization and Port Group Address/Priority Bits for 64 Ports in 8-Bit UTOPIA Mode and

Agere Systems Inc. 9 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8208

1 Product Overview (continued)

1.3 Description

The CelXpres T8208 device integrates all of the required functionality to transport ATM cells across a backplane architecture with high-speed cell traffic exceeding 1.5 Gbits/s to a maximum of 32 destinations. The management of multiple service categories and monitoring of performance on ATM and PHY interfaces is incorporated in the device’s functionality. Traffic delivery to multi-PHYs (MPHYs) is managed through the UTOPIA interface. The T8208 device meets the ATM Forum’s universal test and operations PHY interface for ATM (UTOPIA) Level 1, Version 2.01 and Level 2, Version 1.0 specifications for cell-level handshake and MPHY data path operation with rates up to 635 Mbits/s. The T8208 supports the required MPHY operation as described in Sections 4.1 and 4.2 of the ATM Forum’s level 2 specification. The T8208 supports MPHY operation with one transmit cell available (TxCLAV) signal and one receive cell available (RxCLAV) signal for up to 16 PHY ports for an 8-bit UTOPIA 2 inter- face configuration. With four transmit cells available/enable (TxCLAV/Enb*) pairs of signals and receive cell avail- able/enable (RxCLAV/Enb*) pairs of signals, 64 MPHYs can be supported. For a 16-bit UTOPIA 2 interface configuration, the T8208 supports MPHY operation with one transmit cell available (TxCLAV) signal and one receive cell available (RxCLAV) signal for up to 8 PHY ports. With four transmit cell available (TxCLAV/Enb*) sig- nals and four receive cell available (RxCLAV/Enb*) signals, 32 MPHYs can be supported in 16-bit UTOPIA 2 inter- face configuration. In addition to the required UTOPIA signals, the optional transmit parity (TxPRTY) and receive parity (RxPRTY) signals are provided. The T8208 may be configured as an ATM or PHY level device providing cell routing between UTOPIA and a 32-bit wide cell bus. In addition to the 32 data signals, the bus has the following signals: ■ Read clock ■ Write clock ■ Frame sync ■ Acknowledge ATM cells arriving from the UTOPIA interface may get VPI and VCI translation and routing information from a look- up table in external SRAM. An external synchronous dynamic random access memory (SDRAM) is used to extend the buffering for ATM cells destined for the UTOPIA interface. This external SDRAM may be partitioned into four or less independently sized queues per PHY for a configuration of 32 MPHYs and two queues per PHY or a program- mable number of queues per PHY for a configuration of 64 MPHYs. The four queues may be used to support qual- ity of service (QoS) by directing different traffic categories to each queue. The number of cells per queue per PHY is programmable. The CelXpres T8208 provides a shared UTOPIA mode, which allows two devices on different cell buses to share the same UTOPIA bus in ATM mode. Using a glueless interface, the two T8208 devices resolve queue priorities and arbitrate the use of the UTOPIA bus. This shared mode can be used to provide redundancy or increase UTO- PIA traffic capacity by supporting traffic from multiple cell busses. The CelXpres T8208 supports the transport of control and loopback cells with an external microprocessor. Control or loopback cells may be sent or received through the microprocessor interface. The 8-bit microprocessor interface may be configured to be Motorola or Intel compatible and is used to configure and monitor the device.

Figure 1. Functional Block Diagram

devices by configuring one device to assume bus responsibility from the other. Figure 2. Dual Bus Implementation

12 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8208

1.4 Conventions

■ All numbers in this document are decimals unless otherwise specified. ■ Hexadecimal numbers can be identified by the ‘h’ suffix, e.g., A5h. ■ Binary numbers are either in double quotes for multiple bits or in single quotes for individual bits, e.g., “1001” and ‘0.’ ■ A byte is 8 bits, a word is 16 bits, and a double word (dword) is 32 bits. ■ A binary value of ‘1’ is high, and a binary value of ‘0’ is low. ■ To clear is to change one or multiple bit values to ‘0.’ ■ To set is to change one or multiple bit values to ‘1.’ ■ All memory addresses are specified in hexadecimal. ■ Addresses are converted from bytes to words or double words using the little-endian format, unless otherwise specified. ■ A signal name with a trailing asterisk is active-low, e.g., sd_we*. ■ Bits y to x will be designated bits (y:x).

Agere Systems Inc . 13 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8208

1.5 Glossary

Bus Cell: Major content of the cell bus frame consisting of 56 bytes, 4 bytes for routing options and 52 bytes for the ATM cell content, which excludes the HEC. The bus cell is preceded by the 4 bytes of request and followed by the 4 bytes of grant and parity information. CLP : Cell loss priority. The CLP is a 1-bit field in the cell header that becomes set when the cell violates the negotiated quality of service parameters. EFCI: Explicit forward congestion indication. The EFCI is a 1-bit field in the PTI field of the cell header that becomes set when the cell encounters congestion. FECN : Forward explicit congestion notification. FECN is a method used by the network to signal to the destination when congestion is encountered. The EFCI bit is used to indicate the congestion. GFC : Generic flow control. The GFC is a 4-bit field in the cell header that may be used by a UNI to support traffic and congestion control. Typically, this field is pro- grammed to “0000” indicating that generic flow control is not supported. GFC may be used in priority proto- cols. Grant Section: Last 4 bytes of the cell bus frame. The grant section occurs during the last clock cycle of the cell bus frame. During this cycle, the cell bus arbiter indicates which T8208 may transmit during the next bus cell unit of the cell bus frame. A parity vector is also transmitted dur- ing the grant section. HEC : Header error control. The HEC is a 1-byte field in the cell header used for bit error detection and correction in the header. NNI: Network node interface. The NNI is the interface between nodes in the public network. OAM Cell: Operations and maintenance cell. An OAM cell carries local management information. PPD : Partial packet discard. PPD is a technique to relieve congestion. When one cell in a packet is lost, all remaining cells in the packet, except the last, are dis- carded. PTI: Payload type identifier. The PTI is a 3-bit field in the cell header containing information about the type of data (user, OAM, or traffic management) and about encoun- tered congestion. QoS : Quality of service. Quality of service parameters define the performance requirements and characteristics for traffic on an assigned channel. Some parameters include cell loss ratio, cell transfer delay, cell delay vari- ation, peak cell rate, and sustained cell rate. Request Section: First 4 bytes of the cell bus frame. The request section occurs during the first clock cycle of the cell bus frame. During this cycle, 16 T8208 devices assert their trans- mission requests onto the cell bus. RM : Resource management. RM is the local management of network resources. RxCLAV : Receive cell available signal as described in the ATM Forum’s universal test and operations PHY interface for ATM (UTOPIA) Level 1, Version 2.01 and Level 2, Version 1.0 specifications. RxENB : Receive enable signal as described in the ATM Forum’s universal test and operations PHY interface for ATM (UTOPIA) Level 1, Version 2.01 and Level 2, Version 1.0 specifications. TxCLAV : Transmit cell available signal as described in the ATM Forum’s universal test and operations PHY interface for ATM (UTOPIA) Level 1, Version 2.01 and Level 2, Version 1.0 specifications. TxENB : Transmit enable signal as described in the ATM Forum’s universal test and operations PHY interface for ATM (UTOPIA) Level 1, Version 2.01 and Level 2, Version 1.0 specifications. UNI: User network interface. The UNI is the interface between a private network node and a public network node. VCI: Virtual channel identifier. The VCI is a 2-byte field in the cell header that identifies the virtual channel used by the cell. VPI: Virtual path identifier. The VPI is an 8-bit field in the UNI cell header or a 12-bit field in the NNI cell header that identifies the virtual path of the cell.

2 Pinout

Table 1. UTOPIA Pins —I RX UTOPIA Data Lines. TTL compatible input, 5 V tolerant. u_rxclk T1 Z I/O RX UTOPIA Clock. 10 mA drive, TTL compatible I/O, 5 V tolerant. tolerant. This pin has an internal 50 kΩ pull-up resistor. gle PHY mode. 10 mA drive, TTL compatible I/O, 5 V tolerant. compatible I/O, 5 V tolerant. pin has an internal 50 kΩ pull-up resistor. Z I/O TX UTOPIA Address Lines. 10 mA drive, TTL compatible I/O. ZO TX UTOPIA Data Lines. 10 mA drive, TTL compatible output. u_txclk R18 Z I/O TX UTOPIA Clock. 10 mA drive, TTL compatible I/O, 5 V tolerant. tolerant. This pin has an internal 50 kΩ pull-up resistor. PHY mode. 10 mA drive, TTL compatible I/O, 5 V tolerant. u_txprty T19 Z O TX UTOPIA Odd Parity. 10 mA drive, TTL compatible output.

2 Pinout (continued)

Table 2. Shared UTOPIA Pins requested cell transfer. 6 mA drive, TTL compatible I/O. These pins have an internal 50 kΩ pull-up resistor. pins have an internal 50 kΩ pull-up resistor.

Table 3. Cell Bus Pins Z I/O Cell Bus Data Lines (Active-Low). GTL+ I/O. the same frequency but different phase. GTL+ input. the same frequency but different phase. GTL+ input. cb_fs* C15 Z I/O Cell Bus Frame Sync (Active-Low). GTL+ I/O. broadcast or multicast cells. GTL+ I/O. pin has an internal 50 kΩ pull-up resistor. are active. This pin has an internal 50 kΩ pull-up resistor. nected between this pin and GND. 1% resistors between VTT and cb_vref_vss. cb_vref_vss C10 — — Cell Bus Voltage Reference Ground.

Table 4. SDRAM Interface Pins put. These buffers are 50 Ω impedance matching buffers. wiring board traces should have 50 Ω nominal impedance. sd_bs[1:0] H18, G20 X O SDRAM Bank Selects. 7 mA drive, TTL compatible output. have 50 Ω nominal impedance. should have 50 Ω nominal impedance. wiring board traces should have 50 Ω nominal impedance.

Table 5. Microprocessor Interface Pins 7 bits of the address bus. TTL compatible input, 5 V tolerant. a[0]/ale Y8 — I Microprocessor Port Address 0/Address Latch Enable. mode or address latch enable in multiplexed mode. mode. TTL compatible input, 5 V tolerant. Motorola mode. 4 mA drive, TTL compatible output. compatible input, 5 V tolerant. mode. TTL compatible input, 5 V tolerant.

Table 6. Translation SRAM Interface Table 7. JTAG Pins jtag_tdi Y16 —I Test Data Input (JTAG). TTL compatible input, 5 V tolerant. This pin has an internal 50 kΩ pull-up resistor. tolerant. This pin has an internal 50 kΩ pull-up resistor. pin has an internal 50 kΩ pull-up resistor. ant. This pin has an internal 50 kΩ pull-up resistor.

Table 8. General-Purpose Pins Table 9. Power Pins tolerant. These pins have an internal 50 kΩ pull-up resistor. input with 50 MHz max input frequency. used to drive xtalin, this pin must be left unconnected. decoupled using 0.01 µF or 0.1 µF capacitors.

Figure 3. 272-Pin PBGA— Top View

22 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8208

3 Powerup/Reset Sequence

One of the following two methods may be used to reset the T8208: 1. Assert the reset* pin low for at least 5 pclk periods or 100 ns, whichever is longer, and then return it high for a hardware reset. For a powerup reset, the reset* pin should be held low for at least 5 pclk periods or 100 ns, whichever is longer, after the power supply ramps to its operating voltage and the crystal oscillator is stable. 2. Write both the srst* and srst_reg* bits in the direct configuration/control register (address 28h) to ‘0,’ and leave them at that value for at least 1 µs to perform a software reset. The device is now in the reset state, and the following start-up procedure must be executed to ensure proper oper- ation: 1. After pclk (xtalin) is provided to the T8208, and the device is in the reset state: A. Write the mclk PLL configuration 0 and 1 registers at addresses 2Ah and 2Bh. B. Continue after the PLL has stabilized in 100 µs. 2. Set the srst_reg* bit (to take the main registers out of reset), and program the cyc_per_acc and big_end bits in the direct configuration/control register (address 28h). 3. Wait 1 µs for the circuit to stabilize. Extended memory accesses may now be performed only to the main register group. 4. Write the desired values to the main configuration 1 register (address 0100h), the TX UTOPIA clock configura- tion register (address 010Ch), and the RX UTOPIA clock configuration register (address 010Eh) in the extended memory registers. These bits should not be modified at a later time without returning to the reset state. 5. Program the main configuration 2 register (address 0112h) and the UTOPIA configuration register (address 0114h). These registers should not be modified at a later time without returning to the reset state. 6. Program the cb_arb_sel and cb_usr_mode bits in the cell bus configuration/status register (address 0130h). 7. Wait one clock period of the slowest clock (cell bus, UTOPIA, or pclk) for the circuit to stabilize. 8. Set the srst* bit in the direct configuration/control register (address 28h). 9. Wait three clock periods of the slowest clock (cell bus, UTOPIA, or pclk) for the circuit to stabilize. The T8208 device is now out of reset state. 10. Initialize the SDRAM per the SDRAM specifications. 11. Enable the SDRAM by setting the sdram_en bit in the SDRAM control register (address 0400h). 12. Initialize the LUT to benign values (recommended). 13. Initialize the multicast memory to all '0' (recommended). 14. Program the four routing information registers (addresses 0200h through 0204h and 0214h) and the seven PPD information registers (addresses 0206h through 0212h).

Agere Systems Inc. 23 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8208

4 Hot Insertion

When a connector with proper pin sequencing is used, the Agere Systems Inc. GTL+ buffers withstand hot inser- tion into a backplane without corrupting the cell bus or damaging the device. The ground pins on the connector should extend beyond all other pins so that the ground connections are made first. In addition, the power pins on the connector should extend beyond the signal pins so that the power connections are made before the signal but after the ground connections. During hot insertion, the cell bus is not corrupted because the GTL+ outputs go to a high-impedance state during the powerup reset. Therefore, proper timing should be met in the external powerup reset circuit.

5 PLL Configuration

Note: When the PLL is engaged, mclk is the output of the PLL. Note: The output of the PLL must always be at least 50 MHz. lists the lf[3:0] settings for given values of M. Typical PLL lock-in time is 50 µs. Table 10. Loop Filter Register Settings

Agere Systems Inc. 25 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8208

6 Microprocessor Interface

6.1 Microprocessor Interface Configuration

The microprocessor interface may be configured for either Intel or Motorola mode via the mot_sel input. Tie mot_sel high to select Motorola mode and low to select Intel mode. In addition, the address and data buses may be configured for multiplexed or nonmultiplexed mode using the mux input. To select multiplexed mode, tie mux high, and to select nonmultiplexed mode, tie mux low. In multiplexed mode, d[7:0] are used for both the address and the data bus, and the a[0] input becomes an address latch enable (ale) signal. In nonmultiplexed mode, sepa- rate address, a[7:0], and data, d[7:0], buses are used. In both modes, the active-low sel* input selects the device for microprocessor read or write accesses. The data leads are 3-stated when the sel*, wr*_ds*, or rd*_wr* signal is high. In Motorola mode, rd*_rw* is a read/write enable signal, which indicates the current access is a read when it is high and a write when low. The wr*_ds* signal is data strobe in Motorola mode. The rdy_dtack* output is an active-low data transfer acknowledge signal. The T8208 takes this signal low when the microprocessor access is complete. The rdy_dtack* output returns high when the microprocessor acknowledges the access by taking the sel* or wr*_ds* signal high. The rdy_dtack* output then goes high-impedance. In Intel mode, the rd*_rw* input is an active-low read enable signal, and wr*_ds* is an active-low write enable sig- nal. A logic low level on rd*_rw* indicates to the T8208 that the current access is a read, and a logic low level on wr*_ds* indicates the access is a write. Finally, the rdy_dtack* output is an active-high ready signal. The T8208 asserts this signal high when a microprocessor access is complete. The rdy_dtack* output then goes high-imped- ance when the sel*, wr*_ds*, or rd*_wr* signal goes high.

6.2 Microprocessor Interrupts

The int_irq* output is an active-high interrupt in Intel mode and an active-low interrupt request in Motorola mode. In Intel mode, int_irq* is normally low and goes high when an interrupt is generated. In Motorola mode, the interrupt request signal is normally high and goes low during an interrupt. Interrupts are generated when an enabled inter- rupt status bit becomes set. All interrupt status bits in the T8208 have a corresponding interrupt enable bit. When the enable bit is cleared, the corresponding interrupt status bit is not enabled and will not generate an interrupt. Several registers containing interrupt status bits exist in the four separate extended memory register groups (main, UTOPIA, SDRAM, and bypass SDRAM) of the T8208. The interrupt service request register at direct address 29h indicates which register group is generating the interrupt. Only enabled interrupts will cause the int_serv_mainreg, int_serv_sdramreg, and int_serv_utopiareg bits to become set. For the main register group, a special case exists. The ctrl_cell_sent and the ctrl_cell_av interrupts (in the main interrupt status 1 register) do not cause the main group indication bit to be set in the interrupt service request register. These interrupts have their own dedicated service request bits to optimize sending and receiving control cells. The ctrl_cell_sent and ctrl_cell_av bits may become set whether the corresponding interrupt is enabled or not.

6.3 Accessing the CelXpres T8208 via Microprocessor Interface

The CelXpres T8208 has two distinct memory spaces: the direct memory access registers and the extended mem- ory registers. The direct memory access registers are directly addressed 8-bit (byte) registers and are mapped between addresses 00h and FFh. The extended memory registers are indirectly addressed and mapped between addresses 0100h and 3FFFFFEh. The extended memory contains the SDRAM memory, the translation RAM, internal memories, and the device’s configuration, status, and control registers. Extended memory registers are 16 bits wide, and all accesses to the extended memory registers are executed internally as 16 bits. Direct memory access registers are located in Section 14.2, Direct Memory Access Registers, and extended memory registers are located in Section 14.3, Extended Memory Registers.

26 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8208

6 Microprocessor Interface (continued)

6.3.1 Accessing the Extended Memory Registers

Before accessing the extended memory registers, the powerup sequence, as described in Section 3, Powerup/ Reset Sequence, must be completed. Accesses to extended memory are word accesses internally; therefore, the least significant bit of the address is always ‘0.’ Only the most significant 25 bits are supplied to the extended mem- ory address registers (addresses 30h—34h). The following procedure outlines the steps needed for extended memory accesses in the T8208 device.

6.3.1.1 Extended Memory Writes

1. Write ext_a [25] bit to the extended memory address 4 register (little endian or big endian) (optional). 2. Write ext_a [24:17] byte to the extended memory address register 3 (little endian or big endian) (optional). 3. Write ext_a [16:9] byte to the extended memory address register 2 (little endian or big endian) (optional). 4. Write ext_a [8:6] bits to the extended memory address register 1 (little endian or big endian) (optional). 5. Write ext_d [15:8] byte to the extended memory data high register (little endian or big endian) (optional). 6. Write ext_d [7:0] byte to the extended memory data low register (little endian or big endian) (optional). 7. Write ext_a [5:1] bits; write “01,” “10,” or “11” to ext_we[1:0]; and write ‘1’ to ext_strt_acc in the extended mem- ory access register (little endian or big endian) (mandatory). 8. Read the extended memory access register (little endian or big endian) to determine that the ext_strt_acc bit has been cleared by hardware (mandatory).

6.3.1.2 Extended Memory Reads

1. Write ext_a [25] bit to the extended memory address 4 register (little endian or big endian) (optional). 2. Write ext_a [24:17] byte to the extended memory address register 3 (little endian or big endian) (optional). 3. Write ext_a [16:9] byte to the extended memory address register 2 (little endian or big endian) (optional). 4. Write ext_a [8:6] bits to the extended memory address register 1 (little endian or big endian) (optional). 5. Write ext_a [5:1] bits; write “00” to ext_we[1:0]; and write ‘1’ to ext_strt_acc in the extended memory access register (little endian or big endian) (mandatory). 6. Read the extended memory access register (little endian or big endian) to determine that the ext_strt_acc bit has been cleared by hardware (mandatory). 7. Read ext_d [15:8] byte from the extended memory data high register (little endian or big endian) (optional). 8. Read ext_d [7:0] byte from the extended memory data low register (little endian or big endian) (optional). Note: Once the ext_strt_acc bit is set by software, only the extended memory access register should be accessed until the ext_strt_acc bit is cleared by hardware.

6.3.2 CelXpres T8208 Access Performance

from the completion of a write to register 34h until the ext_strt_acc bit is cleared. The actual times are dependent on the frequency of the pclk and mclk clocks (see Section 5, PLL Configuration). The terms pclkp and mclkp in the table represent the period of pclk and mclk, respectively, in ns. Table 11. Access Times

28 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8208

7 General-Purpose I/O (GPIO)

The T8208 has eight programmable general-purpose I/O pins called GPIO. These GPIO pins may be indepen- dently programmed, via the GPIO_oe[7:0] bits in the GPIO output enable register (address 39h), to be inputs or outputs. If a GPIO_oe bit is set to ‘1,’ the corresponding GPIO pin is an output, or if cleared to ‘0,’ the correspond- ing GPIO pin is an input. Input values are read from the GPIO_in[7:0] bits in the GPIO input value register (address 3Dh), and output values are written to the GPIO_out[7:0] bits in the GPIO output value register (address 3Bh). The GPIO[7:0] pins all have internal 50 kΩ pull-up resistors.

Agere Systems Inc. 29 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8208

8 Look-Up Table

Cells arriving from the UTOPIA bus obtain information from the external static RAM look-up table (LUT), which is divided among VPI, VCI, and OAM/RM records. Each of these records contains specific VPI or VPI/VCI translation and cell bus routing information. The size of the records is programmable to 8 bytes or an extended 16 bytes. The 16-byte mode adds two 32-bit counters to each record. The 16-byte mode is discussed in Section 8.4, Extended Records. The VPI value in the header, in addition to the PHY port number, of the incoming cell points to a VPI record in the look-up table. This VPI record is examined first. If the VPI record indicates OAM F4 routing, the OAM record, to which the VPI record points, provides the OAM routing and VPI/VCI translation information. If OAM F4 routing is not indicated, information about the type of translation, VPI only or VPI/VCI, is obtained from the original VPI record. For VPI only translation, routing information is obtained from the VPI record, and full or partial VPI transla- tion is performed. For VPI/VCI translation, the VPI record points to the appropriate VCI record, where VPI/VCI translation and routing information is stored. If the VCI record indicates OAM F5 routing, the OAM record, to which the VCI record points, provides the OAM routing and VPI/VCI translation information. If no OAM F5 routing is indicated, VPI/VCI transla- tion and cell routing are performed using the information in the VCI record.

8.1 Look-Up Table RAM

The number of memory devices (up to two) used for the look-up table and the size of the external SRAM are pro- grammable. The tram_qnty_sel bit in the main configuration 1 register (address 0100h) specifies whether one or two RAM chips are used. If two memory devices are used, separate chip select signals are generated. These chip selects are created from the decoded RAM addresses. The tram_size configuration bits, also in the main configu- ration 1 register, are used to select memory sizes of 32 Kbytes, 64 Kbytes, 128 Kbytes, or 256 Kbytes. Therefore, the maximum look-up table size of 512 Kbytes is realized when two RAM chips of 256 Kbytes each are used. If a single SRAM of 512 Kbytes is used (instead of two SRAMs of 256 Kbytes each), then bit 5 in the main configu- ration 1 register must be set to ‘1.’ If a single SRAM of 512 Kbytes is not used, this bit must be cleared to ‘0.’

30 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8208

8 Look-Up Table (continued)

8.2 Organization

Organization is discussed in terms of 8-byte records. Differences in organization for 8-byte records and 16-byte records will be discussed in Section 8.4, Extended Records. The look-up table may be configured to support up to 64 ports when multi-PHY mode is used, effectively creating a separate look-up table for each port. All VPI, VCI, and OAM/RM records may be either 8 bytes or 16 bytes in length. (See Section 8.4, Extended Records for information on 16-byte records.) Figure 4 shows the translation RAM memory map for 8-byte records. OAM/RM translation records are located at the bottom of the memory space with 64 OAM/RM records used by each port. If the device is configured to support 64 ports, the first 4096 records will be used for OAM and RM trans- lation records. This translates to 32 Kbytes of memory for 8-byte records. The remaining memory is then used for VPI and VCI records. For 8-byte records, the base addresses of the OAM records are calculated from the following equation: OBA = PN × 8 × 64 In this equation, OBA is the OAM base address, PN is the port number, 8 is the number of bytes per record, and 64 is the number of records per port. For example, the OAM/RM translation records for port 2 will have a base address of 1024 or 400h. Note: If the device is configured to use less than 64 ports, the OAM/RM translation record memory space will be allocated enough memory to handle ports 0 through the maximum port number used. For example, if the device is configured to use ports 0, 2, 4, and 6 (see Section 9, UTOPIA Interface), the OAM/RM translation record memory space will use 448 records (for ports 0 through 6). OAM/RM translation record memory space for ports 1, 3, and 5 will be skipped even though the ports are not used. Note: If the device is configured in PHY mode (see Section 9, UTOPIA Interface), the device supports only a single PHY and the translation RAM memory will be addressed as port 0. Separate VPI record base addresses may be set up for each port in multi-PHY mode, and the number of incoming VPI bits used as a pointer into the look-up table may be programmed. (See Section 14.3, Extended Memory Regis- ters, Table 153, PHY Port X Configuration Structure (PPXCF) (4200h to 42FEh).) For 8-byte records, the total memory used by the VPI records is calculated using the following equation: MS = NP x 2 NB x 8 In this equation, MS is the memory size used for VPI records, NP is the number of ports used, 8 is the number of bytes per record, and NB is the number of incoming VPI bits used to address the look-up table. This calculated memory space must be reserved for VPI records.

Figure 4. Translation RAM Memory Map—8-Byte Records Figure 5. There are two types of VPI translation records: one for VPI translation only and one for VPI/VCI transla- only bits 3 through 18 are stored in the VPI record. translation record. Other control bits in these records are described following Figure 5.

• +0130h Reserved
• • 7A00h OAM Cell Routing Port 61 7C00h OAM Cell Routing Port 62 7E00h OAM Cell Routing Port 63 +01F8h Reserved 8000h Any Purpose Look-Up Memory Shared Between Each of the 64 Ports 7FFFFh

Figure 5. Translation Record Types—8-Byte Records

is used in all types of records. be used to achieve this masking. the software can populate the look-up tables of two T8208 devices (one active and one inactive for redundancy). Table 12. Active and Ignore Truth Table 0 0 The cell is discarded, considered misrouted, and counted as a received cell. 0 1 The cell is discarded, is not flagged as misrouted, and is not counted as a received cell. 1 0 The cell is valid and is counted as a received cell. 1 1 The cell is discarded, is not flagged as misrouted, and is not counted as a received cell.

the appropriate OAM/RM F5 record. This bit is used only in VPI and VCI records. performed. This bit is used only in VPI records. ing bits in the VPI record. See the truth table (Table 13) below. This bit is used in VPI only translation records. bits in the VPI record. See the truth table (Table 13) below. This bit is used in VPI only translation records. Table 13. VPI Value Truth Table ■ OAM Routing Control (C1, C0). These 2 bits determine if the cell is routed as OAM/RM and if VPI/VCI translation is performed. See the truth table (Table 14) below. These bits are used only in OAM/RM records. Table 14. OAM Routing Control Truth Table

1. The most significant 4 bits of the VPI will only be substituted if the global rplc_gfc bit in the direct configuration/control register (address 28h)

is set in UNI mode or if the port is configured in NNI mode. 0 0 No VPI translation is performed. 01 VPI translation is performed only on bits 0—7 of the incoming VPI. 1 0 VPI translation is performed only on bits 8—11 of the incoming VPI. 1 1 Complete VPI translation is performed. dem routing headers in the OAM/RM record.

8.3 Look-Up Procedure

lutX_vpi_chk bit is set, all unused VPI bits in the cell header must be ‘0,’ or the cell will be considered out of range. is out of range, it is discarded and not counted as a received cell. valid, the enable OAM/RM routing (E) bit is consulted to determine if F4 type OAM cell treatment should occur. translation record address is the sum of the port’s OAM base address and 100h. routing header are then added to the cell, and the cell is transmitted on the cell bus. tion 8.2, Organization.) Again, the validity of the VCI translation record is determined by checking its A and I bits. Table 15. F5 Translation Record Addresses Table— 8-Byte Records

36 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8208 Next, the validity of the F5 OAM record is determined by checking its A and I bits. If it is valid, the cell is routed as described by the OAM routing control (C1, C0) bits. (See the definition for these bits in Section 8.2, Organization.) If the E bit in the VCI record is not one or if the C1 and C0 bits in the OAM record are zero and one, respectively, the cell does not receive OAM routing. If the cell is not routed as an OAM cell, information in the VCI translation record is used to route the cell. The cell's VPI and VCI are replaced with the VPI and VCI, respectively, in the VCI record. The most significant 4 bits of the VPI will only be substituted if the global rplc_gfc bit in the direct configura- tion/control register (address 28h) is set or if the port is configured in NNI mode. The cell bus routing header and tandem routing header are then added to the cell, and the cell is transmitted on the cell bus. Note: Unused OAM cell routing records in the LUT memory space can be used for other purposes.

This look-up procedure is outlined in the flow diagram below. Figure 6. Translation RAM Flow Diagram

38 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8208

8.4 Extended Records

The length of the translation records may be extended to 16 bytes to support two cell counts for each translation record. The lut_rec_form bits in the extended LUT configuration register (address 0138h) are used to select this extended mode. In extended (16-byte) mode, two 32-bit counters are appended to the 8-byte records. The first counter in the translation record, total cell count, keeps a total count of all incoming cells received from the UTOPIA bus whether ultimately routed or discarded except those in which the VPI is out of range. See the defini- tion of the A and I bits in Section 8.2, Organization. The second counter, special cell count, is a subset of the total cell count counter. This counter counts only cells whose PTI and CLP values in the cell header match the values specified in the extended LUT control register (address 0120h). For example, this counter may be used to track specific F5 type OAM/RM cells and cells indicat- ing forward congestion (EFCI = 1) or lower priority (CLP = 1).

The four translation record types for extended mode are illustrated in Figure 7 below. Figure 7. Translation Record Types—Extended Mode

40 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8208 Because the translation records are larger in extended mode, the look-up table memory map changes, the transla- tion record address calculations change, and the memory size calculations change. Figure 8 shows the new trans- lation RAM memory map for 16-byte records when the device is configured for 64 PHY ports. Figure 8 . Translation RAM Memory Map—Extended Mode Routing Look-Up Memory Map OAM Cell Routing Port X Record Map 0000h OAM Cell Routing Port 0 +0000h VP OAM VCI = 0 (F4) 0400h OAM Cell Routing Port 1 • 0800h OAM Cell Routing Port 2 0C00h OAM Cell Routing Port 3 1000h OAM Cell Routing Port 4 +01F0h VP OAM VCI = 31 (F4) 1400h OAM Cell Routing Port 5 +0200h VP OAM VCI = 6 & PT = “110” (F4) (RM-VPC) 1800h OAM Cell Routing Port 6 +0210h VC OAM PTI = “100” (F5) 1C00h OAM Cell Routing Port 7 +0220h VC OAM PTI = “101” (F5) 2000h OAM Cell Routing Port 8 +0230h VC OAM PTI = “110” (F5) 2400h OAM Cell Routing Port 9 +0240h VC OAM PTI = “111” (F5) 2800h OAM Cell Routing Port 10 +0250h Reserved

• +0260h Reserved
• • F400h OAM Cell Routing Port 61 F800h OAM Cell Routing Port 62 FC00h OAM Cell Routing Port 63 +03F0h Reserved 10000h Any Purpose Look-Up Memory Shared Between Each of the 64 Ports 7FFFFh

64 is the number of records per port. table. The OAM translation record address is the sum of this offset and the port’s OAM base address. Table 16. F5 Translation Record Addresses Table— Extended Mode bytes per record, and NB is the number of incoming VPI bits used to address the look-up table. through 18 of the VPI base address are stored in the PHY port X configuration structure. 180) to obtain the final address.

42 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8208

8.5 Diagnostics

The T8208 also includes diagnostics to track misrouted cells. A cell is considered misrouted if its A and I bits are “00,” if its VCI is out of range, or if the lutX_vpi_chk bit is ‘1’ and the unused VPI bits in the incoming cell header are not all zero (see Section 8.3, Look-Up Procedure). When a misrouted cell is detected, the misrouted cell header high and low registers (addresses 0146h and 0148h) may be updated. If enabled, the mis_cell interrupt, the vci_or interrupt, or the vpi_or interrupt will be generated as appropriate (see Table 96 in Section 14.3, Extended Memory Registers). The misrouted cell header high and low registers contain the first four header bytes of selected misrouted cells. Only a misrouted cell from a port whose mis_cell_lut_sel bit is set will update these registers, and this misrouted cell will update the registers only if it is the first received after the mis_cell_clr bit is set. The lst_mis_cell_lut bits indicate the port from which the header bytes in the misrouted cell header high and low registers were received. The mis_cell_lut_sel bits are located in the misrouted LUT 0, 1, 2, and 3 registers (addresses 0142h, 0140h, 013Eh, and 013Ch respectively). The mis_cell_clr, mis_cell_latch, and lst_mis_cell_lut bits are located in the mis- routed LUT 4 register (address 0144h). (See Tables 77, 78, 79, 80, and 81 in Section 14.3, Extended Memory Reg- isters, for a complete description of the above bits.)

8.6 Setup

When configuring the lut_en bits in the LUT X configuration/status register (addresses 0320h through 039Eh), care must be taken to ensure that the enabled ports’ LUTs correspond to the ports chosen in UTOPIA mode. (See Sec- tion 9.6, UTOPIA Pin Modes.) If a LUT is not enabled, corresponding bits in the PHY port X configuration structure (Section 14.3.2.4, RX UTOPIA Configuration Monitoring, Table 153) will be ignored. Also, when the device is con- figured for UTOPIA PHY mode (see Section 9, UTOPIA Interface), only port 0 entries in the external RAM look-up table are used; therefore, the look-up table should be set up accordingly.

8.7 LUT Bypass

This feature allows the elimination of the SRAM (which has the LUT information) in implementations that can pro- vide the cell bus routing header (CBRH) and the tandem routing header (TRH) to the T8208 device. This feature is enabled when bit 6 in register 0100h is set to ‘1.’ When this LUT bypass feature is enabled, the T8208 is expecting 58-byte cells in 16-bit UTOPIA mode and 57-byte cells in 8-bit UTOPIA mode on Rx UTOPIA. If bit 7 in register 0100h is cleared to ‘0,’ then the T8208 device expects to see the TRH before the CBRH on the incoming cells. But, if bit 7 in register 0100h is set to ‘1,’ the T8208 device expects to see the CBRH before the TRH on the incoming cells.

Agere Systems Inc. 43 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8208

9 UTOPIA Interface

The CelXpres T8208 supports the ATM Forum’s UTOPIA level 1 and level 2 specifications for cell-level handshake and MPHY operation with rates up to 635 Mbits/s. The device may be configured as an ATM layer or as a PHY layer by programming the phyen* bit in the main configuration 1 register (address 0100h). The device may be configured for 16 data bit operation by setting utopia_16 bit (bit 7) in register 0112h. If the uto- pia-16 bit (bit 7) in register 0112h is cleared to ‘0,’ then the TX and RX UTOPIA interfaces of the T8208 are config- ured for 8 data bit operation. In UTOPIA 2, 16 bit data mode, a maximum of 32 MPHYs (64 queues) are supported. In UTOPIA 2, 8-bit data mode, a maximum of 64 MPHYs (128 queues) are supported. As an ATM layer, the device may interface with a single PHY layer or multiple PHY layers (up to 64). Also as an ATM layer, it may be configured for shared UTOPIA mode for 64 (8-bit data mode) or 32 (16-bit data mode) MPHYs. (Note that if shared UTOPIA mode is not used, the slave_en bit in the main configuration/control register (address 0110h) must be cleared at device setup.) In PHY mode, the T8208 functions as a single PHY device on the UTOPIA bus or as one of 31 PHY devices on the UTOPIA level 2 bus. In addition to the required UTOPIA signals, the T8208 supports an additional three transmit and three receive enable (u_txenb*[3:1] and u_rxenb*[3:1]) signals, an additional three transmit and three receive cell available (u_txclav[3:1] and u_rxclav[3:1]) signals, a transmit parity (u_txprty) signal, and a receive parity (u_rxprty) signal. The T8208 UTOPIA signal names begin with u_tx, for UTOPIA transmit, or u_rx, for UTOPIA receive. Refer- ences to transmit or receive are made relative to the UTOPIA data flow for the ATM layer UTOPIA interface. Therefore, signals starting with u_rx, such as u_rxenb*[3:0] and u_rxdata[15:0], are receive UTOPIA sig- nals for devices in ATM mode but are transmit UTOPIA signals for devices in PHY mode. Furthermore, sig- nals such as u_txclav[3:0] and u_txaddr[4:0] are transmit UTOPIA signals for devices in ATM mode but are receive UTOPIA signals for devices in PHY mode. The above ATM to PHY terminology will be used throughout this UTOPIA Interface section.

44 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8208

9 UTOPIA Interface (continued)

9.1 Incoming UTOPIA Cell Interface

9.1.1 Incoming PHY Mode (Cells Received by T8208)

In PHY mode, only one enable (u_rxenb*[0]) signal and one cell available (u_rxclav[0]) signal are used. The u_rxenb*[0] signal is an input connected to the ATM layer’s TxEnb* signal, and the u_rxclav[0] signal is an output connected to the ATM layer’s TxClav signal. As a PHY device, the T8208 uses only the LUT 0 configuration/status register (address 0320h) and PHY port 0 configuration structure register (addresses 4200h—4202h). For UTOPIA level 2 functionality, the PHY address is programmed in the addr_match bits of the UTOPIA configuration register (address 0114h), and the addr_clav_en bits of the main configuration 2 register (address 0112h) can be pro- grammed to any value mentioned in the register except “0000.” As specified in the UTOPIA level 2 specification, during the polling process, the T8208 drives the u_rxclav[0] signal during the clock cycle following the cycle in which its address appears on the u_rxaddr pins. The u_rxclav[0] pin goes high impedance when not selected to support MPHY operation. In UTOPIA level 1, the above level 2 bits are not meaningful; therefore, the addr_clav_en bits must be programmed to “0000,” the u_rxaddr pins must be grounded, and the addr_match bits cleared. When the T8208 device is in PHY mode, if bit 5 (dont_inhibit_rxphy_clav) of register 0112h is cleared to ‘0,’ the rx_clav signal is deasserted if the RX UTOPIA FIFO is considered full. If this bit is set to ‘1,’ the T8208 keeps the rx_clav signal always asserted high indicating the capability to accept cells even if the RX UTOPIA FIFO could overrun, or is actually overrun.

9.1.2 Incoming ATM Mode (Cells Received by T8208)

In ATM mode, the T8208 may connect to PHY devices that either meet level 1 or level 2 UTOPIA specifications. If the connection is to devices that meet only UTOPIA level 1 specifications, the T8208 may access up to four of these PHY devices using the four enable (u_rxenb*[3:0]) and cell available (u_rxclav[3:0]) signals. Connection to more than one PHY device is possible only if the PHY’s data, start of cell, and parity outputs go high impedance when the device is not enabled. Polling of the cell available signals usually occurs while the current cell is received. If the T8208 connects to PHY devices meeting level 2 UTOPIA specifications, in 8-bit data mode, up to 64 MPHY ports may be accessed. In 8-bit UTOPIA 2 mode, 64 MPHYs are supported with four RxCLAV/RxENB pairs with 16-port addressing per RxCLAV/RxENB pair. For 32 PHY ports, two RxCLAV/RxENB pairs support two groups of 16 PHY ports for a total of 32 PHY ports. In 16-bit UTOPIA 2 mode, the T8208 supports 32 PHYs with four RxCLAV/RxENB pairs with 8-port addressing per RxCLAV/RxENB pair. In ATM MPHY mode, the u_rxdata[15:0], u_rxaddr[4:0], u_rxsoc, and u_rxprty signals are connected to each PHY port. In addition, the T8208 generates the address (u_rxaddr[4:0]) signals, permitting selection and arbitration among the MPHY ports. The number of address lines used in the connection may vary from one to four, giving a maximum address value of 15. (All five address lines must be connected to provide for the NULL address.) Refer to Section 9.6, UTOPIA Pin Modes, for more information about the possible combinations of address, cell available, and enable signals. The UTOPIA specification for operation with one TxClav and one RxClav is used when the T8208 connects to multiple level 2 PHY devices. Whether the T8208 is connected to several level 1 or level 2 PHY devices, a round robin algorithm is implemented that ensures that all PHY devices are serviced (accessed) in a timely manner. In addition, the number of clock cycles wasted for bus arbitration is minimized because polling is performed during cell transfer. In ATM mode, all unused u_rxclav inputs require connection to ground. Note:The u_rxenb outputs are high impedance during powerup and reset. An attached PHY may interpret this high-impedance state as an enable; however, the T8208 is not ready to properly handle input data during this time. Attach pull-up resistors to these outputs if a problem is anticipated. When the T8208 is in ATM mode, if bit 6 (inhibit_rxuto_fifo_overrun) of register 0112h is set to ‘1,’ the T8208 pre- vents the RX UTOPIA FIFO from overflowing by deasserting its rx_enb* signal even though the rx_clav signal is high when polled, if the RX UTOPIA FIFO is considered full. If this bit is cleared to ‘0,’ the rx_enb* signal is not deasserted even if the RX UTOPIA FIFO is considered full.

Agere Systems Inc. 45 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8208

9.2 Outgoing UTOPIA Cell Interface

9.2.1 Outgoing PHY Mode (Cells Sent by T8208)

In PHY mode, only one enable (u_txenb*[0]) signal and one cell available (u_txclav[0]) signal are used. The u_txenb*[0] signal is an input connected to the ATM layer’s RxEnb* signal, and the u_txclav[0] signal is an output connected to the ATM layer’s RxClav signal. As a PHY device, the T8208 may use queue group 0 (queues 0, 1, 2, and 3) in the SDRAM and TX UTOPIA cell buffer. The div_queue bits in the main configuration 2 register (address 0112h) may be programmed to “000” for 4 queues or “111” for 1 queue, and the port_rte[127:0] bits in the TX PHY FIFO routing 0, 1, 2, 3, 4, 5, 6, and 7 registers (addresses 0170h, 0172h, 0174h, 0176h, 0178h, 017Ah, 017Ch, and 017Eh) must be programmed to zero. If only queue 0 is used, configure and use only the queue 0 registers at addresses 0440h and 2000h through 2016h. Also, if only queue 0 is used, program the mphy_select bits and priority_select bits in the routing information 1, 2, 3, and 4 registers addresses 0200h, 0202h, 0204h, and 0214h to the zero value of “110000.” If queues 0, 1, 2, and 3 are used, configure and use only the queue 0, 1, 2, and 3 reg- isters at addresses 0440h through 0446h and 2000h through 2076h. Also, if queues 0, 1, 2, and 3 are used, only the mphy_select bits in the routing information 1, 2, and 4 registers (addresses 0200h, 0202h, and 0214h) must all be programmed to the zero value of “110000.” For UTOPIA level 2 functionality, the PHY address is programmed in the addr_match bits of UTOPIA configuration register (address 0114h), and the addr_clav_en bits of the main configuration 2 register (address 0112h) can be programmed to any value mentioned in the register except “0000.” As specified in the UTOPIA level 2 specifica- tion, the T8208 drives the u_txclav[0] signal during the clock cycle following the one with its address on the u_txaddr pins. The u_txclav[0] pin goes high impedance when not selected to support MPHY operation. When the tx_utopia_hi_z bit in the main configuration 1 register (address 0100h) is cleared, the u_txsoc, u_txdata[7:0], and u_txprty outputs go high impedance when not selected, allowing multiple PHYs to be connected on the same UTO- PIA bus. In UTOPIA level 1, the above level 2 bits are not meaningful; therefore, the addr_clav_en bits must be programmed to “0000,” the u_txaddr pins must be grounded, and the addr_match bits cleared. Note:If the SDRAM is bypassed, the TX UTOPIA cell buffer in the T8208 device can be divided into a minimum of 1 queue and a maximum of 128 queues. Note:Even though the outgoing (egress) queues are 0—3, the egress port is determined by the address match bits in register 0114h.

46 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8208

9.2.2 Outgoing ATM Mode (Cells Sent by T8208)

In ATM mode, the T8208 may connect to PHY devices that either meet level 1 or level 2 UTOPIA specifications. If connection is to devices that meet only UTOPIA level 1 specifications, the T8208 may access up to four of these PHY devices using the four enable (u_txenb*[3:0]) and cell available (u_txclav[3:0]) signals. Polling of the cell avail- able signals occurs while the current cell is transmitted. If the T8208 connects to PHY devices meeting level 2 UTOPIA specifications, in 8-bit data mode, up to 64 MPHY ports may be accessed. In 8-bit UTOPIA 2 mode, 64 MPHYs are supported with four TxCLAV/TxENB pairs with 16-port addressing per TxCLAV/TxENB pair. For 32 PHY ports, two TxCLAV/TxENB pairs support two groups of 16 PHY ports for a total of 32 PHY ports. In 16-bit UTOPIA 2 mode, the T8208 supports 32 PHYs with four TxCLAV/TxENB pairs with 8-port addressing per TxCLAV/TxENB pair. In ATM MPHY mode, the u_txdata[15:0], u_txaddr[4:0], u_txsoc, and u_txprty signals are connected to each PHY port. In addition, the T8208 generates the address (u_txaddr[4:0]) signals, permitting selection and arbitration among the MPHY ports. The number of address lines used in the connection may vary from one to four, giving a maximum address value of 15. (All five address lines must be connected to provide for the NULL address.) Refer to Section 9.6, UTOPIA Pin Modes, for more information about the possible combinations of address, cell avail- able, and enable signals. The UTOPIA specification for operation with one TxClav and one RxClav is used when the T8208 connects to multiple UTOPIA 2 PHY devices. In ATM mode, all unused u_txclav inputs require connection to ground. Note:The u_txenb outputs are high impedance during powerup and reset. An attached PHY may interpret this high-impedance state as an enable; however, the T8208 is not ready to send data during this time. Attach pull-up resistors to these outputs if a problem is anticipated. The TX UTOPIA cell buffer holds the next cells to be transmitted onto the UTOPIA bus. This TX UTOPIA cell buffer, which holds 256 cells, may be divided into 1, 4, 8, 16, 32, 64, or 128 queues using the div_queue bits in the main configuration 2 register (address 0112h). The number of ports that the T8208 supports determines the number of queues that should be chosen. (See Section 9.6, UTOPIA Pin Modes.) The number of cells per queue, held by the buffer, is determined by dividing 256 (maximum number of cells that TX UTOPIA cell buffer holds) by the number of queues selected (e.g., two cells per queue for 128 queues and 64 cells per queue for four queues).

Agere Systems Inc. 47 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8208 Each port is assigned four queues in the TX UTOPIA cell buffer except in the case of 64 ports (for 8-bit UTOPIA) and 32 ports (for 16-bit UTOPIA). In the case of 64 ports (for 8-bit UTOPIA) and 32 ports (for 16-bit UTOPIA), each port is assigned two queues or a programmable number of queues per PHY. Each group of four queues is priority encoded where the lowest-numbered queue has the highest priority. Groups of four queues are shared among two ports as follows: ■ Queues 0—3 are shared between ports 0 and 1. ■ Queues 4—7 are shared between ports 2 and 3. ■ Queues 8—11 are shared between ports 4 and 5. ■ Queues 12—15 are shared between ports 6 and 7. ■ Queues 16—19 are shared between ports 8 and 9. ■ Queues 20—23 are shared between ports 10 and 11. ■ Queues 24—27 are shared between ports 12 and 13. ■ Queues 28—31 are shared between ports 14 and 15. ■ Queues 32—35 are shared between ports 16 and 17. ■ Queues 36—39 are shared between ports 18 and 19. ■ Queues 40—43 are shared between ports 20 and 21. ■ Queues 44—47 are shared between ports 22 and 23. ■ Queues 48—51 are shared between ports 24 and 25. ■ Queues 52—55 are shared between ports 26 and 27. ■ Queues 56—59 are shared between ports 28 and 29. ■ Queues 60—63 are shared between ports 30 and 31. ■ Queues 64—67 are shared between ports 32 and 33. ■ Queues 68—71 are shared between ports 34 and 35. ■ Queues 72—75 are shared between ports 36 and 37. ■ Queues 76—79 are shared between ports 38 and 39. ■ Queues 80—83 are shared between ports 40 and 41. ■ Queues 84—87 are shared between ports 42 and 43. ■ Queues 88—91 are shared between ports 44 and 45. ■ Queues 92—95 are shared between ports 46 and 47. ■ Queues 96—99 are shared between ports 48 and 49. ■ Queues 100—103 are shared between ports 50 and 51. ■ Queues 104—107 are shared between ports 52 and 53. ■ Queues 108—111 are shared between ports 54 and 55. ■ Queues 112—115 are shared between ports 56 and 57. ■ Queues 116—119 are shared between ports 58 and 59. ■ Queues 120—123 are shared between ports 60 and 61. ■ Queues 124—127 are shared between ports 62 and 63.

Figure 9. Queue Priority Multiplexing because polling is performed during cell transfer. lates the HEC and inserts it into each cell before transmitting it onto the UTOPIA bus. See Figure 10.

9.3 Counters

14.3.2.2, TX UTOPIA Monitoring, for the addresses of other ports' outgoing cell counters.

9.3.1 Dropped Cell Counters

discarded since last read by the microprocessor if clear_on_read is enabled. The drop cell counters for the remaining queues (1 to 127) are at addresses 3004h to 31FEh. [7:0] byte. Clearing the sp_utopia_sel* bit in the main configuration 1 register (address 0100h) enables this mode. Figure 10. TX UTOPIA Cell Handling

50 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8208

9.5 Shared UTOPIA Mode

The shared UTOPIA mode allows two T8208 devices on different cell buses to share the same UTOPIA bus. Shared UTOPIA mode functionality requires the T8208 devices to be configured for ATM mode. This configuration is supported for both UTOPIA level 1 and 2 configurations. The shared mode can be used to provide system back- plane redundancy or to increase the cell bus system capacity. One T8208 device is configured as master and the other as slave, using the slave_en bit in the main configuration/control register (address 110h). The master and the slave communicate to each other through the shared UTOPIA pins; u_shr_grant[1:0] and u_shr_req[3:0]. For the master, u_shr_grant[1:0] functions as the grant outputs for the cell of specific queue to be sent, and the u_shr_req[3:0] pins function as the request inputs to identify which cell of the 128 queues is to be sent. For the slave, u_shr_grant[1:0] functions as the grant input, and u_shr_req[3:0] as the request output. The configuration for the addr_clav_en bits must be the same in both devices in MCF2 (0112h) and port_rte (0170h to 017Eh) registers. Note: The T8208 will support shared UTOPIA mode for up to 128 queues (64 MPHYs) in 8-bit UTOPIA mode and will support only 64 queues (32 MPHYs) in 16-bit UTOPIA mode. The TX UTOPIA cell buffers in the master and the slave may be divided into the same number of queues or differ- ent number of queues. The register settings for mast_queue_in[127:112], mast_queue_in[111:96], mast_queue_in[95:80], mast_queue_in[79:64] mast_queue_in[63:48], mast_queue_in[47:32], mast_queue_in[31:16], mast_queue_in[15:0] and slav_queue_in[127:112], slav_queue_in[111:96], slav_queue_in[95:80], slav_queue_in[79:64] slav_queue_in[63:48], slav_queue_in[47:32], slav_queue_in[31:16], and slav_queue_in[15:0] must be configured in the master device. These bits indicate which queues in the master and which queues in the slave are enabled. The master's priority algorithm uses its mast_queue_in information to determine which waiting cell should be transmitted. The slav_queue_in (0160h to 016Eh) registers are ignored in the slave. The transmit operation in shared UTOPIA mode is illustrated in Figure 11 for 8-bit UTOPIA mode and Figure 12 for 16-bit UTOPIA mode. For the transmit interface, all enable, start of cell, and data signals occur relative to the low- going start of grant signal from the master. The start of grant signal occurs every 60 clock cycles for 8-bit UTOPIA mode and 34 clock cycles for 16-bit UTOPIA mode and is always preceded by at least six clock cycles of ones. Both devices can transmit on the TX UTOPIA bus; the master arbitrates the bus and grants the slave access via the u_shr_grant pins. When the slave has cells waiting for transmission, it makes a request for each queue (up to 128 in 8-bit UTOPIA mode and 64 in 16-bit UTOPIA mode) that contains cells. To make this request, the slave pulls its u_shr_req pins low for one clock cycle during the queue's request period. The request clock period for each queue is assigned relative to the master's start of grant signal. The request period for first group of queues occurs ten clock cycles after the falling edge of the start of grant. In 8-bit UTOPIA mode, the next 31 clock cycles evaluate queues 4 to 127 and a low bit for the corresponding queue in the 128 queues represents the queue containing a cell to be sent. In 16-bit UTOPIA mode, the next 15 clock cycles evaluate queues 4 to 63 and a low bit for the cor- responding queue in the 64 queues represents the queue containing a cell to be sent. The master uses the received queue requests and a priority algorithm to determine if a slave's cell should be trans- mitted before one of its own. Both master and slave have an equal chance to transmit cells if the cells have equal priority. The first bit in grant[0] is the low-going grant signal. The next six clock cycles designate the queue number of the cell to be transmitted which only requires 7 of the bits to represent any of the 128 queues in 8-bit UTOPIA mode and 6 bits to represent any of the 64 queues in 16-bit UTOPIA mode. The additional bits in the six clock cycles are reserved. The slave then has 53 cycles (8-bit UTOPIA mode) or 27 cycles (16-bit UTOPIA mode) or 55/28 cycles to transmit its cell depending on the mode.

slave monitors these signals to determine when the cell starts and which port is sending the cell. nals to a high-impedance state when inactive. Figure 11. TX UTOPIA Bus Sharing for 8-Bit UTOPIA Mode

Figure 12. TX UTOPIA Bus Sharing for 16-Bit UTOPIA Mode

9.6 UTOPIA Pin Modes

9.6.1 UTOPIA Pin Modes for 8-Bit UTOPIA Operation

possible configurations for 8-bit UTOPIA operation.

per PHY in this configuration. require connection to ground. Four queues are allocated per PHY in this configuration. per PHY in this configuration. queues can be allocated per PHY based on the settings in registers 0170h—017Eh. Table 17. Pin Configuration for 8-Bit UTOPIA

Table 17. Pin Configuration for 8-Bit UTOPIA (continued)

56 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8208

9.6.2 UTOPIA Pin Modes for 16-Bit UTOPIA Operation

In multi-PHY mode, the T8208 interfaces with up to 32 PHY ports in 16-bit UTOPIA operation. Each port is num- bered and accessed using a certain combination of the cell available/enable (Clav/Enb*) and address (Addr) sig- nals. The addr_clav_en bits in the main configuration 2 register (address 0112h) are used to select this combination of cell available/enable and address signals. Table 18 indicates the port numbering for each of the possible configurations for 16-bit UTOPIA operation. The first selection of zero address and four cell available/enable signals (a value of “0000” in bits 3:0 of register 0112h) is used for connection to UTOPIA level one devices. Use this selection to connect from one to four PHY devices to the T8208 in ATM mode. If only one PHY is connected, any of the four cell available signals may be con- nected to the PHY. For two PHY devices, connect any two. All unused u_rxclav inputs require connection to ground. Four queues are allocated per PHY in this configuration. The second selection of one address and four cell available/enable signals (a value of “0010” in bits 3:0 of register 0112h) is used for connection to UTOPIA level two devices. The selection may be used for up to four PHY groups of two ports each. (See Appendix 1 of The ATM Forum Technical Committee UTOPIA Level 2, Version 1.0 specifi- cation.) All unused u_rxclav inputs require connection to ground. Four queues are allocated per PHY in this config- uration. The third selection of two address and four cell available/enable signals (a value of “0101” in bits 3:0 of register 0112h) is used for connection to four UTOPIA level 2 PHY groups of four ports each. Four queues are allocated per PHY in this configuration. The fourth selection of three address and four cell available/enable signals (a value of “1001” in bits 3:0 of register 0112h) is used for connection to four UTOPIA level 2 PHY groups of eight ports each. Two queues are allocated per PHY if the normal 64-port mode described in Section 11.4 Queuing is used or a programmable number of queues can be allocated per PHY based on the settings in registers 0170h—017Eh.

Table 18. Pin Configuration for 16-Bit UTOPIA

58 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8208

9.7 UTOPIA Clocking

All TX UTOPIA signals in the T8208 are clocked on the rising edge of the TX UTOPIA clock, and all RX UTOPIA signals are clocked on the rising edge of the RX UTOPIA clock. The UTOPIA specifications state that the ATM layer supplies the transmit and receive UTOPIA interface clocks to the PHY layers. The T8208 may be configured to drive these clocks or to be driven by them. In the T8208, the clocks for transmit and receive UTOPIA interfaces may be independently derived from several sources. In addition, each of these clocks may be independently configured. The TX UTOPIA clock configuration (address 010Ch) and RX UTOPIA clock configuration (address 010Eh) registers are used to select and configure the transmit UTOPIA interface and the receive UTOPIA interface clocks, respectively. See these register descrip- tions for more information.

9.8 Option for Counters to Clear on Read

All the counters (addresses 0600h—06FEh, 3000h—31FEh, 4000h—40FEh, and total and special cell counters of the look-up record if the extended records mode is selected) can be cleared automatically when read by the micro- processor, if the clear_on_read bit (bit 12 in register 0112h) is set to ‘1.’ Both the registers for every PHY (and every queue for dropped cell count) must be read consecutively, (bits 31:16 first, bits 15:0 next) so that both the registers can be cleared automatically. If this bit (bit 12 in register 0112h) is cleared to ‘0’ then the microprocessor will have to clear the counters individu- ally by writing a ‘0’ to them after reading, if it is needed.

Agere Systems Inc. 59 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8208

10 Cell Bus Interface

10.1 General Architecture

The high bandwidth, 32-bit cell bus is used to interconnect T8208 devices. Up to 32 devices may be connected to the bus, and cell exchange may occur between any of these devices. Each cell bus frame is 16 clock cycles, and during these 16 cycles, one cell is transmitted. The T8208 is designed to operate with a maximum cell bus fre- quency of 66 MHz, which translates to a cell bandwidth of 1.7 Gbits/s. The maximum achievable frequency for a given bus implementation is dependent on loading and other design considerations. In addition to the 32 bits of data, the cell bus uses four additional control signals. The four signals include a read clock, a write clock, a frame synchronization signal, and an acknowledge signal. The read and write clocks (cb_rc* and cb_wc* pins, respectively) establish the timing for reading and writing cells on the bus and can be generated internally from the T8208 device or from an external clock source. The internal clock source offers the capability to program the required timing skew between write and read clocks. Separate pins are provided for the read and write clock signals. The read clock is used to read the cell from the cell bus, and the write clock is used to write the cell to the cell bus. Because all devices on the cell bus read and write on the same clock edge, the write clock is delayed slightly, relative to the read clock, to ensure sufficient data hold time. The active-low frame sync (cb_fs*) is generated by the bus arbiter and indicates the first cycle of the cell bus frame in 16-user mode or the first cycle of two cell bus frames for 32-user mode. This signal is generated every 16 clock cycles for 16-user mode or every 32 clock cycles for 32-user mode. The acknowledge (cb_ack*) signal is used to acknowledge the successful receipt of a cell. This signal is asserted low during the next request cycle by the T8208 that receives the cell. This signal is not asserted for multicast or broadcast cells. In the event of an overflow in the control cell RX FIFO, the loopback FIFO, the TX PHY FIFO, or the cell bus input FIFO, the acknowledge signal will assert low. In the case of an overflow, this signal will not assert low for multicast and broadcast cells. When cb_disable* is asserted, the device can receive data on the cb_d*[31:0] but cannot transmit data. The device cannot assert the cb_ack* even when a valid cell is received from the cell bus, if cb_disable* is asserted. Several T8208 devices may reside on the cell bus, but one device must be configured as bus arbiter by clearing the cb_arb_sel bit in the cell bus configuration/status register (address 0130h) or by pulling the arb_en* lead low. The cell bus arbiter receives requests for access to the bus from all resident devices during the first cycle of the cell bus frame and grants one of these requests during the last cycle of the cell bus frame. Before issuing the grant and while a cell is transmitted on the cell bus, the arbiter executes its arbitration algorithm to determine the next device to transmit on the bus. The arbiter also generates the frame synchronization signal. Software will designate only one device as cell bus arbiter, at any given time, to ensure proper operation of the bus. A 5-bit unit address is assigned to each device (up to 32) on the bus. Each device uses this address to request cell transmission and to identify incoming cells destined for them. Each device is given a unique unit address by indi- vidually tying each address (ua*[4:0]) input high or low. The unit address inputs are active-low; therefore, a device with its ua*[4:0] inputs tied to “10000” has address 15. Each device can also be given a unique unit address by writing the address into bits 4:0 in register 0130h, provided bit 7 in register 0130h is also set to 1. The device makes a cell transmission request by driving the two assigned bits during the request cycle, which is the first cycle of a frame. For example, device 15 uses bits 30 and 31 of the request cycle as its request bits. (See Section 10.2, Cell Bus Frames.) Also, each device uses its unit address to determine if a received cell is destined for it. (See Section 10.3, Cell Bus Routing Headers.)

60 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8208

10 Cell Bus Interface (continued)

The cell bus may be configured for 16-user or 32-user mode, using the cb_usr_mode bit in the cell bus configura- tion/status register (address 0130h). In 16-user mode, all 16 devices assert their transmission requests during the first cycle of each frame, and the transmission grant for the next frame is given during the last cycle of the frame. In 32-user mode, the frame synchronization signal is asserted every two cell bus frames. The two frames are termed the odd and even frames. The frame synchronization signal marks the beginning of the even frame, and the odd frame starts 16 clock cycles later. During the request cycle of the even frame, devices zero through 15 assert their transmission requests, and during the request cycle of the odd frame, devices 16 through 31 assert theirs. Requests received from odd and even frames are serviced as a group, and grants are given in the order that the requests are received with the highest priority serviced first with the same priority requests serviced using a round robin algorithm. Transmission grants for the next frame are always given at the end of the current frame. Cells to be transmitted onto the cell bus come from three sources internal to the T8208. Data cells from the UTO- PIA bus are placed in the RX PHY FIFO to await transmission onto the cell bus. Control cells from the microproces- sor wait in the control cell TX FIFO, and loopback cells from the cell bus wait in the loopback FIFO. Cells from these three FIFOs are priority multiplexed onto the cell bus output FIFO to be transmitted onto the cell bus. Optional high priority can be established for data cells or control cells sent to the cell bus. If bit 9 in register 0130h is cleared to ‘0’ then cells from the RX PHY FIFO have the highest priority, cells from the control cell TX FIFO have next highest, and finally, cells from the loopback FIFO have the lowest. If bit 9 in register 0130h is set to ‘1,’ then cells from the control cell TX FIFO have the highest priority, cells from the RX PHY FIFO have the next highest pri- ority, and finally, cells from the loopback FIFO have the lowest priority. This bit on default is ‘0.’ Incoming cells may be broadcast, multicast, or single address types. The T8208 receiving device accepts single address cells with an address field in the cell bus routing header that matches the device’s unit address. In addi- tion, the device accepts all broadcast cells and certain multicast cells that it is configured to accept. (See Section 10.3.4, Multicast Routing.) Before a cell is accepted, a check is done on the previous grant to verify whether it is a valid grant or not. The receiving device verifies the cell bus routing header cyclic redundancy check (CRC-4) value in the least significant 4 bits of the cell bus routing header. It also verifies the bit interleave parity (BIP-8) value from bits 24 to 31 of the last cell bus frame cycle. If either is corrupt, the cell is discarded. If kept, cells are routed to the loopback FIFO, control FIFO, or TX PHY FIFO, based on the information in its cell bus routing header. See Section 10.3, Cell Bus Routing Headers.

10.2 Cell Bus Frames

A cell bus frame is always 16 clock cycles. The cell bus frame has three sections (request, bus cell, and grant). onto the bus. During the bus cell section, which is the next 14 clock cycles, a cell is transmitted on the cell bus. Figure 13. Cell Bus Frame Format (Bit Positions for 16-User Mode)

Figure 14. Cell Bus Frame Format (Bit Positions for 32-User Mode)

Agere Systems Inc. 63 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8208 Devices on the cell bus make their requests during the first cycle of each frame. In 16-user mode, each device asserts a request every frame. In 32-user mode, each device asserts a request every two frames. In 32-user mode, devices with unit addresses 0 through 15 assert their requests during the even frames, and devices with unit addresses 16 through 31 assert their requests during the odd frames. During cycle 0 of their assigned frame, each device drives two of the 32 data bits available. The position of the two request bits for each device is based on the device’s unit address. The assigned bit positions for each device are illustrated in Figure 13 and Figure 14 for 16-user and 32-user modes, respectively. For example, in the figures, the device with unit address 0 makes its requests using the 2 bits labeled as U0. Two bits, instead of one, are used for each device so the priority of the request may be included. The priority of the request is set up using the cb_req_pr bits in the main configura- tion/control register (address 0110h). See Table 59 in Section 14.3, Extended Memory Registers, for more informa- tion. During clock cycles 1 through 14, the device that was granted the bus at the end of the previous frame sends its bus cell. The bus cell sent includes the cell bus routing header, the tandem routing header, and the original UTOPIA cell with the header error check (HEC) byte removed. The HEC byte is removed because the cell bus does its own error check over the complete cell using the bit interleave parity byte. The HEC byte is recreated and inserted before the received cell is placed on the UTOPIA bus. The cell bus routing header indicates the type of the cell (data, control, loopback) and its destination (single, multi- cast, broadcast). See Section 10.3, Cell Bus Routing Headers, for more information on the cell bus routing header structure. The tandem routing header is configured by the user. The 32 bits of the grant section of the frame (clock cycle 15) include the bit interleave parity (BIP-8) byte, the grant parity bit, the grant enable bit, and the grant number. The most significant 8 bits of the grant section of the frame is the BIP-8 byte. The BIP-8 byte is calculated over 54 bytes, starting with the first tandem routing header byte and ending with the last payload byte. To calculate this bit interleave parity, an exclusive-OR operation is performed on the first byte of the tandem routing header and the value “11111111.” The exclusive-OR operation then is performed on this result and the following byte. The operation is then repeated with every successive byte through the last data byte of the payload. The resulting byte becomes the BIP-8 byte of the grant section. The next 17 bits of the grant section are unused. The least significant 7 bits of the grant section are used to grant transmission requests. The grant number is located in the least significant 5 bits of the grant section and is the unit address of the device that transmits a cell during the next frame. The grant enable, bit 5, is an active-high signal that indicates if the grant is valid. Finally, the grant parity, bit 6, is the odd parity check calculated over the other six grant bits.

10.3 Cell Bus Routing Headers

T8208 device on the cell bus accepts all broadcast cells and certain multicast cells that it is configured to accept. routed as single address, may be data, control, or loopback cells. Figure 15. Cell Bus Routing Headers two do not match, the cell is discarded.

Agere Systems Inc. 65 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8208

10.3.1 Control Cells

The microprocessor connected to the T8208 may send control cells to the cell bus by writing the cell to the control cell transmit direct memory at addresses A0h to D7h (or extended memory at addresses 0900h to 0936h). After the cell is written to memory, the microprocessor sets the cntl_cell_wr bit in the main configuration/control register (address 0110h). This bit returns to zero when the cell is transmitted and memory is available to load a new control cell into the device. Control cells accepted from the cell bus are routed to the control cell RX FIFO. The microprocessor connected to the T8208 reads the control cell at the head of the FIFO using the control cell receive direct memory at addresses 5Ch to 93h (or extended memory at addresses 07FCh to 0832h). After the microprocessor reads the cell, it sets the cntl_cell_rd bit in the main configuration/control register (address 0110h) to remove the cell from the head of the FIFO. The microprocessor connected to the T8208 can read the cell bus routing header [15:0] and the tandem routing header [15:0] of the received control cell. The cell bus routing header [7:0] is at address 5Ch and the cell bus rout- ing header [15:8] is at address 5Dh. The tandem routing header [7:0] is at address 5Eh and the tandem routing header [15:8] is at address 5Fh.

10.3.2 Data Cells

Data cells accepted from the cell bus are routed to the TX PHY FIFO. From the TX PHY FIFO, the cell is routed to the appropriate transmit queue using the information about the cell's priority and the queue group to which it is des- tined. The priority of the cell is indicated by 2 bits obtained from the first 64 bits of the bus cell (cell bus routing header, tandem routing header, and ATM cell header). The position of these 2 bits in the cell are user programma- ble during configuration using the prior0_sel[5:0] and prior1_sel[5:0] bits of the routing information 3 register (address 0204h). The queue group to which the cell is destined is indicated by 5 bits obtained from the first 64 bits of the bus cell (cell bus routing header, tandem routing header, and ATM cell header). The position of these 5 bits in these headers are user programmable using the mphy1_sel[5:0] and mphy2_sel[5:0] bits of the routing informa- tion 1 register (address 0200h), the mphy0_sel[5:0] bits of the routing information 2 register (address 0202h) and the mphy3_sel[5:0] and mphy4_sel[5:0] bits of the routing information 3 register (address 0214h). See Tables 139, 140, 141, and 149 in Section 14.3, Extended Memory Registers. None of the priority or MPHY bits are required to be adjacent. For more information on queue groups, see Section 11.4, Queuing.

66 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8208

10.3.3 Loopback Cells

A loopback cell may be sent to the cell bus for diagnostic purposes. Initially, the loopback cell is sent from one T8208 (device 1) to a second T8208 (device 2). The second T8208 (device 2) returns the cell to the first T8208 (device 1), or, if desired, the second T8208 (device 2) may send the cell on to one or more entirely different T8208 devices. Device 2 accepts the loopback cell and replaces the most significant 12 bits of the cell bus routing header with the routing_header bits in its loopback register (address 0136h). The 12 routing_header bits in the loopback register correspond to the upper 12 bits of a single destination control cell header, a multicast control cell header, or a broadcast control cell header. To create a loopback path from device 1 to device 2, and back to device 1, coordinated control of device 1 and device 2 is needed. First, the microprocessor connected to device 2 sets up the loopback by writing the routing_header bits in the loopback register of device 2. The routing_header bits indicate a single destination con- trol cell with a unit address field for device 1. Second, the microprocessor connected to device 1 writes a loopback cell to the control cell transmit direct memory (addresses A0h to D7h) of device 1. (See Section 10.3.1, Control Cells, of this document.) The cell bus routing header of this cell is the single destination loopback type, and the unit address section of the header contains the address of device 2. To send the loopback cell, a ‘1' is then written to the cntl_cell_wr bit of the main configuration/control register (address 0110h). Care must be taken to ensure that the routing_header bits in a T8208 device are not changed until any previously set up loopback cell has been received and retransmitted. If these bits are changed prematurely, misrouting will occur. Instead of having to program the loopback register (0136h) of device 2, the tandem routing header of the incoming loopback cell (into device 2) can be used as the new cell bus routing header of the outgoing loopback cell. If the insert_cb_lpbk_hdr bit (bit 8 in register 0130h) is cleared to ‘0’ then the T8208 device uses the tandem routing header of the incoming loopback cell as the new cell bus routing header of the outgoing loopback cell and as a result, also inserts the programmed loopback header (in register 0136h) as the tandem routing header of the out- going loopback cell. If this bit (bit 8 in register 0130h) is set to ‘1’ the T8208 inserts the programmed loopback header (in register 0136h) as the new cell bus routing header of the loopback cell.

10.3.4 Multicast Routing

The T8208 may be programmed to accept certain multicast data cells using the multicast memories at addresses E0h through FFh (or C00h through C1Eh) and C20h through FFEh. The net numbers of accepted multicast control cells are programmed in the memory space E0h through FFh (or C00h through C1Eh) and C20h through FFEh. These memory spaces hold 256 bits each. Each bit represents a multicast net number from 0 to 255. Note:To prevent potential multicast memory errors, these memory spaces should be cleared during the initializa- tion process. For 8-bit UTOPIA ATM mode, the net numbers of accepted multicast data cells are programmed in the multicast number memories, which are divided among 32 queue groups. If 64 ports are used, each memory space is shared between two ports, e.g., ports zero and one use the memory assigned to PHY 0, ports two and three use the mem- ory assigned to PHY 1, and so on. For 16-bit UTOPIA ATM mode, the net numbers of accepted multicast data cells are programmed in the multicast number memories, which are divided among 16 queue groups. If 32 ports are used, each memory space is shared between two ports, e.g., ports zero and one use the memory assigned to PHY 0, ports two and three use the mem- ory assigned to PHY 1, and so on. The cell priority bits select the specific queue in the queue group to which the cell is routed. (See Section 11.4, Queuing). Note that multicast control cells use the same multicast number memory as PHY 0 multicast data cells. See Table 176 in Section 14.3, Extended Memory Registers and Table 53 in Section 14.2, Direct Memory Access Registers, respectively. For PHY mode, multicast cells are only transmitted to queue group 0, and only the PHY port 0 and control cell mul- ticast direct memory at addresses E0h through FFh (or C00h through C1Eh) is used. The cell priority determines the specific queue in queue group 0 to which the cell is routed. (See Section 10.3.2, Data Cells.)

Agere Systems Inc. 67 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8208

10.3.5 Broadcast Routing

Broadcast control cells are transmitted and received as described in Section 10.3.1, Control Cells. The broadcast control cell bus routing header has a broadcast control cell header type. For ATM mode, all PHY ports receive the broadcast data cell. The cell priority bits select the specific queue in the queue group to which the cell is routed. For PHY mode, if SDRAM is bypassed, broadcast data cells are only transmitted to queue 0. If the SDRAM is not bypassed, broadcast data cells are only transmitted to queue group 0, and only PHY port 0 is used (although the device will take the time to try to broadcast data cells to all the ports, cells will not be stored in queue groups other than 0).

10.4 Cell Bus Arbitration

One of the T8208 devices sharing the cell bus must be configured as bus arbiter by clearing the cb_arb_sel bit in the cell bus configuration/status register (address 0130h) or by pulling the arb_en* lead low. Using an arbitration algorithm, the arbiter decides the next device to transmit on the cell bus and issues the grant signals at the end of the cell bus frame. The arbiter also generates the active-low frame synchronization signal that occurs every 16 clock cycles in 16-user mode and every 32 clock cycles in 32-user mode. To grant transmission requests, the arbiter must analyze requests received during the request section of the cur- rent frame for 16-user mode or during two request cycles for 32-user mode. The arbitration algorithm used is round robin and based on the priority of the request and the last request granted. The arbiter circuitry in all T8208 devices on the cell bus will synchronize to the active arbiter on the cell bus. So, when an inactive device becomes the arbiter, it will begin sending frame synchronization signals that coincide to the clock cycle that the original arbiter would have sent its next frame synchronization signal. This prevents the new arbiter from misinterpreting random signals on its first request cycle as valid requests. The T8208 that has been configured as the bus arbiter can mask (remove) any of the active devices on the cell bus from the arbitration logic so that they will never be granted the bus. If any of the bits are set in register 12Eh (en_req_low_bp[15:0]) and register 12Ch (en_req_up_bp[15:0]), then the cell bus access requests from the corre- sponding unit address on the bus are enabled into the arbitration logic. If any of the bits are cleared to ‘0’, access requests are masked and ignored by the arbitration logic.

10.5 Cell Bus Monitoring

32-user mode. This bit is also set when the cell bus write clock is inactive for 32 mclk cycles. main configuration 3 register (address 0116h).

10.6 GTL+ Logic

nation resistors are typically placed at the ends of the bus of the backplane. TT and is created using the voltage divider shown in Figure 16B. pling capacitor on the cb_vref input. Figure 16. GTL+ External Circuitry

Agere Systems Inc. 69 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8208

10.7 Cell Bus Write and Read Clocks

The read and write clocks (cb_wc* and cb_rc* pins) are supplied from an external source. The write clock should be delayed 1.5 ns to 4 ns relative to the read clock to ensure sufficient data hold time. The position of the clock source relative to the cell bus devices on the card or on connecting cards determines the actual delay that should be used. When the clock source is centrally located among the cell bus devices, a longer delay may be used. When the clock source is at either end of the cell bus devices, a shorter delay is needed. Also, a higher clock fre- quency requires a shorter delay. The T8208 can generate both the read and write clocks internally for the cell bus logic, if bit 6 in register 2Eh is cleared to ‘0’ and bit 10 in register 122h is set to ‘1.’ It includes the ability to derive these clocks from several sources (PCLK or MCLK or PLL VCO frequency [twice the MCLK]) and set the skew between the read and write clocks with a programmable granularity (bits 15:13 in register 122h). This feature is useful if the digital loopback (see Section 10.9) is to be used when the card containing the T8208 is operated outside the system. If bit 6 in register 2Eh is cleared to ‘0’ and bit 10 in register 0122h is set to ‘1,’ then the generated read and write cell bus clocks not only drive the internal cell bus logic of this device but also come out on pins cb_gen_rc and cb_gen_wc (pins B4 and A3, respectively) of this device which can then be used to drive the remaining devices on the backplane. Note: Due to the inherent propagation delay between the clocks that drive the cell bus logic of the generating device and the other devices on the backplane, it is recommended that customers set bit 6 in register 2Eh to ‘1’ and set bit 10 in register 0122h to ‘1’ and route these generated clocks (through a GTL+ driver) back to the cb_wc* and cb_rc* pins (pins A10 and B10, respectively). If this bit (bit 10 in register 0122h) is cleared to ‘0’ these 2 pins, cb_gen_rc and cb_gen_wc, are inactive and are 3-stated. In this case, bit 6 in register 2Eh is set to ‘1’ to indicate that pins A10 and B10 will be receiving clocks from a different source on the board. Please see registers 2Eh and 0122h for more details.

70 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8208

10.8 Modify Cell Bus Request Priority Based on RX PHY FIFO Threshold

This allows the T8208 device to modify the request priority for a cell on the cell bus, based on the RX PHY FIFO thresholds. This feature is useful to raise the priority of cells to avoid a situation where the queue is getting filled with low priority cells and hence the high priority cells are blocking low priority cells from being sent to the cell bus. There are two thresholds. Threshold 1 to force request priority to MEDIUM and Threshold 2 to force request priority to HIGH. Bit 4 in register 126h, cb_prio2_thr_en when set, enables the threshold 2. Bits [3:0] in register 0126h, cb_prio2_thr, set the threshold 2. Bit 12 in register 126h, cb_prio1_thr_en when set, enables the threshold 1. Bits [11:8] in register 0126h, cb_prio1_thr, set the threshold 1. Note: When bits 3:2 in register 0110h are set to ‘00’ (disabled) and this feature is enabled, cells are transmitted onto the cell bus as soon as the priority medium is reached. To prevent this, either the feature needs to be disabled or cells should not be transmitted to this FIFO. Note: These threshold levels cannot be changed when there is data flowing through the CelXpres device.

10.9 Digital Loopback Before Cell Bus

The digital loopback allows loopback of all cells without requiring the cell to be sent to the cell bus. The output of the cell bus output FIFO is connected to the input of the cell bus input FIFO internally, so that the cells do not have to go through the GTL+ buffers. The cells being received on the RX UTOPIA should still be addressed properly with in-range VPI/VCI and routing information for the device to be able to loopback the cells. Bit 7 (dig_lpbk_en) in register 2Eh must be set to ‘1’ and bit 2 (GTLTPDN) in register 2Fh must be cleared to ‘0’ to enable a digital loopback. Cell Bus Request Priority Bits 3:2 in Register 110h Priority when Threshold 1 Is Reached Priority when Threshold 2 Is Reached 00 = disabled medium high 01 = low priority medium high 10 = medium priority medium high 11 = high priority high high

11 SDRAM Interface

ration 1 register (address 0100h). divided into is 1 queue and the maximum number of queues is 128 queues (ATM mode) or 4 queues (PHY mode).

11.1 Memory Configuration

or 64 Mbit devices. Table 19 below outlines the various memory configurations supported. Table 19. Supported Memory Configurations

11.2 Powerup Sequence

level or external control signal. timing between commands is met, until the powerup process has been completed. may be configured for either addressing mode.

11 SDRAM Interface (continued)

11.3 SDRAM Interface Timing

■ RAS inactive to CAS active (ras2cas)—its value may be set from two to four SDRAM clock cycles. may be set to three, seven, or fifteen SDRAM clock cycles. a cell using the default values for the parameters. Figure 17. SDRAM Timing Parameters VALUES ARE IN BOLD FOR ras2cas, cas2pre, pre2cmd, AND ref2cmd.

Agere Systems Inc. 73 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8208

11.4 Queuing

For a device configured in ATM mode, up to 32 groups of queues with four priorities per group may be configured in the SDRAM for a total of 128 queues. Therefore, the five port group address bits point to one of 32 queue groups, and the two priority bits point to one of four queues in the group. (For a description of the port group address and priority bits, see Section 10.3.2, Data Cells.) Priority bits with a value of zero represent the highest pri- ority, and those with a value of three, the lowest priority. If an ATM is configured to support 32 PHY ports in 8-bit UTOPIA mode (a value of “0011” in bits 3:0 of register 0112h), each port is assigned to its associated queue group as illustrated in Table 20, regardless of the value of the port_rte[127:0] bits. In this case, port 0 is assigned to queue group 0, port 1 to queue group 1, and so on. For an ATM configured to support 64 PHY ports in 8-bit UTOPIA mode and 32 PHY ports in 16-bit UTOPIA mode, each queue group is shared between two ports as specified in Section 9.2.2, Outgoing ATM Mode (cells sent by T8208), and the four queues may be split in any way between the two ports using the port_rte[127:0] bits. Table 21 illustrates the relationship between the queue organization and the port group address/priority bits for a device configured to support 64 PHY ports in 8-bit UTOPIA mode and 32 PHY ports in 16-bit UTOPIA mode, and whose port_rte[127:0] bits are programmed to the normal 64-port mode as described in Section 9.2.2, Outgoing ATM Mode (cells sent by T8208). See the TxPHY FIFO routing 7, 6, 5, 4, 3, 2, 1, and 0 registers at addresses 0170h, 0172h, 0174h, 0176h, 0178h, 017Ah, 017Ch, and 017Eh, respectively.

Table 20. Queue Organization and Port Group Address/Priority Bits for 32 Ports in 8-Bit UTOPIA Mode

32 Ports in 16-Bit UTOPIA Mode

000 H i g h “00000” “00”

101 H i g h “00000” “01”

214 H i g h “00001” “00”

315 H i g h “00001” “01”

428 H i g h “00010” “00”

529 H i g h “00010” “01”

32 Ports in 16-Bit UTOPIA Mode (continued)

80 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8208 Of the four priority queues, the highest-priority (priority zero), lowest-delay queue may be used for constant bit rate (CBR) traffic. The other three queues, in descending order of priority, may be used for variable bit rate (VBR), avail- able bit rate (ABR), and unspecified bit rate (UBR) traffic, respectively. Generally, as the priority becomes lower, the queues become larger because lower-priority cells are likely to accumulate while higher-priority cells are transmit- ted. The size and location of each queue is programmable using the base_addressX[24:6] and end_addrX[24:6] bits in the Queue X Definition Structure, shown in Table 173. Using these base and end address registers, the size of each queue may be programmed to a minimum of four cells and up to a maximum of 512K cells in one-cell incre- ments. Each queue must be disabled during queue configuration by clearing the queueX_rd_en and queueX_wr_en bits in the queue X registers (addresses 0440h through 053Eh) (shown in Table 172). Cells sent to write-disabled queues will be discarded. Cells sent to read-disabled queues will be written into the SDRAM but never transmitted to the TX UTOPIA port. Read-disabled queues may be used, as large external memory, to store cells bound for the microprocessor. The microprocessor may use as many queues as required for different type cells. Because the microprocessor reads only 2 bytes from the SDRAM per access, the cas2pre value (see Section 11.3, SDRAM Interface Timing) may need to be larger than that required for the transferring of cells only. Therefore, to maximize the bandwidth of the SDRAM for cell bus to UTOPIA traffic, restrict microproces- sor access of the SDRAM to the initialization function (e.g., downloading microcode over the cell bus). When the microprocessor increments the read pointer to read the SDRAM, it must first write the three least signifi- cant bits (rd_pntX[8:6]) of the read pointer for the appropriate queue followed by the 16 most significant bits (rd_pntX[24:9]). This order must be followed for proper operation. All queues used for microprocessor cell recep- tion must be at least 32 cells long. (See Queue X Definition Structure, Table 173, for more information on these bits.)

11.5 SDRAM Refresh

The T8208 SDRAM interface performs CAS before RAS (CBR) refresh commands at a rate programmed in the ref_cnt bits of the refresh register (address 0410h). The value in the refresh register represents refresh cycles in SDRAM clock cycles. One refresh command is executed every ref_cnt clock cycles, on average, when the SDRAM is idle. In addition, the value programmed in the refresh lateness register (address 0412h) represents the maximum time, in programmed refresh cycles, between actual refresh cycles. If this limit is exceeded, the ref_late bit in the SDRAM interrupt status register (address 0402h) will be set, and if the ref_late interrupt is enabled, an interrupt will be generated. The ref_late indication is provided for diagnostic purposes and does not necessarily indicate a fatal error. Bit errors in the actual cell are reported in the crc8_err_even and crc8_err_odd bits of the SDRAM interrupt status register.

Agere Systems Inc. 81 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8208

11.6 SDRAM Throughput

The SDRAM clock frequency must be fast enough for cell transfers, to and from the SDRAM, to occur without over- runs to the TX PHY FIFO. Using the default values for ras2cas, cas2pre, and pre2cmd, thirty-five clock cycles are required to transfer one cell (56 bytes) into or out of the SDRAM. The assumed efficiency rate is 90%. Therefore, the number of cells per second that can be read or written into the SDRAM is calculated using the following equa- tion: Cell Rate = (f mclk/35 cycles per cell x 90%) where fmclk is the frequency of the SDRAM clock. The maximum UTOPIA and cell bus bandwidths must be calculated to ensure that the SDRAM clock frequency supports these bandwidths. For example, assume that the total bandwidth on the UTOPIA bus is 64 Mbits/s and that the cell bus clock rate is 33 MHz. The maximum number of cells per second that the cell bus can send is: = 2.06 Mcells per second. On the UTOPIA port, the total number of cells that can be sent is: = 151 Kcells per second. Thus, the total number of cells per second from the cell bus and to the UTOPIA bus is 2.21 Mcells per second. For the cell rate equation above, the required SDRAM clock frequency is: * 35 cycles per cell = 86 MHz. This is a worst-case example and assumes that all potential cells on the cell bus are going to this one device. The SDRAM frequency calculation produces a lower frequency if the actual system characteristics are considered and if the distribution of cells is controlled.

33 MHz

64 Mbits/s

2.21 Mcells per second

12 Traffic Management

12.1 Cell Loss Priority (CLP)

filled beyond the programmed limit and this feature is enabled. Table 173. The feature is enabled when the queueX_clp_en bit in the queue X registers (address 0440h through reading the value of the read and write pointers for the specific queue.

12.2 Forward Explicit Congestion Notification (FECN)

FECN fill level for a queue, the T8208 sets the corresponding queueX_fecn_lim status bit in the queue X registers. If the fill level is set to zero, the corresponding queueX_fecn_lim bit is set by the first received cell for the queue.

Agere Systems Inc. 83 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8208

12 Traffic Management (continued)

12.3 Partial Packet Discard (PPD)

Partial packet discard (PPD) is accomplished through the cooperation of the T8208 (source), which places the cell on the cell bus and the T8208 (destination), which receives the cell from the bus. The source T8208 uses its trans- lation RAM to place a unique ID (PPD pointer) and PPD enable bit in the cell for each AAL5 connection. The PPD pointer and PPD enable bit may consist of any bit in the first 64 bits of the bus cell (cell bus routing header, tandem routing header, and ATM cell header) and are created at connection establishment. The destination T8208 uses the PPD state memory (address 1000h to 13FEh) to track the state of AAL5 virtual channels for partial packet discard. Each bit in the memory represents one of 8192 potential AAL5 virtual channels. When the virtual channel connection is initially established, the bit in PPD state memory pointed to by the PPD pointer should have been cleared. When a cell that has its PPD enabled is discarded, the bit pointed to by the PPD pointer becomes set. Once this bit is set, successive cells with the same PPD pointer will be discarded until the last cell is received. The last cell is identified using the SDU-type bit in the PTI of the cell header. When the last cell of the packet is received, the virtual channel's corresponding bit in the PPD state memory is automatically cleared, and the last cell is transmitted. The ppd_en_sel[5:0] bits in the PPD information 1 register specify which of the bus cell's first 64 bits (cell bus rout- ing header, tandem routing header, and ATM cell header) enable PPD. PPD is enabled when the associated bit in the headers is one. The partial packet discard bits specify which of the bus cell's first 64 bits are used to create the PPD pointer. These pointer bits are ppd_pnt0_sel[5:0] through ppd_pnt12_sel[5:0] in the PPD information 1 through 7 registers (addresses 0206h through 0212h). When an AAL5 virtual channel connection is initially estab- lished, its PPD bit in the PPD state memory can be cleared using the write_pul, write_val, and write_addr bits in the PPD memory write register at address 0418h.

13 JTAG Test Access Port

high, the JTAG interface is enabled. If the JTAG port is not used, jtag_trst should be tied low. guage may be found on the Agere website.

13.1 Instruction Register

The instruction register (IR) is 3 bits in length. The instructions are defined in Table 22. Table 22. Instruction Register EXTEST “000” Places the boundary-scan register in extest mode. SAMPLE “001” Places the boundary-scan register in sample mode. HIGHZ “010” Places the boundary-scan register in highz mode. RUNBIST “100” Places the boundary-scan register in runbist mode. IDCODE “101” Places the boundary-scan register in idcode mode. BYPASS “011,” “110,” “111” Places the bypass register in the scan chain.

Agere Systems Inc. 85 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8208

13 JTAG Test Access Port (continued)

13.2 Boundary-Scan Register

The boundary-scan register (BSR) is 245 bits in length. Table 23 gives descriptions of each cell in the boundary- scan chain beginning with the least significant bit. Table 23. Boundary-Scan Register Descriptions

Description

0 TR_D_OE — TR_D(0:7) are inputs when TR_D_OE = 0.

1 TR_CONT_OE — TR_OE_N, TR_WE_N, TR_A(17:0), and TR_CS(1:0) are high

impedance when TR_CONT_OE = 0. 2 U_RXCLAV0_OE — U_RXCLV0 is an input when U_RXCLAV0_OE = 0. 3 U_RXENB0_OE — U_RXENB(0) is an input when U_RXENB0_OE = 0. 4 U_RXENB_OE — U_RXENB(1:3) are inputs when U_RXENB_OE = 0. 5 U_RXADDR_OE — U_RXADD(0:4) are inputs when U_RXADDR_OE = 0. 6 U_RXCLK_OE — U_RXCLK is an input when U_RXCLK_OE = 0. 7 GPIO_OE(7) — GPIO(7) is an input when GPIO_OE(7) = 0. 8 GPIO_OE(6) — GPIO(6) is an input when GPIO_OE(6) = 0. 9 GPIO_OE(5) — GPIO(5) is an input when GPIO_OE(5) = 0. 10 GPIO_OE(4) — GPIO(4) is an input when GPIO_OE(4) = 0. 11 GPIO_OE(3) — GPIO(3) is an input when GPIO_OE(3) = 0. 12 GPIO_OE(2) — GPIO(2) is an input when GPIO_OE(2) = 0. 13 GPIO_OE(1) — GPIO(1) is an input when GPIO_OE(1) = 0. 14 GPIO_OE(0) — GPIO(0) is an input when GPIO_OE(0) = 0. 15 D_OE — D(7:0) are inputs when D_OE = 0. 16 CKO_OE — CKO is high impedance when CKO_OE = 0. 17 RDY_DTACK_N_OE — RDYDTACK is high impedance when RDY_DTACK_N_OE = 0.

18 DEVHIZ_N_HIGH_DRIV

E — INT_IRQ, SD_A(11:0), SD_BS(1:0), SD_CAS_N, SD_RAS_N, and SD_WE_N are high impedance when DEVHIZ_N_HIGH_DRIVE = 0. 19 U_SHR_GNT_OE — U_SHR_GNT(0:1) are inputs when U_SHR_GNT_OE = 0. 20 U_TXDATA_OE — U_TXDAT(15:0) are high impedance when U_TXDATA_OE = 0. 21 U_TXPRTY_OE — U_TXPRTY is an input when U_TXPRTY_OE = 0. 22 U_TXSOC_OE — U_TXSOC is high impedance when U_TXSOC_OE = 0. 23 U_TXCLK_OE — U_TXCLK is an input when U_TXCLK_OE = 0. 24 U_TXADDR_OE — U_TXADD(4:0) are inputs when U_TXADDR_OE = 0. 25 U_TXENB_OE — U_TXENB(3:1) are high impedance when U_TXENB_OE = 0. 26 U_TXENB0_OE — U_TXENB0 is an input when U_TXENB0_OE = 0. 27 U_TXCLAV0_OE — U_TXCLV0 is an input when U_TXCLAV0_OE = 0.

Table 23. Boundary-Scan Register Descriptions (continued) 28 SD_CLK_OE — SD_CLK is an input when SD_CLK_OE = 0. 29 SD_D_OE — SD_D(15:0) are inputs when SD_D_OE = 0.

30 CB_GEN_OE — CB_GEN_RC and CB_GEN_WC are inputs when

31 U_SHR_REQ_OE — U_SHR_REQ(0:3) are inputs when

32-39 TR_D(0:7) tr_d[0:7] Bidirectional. 40-41 TR_CS(0:1) tr_cs*[0:1] 3-statable output. 42 TR_OE_N tr_oe* 3-statable output. 43 TR_WE_N tr_we* 3-statable output. 62 U_RXCLV0 u_rxclav[0] Bidirectional. 63-65 U_RXCLV(1:3) u_rxclav[1:3] Input. 66 U_RXENB(0) u_rxenb*[0] Bidirectional. 67-69 U_RXENB(1:3) u_rxenb*[1:3] Bidirectional. 70-74 U_RXADD(0:4) u_rxaddr[0:4] Bidirectional. 75 U_RXCLK T1 Bidirectional. 94 GPIO(7) gpio[7] Bidirectional. 95 GPIO(6) gpio[6] Bidirectional. 96 GPIO(5) gpio[5] Bidirectional. 97 GPIO(4) gpio[4] Bidirectional. 98 GPIO(3) gpio[3] Bidirectional. 99 GPIO(2) gpio[2] Bidirectional. 100 GPIO(1) gpio[1] Bidirectional. 101 GPIO(0) gpio[0] Bidirectional. 118 CKO cko 3-statable output. 120 RDYDTACK rdy_dtack* 3-statable output. 121 INT_IRQ int_irq* 3-statable output.

128-129 U_SHR_GNT(0:1) u_shr_gnt(0:1) Bidirectional. 130-145 U_TXDAT(15:0) u_txdata[15:0] 3-statable output. 146 U_TXPRTY u_txprty Bidirectional. 147 U_TXSOC u_txsoc 3-statable output. 148 U_TXCLK u_txclk Bidirectional. 149-153 U_TXADD(4:0) u_txaddr[4:0] Bidirectional. 154-156 U_TXENB(3:1) u_txenb*[3:1] 3-statable output. 157 U_TXENB0 u_txenb*[0] Bidirectional. 161 U_TXCLV0 u_txclav[0] Bidirectional. 174 SD_CLK sd_clk Bidirectional. 175-176 SD_BS(1:0) sd_bs[1:0] 3-statable output. 177 SD_RAS_N sd_ras* 3-statable output. 178 SD_CAS_N sd_cas* 3-statable output. 179 SD_WE_N sd_we* 3-statable output. 202 CB_DISBL cb_disable* Input. 203 CB_ACK_N cb_ack* Bidirectional. 204 CB_F_N cb_fs* Bidirectional. 239 CB_GEN_RC_N cb_gen_rc* Bidirectional. 240 CB_GEN_WC_N cb_gen_wc* Bidirectional. 241-244 U_SHR_REQ(0:3) u_shr_req(0:3) Bidirectional.

14 Registers

registers are located in Section 14.3, Extended Memory Registers.

14.1 Register Types

Table 24. Register Map Read/Write (RW):These registers may be written or read. Read Only (RO): These registers may only be read. interrupt will be continuously generated until the bit in the ROL register is cleared. Write Only (WO):These registers may only be written. The write only registers in the T8208 are a pulse type.

14 Registers (continued)

Table 24. Register Map (continued)

14.2 Direct Memory Access Registers

Table 25. Identification 0 (IDNT0) (00h) Table 26. Identification 1 (IDNT1) (01h) Table 27. Identification 2 (IDNT2) (02h)

1. RN represents the current revision number of the device.

Device ID 0 7:0 RO 4Fh Device Identification 0. Device ID 1 7:0 RO 08h Device Identification 1. Revision 7:0 RO RN 1 Revision Number.

Table 28. Direct Configuration/Control Register (DCCR) (28h) per read/write to the translation RAM. modified and clocks are not present. Active-low. lation is performed, this bit has no effect. address space, 30h to 37h, will be in big-endian format.

Table 29. Interrupt Service Request (ISREQ) (29h) Table 30. mclk PLL Configuration 0 (MPLLCF0) (2Ah) will cause this bit to become set. enabled for this bit to become set. to be enabled for this bit to become set. pllen 7 RW 0 PLL Enable. If this bit is ‘1,’ the PLL is enabled. If ‘0,’ the PLL is disabled.

Table 31. mclk PLL Configuration 1 (MPLLCF1) (2Bh) Table 32. GTL+ Slew Rate Configuration (GTLSRCF) (2Eh) mum slew rate is 0.9 ns and the maximum slew rate is 3.3 ns. B4), if they are enabled (bit 10 in 0122h = 1). then pins A3 and B4 become 3-stated. clocks from the GTL+ pins A10 and B10. mation for the device to be able to loopback the cells. When this bit is cleared to ‘0,’ there is no digital loopback.

Table 33. GTL+ Control (GTLCNTRL) (2Fh) this condition, no cells can be received from the backplane. and cells are received from the backplane. the GTL+ transmitters on the cell bus pins are powered down. up and cells are transmitted to the backplane.

14.2.1 Little-Endian Format (big_end = 0) for Extended Memory Access Registers 30h—37h

Table 34. Extended Memory Address 1 (Little Endian) (EMA1_LE) (30h) Table 35. Extended Memory Address 2 (Little Endian) (EMA2_LE) (31h) Table 36. Extended Memory Address 3 (Little Endian) (EMA3_LE) (32h) Table 37. Extended Memory Address 4 (Little Endian) (EMA4_LE) (33h) Table 38. Extended Memory Access (Little Endian) (EMA_LE) (34h) high, both data bytes are written. cleared when the access is complete.

Table 39. Extended Memory Data Low (Little Endian) (EMDL_LE) (36h) Table 40. Extended Memory Data High (Little Endian) (EMDH_LE) (37h) available here after the extended read is complete. available here after the extended read is complete.

14.2.2 Big-Endian Format (big_end = 1) for Extended Memory Access Registers 30h—37h

Table 41. Extended Memory Address 4 (Big Endian) (EMA4_BE) (30h) Table 42. Extended Memory Address 3 (Big Endian) (EMA3_BE) (31h) Table 43. Extended Memory Address 2 (Big Endian) (EMA2_BE) (32h) Table 44. Extended Memory Address 1 (Big Endian) (EMA1_BE) (33h)

Table 45. Extended Memory Access (Big Endian) (EMA_BE) (34h) Table 46. Extended Memory Data High (Big Endian) (EMDH_BE) (36h) Table 47. Extended Memory Data Low (Big Endian) (EMDL_BE) (37h) cleared when the access is complete. available here after the extended read is complete. available here after the extended read is complete.

14.2.3 General-Purpose I/O Control Registers

Table 48. GPIO Output Enable (GPIO_OE) (39h) Table 49. GPIO Output Value (GPIO_OV) (3Bh) Table 50. GPIO Input Value (GPIO_IV) (3Dh) sponding output enable bit is high.

14.2.4 Control Cells

Table 51. Control Cell Receive Direct Memory (CCRXDM) (5Ch to 93h) The control cell receive memory may also be accessed from extended memory. See Table 174. Table 52. Control Cell Transmit Direct Memory (CCTXDM) (A0h to D7h) The control cell transmit memory may also be accessed from extended memory. See Table 175. shadow of the control cell receive extended memory.

14.2.5 Multicast Memories

Table 53. PHY Port 0 and Control Cells Multicast Direct Memory (PP0MDM) (E0h to FFh) The PHY port 0 and control cells multicast memory may also be accessed from extended memory (see Table 176).

14.3 Extended Memory Registers

UTOPIA registers, and the SDRAM registers.

14.3.1 Main Registers

Table 54. Main Configuration 1 (MCF1) (0100h) Reserved 4:0 RO 00h Reserved. a single SRAM of 512K bytes is not used. received on RX UTOPIA are not going to pass through an LUT. access for cells being received on RX UTOPIA. cbrh_before_trh 7R W 0 Cell Bus Routing Header Before Tandem Routing Header. come before the cell bus routing header on the incoming cells.

Table 54. Main Configuration 1 (MCF1) (0100h) (continued) high impedance when not active. outputs never go high impedance. SDRAM and will use only internal memory to buffer cell bus data. Clear this bit to enable the SDRAM interface. only one external SRAM will be accessed using tr_cs*[0]. will be appended to the beginning of each cell. SRAM used for the look-up table RAM.

Table 55. Main Interrupt Status 1 (MIS1) (0102h) Note: Immediately following device setup, write FFFFh to this register to clear erroneously set bits. responding enable bit is set. responding enable bit is set. synchronization signal is clocked onto the cell bus by the write clock. An interrupt is generated if the corresponding enable bit is set. if the corresponding enable bit is set. responding enable bit is set. interrupt is generated if the corresponding enable bit is set. cell bus. An interrupt is generated if the corresponding enable bit is set. generated if the corresponding enable bit is set. and is translated and routed. Reserved 15:12 RO 0 Reserved.

Table 56. Main Interrupt Enable 1 (MIE1) (0104h) responding status bit is reset. is generated until this bit or the corresponding status bit is reset. rupt is generated until this bit or the corresponding status bit is reset. is generated until this bit or the corresponding status bit is reset. ated until this bit or the corresponding status bit is reset. generated until this bit or the corresponding status bit is reset. rupt is generated if this bit and the corresponding status bit are set. erated until this bit or the corresponding status bit is reset. erated until this bit or the corresponding status bit is reset. Reserved 15:12 RO 0 Reserved.

Table 57. TX UTOPIA Clock Configuration (TXUCCF) (010Ch) the u_txclk pin is configured as an input. Reserved 15:12 RO 0 Reserved.

Table 58. RX UTOPIA Clock Configuration (RXUCCF) (010Eh) the u_rxclk pin is configured as an input. Reserved 15:12 RO 0 Reserved.

Table 59. Main Configuration/Control (MCFCT) (0110h) clock cycle and will clear to ‘0’ automatically. automatically cleared when the cell is transmitted to the cell bus. which cells with their CLP bit set to ‘1’ will be discarded. grammed in the clp_fill_limit bits is reached. the cell bus. If ‘0,’ cells are not accepted. u_rxenb*[3:1] become inputs.

Table 60. Main Configuration 2 (MCF2) (0112h) addr_clav_en 3:0 RW 0 UTOPIA Address, Cell Available, and Enable Signals. serted if the RX UTOPIA FIFO is considered full. high when polled, if the RX UTOPIA FIFO is considered full. when the RX UTOPIA is in ATM mode. serted even if the RX UTOPIA FIFO is considered full. mode achieves the OC-12 rate on the UTOPIA interfaces.

Table 60. Main Configuration 2 (MCF2) (0112h) (continued) are four. To maximize cell buffering the number of queues must be one. port uses two queues or a programmable number of queues per PHY. ■ RX PHY cell counters (incoming cell count) 4000h—40FEh. ■ TX PHY cell counters (outgoing cell count) 0600h—06FEh. ■ Dropped cell counters 3000h—31FEh. count) must be read consecutively (bits 31:16 first, bits 15:0 next). counters after it reads them, if it is needed. tion of the incoming UTOPIA cells. grammed in the look-up records.

■ RX PHY cell counters (incoming cell count) 4000h—40FEh. ■ TX PHY cell counters (outgoing cell count) 0600h—06FEh. ■ Dropped cell counters 3000h—31FEh. zero to indicate the completion of clearing the look-up table. that the largest possible SRAM size is being used.

Table 61. UTOPIA Configuration (UCF) (0114h) Table 62. Main Configuration 3 (MCF3) (0116h) used when the T8208 is configured as a PHY. Reserved 15:13 RO 0 Reserved. grant time-out (cb_grnt_to) status bit is set. in all cells transmitted to the UTOPIA bus. Reserved 15:13 RO 0 Reserved.

Table 63. UTOPIA Configuration 5 (UCF5) (0118h) Table 64. UTOPIA Configuration 4 (UCF4) (011Ah) Table 65. UTOPIA Configuration 3 (UCF3) (011Ch) Table 66. UTOPIA Configuration 2 (UCF2) (011Eh)

Refer to Section 8.4 for descriptions of special cell counters. Table 67. Extended LUT Control (ELUTCN) (0120h)

Table 68. Generated Cell Bus Clocks Control Register (GCBCCR) (0122h) cb_gen_rc by a certain programmable value. "01”: PLL VCO frequency (twice the Mclk). as it is automatically cleared when a new source is selected.

Table 68. Generated Cell Bus Clocks Control Register (GCBCCR) (0122h) (continued) a. Program the new clock_select value into register 122 Hex. b.Poll bit 11 of register 122 Hex until it is set to ‘1'. a. Program the new divisor_value into register 122 Hex. b. Poll bit 12 of register 122 Hex until it is set to ‘1'. a. Set the clock_enable bit of register 122 Hex in the presently generating T8208 to ‘0'. cating that the cell bus clocks were found to be dead for 32 consecutive mclk cycles. the procedure outlined above. the procedure outlined above. f. Read bits 2:0 of register 102 Hex (cb_fs_miss, cb_rc_miss and cb_wc_miss). g. If the bits read in step f (above) are set to 1, proceed to step h; else, go to step i. h. Clear those 3 bits by writing a 1 to them (in register 102 Hex). Go back to step f. Note: The above delay_select bits have an accuracy of +10% and –50%.

Table 69. RX PHY FIFO Thresholds to Change Cell Bus Request Priority (RXPFTCRP) (0126h) be disabled or cells should not be transmitted to this FIFO. Note: These threshold levels cannot be changed when there is data flowing through the CelXpres device. cells from the RX PHY FIFO onto the backplane. ority to its highest value (as mentioned in bits 3:0 above). Reserved 7:5 RO 000 Reserved. the cells from the RX PHY FIFO onto the backplane. Reserved 15:13 RO 000 Reserved. priority 2 threshold are reached.

Table 70. Enable Request on Upper Backplane Address (ERUB) (012Ch) Table 71. Enable Request on Lower Backplane Address (ERLB) (012Eh) its request served on the backplane. be programmed in this register for both the master and the slave cards. its request served on the backplane. be programmed in this register for both the master and the slave cards.

Table 72. Cell Bus Configuration/Status (CBCFS) (0130h) be the backplane address of the T8208. on the cell bus. If ‘1,’ 16-user mode is selected. finally cells from the loopback FIFO have the lowest priority. strongly advised not to set this bit during data flow. Reserved 15:10 RO 0 Reserved.

Table 73. Main Interrupt Status 2 (MIS2) (0132h) generated if the corresponding enable bit is set. if the corresponding enable bit is set. is generated if the corresponding enable bit is set. if the corresponding enable bit is set. Reserved 15:7 RO 0 Reserved.

Table 74. Main Interrupt Enable 2 (MIE2) (0134h) Table 75. Loopback (LB) (0136h) Table 76. Extended LUT Configuration (ELUTCF) (0138h) Reserved 1 RW 0 Reserved. Program this bit to zero. is generated if this bit and the corresponding status bit are set. sponding status bit is reset. generated if this bit and the corresponding status bit are set. sponding status bit is reset. Reserved 15:7 RO 0 Reserved. ing header of the outgoing loopback cell. "01”: 16 byte record with extended monitoring.

Table 77. Misrouted Cell LUT 3 (MLUT3) (013Ch) Table 78. Misrouted Cell LUT 2 (MLUT2) (013Eh) Table 79. Misrouted Cell LUT 1 (MLUT1) (0140h) Table 80. Misrouted Cell LUT 0 (MLUT0) (0142h) cells from a PHY port are monitored. cells from a PHY port are monitored. cells from a PHY port are monitored. cells from a PHY port are monitored.

Table 81. Misrouted Cell LUT 4 (MLUT4) (0144h) Table 82. Misrouted Cell Header High (MCHH) (0146h) Table 83. Misrouted Cell Header Low (MCHL) (0148h) pulse for one clock cycle and will clear to ‘0’ automatically. port from which the last misrouted cell was latched. Reserved 15:10 RO 0 Reserved. the incoming cell header are not all zero. the incoming cell header are not all zero.

14.3.2 UTOPIA Registers

Table 84. HEC Interrupt Status 3 (HIS3) (0300h) Table 85. HEC Interrupt Status 2 (HIS2) (0302h) Table 86. HEC Interrupt Status 1 (HIS1) (0304h) Table 87. HEC Interrupt Status 0 (HIS0) (0306h) ated bit is set when an HEC error is detected on the PHY port. An interrupt is generated if the corresponding enable bit is set. and is translated and routed. ated bit is set when an HEC error is detected on the PHY port. An interrupt is generated if the corresponding enable bit is set. and is translated and routed. ated bit is set when an HEC error is detected on the PHY port. An interrupt is generated if the corresponding enable bit is set. and is translated and routed. ated bit is set when an HEC error is detected on the PHY port. An interrupt is generated if the corresponding enable bit is set. and is translated and routed.

Table 88. HEC Interrupt Enable 3 (HIE3) (0308h) Table 89. HEC Interrupt Enable 2 (HIE2) (030Ah) Table 90. HEC Interrupt Enable 1 (HIE1) (030Ch) Table 91. HEC Interrupt Enable 0 (HIE0) (030Eh) ated until this bit or the corresponding status bit is reset. ated until this bit or the corresponding status bit is reset. ated until this bit or the corresponding status bit is reset. ated until this bit or the corresponding status bit is reset.

Table 92. LUT Interrupt Service Request 3 (LUTISR3) (0310h) Table 93. LUT Interrupt Service Request 2 (LUTISR2) (0312h) Table 94. LUT Interrupt Service Request 1 (LUTISR1) (0314h) Table 95. LUT Interrupt Service Request 0 (LUTISR0) (0316h) tus register has interrupt status bits that need servicing. tus register has interrupt status bits that need servicing. tus register has interrupt status bits that need servicing. register has interrupt status bits that need servicing.

Table 96. LUT X Configuration/Status (LUTXCFS) (0320h to 039Eh) not counted as a received cell. ated if the corresponding enable bit is set. the corresponding enable bit is set. Reserved 15:13 RO 0 Reserved. tion/status registers are shown below.

Table 96. LUT X Configuration/Status (LUTXCFS) (0320h to 039Eh) (continued)

14.3.2.1 TX UTOPIA Configuration

Table 97. Master Queue 7 (MQ7) (0150h) These bits indicate which queues in the master device are enabled for shared UTOPIA mode. Table 98. Master Queue 6 (MQ6) (0152h) These bits indicate which queues in the master device are enabled for shared UTOPIA mode. Table 99. Master Queue 5 (MQ5) (0154h) These bits indicate which queues in the master device are enabled for shared UTOPIA mode. device is not used in shared UTOPIA mode. associated bit is ‘1,’ it indicates that the queue is enabled. device is not used in shared UTOPIA mode. associated bit is ‘1,’ it indicates that the queue is enabled. device is not used in shared UTOPIA mode.

Table 100. Master Queue 4 (MQ4) (0156h) These bits indicate which queues in the master device are enabled for shared UTOPIA mode. Table 101. Master Queue 3 (MQ3) (0158h) These bits indicate which queues in the master device are enabled for shared UTOPIA mode. Table 102. Master Queue 2 (MQ2) (015Ah) These bits indicate which queues in the master device are enabled for shared UTOPIA mode. associated bit is ‘1,’ it indicates that the queue is enabled. device is not used in shared UTOPIA mode. associated bit is ‘1,’ it indicates that the queue is enabled. device is not used in shared UTOPIA mode. associated bit is ‘1,’ it indicates that the queue is enabled. device is not used in shared UTOPIA mode.

Table 103. Master Queue 1 (MQ1) (015Ch) These bits indicate which queues in the master device are enabled for shared UTOPIA mode. Table 104. Master Queue 0 (MQ0) (015Eh) These bits indicate which queues in the master device are enabled for shared UTOPIA mode. associated bit is ‘1,’ it indicates that the queue is enabled. device is not used in shared UTOPIA mode. ated bit is ‘1,’ it indicates that the queue is enabled. device is not used in shared UTOPIA mode.

Table 105. Slave Queue 7 (SQ7) (0160h) Table 106. Slave Queue 6 (SQ6) (0162h)

Table 107. Slave Queue 5 (SQ5) (0164h) Table 108. Slave Queue 4 (SQ4) (0166h) Table 109. Slave Queue 3 (SQ3) (0168h)

Table 110. Slave Queue 2 (SQ2) (016Ah) Table 111. Slave Queue 1 (SQ1) (016Ch) Table 112. Slave Queue 0 (SQ0) (016Eh) mode and must be programmed in the master device.

Table 113. TX PHY FIFO Routing 7 (TXPFR7) (0170h)

Table 114. TX PHY FIFO Routing 6 (TXPFR6) (0172h)

Table 115. TX PHY FIFO Routing 5 (TXPFR5) (0174h) ‘0,’ the corresponding queue is assigned to the even-numbered port.

Table 116. TX PHY FIFO Routing 4 (TXPFR4) (0176h)

Table 117. TX PHY FIFO Routing 3 (TXPFR3) (0178h)

Table 118. TX PHY FIFO Routing 2 (TXPFR2) (017Ah) ‘0,’ the corresponding queue is assigned to the even-numbered port.

Table 119. TX PHY FIFO Routing 1 (TXPFR1) (017Ch) ‘0,’ the corresponding queue is assigned to the even-numbered port.

Table 120. TX PHY FIFO Routing 0 (TXPFR0) (017Eh)

Table 121. Global Bypass SDRAM Control Register (GBSCR) (01B0h) sponding status bit is reset.

Table 122. Bypass SDRAM Service Request Register (BSSR) (01BEh) interrupt status bits that need servicing. has interrupt status bits that need servicing. has interrupt status bits that need servicing. has interrupt status bits that need servicing. has interrupt status bits that need servicing. has interrupt status bits that need servicing. has interrupt status bits that need servicing. has interrupt status bits that need servicing. has interrupt status bits that need servicing. has interrupt status bits that need servicing. has interrupt status bits that need servicing. has interrupt status bits that need servicing.

Table 122. Bypass SDRAM Service Request Register (BSSR) (01BEh) (continued) 96 has interrupt status bits that need servicing. 111 to 104 has interrupt status bits that need servicing. 119 to 112 has interrupt status bits that need servicing. 127 to 120 has interrupt status bits that need servicing.

Table 123. Bypass SDRAM Queue Interrupt Status Register 0 (BSQISR0) (01C0h) interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set.

Table 124. Bypass SDRAM Queue Interrupt Status Register 1 (BSQISR1) (01C2h) interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set.

Table 125. Bypass SDRAM Queue Interrupt Status Register 2 (BSQISR2) (01C4h) interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set.

Table 126. Bypass SDRAM Queue Interrupt Status Register 3 (BSQIS30) (01C6h) interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set.

Table 127. Bypass SDRAM Queue Interrupt Status Register 4 (BSQISR4) (01C8h) interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set.

Table 128. Bypass SDRAM Queue Interrupt Status Register 5 (BSQISR5) (01CAh) interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set.

Table 129. Bypass SDRAM Queue Interrupt Status Register 6 (BSQISR6) (01CCh) interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set.

Table 130. Bypass SDRAM Queue Interrupt Status Register 7 (BSQISR7) (01CEh) interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set.

Table 131. Bypass SDRAM Queue Interrupt Status Register 8 (BSQISR8) (01D0h) interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set.

Table 132. Bypass SDRAM Queue Interrupt Status Register 9 (BSQISR9) (01D2h) interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set.

Table 133. Bypass SDRAM Queue Interrupt Status Register 10 (BSQISR10) (01D4h) interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set.

Table 134. Bypass SDRAM Queue Interrupt Status Register 11 (BSQIS11) (01D6h) interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set.

Table 135. Bypass SDRAM Queue Interrupt Status Register 12 (BSQISR12) (01D8h) interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. q100_ovrn 9 RO 0 Queue 100 Overrun. This bit is set when queue 100 overruns. An interrupt is generated if the corresponding enable bit is set. q101_ovrn 11 RO 0 Queue 101 Overrun. This bit is set when queue 101 overruns. An interrupt is generated if the corresponding enable bit is set. q102_ovrn 13 RO 0 Queue 102 Overrun. This bit is set when queue 102 overruns. An interrupt is generated if the corresponding enable bit is set. q103_ovrn 15 RO 0 Queue 103 Overrun. This bit is set when queue 103 overruns. An interrupt is generated if the corresponding enable bit is set.

Table 136. Bypass SDRAM Queue Interrupt Status Register 13 (BSQISR13) (01DAh) q104_ovrn 1 RO 0 Queue 104 Overrun. This bit is set when queue 104 overruns. An interrupt is generated if the corresponding enable bit is set. q105_ovrn 3 RO 0 Queue 105 Overrun. This bit is set when queue 105 overruns. An interrupt is generated if the corresponding enable bit is set. q106_ovrn 5 RO 0 Queue 106 Overrun. This bit is set when queue 106 overruns. An interrupt is generated if the corresponding enable bit is set. q107_ovrn 7 RO 0 Queue 107 Overrun. This bit is set when queue 107 overruns. An interrupt is generated if the corresponding enable bit is set. q108_ovrn 9 RO 0 Queue 108 Overrun. This bit is set when queue 108 overruns. An interrupt is generated if the corresponding enable bit is set. q109_ovrn 11 RO 0 Queue 109 Overrun. This bit is set when queue 109 overruns. An interrupt is generated if the corresponding enable bit is set. q110_ovrn 13 RO 0 Queue 110 Overrun. This bit is set when queue 110 overruns. An interrupt is generated if the corresponding enable bit is set. q111_ovrn 15 RO 0 Queue 111 Overrun. This bit is set when queue 111 overruns. An interrupt is generated if the corresponding enable bit is set.

Table 137. Bypass SDRAM Queue Interrupt Status Register 14 (BSQISR14) (01DCh) q112_ovrn 1 RO 0 Queue 112 Overrun. This bit is set when queue 112 overruns. An interrupt is generated if the corresponding enable bit is set. q113_ovrn 3 RO 0 Queue 113 Overrun. This bit is set when queue 113 overruns. An interrupt is generated if the corresponding enable bit is set. q114_ovrn 5 RO 0 Queue 114 Overrun. This bit is set when queue 114 overruns. An interrupt is generated if the corresponding enable bit is set. q115_ovrn 7 RO 0 Queue 115 Overrun. This bit is set when queue 115 overruns. An interrupt is generated if the corresponding enable bit is set. q116_ovrn 9 RO 0 Queue 116 Overrun. This bit is set when queue 116 overruns. An interrupt is generated if the corresponding enable bit is set. q117_ovrn 11 RO 0 Queue 117 Overrun. This bit is set when queue 117 overruns. An interrupt is generated if the corresponding enable bit is set. q118_ovrn 13 RO 0 Queue 118 Overrun. This bit is set when queue 118 overruns. An interrupt is generated if the corresponding enable bit is set. q119_ovrn 15 RO 0 Queue 119 Overrun. This bit is set when queue 119 overruns. An interrupt is generated if the corresponding enable bit is set.

Table 138. Bypass SDRAM Queue Interrupt Status Register 15 (BSQISR15) (01DEh) q120_ovrn 1 RO 0 Queue 120 Overrun. This bit is set when queue 120 overruns. An interrupt is generated if the corresponding enable bit is set. q121_ovrn 3 RO 0 Queue 121 Overrun. This bit is set when queue 121 overruns. An interrupt is generated if the corresponding enable bit is set. q122_ovrn 5 RO 0 Queue 122 Overrun. This bit is set when queue 122 overruns. An interrupt is generated if the corresponding enable bit is set. q123_ovrn 7 RO 0 Queue 123 Overrun. This bit is set when queue 123 overruns. An interrupt is generated if the corresponding enable bit is set. q124_ovrn 9 RO 0 Queue 124 Overrun. This bit is set when queue 124 overruns. An interrupt is generated if the corresponding enable bit is set. q125_ovrn 11 RO 0 Queue 125 Overrun. This bit is set when queue 125 overruns. An interrupt is generated if the corresponding enable bit is set. q126_ovrn 13 RO 0 Queue 126 Overrun. This bit is set when queue 126 overruns. An interrupt is generated if the corresponding enable bit is set. q127_ovrn 15 RO 0 Queue 127 Overrun. This bit is set when queue 127 overruns. An interrupt is generated if the corresponding enable bit is set.

Table 139. Routing Information 1 (RI1) (0200h) mphy1_sel[5:0] 5:0 RW X Multi-PHY 1 Select [5:0]. as this queue group address bit. mphy2_sel[5:0] 11:6 RW X Multi-PHY 2 Select [5:0]. as this queue group address bit. Multi-PHY 1 and 2 Select [5:0]. always ‘0’ and is not extracted from the received cell. Reserved 15:12 RO 0 Reserved.

Table 140. Routing Information 2 (RI2) (0202h) reserved_sel[5:0] 5:0 RW X Reserved Select [5:0]. Program these bits to zero. dem routing header is used as this queue group address bit. always ‘0’ and is not extracted from the received cell. Reserved 15:12 RO 0 Reserved.

Table 141. Routing Information 3 (RI3) (0204h) prior0_sel[5:0] 5:0 RW X Priority 0 Select. prior1_sel[5:0] 11:6 RW X Priority 1 Select. always ‘0’ and is not extracted from the received cell. Reserved 15:12 RO 0 Reserved.

Table 142. PPD Information 1 (PPDI1) (0206h) dem routing header is used as this offset bit. and is not extracted from the received cell. received cell is one, the partial packet discard feature is enabled. Reserved 15:12 RO 0 Reserved.

Table 143. PPD Information 2 (PPDI2) (0208h) ppd_pnt10_sel[5:0] 5:0 RW X PPD Pointer 10 Select. header is used as this offset bit. ppd_pnt11_sel[5:0] 11:6 RW X PPD Pointer 11 Select. header is used as this offset bit. PPD Pointer 10 and 11 Select. Reserved 15:12 RO 0 Reserved.

Table 144. PPD Information 3 (PPDI3) (020Ah) ppd_pnt8_sel[5:0] 5:0 RW X PPD Pointer 8 Select. header is used as this offset bit. ppd_pnt9_sel[5:0] 11:6 RW X PPD Pointer 9 Select. header is used as this offset bit. Reserved 15:12 RO 0 Reserved.

Table 145. PPD Information 4 (PPDI4) (020Ch) ppd_pnt6_sel[5:0] 5:0 RW X PPD Pointer 6 Select. ppd_pnt7_sel[5:0] 11:6 RW X PPD Pointer 7 Select. and is not extracted from the received cell. Reserved 15:12 RO 0 Reserved.

Table 146. PPD Information 5 (PPDI5) (020Eh) ppd_pnt4_sel[5:0] 5:0 RW X PPD Pointer 4 Select. ppd_pnt5_sel[5:0] 11:6 RW X PPD Pointer 5 Select. and is not extracted from the received cell. Reserved 15:12 RO 0 Reserved.

Table 147. PPD Information 6 (PPDI6) (0210h) ppd_pnt2_sel[5:0] 5:0 RW X PPD Pointer 2 Select. header is used as this offset bit. ppd_pnt3_sel[5:0] 11:6 RW X PPD Pointer 3 Select. header is used as this offset bit. Reserved 15:12 RO 0 Reserved.

Table 148. PPD Information 7 (PPDI7) (0212h) ppd_pnt0_sel[5:0] 5:0 RW X PPD Pointer 0 Select. as this queue group offset bit. ppd_pnt1_sel[5:0] 11:6 RW X PPD Pointer 1 Select. as this queue group offset bit. extracted from the received cell. Reserved 15:12 RO 0 Reserved.

Table 149. Routing Information 4 (RI4) (0214h) mphy3_sel[5:0] 5:0 RW X Multi-PHY 3 Select [5:0]. as this queue group address bit. mphy4_sel[5:0] 11:6 RW X Multi-PHY 4 Select [5:0]. as this queue group address bit. Multi-PHY 3 and 4 Select [5:0]. always ‘0’ and is not extracted from the received cell. Reserved 15:12 RO 0 Reserved.

Table 150. PPD Memory Write (PPDMW) (0418h) write_pul bit is cleared by hardware when the write is complete. address of all ones will point to the least significant bit of word 1FF.

14.3.2.2 TX UTOPIA Monitoring

Table 151. PHY Port X Transmit Count Structure (PPXTXCNT) (0600h to 06FEh) running counter of cells transmitted on UTOPIA PHY port X. cells transmitted on UTOPIA PHY port X. base addresses of the 64 data structures are shown below.

14.3.2.3 RX UTOPIA Count Monitoring

Table 152. PHY Port X Receive Count Structure (PPXRXCNT) (4000h to 40FEh) ‘1’ or if their VPI and/or VCI are out of range. ‘1’ or if their VPI and/or VCI are out of range. addresses of the 64 data structures are shown below.

14.3.2.4 RX UTOPIA Configuration Monitoring

Table 153. PHY Port X Configuration Structure (PPXCF) (4200h to 42FEh) lutX_vpi_mask bit equal zero. field of the cell header will not be used in the look-up table. If this bit is ‘0,’ the port is identified as NNI. ports. The base addresses of the 64 data structures are shown below.

Table 153. PHY Port X Configuration Structure (PPXCF) (4200h to 42FEh) (continued)

14.3.3 SDRAM Registers

Table 154. SDRAM Control (SCT) (0400h) Table 155. SDRAM Interrupt Status (SIS) (0402h) Table 156. SDRAM Interrupt Enable (SIE) (0404h) active. If ‘0,’ the SDRAM is in the idle state. Reserved 14:2 RO 0 Reserved. detected on the even byte (sd_d[15:8]) of the SDRAM data bus. An interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. Reserved 15:3 RO 0 Reserved. erated until this bit or the corresponding status bit is reset. is generated if this bit and the corresponding status bit are set. Reserved 15:3 RO 0 Reserved.

Table 157. SDRAM Configuration (SCF) (0408h) SDRAM based on the clock frequency and speed grade of the device. charge command going active. command going inactive to next command going active. command going inactive to next refresh command going active. Reserved 15:11 RO 0 Reserved.

Table 158. Refresh (RFRSH) (0410h) Table 159. Refresh Lateness (RFRSHL) (0412h) Table 160. Idle State 1 (IS1) (0420h) Table 161. Idle State 2 (IS2) (0422h) reached, the ref_late status bit will be set. sd_cas* pin while the SDRAM is idle (sdram_en = ‘0’). sd_ras* pin while the SDRAM is idle (sdram_en = ‘0’). placed on the sd_we* pin while the SDRAM is idle (sdram_en = ‘0’). Reserved 15:5 RO 0 Reserved. the sd_a[11:0] pins while the SDRAM is idle (sdram_en = ‘0’). Reserved 15:12 RO 0 Reserved.

Table 162. Manual Access State 1 (MAS1) (0424h) Table 163. Manual Access State 2 (MAS2) (0426h) Reserved 15:5 RO 0 Reserved. Reserved 15:12 RO 0 Reserved.

Table 164. SDRAM Interrupt Service Request 7 (SISR7) (0430h) Table 165. SDRAM Interrupt Service Request 6 (SISR6) (0432h) Table 166. SDRAM Interrupt Service Request 5 (SISR5) (0434h) Table 167. SDRAM Interrupt Service Request 4 (SISR4) (0436h) rupt status bits that need servicing. status bits that need servicing. status bits that need servicing. status bits that need servicing.

Table 168. SDRAM Interrupt Service Request 3 (SISR3) (0438h) Table 169. SDRAM Interrupt Service Request 2 (SISR2) (043Ah) Table 170. SDRAM Interrupt Service Request 1 (SISR1) (043Ch) Table 171. SDRAM Interrupt Service Request 0 (SISR0) (043Eh) status bits that need servicing. status bits that need servicing. status bits that need servicing. status bits that need servicing.

Table 172. Queue X (QX) (0440h to 053Eh) gestion notification (FECN) feature is enabled. the corresponding enable bit is set. corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. is generated if this bit and the corresponding status bit are set. generated if this bit and the corresponding status bit are set. is generated until this bit or the corresponding status bit is reset.

Table 172. Queue X (QX) (0440h to 053Eh) (continued) ated until this bit or the corresponding status bit is reset.

14.3.3.1 SDRAM Control Memory

Table 173. Queue X Definition Structure (QXDEF) (2000h to 2FFEh) 16 bits of the queue’s end address in increments of one cell. through 8 of the queue’s end address in increments of one cell. ized to the base_addrX[24:9] before the queue is enabled. to the base_addrX[8:6] before the queue is enabled. ized to the base_addrX[24:9] before the queue is enabled. to the base_addrX[8:6] before the queue is enabled.

Table 173. Queue X Definition Structure (QXDEF) (2000h to 2FFEh) (continued)

14.3.4 Various Internal Memories

14.3.4.1 Control Cell Memories

Table 174. Control Cell Receive Extended Memory (CCRXEM) (07FCh to 0832h) The control cell receive memory may also be accessed from direct memory. See Table 51. Table 175. Control Cell Transmit Extended Memory (CCTXEM) (0900h to 0936h) The control cell transmit memory may also be accessed from direct memory. See Table 52.

14.3.4.2 Multicast Number Memories

Table 176. PHY Port 0 and Control Cells Multicast Extended Memory (PP0MEM) (0C00h to 0C1Eh) The PHY port 0 and control cells multicast memory may also be accessed from direct memory (see Table 53). nificant bit is multicast net number 0.

Table 177. PHY Port X Multicast Memory (PPXMM) (0C20h to 0FFEh) ports. The base addresses of the 31 multicast memory locations are shown below.

14.3.4.3 PPD State Memory

Table 178. PPD Memory (PPDM) (1000h to 13FEh) cant bit of word1FF corresponds to AAL5 virtual channel 8191.

14.3.5 Dropped Cell Count

cells dropped at TX PHY FIFO. Table 179. Queue X Dropped Cell Count (QXDCC) (3000h to 31FEh) counter for queue X has not overflowed. SDRAM or TX UTOPIA cell buffer.

Table 179. Queue X Dropped Cell Count (QXDCC) (3000h to 31FEh) (continued)

14.3.6 External Memories

14.3.6.1 Look-Up Translation Memory

Table 180. Translation RAM Memory (TRAM) (100000h to 17FFFEh)

14.3.6.2 SDRAM Buffer Memory

Table 181. SDRAM (SDRAM) (2000000h to 3FFFFFEh) word0 00h RW X This memory space is used to access the SDRAM memory.

periods can adversely affect device reliability. Table 182. Maximum Rating Parameters and Values

1. Except for 5 V tolerant buffers where VIHmax = 5.5 V + 0.3 V.
2. Maximum power dissipation may be determined from the following equation: PD = (125 °C – TA)/22.5 °C/W.

16 Recommended Operating Conditions

Table 183. Recommended Operating Conditions

17 Handling Precautions

used for comparison. The HBM ESD threshold presented here was obtained by using these circuit parameters. Table 184. HBM ESD Threshold

18.1 Crystal Information

crystal specification requirements shown below. Table 185. Crystal Specifications be 5 MHz to 50 MHz. The external clock must meet the requirements shown below. Table 186. External Clock Requirements PLL Configuration, for more information on these clocks. Oscillation Mode Fundamental parallel resonant. Effective Series Resistance See Figure 19 below. Frequency Tolerance and Stability5%. Figure 18. Crystal Figure 19. Negative Resistance Plot

The following conditions apply except where noted: TA = –40 °C to +85 °C, VDD = 3.3 V ± 10%, 15 pF each output. Table 187. dc Electrical Characteristics 20 MHz, cell bus clock = 30 MHz, nominal slew rate (register 2Eh).

0.7 VDD

19 Timing Requirements

period of their respective clocks in ns when used in the following tables. Table 188. Input Clocks Table 189. Output Clocks

19 Timing Requirements (continued)

19.1 Microprocessor Interface Timing

For access time information, see Section 6.3.2, CelXpres T8208 Access Performance.

1. write_access_active is the logical OR function of sel* and wr*_ds*.

Note: sel* and wr*_ds* must not have coinciding edges in opposite directions to prevent glitches on the write_access_active signal. Figure 20. Nonmultiplexed Intel Mode Write Access Timing

1. read_access_active is the logical OR function of sel* and rd*_wr*.

Note: sel* and rd*_wr* must not have coinciding edges in opposite directions to prevent glitches on the read_access_active signals. Figure 21. Nonmultiplexed Intel Mode Read Access Timing

Table 190. Nonmultiplexed Intel Mode Write Access Timing

1. See access times in Table 11.

Note: The term pclkp in the table represents the period of pclk in ns. Table 191. Nonmultiplexed Intel Mode Read Access Timing

1. See access times in Table 11.

Note: The term pclkp in the table represents the period of pclk in ns.

1. write_access_active is the logical OR function of sel*, wr*_ds*, and rd*_wr*.

sel* and wr*_ds* must not have coinciding edges in opposite directions to prevent glitches on the write_access_active signal. rd*_wr* must be stable any time both sel* and wr*_ds* are low to prevent glitches on the write_access_active signals. Figure 22. Motorola Mode Write Access Timing

1. read_access_active is the logical OR function of sel*, wr*_ds*, and rd*_wr*.

sel* and wr*_ds* must not have coinciding edges in opposite directions to prevent glitches on the read_access_active signal. rd*_wr* must be stable any time both sel* and wr*_ds* are low to prevent glitches on the read_access_active signals. Figure 23. Motorola Mode Read Access Timing

Table 192. Motorola Mode Write Access Timing

1. See access times in Table 11.

Note: The term pclkp in the table represents the period of pclk in ns. Table 193. Motorola Mode Read Access Timing

1. See access times in Table 11.

Note: The term pclkp in the table represents the period of pclk in ns.

1. write_access_active is the logical OR function of sel* and wr*_ds*.

Note: sel* and wr*_ds* must not have coinciding edges in opposite directions to prevent glitches on the write_access_active signal. Figure 24. Multiplexed Intel Mode Write Access Timing

1. read_access_active is the logical OR function of sel* and rd*_wr*.

Note: sel* and rd*_wr* must not have coinciding edges in opposite directions prevent glitches on the read_access_active signals. Figure 25. Multiplexed Intel Mode Read Access Timing

Table 194. Multiplexed Intel Mode Write Access Timing

1. See access times in Table 11.

Note: The term pclkp in the table represents the period of pclk in ns. Table 195. Multiplexed Intel Mode Read Access Timing

1. See access times in Table 11.

Note: The term pclkp in the table represents the period of pclk in ns.

19.2 UTOPIA Timing

Table 196. TX UTOPIA Timing (70 pF Load on Outputs) Table 197. RX UTOPIA Timing (70 pF Load on Outputs)

19.3 External LUT Memory Timing

Note: 30 pF load on outputs.

1. TR_RD_ACTIVE is the logical OR function of TR_CS*[1:0] and TR_WE*.
2. When a single SRAM of 512K bytes is used (bit 5 in register 100h must be set to ‘1’), TR_CS0 is used as TR_A[18].

Figure 26. External LUT Memory Read Timing (cyc_per_acc = 2 and cyc_per_acc = 3) Note: 30 pF load on outputs.

1. TR_WR_ACTIVE is the logical OR function of TR_CS*[1:0] and TR_WE*.
2. When a single SRAM of 512K bytes is used (bit 5 in register 100h must be set to ‘1’), TR_CS0 is used as TR_A[18].

Figure 27. External LUT Memory Write Timing (cyc_per_acc = 2 and cyc_per_acc = 3)

The term mclkp in Tables 198, 199, 200, and 201, represents the period of mclk in ns. Table 198. External LUT Memory Read Timing (cyc_per_acc = 2) Table 199. External LUT Memory Read Timing (cyc_per_acc = 3) Table 200. External LUT Memory Write Timing (cyc_per_acc = 2) Table 201. External LUT Memory Write Timing (cyc_per_acc = 3)

19.4 Cell Bus Timing

Figure 28. Cell Bus Timing Table 202. Cell Bus Timing

19.5 SDRAM Interface Timing

Note: 15 pF load on outputs. Figure 29. SDRAM Interface Timing Table 203. SDRAM Interface Timing

Agere Systems Inc. 213 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8208

20 Outline Diagram

All dimensions shown are in millimeters. 5-4406.c SEATING PLANE SOLDER BALL0.60 ± 0.10 0.20 PWB MOLD COMPOUND 27.00 ± 0.20 27.00 ± 0.20 24.00 +0.70 –0.00 24.00 +0.70 –0.00A1 BALL IDENTIFIER ZONE A B C D E F G H J K L M Y N P R T U V W 123 45 678 9 1 0 18 20 CENTER ARRAY FOR THERMAL ENHANCEMENT 19 SPACES @ 1.27 = 24.13 A1 BALL CORNER

19 SPACES

@ 1.27 = 24.13 0.75 ± 0.15

September 2001ATM Interconnect CelXpres T8208 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. CelXpres is a trademark of Agere Systems Inc. Copyright © 2001 Agere Systems Inc. All Rights Reserved September 2001 DS01-295DLC (Replaces DS01-071DLC) For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045 Part Number Package Comcode T-8208---BAL-DB 272-pin PBGAM, Dry Pack Tray 108888876 T-8208---BAL-DT 272-pin PBGAM Dry-bagged, Tape & Reel 700001513 Motorola is a registered trademark of Motorola, Inc. Intel is a registered trademark of Intel Corporation. Transwitch and CellBus are registered trademarks of Transwitch Corp.