T8207

T8207 AGERE | Alldatasheet

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CelXpres™ T8207 ATM Interconnect

1 Product Overview

1.1 Features

■ > OC-3 transport capability ■ UTOPIA level 1 and 2 (8-bit) cell-level handshake interface (ATM or PHY layers) ■ 32 multi-PHY (MPHY) operation ■ Shared UTOPIA mode ■ Egress SDRAM buffer support to expand UTOPIA output priority queues for 32K to 512K cells: — 64 queues configurable up to four queues per PHY with programmable sizes — Programmable number of UTOPIA output queues with four levels of priority ■ Support of ATM traffic management via partial packet discard (PPD), forward explicit congestion notification (FECN), and the cell loss priority (CLP) bit ■ Programmable slew rate GTL+ I/O: — 1.7 Gbits/s cell bus operation — Programmable as bus arbiter ■ Flexible per port cell counters ■ Cell header translation and insertion with virtual path identifier (VPI) and virtual channel identifier (VCI) via external SRAM (up to 64K entries) ■ Support of network node interface (NNI) and user network interface (UNI) header types with optional generic flow control (GFC) insertion ■ Programmable operations and maintenance and resource management (OAM/RM) cell routing ■ Support of multicast and broadcast cells per PHY ■ Programmable priority for control/data cells trans- mission onto cell bus ■ Eight GPIO pins ■ JTAG support ■ Optional monitoring of misrouted cells ■ Microprocessor interface, supporting both Motor- ola® and Intel® modes (multiplexed and nonmulti- plexed) ■ Control cell transmission and reception through microprocessor port ■ Single 3.3 V power supply ■ 3.3 V TTL I/O (5 V tolerant) ■ 272-pin PBGA package ■ Industrial temperature range (–40 °C to +85 °C) ■ Hot insertion capability ■ Compatible with Transwitch CellBus®

1.2 Applications

■ Asymmetric digital subscriber line (ADSL) digital subscriber line access multiplexer (DSLAMs) ■ Access gateways ■ Access multiplexers/concentrators ■ Multiservice access equipment platforms

2 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8207 Table of Contents Contents Page 6.3.2

Agere Systems Inc. 3 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8207 Table of Contents (continued) Contents Page

14.2.1 Little-Endian Format (big_end = 0) for Extended Memory Access

14.2.2 Big-Endian Format (big_end = 1) for Extended Memory Access

Table 135. Nonmultiplexed

8 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8207

1 Product Overview (continued)

1.3 Description

The CelXpres T8207 device integrates all of the required functionality to transport ATM cells across a backplane architecture with high-speed cell traffic exceeding 1.5 Gbits/s to a maximum of 32 destinations. The management of multiple service categories and monitoring of performance on ATM and PHY interfaces is incorporated in the device’s functionality. Traffic delivery to multi-PHYs (MPHYs) is managed through the UTOPIA interface. The T8207 device meets the ATM Forum’s universal test and operations PHY interface for ATM (UTOPIA) Level 1, Version 2.01 and Level 2, Version 1.0 specifications for cell-level handshake and MPHY data path operation with rates up to 353 Mbits/s. The T8207 supports the required MPHY operation as described in Sections 4.1 and 4.2 of the ATM Forum’s Level 2 specification. The T8207 supports MPHY operation with one transmit cell available (TxCLAV) signal and one receive cell available (RxCLAV) signal for up to 16 PHY ports for an 8-bit UTOPIA 2 inter- face configuration. With two transmit cells available/enable (TxCLAV/enb*) pairs of signals and receive cells avail- able/enable (RxCLAV/enb*) pairs of signals, 32 MPHYs can be supported. In addition to the required UTOPIA signals, the optional transmit parity (TxPRTY) and receive parity (RxPRTY) signals are provided. The T8207 may be configured as an ATM or PHY level device providing cell routing between UTOPIA and a 32-bit wide cell bus. In addition to the 32 data signals, the bus has the following signals: ■ Read clock ■ Write clock ■ Frame sync ■ Acknowledge ATM cells arriving from the UTOPIA interface may get VPI and VCI translation and routing information from a look- up table in external SRAM. An external synchronous dynamic random access memory (SDRAM) is used to extend the buffering for ATM cells destined for the UTOPIA interface. This external SDRAM may be partitioned into four or less independently sized queues per PHY for a configuration of 16 MPHYs and two queues per PHY or a program- mable number of queues per PHY for a configuration of 32 MPHYs. The number of cells per queue per PHY is pro- grammable. The four queues may be used to implement quality of service (QoS) using different priorities for each queue. The CelXpres T8207 provides a shared UTOPIA mode, which allows two devices on different cell buses to share the same UTOPIA bus in ATM mode. Using a glueless interface, the two T8207 devices resolve queue priorities and arbitrate the use of the UTOPIA bus. This shared mode can be used to provide redundancy or increase UTOPIA traffic capacity by supporting traffic from multiple cell buses. The CelXpres T8207 supports the transport of control and loopback cells with an external microprocessor. Control or loopback cells may be sent or received through the microprocessor interface. The 8-bit microprocessor interface may be configured to be Motorola or Intel compatible and is used to configure and monitor the device.

Figure 1. Functional Block Diagram

devices by configuring one device to assume bus responsibility from the other. Figure 2. Dual Bus Implementation

Agere Systems Inc. 11 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8207

1.4 Conventions

■ All numbers in this document are decimals unless otherwise specified. ■ Hexadecimal numbers can be identified by the ‘h’ suffix, e.g., A5h. ■ Binary numbers are either in double quotes for multiple bits or in single quotes for individual bits, e.g., “1001” and ‘0.’ ■ A byte is 8 bits, a word is 16 bits, and a double word (dword) is 32 bits. ■ A binary value of ‘1’ is high, and a binary value of ‘0’ is low. ■ To clear is to change one or multiple bit values to ‘0.’ ■ To set is to change one or multiple bit values to ‘1.’ ■ All memory addresses are specified in hexadecimal. ■ Addresses are converted from bytes to words or double words using the little-endian format, unless otherwise specified. ■ A signal name with a trailing asterisk is active-low, e.g., sd_we*. ■ Bits y to x will be designated bits (y:x).

12 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8207

1.5 Glossary

Bus Cell: Major content of the cell bus frame consisting of 56 bytes, 4 bytes for routing options and 52 bytes for the ATM cell content, which excludes the HEC. The bus cell is preceded by the 4 bytes of request and followed by the 4 bytes of grant and parity information. CLP : Cell loss priority. The CLP is a 1-bit field in the cell header that becomes set when the cell violates the negotiated quality of service parameters. EFCI: Explicit forward congestion indication. The EFCI is a 1-bit field in the PTI field of the cell header that becomes set when the cell encounters congestion. FECN : Forward explicit congestion notification. FECN is a method used by the network to signal to the destination when congestion is encountered. The EFCI bit is used to indicate the congestion. GFC : Generic flow control. The GFC is a 4-bit field in the cell header that may be used by a UNI to support traffic and congestion control. Typically, this field is programmed to “0000” indicating that generic flow control is not sup- ported. GFC may be used in priority protocols. Grant Section: Last 4 bytes of the cell bus frame. The grant section occurs during the last clock cycle of the cell bus frame. During this cycle, the cell bus arbiter indicates which T8207 may transmit during the next bus cell unit of the cell bus frame. A parity vector is also transmitted during the grant section. HEC : Header error control. The HEC is a 1-byte field in the cell header used for bit error detection and correction in the header. NNI: Network node interface. The NNI is the interface between nodes in the public network. OAM Cell: Operations and maintenance cell. An OAM cell carries local management information. PPD : Partial packet discard. PPD is a technique to relieve congestion. When one cell in a packet is lost, all remaining cells in the packet, except the last, are dis- carded. PTI: Payload type identifier. The PTI is a 3-bit field in the cell header containing information about the type of data (user, OAM, or traffic management) and about encoun- tered congestion. QoS : Quality of service. Quality of service parameters define the performance requirements and characteristics for traffic on an assigned channel. Some parameters include cell loss ratio, cell transfer delay, cell delay vari- ation, peak cell rate, and sustained cell rate. RM : Resource management. RM is the local management of network resources. RxCLAV: Receive cell available signal as described in the ATM Forum’s universal test and operations PHY interface for ATM (UTOPIA) Level 1, Version 2.01 and Level 2, Version 1.0 specifications. RxENB: Receive enable signal as described in the ATM Forum’s universal test and operations PHY interface for ATM (UTOPIA) Level 1, Version 2.01 and Level 2, Version 1.0 specifications. TxCLAV: Transmit cell available signal as described in the ATM Forum’s universal test and operations PHY interface for ATM (UTOPIA) Level 1, Version 2.01 and Level 2, Version 1.0 specifications. TxENB: Transmit enable signal as described in the ATM Forum’s universal test and operations PHY interface for ATM (UTOPIA) Level 1, Version 2.01 and Level 2, Version 1.0 specifications. UNI: User network interface. The UNI is the interface between a private network node and a public network node. VCI: Virtual channel identifier. The VCI is a 2-byte field in the cell header that identifies the virtual channel used by the cell. VPI: Virtual path identifier. The VPI is an 8-bit field in the UNI cell header or a 12-bit field in the NNI cell header that identifies the virtual path of the cell.

2 Pin Description

Table 1. UTOPIA Pins —I RX UTOPIA Data Lines. TTL compatible input, 5 V tolerant. u_rxclk T1 Z I/O RX UTOPIA Clock. 10 mA drive, TTL compatible I/O, 5 V tolerant. tolerant. This pin has an internal 50 kΩ pull-up resistor. gle PHY mode. 10 mA drive, TTL compatible I/O, 5 V tolerant. compatible I/O, 5 V tolerant. pin has an internal 50 kΩ pull-up resistor. Z I/O TX UTOPIA Address Lines. 10 mA drive, TTL compatible I/O. ZO TX UTOPIA Data Lines. 10 mA drive, TTL compatible output. u_txclk R18 Z I/O TX UTOPIA Clock. 10 mA drive, TTL compatible I/O, 5 V tolerant. tolerant. This pin has an internal 50 kΩ pull-up resistor. PHY mode. 10 mA drive, TTL compatible I/O, 5 V tolerant. u_txprty T19 Z O TX UTOPIA Odd Parity. 10 mA drive, TTL compatible output. UTOPIA master or as request if device is shared UTOPIA slave.

2 Pin Description (continued)

Table 2. Cell Bus Pins Z I/O Cell Bus Data Lines (Active-Low). GTL+ I/O. same frequency but different phase. GTL+ input. same frequency but different phase. GTL+ input. cb_fs* C15 Z I/O Cell Bus Frame Sync (Active-Low). GTL+ I/O. broadcast or multicast cells. GTL+ I/O. an internal 50 kΩ pull-up resistor. active. This pin has an internal 50 kΩ pull-up resistor. between VTT and cb_vref_vss. cb_vref_vss C10 — — Cell Bus Voltage Reference Ground.

Table 3. SDRAM Interface Pins put. These buffers are 50 Ω impedance matching buffers. wiring board traces should have 50 Ω nominal impedance. sd_bs[1:0] H18, G20 X O SDRAM Bank Selects. 7 mA drive, TTL compatible output. have 50 Ω nominal impedance. should have 50 Ω nominal impedance. wiring board traces should have 50 Ω nominal impedance.

Table 4. Microprocessor Interface Pins 7 bits of the address bus. TTL compatible input, 5 V tolerant. a[0]/ale Y8 — I Microprocessor Port Address 0/Address Latch Enable. mode or address latch enable in multiplexed mode. mode. TTL compatible input, 5 V tolerant. Motorola mode. 4 mA drive, TTL compatible output. compatible input, 5 V tolerant. mode. TTL compatible input, 5 V tolerant.

Table 5. Translation SRAM Interface Table 6. JTAG Pins jtag_tdi Y16 —I Test Data Input (JTAG). TTL compatible input, 5 V tolerant. This pin has an internal 50 kΩ pull-up resistor. tolerant. This pin has an internal 50 kΩ pull-up resistor. pin has an internal 50 kΩ pull-up resistor. ant. This pin has an internal 50 kΩ pull-up resistor.

Table 7. General-Purpose Pins Table 8. Power Pins input with 50 MHz max input frequency. used to drive xtalin, this pin must be left unconnected. decoupled using 0.01 µF or 0.1 µF capacitors.

Figure 3. 272-Pin PBGA— Top View

20 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8207

3 Powerup/Reset Sequence

One of the following two methods may be used to reset the T8207: 1. Assert the reset* pin low for at least 5 pclk periods or 100 ns, whichever is longer, and then return it high for a hardware reset. For a powerup reset, the reset* pin should be held low for at least 5 pclk periods or 100 ns, whichever is longer, after the power supply ramps to its operating voltage and the crystal oscillator is stable. 2. Write both the srst* and srst_reg* bits in the direct configuration/control register (address 28h) to ‘0,’ and leave them at that value for at least 1 µs to perform a software reset. The device is now in the reset state, and the following start-up procedure must be executed to ensure proper oper- ation: 1. After pclk (xtalin) is provided to the T8207, and the device is in the reset state: A. Write the mclk PLL configuration 0 and 1 registers at addresses 2Ah and 2Bh. B. Continue after the PLL has stabilized in 100 µs. 2. Set the srst_reg* bit (to take the main registers out of reset), and program the cyc_per_acc and big_end bits in the direct configuration/control register (address 28h). 3. Wait 1 µs for the circuit to stabilize. Extended memory accesses may now be performed only to the main register group. 4. Write the desired values to the main configuration 1 register (address 0100h), the TX UTOPIA clock configura- tion register (address 010Ch), and the RX UTOPIA clock configuration register (address 010Eh) in the extended memory registers. These bits should not be modified at a later time without returning to the reset state. 5. Program the main configuration 2 register (address 0112h) and the UTOPIA configuration register (address 0114h). These registers should not be modified at a later time without returning to the reset state. 6. Program the cb_arb_sel and cb_usr_mode bits in the cell bus configuration/status register (address 0130h). 7. Wait one clock period of the slowest clock (cell bus, UTOPIA, or pclk) for the circuit to stabilize. 8. Set the srst* bit in the direct configuration/control register (address 28h). 9. Wait three clock periods of the slowest clock (cell bus, UTOPIA, or pclk) for the circuit to stabilize. The T8207 device is now out of reset state. 10. Initialize the SDRAM per the SDRAM specifications. 11. Enable the SDRAM by setting the sdram_en bit in the SDRAM control register (address 0400h). 12. Initialize the LUT to benign values (recommended). 13. Initialize the multicast memory to all '0' (recommended). 14. Program the three routing information registers (addresses 0200h through 0204h) and the seven PPD infor- mation registers (addresses 0206h through 0212h).

Agere Systems Inc. 21 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8207

4 Hot Insertion

When a connector with proper pin sequencing is used, the Agere Systems Inc. GTL+ buffers withstand hot inser- tion into a backplane without corrupting the cell bus or damaging the device. The ground pins on the connector should extend beyond all other pins so that the ground connections are made first. In addition, the power pins on the connector should extend beyond the signal pins so that the power connections are made before the signal but after the ground connections. During hot insertion, the cell bus is not corrupted because the GTL+ outputs go to a high-impedance state during the powerup reset. Therefore, proper timing should be met in the external powerup reset circuit.

5 PLL Configuration

Note: When the PLL is engaged, mclk is the output of the PLL. Note: The output of the PLL must always be at least 50 MHz. lists the lf[3:0] settings for given values of M. Typical PLL lock-in time is 50 µs. Table 9. Loop Filter Register Settings

Agere Systems Inc. 23 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8207

6 Microprocessor Interface

6.1 Microprocessor Interface Configuration

The microprocessor interface may be configured for either Intel or Motorola mode via the mot_sel input. Tie mot_sel high to select Motorola mode and low to select Intel mode. In addition, the address and data buses may be configured for multiplexed or nonmultiplexed mode using the mux input. To select multiplexed mode, tie mux high, and to select nonmultiplexed mode, tie mux low. In multiplexed mode, d[7:0] are used for both the address and the data bus, and the a[0] input becomes an address latch enable (ale) signal. In nonmultiplexed mode, sepa- rate address, a[7:0], and data, d[7:0], buses are used. In both modes, the active-low sel* input selects the device for microprocessor read or write accesses. The data leads are 3-stated when the sel*, wr*_ds*, or rd*_wr* signal is high. In Motorola mode, rd*_rw* is a read/write enable signal, which indicates the current access is a read when it is high and a write when low. The wr*_ds* signal is data strobe in Motorola mode. The rdy_dtack* output is an active-low data transfer acknowledge signal. The T8207 takes this signal low when the microprocessor access is complete. The rdy_dtack* output returns high when the microprocessor acknowledges the access by taking the sel* or wr*_ds* signal high. The rdy_dtack* output then goes high-impedance. In Intel mode, the rd*_rw* input is an active-low read enable signal, and wr*_ds* is an active-low write enable sig- nal. A logic low level on rd*_rw* indicates to the T8207 that the current access is a read, and a logic low level on wr*_ds* indicates the access is a write. Finally, the rdy_dtack* output is an active-high ready signal. The T8207 asserts this signal high when a microprocessor access is complete. The rdy_dtack* output then goes high-imped- ance when the sel*, wr*_ds*, or rd*_wr* signal goes high.

6.2 Microprocessor Interrupts

The int_irq* output is an active-high interrupt in Intel mode and an active-low interrupt request in Motorola mode. In Intel mode, int_irq* is normally low and goes high when an interrupt is generated. In Motorola mode, the interrupt request signal is normally high and goes low during an interrupt. Interrupts are generated when an enabled inter- rupt status bit becomes set. All interrupt status bits in the T8207 have a corresponding interrupt enable bit. When the enable bit is cleared, the corresponding interrupt status bit is not enabled and will not generate an interrupt. Several registers containing interrupt status bits exist in the three separate extended memory register groups (main, UTOPIA, and SDRAM) of the T8207. The interrupt service request register at direct address 29h indicates which register group is generating the interrupt. Only enabled interrupts will cause the int_serv_mainreg, int_serv_sdramreg, and int_serv_utopiareg bits to become set. For the main register group, a special case exists. The ctrl_cell_sent and the ctrl_cell_av interrupts (in the main interrupt status 1 register) do not cause the main group indication bit to be set in the interrupt service request register. These interrupts have their own dedicated service request bits to optimize sending and receiving control cells. The ctrl_cell_sent and ctrl_cell_av bits may become set whether the corresponding interrupt is enabled or not.

6.3 Accessing the CelXpres T8207 via Microprocessor Interface

The CelXpres T8207 has two distinct memory spaces, the direct memory access registers and the extended mem- ory registers. The direct memory access registers are directly addressed 8-bit (byte) registers and are mapped between addresses 00h and FFh. The extended memory registers are indirectly addressed and mapped between addresses 0100h and 3FFFFFEh. The extended memory contains the SDRAM memory, the translation RAM, internal memories, and the device’s configuration, status, and control registers. Extended memory registers are 16 bits wide, and all accesses to the extended memory registers are executed internally as 16 bits. Direct memory access registers are located in Section 14.2, Direct Memory Access Registers, and extended memory registers are located in Section 14.3, Extended Memory Registers.

24 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8207

6 Microprocessor Interface (continued)

6.3.1 Accessing the Extended Memory Registers

Before accessing the extended memory registers, the powerup sequence, as described in Section 3, Powerup/ Reset Sequence, must be completed. Accesses to extended memory are word accesses internally; therefore, the least significant bit of the address is always ‘0.’ Only the most significant 25 bits are supplied to the extended mem- ory address registers (addresses 30h—34h). The following procedure outlines the steps needed for extended memory accesses in the T8207 device.

6.3.1.1 Extended Memory Writes

1. Write ext_a [25] bit to the extended memory address 4 register (little endian or big endian) (optional). 2. Write ext_a [24:17] byte to the extended memory address register 3 (little endian or big endian) (optional). 3. Write ext_a [16:9] byte to the extended memory address register 2 (little endian or big endian) (optional). 4. Write ext_a [8:6] bits to the extended memory address register 1 (little endian or big endian) (optional). 5. Write ext_d [15:8] byte to the extended memory data high register (little endian or big endian) (optional). 6. Write ext_d [7:0] byte to the extended memory data low register (little endian or big endian) (optional). 7. Write ext_a [5:1] bits; write “01,” “10,” or “11” to ext_we[1:0]; and write ‘1’ to ext_strt_acc in the extended mem- ory access register (little endian or big endian) (mandatory). 8. Read the extended memory access register (little endian or big endian) to determine that the ext_strt_acc bit has been cleared by hardware (mandatory).

6.3.1.2 Extended Memory Reads

1. Write ext_a [25] bit to the extended memory address 4 register (little endian or big endian) (optional). 2. Write ext_a [24:17] byte to the extended memory address register 3 (little endian or big endian) (optional). 3. Write ext_a [16:9] byte to the extended memory address register 2 (little endian or big endian) (optional). 4. Write ext_a [8:6] bits to the extended memory address register 1 (little endian or big endian) (optional). 5. Write ext_a [5:1] bits; write “00” to ext_we[1:0]; and write ‘1’ to ext_strt_acc in the extended memory access register (little endian or big endian) (mandatory). 6. Read the extended memory access register (little endian or big endian) to determine that the ext_strt_acc bit has been cleared by hardware (mandatory). 7. Read ext_d [15:8] byte from the extended memory data high register (little endian or big endian) (optional). 8. Read ext_d [7:0] byte from the extended memory data low register (little endian or big endian) (optional). Note: Once the ext_strt_acc bit is set by software, only the extended memory access register should be accessed until the ext_strt_acc bit is cleared by hardware.

6.3.2 CelXpres T8207 Access Performance

from the completion of a write to register 34h until the ext_strt_acc bit is cleared. The actual times are dependent on the frequency of the pclk and mclk clocks (see Section 5, PLL Configuration). The terms pclkp and mclkp in the table represent the period of pclk and mclk, respectively, in ns. Table 10. Access Times

26 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8207

7 General-Purpose I/O (GPIO)

The T8207 has eight programmable general-purpose I/O pins called GPIO. These GPIO pins may be indepen- dently programmed, via the GPIO_oe[7:0] bits in the GPIO output enable register (address 39h), to be inputs or outputs. If a GPIO_oe bit is set to ‘1,’ the corresponding GPIO pin is an output, or if cleared to ‘0,’ the correspond- ing GPIO pin is an input. Input values are read from the GPIO_in[7:0] bits in the GPIO input value register (address 3Dh), and output values are written to the GPIO_out[7:0] bits in the GPIO output value register (address 3Bh). The GPIO[7:0] pins all have internal 50 kΩ pull-up resistors.

Agere Systems Inc. 27 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8207

8 Look-Up Table

Cells arriving from the UTOPIA bus obtain information from the external static RAM look-up table (LUT), which is divided among VPI, VCI, and OAM/RM records. Each of these records contains specific VPI or VPI/VCI translation and cell bus routing information. The size of the records is programmable to 8 bytes or an extended 16 bytes. The 16-byte mode adds two 32-bit counters to each record. The 16-byte mode is discussed in Section 8.4, Extended Records. The VPI value in the header, in addition to the PHY port number, of the incoming cell points to a VPI record in the look-up table. This VPI record is examined first. If the VPI record indicates OAM F4 routing, the OAM record, to which the VPI record points, provides the OAM routing and VPI/VCI translation information. If OAM F4 routing is not indicated, information about the type of translation, VPI only or VPI/VCI, is obtained from the original VPI record. For VPI only translation, routing information is obtained from the VPI record, and full or partial VPI transla- tion is performed. For VPI/VCI translation, the VPI record points to the appropriate VCI record, where VPI/VCI translation and routing information is stored. If the VCI record indicates OAM F5 routing, the OAM record, to which the VCI record points, provides the OAM routing and VPI/VCI translation information. If no OAM F5 routing is indicated, VPI/VCI transla- tion and cell routing is performed using the information in the VCI record.

8.1 Look-Up Table RAM

The number of memory devices (up to two) used for the look-up table and the size of the external SRAM are pro- grammable. The tram_qnty_sel bit in the main configuration 1 register (address 0100h) specifies whether one or two RAM chips are used. If two memory devices are used, separate chip select signals are generated. These chip selects are created from the decoded RAM addresses. The tram_size configuration bits, also in the main configu- ration 1 register, are used to select memory sizes of 32 Kbytes, 64 Kbytes, 128 Kbytes, or 256 Kbytes. Therefore, the maximum look-up table size of 512 Kbytes is realized when two RAM chips of 256 Kbytes each are used.

28 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8207

8 Look-Up Table (continued)

8.2 Organization

Organization is discussed in terms of 8-byte records. Differences in organization for 8-byte records and 16-byte records will be discussed in Section 8.4, Extended Records. The look-up table may be configured to support up to 16 ports when multi-PHY mode is used, effectively creating a separate look-up table for each port. For 32 ports, each even and odd pair of ports share a look-up table space. All VPI, VCI, and OAM/RM records may be either 8 bytes or 16 bytes in length. (See Section 8.4, Extended Records for information on 16-byte records.) Figure 4 shows the translation RAM memory map for 8-byte records when the device is configured for 16 or less PHY ports. When greater than 16 PHY ports are used, the look-up table is shared between even and odd ports. Figure 5 shows this translation RAM memory map. OAM/RM transla- tion records are located at the bottom of the memory space with 64 OAM/RM records used by each port. If the device is configured to support 16 to 32 ports, the first 1024 records will be used for OAM and RM translation records. This translates to 8 Kbytes of memory for 8-byte records. The remaining memory is then used for VPI and VCI records. For 8-byte records, when 16 ports or less are used, the base addresses of the OAM records are cal- culated from the following equation: OBA = PN × 8 × 64 In this equation, OBA is the OAM base address, PN is the port number, 8 is the number of bytes per record, and 64 is the number of records per port. For example, the OAM/RM translation records for port 2 will have a base address of 1024 or 400h. For 8-byte records, when greater than 16 ports are used, the base addresses of the OAM records are calculated from the following equation: OBA = INT(PN/2) × 8 × 64 In this equation, OBA is the OAM base address, PN is the port number; 8 is the number of bytes per record, and 64 is the number of records per port. The INT function specifies that the term within the parentheses is an integer, i.e., the fractional part is discarded. For example, the OAM/RM translation records for port 5 will have a base address of 1024 or 400h. Note: If the device is configured to use less than 16 ports, the OAM/RM translation record memory space will be allocated enough memory to handle ports 0 through the maximum port number used. For example, if the device is configured to use ports 0, 2, 4, and 6 (see Section 9, UTOPIA Interface), the OAM/RM translation record memory space will use 448 records (for ports 0 through 6). OAM/RM translation record memory space for ports 1, 3, and 5 will be skipped even though the ports are not used. Note: If the device is configured in PHY mode (see Section 9, UTOPIA Interface), the device supports only a single PHY and the translation RAM memory will be addressed as port 0. Separate VPI record base addresses may be set up for each port in multi-PHY mode (for up to 16 ports), and the number of incoming VPI bits used as a pointer into the look-up table may be programmed. (See Section 14.3, Extended Memory Registers, Table 103.) For 8-byte records, when 16 ports or less are used, the total memory used by the VPI records is calculated using the following equation: MS = NP x 2 NB x 8 In this equation, MS is the memory size used for VPI records, NP is the number of ports used, 8 is the number of bytes per record, and NB is the number of incoming VPI bits used to address the look-up table. For 8-byte records, when greater than 16 ports are used, the total memory used by the VPI records is calculated using the following equation: MS = INT(NP/2) x 2NB x 8 In this equation, MS is the memory size used for VPI records, NP is the number of ports used (greater than 16), 8 is the number of bytes per record, and NB is the number of incoming VPI bits used to address the look-up table. The INT function specifies that the term within the parentheses is an integer, i.e., the fractional part is discarded. This calculated memory space must be reserved for VPI records.

Figure 4. Translation RAM Memory Map—8-Byte Records, for Up to 16 Ports Figure 6. There are two types of VPI translation records: one for VPI translation only and one for VPI/VCI transla- only bits 3 through 18 are stored in the VPI record. translation record. Other control bits in these records are described following Figure 6.

16 PORTS

Figure 5. Translation RAM Memory Map—8-Byte Records, for Greater than 16 Ports

16 PAIRS OF PORTS

Figure 6. Translation Record Types—8-Byte Records is used in all types of records. Table 11. Active and Ignore Truth Table 0 0 The cell is discarded, considered misrouted, and counted as a received cell. 0 1 The cell is discarded, is not flagged as misrouted, and is not counted as a received cell. 1 0 The cell is valid and is counted as a received cell. 1 1 The cell is discarded, is not flagged as misrouted, and is not counted as a received cell.

the appropriate OAM/RM F5 record. This bit is used only in VPI and VCI records. performed. This bit is used only in VPI records. ing bits in the VPI record. See the truth table (Table 12) below. This bit is used in VPI only translation records. bits in the VPI record. See the truth table (Table 12) below. This bit is used in VPI only translation records. Table 12. VPI Value Truth Table ■ OAM Routing Control (C1, C0). These 2 bits determine if the cell is routed as OAM/RM and if VPI/VCI translation is performed. See the truth table (Table 13) below. These bits are used only in OAM/RM records. Table 13. OAM Routing Control Truth Table

1. The most significant 4 bits of the VPI will only be substituted if the global rplc_gfc bit in the direct configuration/control register (address 28h)

is set in UNI mode or if the port is configured in NNI mode. 0 0 No VPI translation is performed. 01 VPI translation is performed only on bits 0—7 of the incoming VPI. 1 0 VPI translation is performed only on bits 8—11 of the incoming VPI. 1 1 Complete VPI translation is performed. dem routing headers in the OAM/RM record.

8.3 Look-Up Procedure

the cell is out of range, it is discarded and not counted as a received cell. valid, the enable OAM/RM routing (E) bit is consulted to determine if F4 type OAM cell treatment should occur. translation record address is the sum of the port’s OAM base address and 100h. routing header are then added to the cell, and the cell is transmitted on the cell bus. tion 8.2, Organization.) Again, the validity of the VCI translation record is determined by checking its A and I bits. Table 14. F5 Translation Record Addresses Table— 8-Byte Records

34 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8207 Next, the validity of the F5 OAM record is determined by checking its A and I bits. If it is valid, the cell is routed as described by the OAM routing control (C1, C0) bits. (See the definition for these bits in Section 8.2, Organization.) If the E bit in the VCI record is not one or if the C1 and C0 bits in the OAM record are zero and one, respectively, the cell does not receive OAM routing. If the cell is not routed as an OAM cell, information in the VCI translation record is used to route the cell. The cell's VPI and VCI are replaced with the VPI and VCI, respectively, in the VCI record. The most significant 4 bits of the VPI will only be substituted if the global rplc_gfc bit in the direct configura- tion/control register (address 28h) is set or if the port is configured in NNI mode. The cell bus routing header and tandem routing header are then added to the cell, and the cell is transmitted on the cell bus. Note: Unused OAM cell routing records in the LUT memory space can be used for other purposes.

This look-up procedure is outlined in the flow diagram below. Figure 7. Translation RAM Flow Diagram

36 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8207

8.4 Extended Records

The length of the translation records may be extended to 16 bytes to support two cell counts for each translation record. The lut_rec_form bits in the extended LUT configuration register (address 011Eh) are used to select this extended mode. In extended (16-byte) mode, two 32-bit counters are appended to the 8-byte records. The first counter in the translation record, total cell count, keeps a total count of all incoming cells received from the UTOPIA bus and ultimately routed from this record. See the definition of the A and I bits in Section 8.2, Organiza- tion. The second counter, special cell count, is a subset of the total cell count counter. This counter counts only cells whose PTI and CLP values in the cell header match the values specified in the extended LUT control register (address 0120h). For example, this counter may be used to track specific F5 type OAM/RM cells and cells indicat- ing forward congestion (EFCI = 1) or lower priority (CLP = 1).

The four translation record types for extended mode are illustrated in Figure 8 below. Figure 8. Translation Record Types—Extended Mode

38 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8207 Because the translation records are larger in extended mode, the look-up table memory map changes, the transla- tion record address calculations change, and the memory size calculations change. Figure 9 shows the new trans- lation RAM memory map for 16-byte records when the device is configured for 16 or less PHY ports. When greater than 16 PHY ports are used, the look-up table is shared between even and odd ports. Figure 10 shows this trans- lation RAM memory map. Figure 9 . Translation RAM Memory Map—Extended Mode, for Up to 16 Ports ROUTING LOOK-UP MEMORY MAP OAM CELL ROUTING PORT X RECORD MAP 0000h OAM CELL ROUTING PORT 0 +0000h VP OAM VCI = 0 (F4) 0400h OAM CELL ROUTING PORT 1 • 0800h OAM CELL ROUTING PORT 2 0C00h OAM CELL ROUTING PORT 3 1000h OAM CELL ROUTING PORT 4 +01F0h VP OAM VCI = 31 (F4) 1400h OAM CELL ROUTING PORT 5 +0200h VP OAM VCI = 6 & PT = “110” (F4) (RM-VPC) 1800h OAM CELL ROUTING PORT 6 +0210h VC OAM PTI = “100” (F5) 1C00h OAM CELL ROUTING PORT 7 +0220h VC OAM PTI = “101” (F5) 2000h OAM CELL ROUTING PORT 8 +0230h VC OAM PTI = “110” (F5) 2400h OAM CELL ROUTING PORT 9 +0240h VC OAM PTI = “111” (F5) 2800h OAM CELL ROUTING PORT 10 +0250h RESERVED 2C00h OAM CELL ROUTING PORT 11 +0260h RESERVED 3000h OAM CELL ROUTING PORT 12 • 3400h OAM CELL ROUTING PORT 13 3800h OAM CELL ROUTING PORT 14 3C00h OAM CELL ROUTING PORT 15 +03F0h RESERVED 4000h ANY PURPOSE LOOK-UP MEMORY SHARED BETWEEN EACH OF THE

Figure 10. Translation RAM Memory Map—Extended Mode, for Greater than 16 Ports bytes per record, and 64 is the number of records per port. parentheses is an integer, i.e., the fractional part is discarded.

table. The OAM translation record address is the sum of this offset and the port’s OAM base address. Table 15. F5 Translation Record Addresses Table— Extended Mode bytes per record, and NB is the number of incoming VPI bits used to address the look-up table. that only bits 3 through 18 of the VPI base address are stored in the LUT X configuration structure. through 18 of the VCI offset which is obtained from the VPI record. This sum is the final offset into the look-up table.

Agere Systems Inc. 41 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8207

8.5 Diagnostics

The T8207 also includes diagnostics to track misrouted cells. A cell is considered misrouted if its A and I bits are “00,” if its VCI is out of range, or if the lutX_vpi_chk bit is ‘1’ and the unused VPI bits in the incoming cell header are not all zero (see Section 8.3, Look-Up Procedure). When a misrouted cell is detected, the misrouted cell header high and low registers (addresses 0146h and 0148h) may be updated. If enabled, the mis_cell interrupt, the vci_or interrupt, or the vpi_or interrupt will be generated as appropriate (see Table 79 in Section 14.3, Extended Memory Registers). The misrouted cell header high and low registers contain the first four header bytes of selected misrouted cells. Only a misrouted cell from a port whose mis_cell_lut_sel bit is set will update these registers, and this misrouted cell will update the registers only if it is the first received after the mis_cell_clr bit is set. The lst_mis_cell_lut bits indicate the port from which the header bytes in the misrouted cell header high and low registers were received. The mis_cell_lut_sel bits are located in the misrouted LUT 1 register (address 0142h). The mis_cell_clr, mis_cell_latch, and lst_mis_cell_lut bits are located in the misrouted LUT 2 register (address 0144h). (See Tables 70 and 71 in Section 14.3, Extended Memory Registers, for a complete description of the above bits.)

8.6 Setup

When configuring the lut_en bits in the LUT X configuration/status register (addresses 0320h through 033Eh), care must be taken to ensure that the enabled ports’ LUTs correspond to the ports chosen in UTOPIA mode. (See Sec- tion 9.6, UTOPIA Pin Modes.) If a LUT is not enabled, corresponding bits in the LUT X configuration structure (Section 14.3.2.3, RX UTOPIA Monitoring, Table 103) will be ignored. Also, when the device is configured for UTO- PIA PHY mode (see Section 9, UTOPIA Interface), only port 0 entries in the external RAM look-up table are used; therefore, the look-up table should be set up accordingly.

42 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8207

9 UTOPIA Interface

The CelXpres T8207 supports the ATM Forum’s UTOPIA level 1 and level 2 specifications for cell-level handshake and MPHY operation with rates up to 353 Mbits/s. The device may be configured as an ATM layer or as a PHY layer by programming the phyen* bit in the main configuration 1 register (address 0100h). As an ATM layer, the device may interface with a single PHY layer or multiple PHY layers (up to 32). Also as an ATM layer, it may be configured for shared UTOPIA mode if 16 or less PHYs are used. (Note that if shared UTOPIA mode is not used, the slave_en bit in the main configuration/control register (address 0110h) must be cleared at device setup.) In PHY mode, the T8207 functions as a single PHY device on the UTOPIA bus or as one of 31 PHY devices on the UTOPIA level two bus. In addition to the required UTOPIA signals, the T8207 supports an additional three transmit and three receive enable (u_txenb*[3:1] and u_rxenb*[3:1]) signals, an additional three transmit and three receive cell available (u_txclav[3:1] and u_rxclav[3:1]) signals, a transmit parity (u_txprty) signal, and a receive parity (u_rxprty) signal. The T8207 UTOPIA signal names begin with u_tx, for UTOPIA transmit, or u_rx, for UTOPIA receive. Refer- ences to transmit or receive are made relative to the UTOPIA data flow for the ATM layer UTOPIA interface. Therefore, signals starting with u_rx, such as u_rxenb*[3:0] and u_rxdata[7:0], are receive UTOPIA signals for devices in ATM mode but are transmit UTOPIA signals for devices in PHY mode. Furthermore, signals such as u_txclav[3:0] and u_txaddr[4:0] are transmit UTOPIA signals for devices in ATM mode but are receive UTOPIA signals for devices in PHY mode. The above ATM to PHY terminology will be used throughout this UTOPIA Interface section.

Agere Systems Inc. 43 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8207

9 UTOPIA Interface (continued)

9.1 Incoming UTOPIA Cell Interface

9.1.1 Incoming PHY Mode (Cells Received by T8207)

In PHY mode, only one enable (u_rxenb*[0]) signal and one cell available (u_rxclav[0]) signal are used. The u_rxenb*[0] signal is an input connected to the ATM layer’s TxEnb* signal, and the u_rxclav[0] signal is an output connected to the ATM layer’s TxClav signal. As a PHY device, the T8207 uses only the LUT 0 configuration/status register (address 0320h) and LUT 0 configuration 1 registers (addresses 0704h—0706h). For UTOPIA level 2 functionality, the PHY address is programmed in the addr_match bits of the UTOPIA configuration register (address 0114h), and the addr_clav_en bits of the main configuration 2 register (address 0112h) can be pro- grammed to any value mentioned in the register except “000.” As specified in the UTOPIA level 2 specification, during the polling process, the T8207 drives the u_rxclav[0] signal during the clock cycle following the cycle in which its address appears on the u_rxaddr pins. The u_rxclav[0] pin goes high impedance when not selected to support MPHY operation. In UTOPIA level 1, the above level 2 bits are not meaningful; therefore, the addr_clav_en bits must be programmed to “000,” the u_rxaddr pins must be grounded, and the addr_match bits cleared. When the T8207 device is in PHY mode, if bit 5 (dont_inhibit_rxphy_clav) of register 0112h is cleared to ‘0,’ the rx_clav signal is deasserted if the RX UTOPIA FIFO is considered full. If this bit is set to ‘1,’ the T8207 keeps the rx_clav signal always asserted high indicating the capability to accept cells even if the RX UTOPIA FIFO could overrun, or is actually overrun.

9.1.2 Incoming ATM Mode (Cells Received by T8207)

In ATM mode, the T8207 may connect to PHY devices that either meet level 1 or level 2 UTOPIA specifications. If the connection is to devices that meet only UTOPIA level 1 specifications, the T8207 may access up to four of these PHY devices using the four enable (u_rxenb*[3:0]) and cell available (u_rxclav[3:0]) signals. Connection to more than one PHY device is possible only if the PHY’s data, start of cell, and parity outputs go high impedance when the device is not enabled. Polling of the cell available signals usually occurs while the current cell is received. If the T8207 connects to PHY devices meeting level 2 UTOPIA specifications, one RxCLAV/RxENB pair supports up to 16 PHY ports. For 32 PHY ports, two RxCLAV/RxENB pairs support two groups of 16 PHY ports for a total of 32 PHY ports. In ATM MPHY mode, the u_rxdata[7:0], u_rxaddr[4:0], u_rxsoc, and u_rxprty signals are connected to each PHY port. In addition, the T8207 generates the address (u_rxaddr[4:0]) signals, permitting selection and arbitration among the MPHY ports. The number of address lines used in the connection may vary from one to four, giving a maximum address value of 15. (All five address lines must be connected to provide for the NULL address.) Refer to Section 9.6, UTOPIA Pin Modes, for more information about the possible combinations of address, cell available, and enable signals. The UTOPIA specification for operation with one TxClav and one RxClav is used when the T8207 connects to multiple level 2 PHY devices. Whether the T8207 is connected to several level 1 or level 2 PHY devices, a round-robin algorithm is implemented that ensures that all PHY devices are serviced (accessed) in a timely manner. In addition, the number of clock cycles wasted for bus arbitration is minimized because polling is performed during cell transfer. In ATM mode, all unused u_rxclav inputs require connection to ground. Note:The u_rxenb outputs are high impedance during powerup and reset. An attached PHY may interpret this high-impedance state as an enable; however, the T8207 is not ready to properly handle input data during this time. Attach pull-up resistors to these outputs if a problem is anticipated. When the T8207 is in ATM mode, if bit 6 (inhibit_rxuto_fifo_overrun) of register 0112h is set to ‘1,’ the T8207 pre- vents the RX UTOPIA FIFO from overflowing by deasserting its rx_enb* signal even though the rx_clav signal is high when polled, if the RX UTOPIA FIFO is considered full. If this bit is cleared to ‘0,’ the rx_enb* signal is not deasserted even if the RX UTOPIA FIFO is considered full.

44 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8207

9.2 Outgoing UTOPIA Cell Interface

9.2.1 Outgoing PHY Mode (Cells Sent by T8207)

In PHY mode, only one enable (u_txenb*[0]) signal and one cell available (u_txclav[0]) signal are used. The u_txenb*[0] signal is an input connected to the ATM layer’s RxEnb* signal, and the u_txclav[0] signal is an output connected to the ATM layer’s RxClav signal. As a PHY device, the T8207 may use queue group 0 (queues 0, 1, 2, and 3) in the SDRAM and TX UTOPIA cell buffer. The div_queue bits in the main configuration 2 register (address 0112h) may be programmed to “000” for 4 queues or “101” for 1 queue, and the port_rte[63:0] bits in the TX PHY FIFO routing 0, 1, 2, and 3 registers (addresses 017Ch, 017Eh, 017Ah, and 0178h respectively) must be pro- grammed to zero. If only queue 0 is used, configure and use only the queue 0 registers at addresses 0440h and 2000h through 2016h. Also, if only queue 0 is used, program the mphy_select bits and priority_select bits in the routing information 1, 2, and 3 registers addresses 0200h, 0202h, and 0204h to the zero value of “110000.” If queues 0, 1, 2, and 3 are used, configure and use only the queue 0, 1, 2, and 3 registers at addresses 0440h through 0446h and 2000h through 2076h. Also, if queues 0, 1, 2, and 3 are used, only the mphy_select bits in the routing information 1 and 2 registers (addresses 0200h and 0202h) must all be programmed to the zero value of “110000.” For UTOPIA level 2 functionality, the PHY address is programmed in the addr_match bits of UTOPIA configuration register (address 0114h), and the addr_clav_en bits of the main configuration 2 register (address 0112h) can be programmed to any value mentioned in the register except “000.” As specified in the UTOPIA level 2 specification, the T8207 drives the u_txclav[0] signal during the clock cycle following the one with its address on the u_txaddr pins. The u_txclav[0] pin goes high impedance when not selected to support MPHY operation. When the tx_utopia_hi_z bit in the main configuration 1 register (address 0100h) is cleared, the u_txsoc, u_txdata[7:0] and u_txprty outputs go high impedance when not selected, allowing multiple PHYs to be connected on the same UTO- PIA bus. In UTOPIA level 1, the above level 2 bits are not meaningful; therefore, the addr_clav_en bits must be programmed to “000,” the u_txaddr pins must be grounded, and the addr_match bits cleared. Note: If the SDRAM is bypassed, the T8207 uses only queue 0 in the TX UTOPIA cell buffer. Note:Even though the outgoing (egress) queues are 0—3, the egress port is determined by the address match bits in register 0114h.

Agere Systems Inc. 45 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8207

9.2.2 Outgoing ATM Mode (Cells Sent by T8207)

In ATM mode, the T8207 may connect to PHY devices that either meet level 1 or level 2 UTOPIA specifications. If connection is to devices that meet only UTOPIA level 1 specifications, the T8207 may access up to four of these PHY devices using the four enable (u_txenb*[3:0]) and cell available (u_txclav[3:0]) signals. Polling of the cell available signals occurs while the current cell is transmitted. If the T8207 connects to PHY devices meeting level 2 UTOPIA specifications, one TxCLAV/TxENB pair supports up to 16 PHY ports. For 32 PHY ports, two TxCLAV/TxENB pairs support two groups of 16 PHY ports for a total of 32 PHY ports. In ATM MPHY mode, the u_txdata[7:0], u_txaddr[4:0], u_txsoc, and u_txprty outputs are connected to each PHY port. In addition, the T8207 generates the address (u_txaddr[4:0]) signals, permitting selection and arbitration among the ports. The number of address lines used in the connection may vary from one to four giving a maximum address value of 15. (All five address lines must be connected to provide for the NULL address.) Refer to Section 9.6, UTOPIA Pin Modes, for more information about the possible combinations of address, cell available, and enable signals. The UTOPIA specification for operation with one TxClav and one RxClav is used when the T8207 connects to multiple UTOPIA level 2 PHY devices. In ATM mode, all unused u_txclav inputs require connection to ground. Note:The u_txenb outputs are high impedance during powerup and reset. An attached PHY may interpret this high-impedance state as an enable; however, the T8207 is not ready to send data during this time. Attach pull-up resistors to these outputs if a problem is anticipated. The TX UTOPIA cell buffer holds the next cells to be transmitted onto the UTOPIA bus. This TX UTOPIA cell buffer, which holds 128 cells, may be divided into 1, 4, 8, 16, 32, or 64 queues using the div_queue bits in the main configuration 2 register (address 0112h). The number of ports that the T8207 supports determines the number of queues that should be chosen. (See Section 9.6, UTOPIA Pin Modes.) The number of cells per queue, held by the buffer, is determined by dividing 128 (maximum number of cells that TX UTOPIA cell buffer holds) by the number of queues selected (e.g., two cells per queue for 64 queues and 32 cells per queue for 4 queues). If the T8207_sel bit in the main configuration 2 register, Table 59, is set, each port is assigned four queues in the TX UTOPIA cell buffer except in the case of 32 ports. For 32 ports, each port is assigned two queues. Each group of four queues is priority encoded where the lowest-numbered queue has the highest priority. Groups of four queues are shared among two ports as follows: ■ Queues 0—3 are shared between ports 0 and 1. ■ Queues 4—7 are shared between ports 2 and 3. ■ Queues 8—11 are shared between ports 4 and 5. ■ Queues 12—15 are shared between ports 6 and 7. ■ Queues 16—19 are shared between ports 8 and 9. ■ Queues 20—23 are shared between ports 10 and 11. ■ Queues 24—27 are shared between ports 12 and 13. ■ Queues 28—31 are shared between ports 14 and 15. ■ Queues 32—35 are shared between ports 16 and 17. ■ Queues 36—39 are shared between ports 18 and 19. ■ Queues 40—43 are shared between ports 20 and 21. ■ Queues 44—47 are shared between ports 22 and 23. ■ Queues 48—51 are shared between ports 24 and 25. ■ Queues 52—55 are shared between ports 26 and 27. ■ Queues 56—59 are shared between ports 28 and 29. ■ Queues 60—63 are shared between ports 30 and 31.

ters, respectively. Figure 11 illustrates the selection of ports when 32 are used. and 3 to the odd-numbered ports. Figure 11. Queue Priority Multiplexing because polling is performed during cell transfer. lates the HEC and inserts it into each cell before transmitting it onto the UTOPIA bus. See Figure 12.

9.3 Counters

Table 102 in Section 14.3.2.3, RX UTOPIA Monitoring, for the addresses of other ports' incoming cell counters. 14.3.2.2, TX UTOPIA Monitoring, for the addresses of other ports' outgoing cell counters.

[7:0] byte. Clearing the sp_utopia_sel* bit in the main configuration 1 register (address 0100h) enables this mode. configured for 55-byte UTOPIA mode whether it is an ATM or PHY device. Figure 12. TX UTOPIA Cell Handling

48 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8207

9.5 Shared UTOPIA Mode

The shared UTOPIA mode supports up to 16 PHY ports using only 32 queues, and it allows two T8207 devices on different cell buses to share the same UTOPIA bus. This shared mode can be used to provide redundancy or to increase the cell bus system capacity. One T8207 device is configured as master and the other as slave, using the slave_en bit in the main configuration/control register (address 0110h). The master and the slave communicate to each other through the shared UTOPIA output (u_shr_o) and input (u_shr_i) pins. For the master, u_shr_o func- tions as the grant output, and u_shr_i, as the request input. For the slave, u_shr_o functions as the request output, and u_shr_i, as the grant input. Only T8207 devices configured for ATM mode may be used in shared UTOPIA mode. This configuration is supported for both UTOPIA level 1 and 2 configurations. The configuration for the addr_clav_en bits must be the same in both devices in MCF2 (0112h) and port_rte (0178h to 017Eh) registers. Note:The T8207 will support shared UTOPIA mode for only up to 32 queues. To use shared UTOPIA with 16 PHY ports, only 32 queues, shared between even and odd ports can be used, which translates to a zero value for the T8207_sel bit (Table 59). The TX UTOPIA cell buffers in the master and the slave may be divided into the same number of queues or differ- ent number of queues. The mast_queue_in[31:16], mast_queue_in[15:0], slav_queue_in[31:16], and slav_queue_in[15:0] bits in the master queue 0 (address 015Ch), master queue 1 (address 015Eh), slave queue 0 (address 016Ch), and slave queue 1 (address 016Eh) registers, respectively, must be configured in the master device. These bits indicate which queues in the master and which queues in the slave are enabled. The master’s priority algorithm uses this information to determine which waiting cell should be transmitted. The slave queue 0 and 1 registers are ignored in the slave. The transmit operation in shared UTOPIA mode is illustrated in Figure 13. For the transmit interface, all enable, start of cell, and data signals occur relative to the low-going start of grant signal from the master. The start of grant signal occurs every 60 clock cycles and is always preceded by at least six clock cycles of ones. Both devices transmit on the TX UTOPIA bus; the master arbitrates the bus and grants the slave access via its u_shr_o pin. When the slave has cells waiting for transmission, it makes a request for each queue (up to 32) that contains cells. To make this request, the slave pulls its request output low for one clock cycle during the queue’s request period. The request period for each queue is assigned relative to the master’s start of grant signal. The request period for queue zero occurs ten clock cycles after the start of grant and is followed by the request period for queue one. The master uses the received queue number and a priority algorithm to determine if a slave’s cell should be transmitted before one of its own. Both master and slave have an equal chance to transmit cells if the cells have equal priority. The master grants the slave’s request by sending 8 bits of serial data, clocked at the rate of the UTOPIA transmit clock, to its grant output. The first bit is the low-going grant signal. The next 5 bits desig- nate the queue number of the cell to be transmitted. The queue number is sent most significant bit first. The next bit is the valid bit; it is low if this grant is valid. Finally, the last bit (R[0]) is reserved for future use. The slave then has 53 cycles or 55 cycles to transmit its cell depending on the mode. In UTOPIA receive mode, the master controls the UTOPIA bus, and the slave only monitors the bus. Both master and slave receive all cells and use their individual look-up tables to determine which cells are destined for their cell bus. The master controls the enable (u_rxenb[3:0]) and address (u_rxaddr[4:0]) signals to the UTOPIA bus. The slave monitors these signals to determine when the cell starts and which port is sending the cell. In shared UTOPIA mode, the master always drives the u_rxaddr[4:0], u_txaddr[4:0], u_txsoc, u_rxenb*[3:0], and u_txenb*[3:0] signals. These signals become high impedance on the slave when the slave_en bit in the main con- figuration/control register (address 0110h) is set. Both the master and slave drive the u_txprty and u_txdata[7:0] signals when they transmit a cell; therefore, these signals must transition to a high-impedance state when not active. Clear the tx_utopia_hi_z bit in the main configuration 1 register (address 0100h) to force the u_txprty and u_txdata[7:0] signals to a high-impedance state when inactive.

Figure 13. TX UTOPIA Bus Sharing

50 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8207

9.6 UTOPIA Pin Modes

In multi-PHY mode, the T8207 interfaces with up to 32 PHY ports. Each port is numbered and accessed using a certain combination of the cell available/enable (Clav/Enb*) and address (Addr) signals. The addr_clav_en bits in the main configuration 2 register (address 0112h) are used to select this combination of cell available/enable and address signals. Table 16 indicates the port numbering for each of the possible configurations. The first selection of zero address and four cell available/enable signals (a value of “000” in bits 2:0 of register 0112h) is used for connection to UTOPIA level one devices. Use this selection to connect from one to four PHY devices to the T8207 in ATM mode. If only one PHY is connected, any of the four cell available signals may be con- nected to the PHY. For two PHY devices, connect any two (internal port number must be matched to the clav being used). All unused u_rxclav inputs require connection to ground. Four queues are allocated per PHY in this configu- ration. The second selection of one address and four cell available/enable signals (a value of “010” in bits 2:0 of register 0112h) is used for connection to UTOPIA level two devices. The selection may be used for up to four PHY groups of two ports each. (See Appendix 1 of The ATM Forum Technical Committee UTOPIA Level 2, Version 1.0 specifi- cation.) All unused u_rxclav inputs require connection to ground. Four queues are allocated per PHY in this config- uration. The third selection of two address and four cell available/enable signals (a value of “101” in bits 2:0 of register 0112h) is used for connection to four UTOPIA level 2 PHY groups of four ports each. If the T8207_sel bit in register 0112h is set, four queues are allocated per PHY. If the T8207_sel bit is cleared, two queues are allocated per PHY if the normal 16-port mode described in Section 11.4, Queuing is used or a programmable number of queues can be allocated per PHY based on the settings in registers 017Ch—017Eh. The fourth selection of two address and two cell available/enable signals (a value of “100” in bits 2:0 of register 0112h) is used for connection to two UTOPIA level 2 PHY groups of four ports each. All unused u_rxclav inputs require connection to ground. Four queues are allocated per PHY in this configuration. The fifth selection of three address and two cell available/enable signals (a value of “111” in bits 2:0 of register 0112h) is used for connection to two UTOPIA level 2 PHY groups of eight ports each. All unused u_rxclav inputs require connection to ground. If the T8207_sel bit in register 0112h is set, four queues are allocated per PHY. If the T8207_sel bit is cleared, two queues are allocated per PHY if the normal 16-port mode described in Section 11.4, Queuing is used or a programmable number of queues can be allocated per PHY based on the settings in registers 017Ch—017Eh. The sixth selection of three address and one cell available/enable signals (a value of “110” in bits 2:0 of register 0112h) is used for connection to eight UTOPIA level 2 PHY ports. All unused u_rxclav inputs require connection to ground. Four queues are allocated per PHY in this configuration. The seventh selection of four address and one cell available/enable signals (a value of “001” in bits 2:0 of register 0112h) is used for connection to sixteen UTOPIA level 2 PHY ports. All unused u_rxclav inputs require connection to ground. If the T8207_sel bit in register 0112h is set, four queues are allocated per PHY. If the T8207_sel bit is cleared, two queues are allocated per PHY if the normal 16-port mode described in Section 11.4, Queuing is used or a programmable number of queues can be allocated per PHY based on the settings in registers 017Ch—017Eh. Finally, the eighth selection of four address and two cell available/enable signals (a value of “011” in bits 2:0 of reg- ister 0112h) is used for connection to two UTOPIA Level 2 PHY groups of 16 ports each. All unused u_rxclav inputs require connection to ground. The T8207_sel bit in register 0112h must be set to ‘1’ for this mode. Two queues are allocated per PHY, if the normal 32-port mode described in Section 11.4, Queuing is used or a programmable number of queues can be allocated per PHY based on the settings in registers 0178h—017Eh.

Table 16. Port Numbering for MPHY Configurations

Table 16. Port Numbering for MPHY Configurations (continued)

Agere Systems Inc. 53 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8207

9.7 UTOPIA Clocking

All TX UTOPIA signals in the T8207 are clocked on the rising edge of the TX UTOPIA clock, and all RX UTOPIA signals are clocked on the rising edge of the RX UTOPIA clock. The UTOPIA specifications state that the ATM layer supplies the transmit and receive UTOPIA interface clocks to the PHY layers. The T8207 may be configured to drive these clocks or to be driven by them. In the T8207, the clocks for transmit and receive UTOPIA interfaces may be independently derived from several sources. In addition, each of these clocks may be independently configured. The TX UTOPIA clock configuration (address 010Ch) and RX UTOPIA clock configuration (address 010Eh) registers are used to select and configure the transmit UTOPIA interface and the receive UTOPIA interface clocks, respectively. See these register descrip- tions for more information.

54 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8207

10 Cell Bus Interface

10.1 General Architecture

The high bandwidth, 32-bit cell bus is used to interconnect T8207 devices. Up to 32 devices may be connected to the bus, and cell exchange may occur between any of these devices. Each cell bus frame is 16 clock cycles, and during these 16 cycles, one cell is transmitted. The T8207 is designed to operate with a maximum cell bus fre- quency of 66 MHz, which translates to a cell bandwidth of 1.7 Gbits/s. The maximum achievable frequency for a given bus implementation is dependent on loading and other design considerations. In addition to the 32 bits of data, the cell bus uses four additional control signals. The four signals include a read clock, a write clock, a frame synchronization signal, and an acknowledge signal. The read and write clocks (cb_rc* and cb_wc* pins, respectively) establish the timing for reading and writing cells on the bus and are generated from an external clock source. The read clock is used to read the cell from the cell bus, and the write clock is used to write the cell to the cell bus. Because all devices on the cell bus read and write on the same clock edge, the write clock is delayed slightly, relative to the read clock, to ensure sufficient data hold time. The active-low frame sync (cb_fs*) is generated by the bus arbiter and indicates the first cycle of the cell bus frame in 16 user mode or the first cycle of two cell bus frames for 32 user mode. This signal is generated every 16 clock cycles for 16 user mode or every 32 clock cycles for 32 user mode. The acknowledge (cb_ack*) signal is used to acknowledge the successful receipt of a cell. This signal is asserted low during the next request cycle by the T8207 that receives the cell. This signal is not asserted for multicast or broadcast cells. In the event of an overflow in the control cell RX FIFO, the loopback FIFO, the TX PHY FIFO, or the cell bus input FIFO, the acknowledge signal will assert low. In the case of an overflow, this signal will not assert low for multicast and broadcast cells. When cb_disable* is asserted, the device can receive data on the cb_d*[31:0] but cannot transmit data. The device cannot assert the cb_ack* even when a valid cell is received from the cell bus, if cb_disable* is asserted. Several T8207 devices may reside on the cell bus, but one device must be configured as bus arbiter by clearing the cb_arb_sel bit in the cell bus configuration/status register (address 0130h) or by pulling the arb_en* lead low. The cell bus arbiter receives requests for access to the bus from all resident devices during the first cycle of the cell bus frame and grants one of these requests during the last cycle of the cell bus frame. Before issuing the grant and while a cell is transmitted on the cell bus, the arbiter executes its arbitration algorithm to determine the next device to transmit on the bus. The arbiter also generates the frame synchronization signal. Software shall designate only one device as cell bus arbiter, at any given time, to ensure proper operation of the bus. A 5-bit unit address is assigned to each device (up to 32) on the bus. Each device uses this address to request cell transmission and to identify incoming cells destined for them. Each device is given a unique unit address by indi- vidually tying each address (ua*[4:0]) input high or low. The unit address inputs are active-low; therefore, a device with its ua*[4:0] inputs tied to “10000” has address 15. The device makes a cell transmission request by driving the two assigned bits during the request cycle, which is the first cycle of a frame. For example, device 15 uses bits 30 and 31 of the request cycle as its request bits. (See Section 10.2, Cell Bus Frames.) Also, each device uses its unit address to determine if a received cell is destined for it. (See Section 10.3, Cell Bus Routing Headers.)

Agere Systems Inc. 55 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8207

10 Cell Bus Interface (continued)

The cell bus may be configured for 16-user or 32-user mode using the cb_usr_mode bit in the cell bus configura- tion/status register (address 0130h). In 16-user mode, all 16 devices assert their transmission requests during the first cycle of each frame, and the transmission grant for the next frame is given during the last cycle of the frame. In 32-user mode, the frame synchronization signal is asserted every two cell bus frames. The two frames are termed the odd and even frames. The frame synchronization signal marks the beginning of the even frame, and the odd frame starts 16 clock cycles later. During the request cycle of the even frame, devices zero through 15 assert their transmission requests, and during the request cycle of the odd frame, devices 16 through 31 assert theirs. Requests received from odd and even frames are serviced as a group, and grants are given in the order that the requests are received with the highest priority serviced first with the same priority requests serviced using a round- robin algorithm. Transmission grants for the next frame are always given at the end of the current frame. Cells to be transmitted onto the cell bus come from three sources internal to the T8207. Data cells from the UTOPIA bus are placed in the RX PHY FIFO to await transmission onto the cell bus. Control cells from the micro- processor wait in the control cell TX FIFO, and loopback cells from the cell bus wait in the loopback FIFO. Cells from these three FIFOs are priority multiplexed onto the cell bus output FIFO to be transmitted onto the cell bus. Optional high priority can be established for data cells or control cells sent to the cell bus. If bit 9 in register 0130h is cleared to ‘0’ then cells from the RX PHY FIFO have the highest priority, cells from the control cell TX FIFO have next highest, and finally, cells from the loopback FIFO have the lowest. If bit 9 in register 0130h is set to ‘1,’ then cells from the control cell TX FIFO have the highest priority, cells from the RX PHY FIFO have the next highest pri- ority, and finally, cells from the loopback FIFO have the lowest priority. This bit on default is ‘0.’ Incoming cells may be broadcast, multicast, or single address types. The T8207 receiving device accepts single address cells with an address field in the cell bus routing header that matches the device’s unit address. In addi- tion, the device accepts all broadcast cells and certain multicast cells that it is configured to accept. (See Section 10.3.4, Multicast Routing (continued).) Before a cell is accepted, a check is done on the previous grant to verify whether it is a valid grant or not. The receiving device verifies the cell bus routing header cyclic redundancy check (CRC-4) value in the least significant 4 bits of the cell bus routing header. It also verifies the bit interleave parity (BIP-8) value from bits 24 to 31 of the last cell bus frame cycle. If either is corrupt, the cell is discarded. If kept, cells are routed to the loopback FIFO, control FIFO, or TX PHY FIFO, based on the information in its cell bus routing header. See Section 10.3, Cell Bus Routing Headers.

10.2 Cell Bus Frames

A cell bus frame is always 16 clock cycles. The cell bus frame has three sections (request, bus cell, and grant). bus cell includes the cell bus routing header, the optional tandem routing header, and the 52-byte body of the cell. Figure 14. Cell Bus Frame Format (Bit Positions for 16 User Mode)

Figure 15. Cell Bus Frame Format (Bit Positions for 32 User Mode)

58 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8207 Devices on the cell bus make their requests during the first cycle of each frame. In 16-user mode, each device asserts a request every frame. In 32-user mode, each device asserts a request every two frames. In 32-user mode, devices with unit addresses 0 through 15 assert their requests during the even frames, and devices with unit addresses 16 through 31 assert their requests during the odd frames. During cycle 0 of their assigned frame, each device drives two of the 32 data bits available. The position of the two request bits for each device is based on the device’s unit address. The assigned bit positions for each device are illustrated in Figure 14 and Figure 15 for 16-user and 32-user modes, respectively. For example, in the figures, the device with unit address 0 makes its requests using the 2 bits labeled as U0. Two bits, instead of one, are used for each device so the priority of the request may be included. The priority of the request is set up using the cb_req_pr bits in the main configura- tion/control register (address 0110h). See Table 58 in Section 14.3, Extended Memory Registers, for more informa- tion. During clock cycles 1 through 14, the device that was granted the bus at the end of the previous frame sends its bus cell. The bus cell sent includes the cell bus routing header, the tandem routing header, and the original UTOPIA cell with the header error check (HEC) byte removed. The HEC byte is removed because the cell bus does its own error check over the complete cell using the bit interleave parity byte. The HEC byte is recreated and inserted before the received cell is placed on the UTOPIA bus. The cell bus routing header indicates the type of the cell (data, control, loopback) and its destination (single, multi- cast, broadcast). See Section 10.3, Cell Bus Routing Headers, for more information on the cell bus routing header structure. The optional tandem routing header is configured by the user. The 32 bits of the grant section of the frame (clock cycle 15) includes the bit interleave parity (BIP-8) byte, the grant parity bit, the grant enable bit, and the grant number. The most significant 8 bits of the grant section of the frame is the BIP-8 byte. The BIP-8 byte is calculated over 54 bytes starting with the first tandem routing header byte and ending with the last payload byte. To calculate this bit interleave parity, an exclusive-OR operation is performed on the first byte of the tandem routing header and the value “11111111.” The exclusive-OR operation then is performed on this result and the following byte. The operation is then repeated with every successive byte through the last data byte of the payload. The resulting byte becomes the BIP-8 byte of the grant section. The next 17 bits of the grant section are unused. The least significant 7 bits of the grant section are used to grant transmission requests. The grant number is located in the least significant 5 bits of the grant section and is the unit address of the device that transmits a cell during the next frame. The grant enable, bit 5, is an active-high signal that indicates if the grant is valid. Finally, the grant parity, bit 6, is the odd parity check calculated over the other six grant bits.

10.3 Cell Bus Routing Headers

T8207 device on the cell bus accepts all broadcast cells and certain multicast cells that it is configured to accept. routed as single address, may be data, control, or loopback cells. Figure 16. Cell Bus Routing Headers two do not match, the cell is discarded.

10.3.1 Control Cells

60 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8207

10.3.2 Data Cells

Data cells accepted from the cell bus are routed to the TX PHY FIFO. From the TX PHY FIFO, the cell is routed to the appropriate transmit queue using the information about the cell’s priority and the queue group to which it is des- tined. The priority of the cell is indicated by 2 bits obtained from the first 64 bits of the bus cell (cell bus routing header, tandem routing header, and ATM cell header). The position of these 2 bits in the cell are user programma- ble during configuration using the prior0_sel[5:0] and prior1_sel[5:0] bits of the routing information 3 register (address 0204h). The queue group to which the cell is destined is indicated by 4 bits obtained from the first 64 bits of the bus cell (cell bus routing header, tandem routing header, and ATM cell header). The position of these 4 bits in these headers are user programmable using the mphy1_sel[5:0] and mphy2_sel[5:0] bits of the routing informa- tion 1 register (address 0200h) and the mphy3_sel[5:0] and mphy0_sel[5:0] bits of the routing information 2 regis- ter (address 0202h). See Tables 90, 91, and 92 in Section 14.3, Extended Memory Registers. None of the priority or MPHY bits are required to be adjacent. For more information on queue groups, see Section 11.4, Queuing. If the T8207_sel bit (Table 59) is zero, the mphy3_sel[5:0] bits are not used.

10.3.3 Loopback Cells

A loopback cell may be sent to the cell bus for diagnostic purposes. Initially, the loopback cell is sent from one T8207 (device 1) to a second T8207 (device 2). The second T8207 (device 2) returns the cell to the first T8207 (device 1), or, if desired, the second T8207 (device 2) may send the cell on to one or more entirely different T8207 devices. Device 2 accepts the loopback cell and replaces the most significant 12 bits of the cell bus routing header with the routing_header bits in its loopback register (address 0118h). The 12 routing_header bits in the loopback register correspond to the upper 12 bits of a single destination control cell header, a multicast control cell header, or a broadcast control cell header. (See Figure 16.) To create a loopback path from device 1 to device 2, and back to device 1, coordinated control of device 1 and device 2 is needed. First, the microprocessor connected to device 2 sets up the loopback by writing the routing_header bits in the loopback register of device 2. The routing_header bits indicate a single destination con- trol cell with a unit address field for device 1. Second, the microprocessor connected to device 1 writes a loopback cell to the control cell transmit direct memory (addresses A0h to D7h) of device 1. (See Section 10.3.1, Control Cells of this document.) The cell bus routing header of this cell is the single destination loopback type, and the unit address section of the header contains the address of device 2. To send the loopback cell, a ‘1’ is then written to the cntl_cell_wr bit of the main configuration/control register (address 0110h). Care must be taken to ensure that the routing_header bits in a T8207 device are not changed until any previously setup loopback cell has been received and retransmitted. If these bits are changed prematurely, misrouting will occur.

10.3.4 Multicast Routing

The T8207 may be programmed to accept certain multicast data cells using the multicast memories at addresses E0h through FFh (or 0C00h through 0C1Eh) and 0C20h through 0DFEh. The net numbers of accepted multicast control cells are programmed in the memory space E0h through FFh (or 0C00h through 0C1Eh) and 0C20h through 0DFEh. These memory spaces hold 256 bits each. Each bit represents a multicast net number from 0 to 255. If the T8207_sel bit (Table 59) is cleared, the multicast memories at addresses 0D00h to 0DFEh are ignored. Note:To prevent potential multicast memory errors, these memory spaces should be cleared during the initializa- tion process. For ATM mode, if the T8207_sel bit is cleared, the net numbers of accepted multicast data cells are programmed in the multicast number memories, which are divided among eight PHY ports. If 16 ports are used in this mode, each memory space is shared between two ports, e.g., ports zero and one use the memory assigned to PHY 0, ports two and three use the memory assigned to PHY 1, and so on (see Section 9.2.2, Outgoing ATM Mode (Cells Sent by T8207)).

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10.3.4 Multicast Routing (continued)

For ATM mode, if the T8207_sel bit is set, the net numbers of accepted multicast data cells are programmed in the multicast number memories, which are divided among sixteen PHY ports. If 16 ports are used, each port has one memory space. If 32 ports are used, each memory space is shared between two ports, e.g., ports zero and one use the memory assigned to PHY 0, ports two and three use the memory assigned to PHY 1, and so on. The cell priority bits select the specific queue in the queue group to which the cell is routed. (See Section 11.4, Queuing.) Note that multicast control cells use the same multicast number memory as PHY 0 multicast data cells. See Table 122 in Section 14.3, Extended Memory Registers and Table 52 in Section 14.2, Direct Memory Access Registers, respectively. For PHY mode, multicast cells are only transmitted to queue group 0, and only the PHY port 0 and control cell mul- ticast direct memory at addresses E0h through FFh (or 0C00h through 0C1Eh) is used. The cell priority determines the specific queue in queue group 0 to which the cell is routed. (See Section 10.3.2, Data Cells.)

10.3.5 Broadcast Routing

Broadcast control cells are transmitted and received as described in Section 10.3.1, Control Cells. The broadcast control cell bus routing header has a broadcast control cell header type. For ATM mode, if the T8207_sel bit (Table 59) is cleared and 8 PHY ports or less are being used, the broadcast data cells are transmitted to all the ports. If 16 ports are used, the broadcast data cells are transmitted to only 8 of the 16 ports depending on the cell priority bits that select the specific queue. For ATM mode, if the T8207_sel bit (Table 59) is set, and 16 PHY ports or less are being used, the broadcast data cells are transmitted to all the ports. If 32 ports are used, the broadcast data cells are transmitted to only 16 of the 32 ports depending on the cell priority bits that select the specific queue. For PHY mode, if SDRAM is bypassed, broadcast data cells are only transmitted to queue 0. If the SDRAM is not bypassed, broadcast data cells are only transmitted to queue group 0, and only PHY port 0 is used (although the device will take the time to try to broadcast data cells to all the ports, cells will not be stored in queue groups other than 0).

10.4 Cell Bus Arbitration

One of the T8207 devices sharing the cell bus must be configured as bus arbiter by clearing the cb_arb_sel bit in the cell bus configuration/status register (address 0130h) or by pulling the arb_en* lead low. Using an arbitration algorithm, the arbiter decides the next device to transmit on the cell bus and issues the grant signals at the end of the cell bus frame. The arbiter also generates the active-low frame synchronization signal that occurs every 16 clock cycles in 16-user mode and every 32 clock cycles in 32-user mode. To grant transmission requests, the arbiter must analyze requests received during the request section of the cur- rent frame for 16-user mode or during two request cycles for 32-user mode. The arbitration algorithm used is round-robin and based on the priority of the request and the last request granted. The arbiter circuitry in all T8207 devices on the cell bus will synchronize to the active arbiter on the cell bus. So, when an inactive device becomes the arbiter, it will begin sending frame synchronization signals that coincide to the clock cycle that the original arbiter would have sent its next frame synchronization signal. This prevents the new arbiter from misinterpreting random signals on its first request cycle as valid requests.

10.5 Cell Bus Monitoring

32-user mode. This bit is also set when the cell bus write clock is inactive for 32 mclk cycles. main configuration 3 register (address 0116h).

10.6 GTL+ Logic

nation resistors are typically placed at the ends of the bus of the backplane. TT and is created using the voltage divider shown in Figure 17B. pling capacitor on the cb_vref input. Figure 17. GTL+ External Circuitry

Agere Systems Inc. 63 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8207

10.7 Cell Bus Write and Read Clocks

The read and write clocks (cb_wc* and cb_rc* pins) are supplied from an external source. The write clock should be delayed 1.5 ns to 4 ns relative to the read clock to ensure sufficient data hold time. The position of the clock source relative to the cell bus devices on the card or on connecting cards determines the actual delay that should be used. When the clock source is centrally located among the cell bus devices, a longer delay may be used. When the clock source is at either end of the cell bus devices, a shorter delay is needed. Also, a higher clock fre- quency requires a shorter delay.

11 SDRAM Interface

tion 1 register (address 0100h). to “101” to maximize buffering.

11.1 Memory Configuration

or 64 Mbit devices. Table 17 below outlines the various memory configurations supported. Table 17. Supported Memory Configurations

11.2 Powerup Sequence

timing between commands is met, until the powerup process has been completed. may be configured for either addressing mode.

11 SDRAM Interface (continued)

11.3 SDRAM Interface Timing

■ RAS inactive to CAS active (ras2cas)—its value may be set from two to four SDRAM clock cycles. may be set to 3, 7, or 15 SDRAM clock cycles. a cell using the default values for the parameters. Figure 18. SDRAM Timing Parameters VALUES ARE IN BOLD FOR ras2cas, cas2pre, pre2cmd, AND ref2cmd.

66 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8207

11.4 Queuing

Queuing is different for a T8207 device with its T8207_sel (Table 59) bit set than a T8207 device with its T8207_sel bit cleared. For a device configured in ATM mode with its T8207_sel bit set, up to 16 groups of queues with four priorities per group may be configured in the SDRAM for a total of 64 queues. Therefore, the four port group address bits point to one of 16 queue groups, and the two priority bits point to one of four queues in the group. (For a description of the port group address and priority bits, see Section 10.3.2, Data Cells.) Priority bits with a value of zero represent the highest priority, and those with a value of three, the lowest priority. If the ATM is configured to support eight or less PHY ports, each port is mapped to one queue group using the port_rte[31:0] bits in the TX PHY FIFO routing 0 and 1 registers (addresses 017Ch and 017Eh). For example, for a configuration of eight PHY ports, which includes ports 0, 2, 4, 6, 8, 10, 12, and 14, PHY port 0 is assigned queue group zero or queues zero, one, two, and three. Likewise, PHY port 2 is assigned group one or queues four, five, six, and seven, and so on. An ATM configured to support 16 PHY ports is a special case. When the T8207_sel bit is set and the ATM is con- figured to support 16 PHY ports, each port (0— 15) is assigned to its associated queue group as illustrated in Table 18, regardless of the value of the port_rte[63:0] bits. In this case, port 0 is assigned to queue group 0, port 1 to queue group 1, and so on. For an ATM configured to support 32 PHY ports, each queue group is shared between two ports as specified in Section 9.2.2, Outgoing ATM Mode (Cells Sent by T8207), and the four queues may be split in any way between the two ports using the port_rte[63:0] bits. Table 19 illustrates the relationship between the queue organization and the port group address/priority bits for a device configured to support 32 PHY ports and whose port_rte[63:0] bits are programmed to the normal 32-port mode as described in Section 9.2.2, Outgoing ATM Mode (Cells Sent by T8207). See the TX PHY FIFO routing 3, 2, 0, and 1 registers at addresses 0178h, 017Ah, 017Ch, and 017Eh. When the T8207_sel bit is cleared, 32 PHY ports are not supported. In this mode, eight or less PHY ports are each mapped to one queue group using the port_rte[31:0] bits in the TX PHY FIFO routing 0 and 1 registers. For 16 PHY ports, each queue group is shared between two ports, and the four queues may be split in any way between the two ports using the port_rte[31:0] bits. Table 20 illustrates the relationship between the queue organization and the port address/priority bits for a device configured to support 16 PHY ports and whose port_rte[31:0] bits are pro- grammed to the normal 16-port mode as described in Section 9.2.2, Outgoing ATM Mode (Cells Sent by T8207). See the TX PHY FIFO routing 0 and 1 registers at addresses 017Ch and 017Eh.

Table 18. Queue Organization and Port Group Address/Priority Bits for 16 Ports with T8207_sel = 1

Table 19. Queue Organization and Port Group Address/Priority Bits for 32 Ports

000 H i g h “0000” “00”

002 L o w “0000” “10”

101 H i g h “0000” “01”

103 L o w “0000” “11”

214 H i g h “0001” “00”

216 L o w “0001” “10”

315 H i g h “0001” “01”

317 L o w “0001” “11”

428 H i g h “0010” “00”

529 H i g h “0010” “01”

Table 19. Queue Organization and Port Group Address/Priority Bits for 32 Ports (continued)

Table 20. Queue Organization and Port Group Address/Priority Bits for 16 Ports with T8207_sel = 0

72 Agere Systems Inc. Advance Data Sheet September 2001ATM Interconnect CelXpres T8207 Of the four priority queues, the highest-priority (priority zero), lowest-delay queue may be used for constant bit rate (CBR) traffic. The other three queues, in descending order of priority, may be used for variable bit rate (VBR), avail- able bit rate (ABR), and unspecified bit rate (UBR) traffic, respectively. Generally, as the priority becomes lower, the queues become larger because lower-priority cells are likely to accumulate while higher-priority cells are transmit- ted. The size and location of each queue is programmable using the base_addressX[24:6] and end_addrX[24:6] bits in the Queue X Definition Structure shown in Table 119. Using these base and end address registers, the size of each queue may be programmed to a minimum of four cells and up to a maximum of 512K cells in one-cell increments. Each queue must be disabled during queue configuration by clearing the queueX_rd_en and queueX_wr_en bits in the queue X registers (addresses 0440h through 04BEh) (Table 118). Cells sent to write-disabled queues will be discarded. Cells sent to read-disabled queues will be written into the SDRAM but never transmitted to the TX UTOPIA port. Read-disabled queues may be used, as large external memory, to store cells bound for the microprocessor. The microprocessor may use as many queues as required for different type cells. Because the microprocessor reads only 2 bytes from the SDRAM per access, the cas2pre value (see Section 11.3, SDRAM Interface Timing) may need to be larger than that required for the transferring of cells only. Therefore, to maximize the bandwidth of the SDRAM for cell bus to UTOPIA traffic, restrict microproces- sor access of the SDRAM to the initialization function (e.g., downloading microcode over the cell bus). When the microprocessor increments the read pointer to read the SDRAM, it must first write the three least signifi- cant bits (rd_pntX[8:6]) of the read pointer for the appropriate queue followed by the 16 most significant bits (rd_pntX[24:9]). This order must be followed for proper operation. All queues used for microprocessor cell recep- tion must be at least 32 cells long. (See the Queue X Definition Structure, Table 119, for more information on these bits.)

11.5 SDRAM Refresh

The T8207 SDRAM interface performs CAS before RAS (CBR) refresh commands at a rate programmed in the ref_cnt bits of the refresh register (address 0410h). The value in the refresh register represents refresh cycles in SDRAM clock cycles. One refresh command is executed every ref_cnt clock cycles, on average, when the SDRAM is idle. In addition, the value programmed in the refresh lateness register (address 0412h) represents the maximum time, in programmed refresh cycles, between actual refresh cycles. If this limit is exceeded, the ref_late bit in the SDRAM interrupt status register (address 0402h) will be set, and if the ref_late interrupt is enabled, an interrupt will be generated. The ref_late indication is provided for diagnostic purposes and does not necessarily indicate a fatal error. Bit errors in the actual cell are reported in the crc8_err_even and crc8_err_odd bits of the SDRAM interrupt status register.

Agere Systems Inc. 73 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8207

11.6 SDRAM Throughput

The SDRAM clock frequency must be fast enough for cell transfers, to and from the SDRAM, to occur without over- runs to the TX PHY FIFO or underruns to the TX UTOPIA cell buffer. Using the default values for ras2cas, cas2pre, and pre2cmd, thirty-five clock cycles are required to transfer one cell (56 bytes) into or out of the SDRAM. The assumed efficiency rate is 90%. Therefore, the number of cells per second that can be read or written into the SDRAM is calculated using the following equation: Cell Rate = (f mclk/35 cycles per cell x 90%) where fmclk is the frequency of the SDRAM clock. The maximum UTOPIA and cell bus bandwidths must be calculated to ensure that the SDRAM clock frequency supports these bandwidths. For example, assume that the total bandwidth on the UTOPIA bus is 64 Mbits/s and that the cell bus clock rate is 33 MHz. The maximum number of cells per second that the cell bus can send is: = 2.06 Mcells per second. On the UTOPIA port, the total number of cells that can be sent is: = 151 Kcells per second. Thus, the total number of cells per second from the cell bus and to the UTOPIA bus is 2.21 Mcells per second. For the cell rate equation above, the required SDRAM clock frequency is: * 35 cycles per cell = 86 MHz. This is a worst-case example and assumes that all potential cells on the cell bus are going to this one device. The SDRAM frequency calculation produces a lower frequency if the actual system characteristics are considered and if the distribution of cells is controlled.

33 MHz

64 Mbits/s

2.21 Mcells per second

12 Traffic Management

12.1 Cell Loss Priority (CLP)

filled beyond the programmed limit and this feature is enabled. Table 119. The feature is enabled when the queueX_clp_en bit in the queue X registers (address 0440h through reading the value of the read and write pointers for the specific queue.

12.2 Forward Explicit Congestion Notification (FECN)

and write pointers for the specific queue.

12.3 Partial Packet Discard (PPD)

header, and ATM cell header) and are created at connection establishment. channels for partial packet discard. Each bit in the memory represents one of 8192 potential AAL5 virtual channels. the last cell is transmitted. the PPD memory write register at address 0418h.

13 JTAG Test Access Port

high, the JTAG interface is enabled. If the JTAG port is not used, jtag_trst should be tied low. guage may be found on the Agere website.

13.1 Instruction Register

The instruction register (IR) is 3 bits in length. The instructions are defined in Table 21. Table 21. Instruction Register EXTEST “000” Places the boundary-scan register in extest mode. SAMPLE “001” Places the boundary-scan register in sample mode. Reserved “010”—“110” Reserved. BYPASS “111” Places the bypass register in the scan chain.

13 JTAG Test Access Port (continued)

13.2 Boundary-Scan Register

scan chain beginning with the least significant bit. Table 22. Boundary-Scan Register Descriptions 5 ENARB_OE — ENARB is an input when ENARB_OE = 0. 6 ENARB arb_enb* Bidirectional. 7C K O E _ I N — CKO is high impedance when CKOE_IN = 0. 8 CKO cko 3-statable output. 10 GPIO_OE(0) — GPIO(0) is an input when GPIO_OE(0) = 0. 11 GPIO(0) gpio[0] Bidirectional. 12 GPIO_OE(1) — GPIO(1) is an input when GPIO_OE(1) = 0. 13 GPIO(1) gpio[1] Bidirectional. 14 GPIO_OE(2) — GPIO(2) is an input when GPIO_OE(2) = 0. 15 GPIO(2) gpio[2] Bidirectional. 16 GPIO_OE(3) — GPIO(3) is an input when GPIO_OE(3) = 0. 17 GPIO(3) gpio[3] Bidirectional. 18 GPIO_OE(4) — GPIO(4) is an input when GPIO_OE(4) = 0. 19 GPIO(4) gpio[4] Bidirectional. 20 GPIO_OE(5) — GPIO(5) is an input when GPIO_OE(5) = 0. 21 GPIO(5) gpio[5] Bidirectional. 22 GPIO_OE(6) — GPIO(6) is an input when GPIO_OE(6) = 0. 23 GPIO(6) gpio[6] Bidirectional. 24 GPIO_OE(7) — GPIO(7) is an input when GPIO_OE(7) = 0. 25 GPIO(7) gpio[7] Bidirectional. 28 CB_ACK_N cb_ack* Bidirectional. 61 CB_F_N cb_fs* Bidirectional. 62 CB_DISBL cb_disable* Input. 73 D_OE — D(0:7) are inputs when D_OE = 0.

Table 22. Boundary-Scan Register Descriptions (continued)

84 RDY_DTACK_N_OE — RDYDTACK is high impedance when

85 RDYDTACK rdy_dtack* 3-statable output.

88 DEVHIZ_N_HIGH_DRIVE — INT_IRQ, SD_A(11:0), SD_BS(1:0), SD_CAS_N,

when DEVHIZ_N_HIGH_DRIVE = 0. 89 INT_IRQ int_irq* 3-statable output. 104 SD_CAS_N sd_cas* 3-statable output. 105 SD_CLK_OE — SD_CLK is an input when SD_CLK_OE = 0. 106 SD_CLK sd_clk Bidirectional. 107 SD_D_OE — SD_D(15:0) are inputs when SD_D_OE = 0. 124 SD_RAS_N sd_ras* 3-statable output. 125 SD_WE_N sd_we* 3-statable output.

126 TR_CONT_OE — TR_OE_N, TR_WE_N, TR_A(17:0), and

127 TR_OE_N tr_oe* 3-statable output. 128 TR_WE_N tr_we* 3-statable output. 149 TR_D_OE — TR_D(7:0) are inputs when TR_D_OE = 0.

158 U_RXADDR_OE — U_RXADD(4:0) are inputs when U_RXADDR_OE

159— 163 U_RXADD(0:4) u_rxaddr[0:4] Bidirectional.

164 U_RXCLAV0_OE — U_RXCLV0 is an input when U_RXCLAV0_OE =

165 U_RXCLV0 u_rxclav[0] Bidirectional. 166— 168 U_RXCLV1 —U_RXCLV3 u_rxclav[1:3] Input. 169 U_RXCLK_OE — U_RXCLK is an input when U_RXCLK_OE = 0. 170 U_RXCLK T1 Bidirectional.

179 U_RXENB0_OE — U_RXENB(0) is an input when U_RXENB0_OE =

180 U_RXENB(0) u_rxenb*[0] Bidirectional.

181 U_RXENB_OE — U_RXENB(3:1) are inputs when U_RXENB_OE =

u_rxenb*[1:3] Bidirectional. 185 U_RXPRTY u_rxprty Input. 188 U_SHR_O_OE — U_SHR_O is an input when U_SHR_O_OE = 0. 189 U_SHR_O u_shr_o Bidirectional.

190 U_TXADDR_OE — U_TXADD(4:0) are inputs when U_TXADDR_OE

191— 195 U_TXADD(0:4) u_txaddr[0:4] Bidirectional.

196 U_TXCLAV0_OE — U_TXCLV0 is an input when U_TXCLAV0_OE =

197 U_TXCLV0 u_txclav[0] Bidirectional. 198— 200 U_TXCLV1 – U_TXCLV3 u_txclav[1:3] Input. 201 U_TXCLK_OE — U_TXCLK is an input when U_TXCLK_OE = 0. 202 U_TXCLK u_txclk Bidirectional.

203 U_TXDATA_OE — U_TXDAT(7:0) are high impedance when

204— 211 U_TXDAT(0:7) u_txdata[0:7] 3-statable output. 212 U_TXENB0_OE — U_TXENB0 is an input when U_TXENB0_OE = 0. 213 U_TXENB0 u_txenb*[0] Bidirectional.

214 U_TXENB_OE — U_TXENB1, U_TXENB2, and U_TXENB3 are

high impedance when U_TXENB_OE = 0. 215— 217 U_TXENB1 – U_TXENB3 u_txenb*[1:3] 3-statable output.

218 U_TXPRTY_OE — U_TXPRTY is an input when U_TXPRTY_OE =

219 U_TXPRTY u_txprty Bidirectional.

220 U_TXSOC_OE — U_TXSOC is high impedance when

221 U_TXSOC u_txsoc 3-statable output.

14 Registers

located in Section 14.3, Extended Memory Registers.

14.1 Register Types

Table 23. Register Map Read/Write (RW): These registers may be written or read. Read Only (RO): These registers may only be read. the ROL register is cleared. clock cycle and then return to zero.

14 Registers (continued)

Table 23. Register Map (continued)

14.2 Direct Memory Access Registers

Table 24. Identification 0 (IDNT0) (00h) Table 25. Identification 1 (IDNT1) (01h) Table 26. Identification 2 (IDNT2) (02h)

1. RN represents the current revision number of the device.

Device ID 0 7:0 RO 4Fh Device Identification 0. Device ID 1 7:0 RO 07h Device Identification 1. Device ID 2 7:0 RO RN 1 Revision Number.

Table 27. Direct Configuration/Control Register (DCCR) (28h) per read/write to the translation RAM. modified and clocks are not present. Active-low. lation is performed, this bit has no effect. address space, 30h to 37h, will be in big-endian format.

Table 28. Interrupt Service Request (ISREQ) (29h) Table 29. mclk PLL Configuration 0 (MPLLCF0) (2Ah) rupts will cause this bit to become set. cause this bit to become set. cause this bit to become set. need to be enabled for this bit to become set. does not need to be enabled for this bit to become set.

Table 30. mclk PLL Configuration 1 (MPLLCF1) (2Bh) Table 31. GTL+ Slew Rate Configuration (GTLSRCF) (2Eh) Table 32. GTL+ Control (GTLCNTRL) (2Fh) time is 0.9 ns and the maximum slew rate time is 3.8 ns. this condition, no cells can be received from the backplane. and cells are received from the backplane. the GTL+ transmitters on the cell bus pins are powered down. up and cells are transmitted to the backplane.

14.2.1 Little-Endian Format (big_end = 0) for Extended Memory Access Registers 30h—37h

Table 33. Extended Memory Address 1 (Little Endian) (EMA1_LE) (30h) Table 34. Extended Memory Address 2 (Little Endian) (EMA2_LE) (31h) Table 35. Extended Memory Address 3 (Little Endian) (EMA3_LE) (32h) Table 36. Extended Memory Address 4 (Little Endian) (EMA4_LE) (33h) Table 37. Extended Memory Access (Little Endian) (EMA_LE) (34h) high, both data bytes are written. cleared when the access is complete.

Table 38. Extended Memory Data Low (Little Endian) (EMDL_LE) (36h) Table 39. Extended Memory Data High (Little Endian) (EMDH_LE) (37h) available here after the extended read is complete. available here after the extended read is complete.

14.2.2 Big-Endian Format (big_end = 1) for Extended Memory Access Registers 30h—37h

Table 40. Extended Memory Address 4 (Big Endian) (EMA4_BE) (30h) Table 41. Extended Memory Address 3 (Big Endian) (EMA3_BE) (31h) Table 42. Extended Memory Address 2 (Big Endian) (EMA2_BE) (32h) Table 43. Extended Memory Address 1 (Big Endian) (EMA1_BE) (33h)

Table 44. Extended Memory Access (Big Endian) (EMA_BE) (34h) Table 45. Extended Memory Data High (Big Endian) (EMDH_BE) (36h) Table 46. Extended Memory Data Low (Big Endian) (EMDL_BE) (37h) high, both data bytes are written. cleared when the access is complete. available here after the extended read is complete. available here after the extended read is complete.

14.2.3 General-Purpose I/O Control Registers

Table 47. GPIO Output Enable (GPIO_OE) (39h) Table 48. GPIO Output Value (GPIO_OV) (3Bh) Table 49. GPIO Input Value (GPIO_IV) (3Dh) sponding output enable bit is high.

14.2.4 Control Cells

Table 50. Control Cell Receive Direct Memory (CCRXDM) (60h to 93h) The control cell receive memory may also be accessed from extended memory. See Table 120. Table 51. Control Cell Transmit Direct Memory (CCTXDM) (A0h to D7h) The control cell transmit memory may also be accessed from extended memory. See Table 121. shadow of the control cell receive extended memory. should be written to this direct memory space.

14.2.5 Multicast Memories

Table 52. PHY Port 0 and Control Cells Multicast Direct Memory (PP0MDM) (E0h to FFh) The PHY port 0 and control cells multicast memory may also be accessed from extended memory (see Table 122).

14.3 Extended Memory Registers

UTOPIA registers, and the SDRAM registers.

14.3.1 Main Registers

Table 53. Main C onfiguration 1 (MCF1) (0100h) R eserved 7:0 RO 00h R eserved. high im pedance when not active. outputs never go high impedance. SDRAM a nd will use only internal me m ory to buffer cell bus data. w hen the SDRAM is bypassed. only one external SRAM w ill be accessed using tr_cs*[0]. will be appended to the beginning of each cell. SRAM used for the look-up table RAM.

Table 54. Main Interrupt Status 1 (MIS1) (0102h) Note: Immediately following device setup, write FFFFh to this register to clear erroneously set bits. responding enable bit is set. responding enable bit is set. ated if the corresponding enable bit is set. responding enable bit is set. corresponding enable bit is set. not been granted within the time programmed in the cb_req_to bits. An interrupt is generated if the corresponding enable bit is set. generated if the corresponding enable bit is set. received and is translated and routed. Reserved 15:12 RO 0 Reserved.

Table 55. Main Interrupt Enable 1 (MIE1) (0104h) responding status bit is reset. is generated until this bit or the corresponding status bit is reset. rupt is generated until this bit or the corresponding status bit is reset. is generated until this bit or the corresponding status bit is reset. ated until this bit or the corresponding status bit is reset. generated until this bit or the corresponding status bit is reset. rupt is generated if this bit and the corresponding status bit are set. erated until this bit or the corresponding status bit is reset. erated until this bit or the corresponding status bit is reset. Reserved 15:12 RO 0 Reserved.

Table 56. TX UTOPIA Clock Configuration (TXUCCF) (010Ch) the u_txclk pin is configured as an input. Reserved 15:12 RO 0 Reserved.

Table 57. RX UTOPIA Clock Configuration (RXUCCF) (010Eh) the u_rxclk pin is configured as an input. Reserved 15:12 RO 0 Reserved.

Table 58. Main Configuration/Control (MCFCT) (0110h) Table 59. Main Configuration 2 (MCF2) (0112h) clock cycle and will clear to ‘0’ automatically. automatically cleared when the cell is transmitted to the cell bus. which cells with their CLP bit set to one will be discarded. grammed in the clp_fill_limit bits is reached. the cell bus. If ‘0,’ cells are not accepted. u_rxenb*[3:1] become inputs.

Table 59. Main Configuration 2 (MCF2) (0112h) (continued) (Table 87) registers do not need to be programmed. when the RX UTOPIA is in PHY mode. UTOPIA FIFO is considered full. the RX UTOPIA FIFO is considered full. PHY ports 0, 1, 2, and 3, and so on. PHY ports 0, 1, 2, and 3, and so on. Reserved 14:11 RO 0 Reserved.

Table 60. UTOPIA Configuration (UCF) (0114h) Table 61. Main Configuration 3 (MCF3) (0116h) used when the T8207 is configured as a PHY. Reserved 15:13 RO 0 Reserved. grant time-out (cb_grnt_to) status bit is set. in all cells transmitted to the UTOPIA bus. Reserved 15:13 RO 0 Reserved.

Table 62. Loopback (LB) (0118h) Table 63. UTOPIA Configuration 3 (UCF3) (011Ah) Table 64. UTOPIA Configuration 2 (UCF2) (011Ch) Table 65. Extended LUT Configuration (ELUTCF) (011Eh) retransmitted on the cell bus. Reserved 15:2 RO 0 Reserved.

Table 66. Extended LUT Control (ELUTCN) (0120h)

Table 67. Cell Bus Configuration/Status (CBCFS) (0130h) Table 68. Main Interrupt Status 2 (MIS2) (0132h) unit_addr* 4:0 RO ua*[4:0] Unit Address. These bits indicate the values at the ua*[4:0] inputs. cb_arb_sel* 5 RW 1 Cell Bus Arbiter Select. If this bit is ‘0,’ cell bus arbiter is selected. the cell bus. If ‘1,’ 16-user mode is selected. back FIFO have the lowest priority. advised not to set this bit during data flow. Reserved 15:10 RO 0 Reserved. generated if the corresponding enable bit is set. if the corresponding enable bit is set. rupt is generated if the corresponding enable bit is set. the corresponding enable bit is set. Reserved 15:7 RO 0 Reserved.

Table 69. Main Interrupt Enable 2 (MIE2) (0134h) sponding status bit is reset. Reserved 1 RW 0 Reserved. Program this bit to zero. sponding status bit is reset. sponding status bit is reset. cell_clp1_dis_ie 4 RW 0 Cell with CLP Set to One Discarded Interrupt Enable. the corresponding status bit is reset. sponding status bit is reset. corresponding status bit is reset. Reserved 15:7 RO 0 Reserved.

Table 70. Misrouted LUT 1 (MLUT1) (0142h) Table 71. Misrouted LUT 2 (MLUT2) (0144h) Table 72. Misrouted Cell Header High (MCHH) (0146h) Table 73. Misrouted Cell Header Low (MCHL) (0148h) pulse for one clock cycle and will clear to ‘0’ automatically. Reserved 15:8 RO 0 Reserved. the incoming cell header are not all zero. the incoming cell header are not all zero.

14.3.2 UTOPIA Registers

Table 74. HEC Interrupt Status 1 (HIS1) (0302h) Table 75. HEC Interrupt Enable 1 (HIE1) (0304h) Table 76. HEC Interrupt Status (HIS) (0306h) Table 77. HEC Interrupt Enable (HIE) (0308h) Table 78. LUT Interrupt Service Request (LUTISR) (030Eh)

16 PHY ports where the most significant bit is port 31 and the

generated until this bit or the corresponding status bit is reset.

16 PHY ports where the most significant bit is port 15 and the

generated until this bit or the corresponding status bit is reset. has interrupt status bits that need servicing.

Table 79. LUT X Configuration/Status (LUTXCFS) (0320h to 033Eh) not counted as a received cell.

16 PHY ports, PHY ports 0 and 1 use LUT 0 memory

PHY ports 4 and 5 use LUT 2 memory space, and so on. if the corresponding enable bit is set. the corresponding enable bit is set. Reserved 15:13 RO 0 Reserved. status registers are shown below.

14.3.2.1 TX UTOPIA Configuration

Table 80. Master Queue 3 (MQ3) (0158h) Table 81. Master Queue 2 (MQ2) (015Ah) device is not used in shared UTOPIA mode. device is not used in shared UTOPIA mode.

Table 82. Master Queue 0 (MQ0) (015Ch) Table 83. Master Queue 1 (MQ1) (015Eh) associated bit is ‘1,’ it indicates that the queue is enabled. device is not used in shared UTOPIA mode. Note: Shared UTOPIA mode supports up to 32 queues only. associated bit is ‘1,’ it indicates that the queue is enabled. device is not used in shared UTOPIA mode. Note: Shared UTOPIA mode supports up to 32 queues only.

Table 84. Slave Queue 0 (SQ0) (016Ch) Table 85. Slave Queue 1 (SQ1) (016Eh) Note: Shared UTOPIA mode supports up to 32 queues only. Note: Shared UTOPIA mode supports up to 32 queues only.

Table 86. TX PHY FIFO Routing 3 (TXPFR3) (0178h) nificant bit is queue 48, and the most significant bit is queue 63.

Table 87. TX PHY FIFO Routing 2 (TXPFR2) (017Ah) nificant bit is queue 32, and the most significant bit is queue 47. assigned queues 37 and 39, and so on.

Table 88. TX PHY FIFO Routing 0 (TXPFR0) (017Ch) 64 queues are divided into sixteen groups of four queues each. 22, PHY port 11 is assigned queues 21 and 23, and so on. assigned queues 21 and 23, and so on.

Table 89. TX PHY FIFO Routing 1 (TXPFR1) (017Eh)

1. These 64 queues are divided into sixteen groups of four queues

Table 90. Routing Information 1 (RI1) (0200h) mphy1_sel[5:0] 5:0 RW X Multi-PHY 1 Select [5:0]. as this port group address bit. mphy2_sel[5:0] 11:6 RW X Multi-PHY 2 Select [5:0]. as this port group address bit. Multi-PHY 1 and 2 Select [5:0]. pointer is always ‘0’ and is not extracted from the received cell. Reserved 15:12 RO 0 Reserved.

Table 91. Routing Information 2 (RI2) (0202h) mphy3_sel[5:0] 5:0 RW X Multi-PHY 3 Select [5:0]. mphy0_sel[5:0] 11:6 RW X Multi-PHY 0 Select [5:0]. as this port group address bit. Multi-PHY 0 and 3 Select [5:0]. pointer is always ‘0’ and is not extracted from the received cell. Reserved 15:12 RO 0 Reserved.

Table 92. Routing Information 3 (RI3) (0204h) prior0_sel[5:0] 5:0 RW X Priority 0 Select. prior1_sel[5:0] 11:6 RW X Priority 1 Select. Reserved 15:12 RO 0 Reserved.

Table 93. PPD Information 1 (PPDI1) (0206h) dem routing header is used as this offset bit. ‘0’ and is not extracted from the received cell. received cell is one, the partial packet discard feature is enabled. Reserved 15:12 RO 0 Reserved.

Table 94. PPD Information 2 (PPDI2) (0208h) ppd_pnt10_sel[5:0] 5:0 RW X PPD Pointer 10 Select. header is used as this offset bit. ppd_pnt11_sel[5:0] 11:6 RW X PPD Pointer 11 Select. header is used as this offset bit. PPD Pointer 10 and 11 Select. not extracted from the received cell. Reserved 15:12 RO 0 Reserved.

Table 95. PPD Information 3 (PPDI3) (020Ah) ppd_pnt8_sel[5:0] 5:0 RW X PPD Pointer 8 Select. header is used as this offset bit. ppd_pnt9_sel[5:0] 11:6 RW X PPD Pointer 9 Select. header is used as this offset bit. not extracted from the received cell. Reserved 15:12 RO 0 Reserved.

Table 96. PPD Information 4 (PPDI4) (020Ch) ppd_pnt6_sel[5:0] 5:0 RW X PPD Pointer 6 Select. ppd_pnt7_sel[5:0] 11:6 RW X PPD Pointer 7 Select. ‘0’ and is not extracted from the received cell. Reserved 15:12 RO 0 Reserved.

Table 97. PPD Information 5 (PPDI5) (020Eh) ppd_pnt4_sel[5:0] 5:0 RW X PPD Pointer 4 Select. ppd_pnt5_sel[5:0] 11:6 RW X PPD Pointer 5 Select. ‘0’ and is not extracted from the received cell. Reserved 15:12 RO 0 Reserved.

Table 98. PPD Information 6 (PPDI6) (0210h) ppd_pnt2_sel[5:0] 5:0 RW X PPD Pointer 2 Select. header is used as this offset bit. ppd_pnt3_sel[5:0] 11:6 RW X PPD Pointer 3 Select. header is used as this offset bit. not extracted from the received cell. Reserved 15:12 RO 0 Reserved.

Table 99. PPD Information 7 (PPDI7) (0212h) Table 100. PPD Memory Write (PPDMW) (0418h) ppd_pnt0_sel[5:0] 5:0 RW X PPD Pointer 0 Select. ppd_pnt1_sel[5:0] 11:6 RW X PPD Pointer 1 Select. always ‘0’ and is not extracted from the received cell. Reserved 15:12 RO 0 Reserved. memory. This address will be used when a write is performed. to the least significant bit of word1FF.

14.3.2.2 TX UTOPIA Monitoring

Table 101. PHY Port X Transmit Count Structure (PPXTXCNT) (0600h to 067Ch) ports. The base addresses of the 32 data structures and their associated PHY port number are shown below.

14.3.2.3 RX UTOPIA Monitoring

Table 102. PHY Port X Receive Count Structure (PPXRXCNT) (0700h to 07F8h) port X. Both valid and misrouted cells are counted. their VPI and/or VCI are out of range. port X. Both valid and misrouted cells are counted. their VPI and/or VCI are out of range. ports. The base addresses of the 32 data structures are shown below.

Table 103. LUT X Configuration 1 Structure (LUTXCF1) (0704h to 077Ch) port has its own look-up table memory space.

16 PHY ports are used, even and odd PHY ports

use LUT 2 memory space, and so on. responding lutX_vpi_mask bit equal zero. up table. If this bit is ‘0,’ the port is identified as NNI. table configurations. The base addresses of the 16 data structures are shown below.

14.3.3 SDRAM Registers

Table 104. SDRAM Control (SCT) (0400h) Table 105. SDRAM Interrupt Status (SIS) (0402h) Table 106. SDRAM Interrupt Enable (SIE) (0404h) active. If ‘0,’ the SDRAM is in the idle state. Reserved 14:2 RO 0 Reserved. detected on the even byte (sd_d[15:8]) of the SDRAM data bus. An interrupt is generated if the corresponding enable bit is set. interrupt is generated if the corresponding enable bit is set. Reserved 15:3 RO 0 Reserved. erated until this bit or the corresponding status bit is reset. is generated if this bit and the corresponding status bit are set. is generated if this bit and the corresponding status bit are set. Reserved 15:3 RO 0 Reserved.

Table 107. SDRAM Configuration (SCF) (0408h) SDRAM based on the clock frequency and speed grade of the device. charge command going active. command going inactive to next command going active. other command is 15 clock cycles. Reserved 15:11 RO 0 Reserved.

Table 108. Refresh (RFRSH) (0410h) Table 109. Refresh Lateness (RFRSHL) (0412h) Table 110. Idle State 1 (IS1) (0420h) Table 111. Idle State 2 (IS2) (0422h) reached, the ref_late status bit will be set. sd_cas* pin while the SDRAM is idle (sdram_en = ‘0’). sd_ras* pin while the SDRAM is idle (sdram_en = ‘0’). placed on the sd_we* pin while the SDRAM is idle (sdram_en = ‘0’). Reserved 15:5 RO 0 Reserved. the sd_a[11:0] pins while the SDRAM is idle (sdram_en = ‘0’). Reserved 15:12 RO 0 Reserved.

Table 112. Manual Access State 1 (MAS1) (0424h) Table 113. Manual Access State 2 (MAS2) (0426h) Reserved 15:5 RO 0 Reserved. Reserved 15:12 RO 0 Reserved.

Table 114. SDRAM Interrupt Service Request 4 (SISR4) (0438h) Table 115. SDRAM Interrupt Service Request 3 (SISR3) (043Ah) Table 116. SDRAM Interrupt Service Request 1 (SISR1) (043Ch) Table 117. SDRAM Interrupt Service Request 2 (SISR2) (043Eh) bits that need servicing (see Table 118). bits that need servicing (see Table 118). bits that need servicing (see Table 118). that need servicing (see Table 118).

Table 118. Queue X (QX) (0440h to 04BEh) congestion notification (FECN) feature is enabled. generated if the corresponding enable bit is set. ated if the corresponding enable bit is set. queueX_ovrn 10 ROL 0 Queue X Overrun. This bit is set when the queue overruns. interrupt is generated if the corresponding enable bit is set. sponding status bit is reset. sponding status bit is reset.

Table 118. Queue X (QX) (0440h to 04BEh) (continued) Note: When the T8207_sel bit = 0, queues 32—63 are disabled (default). corresponding status bit is reset.

14.3.3.1 SDRAM Control Memory

Table 119. Queue X Definition Structure (QXDEF) (2000h to 27E0h) 16 bits of the queue’s end address offset in increments of one cell. difference. The minimum size of any queue is four cells. the base_addr from the end_addr and adding one to the difference. The minimum size of any queue is four cells. the base_addrX[24:9] before the queue is enabled. base_addrX[8:6] before the queue is enabled. the base_addrX[24:9] before the queue is enabled. base_addrX[8:6] before the queue is enabled.

Table 119. Queue X Definition Structure (QXDEF) (2000h to 27E0h) (continued)

14.3.4 Various Internal Memories

14.3.4.1 Control Cell Memories

Table 120. Control Cell Receive Extended Memory (CCRXEM) (0800h to 0832h) The control cell receive memory may also be accessed from direct memory. See Table 50. Table 121. Control Cell Transmit Extended Memory (CCTXEM) (0900h to 0936h) The control cell transmit memory may also be accessed from direct memory. See Table 51.

14.3.4.2 Multicast Number Memories

Table 122. PHY Port 0 and Control Cells Multicast Extended Memory (PP0MEM) (0C00h to 0C1Eh) The PHY port 0 and control cells multicast memory may also be accessed from direct memory (see Table 52). nificant bit is multicast net number 0.

Table 123. PHY Port X Multicast Memory (PPXMM) (0C20h to 0DE0h) Note:When the T8207_sel bit = ‘0’ multicast memory at address 0D00h—0 DECh are ignored. ports. The base addresses of the 15 multicast memory locations are shown below.

14.3.4.3 PPD State Memory

Table 124. PPD Memory (PPDM) (1000h to 13FEh) cant bit of word1FF corresponds to AAL5 virtual channel 8191.

14.3.5 External Memories

14.3.5.1 Look-Up Translation Memory

Table 125. Translation RAM Memory (TRAM) (100000h to 17FFFEh)

14.3.5.2 SDRAM Buffer Memory

Table 126. SDRAM (SDRAM) (2000000h to 3FFFFFEh) word0 00h RW X This memory space is used to access the translation RAM memory. word0 00h RW X This memory space is used to access the SDRAM memory.

periods can adversely affect device reliability. Table 127. Maximum Rating Parameters and Values

1. Except for 5 V tolerant buffers where VIHmax = 5.5 V + 0.3 V.
2. Maximum power dissipation may be determined from the following equation: PD = (125 °C – TA)/22.5 °C/W.

16 Recommended Operating Conditions

Table 128. Recommended Operating Conditions

17 Handling Precautions

used for comparison. The HBM ESD threshold presented here was obtained by using these circuit parameters. Table 129. HBM ESD Threshold

18.1 Crystal Information

crystal specification requirements shown below. Table 130. Crystal Specifications be 5 MHz to 50 MHz. The external clock must meet the requirements shown below. Table 131. External Clock Requirements PLL Configuration, for more information on these clocks. Figure 19. Crystal Figure 20. Negative Resistance Plot

The following conditions apply except where noted: TA = –40 °C to +85 °C, VDD = 3.3 V ± 10%, 15 pF each output. Table 132. dc Electrical Characteristics 20 MHz, cell bus clock = 30 MHz, nominal slew rate (register 2Eh).

0.7 VDD

19 Timing Requirements

period of their respective clocks in ns when used in the following tables. Table 133. Input Clocks Table 134. Output Clocks

19 Timing Requirements (continued)

19.1 Microprocessor Interface Timing

For access time information, see Section 6.3.2, CelXpres T8207 Access Performance.

1. write_access_active is the logical OR function of sel* and wr*_ds*.

Note: sel* and wr*_ds* must not have coinciding edges in opposite directions to prevent glitches on the write_access_active signal. Figure 21. Nonmultiplexed Intel Mode Write Access Timing

1. read_access_active is the logical OR function of sel* and rd*_wr*.

Note: sel* and rd*_wr* must not have coinciding edges in opposite directions to prevent glitches on the read_access_active signals. Figure 22. Nonmultiplexed Intel Mode Read Access Timing

Table 135. Nonmultiplexed Intel Mode Write Access Timing

1. See access times in Table 10.

Note: The term pclkp in the table represents the period of pclk in ns. Table 136. Nonmultiplexed Intel Mode Read Access Timing

1. See access times in Table 10.

Note: The term pclkp in the table represents the period of pclk in ns.

1. write_access_active is the logical OR function of sel*, wr*_ds*, and rd*_wr*.

sel* and wr*_ds* must not have coinciding edges in opposite directions to prevent glitches on the write_access_active signal. rd*_wr* must be stable any time both sel* and wr*_ds* are low to prevent glitches on the write_access_active signals. Figure 23. Motorola Mode Write Access Timing

1. read_access_active is the logical OR function of sel*, wr*_ds*, and rd*_wr*.

sel* and wr*_ds* must not have coinciding edges in opposite directions to prevent glitches on the read_access_active signal. rd*_wr* must be stable any time both sel* and wr*_ds* are low to prevent glitches on the read_access_active signals. Figure 24. Motorola Mode Read Access Timing

Table 137. Motorola Mode Write Access Timing

1. See access times in Table 10.

Note: The term pclkp in the table represents the period of pclk in ns. Table 138. Motorola Mode Read Access Timing

1. See access times in Table 10.

Note: The term pclkp in the table represents the period of pclk in ns.

1. write_access_active is the logical OR function of sel* and wr*_ds*.

Note: sel* and wr*_ds* must not have coinciding edges in opposite directions to prevent glitches on the write_access_active signal. Figure 25. Multiplexed Intel Mode Write Access Timing

1. read_access_active is the logical OR function of sel* and rd*_wr*.

Note: sel* and rd*_wr* must not have coinciding edges in opposite directions prevent glitches on the read_access_active signals. Figure 26. Multiplexed Intel Mode Read Access Timing

Table 139. Multiplexed Intel Mode Write Access Timing

1. See access times in Table 10.

Note: The term pclkp in the table represents the period of pclk in ns. Table 140. Multiplexed Intel Mode Read Access Timing

1. See access times in Table 10.

Note: The term pclkp in the table represents the period of pclk in ns.

19.2 UTOPIA Timing

Table 141. TX UTOPIA Timing (70 pF Load on Outputs) Table 142. RX UTOPIA Timing (70 pF Load on Outputs)

19.3 External LUT Memory Timing

Note: 30 pF load on outputs. Figure 27. External LUT Memory Read Timing (cyc_per_acc = 2 and cyc_per_acc = 3) Note: 30 pF load on outputs. Figure 28. External LUT Memory Write Timing (cyc_per_acc = 2 and cyc_per_acc = 3)

The term mclkp in Tables 143, 144, 145, and 146, represents the period of mclk in ns. Table 143. External LUT Memory Read Timing (cyc_per_acc = 2) Table 144. External LUT Memory Read Timing (cyc_per_acc = 3) Table 145. External LUT Memory Write Timing (cyc_per_acc = 2) Table 146. External LUT Memory Write Timing (cyc_per_acc = 3)

19.4 Cell Bus Timing

Figure 29. Cell Bus Timing Table 147. Cell Bus Timing

19.5 SDRAM Interface Timing

Note: 15 pF load on outputs. Figure 30. SDRAM Interface Timing Table 148. SDRAM Interface Timing

Agere Systems Inc. 157 Advance Data Sheet September 2001 ATM Interconnect CelXpres T8207

20 Outline Diagram

All dimensions shown are in millimeters. 5-4406.c SEATING PLANE SOLDER BALL0.60 ± 0.10 0.20 PWB MOLD COMPOUND 27.00 ± 0.20 27.00 ± 0.20 24.00 +0.70 –0.00 24.00 +0.70 –0.00A1 BALL IDENTIFIER ZONE A B C D E F G H J K L M Y N P R T U V W 123 45 678 9 1 0 18 20 CENTER ARRAY FOR THERMAL ENHANCEMENT 19 SPACES @ 1.27 = 24.13 A1 BALL CORNER

19 SPACES

@ 1.27 = 24.13 0.75 ± 0.15

September 2001ATM Interconnect CelXpres T8207 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. CelXpres is a trademark of Agere Systems Inc. Copyright © 2001 Agere Systems Inc. All Rights Reserved September 2001 DS01-252DLC (Replaces DS00-211DLC) For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045 Part Number Package Comcode T-8207---BAL-DB 272-pin PBGAM, Dry Pack Tray 108698077 T-8207---BAL-DT 272-pin PBGAM Dry-bagged, Tape & Reel 108699265 Motorola is a registered trademark of Motorola, Inc. Intel is a registered trademark of Intel Corporation. Transwitch and CellBus are registered trademarks of Transwitch Corp.