T8110L

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Ambassador ® T8110L H.100/H.110 Switch

1 Introduction

The T8110L is the newest addition to the Ambassa- dor series of TDM switching and backlane intercon- nect standard products. The T8110L can switch 4096 simultaneous time slots with 32 bidirectional local streams and 32 bidirectional H.100/H.110 streams. The T8110L has all the features of the T810X devices. Additionally, the T8110L has more robust clocking fallback abilities and is pin compatible with the T8110. (The full version of the T8110 has a PCI and minbridge interface.)

1.1 Features

! 4,096-connection unified switch ! Full H.100/H.110 support (32 data lines, all clock modes) ! 32 local I/O lines (2, 4, 8, or 16 Mbits/s) ! Microprocessor interface: Motorola® /Intel® modes ! Interrupt controller with external inputs ! Eight independent general-purpose I/O lines ! Eight independently programmed framing signals ! Four local clocks ! T1/E1 rate adaptation ! Two clock-fallback modes ! Stratum 4/4E and AT&T ® 62411 MTIE compliant ! Incorporates 38 H.100 and 34 H.110 termination resistors ! Subrate switching of 4 bits, 2 bits, or 1 bit ! Backward compatible to all T810x devices ! Pin compatible with T8110 ! JTAG/boundary-scan testing support ! BSDL files available ! Assists H.110 hot swap ! Single 3.3 V supply with 5 V tolerant inputs and TTL compatible outputs ! 272 PBGA package ! Evaluation boards available

2 Agere Systems Inc. Data Sheet February 2004Ambassador T8110L H.100/H.110 Switch

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Table of Contents (continued) Contents Page 4 Agere Systems Inc. Data Sheet February 2004Ambassador T8110L H.100/H.110 Switch

Table of Contents (continued) Contents Page Agere Systems Inc. 5 February 2004 Ambassador T8110L H.100/H.110 Switch Data Sheet

13.10 APLL V

2 Pin Description

2.1 Interface Signals

Table 1. Microprocessor Interface Signals WR# (R/W#) I 1 WRn(R/Wn) in. WB_SEL I 1 Word/byte select in. RDY (DTACK#) Out 1 RDY(DTACKn) out. IM_SEL I 1 Intel/Motorola select in. Table 2. H-Bus (H.100/H.110 Interface) Signals CT_D, CT_NETREF1, CT_NETREF2. CT_NETREF2, CT_C8_A, CT_C8_B, /CT_FRAME_A, /CT_FRAME_B. /CT_FRAME_A I/O 1 H.100/H.110 frame reference A. /CT_FRAME_B I/O 1 H.100/H.110 frame reference B. CT_NETREF1 I/O 1 H.100/H.110 network reference 1. CT_NETREF2 I/O 1 H.100/H.110 network reference 2. /C16+ I/O 1 H- MVIP ™ compatibility clock (16.384 MHz, differential). /C16– I/O 1 H- MVIP compatibility clock (16.384 MHz, differential). /C4 I/O 1 MVIP compatibility clock (4.096 MHz). C2 I/O 1 MVIP compatibility clock (2.048 MHz). SCLK I/O 1 SC-bus compatibility clock. /SCLKx2 I/O 1 SC-bus compatibility clock. /FR_COMP I/O 1 Compatibility frame reference. Table 3. L-Bus (Local) Interface Signals L_SC Out 4 Local bus clock outputs. FG I/O 8 Local frame groups.

2 Pin Description (continued)

2.1 Interface Signals (continued)

Table 4. Clock Circuit Interface Signals XTAL1_IN In 1 Crystal oscillator #1 input (16.384 MHz). XTAL1_OUT Out 1 Crystal oscillator #1 feedback. XTAL2_IN In 1 Crystal oscillator #2 input (6.176 MHz or 12.352 MHz). XTAL2_OUT Out 1 Crystal oscillator #2 feedback. LREF In 8 Local clock reference inputs. TCLK_OUT Out 1 Internal chip clock output. PRI_REF_OUT Out 1 Main divider reference out for CLAD/DJAT. PRI_REF_IN In 1 CLAD/DJAT reference in for APLL1. NR1_SEL_OUT Out 1 CT_NETREF1 selection out for CLAD/DJAT. NR1_DIV_IN In 1 CLAD/DJAT reference in for CT_NETREF1 divider. NR2_SEL_OUT Out 1 CT_NETREF2 selection out for CLAD/DJAT. NR2_DIV_IN In 1 CLAD/DJAT reference in for CT_NETREF2 divider. Table 5. GPIO Interface Signals GP0 I/O 1 GPIO bit 0 I/O A-master indicator out. GP1 I/O 1 GPIO bit 1 I/O B-master indicator out. Table 6. Miscellaneous Interface Signals SYSERR Out 1 System error indicator. CLKERR Out 1 Clocking error indicator. PEN In 1 Reserved. Must be left unconnected. TESTMODE In 1 Reserved. Must be left unconnected. Table 7. JTAG Signals

12 Agere Systems Inc. Data Sheet February 2004Ambassador T8110L H.100/H.110 Switch

2.2 T8110L Pinout Information

The T8110L package is a 272-pin PBGA ball grid array. Refer to the table below for ball assignment, buffer type, and pull-up/pull-down information. Note:The pull-up/down column in the following table is defined as follows: ! 20 kΩ down—20 kΩ pull-down resistor is always in-circuit. ! 50 kΩ up—50 kΩ pull-up resistor is always in-circuit. ! LPUE: 50 kΩ up—when LPUE = 1, a 50 kΩ pull-up resistor is in-circuit. ! Enabled: 50 kΩ up/20 kΩ Vpre—when H100_ENABLE = 1, a 50 kΩ pull-up resistor is in-circuit (see Figure 1 on page 20). When H110_ENABLE = 1, a 20 kΩ pull-down resistor from the VPRECHARGE input to this signal is in- circuit.

2.2 T8110L Pinout Information (continued)

Table 8. T8110L Pinouts

Table 8. T8110L Pinouts (continued)

D16 No connects must be left unconnected.

pins be tied to a common 20 kΩ pull-up resistor.

2.3 Special Buffer Requirements

2.3.1 H1x0 Bus Signal Internal Pull-Up/Pull-Down

CT_C8_B, /CT_FRAME_A, and /CT_FRAME_B signals. Note:The two H1x0 enables are active-high. Only one or the other should ever be asserted. Warning: Do not assert both at the same time. Please refer to Figure 1 for more detail. Figure 1. T8110L Pull-Up/Pull-Down Arrangement for H1x0 Pins

2.3.2 Local Bus Signal Internal Pull-Up

D[15:0], LD[31:0], LREF[7:0], PRI_REF_IN, NR1_DIV_IN, and NR2_DIV_IN.

3 Main Architectural Features

3.1 T8110L Architecture

T8110L and T8110 are pin compatible. Figure 2. T8110L Architecture Block Diagram

4 Microprocessor Interface

4.1 Intel/Motorola Protocol Selector

IM_SEL = 1 is the default, if left unconnected, and selects an Intel handshake protocol. IM_SEL = 0 selects a Motorola handshake protocol. Note:The IM_SEL signal must be static (either pulled high or pulled low).

4.2 Word/Byte Addressing Selector

WB_SEL = 1 is the default, if left unconnected, and selects 16-bit word aligned addressing. WB_SEL = 0 selects 8-bit byte aligned addressing. requirements as the address bus. along with WB_SEL to control a dword-to-word or dword-to-byte swap function back to the data bus. Table 9. Intel/Motorola Protocol Selector

4 Microprocessor Interface (continued)

4.3 Access Via the Microprocessor Bus

Table 10. T8110L Memory Mapping to Microprocessor Space

4.3 Access Via the Microprocessor Bus (continued)

4.3.1 Microprocessor Interface Register Map

The T8110L registers map into the microprocessor bus space as follows. Table 11. Microprocessor Interface Register Map

4.3.1 Microprocessor Interface Register Map (continued)

Table 11. Microprocessor Interface Register Map (continued)

Figure 3. Microprocessor Access Timing, Intel Protocol

Figure 4. Microprocessor Access Timing, Motorola Protocol

4.3.2 Register Space Access

4.3.3 Connection Memory Space Access

timing for Figure 3 and Figure 4 is shown below. Table 12. Register Space Access Timing Table 13. Connection Memory Space Access Timing

4.3.4 Data Memory Space Access

switching configuration. Data memory access timing for Figure 3 and Figure 4 is shown below. Table 14. Data Memory Space Access Timing

5 Operating Control and Status

5.1 Control Registers

clock fallback, and clock watchdog configuration.

5.1.1 Reset Registers

reset register trigger the corresponding action, and the set bit(s) are automatically cleared. power-on reset cell test input is controlled via diagnostic register; see Section 11. Soft resets are maskable via reset select register, SRBEB, and selectable via soft reset register, SRESR. ! Soft reset 1: Initialize all T8110L registers (excluding reset select register) and connection valid flags. ! Soft reset 2: Initialize all T8110L registers (excluding reset select register). ! Soft reset 3: Reset all interrupt pending registers and the interrupt in-service register. ! Soft reset 4: Reset the interrupt in-service register only. Table 15. Control Register Map

5 Operating Control and Status (continued)

5.1 Control Registers (continued)

5.1.2 Master Output Enable Register

CLKERR, SYSERR, PRI_REF_OUT, NR1_SEL_OUT, and NR2_SEL_OUT. Table 16. Reset Registers Reset all registers and connection valid flags. Reset interrupt pending and in-service registers. Reset interrupt in-service register only. 0x00101 Reset Select 7:2 Reserved 0000 NOP (default).

1 HRBEB 0

Disable hard reset to back end. Enable hard reset to back end (default). Disable soft resets to back end. Enable soft resets to back end (default).

5.1.3 Connection Control—Data Memory Selector Register

1. 4k single-buffered switch. Standard H-bus/L-bus switching only, up to 4096 simplex connections, all connections

are minimum delay due to single-buffer configuration.

1. 2k double-buffered switch. Standard H-bus/L-bus switching only, up to 2048 simplex connections, all connec-

tions are programmable for minimum or constant delay via the double-buffer configuration.

1. 2k single-buffered switch + 1k double-buffered switch. Standard H-bus/L-bus switching only, up to 2048 simplex

Table 17. Master Output Enable Register Individual enables via bits [6:0] (default). Enable all (same as bits [6:0] = 1111111).

3 HCKEB 0

Disable H-bus clocks (default).

2 HDBEB 0

Disable H-bus data streams (default). Disable L-bus clocks, L_SC, FG (default). Disable L-bus data streams (default). Table 18. Data Memory Mode Select Register Disable subrate switching (default). 4k single-buffer switch (default). 2k single-buffer, 1k double-buffer switch.

5.1.4 General Clock Control (Phase Alignment, Fallback, Watchdogs) Register

5.1.5 Phase Alignment Select Register

reference from the H-bus (/CT_FRAME_A, /CT_FRAME_B, or /FR_COMP) or local clock reference (LREF[4:7]).

5.1.6 Fallback Control Register

ence (synchronized to frame). to be performed until the next 8 kHz frame reference (synchronized to frame). Table 19. Clock Register Access Select Register Access inactive clock registers (default). Access active clock registers. Table 20. Phase Alignment Select Register Phase alignment is disabled (default).

5.1.6 Fallback Control Register (continued)

performed until the next 8 kHz frame reference (synchronized to frame). tive clock register set. This command is performed immediately upon issue.

5.1.7 Fallback Type Select Register

require the fallback trigger register settings. For more details, see Section 6.7.1 on page 64. are three possible selections. For more details, see Section 6.7 on page 64. ! Disabled. No transitions of clock register X and Y sets to active/inactive. ! Fixed secondary. Swap the active/inactive sets on a fallback event; swap them back when fallback is cleared. Table 21. Fallback Control Register GO_CLOCKS synchronized to frame*. CLEAR_FALLBACK synchronized to frame*. FORCE_FALLBACK synchronized to frame*.

5.1.7 Fallback Type Select Register (continued)

5.1.8 Fallback Trigger Registers

DPLL2 can also trigger a clock fallback event upon detection of an error. Table 22. Fallback Type Select Register Legacy, fallback to OSC/4 on main select failure. Legacy, fallback X/Y set on main select failure. Legacy, fallback X/Y set on H-bus A/B failure. Fallback trigger registers control fallback. H-Bus clock enable state machine is enabled. Fallback is disabled (default). Enable fixed secondary fallback. Enable rotating secondary fallback. Table 23. Fallback Trigger Registers Disable /SCLKx2 trigger (default). Disable SCLK trigger (default). Disable C2 trigger (default). Disable /C4 trigger (default). Disable /C16– trigger (default). Disable /C16+ trigger (default). Disable CT_C8_B trigger (default). Disable CT_C8_A trigger (default).

5.1.8 Fallback Trigger Registers (continued)

5.1.9 Watchdog Select, C8, and NETREF Registers

clocking architecture, including 8 kHz (frame reference), 1.544 MHz (T1 bit clock), and 2.048 MHz (E1 bit clock). Table 23. Fallback Trigger Registers (continued) 0x0010B Fallback Trigger, Upper 7 Reserved 0 NOP (default). Disable DPLL2 sync trigger (default). Disable DPLL1 sync trigger (default). Disable CT_NETREF2 trigger (default). Disable CT_NETREF1 trigger (default). Disable /FR_COMP trigger (default). Disable /CT_FRAME_B trigger (default). Disable /CT_FRAME_A trigger (default). Table 24. Watchdog Select, C8, NETREF Registers CT_C8_B watchdog at 8.192 MHz (default). CT_C8_B watchdog at 4.096 MHz MC1mode. CT_C8_A watchdog at 8.192 MHz (default). CT_C8_A watchdog at 4.096 MHz MC1mode. CT_NETREF2 watchdog at 8 kHz (default). CT_NETREF2 watchdog at 1.544 MHz. CT_NETREF2 watchdog at 2.048 MHz. CT_NETREF1 watchdog at 8 kHz (default). CT_NETREF1 watchdog at 1.544 MHz. CT_NETREF1 watchdog at 2.048 MHz.

5.1.10 Watchdog EN Register

dogs on the sync inputs of DPLL1 and DPLL2. Table 25. Watchdog EN Registers Disable /SCLKx2 watchdog (default). Disable SCLK watchdog (default). Disable C2 watchdog (default). Disable/C4 watchdog (default). Disable/C16– watchdog (default). Disable/C16+ watchdog (default). Disable CT_C8_B watchdog (default). Disable CT_C8_A watchdog (default). Disable FAILSAFE ref watchdog (default). Enable FAILSAFE ref watchdog. Disable DPLL2 sync watchdog (default). Disable DPLL1 sync watchdog (default). Disable CT_NETREF2 watchdog (default). Disable CT_NETREF1 watchdog (default). Disable /FR_COMP watchdog (default).

1 FBWEB 0

Disable /CT_FRAME_B watchdog (default). Enable /CT_FRAME_B watchdog. Disable /CT_FRAME_A watchdog (default). Enable /CT_FRAME_A watchdog.

5.1.11 Failsafe Control Registers

either the primary or secondary clock register sets. For more on failsafe, please see Section 6.7.2 on page 70. see Section 6.7.2 on page 70. on OOL operation, please see Section 6.7.2 on page 70. Table 26. Failsafe Control Register Return from failsafe to nonfallback condition. Return from failsafe to fallback condition. Failsafe watchdog highest sensitivity. Failsafe watchdog + 30.5 ns. Failsafe watchdog + 121.0 ns. Failsafe watchdog + 244.0 ns. Failsafe watchdog + 488.0 ns. 0x00118 OOL Threshold Low 7:0 OLLLR LLLL LLLL Failsafe threshold value, low byte. 0x00119 OOL Threshold High 7:0 OLHLR LLLL LLLL Failsafe threshold value, high byte. Monitor direct APLL1 lock detect at PLOCK. Monitor user threshold lock detect at PLOCK.

5.2 Error and Status Registers

of these registers will clear the corresponding error bit. The remaining error and status registers are read-only. Table 27. Error and Status Register Map

5.2 Error and Status Registers (continued)

5.2.1 Clock Errors

5.2.1.1 Transient Clock Errors Registers

Table 28. Clock Error Registers Failsafe indicator: APLL1 reference no error. DPLL2 sync no error (default). DPLL1 sync no error (default). CT_NETREF2 no error (default). CT_NETREF1 no error (default). /FR_COMP no error (default). /CT_FRAME_B no error (default). /CT_FRAME_A no error (default).

5.2.1 Clock Errors (continued)

5.2.1.2 Latched Clock Error Register

tion 10 on page 90 for more details. Table 29. Latched Clock Error Registers Failsafe indicator: APLL1 reference no error. DPLL2 sync no error (default). DPLL1 sync no error (default). CT_NETREF2 no error (default). CT_NETREF1 no error (default). /FR_COMP no error (default). /CT_FRAME_B no error (default). /CT_FRAME_A no error (default).

5.2.2 System Status

5.2.2.1 Clock Fallback Status Register

The lower nibble provides status indicators related to the X and Y clock register set active/inactive assignments. 0x00108), which are waiting for a frame sync. Table 30. Fallback and Failsafe Status Register Indicates not in fallback/failsafe state (default). Indicates fallback/failsafe state. Fallback state = INITIAL (default). Fallback state = TO_PRIMARY. Fallback state = TO_SECONDARY. Clock register Y set is active, X is inactive. Clock register X set is active, Y is inactive.

2 GOPOB 0

No GO_CLOCKS pending (default). GO_CLOCKS pending, waiting for frame. No CLEAR_FALLBACK pending (default). CLEAR_FALLBACK pending, waiting for frame.

0 FFPOB 0

No FORCE_FALLBACK pending (default).

5.2.2 System Status (continued)

5.2.2.2 Device Identification Registers

5.2.2.3 System Device Errors

These registers identify the device type and revision status, T8110L revision n. Table 31. System Errors Registers Table 32. Device Identification Registers 0x00128 Version ID 7:0 VEROR 0000 0001 Revision status (value shown = REV1). 0x0012A Device ID, Lower 7:0 IDLOR 0001 0000 Device ID low status 0x10. 0x0012B Device ID, Upper 7:0 IDHOR 1000 0001 Device ID high status 0x81.

6 Clock Architecture

Figure 5. T8110L Main Clocking Paths Figure 6. T8110L NETREF Paths

2.048 MHz

4.096 MHz

8.192 MHz

16.364 MHz

32.768 MHz

65.536 MHz

49.408 MHz

4 MHz

6 Clock Architecture (continued)

6.1 Clock Input Control Registers

The following registers control the T8110L main clocking paths and NETREF paths.

6.1.1 Main Input Selector Register

The main input selector register controls clock and frame input selection.

• C2 is allowed as the bit clock input.
• Selection of which LREF is controlled at register 0x00208. Selection of LREF polarity is controlled at register 0x0020C.

Table 33. Clock Input Control Register Map Table 34. Main Input Selector Register Select oscillator/crystal (default). Select LREF[0:7] individually. Select LREF[0:3, 4:7] paired. Select MVIP clocks (C2 bit clock)*. Select MVIP clocks (/C4 bit clock). Select H-MVIP clocks (/C16± bit clock). Select SC-bus clocks 4/8 MHz.

6.1 Clock Input Control Registers (continued)

• C2 is allowed as the bit clock input.

6.1.2 Main Divider Register

The main divider register contains [divider value – 1]. A value of 0x00 yields a divide-by-1 function. A value of 0xFF yields a divide-by-256 function.

6.1.3 Analog PLL1 (APLL1) Input Selector Register

Table 35. Main Divider Register Table 36. APLL1 Input Selector Register Select oscillator/4 (default). Select resource divider output. Select external input PRI_REF_IN.

6.1.4 APLL1 Rate Register

[x32 (multiplied by)] value must be selected. A [x1 (multiplied by)] value is provided in order to bypass APLL1.

6.1.5 Main Inversion Select Register

! Main clock selection CLK SEL MUX output; see Figure 5 on page 44. ! NETREF2 divider output; see Figure 6 on page 44. ! NETREF2 selection MUX output. ! NETREF1 selection MUX output. Table 37. APLL1 Rate Register Times 1 BYPASS (lower nibble is don't care). Table 38. Main Inversion Select Register 0x00204 Main Inversion Select 7:5 Reserved 000 NOP (default). Don't invert main clock selection (default). Invert main clock selection. Don't invert NETREF2 divider output (default). Invert NETREF2 divider output.

2 N2SSB 0

Don't invert NETREF2 selection (default). Don't invert NETREF1 divider output (default). Invert NETREF1 divider output.

0 N1SSB 0

Don't invert NETREF1 selection (default).

6.1.6 Resource Divider Register

0xFF yields a divide-by-256 function.

6.1.7 Analog PLL2 (APLL2) Rate Register

(times 8) value must be selected. A (times 1) value is provided in order to bypass APLL2. Table 39. Resource Divider Register Table 40. APLL2 Rate Register Times 1 BYPASS (lower nibble is don't care).

6.1.8 LREF Input Select Registers

selection control among the eight LREF inputs when the main selection is set for either individual or paired LREFs. Section 6.4.1.3 on page 60 for further details. Table 41. LREF Input/Inversion Select Registers Select paired, clock = LREF0, frame = LREF4. Select paired, clock = LREF1, frame = LREF5. Select paired, clock = LREF2, frame = LREF6. Select paired, clock = LREF3, frame = LREF7. Don't invert LREF7 (default). Don't invert LREF6 (default). Don't invert LREF5 (default). Don't invert LREF4 (default). Don't invert LREF3 (default). Don't invert LREF2 (default). Don't invert LREF1 (default). Don't invert LREF0 (default).

6.1.9 DPLL1 Input Selector

6.1.9.1 DPLL1 Rate Register

The DPLL1 rate register controls the DPLL1 output frequency.

6.1.10 DPLL2 Input Selector

Table 42. DPLL1 Input Selector Registers DPLL1 output at 4.096 MHz (default).

6.1.10 DPLL2 Input Selector (continued)

6.1.10.1 DPLL2 Rate Register

The DPLL2 rate register controls the DPLL2 output frequency.

6.1.11 NETREF1 Registers

used to generate CT_NETREF1 (see Figure 6 on page 44).

• Selection of which LREF is controlled at register 0x00212.

Table 43. DPLL2 Register T8110L internally generated frame. Table 44. NETREF1 Registers Divider input = selector output (default). Divider input = external input NR1_DIV_IN. Oscillator/XTAL1-div-8, 2.048 MHz (default). Oscillator/XTAL1, 16.384 MHz. Oscillator/XTAL2, 6.176 MHz, or 12.352 MHz.

6.1.12 NETREF2 Registers

used to generate CT_NETREF2 (see Figure 6 on page 44).

• Selection of which LREF is controlled at register 0x00216.

Table 45. NETREF2 Registers Divider input = selector output (default). Divider input = external input NR1_DIV_IN. Oscillator/XTAL1-div-8, 2.048 MHz (default). Oscillator/XTAL1, 16.384 MHz. Oscillator/XTAL2, 6.176 MHz, or 12.352 MHz.

6.2 Clock Output Control Registers

The registers listed below control output enable and rate selection of the T8110L clock path outputs.

6.2.1 Master Output Enables Register

B-clocks refers to the CT_C8_B bit clock and /CT_FRAME_B frame reference. Table 46. Clock Output Control Register Map

6.2 Clock Output Control Registers (continued)

6.2.1 Master Output Enables Register (continued)

6.2.2 Clock Output Format Registers

The clock output format registers select the pulse width of the /FR_COMP pulse width. not phase align to a 244 ns /FR_COMP signal. (H1x0) mode, or 4.096 MHz for MC1 mode. Table 47. Master Output Enables Registers Disable A and B clock outputs (default). Enable A clock outputs only. Enable B clock outputs only. Enable both A and B clock outputs. Disable compatibility (C clock) outputs (default). Enable C clocks individually*. CT_NETREF2 disabled (default). CT_NETREF1 disabled (default). /FR_COMP disabled (default). C-clock bit clocks disabled (default).

6.2.2 Clock Output Format Registers (continued)

6.2.3 TCLK and L_SCx Select Registers

L_SC1, L_SC2, and L_SC3 signals. Table 48. Clock Output Format Registers /FR_COMP width is 122 ns (default). CT_C8_B output at 8.192 MHz (default). CT_C8_B output at 4.096 MHz, MC1 mode. CT_C8_A output at 8.192 MHz (default). CT_C8_A output at 4.096 MHz, MC1 mode. SCLK = 4 MHz, /SCLKx2 = 8 MHz. SCLK = 8 MHz, /SCLKx2 = 8 MHz phase shifted.

6.2.3 TCLK and L_SCx Select Registers (continued)

Table 49. TCLK Select and L_SCx Select Registers TCLK output disabled (default). Select APLL1 output, 65.536 MHz. Select APLL2 output, 49.704 MHz. Select DPLL2 output inverted. Select APLL1 output inverted. Select APLL2 output inverted. Select generated 16.384 MHz. Select generated 32.768 MHz. Select generated 2.048 MHz inverted. Select generated 4.096 MHz inverted. Select generated 8.192 MHz inverted. Select generated 16.384 MHz inverted. select generated 32.768 MHz inverted. Select generated CT_NETREF1. Select generated CT_NETREF2. Select generated frame inverted. Select generated CT_NETREF1 inverted. Select generated CT_NETREF2 inverted. L_SCx output disabled (default). Select generated 16.384 MHz. Select generated 32.768 MHz. Select generated 2.048 MHz inverted. Select generated 4.096 MHz inverted. Select generated 8.192 MHz inverted. Select generated 16.384 MHz inverted. Select generated 32.768 MHz inverted. Select generated CT_NETREF1. Select generated CT_NETREF2. Select generated frame inverted. Select generated CT_NETREF1 inverted. Select generated CT_NETREF2 inverted.

6.3 Clock Register Access

6.4 Clock Circuit Operation—APLL1

diagnostic purposes. Please refer to Figure 5 on page 44.

6.4.1 Main Clock Selection, Bit Clock, and Frame

main divider, resource divider, and DPLL1.

• MVIP, /C4 is typically the bit clock. C2 is selectable as the bit clock as well.

† Used when LREF pairing is enabled. When using LREF pairing, the bit clock should be 2.048 MHz. Table 50. Bit Clock and Frame

6.4 Clock Circuit Operation—APLL1 (continued)

6.4.1 Main Clock Selection, Bit Clock, and Frame (continued)

6.4.1.1 Watchdog Timers

incoming clocks at 32.768 MHz (derived from the XTAL1 crystal) and monitor for loss of signal, as shown below. Table 51. Watchdog Timer Description 35 ns window of its expected arrival. MC1 mode. Monitors for loss of signal (falling edges). (i.e., next frame pulse too early). (i.e., next frame pulse too early). (i.e., next frame pulse too early).

• User selects frequency at which to monitor the CT_C8 clocks via register 0x0010C, watchdog select, C8.

†DPLL sync reference is expected to be 8 kHz.

6.4.1.2 Frame Center Sampling

relevant when the main clock selection is based on a paired bit clock/frame reference, as follows. Table 52. Frame Center Sampling /CT_FRAME_A CT_C8_A Recovered 8.192 MHz, rising edge. /CT_FRAME_B CT_C8_B Recovered 8.192 MHz, rising edge. Recovered 4.096 MHz, falling edge. /FR_COMP SCLK or /SCLKx2 (SC-bus) Recovered 2.048 MHz, rising edge. LREF[4] LREF[0] Recovered 2.048 MHz, rising edge. LREF[5] LREF[1] Recovered 2.048 MHz, rising edge. LREF[6] LREF[2] Recovered 2.048 MHz, rising edge. LREF[7] LREF[3] Recovered 2.048 MHz, rising edge.

6.4.1.3 LREF Pair Polarity Configuration

provided with a frame pulse and bit clock with polarities as shown below. Figure 7. T8110L Required Frame Pulse and Bit Clock with Polarities allows any LREF signal to be inverted. the T8110L is deriving clocking from the LREF pair.

Agere Systems Inc. 61 Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch

6.4.2 Main and Resource Dividers

Two independently programmable dividers are available to divide down the main clock selection signal. The func- tion ranges from divide-by-1 (bypass) to divide-by-256. ! For binary divider values of 1, 2, 4, 8, 16, 32, 64, 128, and 256, the output is 50% duty cycle. ! For a divider value of 193, the output is almost 50% duty cycle (low-level duration is one clock cycle shorter than high-level duration). ! For all other divider values, the output is a pulse whose width is one full period of the main clock selection signal. Output of both dividers is available to the DPLL1 and the APLL1 reference selector. The output of the main divider is also available at the PRI_REF_OUT chip output. Both dividers are reset whenever a changeover between X and Y clock register sets is detected; see Section 6.3 on page 57. This allows for immediate loading of the newly activated divider register values.

6.4.3 DPLL1

A digital phase-lock loop is provided to generate a 4.096 MHz or 2.048 MHz reference to APLL1, selectable via register 0x0020B (DPLL1 rate). The DPLL1 operates at 32.768 MHz, derived from the XTAL1 crystal input. The DPLL1 synchronization source is selectable (register 0x0020A, DPLL1 input selector) between the main clock selection signal, the output of the resource divider, or the output of the main divider, and is intended to be pre- sented as an 8 kHz frame reference. DPLL1 is determined to be in-lock or out-of-lock, based on the state of the output clock when an edge transition is detected at the synchronization source. An out-of-lock condition results in a DPLL1 correction, which can either lengthen or shorten its current output clock period by 30.5 ns.

6.4.4 Reference Selector

The APLL1 reference clock is selectable between five possible sources via register 0x00202, APLL1 input selector. A 4.096 MHz or 2.048 MHz reference must be provided. The five possible sources are shown below: ! XTAL1 crystal (16.384 MHz) divided-by-4 ! Main divider output ! Resource divider output ! DPLL1 output ! PRI_REF_IN external chip input

6.4.5 Internal Clock Generation

The main internal functions of T8110L are synchronous to the 65.536 MHz output of APLL1. This clock is further divided to generate 32.768 MHz, 16.384 MHz, and 8 kHz internal reference signals. Additional divide-down values to 8.192 MHz, 4.096 MHz, and 2.048 MHz are generated. These generated clocks are the source for H1x0, H-MVIP, MVIP, and SC-bus clocks when the T8110L is mastering the bus clocks; see Section 6.2 on page 53. These internally generated clocks can either be free-running, or can be aligned to the incoming main selection clock and frame, via a phase alignment circuit (see Section 7.4.5.1).

6.4.5 Internal Clock Generation (continued)

6.4.5.1 Phase Alignment

the phase alignment circuit is enabled (via register 0x00107, phase alignment select). pared to the state of the internally generated frame. The circuit determines whether the frame centers are aligned. ! NOP: no corrections when phase alignment is disabled. frame periods that are 15.25 ns longer than 125 µs until the frames are aligned. Please refer to Figure 8. Figure 8. T8110L Phase Alignment, SNAP and SLIDE

Agere Systems Inc. 63 Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch

6.5 Clock Circuit Operation, APLL2

APLL2 requires either a 6.176 MHz or 12.352 MHz reference clock to produce a 49.408 MHz clock for operating DPLL2. A user-supplied rate multiplier (register 0x00207, APLL2 rate) provides either a times 8 function (when ref- erence clock = 6.176 MHz) or a times 4 function (when reference clock = 12.352 MHz). Additionally, APLL2 may be bypassed for circuit diagnostic purposes (see Figure 5 on page 44).

6.5.1 DPLL2

A second digital phase-lock loop is provided to generate various derivations of T1 operating frequencies, available by selection via the TCLK_OUT output. The possible output frequencies are selectable via register 0x0020F 49.408 MHz from the APLL2 output. Synchronization sources for DPLL2 include the same sources provided to DPLL1 (selectable between the main clock selection signal, the output of the resource divider, or the output of the main divider) and two additional sources, including the T8110L internally generated frame signal and the PRI_REF_IN input. These selections are available via register 0x0020E, DPLL2 input selector. DPLL2 is deter- mined to be in-lock or out-of-lock based on the state of its output when an edge transition is detected at the syn- chronization source. An out-of-lock condition results in a DPLL2 correction, which can either lengthen or shorten its current output clock period by 20.2 ns.

6.6 Clock Circuit Operation, CT_NETREF Generation

The T8110L provides two independently programmable paths to generate CT_NETREF1 and CT_NETREF2, via registers 0x00210—0x00216. Each CT_NETREF is individually enabled with register 0x00221, NETREF output enables. Each path consists of a source selector MUX and a divider circuit (see Figure 6 on page 44).

6.6.1 NETREF Source Select

XTAL1 input DIV 8 (2.048 MHz) XTAL1 input (16.384 MHz) XTAL2 input (6.176 MHz or 12.352 MHz) LREF[7:0] CT_NETREFx (the other NETREF—i.e., CT_NETREF1 can be derived from CT_NETREF2, and vise-versa). The output of the source select MUX is made available directly to the NETREF divider, and also to chip output (NR1_SEL_OUT, NR2_SEL_OUT).

6.6.2 NETREF Divider

Each NETREF path provides a divider from a divide-by-1 function up to a divide-by-256 function. The clock source for the divider is selectable between the output of the source select MUX or from external chip input (NR1_DIV_IN, NR2_DIV_IN). ! For binary divider values of 1, 2, 4, 8, 16, 32, 64, and 128, output is 50% duty cycle. ! For divider values of 256, 193, plus all other nonbinary values, output is a pulse whose width is one-half of a clock period, asserted during the second half of the divider clock period. The NETREF dividers are reset whenever a changeover between X and Y clock register sets is detected (see Sec- tion 6.3 on page 57). This allows for immediate loading of the newly activated divider register values.

64 Agere Systems Inc. Data Sheet February 2004Ambassador T8110L H.100/H.110 Switch

6.7 Clock Circuit Operation—Fallback and Failsafe

Fallback is a means to alter the reference source to APLL1 by switching between two clock control register sets upon detection of a fallback event. Failsafe is a feature to provide a safety net for the reference source to APLL1, independent of clock fallback.

6.7.1 Clock Fallback

Clock fallback is a means to alter the APLL1 reference clock source upon detection of a fallback event and is con- trolled by eight registers, 0x00108—0x0010F (refer to Section 5.1.4 on page 33). These registers enable and con- trol the state transitions that determine which of two clock register sets is used to control the APLL1 reference clock source (see Section 6.1 on page 45 through Section 6.3, Table 54 on page 67, and Figure 10 on page 66).

6.7.1.1 Fallback Events

Clock fallback (transition from primary to secondary clock sets) can only occur if the fallback mode is enabled (reg- ister 0x00109, lower nibble) and a fallback event occurs. When enabled, there are three ways to trigger the fallback event: ! Software, via a FORCE_FALLBACK command. The user sets bit 2 of the fallback control register, 0x00108, cre- ating a software-invoked fallback event. ! Hardware via the fallback trigger enable registers, 0x0010A—0x0010B. User may enable specific watchdog tim- ers and corresponding fallback trigger enable bits. If a watchdog timer indicates a clock error, and its correspond- ing trigger enable bit is set, a hardware-invoked fallback event is produced. ! Hardware, legacy modes, via the fallback type select register, 0x00109, upper nibble. The legacy modes are included to maintain backwards compatibility with earlier Ambassador devices. User may enable specific watch- dog timers, but the fallback trigger enable registers are ignored. Instead, the watchdogs which are allowed to trigger a fallback event are automatically selected based on the state of the main input selector register, 0x00200 (refer to Table 53). If a watchdog timer indicates a clock error, and its corresponding trigger enable is selected via the main input selector, a hardware-invoked fallback event is produced.

6.7 Clock Circuit Operation—Fallback and Failsafe (continued)

6.7.1 Clock Fallback (continued)

6.7.1.1 Fallback Events (continued)

between the primary and secondary clock sets. fallback event is cleared (via user-invoked CLEAR_FALLBACK), the active clock set returns to primary. the new primary, and the primary becomes the new secondary. The concepts are illustrated in the figure below. Figure 9. Fallback—Fixed vs. Rotating Secondary Table 53. Legacy Mode Fallback Event Triggers

Figure 10. T8110L Clock Fallback States

• Fallback event; refer to Section 6.7.1.1 on page 64.

† Fixed, rotating secondary; refer to Section 6.7.1.2 on page 65. Table 54. Clock Fallback State Description (set register 0x00108 bit 0).

6.7.1.3 H-Bus Clock Enable/Disable on Fallback

enable/disable is activated. determine what triggers a fallback, and the state machine which controls H-bus clock enable/disable is activated. Figure 11. T8110L H-Bus Clock Enable States

6.7.1.1 H-Bus Clock Enable/Disable on Fallback (continued)

Table 55. H-Bus Clock Enable State Description ter (0x00220, master output enables). ter (0x00220, master output enables). and B clocks (diagnostic mode). ter (0x00220, master output enables). ter (0x00220, master output enables). been promoted to A clock master. is detected; disable clock outputs. ter (0x00220, master output enables). is detected; promote to A clock master. is detected; disable clock outputs. ter (0x00220, master output enables). stopped driving any H bus clocks. ter (0x00220, master output enables). been promoted to B clock master. is detected; disable clock outputs. ter (0x00220, master output enables). is detected; promote to B clock master. is detected; disable clock outputs. ter (0x00220, master output enables). stopped driving any H bus clocks. ter (0x00220, master output enables).

6.7.2 Clock Failsafe

(primary or secondary) or a fallback (TO_SECONDARY or TO_PRIMARY) state. Refer to Table 56 and Figure 12.

6.7.2.1 Failsafe Events

is triggered by a watchdog error on the APLL1 reference clock (i.e., loss-of-reference). Figure 12. T8110L Clock Failsafe States

6.7.2 Clock Failsafe (continued)

6.7.2.1 Failsafe Events (continued)

Table 56. Clock Failsafe State Descriptions (set register 0x00114 bit 0). (set register 0x00114 bit 1). (set register 0x00114 bit 0). (set register 0x00114 bit 1).

7 Frame Group and FG I/O

ation, providing a timer via a 16-bit programmable counter.

7.1 Frame Group Control Registers

7.1.1 FGx Lower and Upper Start Registers

The FGx lower and upper start registers provide a 12-bit delay offset value for the corresponding frame group bit. 32.768 MHz clock period (30.5 ns increments). Table 57. Frame Group and FG I/O Register Map Table 58. FGx Lower and Upper Start Registers LLLL LLLL Lower 8 bits of 12-bit start offset. 0000 LLLL Upper 4 bits of 12-bit start offset.

7 Frame Group and FG I/O (continued)

7.1 Frame Group Control Registers (continued)

7.1.2 FGx Width Registers

The FGx width registers control the polarity and the pulse widths generated for the corresponding frame group bit. 1-byte, and 2-byte wide pulses for any of the available frame group rates (see Table 59).

7.1.3 FGx Rate Registers

• FGIO operation is controlled at registers 0x00480—482. Refer to Section 7.3 on page 75.

Table 59. FGx Width Registers Generate active-high pulse (default). Table 60. FGx Rate Registers FGIO enabled* (not used as a frame group).

7.2 FG7 Timer Option

The FG7 signal allows for an added function of a timer output, via a 16-bit programmable counter.

7.2.1 FG7 Counter (Low and High Byte) Registers

• Normal operation allows frame group or FGIO control via registers 0x00470—473. Enabling the counter overrides 0x00470—473 settings.

‡ Carry out pulse is active for one FG7 timer clock period. § Programmable pulses are based on T8110L internal 32.768 MHz clock periods. Table 61. FG7 Counter (Low and High Byte) Registers 0x00474 FG7 Counter, Low Byte 7:0 FCLLR LLLL LLLL Lower 8 bits of 16-bit counter value. 0x00475 FG7 Counter, High Byte 7:0 FCULR LLLL LLLL Upper 8 bits of 16-bit counter value. Normal operation* (default). Enable timer, clock = internal frame. Enable timer, clock = external FG6. Inverted FG7 timer output, low pulses. FG7 timer output off (default). FG7 timer output = carry out pulse‡. FG7 timer output = programmable pulse§. Programmable pulse width = 30.5 ns. Programmable pulse width = 61.0 ns. Programmable pulse width = 91.5 ns. Programmable pulse width = 122 ns.

7.3 FGIO Control Registers

7.3.1 FGIO Data Register

FGx rate registers. Reads are maskable, controlled via register 0x00481.

7.3.2 FGIO Read Mask Register

on a read access to the FGIO register. Table 62. FGIO Data Register 0x00480 FGIO Data Register 7 F7IOB L FGIO bit 7 value. Table 63. FGIO Read Mask Register Unmask FGIO bit 7 (default). Mask FGIO bit 7, return 0 on a read. Unmask FGIO bit 6 (default). Mask FGIO bit 6, return 0 on a read. Unmask FGIO bit 5 (default). Mask FGIO bit 5, return 0 on a read. Unmask FGIO bit 4 (default). Mask FGIO bit 4, return 0 on a read. Unmask FGIO bit 3 (default). Mask FGIO bit 3, return 0 on a read. Unmask FGIO bit 2 (default). Mask FGIO bit 2, return 0 on a read. Unmask FGIO bit 1 (default). Mask FGIO bit 1, return 0 on a read. Unmask FGIO bit 0 (default). Mask FGIO bit 0, return 0 on a read.

7.3 FGIO Control Registers (continued)

7.3.3 FGIO R/W Register

Table 64. FGIO R/W Register FGIO bit 7 direction is input (default). FGIO bit 7 direction is output. FGIO bit 6 direction is input (default). FGIO bit 6 direction is output. FGIO bit 5 direction is input (default). FGIO bit 5 direction is output. FGIO bit 4 direction is input (default). FGIO bit 4 direction is output. FGIO bit 3 direction is input (default). FGIO bit 3 direction is output. FGIO bit 2 direction is input (default). FGIO bit 2 direction is output. FGIO bit 1 direction is input (default). FGIO bit 1 direction is output. FGIO bit 0 direction is input (default). FGIO bit 0 direction is output.

7.4 FG Circuit Operation

Figure 13. FG[7:0] Functional Paths

7.4 FG Circuit Operation (continued)

7.4.1 Frame Group 8 kHz Reference Generation

control required, an offset delay from internal frame center, and pulse shaping.

2.048 Mbits/s 488 ns

4.096 Mbits/s 244 ns

8.192 Mbits/s 122 ns

16.384 Mbits/s 61 ns

Frame group signals shown with offset = 0 (default). At offset = 0, the pulse starts at frame center. period. Offsets may be programmed in the range from 0—4095. Frame group signals are shown as active high pulses (default)—they may be programmed as active-low pulses. rates (2 Mbits/s, 4 Mbits/s, 8 Mbits/s, or 16 Mbits/s). Figure 14. Frame Group 8 kHz Reference Timing

Agere Systems Inc. 79 Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch

7.4.2 FGIO General-Purpose Bits

Any of the T8110L FG signals may be used as general-purpose I/O bits. Each FG bit used as FGIO is configured by enabling the FGIO function via the FGx rate register(s) and setting the direction via the appropriate bits in the FGIO R/W register. For write access to the FGIO, the FGIO data register is used to hold data for output to the FG pin(s). Read accesses are maskable via the FGIO read mask register. For read access from the FGIO, the logical state of the FG[7:0] signals is returned if unmasked. If an FGIO bit is masked, a read access returns 0.

7.4.3 Programmable Timer (FG7 Only)

The FG7 signal can be used as a programmable timer output, via the FG7 mode upper/lower, and FG7 counter high and low byte registers. The FG7 timer is simply a clock divider. The FG7 counter high/low provides a 16-bit [divider value – 1]. Note:[divider value – 1], i.e., a value of 0000000000000011 yields a div-by-4 operation. The FG7 mode lower register enables the counter and selects between two clock sources into the counter: either the T8110L internal frame (8 kHz) or an external clock via the FG6 input. The FG7 mode upper register controls the output pulse shape. The output can be inverted or noninverted and shaped as either a square wave, a carryout pulse, or a programmable-width pulse. ! Square wave. This option is applicable only for divide operations that are binary multiples (i.e., div-by-2, div-by- 4, div-by-8, div-by-16, div-by-65536). Nonbinary divide operations while square wave is selected result in a car- ryout pulse. ! Carryout pulse. The output is a pulse, width = one FG7 timer clock period. ! Programmable-width pulse. The timer output is synchronized to the T8110L 32.768 MHz clock domain and can be programmed for 1, 2, 3, or 4, 32.768 MHz clock periods in width (30.5 ns, 61 ns, 91.5 ns, or 122 ns).

7.4.4 FG External Interrupts

All FG signals are internally connected as inputs to the interrupt controller logic. Any FG signal, whether an output or an input, may be used to trigger interrupts. When a T8110L FG signal is used as an externally sourced input into the interrupt controller logic, it must be in input mode (i.e., shut-off, FGx rate register(s) FxRSR = 0000 0000). An FG signal in output mode may also be used for interrupts (i.e., an 8 kHz periodic signal, see Section 7.4.1 on page 78). The interrupt control registers (0x00600—603) control how the FG inputs are handled (for more details, refer to Section 10.1 on page 90).

7.4.5 FG Diagnostic Test Point Observation

Any of the T8110L FG signals may be used to observe a predefined set of internal testpoints. Each FG bit used as a testpoint output is enabled via diagnostic register 0x00140, FG testpoint enable. Settings in this register override the FGx rate and FGIO R/W register, and force the selected bits to be testpoint outputs, see Section 11.1 on page 106 and Table 88 on page 106.

8 General-Purpose I/O

8.1 GPIO Control Registers

8.1.1 GPIO Data Register

eral-purpose register bits. Reads from GPIO are maskable, controlled via register 0x00501. Table 65. GPIO Register Table 66. GPIO Data Register 0x00500 GPIO Data Register 7 G7IOB L GPIO bit 7 value.

8 General-Purpose I/O (continued)

8.1 GPIO Control Registers (continued)

8.1.2 GPIO Read Mask Register

on a read access to the GPIO register.

8.1.3 GPIO R/W Register

Table 67. GPIO Read Mask Register Unmask GPIO bit 7 (default). Mask GPIO bit 7, return 0 on a read. Unmask GPIO bit 6 (default). Mask GPIO bit 6, return 0 on a read. Unmask GPIO bit 5 (default). Mask GPIO bit 5, return 0 on a read. Unmask GPIO bit 4 (default). Mask GPIO bit 4, return 0 on a read. Unmask GPIO bit 3 (default). Mask GPIO bit 3, return 0 on a read. Unmask GPIO bit 2 (default). Mask GPIO bit 2, return 0 on a read. Unmask GPIO bit 1 (default). Mask GPIO bit 1, return 0 on a read. Unmask GPIO bit 0 (default). Mask GPIO bit 0, return 0 on a read. Table 68. GPIO R/W Register GPIO bit 7 direction is input (default). GPIO bit 7 direction is output. GPIO bit 6 direction is input (default). GPIO bit 6 direction is output. GPIO bit 5 direction is input (default). GPIO bit 5 direction is output. GPIO bit 4 direction is input (default). GPIO bit 4 direction is output. GPIO bit 3 direction is input (default). GPIO bit 3 direction is output. GPIO bit 2 direction is input (default). GPIO bit 2 direction is output. GPIO bit 1 direction is input (default). GPIO bit 1 direction is output. GPIO bit 0 direction is input (default). GPIO bit 0 direction is output.

8.1.4 GPIO Override Register

8.2 GP Circuit Operation

refer to Figure 15 on page 82. Figure 15. GP[7:0] Functional Paths Table 69. GPIO Override Register 0x00503 GPIO Override 7:2 Reserved 0000 0 NOP (default). GPIO bit 1 is GPIO (default). GPIO bit 1 B-master indicator output. GPIO bit 0 is GPIO (default). GPIO bit 0 A-master indicator output.

Agere Systems Inc. 83 Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch

8.2 GP Circuit Operation (continued)

8.2.1 GPIO General-Purpose Bits

Any of the T8110L GP signals may be used as general-purpose I/O bits. Each GP bit used as GPIO is configured by setting the direction via the appropriate bits in the GPIO R/W register. For write access to the GPIO, the GPIO data register is used to hold data for output to the GP pin(s). Read accesses are maskable via the GPIO read mask register. For read access from the GPIO, the logical state of the GP[7:0] signals is returned if unmasked. If a GPIO bit is masked, a read access returns 0.

8.2.2 GP Dual-Purpose Bits GPIO (Override)

8.2.2.1 GP H.110 Clock Master Indicators (GP0, GP1 Only) An additional function is provided for GP0 and GP1 only, controlled via the GPIO override register. GP0 may be used as a dedicated output (set GPIO override register bit 0), which transmits the state of the T8110L A clock master enable (register 0x00220, bit 4). This output is intended to drive the external A clock FETs required for H.110 bus mastering. GP1 may be used as a dedicated output (set GPIO override register bit 1), which transmits the state of the T8110L B clock master enable (register 0x00220, bit 5). This output is intended to drive the external B clock FETs required for H.110 bus mastering.

8.2.3 GP External Interrupts

Any of the T8110L GP signals may be used as externally sourced inputs into the interrupt controller logic. Each GP bit used as an interrupt input must be shut off by setting the appropriate GPIO R/W register bit to be input. The interrupt control registers (0x00604—607) control how the GP inputs are handled. For more details, see Section 10.1 on page 90.

8.2.4 GP Diagnostic Test Point Observation

Any of the T8110L GP signals may be used to observe a predefined set of internal testpoints. Each GP bit used as a testpoint output is enabled via diagnostic register 0x00142, GP testpoint enable. Settings in this register override the GPIO R/W register and force the selected bits to be testpoint outputs (refer to Section 11.1 on page 106, and Table 90 on page 108).

9 Stream Rate Control

There are a total of 64 data streams, divided into 16 stream groups of four streams each, as shown below. The H-bus group operational frequencies are selectable between 2.048 MHz, 4.096 MHz, and 8.192 MHz. Table 70. T8110L Serial Stream Groupings

9 Stream Rate Control (continued)

9.1 H-Bus Stream Rate Control Registers

9.1.1 H-Bus Rate Registers

A—H. The upper nibble controls groups B, D, F, and H. The lower nibble controls groups A, C, E, and G.

9.2 L-Bus Stream Rate Control Registers

9.2.1 L-Bus Rate Registers

streams have a 16.384 MHz rate option (refer to Section 9.2.2 on page 86). Table 71. H-Bus Rate Registers H-bus group B(D, F, H) off (default). H-bus group B(D, F, H) rate = 2.048 MHz. H-bus group B(D, F, H) rate = 4.096 MHz. H-bus group B(D, F, H) rate = 8.192 MHz. H-bus group A(C, E, G) off (default). H-bus group A(C, E, G) rate = 2.048 MHz. H-bus group A(C, E, G) rate = 4.096 MHz. H-bus group A(C, E, G) rate = 8.192 MHz. Table 72. L-Bus Rate Registers L-bus group B(D, F, H) off (default). L-bus group B(D, F, H) rate = 2.048 MHz. L-bus group B(D, F, H) rate = 4.096 MHz. L-bus group B(D, F, H) rate = 8.192 MHz. L-bus group B(D, F, H) rate = 16.384 MHz. L-bus group A(C, E, G) off (default). L-bus group A(C, E, G) rate = 2.048 MHz. L-bus group A(C, E, G) rate = 4.096 MHz. L-bus group A(C, E, G) rate = 8.192 MHz. L-bus group A(C, E, G) rate = 16.384 MHz.

9.2 L-Bus Stream Rate Control Registers (continued)

input of the odd stream shift register (refer to Figure 17). Figure 16. Local Stream 16.384 Mbits/s Timing

16.384 MHz

Figure 17. Local Stream 16.384 Mbits/s Circuit

16.384 Mbits/s

the application can have 16 lines, all at 16.384 Mbits/s, in contrast to the 32 I/O lines at normal rates. Figure 18. Superrate I/O Configuration

tions, one for the MS-byte and the other for the LS-byte. Note: n = even number, m = integer. Figure 19. Relationship Between 8.192 Mbits/s and 16.384 Mbits/s Time Slots and programming a connection from stream n is programming a connection from the LS-byte on input pin n.

8.192 Mbits/s STREAM n, TIMESLOT m

8.192 Mbits/s STREAM n + 1, TIMESLOT m

8.192 Mbits/s INPUT DATA BITS ARE SAMPLED AT 3/4 POINT (91 ns) OF THE 122 ns BIT TIME

16.384 Mbits/s INPUT DATA BITS ARE SAMPLED AT 3/4 POINT (45 ns) OF THE 61 ns BIT TIME

10 Error Reporting and Interrupt Control

10.1 Interrupt Control Registers

10.1.1 Interrupts Via External FG[7:0] Registers

10.1.1.1 FGIO Interrupt Pending Register

Table 73. Interrupt Control Register Map Table 74. FGIO Interrupt Pending Registers No pending interrupts via FG7 (default). No pending interrupts via FG6 (default). No pending interrupts via FG5 (default). No pending interrupts via FG4 (default). No pending interrupts via FG3 (default). No pending interrupts via FG2 (default). No pending interrupts via FG1 (default). No pending interrupts via FG0 (default).

10 Error Reporting and Interrupt Control (continued)

10.1 Interrupt Control Registers (continued)

10.1.1 Interrupts Via External FG[7:0] Registers (continued)

10.1.1.1 FGIO Interrupt Pending Register (continued)

(negative edge, positive edge, low level, or high level). Table 74. FGIO Interrupt Pending Registers (continued) Disable (mask) interrupts via FG7 (default). Enable (unmask) interrupts via FG7. Disable (mask) interrupts via FG6 (default). Enable (unmask) interrupts via FG6. Disable (mask) interrupts via FG5 (default). Enable (unmask) interrupts via FG5. Disable (mask) interrupts via FG4 (default). Enable (unmask) interrupts via FG4. Disable (mask) interrupts via FG3 (default). Enable (unmask) interrupts via FG3. Disable (mask) interrupts via FG2 (default). Enable (unmask) interrupts via FG2. Disable (mask) interrupts via FG1 (default). Enable (unmask) interrupts via FG1. Disable (mask) interrupts via FG0 (default). Enable (unmask) interrupts via FG0. Table 75. FGIO Edge/Level and Polarity Registers FG7 interrupts are negative edge or low level (default). FG7 interrupts are positive edge or high level. FG6 interrupts are negative edge or low level (default). FG6 interrupts are positive edge or high level. FG5 interrupts are negative edge or low level (default). FG5 interrupts are positive edge or high level. FG4 interrupts are negative edge or low level (default). FG4 interrupts are positive edge or high level. FG3 interrupts are negative edge or low level (default). FG3 interrupts are positive edge or high level. FG2 interrupts are negative edge or low level (default). FG2 interrupts are positive edge or high level. FG1 interrupts are negative edge or low level (default). FG1 interrupts are positive edge or high level. FG0 interrupts are negative edge or low level (default). FG0 interrupts are positive edge or high level.

10.1.2 Interrupts Via External GP[7:0]

10.1.2.1 GPIO Interrupt Pending Register

Table 76. GPIO Interrupt Pending Register No pending interrupts via GP7 (default).

6 JG6OB 0

No pending interrupts via GP6 (default).

5 JG5OB 0

No pending interrupts via GP5 (default).

4 JG4OB 0

No pending interrupts via GP4 (default).

3 JG3OB 0

No pending interrupts via GP3 (default).

2 JG2OB 0

No pending interrupts via GP2 (default).

1 JG1OB 0

No pending interrupts via GP1 (default).

0 JG0OB 0

No pending interrupts via GP0 (default). Disable (mask) interrupts via GP7 (default). Enable (unmask) interrupts via GP7. Disable (mask) interrupts via GP6 (default). Enable (unmask) interrupts via GP6. Disable (mask) interrupts via GP5 (default). Enable (unmask) interrupts via GP5. Disable (mask) interrupts via GP4 (default). Enable (unmask) interrupts via GP4. Disable (mask) interrupts via GP3 (default). Enable (unmask) interrupts via GP3. Disable (mask) interrupts via GP2 (default). Enable (unmask) interrupts via GP2. Disable (mask) interrupts via GP1 (default). Enable (unmask) interrupts via GP1. Disable (mask) interrupts via GP0 (default). Enable (unmask) interrupts via GP0.

10.1.2 Interrupts Via External GP[7:0] (continued)

10.1.2.2 GPIO Edge/Level and GPIO Polarity Registers

(negative edge, positive edge, low level, or high level).

10.1.3 Interrupts Via Internal System Errors

Table 77. GPIO Edge/Level and GPIO Polarity Registers GP7 interrupts are negative edge or low level (default). GP7 interrupts are positive edge or high level. GP6 interrupts are negative edge or low level (default). GP6 interrupts are positive edge or high level. GP5 interrupts are negative edge or low level (default). GP5 interrupts are positive edge or high level. GP4 interrupts are negative edge or low level (default). GP4 interrupts are positive edge or high level. GP3 interrupts are negative edge or low level (default). GP3 interrupts are positive edge or high level. GP2 interrupts are negative edge or low level (default). GP2 interrupts are positive edge or high level. GP1 interrupts are negative edge or low level (default). GP1 interrupts are positive edge or high level. GP0 interrupts are negative edge or low level (default). GP0 interrupts are positive edge or high level. Table 78. System Error Interrupt Assignments SYS15 Clock failsafe indicator. SYS14 Clock fallback indicator.

10.1.4 System Interrupt Pending High/Low Registers

user can clear specific bits by writing 1 to that bit (write 1 to clear). Table 79. System Interrupt Pending High/Low Registers No pending interrupts via SYS7 (default). No pending interrupts via SYS6 (default). No pending interrupts via SYS5 (default). No pending interrupts via SYS4 (default). No pending interrupts via SYS3 (default). No pending interrupts via SYS2 (default). No pending interrupts via SYS1 (default). No pending interrupts via SYS0 (default). No pending interrupts via SYS15 (default). Pending interrupt via SYS15. No pending interrupts via SYS14 (default). Pending interrupt via SYS14. No pending interrupts via SYS13 (default). Pending interrupt via SYS13. No pending interrupts via SYS12 (default). Pending interrupt via SYS12. No pending interrupts via SYS11 (default). Pending interrupt via SYS11. No pending interrupts via SYS10 (default). Pending interrupt via SYS10. No pending interrupts via SYS9 (default). No pending interrupts via SYS8 (default).

10.1.5 System Interrupt Enable High/Low Registers

The system interrupt enable high/low registers allow for masking of interrupts via the internal system error signals. Table 80. System Interrupt Enable High/Low Registers

7 JS7EB 0

Disable (mask) interrupts via SYS7 (default). Enable (unmask) interrupts via SYS7.

6 JS6EB 0

Disable (mask) interrupts via SYS6 (default). Enable (unmask) interrupts via SYS6.

5 JS5EB 0

Disable (mask) interrupts via SYS5 (default). Enable (unmask) interrupts via SYS5.

4 JS4EB 0

Disable (mask) interrupts via SYS4 (default). Enable (unmask) interrupts via SYS4.

3 JS3EB 0

Disable (mask) interrupts via SYS3 (default). Enable (unmask) interrupts via SYS3.

2 JS2EB 0

Disable (mask) interrupts via SYS2 (default). Enable (unmask) interrupts via SYS2.

1 JS1EB 0

Disable (mask) interrupts via SYS1 (default). Enable (unmask) interrupts via SYS1.

0 JS0EB 0

Disable (mask) interrupts via SYS0 (default). Enable (unmask) interrupts via SYS0. Disable (mask) interrupts via SYS15 (default). Enable (unmask) interrupts via SYS15. Disable (mask) interrupts via SYS14 (default). Enable (unmask) interrupts via SYS14.

5 JSDEB 0

Disable (mask) interrupts via SYS13 (default). Enable (unmask) interrupts via SYS13.

4 JSCEB 0

Disable (mask) interrupts via SYS12 (default). Enable (unmask) interrupts via SYS12. Disable (mask) interrupts via SYS11 (default). Enable (unmask) interrupts via SYS11. Disable (mask) interrupts via SYS10 (default). Enable (unmask) interrupts via SYS10.

1 JS9EB 0

Disable (mask) interrupts via SYS9 (default). Enable (unmask) interrupts via SYS9.

0 JS8EB 0

Disable (mask) interrupts via SYS8 (default). Enable (unmask) interrupts via SYS8.

10.1.6 Interrupts Via Internal Clock Errors

Table 81. Clock Error Interrupt Assignments CLK15 Failsafe indicator—APLL1 reference error. CLK14 DPLL2 sync input error. CLK13 DPLL1 sync input error.

10.1.7 Clock Interrupt Pending High/Low Registers

Section 5.2.1 on page 40). The user can clear specific bits by writing 1 to that bit (write 1 to clear). Table 82. Clock Interrupt Pending High/Low Registers No pending interrupts via CLK7 (default). No pending interrupts via CLK6 (default). No pending interrupts via CLK5 (default). No pending interrupts via CLK4 (default). No pending interrupts via CLK3 (default). No pending interrupts via CLK2 (default). No pending interrupts via CLK1 (default). No pending interrupts via CLK0 (default). No pending interrupts via CLK15 (default). Pending interrupt via CLK15. No pending interrupts via CLK14 (default). Pending interrupt via CLK14.

5 JCDOB 0

No pending interrupts via CLK13 (default). Pending interrupt via CLK13.

4 JCCOB 0

No pending interrupts via CLK12 (default). Pending interrupt via CLK12. No pending interrupts via CLK11 (default). Pending interrupt via CLK11. No pending interrupts via CLK10 (default). Pending interrupt via CLK10. No pending interrupts via CLK9 (default). No pending interrupts via CLK8 (default).

10.1.8 Clock Interrupt Enable High/Low Registers

The clock interrupt enable high/low registers allow for masking of interrupts via the internal clock error signals. Table 83. Clock Interrupt Enable High/Low Registers Disable (mask) interrupts via CLK7 (default). Enable (unmask) interrupts via CLK7. Disable (mask) interrupts via CLK6 (default). Enable (unmask) interrupts via CLK6. Disable (mask) interrupts via CLK5 (default). Enable (unmask) interrupts via CLK5. Disable (mask) interrupts via CLK4 (default). Enable (unmask) interrupts via CLK4. Disable (mask) interrupts via CLK3 (default). Enable (unmask) interrupts via CLK3. Disable (mask) interrupts via CLK2 (default). Enable (unmask) interrupts via CLK2. Disable (mask) interrupts via CLK1 (default). Enable (unmask) interrupts via CLK1. Disable (mask) interrupts via CLK0 (default). Enable (unmask) interrupts via CLK0. Disable (mask) interrupts via CLK15 (default). Enable (unmask) interrupts via CLK15.

6 JCEEB 0

Disable (mask) interrupts via CLK14 (default). Enable (unmask) interrupts via CLK14.

5 JCDEB 0

Disable (mask) interrupts via CLK13 (default). Enable (unmask) interrupts via CLK13.

4 JCCEB 0

Disable (mask) interrupts via CLK12 (default). Enable (unmask) interrupts via CLK12.

3 JCBEB 0

Disable (mask) interrupts via CLK11 (default). Enable (unmask) interrupts via CLK11.

2 JCAEB 0

Disable (mask) interrupts via CLK10 (default). Enable (unmask) interrupts via CLK10. Disable (mask) interrupts via CLK9 (default). Enable (unmask) interrupts via CLK9. Disable (mask) interrupts via CLK8 (default). Enable (unmask) interrupts via CLK8.

10.1.9 Interrupt Servicing Registers

10.1.9.1 Arbitration Control Register

a simple logical OR of the internal clock error bits. ority encodes between the three levels. Multiple interrupts within a level are queued round-robin. rupt according to the three priority levels.

10.1.9.2 SYSERR and CLKERR Output Select Register

level, active-high pulse, or active-low pulse). low pulse). Value corresponds to the number of 32.768 MHz periods – 1. level, active-high pulse, or active-low pulse). low pulse). Value corresponds to the number of 32.768 MHz periods – 1. Table 84. Arbitration Control Register Disable interrupt controller (default). Flat structure (round-robin arbiter). Tier structure (three levels), no pre-empting. Tier structure (three levels), pre-empting.

10.1.9 Interrupt Servicing Registers (continued)

10.1.9.2 SYSERR and CLKERR Output Select Register (continued)

clock) pending bits are cleared. Table 85. SYSERR Output Select Registers SYSERR is active-high level* (default). SYSERR is active-low level*. SYSERR is active-high single pulse. SYSERR is active-low single pulse. 0x00616 SYSERR Pulse Width 7:0 JSWSR LLLL LLLL SYSERR pulse-width value. CLKERR is active-high level* (default). CLKERR is active-low level*. CLKERR is active-high single pulse. CLKERR is active-low single pulse. 0x00617 CLKERR Pulse Width 7:0 JCWSR LLLL LLLL CLKERR pulse-width value.

10.1.9.3 Interrupt In-Service Registers

48 possible interrupts is currently in-service. Table 86. Interrupt In-Service Register No interrupt in-service (default).

10.1.9.3 Interrupt In-Service Registers (continued)

48 possible interrupts is currently in-service. Table 86. Interrupt In-Service Register (continued)

10.2 Error Reporting and Interrupt Controller Circuit Operation

Figure 20. Interrupt Controller

104 Agere Systems Inc. Data Sheet February 2004Ambassador T8110L H.100/H.110 Switch

10.2 Error Reporting and Interrupt Controller Circuit Operation (continued)

10.2.1 Externally Sourced Interrupts Via FG[7:0], GP[7:0]

Up to 16 of the 48 interrupt inputs are sourced external to the T8110L, via the FG[7:0] and GP[7:0] signals. Each input is independently controlled via the interrupt control registers (refer to Section 10.1.1 on page 90 and Section 10.1.2 on page 92). Any externally sourced interrupt may be presented as active-high level, active-low level, posi- tive edge, or negative edge sense. Each external interrupt is maskable. Any detected interrupt which is unmasked is held in an interrupt pending register, and presented to the arbitration circuit for servicing.

10.2.2 Internally Sourced System Error Interrupts

Another set of 16 of the 48 interrupt inputs are sourced internally via the system error register bits (0x00126—127). Each of these inputs is independently controlled via the interrupt control registers (refer to Section 10.1.3 on page 93). All internal system error bit interrupts are presented as active-high level sense. Each system error bit interrupt is maskable. Any detected interrupt which is unmasked is held in an interrupt pending register and presented to the arbitration circuit for servicing.

10.2.3 Internally Sourced Clock Error Interrupts

Another set of 16 of the 48 interrupt inputs are sourced internally via the latched clock error register bits (0x00122—123; refer to Section 5.2.1 on page 40). Each of these inputs is independently controlled via the inter- rupt control registers (refer to Section 10.1.6 on page 96). All internal clock error bit interrupts are presented as active-high level sense. Each clock error bit interrupt is maskable. Any detected interrupt that is unmasked is held in an interrupt pending register and presented to the arbitration circuit for servicing.

10.2.4 Arbitration of Pending Interrupts

The arbitration of the pending interrupts can be handled in one of four selectable modes: arbitration off, flat arbitra- tion, tier arbitration with pre-empting disabled, and tier arbitration with pre-empting enabled. Interrupts are reported to the system via the SYSERR signal.

10.2.4.1 Arbitration Off

This mode only allows the 16 internal system error register bits to generate interrupts, and no arbitration takes place. The trigger for the SYSERR output is simply a logical OR of the internal system error register bits. All bits of the internal system error register must be cleared in order to rearm the SYSERR trigger in this mode.

10.2.4.2 Flat Arbitration

The flat arbitration mode performs a round-robin arbitrations on all 48 interrupt sources. When a pending interrupt wins the arbitration, the in-service register is loaded with its corresponding interrupt vector, SYSERR is triggered, and that pending bit is cleared, removing it from the next round-robin arbitration cycle. The system must respond to the current in-service interrupt (refer to Section 10.2.7 on page 105), after which the next arbitration cycle takes place.

10.2.4.3 Tier Arbitration

The tier arbitration creates three prioritized groups as shown below: ! Highest priority. The 16 internal latched clock error register bits. ! Next highest priority. The 16 internal system error register bits. ! Lowest priority. The 16 external FG[7:0] and GP[7:0] bits.

Agere Systems Inc. 105 Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch

10.2.4 Arbitration of Pending Interrupts (continued)

10.2.4.3 Tier Arbitration (continued)

Arbitration assigns interrupt servicing priority to the three groups. Multiple pending interrupts within the same group are arbitrated round-robin. When a pending interrupt wins the arbitration, the in-service register is loaded with its corresponding interrupt vector, SYSERR is triggered, and that pending bit is cleared, removing it from the next arbitration cycle.

10.2.4.4 Pre-Empting Disabled

With pre-empting disabled, once a pending interrupt wins the arbitration and the in-service register is loaded with its corresponding interrupt vector, new incoming pending interrupts of higher priority must wait for the system to respond to the current in-service interrupt (refer to Section 10.2.7 on page 105), at which time another arbitration cycle takes place.

10.2.4.5 Pre-Empting Enabled

With pre-empting enabled, an interrupt that is in-service (i.e., its interrupt vector is loaded in the in-service register and SYSERR has been triggered) can be overridden by new incoming pending interrupts of higher priority. The current in-service interrupt is pushed onto a stack for storage; the higher-priority interrupt vector is loaded into the in-service register and SYSERR is retriggered. Once all interrupts of higher priority have been serviced by the sys- tem (refer to Section 10.2.7 on page 105), the stack is popped and the original lower-priority interrupt is reissued.

10.2.5 CLKERR Output

The CLKERR output signal is used to indicate any internal clocking errors. The trigger for the CLKERR output is simply a logical OR of the internal latched clock error register bits. All bits of the internal clock error register must be cleared in order to rearm the CLKERR trigger. The CLKERR trigger induces a state machine to generate the CLKERR signal in one of four possible ways: active-high level, active-low level, active-high single pulse, or active- low single pulse.

10.2.6 SYSERR Output

The T8110L SYSERR output signal is used to report interrupts. Internally, the arbitration circuit provides a SYSERR trigger, which induces a state machine to generate the SYSERR signal in one of four possible ways: active-high level, active-low level, active-high single pulse, or active-low single pulse.

10.2.7 System Handling of Interrupts

The T8110L interrupt controller presents an interrupt to the system by triggering the SYSERR output and providing a predefined interrupt vector value at the interrupt in-service register (ISR). The system may acknowledge the interrupt in three ways as shown below: ! System reads the T8110L ISR register. This allows the arbiter to advance, and if more pending interrupts are active, reloads the ISR with the winner of the arbitration and retriggers SYSERR. ! System clears the T8110L ISR register (via register 0x00100, soft reset; write 0x20 clears the ISR). The arbiter advances, and if more pending interrupts are active, reloads the ISR and retriggers SYSERR. ! System resets the interrupt controller (via register 0x00100, soft reset, write 0x10 clears the ISR and all the pending interrupt registers). All pending interrupts are cleared, and the arbiter is reset.

11 Test and Diagnostics

11.1 Diagnostics Control Registers

The diagnostic control registers allow for various diagnostic modes (refer to Section 11.2 on page 112).

11.1.1 FG Testpoint Enable Register

or FGIO) or as testpoint outputs. FG testpoint select controls the MUX selection for which testpoints are selected. Refer to Table 89 on page 107 for testpoint assignments for each FG bit. Table 87. Diagnostics Control Register Map Table 88. FG Testpoint Enable Registers

7 FT7EB 0

FG7 is standard FG or FGIO bit (default).

6 FT6EB 0

FG6 is standard FG or FGIO bit (default).

5 FT5EB 0

FG5 is standard FG or FGIO bit (default).

4 FT4EB 0

FG4 is standard FG or FGIO bit (default).

3 FT3EB 0

FG3 is standard FG or FGIO bit (default).

2 FT2EB 0

FG2 is standard FG or FGIO bit (default).

1 FT1EB 0

FG1 is standard FG or FGIO bit (default).

0 FT0EB 0

FG0 is standard FG or FGIO bit (default).

11 Test and Diagnostics (continued)

11.1 Diagnostics Control Registers (continued)

11.1.1 FG Testpoint Enable Register (continued)

Table 89. FG[7:0] Internal Testpoint Assignments

11.1.2 GP Testpoint Enable Register

GPIO) or as testpoint outputs. GP testpoint select controls the MUX selection for which testpoints are selected. Refer to Table 91 on page 109 for testpoint assignments for each GP bit. Table 90. Testpoint Enable Registers GP7 is standard GPIO bit (default). GP6 is standard GPIO bit (default). GP5 is standard GPIO bit (default). GP4 is standard GPIO bit (default). GP3 is standard GPIO bit (default). GP2 is standard GPIO bit (default). GP1 is standard GPIO bit (default). GP0 is standard GPIO bit (default).

11.1.2 GP Testpoint Enable Register (continued)

Table 91. GP[7:0] Internal Testpoint Assignments

8 MHz tap

4 MHz tap

2 MHz tap

11.1.3 State Counter Modes Registers

modulo function. For more details, refer to Section 11.2 on page 112.

11.1.4 Miscellaneous Diagnostics Low Register

ers. Bit 0 controls the TST input of the power-on reset cell. Table 92. State Counter Modes Registers 7:6 Reserved 00 NOP (default). Normal carry chain operation (default). Break state counter carry chains. Normal internal frame operation (default). Use /FR_COMP as internal frame. State counter modulo counting. Table 93. Miscellaneous Diagnostics Low Register 7:3 Reserved 00 NOP (default).

2 FB2SB 0

APLL2 feedback divider reset inactive (default). APLL2 feedback divider reset active.

1 FB1SB 0

APLL1 feedback divider reset inactive (default). APLL1 feedback divider reset active.

0 Reserved — —

11.1.5 Miscellaneous Diagnostic Registers

Table 94. Miscellaneous Diagnostic Registers 0x00147 Diag7 7:0 Reserved — NOP. Interrupt controller, normal mode (default). Interrupt controller, DIAG mode. 5:4 ICKLP LL DIAG mode, force CLK[1:0] errors. 3:2 ISYLP LL DIAG mode, force SYS[1:0] errors. 1:0 IEXLP LL DIAG mode, force EXT[8, 0] errors. Disable delay mode (default).

112 Agere Systems Inc. Data Sheet February 2004Ambassador T8110L H.100/H.110 Switch

11.2 Diagnostic Circuit Operation

The T8110L internal diagnostic modes are intended primarily for chip manufacturing test. The diagnostic functions include the following: ! DIAG0—3, observability of internal testpoints via FG(7:0), GP(7:0): — Internal testpoints are brought to chip I/O at FG and GP signals. Refer to Table 89 on page 107 and Table 91 on page 109 for testpoint assignment. ! DIAG4—5, internal state counter diagnostic modes: — Break counter carry chains—this is used in conjunction with monitoring of the state counter bits at FG and GP, and breaks the 11-bit state counter into three separate pieces (bits [10:8], [7:4] and [3:0]). — Shorten frame operation—the internally generated 8 kHz frame is bypassed in favor of the /FR_COMP input. The /FR_COMP input still denotes the frame center and may be presented at a higher frequency than 8 kHz. This is used in conjunction with the state counter modulo function, which when properly programmed allows the internal state counter to roll over coincident with the /FR_COMP frame center. ! DIAG6, forced RESET of analog APLL1 feedback dividers: — The APLL1 feedback dividers are typically not reset. This diagnostic mode allows each feedback divider to be held in a reset state. ! DIAG7, reserved. ! DIAG8, interrupt controller diagnostics: — When the diagnostic mode is enabled (DIAG8 register, bits 7:6 = 01), then bits 5:4 override the CLK error[1:0] inputs, bits [3:2] override the SYS error[1:0] inputs, bit 1 overrides the GP[0] input, and bit 0 overrides the FG[0] input to the interrupt controller. This allows for direct manipulation to set/clear a portion of interrupt bits from each tier group. Please see Section 10.2 on page 103 for more details. ! DIAG9, interrupt controller deassertion delay: — Allows a programmable deassertion time for the SYSERR signal in between back-to-back interrupts. ! DIAG10—11, sync-to-frame command delay: — Allows a programmable delay time from the FRAME boundary for execution of the sync-to-frame clock com- mands, GO_CLOCKS, CLEAR_FALLBACK, FORCE_FALLBACK.

12 Connection Control

12.1 Programming Interface

12.1.1 Connection Memory Programming

(or upper word) to actually move data into the connection memory; refer to Table 95. nection memory locations are addressed relative to time slot and stream. ! MAKE/BREAK/QUERY, telephony connection (see Figure 22 on page 114). is presented as multiple microprocessor read cycles; refer to Table 95. Note:Data byte n required information is shown in Figure 22. Table 95. Microprocessor Programming, Connection Memory Access nection memory, or read data byte 3 information. data bytes 1 and 0 information.

12 Connection Control (continued)

12.1 Programming Interface (continued)

12.1.1 Connection Memory Programming (continued)

Figure 21. Microprocessor Programming—Reset Page Command Figure 22. Microprocessor Programming—Make/Break/Query Telephony Connections

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12.2 Switching Operation

The basic building block of switching is one-half simplex connections loaded into the connection memory. Each connection memory location controls data flow, either from a serial stream input to a location in data memory, or from data memory to a serial stream output. A typical telephony simplex switch connection would use one from and one to connection, each using the same data memory location.

12.2.1 Memory Architecture and Configuration

12.2.1.1 Connection Memory

The T8110L connection memory consists of 8192 locations, one location for each of the possible stream/time-slot combinations, to provide a full nonblocking switch for up to 128 time slots on 32 H1x0 streams (CT_D[31:0]) and 32 local streams (L_D[31:0]). Connection memory is physically addressed by time slot (7 bits), H1x0/local select (1 bit), and stream (5 bits). The 8192 locations are divided into four pages of 2048, with each page dedicated to a set of 16 serial streams as follows: ! H1x0 even streams (CT_D[30, 28, . . . 0]) ! H1x0 odd streams (CT_D[31, 29, . . . 1]) ! Local high streams (L_D[31:16]) ! Local low streams (L_D[15:0]) Each of these connection memory pages are initialized at reset (valid bit entries are reset to invalid). Additionally, each page may be initialized individually via software command, RESET PAGE (refer to Figure 21 on page 114). Connection memory locations contain the following control information: ! VALID bit indicates that a valid switch connection exists for this stream/time slot. ! RWS indicates whether the connection is from (from serial stream to data memory) or to (from DATA memory to serial stream). ! VFC (virtual framing control) controls which data page is used in double-buffer scenarios. Note: There are two data memory configurations that allow double-buffering of the data, in order to create con- ! PME indicates a pattern mode connection. ! TAG is the data memory location used for this one-half simplex switch connection (or the data pattern sent to serial output for pattern mode connections). ! SUBRATE information is subrate switching control (bitswap).

12.2 Switching Operation (continued)

12.2.1 Memory Architecture and Configuration (continued)

12.2.1.2 Data Memory

memory mode select register (0x00105; refer to Section 5.1.3 on page 32). Figure 23. T8110L Data Memory Map and Configurations

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12.2.2 Standard Switching

Standard telephony switching is achieved by loading control fields into the connection memory for one-half simplex connections (refer to Figure 22 on page 114, and Section 12.2.1.1 on page 115).

12.2.2.1 Constant Delay and Minimum Delay Connections

The VFC control bit in connection memory determines which of two data pages is accessed, when the data mem- ory is configured to double-buffering for telephony connections (refer to Figure 23). This bit always affects to con- nections (read the data memory, send it out to a serial stream output) in a double-buffer configuration. This bit can control a from connection in a double-buffer configuration, only if it is a subrate connection; otherwise, the VFC bit has no bearing on from connections. The double-buffering configuration creates two data pages. During a particular frame (125 µs time boundary, parti- tioned into time slots), one page is the active page, the other is the inactive page. The active/inactive page status toggles at every frame boundary. For all from connections (except for subrate connections), incoming serial data is always written to the active page. For all to connections, the VFC control bit indicates whether to read from the active or inactive page. Manipulation of this bit affects the latency between the incoming from data and the outgo- ing to data. This latency defines whether or not a connection is constant delay or minimum delay. Please see Appendix A on page 139 for more details on constant and minimum delay connections.

12.2.2.2 Pattern Mode

The PME control bit in connection memory affects only to connections. Instead of reading a value out of the data memory for subsequent output to a serial stream, the lower 8 bits of the TAG field provide a byte pattern for the serial output.

12.2.2.3 Subrate

The subrate control bit field in connection memory is used only by from connections and controls how individual bits or groups of bits of an incoming serial byte are shuffled prior to writing them to the data memory, in order to achieve subrate switching.

12.2.2 Standard Switching (continued)

12.2.2.1 Subrate (continued)

TDM stream bit rate. A particular channel occurs once every 8 kHz frame, and there are 8K frames per second. This allows for a channel data propagation rate of (8 bits/frame * 8K frames/s = 64 kbits/s). Refer to Figure 24 and Table 97. Figure 24. TDM Data Stream Bit Rates channel capacity for a given time slot. Refer to Table 96 and Table 97. Bit subrate = 8 channels per time slot, 1 bit per channel. Di-bit = 4 channels per time slot, 2 bits per channel. Nibble subrate = 2 channels per time slot, 4 bits per channel. Byte (no subrate) = 1 channel per time slot, 8 bits per channel. Table 96. TDM Data Stream

64 TIME SLOTS (CHANNELS) PER FRAME

32 TIME SLOTS (CHANNELS) PER FRAME

8 Mbits/s

4 Mbits/s

2 Mbits/s

128 TIME SLOTS (CHANNELS) PER FRAME

data, from and to (refer to Figure 22 on page 114, and Table 98). Table 97. Subrate Switching, Data Propagation Rate vs. Channel Capacity

a byte that will be output as defined by the to connection. Figure 25. This example shows the packing of four separate incoming di-bits from four different channels into one outgoing byte on one channel. Note:Please note the limitation that multiple di-bits from the same time slot cannot be switched simultaneously. This would require the byte of that time slot to be unpacked first, which is discussed in Section on page 122. Table 98. Subrate Switching, Connection Memory Programming Setup

! From stream a, time slot n, bits[1:0] to stream e, time slot n + 10, bits[7:6]. ! From stream b, time slot n + 1, bits[1:0] to stream e, time slot n + 10, bits[3:2]. ! From stream c, time slot n + 2, bits[3:2] to stream e, time slot n + 10, bits[1:0]. ! From stream d, time slot n + 3, bits[5:4] to stream e, time slot n + 10, bits[5:4]. Five 1/2 simplex connections are required to pack four incoming di-bits into an outgoing byte. ! From stream a, time slot n. Connection memory subrate field = 0100X11. ! From stream b, time slot n + 1. Connection memory subrate field = 0100X01. ! From stream c, time slot n + 2. Connection memory subrate field = 0101X00. ! From stream d, time slot n + 3. Connection memory subrate field = 0110X10. ! To stream e, time slot n + 10. Connection memory subrate field is don't care. Figure 25. Subrate Switching Example, Byte Packing

122 Agere Systems Inc. Data Sheet February 2004Ambassador T8110L H.100/H.110 Switch Subrate Unpacking of Incoming Bytes Because the H1x0 bus and the local stream bus are based on byte-oriented TDM data streams, and the T8110L architecture is geared towards standard byte switching, it is not possible to simultaneously switch subrate portions of a single byte to different places. This limitation is overcome by application. To gain access to each subrate piece contained in one incoming byte, that byte must be broadcast onto additional channels, one channel for each sub- rate piece required. The means of broadcasting is up to the application—either the source device of the packed subrate byte can broadcast it, or the device receiving that byte can broadcast it over unused channels and loop the broadcast bytes back in. The example from Figure 25 is extended in Figure 26. This example shows the unpacking of the packed byte created in Figure 25, output to four different channels.

From stream e, time slot n + 3, bits[1:0] to stream j, time slot n + 8, bits[7:6]. From stream f, time slot n + 5, bits[3:2] to stream i, time slot n + 8, bits[5:4]. From stream f, time slot n + 6, bits[5:4] to stream h, time slot n + 8, bits[1:0]. From stream f, time slot n + 7, bits[7:6] to stream g, time slot n + 8, bits[7:6]. Eight 1/2 simplex connections are required to unpack one incoming byte to four separate outgoing di-bits. From stream e, time slot n + 3. Connection memory subrate field = 0100X11. From stream f, time slot n + 5. Connection memory subrate field = 0101X10. From stream f, time slot n + 6. Connection memory subrate field = 0110X00. From stream f, time slot n + 7. Connection memory subrate field = 0111X11. To stream g, time slot n + 8. Connection memory subrate field is don't care. To stream h, time slot n + 8. Connection memory subrate field is don't care. To stream i, time slot n + 8. Connection memory subrate field is don't care. To stream j, time slot n + 8. Connection memory subrate field is don't care. Figure 26. Subrate Switching Example, Byte Unpacking

4 X X

3 X X X

13.1 Absolute Maximum Ratings

periods can adversely affect device reliability.

13.1.1 Handling Precautions

13.2 Crystal Specifications

13.2.1 XTAL1 Crystal

5% capacitors must be connected from XTAL1_IN and XTAL1_OUT to Vss, as shown in the diagram below. bus. Otherwise, a crystal with a lesser tolerance can be used. The crystal specifications are shown below. Table 99. Absolute Maximum Ratings Table 100. XTAL1 Specifications

13.2 Crystal Specifications (continued)

13.2.1 XTAL1 Crystal (continued)

If an oscillator is used (see Section 6.4.4 on page 61), the signal has to be connected to the XTAL1_IN pin. oscillator must meet the requirements shown below.

13.2.2 XTAL2 Crystal

with a lesser tolerance can be used (see Table 121). DD and XTAL2_OUT should be left unconnected.

• 120 Ω maximum for 6.176 MHz crystal.

† 24 pF for 6.176 MHz crystal also. ‡ 18 pF for 6.176 MHz crystal also. If an oscillator is used (see Section 6.5.1 on page 63), the signal has to be connected to the XTAL2_IN pin. oscillator must meet the requirements shown below. Table 101. 16.384 MHz Oscillator Requirements Table 102. XTAL2 Specifications Table 103. 6.176 MHz/12.352 MHz Oscillator Requirements

1 MΩT8110L

12.352 MHz

13.2.3 Reset Pulse

13.3 Thermal Parameters (Definitions and Values)

system designer to thermally design and integrate their systems. paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow. Table 104. Reset Pulse

13.3 Thermal Parameters (Definitions and Values) (continued)

die out of the package through the leads or balls by lowering the board temperature and insulating the package top.

13.4 Reliability

1 FIT = 1 Failure/1x10e

Table 105. Thermal Parameter Values Table 106. Reliability Data

13.5.1 Electrical Drive Specifications, CT_C8 and /CT_FRAME

VDD = 3.3 V and VSS = 0.0 V, unless otherwise specified. CT_C8 and /CT_FRAME signals, though this is not explicitly stated as a part of the H.1x0 specification. Table 107. Electrical Drive Specifications, CT_C8 and /CT_FRAME

13.5.2 All Other Pins

VDD = 3.3 V and Vss = 0.0 V, unless otherwise specified.

13.6 H-Bus Timing

13.6.1 Timing Diagrams

Figure 27. Clock Alignment Table 108. dc Electrical Characteristics, All Other Pins

13.6 H-Bus Timing (continued)

13.6.1 Timing Diagrams (continued)

Note: Bit 1 is the MSB and Bit 8 is the LSB. MSB is always transmitted first in all transfers. Figure 28. Frame Timing Diagram Figure 29. Detailed Clock Skew Timing Diagram

13.7.1 Skew Timing, H-Bus

† Assumes A and B masters in adjacent slots. skew of 30 ns will occur during that clock cycle. generating CT_C8 to have different time constants when acting as primary and secondary clock masters. Table 109. Skew Timing, H-Bus

13.7.1 Skew Timing, H-Bus (continued)

• Worst-case loading of 50 pF on all outputs.

13.8 Hot Swap

swap applications. The circuit that generates the 0.7 V precharge voltage must also be powered from early power. ® Hot Swap specifications for hot swap requirements.

13.8.1 LPUE (Local Pull-Up Enable)

LD[31:0], LREF[7:0], PRI_REF_IN, NR1_DIV_IN, and NR2_DIV_IN.

13.9 Decoupling

in addition to the 0.1 µF capacitors to provide additional decoupling. Table 110. L_SC[3:0] and Frame Group Rise and Fall Time

13.10 APLL VDD Filter

Figure 30. APLL VDD Filtering

13.11 PC Board PBGA Considerations

with applicable specifications for any PC board requirements.

13.12 Unused Pins

Multiple pins may share a common resistor. Signals with pull-up/down resistors may be left unconnected if unused.

13.13 External Pull-Up Pins

mended that all EPU pins be tied to a commmon 20 kΩ pull-up resistor.

13.14 T8110L Evaluation Kits

13.15 T8110L Ordering Information

Table 111. T8110L Ordering Information

13.15 Pin and Pad Assignments (continued)

Figure 31. T8110L Pins by Functional Group

Agere Systems Inc. 135 Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch A B C D E F G H J K L M Y N P R T U V W 12345678910 1820 19 SPACES @ 1.27 = 24.13

19 SPACES

@ 1.27 = 24.13 0.76 +0.14 –0.16 A1 BALL PAD CORNER

136 Agere Systems Inc. Data Sheet February 2004Ambassador T8110L H.100/H.110 Switch 1.17 ± 0.05 SEATING PLANE SOLDER BALL0.60 ± 0.10 0.20 0.36 +0.04 –0.06 2.13 +0.19 –0.21 27.00 24.00 +0.70 –0.50 24.00 +0.70 –0.50A1 BALL PAD CORNER 27.00

14 JTAG/Boundary Scan

14.1 The Principle of Boundary-Scan Architecture

referred to as output cells. Input and output is relative to the core logic of the device. Figure 32. IEEE boundary-scan register (boundary scan). ! A finite-state machine TAP controller with inputs TCK and TMS. ! An n-bit (n = 3) instruction register (IR), holding the current instruction. ! A 1-bit bypass register (BYPASS).

14 JTAG/Boundary Scan (continued)

14.1.1 Instruction Register

The instruction register is 3 bits long and the capture value is 001.

14.2 Boundary-Scan Register

ground. Please refer to the T8110 datasheet for the bit-to-pin assignment. Table 112. Instruction Register EXTEST 000 Places the boundary-scan register in EXTEST mode. SAMPLE 001 Places the boundary-scan register in sample mode. IDCODE 101 Identification code. BYPASS 110, 111 Places the bypass register in the scan chain. HIGH Z 010 Places all outputs and I/Os in 3-state mode.

Agere Systems Inc. 139 Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch Appendix A. Constant and Minimum Delay Connections A.1 Connection Definitions A forward connection is defined as one in which the output to time slot has a greater value than the input from time slot, or, put another way, the delta between them is positive. A reverse connection is defined as one in which the output to time slot has a lesser value than the input from time slot, and the delta between them is negative. For example, going from TS(1) to TS(38) is a forward connection, and the TS∆ is +37, but going from TS(38) to TS(1) is a reverse connection, with a TS∆ of –37: where TS∆ = TS(to) – TS(from). Similarly, a delta can be introduced for streams which will have a bearing in certain exceptions (discussed later): STR ∆ = STR(to) – STR(from). There is only one combination which forms a TS∆ of +127 or –127: TS ∆ = TS(127) – TS(0) = +127, and but there are two combinations which form TS∆s of +126 or –126: TS ∆ = TS(127) – TS(1) = TS(126) – TS(0) = +126, and there are three combinations which yield +125 or –125, and so on. The user can utilize the TS∆ to control the latency of the resulting connection. In some cases, the latency must be minimized. In other cases, such as a block of connections which must maintain some relative integrity while cross- ing a frame boundary, the required latency of some of the connections may exceed a one frame (>128 time slots) to maintain the integrity of this virtual frame. The device uses a control bit at each connection memory location, VFC, for controlling latency, allowing each con- nection to select one of two alternating data buffers. A.2 Delay Type Definitions Constant Delay—This is a well-defined, predictable, and linear region of latency in which the to time slot is at least 128 time slots after the from time slot, but no more than 256 time slots after the from time slot. Mathematically, constant delay latency is described as follows*, with L denoting latency, and VFC set to the value indicated: Forward connections, VFC = 1: L = 128 + TS∆ (0 ≤ TS∆ ≤ 127) Reverse connections, VFC = 0: L = 256 + TS∆ (–127 ≤ TS∆ ≤ –1) Example: Switching from TS(37) to TS(1) as a constant delay, the delta is –36, so FME is set to 0 and the result- ing latency is 256 – 36 = 220 time slots. Thus, the connection will be made from TS(37) of frame(n) to TS(1) of frame(n + 2). Simple summary: Use constant delay for latencies of 128 to 256 time slots, set VFC = 1 for forward connections, set VFC = 0 for reverse connections. * Since TS∆ = TS(to) –TS(from), the user can modify the equations to solve for either TS(to) or TS(from).

Figure 33. Constant Delay Connection Latency time slot. Exceptions exist at TS∆s of +1, +2, –126, and –127. Forward connections, VFC = 0: L = TS∆ (3 ≤ TS∆ ≤ 127). set VFC = 1 for reverse connections. because the to and from streams have been irrelevant in the switching process. two frames due to the interaction of the intrinsic pipeline delays with the double buffering.

been included in the diagram, connected to the main function by dashed lines. Figure 34. Minimum Delay Connection Latency larly, multiply values by four to convert 2.048 Mbits/s values. The latency equations can then be applied directly. Table 113. Special Cases (Exceptions)

142 Agere Systems Inc. Data Sheet February 2004Ambassador T8110L H.100/H.110 Switch Appendix B. Register Bit Field Mnemonic Summary Key to using the table below: ! Five character alphanumeric designation ! Character 4 indicates the general register type as follows: — Divide = load value for divider — Enable = bit or bits to enable a function — Load = load value, typically for counter — Output = output only — Select = bit or bits select multiple functions ! Character 5 indicates the size as follows: — B = bit — N = nibble — P = partial register (2, 3, 5, 6, or 7 bits) — R = register ! Position column identifies the bit position in the register: — 0, 1, 2, 3, 4, 5, 6, 7 for bits — L for lower nibble — U for upper nibble — n-m for bit positions in a partial register

Table 114. Mnemonic Summary, Sorted by Name

Table 114. Mnemonic Summary, Sorted by Name (continued)

Table 115. Mnemonic Summary, Sorted by Register

Table 115. Mnemonic Summary, Sorted by Register (continued)

Changes that were made to this document (since Revision 3) are listed below. Table 116. Changes page 11 Added PEN, TESTMODE Interface Signals to Table 6. page 17 Added PEN, TESTMODE pins to Table 8. page 126 Added Thermal Parameters definitions and values. page 133 Removed signals listed as no connects. page 141 Changed boundary of Constant Delay Rev Connections.

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