T8110

T8110 AGERE | Alldatasheet

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Ambassador ® T8110 Version History Introduction The purpose of this advisory is to provide information on the different versions of the Ambassador T8110. T8110 Version 1 Models of the T8110 V1 had two device issues. The two device issues only affect the microprocessor interface and packet switching capabilities. The T8110 V1 can function as a 4096 connection standard telephony switch when using the PCI interface. Issue 1: Microprocessor interface: The RDY(DTACKn) signal can oscillate if the microprocessor device driving the microprocessor interface does not relinquish its RDn (or WRn) signal within one

65 MHz clock cycle after the reassertion of RDY (

Intel® mode) or deassertion of DTACKn (Motorola® mode). Workaround: The processor or board-level component driving the microprocessor port must deassert RDn or WRn immediately (within 15 ns) upon reassertion of RDY . Issue 2: Packet switch malfunction: The T8110 does not disable its upper byte lanes on the descriptor table update, resulting in an over-write of descriptor table data. The descriptor table update occurs as the last phase of a PCI Master PUSH & PULL cycle. This results in virtual channel connection malfunctions. TDM switching is unaffected. Workaround: A systemic workaround for the user is to keep a shadow table for the UOR portion of the descriptor table. T8110 version 1 models can be identified by the markings on the device or by reading the version ID register. If the last line of the device markings is a 7 digit number followed by no version number, then the device is a ver- sion 1. Reading the version ID register 0x00128 will read back a value of 01h, indicating the device is version Samples of version 1 are no longer available (version 2 samples are now available). T8110 Version 2 Models of the T8110 V2 have one device issue. The device issue only affects the packet switching capabilities. The T8110 V2 can function as a 4096 connection standard telephony switch when using either PCI or micro- processor interface. Issue 1 (from version 1): Fixed. The microprocessor interface issue has been resolved. Issue 2 (from version 1): Will be fixed in version 3. T8110 version 2 models can be identified by the markings on the device or by reading the version ID register. If the last line of the device markings is a 7 digit number followed by V2, then the device is a version 2. Reading the version ID register 0x00128 will read back a value of 02h, indicating the device is a version 2. Samples of version 2 are currently available. For additional information, contact your local FAE (field application engineer), or call 1-800-372-2447.

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Copyright © 2001 Agere Systems Inc. All Rights Reserved September 2001 AY01-038CTI (Replaces AY01-021CTI and must accompany DS00-434CTI) For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045 Intel is a registered trademark of Intel Corporation. Motorola is a registered trademark of Motorola, Inc.

1 Introduction

for non-PCI devices is provided through a minibridge.

1.1 Features

Figure 1. Basic Application of the T8110 as a CT

• Motorola is a registered trademark of Motorola, Inc.

† Intel is a registered trademark of Intel Corporation. ‡ CompactPCI is a registered trademark of the PCI Industrial Computer Manufacturers Group.

2 Agere Systems Inc. Data Sheet May 2001and Packet Payload Engine Ambassador T8110 PCI-Based H.100/H.110 Switch

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15.9 APLL V

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2 Pin Description

2.1 Interface Signals

• Intel is a registered trademark of Intel Corporation.

† Motorola is a registered trademark of Motorola, Inc. Table 1. Interface Signals PCI_AD I/O 32 PCI bus address/data. PCI_CBE# I/O 4 PCI bus command/byte enable. PCI_CLK In 1 PCI bus clock (33 MHz). PCI_DEVSEL# I/O 1 PCI bus device select. PCI_FRAME# I/O 1 PCI bus cycle frame. PCI_GNT# In 1 PCI bus grant. PCI_IDSEL In 1 PCI bus initialization device select. PCI_INTA# Out 1 PCI bus interrupt. PCI_IRDY# I/O 1 PCI bus initiator ready. PCI_LOCK# In 1 PCI bus lock. PCI_PAR I/O 1 PCI bus parity. PCI_PERR# I/O 1 PCI bus parity error. PCI_REQ# Out 1 PCI bus request. PCI_RST# In 1 PCI bus reset. PCI_SERR# Out 1 PCI bus system error. PCI_STOP# I/O 1 PCI bus stop. PCI_TRDY# I/O 1 PCI bus target ready. Table 2. Minibridge Interface Signals MB_A I/O 16 Address[15:0] out. MB_D I/O 16 Data bus I/O. Data bus in/out. MB_RD I/O 1 Read strobe output. RDn(DSn) in. MB_WR I/O 1 Write strobe output. WRn(R/Wn) in. MB_CS0 I/O 1 Chip select 0 output. Address[16] in. MB_CS1 I/O 1 Chip select 1 output. Address[17] in. MB_CS2 I/O 1 Chip select 2 output. Address[18] in. MB_CS3 I/O 1 Chip select 3 output. Address[19] in. MB_CS4 I/O 1 Chip select 4 output. CSn in. MB_CS5 I/O 1 Chip select 5 output. Word/byte select in. MB_CS6 Out 1 Chip select 6 output. RDY(DTACKn) out. MB_CS7 I/O 1 Chip select 7 output.

2 Pin Description (continued)

• MVIP is a trademark of Natural MicroSystems Corporation.

Table 3. H-Bus (H.100/H.110 Interface) Signals CT_D, CT_NETREF1, CT_NETREF2. CT_NETREF2, CT_C8_A, CT_C8_B, /CT_FRAME_A, /CT_FRAME_B. /CT_FRAME_A I/O 1 H.100/H.110 frame reference A. /CT_FRAME_B I/O 1 H.100/H.110 frame reference B. CT_NETREF1 I/O 1 H.100/H.110 network reference 1. CT_NETREF2 I/O 1 H.100/H.110 network reference 2. MVIP * compatibility clock (16.384 MHz, differential). /C16– I/O 1 H- MVIP compatibility clock (16.384 MHz, differential). /C4 I/O 1 MVIP compatibility clock (4.096 MHz). C2 I/O 1 MVIP compatibility clock (2.048 MHz). SCLK I/O 1 SC-bus compatibility clock. /SCLKx2 I/O 1 SC-bus compatibility clock. /FR_COMP I/O 1 Compatibility frame reference. Table 4. L-Bus (Local) Interface Signals L_SC Out 4 Local bus clock outputs. FG I/O 8 Local frame groups. Table 5. Clock Circuit Interface Signals XTAL1_IN In 1 Crystal oscillator #1 input (16.384 MHz). XTAL1_OUT Out 1 Crystal oscillator #1 feedback. XTAL2_IN In 1 Crystal oscillator #2 input (6.176 MHz or 12.352 MHz). XTAL2_OUT Out 1 Crystal oscillator #2 feedback.

LREF In 8 Local clock reference inputs. TCLK_OUT Out 1 Internal chip clock output. PRI_REF_OUT Out 1 Main divider reference out for CLAD/DJAT. PRI_REF_IN In 1 CLAD/DJAT reference in for APLL1. NR1_SEL_OUT Out 1 CT_NETREF1 selection out for CLAD/DJAT. NR1_DIV_IN In 1 CLAD/DJAT reference in for CT_NETREF1 divider. NR2_SEL_OUT Out 1 CT_NETREF2 selection out for CLAD/DJAT. NR2_DIV_IN In 1 CLAD/DJAT reference in for CT_NETREF2 divider. Table 6. GPIO Interface Signals GP0 I/O 1 GPIO bit 0 I/O A-master indicator out. GP1 I/O 1 GPIO bit 1 I/O B-master indicator out. GP2 I/O 1 GPIO bit 2 I/O Forwarded PCI_RST# out. Table 7. Miscellaneous Interface Signals SYSERR Out 1 System error indicator. CLKERR Out 1 Clocking error indicator. EE_CS Out 1 EEPROM chip select. Table 8. JTAG Signals Table 5. Clock Circuit Interface Signals (continued)

2.2 T8110 Pinout Information

pull-up/pull-down information. /c110 20 kΩ down—20 kΩ pull-down resistor is always in-circuit. /c110 50 kΩ up—50 kΩ pull-up resistor is always in-circuit. /c110 LPUE: 50 kΩ up—when LPUE = 1, a 50 kΩ pull-up resistor is in-circuit. Table 9. T8110 Pinouts

Table 9. T8110 Pinouts (continued)

A20 No connects must be left unconnected.

2.3 Special Buffer Requirements

2.3.1 H1x0 Bus Signal Internal Pull-Up/Pull-Down

CT_C8_B, /CT_FRAME_A, and /CT_FRAME_B signals. Note: The two H1x0 enables are active-high. Only one or the other should ever be asserted. Warning: Do not assert both at the same time. Please refer to Figure 2 for more detail. Figure 2. T8110 Pull-Up/Pull-Down Arrangement for H1x0 Pins

2.3.2 Local Bus Signal Internal Pull-Up

MB_D[15:0], LD[31:0], LREF[7:0], PRI_REF_IN, NR1_DIV_IN, and NR2_DIV_IN.

3 Main Architectural Features

3.1 T8110 Architecture

Section 4 on page 22) and microprocessor (see Section 5 on page 38). these accesses to external devices connected to this port; see Section 11, starting on page 107. minibridge port is used as the microprocessor bus port, and the PCI interface is ignored. Figure 3. T8110 Block Diagram

3 Main Architectural Features (continued)

Figure 4. T8110 Architecture 1—PCI Bus Interface

65.536 MHz

32.768 MHz

16.384 MHz

6.176 MHz

12.352 MHz

Figure 5. T8110 Architecture 2—Microprocessor Bus Interface

16.348 MHz

4 PCI Interface

signal (either pulled high or pulled low). /c110 VIO/µP_SELECT tied to GND = T8110 interface to a microprocessor bus, connected via the minibridge port. /c110 VIO/µP_SELECT tied to 3.3 V = T8110 interface to a local PCI bus, 3.3 V signaling. /c110 VIO/µP_SELECT tied to 5 V = T8110 interface to a local PCI bus, 5 V signaling. nal, non-PCI devices connected to this port. For more details, see Section 11, starting on page 107. to and from the PCI bus as well.

4.1 Target

while the lower 20 provide addressing for the internal regions of the T8110, as shown in Table 10. Table 10. T8110 Memory Mapping to PCI Space

4 PCI Interface (continued)

4.1.1 PCI Interface Registers

Table 11. PCI Interface Registers Map

Table 11. PCI Interface Registers Map (continued)

All memory writes get posted to the T8110. Turnaround time for a single cycle write is three PCI clocks. Figure 6. T8110 PCI Interface—Single Write Cycle

All memory writes get posted to the T8110. Turnaround time for the first data phase write is three PCI clocks. PCI core write FIFO depth = 8, so up to 8 data words can immediately get posted. PCI_TRDY# will remain active. case, the PCI_TRDY# signal is deasserted while the application side catches up. Figure 7. T8110 PCI Interface—Burst Write Cycle the PCI clock and application clock domains. Initial target latency is typically between 10—12 PCI clock cycles. Figure 8. T8110 PCI Interface—Single Read Cycle

the PCI clock and application clock domains. Initial target latency is typically between 10—12 PCI clock cycles. PCI core read FIFO depth = 8. read data is returned as quickly as the PCI bus can accept it. case, the PCI_TRDY# signal is deasserted while the application side catches up. Figure 9. T8110 PCI Interface—Burst Read Cycle clock and application clock domains. Initial target latency for a RETRY is typically between 8—10 PCI clock cycles. Figure 10. T8110 PCI Interface—Delayed Read Cycle (Retry)

10 TO 12 CLOCKS (TYPICAL)

Turnaround time for memory read target ABORT is 4 PCI clocks. Figure 11. T8110 PCI Interface—Target Abort (Address Parity Error)

Agere Systems Inc. 29 Data Sheet May 2001 and Packet Payload Engine Ambassador T8110 PCI-Based H.100/H.110 Switch

4.1.2 Register Space Target Access

The T8110 registers are always immediately available for access. Read and write bursting is allowed to this region. Read access to reserved addresses returns 0x00. For more details on register programming; refer to Section 6, starting on page 46, through Section 13, and to Figure 6 on page 25, through Figure 9. A detected address parity error on any read transaction results in a target abort; refer to Figure 11 on page 28. Address parity errors on write transactions are still posted to the PCI core interface, but are discarded. For burst transactions to the register space, the application side of the PCI core interface operates faster than the PCI bus, so the PCI core interface FIFOs will never get full. PCI_TRDY# remains asserted for all valid data phases applied.

4.1.3 Connection Memory Space Target Access

The T8110 connection memory is always immediately available for access (via dedicated access times assigned for PCI bus target transactions). Read and write bursting is allowed to this region. For more details on connection memory programming, see Section 14.1 on page 136, and Figure 6 through Figure 9. A detected address parity error on any read transaction results in a target abort; refer to Figure 11. Address parity errors on write transactions are still posted to the PCI core interface, but are discarded. For burst transactions to the connection memory space, the application side of the PCI core interface operates slightly slower than the PCI bus, so the PCI core interface FIFOs may get full. In this case, PCI_TRDY# gets deas- serted until the application side catches up.

4.1.4 Data Memory Space Target Access

The T8110 data memory is not guaranteed to be immediately available for access. Access to data memory is prior- itized for standard H-bus/L-bus switching and packet payload switching, with PCI target access allowed as the low- est priority. Because there is an indeterminate amount of latency, target burst transfers are not allowed to the data memory. Upon reception of a PCI read or write request, if the data memory is immediately available, the transac- tion is completed as normal single-cycle access; refer to Figure 6 and Figure 7. If the data memory is not available at the time of the request, any write cycle is posted and any read cycle becomes a delayed read. A detected address parity error on any read transaction results in a target abort (refer to Figure 11 on page 28). Address parity errors on write transactions are still posted to the PCI core interface, but are discarded.

4.1.4.1 Posted Write Transaction

Only one posted write to the data memory may be queued at a time; refer to Figure 6 for more details. The user must monitor a status bit (register status 8, bit 0; refer to Section 6.2.7) to determine whether a posted write is already queued before attempting more writes. Subsequent posted write attempts to the data memory while a queued posted write has not completed result in an error condition, and both writes (the queued one and the sub- sequent one) are ignored. Error is reported at register status 7, bit 0 (refer to Section 6.2.5 on page 59). Subse- quent read attempts from the data memory while a posted write is queued result in a target RETRY; please refer to Figure 10.

30 Agere Systems Inc. Data Sheet May 2001and Packet Payload Engine Ambassador T8110 PCI-Based H.100/H.110 Switch

4.1.4.2 Delayed Read Transaction

Only one delayed read from the data memory may be queued at a time. A delayed read transaction latches the address and command information, and issues a retry back to the initiator (refer to Figure 10). If the initiator retries the same transaction or attempts a different read transaction from data memory prior to the queued delayed read completion, a retry is issued. The delayed read transaction is completed when the initiator retries the same trans- action after the queued delayed read has finished (i.e., a normal completion of a single-cycle read; please refer to Figure 8). Any subsequent posted write attempts to the data memory while a delayed read is in progress result in an error condition, and the delayed read and the posted write attempts are ignored. Error is reported at register sta- tus 7, bit 0 (refer to Section 6.2.5 on page 59).

4.1.5 Virtual Channel Memory Space Target Access

The T8110 virtual channel memory is not guaranteed to be immediately available for access. Access to this mem- ory is prioritized for H-bus/L-bus switching and packet payload switching with PCI target access allowed as the lowest priority. Because there is an indeterminate amount of latency, target burst transfers are not allowed to the virtual channel memory. Upon reception of a PCI read or write request, if the virtual channel memory is immediately available, the transaction is completed as normal single-cycle access (refer to Figure 6 and Figure 8). If the virtual channel memory is not available at the time of the request, any write cycle is posted and any read cycle becomes a delayed read (for more detail on virtual channel memory programming; refer to Section 14.1.1.2 on page 138). A detected address parity error on any read transaction results in a target abort (refer to Figure 11). Address parity errors on write transactions are still posted to the PCI core interface, but are discarded.

4.1.5.1 Posted Write Transaction

Only one posted write to the virtual channel memory may be queued at a time. Refer to Figure 6. The user must monitor a status bit (register status 8, bit 1; refer to Section 6.2.7) to determine whether a posted write is already queued before attempting more writes. Subsequent posted write attempts to the virtual channel memory while a queued posted write has not completed result in an error condition, and both writes (the queued one and the sub- sequent one) are ignored. Error is reported at register status 7, bit 1 (refer to Section 6.2.5 on page 59). Subse- quent read attempts from the virtual channel memory while a posted WRITE is queued result in a target retry (refer to Figure 10).

4.1.5.2 Delayed Read Transaction

Only one delayed read from the virtual channel memory may be queued at a time. A delayed read transaction latches the address and command information, and issues a retry back to the initiator (refer to Figure 10). If the ini- tiator retries the same transaction or attempts a different read transaction from virtual channel memory prior to the queued delayed read completion, a retry is issued. The delayed read transaction is completed when the initiator retries the same transaction after the queued delayed read has finished (i.e., a normal completion of a single-cycle read; refer to Figure 8). Any subsequent posted write attempts to the virtual channel memory while a delayed read is in progress result in an error condition, and the delayed read and the posted write attempts are ignored. Error is reported at register status 7, bit 1 (refer to Section 6.2.5 on page 59).

4.1.6 Minibridge Space Target Access

The T8110 minibridge port is not guaranteed to be immediately available for access. Access time to this space is dependent on wait-state control register setups. Because there is a potential variable amount of latency, target burst transfers are not allowed to the minibridge port. All write cycles are posted writes. All read cycles are delayed reads. Refer to the Minibridge section, starting on page 107, for more details on minibridge control and operation. A detected address parity error on any read transaction results in a target abort (refer to Figure 11). Address parity errors on write transactions are still posted to the PCI core interface, but are discarded.

Agere Systems Inc. 31 Data Sheet May 2001 and Packet Payload Engine Ambassador T8110 PCI-Based H.100/H.110 Switch

4.1.6.1 Posted Write Transaction

Only one posted write to the minibridge port may be queued at a time; please refer to Figure 6. The user must monitor a status bit (register status 8, bit 2) to determine whether a posted write is already queued before attempt- ing more writes. Subsequent posted write attempts to the minibridge port while a queued posted write has not completed result in an error condition. The queued write is allowed to complete, but the subsequent write is ignored. Error is reported at register status 7, bit 2 (refer to Section 6.2.5 on page 59). Subsequent read attempts from the minibridge port, while a posted write is queued, result in a target retry (refer to Figure 10).

4.1.6.2 Delayed Read Transaction

Only one delayed read from the minibridge port may be queued at a time. A delayed read transaction latches the address and command information, and issues a retry back to the initiator (refer to Figure 10). If the initiator retries the same transaction or attempts a different read transaction from the minibridge port prior to the queued delayed read completion, a retry is issued. The delayed read transaction is completed when the initiator retries the same transaction after the queued delayed read has finished (i.e., a normal completion of a single-cycle read; refer to Figure 8). Any subsequent posted write attempts to the minibridge port while a delayed read is in progress result in an error condition. The delayed read is allowed to complete, but the write request is ignored. Error is reported at register status 7, bit 2 (refer to Section 6.2.5 on page 59).

4.2 Initiator

The T8110 can initiate PCI transactions in order to perform packet payload switching between the local PCI bus and the 64 H-bus/L-bus data streams. The T8110 initiates accesses in order to either send (or push) data received from H-bus/L-bus streams to an external data buffer, or to retrieve (or pull) data from an external data buffer to transmit out to the H-bus/L-bus streams. Each operation requires three PCI burst accesses. An external descriptor table provides current read/write pointer status to the external data buffer. The T8110 fetches pointer information from the descriptor table, transfers data to/from the external data buffer, and then updates the descriptor table pointer information. For more details, see Section 14.2.3 on page 155.

4.2.1 PUSH Operation (Upstream Transaction)

The push operation takes data received from incoming H-bus/L-bus streams and passes it to an external data buffer. This is denoted as an upstream transaction. The three required T8110 initiated burst cycles are shown below. For more details, see Section 14.2.3 on page 155. /c110 Memory read burst (fetch the write pointer information from the descriptor table). /c110 Memory write burst (upload the received H-bus/L-bus data to external data buffer). /c110 Memory write burst (update the write pointer information in the descriptor table).

This diagram depicts a target with medium decode speed (two-cycle turnaround to assertion of PCI_DEVSEL#). Each of the three separate PCI transactions requires a PCI bus arbitration (PCI_REQ# active, system responds with PCI_GNT#). Figure 12. T8110 PCI Interface, Initiated PUSH Operation

4.2.2 PULL Operation (Downstream Transaction)

ated burst cycles are shown below. For more information, see Section 14.2.3 on page 155. /c110 Memory read burst (fetch the read pointer information from the descriptor table). /c110 Memory write burst (update the read pointer information in the descriptor table).

This diagram depicts a target with medium decode speed (two-cycle turnaround to assertion of PCI_DEVSEL#). Each of the three separate PCI transactions requires a PCI bus arbitration (PCI_REQ# active, system responds with PCI_GNT#). Figure 13. T8110 PCI Interface, Initiated PULL Operation

4.3 Configuration Space/EEPROM Interface

single data phase burst cycles of two or more data phases. Table 12. T8110 PCI Configuration Registers

region of addressable space. A configuration write access cycle takes five PCI clocks. Figure 14. T8110 PCI Interface— Configuration WRITE Cycle

A configuration read access cycle takes six PCI clocks. Figure 15. T8110 PCI Interface— Configuration READ Cycle

4.3.1 Loadable PCI Configuration Space Via EEPROM

returned by the EEPROM are ignored, but must be present as placeholders.

Signals output from T8110 are driven relative to the falling edge of EE_SK and are sampled by the EEPROM on the rising edge. Signals output from the EEPROM are driven relative to the rising edge of EE_SK and are sampled by the T8110 on the falling edge. Each read cycle takes 26 EE_SK clocks. There are nine read cycles in all generated by the T8110's PCI core. Figure 16. EEPROM Interface Protocol Table 13. PCI Configuration Space, EEPROM Map

000000 Device ID field

000010 Vendor ID field

001000 Class code field (upper 2 bytes)

001010 Class code field (lower byte) and revision ID field

001100 BIST and header fields

101100 Subsystem ID field

101110 Subsystem vendor ID field

111100 MAX_LAT and MIN_GNT fields

111110 Interrupt pin field

38 Agere Systems Inc. Data Sheet May 2001and Packet Payload Engine Ambassador T8110 PCI-Based H.100/H.110 Switch

5 Microprocessor Interface

The T8110 provides a selection of two interface mechanisms via the VIO/µP_SELECT input. This must be a static signal (either pulled high or pulled low). /c110 VIO/µP_SELECT tied to GND = T8110 interface to a microprocessor bus, connected via the minibridge port. /c110 VIO/µP_SELECT tied to 3.3 V = T8110 interface to a local PCI bus, 3.3 V signaling. /c110 VIO/µP_SELECT tied to 5 V = T8110 interface to a local PCI bus, 5 V signaling. The T8110 microprocessor bus interface allows access to the T8110 internal regions via the minibridge port; see Table 9 on page 11 for pin descriptions. There are two user-selectable input signals that set up the microprocessor interface, MB_CS7 ( Intel/Motorola protocol select) and MB_CS5 (word/byte address select).

5.1 Intel/Motorola Protocol Selector

MB_CS7 = 1 is the default, if left unconnected, and selects an Intel handshake protocol. MB_CS7 = 0 selects a Motorola handshake protocol. Note: The MB_CS7 signal must be static (either pulled high or pulled low).

5.2 Word/Byte Addressing Selector

MB_CS5 = 1 is the default, if left unconnected, and selects 16-bit word aligned addressing. MB_CS5 = 0 selects 8-bit byte aligned addressing. Note: The MB_CS5 signal may be static or dynamic in nature. If dynamic, MB_CS5 must follow the same timing requirements as the address bus. Word-aligned addressing produces 16-bit data transfers via MB_D[15:0]. Byte-aligned addressing produces 8-bit data transfers via MB_D[7:0] (MB_D[15:8] is unused). The T8110 internal data bus is 32 bits, so MB_A[1:0] address bits are decoded along with MB_CS5 to control a dword-to-word or dword-to-byte swap function back to the MB_D bus. Table 14. Intel/Motorola Protocol Selector Intel/Motorola Protocol Selector Signal Intel Mnemonic Motorola Mnemonic MB_CS0 A[16] A[16] MB_CS1 A[17] A[17] MB_CS2 A[18] A[18] MB_CS3 A[19] A[19] MB_CS4 CSn CSn MB_CS6 RDY DTACKn MB_RD RDn (read strobe) DSn (data strobe) MB_WR WRn (write strobe) R/Wn (read/write selector) MB_CS5 Default Default MB_CS7 Default Default

5 Microprocessor Interface (continued)

5.3 Access Via the Microprocessor Bus

microprocessor bus asynchronous strobes are synchronized to the T8110's internal 65.536 MHz clock domain. There are 20 address bits provided to address the internal regions and these are defined in Table 15. Table 15. T8110 Memory Mapping to Microprocessor Space

5.3.1 Microprocessor Interface Register Map

The T8110 registers map into the microprocessor bus space as follows. Table 16. Microprocessor Interface Register Map

Table 16. Microprocessor Interface Register Map (continued)

Figure 17. Microprocessor Access Timing, Intel Protocol

Figure 18. Microprocessor Access Timing, Motorola Protocol

5.3.2 Register Space Access

5.3.3 Connection Memory Space Access

access timing for Figure 17 and Figure 18 is shown below. Table 17. Register Space Access Timing Table 18. Connection Memory Space Access Timing

5.3.4 Data Memory Space Access

switching configuration. Data memory access timing for Figure 17 and Figure 18 is shown below.

5.3.5 Virtual Channel Memory Space Access

switching configuration. Virtual channel memory access timing for Figure 17 and Figure 18 is shown below. channels aren't supported with the microprocessor interface protocol selected). Table 19. Data Memory Space Access Timing Table 20. Virtual Channel Memory Space Access Timing

6 Operating Control and Status

6.1 Control Registers

clock fallback, and clock watchdog configuration. interface is to the microprocessor bus, this register is [reserved].

6.1.1 Reset Registers

reset register trigger the corresponding action, and the set bit(s) are automatically cleared. — Maskable to T8110 back-end via reset select register, PRBEB. T8110 registers (excluding reset select register) and connection valid flags. — Maskable to minibridge port via reset select register, PMBEB. see Section 11.2 on page 110). Soft resets are maskable via reset select register, SRBEB, and selectable via soft reset register, SRESR. /c110 Soft reset 1: Initialize all T8110 registers (excluding reset select register) and connection valid flags. /c110 Soft reset 2: Initialize all T8110 registers (excluding reset select register). /c110 Soft reset 3: Reset all interrupt pending registers and the interrupt in-service register. Table 21. Control Register Map

6 Operating Control and Status (continued)

/c110 Soft reset 4: Reset the interrupt in-service register only. /c110 RESET_PENDING_MEM: Reset the virtual channel NOTIFY_PENDING memory. /c110 RESET_QUEUE: Reset the virtual channel NOTIFY_QUEUE FIFO.

6.1.2 Master Output Enable Register

CLKERR, SYSERR, PRI_REF_OUT, NR1_SEL_OUT, and NR2_SEL_OUT. Table 22. Reset Registers Reset all registers and connection valid flags. Reset interrupt pending and in-service registers. Reset interrupt in-service register only. Reset virtual channel NOTIFY_PENDING memory. Reset virtual channel NOTIFY_QUEUE. 0x00101 Reset Select 7:4 Reserved 0000 NOP (default). Disable PCI reset to minibridge (default). Enable PCI reset to minibridge. Disable PCI reset to back end (default). Enable PCI reset to back end.

1 HRBEB 0

Disable hard reset to back end. Enable hard reset to back end (default). Disable soft resets to back end. Enable soft resets to back end (default).

*MBREB is only relevant if the T8110 interfaces to the PCI bus. If the selected T8110 interface is to the microprocessor bus, this bit is reserved.

6.1.3 Connection Control—Virtual Channel Enable and Data Memory Selector Register

Table 23. Master Output Enable Register Individual enables via bits [6:0] (default). Enable all (same as bits [6:0] = 1111111). Disable minibridge* (default).

3 HCKEB 0

Disable H-bus clocks (default).

2 HDBEB 0

Disable H-bus data streams (default). Disable L-bus clocks, L_SC, FG (default). Disable L-bus data streams (default). Table 24. Virtual Channel Enable and Data Memory Selector Register START (enable) VC switching, immediate. PAUSE (disable) VC switching, immediate. START VC switching, synchronized to frame. PAUSE VC switching, synchronized to frame.

1. 4k single-buffered switch. Standard H-bus/L-bus switching only, up to 4096 simplex connections, all connections

are minimum delay due to single-buffer configuration.

1. 2k double-buffered switch. Standard H-bus/L-bus switching only, up to 2048 simplex connections, all connec-

tions are programmable for minimum or constant delay via the double-buffer configuration.

1. 2k single-buffered switch + 1k double-buffered switch. Standard H-bus/L-bus switching only, up to 2048 simplex
2. 2k single-buffered switch + 256 virtual channels. Standard H-bus/L-bus switching, up to 2048 simplex minimum

delay connections (single buffer), PLUS packet payload switching, up to 256 virtual channels.

1. 1k double-buffered switch + 256 virtual channels. Standard H-bus/L-bus switching, up to 1024 simplex minimum
2. No standard switching + 512 virtual channels. Packet payload switching only, up to 512 virtual channels.

6.1.4 General Clock Control (Phase Alignment, Fallback, Watchdogs) Register

Clock Output Control Register Map. Only one set is used at a time. It is selected based on the clock fallback setup. Table 25. Data Memory Mode Select Register

7 GSREB 0

Disable subrate switching (default). 4k single-buffer switch (default). 2k single-buffer, 1k double-buffer switch. 2k single buffer switch, 256 virtual channels. 1k double buffer switch, 256 virtual channels. Table 26. Clock Register Access Select Register Access inactive clock registers (default). Access active clock registers.

6.1.5 Phase Alignment Select Register

reference from the H-bus (/CT_FRAME_A, /CT_FRAME_B, or /FR_COMP) or local clock reference (LREF[4:7]).

6.1.6 Fallback Control Register

to be performed until the next 8 kHz frame reference (synchronized to frame). performed until the next 8 kHz frame reference (synchronized to frame). tive clock register set. This command is performed immediately upon issue. Table 27. Phase Alignment Select Register Phase alignment is disabled (default).

6.1.7 Fallback Type Select Register

require the fallback trigger register settings. For more details, see Section 7.7.1 on page 82. are three possible selections. For more details, see Section 7.7 on page 82. /c110 Disabled. No transitions of clock register X and Y sets to active/inactive. /c110 Fixed secondary. Swap the active/inactive sets on a fallback event; swap them back when fallback is cleared.

6.1.8 Fallback Trigger Registers

DPLL2 can also trigger a clock fallback event upon detection of an error. Table 28. Fallback Control Register GO_CLOCKS synchronized to frame*. CLEAR_FALLBACK synchronized to frame*. FORCE_FALLBACK synchronized to frame*. Table 29. Fallback Type Select Register Legacy, fallback to OSC/4 on main select failure. Legacy, fallback X/Y set on main select failure. Legacy, fallback X/Y set on H-bus A/B failure. Fallback trigger registers control fallback. H-Bus clock enable state machine is enabled. Fallback is disabled (default). Enable fixed secondary fallback. Enable rotating secondary fallback.

6.1.9 Watchdog Select, C8, and NETREF Registers

clocking architecture, including 8 kHz (frame reference), 1.544 MHz (T1 bit clock), and 2.048 MHz (E1 bit clock). Table 30. Fallback Trigger Registers Disable /SCLKx2 trigger (default). Disable SCLK trigger (default). Disable C2 trigger (default). Disable /C4 trigger (default). Disable /C16– trigger (default). Disable /C16+ trigger (default). Disable CT_C8_B trigger (default). Disable CT_C8_A trigger (default). 0x0010B Fallback Trigger, Upper 7 Reserved 0 NOP (default). Disable DPLL2 sync trigger (default). Disable DPLL1 sync trigger (default). Disable CT_NETREF2 trigger (default). Disable CT_NETREF1 trigger (default). Disable /FR_COMP trigger (default). Disable /CT_FRAME_B trigger (default).

0 FAFEB 0

Disable /CT_FRAME_A trigger (default).

6.1.10 Watchdog EN Register

dogs on the sync inputs of DPLL1 and DPLL2. Table 31. Watchdog Select, C8, NETREF Registers CT_C8_B watchdog at 8.192 MHz (default). CT_C8_B watchdog at 4.096 MHz MC1mode. CT_C8_A watchdog at 8.192 MHz (default). CT_C8_A watchdog at 4.096 MHz MC1mode. CT_NETREF2 watchdog at 8 kHz (default). CT_NETREF2 watchdog at 1.544 MHz. CT_NETREF2 watchdog at 2.048 MHz. CT_NETREF1 watchdog at 8 kHz (default). CT_NETREF1 watchdog at 1.544 MHz. CT_NETREF1 watchdog at 2.048 MHz. Table 32. Watchdog EN Registers Disable /SCLKx2 watchdog (default). Disable SCLK watchdog (default). Disable C2 watchdog (default). Disable/C4 watchdog (default). Disable/C16– watchdog (default).

2 CPWEB 0

Disable/C16+ watchdog (default).

1 CBWEB 0

Disable CT_C8_B watchdog (default). Disable CT_C8_A watchdog (default).

6.1.11 Failsafe Control Registers

either the primary or secondary clock register sets. For more on failsafe, please see Section 7.7.2 on page 88. Disable FAILSAFE ref watchdog (default). Enable FAILSAFE ref watchdog. Disable DPLL2 sync watchdog (default). Disable DPLL1 sync watchdog (default). Disable CT_NETREF2 watchdog (default). Disable CT_NETREF1 watchdog (default). Disable /FR_COMP watchdog (default).

1 FBWEB 0

Disable /CT_FRAME_B watchdog (default). Enable /CT_FRAME_B watchdog. Disable /CT_FRAME_A watchdog (default). Enable /CT_FRAME_A watchdog. Table 33. Failsafe Control Register Return from failsafe to nonfallback condition. Return from failsafe to fallback condition. Failsafe watchdog highest sensitivity. Failsafe watchdog + 30.5 ns. Failsafe watchdog + 121.0 ns. Failsafe watchdog + 244.0 ns. Failsafe watchdog + 488.0 ns. 0x00118 OOL Threshold Low 7:0 OLLLR LLLL LLLL Failsafe threshold value, low byte. 0x00119 OOL Threshold High 7:0 OLHLR LLLL LLLL Failsafe threshold value, high byte. Monitor direct APLL1 lock detect at PLOCK. Monitor user threshold lock detect at PLOCK. Table 32. Watchdog EN Registers (continued)

see Section 7.7.2 on page 88. on OOL operation, please see Section 7.7.2 on page 88.

6.1.12 External Buffers—Descriptor Table Base Address

6.2 Error and Status Registers

of these registers will clear the corresponding error bit. The remaining error and status registers are read-only. Table 34. Extended Buffers Base Addresses Table 35. Error and Status Register Map

6.2.1 Clock Errors

6.2.1.1 Transient Clock Errors Registers

Table 36. Clock Error Registers Failsafe indicator: APLL1 reference no error. DPLL2 sync no error (default). DPLL1 sync no error (default). CT_NETREF2 no error (default). CT_NETREF1 no error (default). /FR_COMP no error (default). /CT_FRAME_B no error (default). /CT_FRAME_A no error (default).

6.2.1.2 Latched Clock Error Register

tion 12 on page 113 for more details. Table 37. Latched Clock Error Registers

5 C2LOB 0

4 C4LOB 0

Failsafe indicator: APLL1 reference no error.

6 D2LOB 0

DPLL2 sync no error (default).

5 D1LOB 0

DPLL1 sync no error (default).

4 N2LOB 0

CT_NETREF2 no error (default).

3 N1LOB 0

CT_NETREF1 no error (default). /FR_COMP no error (default). /CT_FRAME_B no error (default). /CT_FRAME_A no error (default).

6.2.2 System Status

6.2.3 Clock Fallback Status Register

The lower nibble provides status indicators related to the X and Y clock register set active/inactive assignments. 0x00108), which are waiting for a frame sync.

6.2.4 PLL and Switching Status Register

switching; see Section 14.2.1.2 on page 148. Table 38. Fallback and Failsafe Status Register Indicates not in fallback/failsafe state (default). Indicates fallback/failsafe state. Fallback state = INITIAL (default). Fallback state = TO_PRIMARY . Fallback state = SECONDARY . Fallback state = TO_SECONDARY .

3 XYSOB 0

Clock register Y set is active, X is inactive. Clock register X set is active, Y is inactive. No GO_CLOCKS pending (default). GO_CLOCKS pending, waiting for frame. No CLEAR_FALLBACK pending (default). CLEAR_FALLBACK pending, waiting for frame. No FORCE_FALLBACK pending (default).

6.2.5 System Errors Register

Table 39. PLL and Switching Status Register

7 A1LOB 0

Out-of-lock indicator inactive. Out-of-lock indicator active. DPLL1 out-of-lock, slow correction. DPLL1 out-of-lock, fast correction. DPLL2 out-of-lock, slow correction. DPLL2 out-of-lock, fast correction. Connection memory not resetting (default). Connection memory reset loop is active. Active page = data memory page 1. Active page = date memory page 2. Table 40. System Errors Registers PCI master, PCI bus fatal error. PCI master, external buffer LOCK error. PCI master, external buffer STALL error. PCI master, external buffer STALL warning. PCI master, external buffer overwrite warning. PCI master, external buffer INITIAL warning. VC memory, scratchpad overflow warning.

0 NQOOB 0

NOTIFY_QUEUE, overflow warning.

6.2.6 Device Identification Registers

These registers identify the device type and revision status, T8110 revision n. PCI target, minibridge discard timer expired. PCI target, VC memory discard timer expired. PCI target, data memory discard timer expired.

2 MBPOB 0

PCI target, minibridge protocol error. PCI target, VC memory protocol error. PCI target, data memory protocol error. Table 41. Device Identification Registers 0x00128 Version ID 7:0 VEROR 0000 0001 Revision status (value shown = REV1). 0x0012A Device ID, Lower 7:0 IDLOR 0001 0000 Device ID low status 0x10. 0x0012B Device ID, Upper 7:0 IDHOR 1000 0001 Device ID high status 0x81. Table 40. System Errors Registers (continued)

6.2.7 Miscellaneous Status

Table 42. Miscellaneous Status Registers 0x0012C Status 8 7:3 Reserved 0000 0 NOP . Minibridge PCI target queue is empty. Minibridge PCI target queue is full. VC memory PCI target queue is empty. VC memory PCI target queue is full. Data memory PCI target queue is empty. data memory PCI target queue is full. 0x0012D Status 9 7:6 Reserved 00 NOP .

5 VPPOB 0

PAUSE is pending (waiting for frame).

4 VSPOB 0

START is pending (waiting for frame). PAUSE virtual channel switching (disabled). START virtual channel switching (enabled).

7 Clock Architecture

Figure 19. T8110 Main Clocking Paths Figure 20. T8110 NETREF Paths

2.048 MHz

4.096 MHz

8.192 MHz

16.364 MHz

49.408 MHz

4 MHz

7 Clock Architecture (continued)

7.1 Clock Input Control Registers

The following registers control the T8110 main clocking paths and NETREF paths.

7.1.1 Main Input Selector Register

The main input selector register controls clock and frame input selection.

• C2 is allowed as the bit clock input.
• Selection of which LREF is controlled at register 0x00208. Selection of LREF polarity is controlled at register 0x0020C.

Table 43. Clock Input Control Register Map Table 44. Main Input Selector Register Select oscillator/crystal (default). Select LREF[0:7] individually. Select LREF[0:3, 4:7] paired. MVIP clocks (C2 bit clock)*. Select MVIP clocks (/C4 bit clock). Select H-MVIP clocks (/C16± bit clock). Select SC-bus clocks 4/8 MHz.

• C2 is allowed as the bit clock input.

7.1.2 Main Divider Register

The main divider register contains [divider value – 1]. A value of 0x00 yields a divide-by-1 function. A value of 0xFF yields a divide-by-256 function.

7.1.3 Analog PLL1 (APLL1) Input Selector Register

Table 45. Main Divider Register Table 46. APLL1 Input Selector Register Select oscillator/4 (default). Select resource divider output. Select external input PRI_REF_IN.

7.1.4 APLL1 Rate Register

[x32 (multiplied by)] value must be selected. A [x1 (multiplied by)] value is provided in order to bypass APLL1.

7.1.5 Main Inversion Select Register

/c110 Main clock selection CLK SEL MUX output; see Figure 19 on page 62. /c110 NETREF2 divider output; see Figure 20 on page 62. Table 47. APLL1 Rate Register Times 1 BYPASS (lower nibble is don't care). Table 48. Main Inversion Select Register 0x00204 Main Inversion Select 7:5 Reserved 000 NOP (default). Don't invert main clock selection (default). Invert main clock selection. Don't invert NETREF2 divider output (default). Invert NETREF2 divider output. Don't invert NETREF2 selection (default). Don't invert NETREF1 divider output (default). Invert NETREF1 divider output. Don't invert NETREF1 selection (default).

7.1.6 Resource Divider Register

0xFF yields a divide-by-256 function.

7.1.7 Analog PLL2 (APLL2) Rate Register

(times 8) value must be selected. A (times 1) value is provided in order to bypass APLL2. Table 49. Resource Divider Register Table 50. APLL2 Rate Register Times 1 BYPASS (lower nibble is don't care).

7.1.8 LREF Input Select Registers

selection control among the eight LREF inputs when the main selection is set for either individual or paired LREFs. on page 62 for further details. Table 51. LREF Input/Inversion Select Registers Select paired, clock = LREF0, frame = LREF4. Select paired, clock = LREF1, frame = LREF5. Select paired, clock = LREF2, frame = LREF6. Select paired, clock = LREF3, frame = LREF7. Don't invert LREF7 (default). Don't invert LREF6 (default). Don't invert LREF5 (default). Don't invert LREF4 (default). Don't invert LREF3 (default). Don't invert LREF2 (default). Don't invert LREF1 (default). Don't invert LREF0 (default).

7.1.9 DPLL1 Input Selector

7.1.9.1 DPLL1 Rate Register

The DPLL1 rate register controls the DPLL1 output frequency. Table 52. DPLL1 Input Selector Registers DPLL1 output at 4.096 MHz (default).

7.1.10 DPLL2 Input Selector

7.1.10.1 DPLL2 Rate Register

The DPLL2 rate register controls the DPLL2 output frequency. Table 53. DPLL2 Register T8110 internally generated frame.

7.1.11 NETREF1 Registers

used to generate CT_NETREF1 (see Figure 20 on page 62).

• Selection of which LREF is controlled at register 0x00212.

Table 54. NETREF1 Registers Divider input = selector output (default). Divider input = external input NR1_DIV_IN. Oscillator/XTAL1-div-8, 2.048 MHz (default). Oscillator/XTAL1, 16.384 MHz. Oscillator/XTAL2, 6.176 MHz, or 12.352 MHz.

7.1.12 NETREF2 Registers

used to generate CT_NETREF2 (see Figure 20 on page 62).

• Selection of which LREF is controlled at register 0x00216.

Table 55. NETREF2 Registers Divider input = selector output (default). Divider input = external input NR1_DIV_IN. Oscillator/XTAL1-div-8, 2.048 MHz (default). Oscillator/XTAL1, 16.384 MHz. Oscillator/XTAL2, 6.176 MHz, or 12.352 MHz.

7.2 Clock Output Control Registers

The registers listed below control output enable and rate selection of the T8110 clock path outputs.

7.2.1 Master Output Enables Register

B-clocks refers to the CT_C8_B bit clock and /CT_FRAME_B frame reference. Table 56. Clock Output Control Register Map

Table 57. Master Output Enables Registers Disable A and B clock outputs (default). Enable A clock outputs only. Enable B clock outputs only. Enable both A and B clock outputs. Disable compatibility (C clock) outputs (default). Enable C clocks individually*. CT_NETREF2 disabled (default). CT_NETREF1 disabled (default). /FR_COMP disabled (default). C-clock bit clocks disabled (default).

7.2.2 Clock Output Format Registers

The clock output format registers select the pulse width of the /FR_COMP pulse width. (H1x0) mode, or 4.096 MHz for MC1 mode.

7.2.3 TCLK and L_SCx Select Registers

L_SC1, L_SC2, and L_SC3 signals. Table 58. Clock Output Format Registers /FR_COMP width is 122 ns (default). CT_C8_B output at 8.192 MHz (default). CT_C8_B output at 4.096 MHz, MC1 mode. CT_C8_A output at 8.192 MHz (default). CT_C8_A output at 4.096 MHz, MC1 mode. SCLK = 4 MHz, /SCLKx2 = 8 MHz. SCLK = 8 MHz, /SCLKx2 = 8 MHz phase shifted.

Table 59. TCLK Select and L_SCx Select Registers TCLK output disabled (default). Select APLL1 output, 65.536 MHz. Select APLL2 output, 49.704 MHz. Select DPLL2 output inverted. Select APLL1 output inverted. Select APLL2 output inverted. Select generated 16.384 MHz. Select generated 32.768 MHz. Select generated 2.048 MHz inverted. Select generated 4.096 MHz inverted. Select generated 8.192 MHz inverted. Select generated 16.384 MHz inverted. select generated 32.768 MHz inverted. Select generated CT_NETREF1. Select generated CT_NETREF2. Select generated frame inverted. Select generated CT_NETREF1 inverted. Select generated CT_NETREF2 inverted. L_SCx output disabled (default). Select generated 16.384 MHz. Select generated 32.768 MHz. Select generated 2.048 MHz inverted. Select generated 4.096 MHz inverted. Select generated 8.192 MHz inverted. Select generated 16.384 MHz inverted. Select generated 32.768 MHz inverted. Select generated CT_NETREF1. Select generated CT_NETREF2. Select generated frame inverted. Select generated CT_NETREF1 inverted. Select generated CT_NETREF2 inverted.

7.3 Clock Register Access

7.4 Clock Circuit Operation—APLL1

diagnostic purposes. Please refer to Figure 19 on page 62.

7.4.1 Main Clock Selection, Bit Clock, and Frame

main divider, resource divider, and DPLL1.

• MVIP, /C4 is typically the bit clock. C2 is selectable as the bit clock as well.

† When LREF pairing is enabled. Table 60. Bit Clock and Frame

7.4.1.1 Watchdog Timers

incoming clocks at 32.768 MHz (derived from the XTAL1 crystal) and monitor for loss of signal, as shown below. Table 61. Watchdog Timer Description 35 ns window of its expected arrival. MC1 mode. Monitors for loss of signal (falling edges). (i.e., next frame pulse too early). (i.e., next frame pulse too early). (i.e., next frame pulse too early).

• User selects frequency at which to monitor the CT_C8 clocks via register 0x0010C, watchdog select, C8.

† DPLL sync reference is expected to be 8 kHz.

7.4.1.2 Frame Center Sampling

evant when the main clock selection is based on a paired bit clock/frame reference, as follows.

7.4.2 Main and Resource Dividers

tion ranges from divide-by-1 (bypass) to divide-by-256. /c110 For binary divider values of 1, 2, 4, 8, 16, 32, 64, 128, and 256, the output is 50% duty cycle. /c110 For all other divider values, the output is a pulse whose width is one full period of the main clock selection signal. is also available at the PRI_REF_OUT chip output. on page 76. This allows for immediate loading of the newly activated divider register values. Table 62. Frame Center Sampling /CT_FRAME_A CT_C8_A Recovered 8.192 MHz, rising edge. /CT_FRAME_B CT_C8_B Recovered 8.192 MHz, rising edge. Recovered 4.096 MHz, falling edge. /FR_COMP SCLK or /SCLKx2 (SC-bus) Recovered 2.048 MHz, rising edge. LREF[4] LREF[0] Recovered 2.048 MHz, rising edge. LREF[5] LREF[1] Recovered 2.048 MHz, rising edge. LREF[6] LREF[2] Recovered 2.048 MHz, rising edge. LREF[7] LREF[3] Recovered 2.048 MHz, rising edge.

Agere Systems Inc. 79 Data Sheet May 2001 and Packet Payload Engine Ambassador T8110 PCI-Based H.100/H.110 Switch

7.4.3 DPLL1

A digital phase-lock loop is provided to generate a 4.096 MHz or 2.048 MHz reference to APLL1, selectable via register 0x0020B (DPLL1 rate). The DPLL1 operates at 32.768 MHz, derived from the XTAL1 crystal input. The DPLL1 synchronization source is selectable (register 0x0020A, DPLL1 input selector) between the main clock selection signal, the output of the resource divider, or the output of the main divider, and is intended to be pre- sented as an 8 kHz frame reference. DPLL1 is determined to be in-lock or out-of-lock, based on the state of the output clock when an edge transition is detected at the synchronization source. An out-of-lock condition results in a DPLL1 correction, which can either lengthen or shorten its current output clock period by 30.5 ns.

7.4.4 Reference Selector

The APLL1 reference clock is selectable between five possible sources via register 0x00202, APLL1 input selec- tor. A 4.096 MHz or 2.048 MHz reference must be provided. The five possible sources are shown below: /c110 XTAL1 crystal (16.384 MHz) divided-by-4 /c110 Main divider output /c110 Resource divider output /c110 DPLL1 output /c110 PRI_REF_IN external chip input

7.4.5 Internal Clock Generation

The main internal functions of T8110 are synchronous to the 65.536 MHz output of APLL1. This clock is further divided to generate 32.768 MHz, 16.384 MHz, and 8 kHz internal reference signals. Additional divide-down values to 8.192 MHz, 4.096 MHz, and 2.048 MHz are generated. These generated clocks are the source for H1x0, MVIP , MVIP, and SC-bus clocks when the T8110 is mastering the bus clocks; see Section 7.2 on page 72. These internally generated clocks can either be free-running, or can be aligned to the incoming main selection clock and frame, via a phase alignment circuit (see Section 7.4.5.1).

7.4.5.1 Phase Alignment

the phase alignment circuit is enabled (via register 0x00107, phase alignment select). pared to the state of the internally generated frame. The circuit determines whether the frame centers are aligned. /c110 NOP: no corrections when phase alignment is disabled. frame periods that are 15.25 ns longer than 125 µs until the frames are aligned. Please refer to Figure 21. Figure 21. T8110 Phase Alignment, SNAP and SLIDE

Agere Systems Inc. 81 Data Sheet May 2001 and Packet Payload Engine Ambassador T8110 PCI-Based H.100/H.110 Switch

7.5 Clock Circuit Operation, APLL2

APLL2 requires either a 6.176 MHz or 12.352 MHz reference clock to produce a 49.408 MHz clock for operating DPLL2. A user-supplied rate multiplier (register 0x00207, APLL2 rate) provides either a times 8 function (when ref- erence clock = 6.176 MHz) or a times 4 function (when reference clock = 12.352 MHz). Additionally, APLL2 may be bypassed for circuit diagnostic purposes (see Figure 19 on page 62).

7.5.1 DPLL2

A second digital phase-lock loop is provided to generate various derivations of T1 operating frequencies, available by selection via the TCLK_OUT output. The possible output frequencies are selectable via register 0x0020F 49.408 MHz from the APLL2 output. Synchronization sources for DPLL2 include the same sources provided to DPLL1 (selectable between the main clock selection signal, the output of the resource divider, or the output of the main divider) and two additional sources, including the T8110 internally generated frame signal and the PRI_REF_IN input. These selections are available via register 0x0020E, DPLL2 input selector. DPLL2 is deter- mined to be in-lock or out-of-lock based on the state of its output when an edge transition is detected at the syn- chronization source. An out-of-lock condition results in a DPLL2 correction, which can either lengthen or shorten its current output clock period by 20.2 ns.

7.6 Clock Circuit Operation, CT_NETREF Generation

The T8110 provides two independently programmable paths to generate CT_NETREF1 and CT_NETREF2, via registers 0x00210—0x00216. Each CT_NETREF is individually enabled with register 0x00221, NETREF output enables. Each path consists of a source selector MUX and a divider circuit (see Figure 20 on page 62).

7.6.1 NETREF Source Select

XTAL1 input DIV 8 (2.048 MHz) XTAL1 input (16.384 MHz) XTAL2 input (6.176 MHz or 12.352 MHz) LREF[7:0] CT_NETREFx (the other NETREF—i.e., CT_NETREF1 can be derived from CT_NETREF2, and vise-versa). The output of the source select MUX is made available directly to the NETREF divider, and also to chip output (NR1_SEL_OUT, NR2_SEL_OUT).

7.6.2 NETREF Divider

Each NETREF path provides a divider from a divide-by-1 function up to a divide-by-256 function. The clock source for the divider is selectable between the output of the source select MUX or from external chip input (NR1_DIV_IN, NR2_DIV_IN). /c110 For binary divider values of 1, 2, 4, 8, 16, 32, 64, and 128, output is 50% duty cycle. /c110 For divider values of 256, 193, plus all other nonbinary values, output is a pulse whose width is one-half of a clock period, asserted during the second half of the divider clock period. The NETREF dividers are reset whenever a changeover between X and Y clock register sets is detected (see Sec- tion 7.3 on page 76). This allows for immediate loading of the newly activated divider register values.

82 Agere Systems Inc. Data Sheet May 2001and Packet Payload Engine Ambassador T8110 PCI-Based H.100/H.110 Switch

7.7 Clock Circuit Operation—Fallback and Failsafe

Fallback is a means to alter the reference source to APLL1 by switching between two clock control register sets upon detection of a fallback event. Failsafe is a feature to provide a safety net for the reference source to APLL1, independent of clock fallback.

7.7.1 Clock Fallback

Clock fallback is a means to alter the APLL1 reference clock source upon detection of a fallback event and is con- trolled by eight registers, 0x00108—0x0010F (refer to Section 6.1.4 on page 49). These registers enable and con- trol the state transitions that determine which of two clock register sets is used to control the APLL1 reference clock source (see Section 7.1 on page 63 through Section 7.3, Table 64 on page 85, and Figure 23 on page 84).

7.7.1.1 Fallback Events

Clock fallback (transition from primary to secondary clock sets) can only occur if the fallback mode is enabled (reg- ister 0x00109, lower nibble) and a fallback event occurs. When enabled, there are three ways to trigger the fallback event: /c110 Software, via a FORCE_FALLBACK command. The user sets bit 2 of the fallback control register, 0x00108, cre- ating a software-invoked fallback event. /c110 Hardware via the fallback trigger enable registers, 0x0010A—0x0010B. User may enable specific watchdog tim- ers and corresponding fallback trigger enable bits. If a watchdog timer indicates a clock error, and its correspond- ing trigger enable bit is set, a hardware-invoked fallback event is produced. /c110 Hardware, legacy modes, via the fallback type select register, 0x00109, upper nibble. The legacy modes are included to maintain backwards compatibility with earlier Ambassador devices. User may enable specific watch- dog timers, but the fallback trigger enable registers are ignored. Instead, the watchdogs which are allowed to trigger a fallback event are automatically selected based on the state of the main input selector register, 0x00200 (refer to Table 63). If a watchdog timer indicates a clock error, and its corresponding trigger enable is selected via the main input selector, a hardware-invoked fallback event is produced.

between the primary and secondary clock sets. fallback event is cleared (via user-invoked CLEAR_FALLBACK), the active clock set returns to primary. the new primary, and the primary becomes the new secondary. The concepts are illustrated in the figure below. Figure 22. Fallback—Fixed vs. Rotating Secondary Table 63. Legacy Mode Fallback Event Triggers

Figure 23. T8110 Clock Fallback States

• Fallback event; refer to Section 7.7.1.1 on page 82.

† Fixed, rotating secondary; refer to Section 7.7.1.2 on page 83. Table 64. Clock Fallback State Description (set register 0x00108 bit 0).

7.7.1.3 H-Bus Clock Enable/Disable on Fallback

enable/disable is activated. determine what triggers a fallback, and the state machine which controls H-bus clock enable/disable is activated. Figure 24. T8110 H-Bus Clock Enable States

Table 65. H-Bus Clock Enable State Description ter (0x00220, master output enables). ter (0x00220, master output enables). and B clocks (diagnostic mode). ter (0x00220, master output enables). ter (0x00220, master output enables). is detected; disable clock outputs. ter (0x00220, master output enables). is detected; promote to A clock master. is detected; disable clock outputs. ter (0x00220, master output enables). stopped driving any H bus clocks. ter (0x00220, master output enables). is detected; disable clock outputs. ter (0x00220, master output enables). is detected; promote to B clock master. is detected; disable clock outputs. ter (0x00220, master output enables). stopped driving any H bus clocks. ter (0x00220, master output enables).

7.7.2 Clock Failsafe

(primary or secondary) or a fallback (TO_SECONDARY or TO_PRIMARY) state. Refer to Table 66 and Figure 25.

7.7.2.1 Failsafe Events

is triggered by a watchdog error on the APLL1 reference clock (i.e., loss-of-reference). Figure 25. T8110 Clock Failsafe States

Table 66. Clock Failsafe State Descriptions (set register 0x00114 bit 0). (set register 0x00114 bit 1). (set register 0x00114 bit 0). (set register 0x00114 bit 1).

8 Frame Group and FG I/O

providing a timer via a 16-bit programmable counter.

8.1 Frame Group Control Registers

8.1.1 FGx Lower and Upper Start Registers

The FGx lower and upper start registers provide a 12-bit delay offset value for the corresponding frame group bit. 32.768 MHz clock period (30.5 ns increments). Table 67. Frame Group and FG I/O Register Map Table 68. FGx Lower and Upper Start Registers LLLL LLLL Lower 8 bits of 12-bit start offset. 0000 LLLL Upper 4 bits of 12-bit start offset.

8 Frame Group and FG I/O (continued)

8.1.2 FGx Width Registers

The FGx width registers control the polarity and the pulse widths generated for the corresponding frame group bit. 1-byte, and 2-byte wide pulses for any of the available frame group rates (see Table 69).

8.1.3 FGx Rate Registers

• FGIO operation is controlled at registers 0x00480—482. Refer to Section 8.3 on page 93.

Table 69. FGx Width Registers Generate active-high pulse (default). Table 70. FGx Rate Registers FGIO enabled* (not used as a frame group).

8.2 FG7 Timer Option

The FG7 signal allows for an added function of a timer output, via a 16-bit programmable counter.

8.2.1 FG7 Counter (Low and High Byte) Registers

*Normal operation allows frame group or FGIO control via registers 0x00470—473. Enabling the counter overrides 0x00470—473 settings. ‡Carry out pulse is active for one FG7 timer clock period. §Programmable pulses are based on T8110 internal 32.768 MHz clock periods. Table 71. FG7 Counter (Low and High Byte) Registers 0x00474 FG7 Counter, Low Byte 7:0 FCLLR LLLL LLLL Lower 8 bits of 16-bit counter value. 0x00475 FG7 Counter, High Byte 7:0 FCULR LLLL LLLL Upper 8 bits of 16-bit counter value. Normal operation* (default). Enable timer, clock = internal frame. Enable timer, clock = external FG6. Inverted FG7 timer output, low pulses. FG7 timer output off (default). FG7 timer output = carry out pulse‡. FG7 timer output = programmable pulse§. Programmable pulse width = 30.5 ns. Programmable pulse width = 61.0 ns. Programmable pulse width = 91.5 ns. Programmable pulse width = 122 ns.

8.3 FGIO Control Registers

8.3.1 FGIO Data Register

FGx rate registers. Reads are maskable, controlled via register 0x00481.

8.3.2 FGIO Read Mask Register

on a read access to the FGIO register. Table 72. FGIO Data Register 0x00480 FGIO Data Register 7 F7IOB L FGIO bit 7 value. Table 73. FGIO Read Mask Register Unmask FGIO bit 7 (default). Mask FGIO bit 7, return 0 on a read. Unmask FGIO bit 6 (default). Mask FGIO bit 6, return 0 on a read. Unmask FGIO bit 5 (default). Mask FGIO bit 5, return 0 on a read. Unmask FGIO bit 4 (default). Mask FGIO bit 4, return 0 on a read. Unmask FGIO bit 3 (default). Mask FGIO bit 3, return 0 on a read. Unmask FGIO bit 2 (default). Mask FGIO bit 2, return 0 on a read. Unmask FGIO bit 1 (default). Mask FGIO bit 1, return 0 on a read. Unmask FGIO bit 0 (default). Mask FGIO bit 0, return 0 on a read.

8.3.3 FGIO R/W Register

Table 74. FGIO R/W Register FGIO bit 7 direction is input (default). FGIO bit 7 direction is output. FGIO bit 6 direction is input (default). FGIO bit 6 direction is output. FGIO bit 5 direction is input (default). FGIO bit 5 direction is output. FGIO bit 4 direction is input (default). FGIO bit 4 direction is output. FGIO bit 3 direction is input (default). FGIO bit 3 direction is output. FGIO bit 2 direction is input (default). FGIO bit 2 direction is output. FGIO bit 1 direction is input (default). FGIO bit 1 direction is output. FGIO bit 0 direction is input (default). FGIO bit 0 direction is output.

8.4 FG Circuit Operation

Figure 26. FG[7:0] Functional Paths

8.4.1 Frame Group 8 kHz Reference Generation

control required, an offset delay from internal frame center, and pulse shaping.

2.048 Mbits/s 488 ns

4.096 Mbits/s 244 ns

8.192 Mbits/s 122 ns

16.384 Mbits/s 61 ns

Frame group signals shown with offset = 0 (default). At offset = 0, the pulse starts at frame center. period. Offsets may be programmed in the range from 0—4095. Frame group signals are shown as active high pulses (default)—they may be programmed as active-low pulses. rates (2 Mbits/s, 4 Mbits/s, 8 Mbits/s, or 16 Mbits/s). Figure 27. Frame Group 8 kHz Reference Timing

Agere Systems Inc. 97 Data Sheet May 2001 and Packet Payload Engine Ambassador T8110 PCI-Based H.100/H.110 Switch

8.4.2 FGIO General-Purpose Bits

Any of the T8110 FG signals may be used as general-purpose I/O bits. Each FG bit used as FGIO is configured by enabling the FGIO function via the FGx rate register(s) and setting the direction via the appropriate bits in the FGIO R/W register. For write access to the FGIO, the FGIO data register is used to hold data for output to the FG pin(s). Read accesses are maskable via the FGIO read mask register. For read access from the FGIO, the logical state of the FG[7:0] signals is returned if unmasked. If an FGIO bit is masked, a read access returns 0.

8.4.3 Programmable Timer (FG7 Only)

The FG7 signal can be used as a programmable timer output, via the FG7 mode upper/lower, and FG7 counter high and low byte registers. The FG7 timer is simply a clock divider. The FG7 counter high/low provides a 16-bit [divider value – 1]. Note: [divider value – 1], i.e., a value of 0000000000000011 yields a div-by-4 operation. The FG7 mode lower register enables the counter and selects between two clock sources into the counter: either the T8110 internal frame (8 kHz) or an external clock via the FG6 input. The FG7 mode upper register controls the output pulse shape. The output can be inverted or noninverted and shaped as either a square wave, a carryout pulse, or a programmable-width pulse. /c110 Square wave. This option is applicable only for divide operations that are binary multiples (i.e., div-by-2, div-by- 4, div-by-8, div-by-16, div-by-65536). Nonbinary divide operations while square wave is selected result in a car- ryout pulse. /c110 Carryout pulse. The output is a pulse, width = one FG7 timer clock period. /c110 Programmable-width pulse. The timer output is synchronized to the T8110 32.768 MHz clock domain and can be programmed for 1, 2, 3, or 4, 32.768 MHz clock periods in width (30.5 ns, 61 ns, 91.5 ns, or 122 ns).

8.4.4 FG External Interrupts

All FG signals are internally connected as inputs to the interrupt controller logic. Any FG signal, whether an output or an input, may be used to trigger interrupts. When a T8110 FG signal is used as an externally sourced input into the interrupt controller logic, it must be in input mode (i.e., shut-off, FGx rate register(s) FxRSR = 0000 0000). An FG signal in output mode may also be used for interrupts (i.e., an 8 kHz periodic signal, see Section 8.4.1 on page 96). The interrupt control registers (0x00600—603) control how the FG inputs are handled (for more details, refer to Section 12.1 on page 113).

8.4.5 FG Diagnostic Test Point Observation

Any of the T8110 FG signals may be used to observe a predefined set of internal test-points. Each FG bit used as a test-point output is enabled via diagnostic register 0x00140, FG test-point enable. Settings in this register over- ride the FGx rate and FGIO R/W register, and force the selected bits to be test-point outputs, see Section 13.1 on page 128 and Table 103 on page 128.

9 General-Purpose I/O

9.1 GPIO Control Registers

9.1.1 GPIO Data Register

eral-purpose register bits. Reads from GPIO are maskable, controlled via register 0x00501. Table 75. GPIO Register Table 76. GPIO Data Register 0x00500 GPIO Data Register 7 G7IOB L GPIO bit 7 value.

9 General-Purpose I/O (continued)

9.1.2 GPIO Read Mask Register

on a read access to the GPIO register.

9.1.3 GPIO R/W Register

Table 77. GPIO Read Mask Register Unmask GPIO bit 7 (default). Mask GPIO bit 7, return 0 on a read. Unmask GPIO bit 6 (default). Mask GPIO bit 6, return 0 on a read. Unmask GPIO bit 5 (default). Mask GPIO bit 5, return 0 on a read. Unmask GPIO bit 4 (default). Mask GPIO bit 4, return 0 on a read. Unmask GPIO bit 3 (default). Mask GPIO bit 3, return 0 on a read. Unmask GPIO bit 2 (default). Mask GPIO bit 2, return 0 on a read. Unmask GPIO bit 1 (default). Mask GPIO bit 1, return 0 on a read. Unmask GPIO bit 0 (default). Mask GPIO bit 0, return 0 on a read. Table 78. GPIO R/W Register GPIO bit 7 direction is input (default). GPIO bit 7 direction is output. GPIO bit 6 direction is input (default). GPIO bit 6 direction is output. GPIO bit 5 direction is input (default). GPIO bit 5 direction is output. GPIO bit 4 direction is input (default). GPIO bit 4 direction is output. GPIO bit 3 direction is input (default). GPIO bit 3 direction is output. GPIO bit 2 direction is input (default). GPIO bit 2 direction is output. GPIO bit 1 direction is input (default). GPIO bit 1 direction is output. GPIO bit 0 direction is input (default). GPIO bit 0 direction is output.

9.1.4 GPIO Override Register

9.2 GP Circuit Operation

refer to Figure 28 on page 100. Figure 28. GP[7:0] Functional Paths Table 79. GPIO Override Register 0x00503 GPIO Override 7:3 Reserved 0000 0 NOP (default). GPIO bit 2 is GPIO (default). GPIO bit 2 is PCI_RST# indicator. GPIO bit 1 is GPIO (default). GPIO bit 1 B-master indicator output. GPIO bit 0 is GPIO (default). GPIO bit 0 A-master indicator output.

Agere Systems Inc. 101 Data Sheet May 2001 and Packet Payload Engine Ambassador T8110 PCI-Based H.100/H.110 Switch

9.2.1 GPIO General-Purpose Bits

Any of the T8110 GP signals may be used as general-purpose I/O bits. Each GP bit used as GPIO is configured by setting the direction via the appropriate bits in the GPIO R/W register. For write access to the GPIO, the GPIO data register is used to hold data for output to the GP pin(s). Read accesses are maskable via the GPIO read mask reg- ister. For read access from the GPIO, the logical state of the GP[7:0] signals is returned if unmasked. If a GPIO bit is masked, a read access returns 0.

9.2.2 GP Dual-Purpose Bits GPIO (Override)

9.2.2.1 GP H.110 Clock Master Indicators (GP0, GP1 Only) An additional function is provided for GP0 and GP1 only, controlled via the GPIO override register. GP0 may be used as a dedicated output (set GPIO override register bit 0), which transmits the state of the T8110 A clock master enable (register 0x00220, bit 4). This output is intended to drive the external A clock FETs required for H.110 bus mastering. GP1 may be used as a dedicated output (set GPIO override register bit 1), which transmits the state of the T8110 B clock master enable (register 0x00220, bit 5). This output is intended to drive the external B clock FETs required for H.110 bus mastering.

9.2.2.2 PCI_RST# Indicator (GP2 Only)

An additional function is provided for GP2 only, controlled via the GPIO override register. GP2 may be used as a dedicated output (set GPIO override register bit 2), which forwards the state of the PCI_RST# signal. Polarity of the transmitted signal is selectable via register 0x00780 (refer to Section 11.2 on page 110). This function provides access to a forwarded PCI_RST# signal by external devices hanging off the minibridge port.

9.2.3 GP External Interrupts

Any of the T8110 GP signals may be used as externally sourced inputs into the interrupt controller logic. Each GP bit used as an interrupt input must be shut off by setting the appropriate GPIO R/W register bit to be input. The interrupt control registers (0x00604—607) control how the GP inputs are handled. For more details, see Section 12.1 on page 113.

9.2.4 GP Diagnostic Test Point Observation

Any of the T8110 GP signals may be used to observe a predefined set of internal test-points. Each GP bit used as a test-point output is enabled via diagnostic register 0x00142, GP test-point enable. Settings in this register over- ride the GPIO R/W register and force the selected bits to be test-point outputs (refer to Section 13.1 on page 128, and Table 105 on page 130).

10 Stream Rate Control

There are a total of 64 data streams, divided into 16 stream groups of four streams each, as shown below. The H-bus group operational frequencies are selectable between 2.048 MHz, 4.096 MHz, and 8.192 MHz. Table 80. T8110 Serial Stream Groupings

10 Stream Rate Control (continued)

10.1 H-Bus Stream Rate Control Registers

10.1.1 H-Bus Rate Registers

A—H. The upper nibble controls groups B, D, F, and H. The lower nibble controls groups A, C, E, and G.

10.2 L-Bus Stream Rate Control Registers

10.2.1 L-Bus Rate Registers

streams have a 16.384 MHz rate option (refer to Section 10.2.2 on page 104). Table 81. H-Bus Rate Registers H-bus group B(D, F, H) off (default). H-bus group B(D, F, H) rate = 2.048 MHz. H-bus group B(D, F, H) rate = 4.096 MHz. H-bus group B(D, F, H) rate = 8.192 MHz. H-bus group A(C, E, G) off (default). H-bus group A(C, E, G) rate = 2.048 MHz. H-bus group A(C, E, G) rate = 4.096 MHz. H-bus group A(C, E, G) rate = 8.192 MHz. Table 82. L-Bus Rate Registers L-bus group B(D, F, H) off (default). L-bus group B(D, F, H) rate = 2.048 MHz. L-bus group B(D, F, H) rate = 4.096 MHz. L-bus group B(D, F, H) rate = 8.192 MHz. L-bus group B(D, F, H) rate = 16.384 MHz. L-bus group A(C, E, G) off (default). L-bus group A(C, E, G) rate = 2.048 MHz. L-bus group A(C, E, G) rate = 4.096 MHz. L-bus group A(C, E, G) rate = 8.192 MHz. L-bus group A(C, E, G) rate = 16.384 MHz.

input of the odd stream shift register (refer to Figure 30). Figure 29. Local Stream 16.384 Mbits/s Timing Figure 30. Local Stream 16.384 Mbits/s Circuit

16.384 Mbits/s

the application can have 16 lines, all at 16.384 Mbits/s, in contrast to the 32 I/O lines at normal rates. Figure 31. Superrate I/O Configuration

tions, one for the MS-byte and the other for the LS-byte. Note: n = even number, m = integer. Figure 32. Relationship Between 8.192 Mbits/s and 16.384 Mbits/s Time-Slots and programming a connection from stream n is programming a connection from the LS-byte on input pin n.

8.192 Mbits/s Stream n, Timeslot m

8.192 Mbits/s Stream n + 1, Timeslot m

8.192 Mbits/s input data bits are sampled at 3/4 point (91 ns) of the 122 ns bit time

16.384 Mbits/s input data bits are sampled at 3/4 point (45 ns) of the 61 ns bit time

11 Minibridge

The T8110 provides for access to non-PCI devices from the PCI bus via the minibridge port. the minibridge port pins are used for the microprocessor interface. Refer to Section 5 on page 38. MEMORY transactions (which is the only type of transaction T8110 responds to), the value is always 00. bits [15:0] of PCI_AD during the data phase.

11.1 Wait-State Control Registers

11.1.1 Minibridge Wait-State Control Registers

refer to Figure 29 on page 104. Table 83. Minibridge Wait-State Control Register Map

11 Minibridge (continued)

Table 84. Minibridge Wait-State Control Registers

Table 84. Minibridge Wait-State Control Registers (continued)

11.2 Strobe Control Registers

the GP(2) output) is selectable.

11.3 Minibridge Circuit Operation

asynchronous* control strobes for external devices hanging off the minibridge port. PCI_AD[15:0]. Byte lane enables, PCI_CBEn[3:0], are ignored for minibridge transactions. access cycle descriptions of the minibridge side of the transactions.

• Asynchronous relative to the PCI clock. Strobes are generated relative to the internal chip clock in multiples of 65.536 MHz clock periods.

Table 85. Strobe Control Registers CS7 strobe is active-high (default). CS6 strobe is active-high (default). CS5 strobe is active-high (default). CS4 strobe is active-high (default). CS3 strobe is active-high (default). CS2 strobe is active-high (default). CS1 strobe is active-high (default). CS0 strobe is active-high (default). 0x00781 R/W Strobe Inversion 7:3 Reserved 0000 0 NOP (default). Forward direct PCI_RST# (default). MB_RD strobe is active-high (default). MB_WR strobe is active-high, (default).

Figure 33. Minibridge Read/Write Access Cycles — Delay from valid address to MB_CSn assertion (address wait). — Delay from MB_CSn assertion to the leading edge of the MB_RD (or MB_WR) strobe (setup wait). — Pulse width of the MB_RD (or MB_WR) strobe (width wait). — Delay from MB_RD (or MB_WR) trailing edge to the deassertion of MB_CSn (hold wait). — Delay from deassertion of MB_CSn to address invalid (address wait). (five 65.536 MHz clock cycles). (256 clock cycles) user-programmable via CSn address wait register. (256 clock cycles) user-programmable via CSn address wait register. cycle), maximum = 3.9 µs (256 clock cycles) user-programmable via CSn RD setup wait register.

(256 clock cycles) user-programmable via CSn RD width wait register. (one clock cycle), maximum = 3.9 µs (256 clock cycles) user-programmable via CSn RD hold wait register. — trdsu: read cycle data setup to trailing edge RDn. Minimum = 10 ns. — trdh: read cycle data hold from trailing edge RDn. Minimum = 0 ns. (one clock cycle), maximum = 3.9 µs (256 clock cycles) user-programmable via CSn WR setup wait register. (256 clock cycles) user-programmable via CSn WR width wait register. (one clock cycle), maximum = 3.9 µs (256 clock cycles) user-programmable via CSn WR hold wait register. — twrsu: write cycle data setup to trailing edge of MB_WR. Minimum = 30.5 ns (two clock cycles).

11.4 Minibridge Operational Addressing

ble to create variations of the selected spaces using a minimal amount of external logic. address, and data is set by the parameters for CS3 in PCI registers 0x00730—00737. Table 86. Minibridge Operating Space (PCI)

12 Error Reporting and Interrupt Control

12.1 Interrupt Control Registers

12.1.1 Interrupts Via External FG[7:0] Registers

12.1.1.1 FGIO Interrupt Pending Register

Table 87. Interrupt Control Register Map Table 88. FGIO Interrupt Pending Registers No pending interrupts via FG7 (default). No pending interrupts via FG6 (default). No pending interrupts via FG5 (default). No pending interrupts via FG4 (default). No pending interrupts via FG3 (default). No pending interrupts via FG2 (default). No pending interrupts via FG1 (default). No pending interrupts via FG0 (default).

12 Error Reporting and Interrupt Control (continued)

(negative edge, positive edge, low level, or high level). Disable (mask) interrupts via FG7 (default). Enable (unmask) interrupts via FG7. Disable (mask) interrupts via FG6 (default). Enable (unmask) interrupts via FG6. Disable (mask) interrupts via FG5 (default). Enable (unmask) interrupts via FG5. Disable (mask) interrupts via FG4 (default). Enable (unmask) interrupts via FG4. Disable (mask) interrupts via FG3 (default). Enable (unmask) interrupts via FG3. Disable (mask) interrupts via FG2 (default). Enable (unmask) interrupts via FG2. Disable (mask) interrupts via FG1 (default). Enable (unmask) interrupts via FG1. Disable (mask) interrupts via FG0 (default). Enable (unmask) interrupts via FG0. Table 89. FGIO Edge/Level and Polarity Registers FG7 interrupts are negative edge or low level (default). FG7 interrupts are positive edge or high level. FG6 interrupts are negative edge or low level (default). FG6 interrupts are positive edge or high level. FG5 interrupts are negative edge or low level (default). FG5 interrupts are positive edge or high level. FG4 interrupts are negative edge or low level (default). FG4 interrupts are positive edge or high level. FG3 interrupts are negative edge or low level (default). FG3 interrupts are positive edge or high level. FG2 interrupts are negative edge or low level (default). FG2 interrupts are positive edge or high level. FG1 interrupts are negative edge or low level (default). FG1 interrupts are positive edge or high level. FG0 interrupts are negative edge or low level (default). FG0 interrupts are positive edge or high level. Table 88. FGIO Interrupt Pending Registers (continued)

12.1.2 Interrupts Via External GP[7:0]

12.1.2.1 GPIO Interrupt Pending Register

Table 90. GPIO Interrupt Pending Register No pending interrupts via GP7 (default).

6 JG6OB 0

No pending interrupts via GP6 (default).

5 JG5OB 0

No pending interrupts via GP5 (default).

4 JG4OB 0

No pending interrupts via GP4 (default).

3 JG3OB 0

No pending interrupts via GP3 (default).

2 JG2OB 0

No pending interrupts via GP2 (default).

1 JG1OB 0

No pending interrupts via GP1 (default).

0 JG0OB 0

No pending interrupts via GP0 (default). Disable (mask) interrupts via GP7 (default). Enable (unmask) interrupts via GP7. Disable (mask) interrupts via GP6 (default). Enable (unmask) interrupts via GP6. Disable (mask) interrupts via GP5 (default). Enable (unmask) interrupts via GP5. Disable (mask) interrupts via GP4 (default). Enable (unmask) interrupts via GP4. Disable (mask) interrupts via GP3 (default). Enable (unmask) interrupts via GP3. Disable (mask) interrupts via GP2 (default). Enable (unmask) interrupts via GP2. Disable (mask) interrupts via GP1 (default). Enable (unmask) interrupts via GP1. Disable (mask) interrupts via GP0 (default). Enable (unmask) interrupts via GP0.

12.1.2.2 GPIO Edge/Level and GPIO Polarity Registers

(negative edge, positive edge, low level, or high level).

12.1.3 Interrupts Via Internal System Errors

Table 91. GPIO Edge/Level and GPIO Polarity Registers GP7 interrupts are negative edge or low level (default). GP7 interrupts are positive edge or high level. GP6 interrupts are negative edge or low level (default). GP6 interrupts are positive edge or high level. GP5 interrupts are negative edge or low level (default). GP5 interrupts are positive edge or high level. GP4 interrupts are negative edge or low level (default). GP4 interrupts are positive edge or high level. GP3 interrupts are negative edge or low level (default). GP3 interrupts are positive edge or high level. GP2 interrupts are negative edge or low level (default). GP2 interrupts are positive edge or high level. GP1 interrupts are negative edge or low level (default). GP1 interrupts are positive edge or high level. GP0 interrupts are negative edge or low level (default). GP0 interrupts are positive edge or high level. Table 92. System Error Interrupt Assignments SYS15 Clock failsafe indicator. SYS14 Clock fallback indicator. SYS13 PCI target, minibridge discard timer expired. SYS12 PCI target, VC memory discard timer expired. SYS11 PCI target, data memory discard timer expired. SYS10 PCI target, minibridge protocol error. SYS9 PCI target, VC memory protocol error. SYS8 PCI target, data memory protocol error. SYS7 PCI master, PCI bus fatal error. SYS6 PCI master, external buffer lock error. SYS5 PCI master, external buffer stall error. SYS4 PCI master, external buffer stall warning. SYS3 PCI master, external buffer overwrite warning. SYS2 PCI master, external buffer initial warning. SYS1 VC memory, scratc hpad overflow warning. SYS0 NOTIFY_QUEUE, overflow warning.

12.1.4 System Interrupt Pending High/Low Registers

to Section 6.2.5 on page 59). The user can clear specific bits by writing 1 to that bit (write-1-to-clear). Table 93. System Interrupt Pending High/Low Registers No pending interrupts via SYS7 (default). No pending interrupts via SYS6 (default). No pending interrupts via SYS5 (default). No pending interrupts via SYS4 (default). No pending interrupts via SYS3 (default). No pending interrupts via SYS2 (default). No pending interrupts via SYS1 (default). No pending interrupts via SYS0 (default). No pending interrupts via SYS15 (default). Pending interrupt via SYS15.

6 JSEOB 0

No pending interrupts via SYS14 (default). Pending interrupt via SYS14. No pending interrupts via SYS13 (default). Pending interrupt via SYS13. No pending interrupts via SYS12 (default). Pending interrupt via SYS12.

3 JSBOB 0

No pending interrupts via SYS11 (default). Pending interrupt via SYS11.

2 JSAOB 0

No pending interrupts via SYS10 (default). Pending interrupt via SYS10. No pending interrupts via SYS9 (default). No pending interrupts via SYS8 (default).

12.1.5 System Interrupt Enable High/Low Registers

The system interrupt enable high/low registers allow for masking of interrupts via the internal system error signals. Table 94. System Interrupt Enable High/Low Registers

7 JS7EB 0

Disable (mask) interrupts via SYS7 (default). Enable (unmask) interrupts via SYS7.

6 JS6EB 0

Disable (mask) interrupts via SYS6 (default). Enable (unmask) interrupts via SYS6.

5 JS5EB 0

Disable (mask) interrupts via SYS5 (default). Enable (unmask) interrupts via SYS5.

4 JS4EB 0

Disable (mask) interrupts via SYS4 (default). Enable (unmask) interrupts via SYS4.

3 JS3EB 0

Disable (mask) interrupts via SYS3 (default). Enable (unmask) interrupts via SYS3.

2 JS2EB 0

Disable (mask) interrupts via SYS2 (default). Enable (unmask) interrupts via SYS2.

1 JS1EB 0

Disable (mask) interrupts via SYS1 (default). Enable (unmask) interrupts via SYS1.

0 JS0EB 0

Disable (mask) interrupts via SYS0 (default). Enable (unmask) interrupts via SYS0.

7 JSFEB 0

Disable (mask) interrupts via SYS15 (default). Enable (unmask) interrupts via SYS15.

6 JSEEB 0

Disable (mask) interrupts via SYS14 (default). Enable (unmask) interrupts via SYS14.

5 JSDEB 0

Disable (mask) interrupts via SYS13 (default). Enable (unmask) interrupts via SYS13.

4 JSCEB 0

Disable (mask) interrupts via SYS12 (default). Enable (unmask) interrupts via SYS12.

3 JSBEB 0

Disable (mask) interrupts via SYS11 (default). Enable (unmask) interrupts via SYS11.

2 JSAEB 0

Disable (mask) interrupts via SYS10 (default). Enable (unmask) interrupts via SYS10.

1 JS9EB 0

Disable (mask) interrupts via SYS9 (default). Enable (unmask) interrupts via SYS9.

0 JS8EB 0

Disable (mask) interrupts via SYS8 (default). Enable (unmask) interrupts via SYS8.

12.1.6 Interrupts Via Internal Clock Errors

Table 95. Clock Error Interrupt Assignments CLK15 Failsafe indicator—APLL1 reference error. CLK14 DPLL2 sync input error. CLK13 DPLL1 sync input error.

12.1.7 Clock Interrupt Pending High/Low Registers

Section 6.2.1 on page 56). The user can clear specific bits by writing 1 to that bit (write 1 to clear). Table 96. Clock Interrupt Pending High/Low Registers No pending interrupts via CLK7 (default). No pending interrupts via CLK6 (default). No pending interrupts via CLK5 (default). No pending interrupts via CLK4 (default). No pending interrupts via CLK3 (default). No pending interrupts via CLK2 (default). No pending interrupts via CLK1 (default). No pending interrupts via CLK0 (default). No pending interrupts via CLK15 (default). Pending interrupt via CLK15. No pending interrupts via CLK14 (default). Pending interrupt via CLK14.

5 JCDOB 0

No pending interrupts via CLK13 (default). Pending interrupt via CLK13.

4 JCCOB 0

No pending interrupts via CLK12 (default). Pending interrupt via CLK12. No pending interrupts via CLK11 (default). Pending interrupt via CLK11. No pending interrupts via CLK10 (default). Pending interrupt via CLK10. No pending interrupts via CLK9 (default). No pending interrupts via CLK8 (default).

12.1.8 Clock Interrupt Enable High/Low Registers

The clock interrupt enable high/low registers allow for masking of interrupts via the internal clock error signals. Table 97. Clock Interrupt Enable High/Low Registers Disable (mask) interrupts via CLK7 (default). Enable (unmask) interrupts via CLK7. Disable (mask) interrupts via CLK6 (default). Enable (unmask) interrupts via CLK6. Disable (mask) interrupts via CLK5 (default). Enable (unmask) interrupts via CLK5. Disable (mask) interrupts via CLK4 (default). Enable (unmask) interrupts via CLK4. Disable (mask) interrupts via CLK3 (default). Enable (unmask) interrupts via CLK3. Disable (mask) interrupts via CLK2 (default). Enable (unmask) interrupts via CLK2. Disable (mask) interrupts via CLK1 (default). Enable (unmask) interrupts via CLK1. Disable (mask) interrupts via CLK0 (default). Enable (unmask) interrupts via CLK0. Disable (mask) interrupts via CLK15 (default). Enable (unmask) interrupts via CLK15.

6 JCEEB 0

Disable (mask) interrupts via CLK14 (default). Enable (unmask) interrupts via CLK14.

5 JCDEB 0

Disable (mask) interrupts via CLK13 (default). Enable (unmask) interrupts via CLK13.

4 JCCEB 0

Disable (mask) interrupts via CLK12 (default). Enable (unmask) interrupts via CLK12.

3 JCBEB 0

Disable (mask) interrupts via CLK11 (default). Enable (unmask) interrupts via CLK11.

2 JCAEB 0

Disable (mask) interrupts via CLK10 (default). Enable (unmask) interrupts via CLK10. Disable (mask) interrupts via CLK9 (default). Enable (unmask) interrupts via CLK9. Disable (mask) interrupts via CLK8 (default). Enable (unmask) interrupts via CLK8.

12.1.9 Interrupt Servicing Registers

12.1.9.1 Arbitration Control Register

a simple logical OR of the internal clock error bits. ority encodes between the three levels. Multiple interrupts within a level are queued round-robin. rupt according to the three priority levels.

12.1.10 PCI_INTA Output Select Register

12.1.10.1 SYSERR and CLKERR Output Select Register

level, active-high pulse, or active-low pulse). low pulse). Value corresponds to the number of 32.768 MHz periods – 1. level, active-high pulse, or active-low pulse). low pulse). Value corresponds to the number of 32.768 MHz periods – 1. Table 98. Arbitration Control Register Disable interrupt controller (default). Flat structure (round-robin arbiter). Tier structure (three levels), no pre-empting. Tier structure (three levels), pre-empting. Table 99. PCI_INTA Output Select Register Do not route SYSERR to PCI_INTA (default).

clock) pending bits are cleared.

12.1.10.2 Interrupt In-Service Registers

48 possible interrupts is currently in-service. Table 100. SYSERR Output Select Registers SYSERR is active-high level* (default). SYSERR is active-low level*. SYSERR is active-high single pulse. SYSERR is active-low single pulse. 0x00616 SYSERR Pulse Width 7:0 JSWSR LLLL LLLL SYSERR pulse-width value. CLKERR is active-high level* (default). CLKERR is active-low level*. CLKERR is active-high single pulse. CLKERR is active-low single pulse. 0x00617 CLKERR Pulse Width 7:0 JCWSR LLLL LLLL CLKERR pulse-width value. Table 101. Interrupt In-Service Register No interrupt in-service (default).

0x0061A Interrupt In-service, Byte 2 7:0 LLLL LLLL Low-byte, virtual channel identifier. 0x0061B Interrupt In-service, Byte 3 7:1 0000 000 NOP . 0 L MS bit, virtual channel identifier. Table 101. Interrupt In-Service Register (continued)

12.2 Error Reporting and Interrupt Controller Circuit Operation

the system is also selectable. Figure 34. Interrupt Controller

126 Agere Systems Inc. Data Sheet May 2001and Packet Payload Engine Ambassador T8110 PCI-Based H.100/H.110 Switch

12.2.1 Externally Sourced Interrupts Via FG[7:0], GP[7:0]

Up to 16 of the 48 interrupt inputs are sourced external to the T8110, via the FG[7:0] and GP[7:0] signals. Each input is independently controlled via the interrupt control registers (refer to Section 12.1.1 on page 113 and Section 12.1.2 on page 115). Any externally sourced interrupt may be presented as active-high level, active-low level, pos- itive edge, or negative edge sense. Each external interrupt is maskable. Any detected interrupt which is unmasked is held in an interrupt pending register, and presented to the arbitration circuit for servicing.

12.2.2 Internally Sourced System Error Interrupts

Another set of 16 of the 48 interrupt inputs are sourced internally via the system error register bits (0x00126—127; refer to Section 6.2.5 on page 59). Each of these inputs is independently controlled via the interrupt control regis- ters (refer to Section 12.1.3 on page 116). All internal system error bit interrupts are presented as active-high level sense. Each system error bit interrupt is maskable. Any detected interrupt which is unmasked is held in an interrupt pending register and presented to the arbitration circuit for servicing.

12.2.3 Internally Sourced Clock Error Interrupts

Another set of 16 of the 48 interrupt inputs are sourced internally via the latched clock error register bits (0x00122—123; refer to Section 6.2.1 on page 56). Each of these inputs is independently controlled via the inter- rupt control registers (refer to Section 12.1.6 on page 119). All internal clock error bit interrupts are presented as active-high level sense. Each clock error bit interrupt is maskable. Any detected interrupt that is unmasked is held in an interrupt pending register and presented to the arbitration circuit for servicing.

12.2.4 Arbitration of Pending Interrupts

The arbitration of the pending interrupts can be handled in one of four selectable modes: arbitration off, flat arbitra- tion, tier arbitration with pre-empting disabled, and tier arbitration with pre-empting enabled. Interrupts are reported to the system via the SYSERR signal (and the PCI_INTA# signal, if enabled to do so).

12.2.4.1 Arbitration Off

This mode only allows the 16 internal system error register bits to generate interrupts, and no arbitration takes place. The trigger for the SYSERR output is simply a logical OR of the internal system error register bits. All bits of the internal system error register must be cleared in order to rearm the SYSERR trigger in this mode.

12.2.4.2 Flat Arbitration

The flat arbitration mode performs a round-robin arbitrations on all 48 interrupt sources. When a pending interrupt wins the arbitration, the in-service register is loaded with its corresponding interrupt vector, SYSERR is triggered, and that pending bit is cleared, removing it from the next round-robin arbitration cycle. The system must respond to the current in-service interrupt (refer to Section 12.2.8 on page 127), after which the next arbitration cycle takes place.

12.2.4.3 Tier Arbitration

The tier arbitration creates three prioritized groups as shown below: /c110 Highest priority. The 16 internal latched clock error register bits. /c110 Next highest priority. The 16 internal system error register bits. /c110 Lowest priority. The 16 external FG[7:0] and GP[7:0] bits.

Agere Systems Inc. 127 Data Sheet May 2001 and Packet Payload Engine Ambassador T8110 PCI-Based H.100/H.110 Switch Arbitration assigns interrupt servicing priority to the three groups. Multiple pending interrupts within the same group are arbitrated round-robin. When a pending interrupt wins the arbitration, the in-service register is loaded with its corresponding interrupt vector, SYSERR is triggered, and that pending bit is cleared, removing it from the next arbitration cycle.

12.2.4.3.1 Pre-Empting Disabled

With pre-empting disabled, once a pending interrupt wins the arbitration and the in-service register is loaded with its corresponding interrupt vector, new incoming pending interrupts of higher priority must wait for the system to respond to the current in-service interrupt (refer to Section 12.2.8 on page 127), at which time another arbitration cycle takes place.

12.2.4.3.2 Pre-Empting Enabled

With pre-empting enabled, an interrupt that is in-service (i.e., its interrupt vector is loaded in the in-service register and SYSERR has been triggered) can be overridden by new incoming pending interrupts of higher priority. The current in-service interrupt is pushed onto a stack for storage; the higher-priority interrupt vector is loaded into the in-service register and SYSERR is retriggered. Once all interrupts of higher priority have been serviced by the sys- tem (refer to Section 12.2.8 on page 127), the stack is popped and the original lower-priority interrupt is reissued.

12.2.5 CLKERR Output

The CLKERR output signal is used to indicate any internal clocking errors. The trigger for the CLKERR output is simply a logical OR of the internal latched clock error register bits. All bits of the internal clock error register must be cleared in order to rearm the CLKERR trigger. The CLKERR trigger induces a state machine to generate the CLKERR signal in one of four possible ways: active-high level, active-low level, active-high single pulse, or active- low single pulse.

12.2.6 SYSERR Output

The T8110 SYSERR output signal is used to report interrupts. Internally, the arbitration circuit provides a SYSERR trigger, which induces a state machine to generate the SYSERR signal in one of four possible ways: active-high level, active-low level, active-high single pulse, or active-low single pulse.

12.2.7 PCI_INTA# Output

The internal SYSERR trigger can be enabled to also trigger a PCI interrupt via the PCI_INTA# signal.

12.2.8 System Handling of Interrupts

The T8110 interrupt controller presents an interrupt to the system by triggering the SYSERR output and providing a predefined interrupt vector value at the interrupt in-service register (ISR). The system may acknowledge the interrupt in three ways as shown below: /c110 System reads the T8110 ISR register. This allows the arbiter to advance, and if more pending interrupts are active, reloads the ISR with the winner of the arbitration and retriggers SYSERR. /c110 System clears the T8110 ISR register (via register 0x00100, soft reset; write 0x20 clears the ISR). The arbiter advances, and if more pending interrupts are active, reloads the ISR and retriggers SYSERR. /c110 System resets the interrupt controller (via register 0x00100, soft reset, write 0x10 clears the ISR and all the pending interrupt registers). All pending interrupts are cleared, and the arbiter is reset.

13 Test and Diagnostics

13.1 Diagnostics Control Registers

The diagnostic control registers allow for various diagnostic modes (refer to Section 13.2 on page 135).

13.1.1 FG Testpoint Enable Register

selected. Refer to Table 104 on page 129 for test-point assignments for each FG bit. Table 102. Diagnostics Control Register Map Table 103. FG Testpoint Enable Registers FG7 is standard FG or FGIO bit (default). FG6 is standard FG or FGIO bit (default). FG5 is standard FG or FGIO bit (default). FG4 is standard FG or FGIO bit (default). FG3 is standard FG or FGIO bit (default). FG2 is standard FG or FGIO bit (default). FG1 is standard FG or FGIO bit (default). FG0 is standard FG or FGIO bit (default).

13 Test and Diagnostics (continued)

13.1.2 GP Testpoint Enable Register

GPIO) or as test-point outputs. GP test-point select controls the MUX selection for which test-points are selected. Refer to Table 106 on page 131 for test-point assignments for each GP bit. Table 104. FG[7:0] Internal Testpoint Assignments

Table 105. Testpoint Enable Registers GP7 is standard GPIO bit (default). GP6 is standard GPIO bit (default). GP5 is standard GPIO bit (default). GP4 is standard GPIO bit (default). GP3 is standard GPIO bit (default). GP2 is standard GPIO bit (default). GP1 is standard GPIO bit (default). GP0 is standard GPIO bit (default).

Table 106. GP[7:0] Internal Testpoint Assignments

8 MHz tap

4 MHz tap

2 MHz tap

13.1.3 State Counter Modes Registers

modulo function. For more details, refer to Section 13.2 on page 135. Table 107. State Counter Modes Registers 7:6 Reserved 00 NOP (default). Normal carry chain operation (default). Break state counter carry chains. Normal internal frame operation (default). Use /FR_COMP as internal frame. State counter modulo counting.

13.1.4 Miscellaneous Diagnostics Low Register

Table 108. Miscellaneous Diagnostics Low Register 7:6 Reserved 00 NOP (default). PCI target discard timers normal (default). PCI target discard timers shortened. Microprocessor access to VC memory enabled.

2 FB2SB 0

APLL2 feedback divider reset inactive (default). APLL2 feedback divider reset active.

1 FB1SB 0

APLL1 feedback divider reset inactive (default). APLL1 feedback divider reset active.

0 Reserved ——

13.1.5 External Buffer Retry Timer Register

Table 109. External Buffer Retry Timer Register Interrupt controller, normal mode (default). Interrupt controller, DIAG mode. 5:4 ICKLP LL DIAG mode, force CLK[1:0] errors. 3:2 ISYLP LL DIAG mode, force SYS[1:0] errors. 1:0 IEXLP LL DIAG mode, force EXT[8, 0] errors. Disable delay mode (default).

Agere Systems Inc. 135 Data Sheet May 2001 and Packet Payload Engine Ambassador T8110 PCI-Based H.100/H.110 Switch

13.2 Diagnostic Circuit Operation

The T8110 internal diagnostic modes are intended primarily for chip manufacturing test. The diagnostic functions include the following: /c110 DIAG0—3, observability of internal test-points via FG(7:0), GP(7:0): — Internal test-points are brought to chip I/O at FG and GP signals. Refer to Table 104 on page 129 and Table 106 on page 131 for test-point assignment. /c110 DIAG4—5, internal state counter diagnostic modes: — Break counter carry chains—this is used in conjunction with monitoring of the state counter bits at FG and GP , and breaks the 11-bit state counter into three separate pieces (bits [10:8], [7:4] and [3:0]). — Shorten frame operation—the internally generated 8 kHz frame is bypassed in favor of the /FR_COMP input. The /FR_COMP input still denotes the frame center and may be presented at a higher frequency than 8 kHz. This is used in conjunction with the state counter modulo function, which when properly programmed allows the internal state counter to roll over coincident with the /FR_COMP frame center. /c110 DIAG6, microprocessor access to the virtual channel memory and minibridge register regions: — The VC memory region is only functionally applicable for packet payload switching, which is only available when the T8110 interface to a local PCI bus is selected. When interface to microprocessor bus is selected, this diagnostic setting allows direct access to the virtual channel memory. — The minibridge registers are only functionally applicable for minibridge port operation and are only available when the T8110 interface to a local PCI bus is selected. When interface to microprocessor bus is selected, this diagnostic setting allows direct access to the minibridge registers. /c110 DIAG6, forced RESET of analog APLL1 feedback dividers: — The APLL1 feedback dividers are typically not reset. This diagnostic mode allows each feedback divider to be held in a reset state. /c110 DIAG7, external buffer RETRY timer: — The external buffer access protocol allows for one RETRY of a descriptor table fetch in the case of a locked external buffer. This diagnostic register allows for manipulation of the amount of time to wait before retrying a /c110 DIAG8, interrupt controller diagnostics: — When the diagnostic mode is enabled (DIAG8 register, bits 7:6 = 01), then bits 5:4 override the CLK error[1:0] inputs, bits [3:2] override the SYS error[1:0] inputs, bit 1 overrides the GP[0] input, and bit 0 overrides the FG[0] input to the interrupt controller. This allows for direct manipulation to set/clear a portion of interrupt bits from each tier group. Please see Section 12.2 on page 125 for more details. /c110 DIAG9, interrupt controller deassertion delay: — Allows a programmable deassertion time for the SYSERR signal in between back-to-back interrupts. /c110 DIAG10—11, sync-to-frame command delay: — Allows a programmable delay time from the FRAME boundary for execution of the sync-to-frame clock com- mands, GO_CLOCKS, CLEAR_FALLBACK, FORCE_FALLBACK.

14 Connection Control—Standard and Virtual Channel

14.1 Programming Interface

ters) is made through a standard direct access via the interface (described starting in Section 4 on page 22).

14.1.1 PCI Interface

14.1.1.1 PCI Connection Memory Programming

that gets addressed during a burst, the user must disable all the byte enables for that particular data phase. presented as a PCI memory WRITE command; refer to Figure 35. /c110 MAKE/BREAK/QUERY— telephony connection; refer to Figure 36. /c110 MAKE/BREAK/QUERY— virtual channel nonbonded connection; refer to Figure 37. /c110 MAKE/BREAK/QUERY— virtual channel bonded connection; refer to Figure 38. are presented as PCI memory read commands. Figure 35. PCI Programming—Reset Page Command

14 Connection Control—Standard and Virtual Channel (continued)

Figure 36. PCI Programming—Make/Break/Query Telephony Connection Figure 37. PCI Programming—Make/Break/Query Virtual Channel Nonbonded Connection

Figure 38. PCI Programming—Make/Break/Query Virtual Channel Bonded Connection

14.1.1.2 PCI Virtual Channel Memory Programming

/c110 A WRITE is presented as a PCI memory write command Figure 39 below. /c110 A READ STATIC is presented as a PCI memory read command (see Figure 40 on page 139). /c110 A READ SCRATCHPAD is presented as a PCI memory read command (see Figure 41 on page 139). Figure 39. PCI Programming—Write Virtual Channel Command

1 TO 64 DWORDS DEEP

Figure 40. PCI Programming—Read Virtual Channel Static Command Figure 41. PCI Programming—Read Virtual Channel Scratchpad Command

14.1.2 Microprocessor Interface

interface, included for diagnostic purposes only.

14.1.2.1 Microprocessor Connection Memory Programming

OFFSET WITHIN CHANNEL BUFFER.

nection memory locations are addressed relative to time slot and stream. /c110 MAKE/BREAK/QUERY , telephony connection (see Figure 43 on page 141). /c110 MAKE/BREAK/QUERY , virtual channel nonbonded connection* (see Figure 44 on page 142). /c110 MAKE/BREAK/QUERY , virtual channel bonded connection* (see Figure 45 on page 143). is presented as multiple microprocessor read cycles; refer to Table 110.

• Making virtual channel connections in the connection memory is for diagnostic purpose only when the microprocessor interface is selected.

Note: Data byte n required information is shown in Figure 43—Figure 45. Table 110. Microprocessor Programming, Connection Memory Access nection memory, or read data byte 3 information. data bytes 1 and 0 information.

Figure 42. Microprocessor Programming—Reset Page Command Figure 43. Microprocessor Programming—Make/Break/Query Telephony Connections

Figure 44. Microprocessor Programming—Make/Break/Query Virtual Channel Nonbonded Connections

Figure 45. Microprocessor Programming—Make/Break/Query Virtual Channel Bonded Connection

14.1.2.2 Microprocessor Virtual Channel Memory Programming

two address bits [1:0] and holding registers. For byte access, there are a total of three byte-wide holding registers. /c110 The WRITE command is presented as a microprocessor write cycle (see Figure 46 on page 145). /c110 The READ STATIC command is presented as a microprocessor read cycle (see Figure 47 on page 145). /c110 The READ SCRATCHPAD command is presented as a microprocessor read cycle (see Figure 48 on page 146). Note: Data byte n required information is shown in Figure 46—Figure 48. Table 111. Virtual Channel Memory Access read data bytes 1 and 0 information.

Figure 46. Microprocessor Programming—Write Virtual Channel Memory Command Figure 47. Microprocessor Programming—Read Virtual Channel Static Command

Figure 48. Microprocessor Programming—Read Virtual Channel Scratchpad Command

14.2 Switching Operation

transfers between the data memory and an external buffer in the PCI space.

14.2.1 Memory Architecture and Configuration

14.2.1.1 Connection Memory

(1 bit), and stream (5 bits).

Agere Systems Inc. 147 Data Sheet May 2001 and Packet Payload Engine Ambassador T8110 PCI-Based H.100/H.110 Switch Each of these connection memory pages are initialized at reset (valid bit entries are reset to invalid). Additionally, each page may be initialized individually via software command, RESET PAGE (refer to Figure 35 on page 136 and Figure 42 on page 141). For standard telephony switching connections, the connection memory locations contain one-half simplex switch control information (refer to Figure 36 on page 137 and Figure 43 on page 141), as follows: /c110 VALID bit indicates that a valid switch connection exists for this stream/time-slot. /c110 VTC indicates whether the connection is a virtual channel connection or a telephony connection. A 0 denotes a telephony connection. /c110 RWS indicates whether the connection is from (from serial stream to data memory) or to (from DATA memory to serial stream). /c110 VFC (virtual framing control) controls which data page is used in double-buffer scenarios. Note:There are three data memory configurations that allow double-buffering of the data, in order to create con- /c110 PME indicates a pattern mode connection. /c110 TAG is the data memory location used for this one-half simplex switch connection (or the data pattern sent to serial output for pattern mode connections). /c110 SUBRATE information is subrate switching control (bitswap). For virtual channel (packet payload) switching connections, there are two possible control fields, depending on whether the virtual channel is nonbonded (refer to Figure 37) or bonded (refer to Figure 38).

14.2.1.1.1 Virtual Channel Switching, Nonbonded Connections

/c110 VALID bit indicates that a valid switch connection exists for this stream/time slot. /c110 VTC indicates whether the connection is a virtual channel connection or a telephony connection. A 1 denotes a virtual channel connection. /c110 RWS indicates whether the connection is from (from serial stream to data memory) or to (from DATA memory to serial stream). /c110 BVF is bonded virtual frame marker (unused for nonbonded channels). /c110 BCC is bonded channel control indicator; 0 denotes a nonbonded channel. /c110 VC identifier and VCP indicates which virtual channel this information is for (0 up to 511 virtual channels). /c110 SVF (subrate virtual frame marker) is an indicator for the last piece of a packed subrate byte. /c110 SUBRATE information is subrate switching control (bitswap); refer to Section 14.2.2.3.

14.2.1.1.2 Virtual Channel Switching, Bonded Connections

/c110 VALID bit indicates that a valid switch connection exists for this stream/time slot. /c110 VTC indicates whether the connection is a virtual channel connection or a telephony connection. A 1 denotes a virtual channel connection. /c110 RWS indicates whether the connection is from (from serial stream to data memory) or to (from data memory to serial stream). /c110 BVF (bonded virtual frame marker) is an indicator for the last byte switched in a frame.

/c110 BCC (bonded channel control indicator), a 1 denotes a bonded channel. /c110 VC identifier and VCP indicates which virtual channel this information is for (0 up to 511 virtual channels). /c110 Bonded channel depth defines how many bytes within one frame are switched. /c110 Bonded channel offset is a specific data memory pointer offset for the data byte related to this connection.

14.2.1.2 Data Memory

Figure 49. T8110 Data Memory Map and Configurations

Agere Systems Inc. 149 Data Sheet May 2001 and Packet Payload Engine Ambassador T8110 PCI-Based H.100/H.110 Switch

14.2.1.3 Virtual Channel Memory

The T8110 virtual channel memory consists of 512 locations, one location for each possible virtual channel. Virtual channel memory consists of two portions, static and scratchpad, and controls how the VC portion of the data mem- ory is partitioned when the data memory is configured to allow for virtual channels (refer to Figure 49). The data memory partition for a virtual channel is defined by the static portion of the virtual channel memory (refer to Figure 39 and Figure 40), which includes the following information: /c110 SBA (static base address) is the physical start address for this particular virtual channel in the data memory VC space. /c110 STD (static depth) is the total number of bytes (in DWORDS) allotted for this virtual channel. A virtual channel can occupy 2 DWORDS (minimum) up to 64 DWORDS (maximum) in the data memory VC space. The scratchpad portion of the virtual channel memory (refer to Figure 39 and Figure 41) keeps track of the current data memory address within the data memory partition as follows: /c110 SPCD (scratchpad current depth) is the current number of bytes transferred to/from serial streams. /c110 SPCO (scratchpad current offset) is the data memory address pointer.

14.2.2 Standard Switching

Standard telephony switching is achieved by loading control fields into the connection memory for one-half simplex connections (refer to Figure 36 on page 137, Figure 43 on page 141, and Section 14.2.1.1 on page 146).

14.2.2.1 Constant Delay and Minimum Delay Connections

The VFC control bit in connection memory determines which of two data pages is accessed, when the data mem- ory is configured to double-buffering for telephony connections (refer to Figure 49). This bit always affects to con- nections (read the data memory, send it out to a serial stream output) in a double-buffer configuration. This bit can control a from connection in a double-buffer configuration, only if it is a subrate connection; otherwise, the VFC bit has no bearing on from connections. The double-buffering configuration creates two data pages. During a particular frame (125 µs time boundary, parti- tioned into time-slots), one page is the active page, the other is the inactive page. The active/inactive page status toggles at every frame boundary. For all from connections (except for subrate connections), incoming serial data is always written to the active page. For all to connections, the VFC control bit indicates whether to read from the active or inactive page. Manipulation of this bit affects the latency between the incoming from data and the outgo- ing to data. This latency defines whether or not a connection is constant delay or minimum delay. Please see Appendix A on page 190 for more details on constant and minimum delay connections.

14.2.2.2 Pattern Mode

The PME control bit in connection memory affects only to connections. Instead of reading a value out of the data memory for subsequent output to a serial stream, the lower 8 bits of the TAG field provide a byte pattern for the serial output.

14.2.2.3 Subrate

The subrate control bit field in connection memory is used only by from connections and controls how individual bits or groups of bits of an incoming serial byte are shuffled prior to writing them to the data memory, in order to achieve subrate switching.

14.2.2.3.1 Subrate Switching Overview

TDM stream bit rate. A particular channel occurs once every 8 kHz frame, and there are 8K frames per second. This allows for a channel data propagation rate of (8 bits/frame * 8K frames/s = 64 Kbits/s). Refer to Figure 50 and Table 113. Figure 50. TDM Data Stream Bit Rates channel capacity for a given time-slot. Refer to Table 112 and Table 113. Bit subrate = 8 channels per time slot, 1 bit per channel. Di-bit = 4 channels per time slot, 2 bits per channel. Nibble subrate = 2 channels per time slot, 4 bits per channel. Byte (no subrate) = 1 channel per time slot, 8 bits per channel. Table 112. TDM Data Stream

64 TIME SLOTS (CHANNELS) PER FRAME

32 TIME SLOTS (CHANNELS) PER FRAME

8 MBITS/S

4 MBITS/S

2 MBITS/S

128 TIME SLOTS (CHANNELS) PER FRAME

14.2.2.3.2 Subrate Switching Using T8110

data, from and to (refer to Figure 36 on page 137, Figure 43 on page 141, and Table 114). Table 113. Subrate Switching, Data Propagation Rate vs. Channel Capacity Table 114. Subrate Switching, Connection Memory Programming Setup

14.2.2.3.3 Subrate Packing of Outgoing Bytes

a byte that will be output as defined by the to connection. Figure 48. This example shows the packing of four separate incoming di-bits from four different channels into one outgoing byte on one channel. Note: Please note the limitation that multiple di-bits from the same time slot cannot be switched simultaneously. Table 114. Subrate Switching, Connection Memory Programming Setup (continued)

/c110 From stream a, time slot n, bits[1:0] to stream e, time slot n + 10, bits[7:6]. /c110 From stream b, time slot n + 1, bits[1:0] to stream e, time slot n + 10, bits[3:2]. /c110 From stream c, time slot n + 2, bits[3:2] to stream e, time slot n + 10, bits[1:0]. /c110 From stream d, time slot n + 3, bits[5:4] to stream e, time slot n + 10, bits[5:4]. Five 1/2 simplex connections are required to pack four incoming di-bits into an outgoing byte. /c110 From stream a, time slot n. Connection memory subrate field = 0100X11. /c110 From stream b, time slot n + 1. Connection memory subrate field = 0100X01. /c110 From stream c, time slot n + 2. Connection memory subrate field = 0101X00. /c110 From stream d, time slot n + 3. Connection memory subrate field = 0110X10. /c110 To stream e, time slot n + 10. Connection memory subrate field is don't care. Figure 51. Subrate Switching Example, Byte Packing

14.2.2.3.4 Subrate Unpacking of Incoming Bytes

of the packed byte created in Figure 51, output to four different channels.

From stream e, time slot n + 3, bits[1:0] to stream j, time slot n + 8, bits[7:6]. From stream f, time slot n + 5, bits[3:2] to stream i, time slot n + 8, bits[5:4]. From stream f, time slot n + 6, bits[5:4] to stream h, time slot n + 8, bits[1:0]. From stream f, time slot n + 7, bits[7:6] to stream g, time slot n + 8, bits[7:6]. Eight 1/2 simplex connections are required to unpack one incoming byte to four separate outgoing di-bits. From stream e, time slot n + 3. Connection memory subrate field = 0100X11. From stream f, time slot n + 5. Connection memory subrate field = 0101X10. From stream f, time slot n + 6. Connection memory subrate field = 0110X00. From stream f, time slot n + 7. Connection memory subrate field = 0111X11. To stream g, time slot n + 8. Connection memory subrate field is don't care. To stream h, time slot n + 8. Connection memory subrate field is don't care. To stream i, time slot n + 8. Connection memory subrate field is don't care. To stream j, time slot n + 8. Connection memory subrate field is don't care. Figure 52. Subrate Switching Example, Byte Unpacking

4 X X X

4 X X

3 X X X

Agere Systems Inc. 155 Data Sheet May 2001 and Packet Payload Engine Ambassador T8110 PCI-Based H.100/H.110 Switch

14.2.3 Virtual Channel (Packet Payload) Switching

Packet payload switching is achieved by loading control fields into the connection memory for one-half simplex connections (refer to Figure 37 and Figure 38) and loading control fields for a corresponding virtual channel into the virtual channel memory (refer to Figure 39—Figure 41). A virtual channel connection consists of the following two parts: /c110 A one-half simplex connection to (or from) a channel (or channels) in the H1x0 or local bus TDM switching domain. These connections are made in a similar manner to standard telephony switching connections—by loading the proper control fields into the T8110 connection memory (refer to Section 14.2.1.1, Figure 38, and Figure 39). There are two types of virtual channel connections: nonbonded refers to switching of a single TDM channel each frame, bonded refers to switching of multiple TDM channels each frame. Additionally, subrate /c110 A store-and-forward buffer that has access from (or to) an external buffer which is defined somewhere in the Depending on the data memory configuration (refer to Figure 49), there can be as many as 512 unique virtual channels defined simultaneously (using all 4 Kbytes of the available space). Configuration of the data memory space for virtual channels is achieved by loading control fields into the virtual channel memory (refer to Section The above two parts define a virtual channel. Each virtual channel can be either: /c110 From TDM domain to PCI domain. The data flow from incoming serial TDM data to the PCI external buffer is referred to as PUSH. In this case, the T8110 controls writes to the external buffer. Another agent on the PCI bus (such as a coprocessor) would control the reads from the external buffer. The handshake between the T8110 and the other agent is described in Section 14.2.3.4. /c110 From PCI domain to TDM domain. The data flow from the PCI external buffer to outgoing serial TDM data is referred to as PULL. In this case, the T8110 controls reads from the external buffer. Another agent on the PCI bus (such as a coprocessor) would control the writes to the external buffer. The handshake between the T8110 and the other agent is described in Section 14.2.3.4.

14.2.3.1 Nonbonded Channels

A nonbonded virtual channel means that only one byte of information per 8 kHz frame is switched in the TDM domain for that channel. The T8110 data memory configuration for any virtual channel holds multiple data bytes at a time (minimum of 8 bytes, maximum of 256 bytes, in increments of 4 bytes). Since only 1 byte per frame is switched, the data memory depth defined for a nonbonded virtual channel directly corresponds to the number of TDM frames worth of data stored at one time. The concept is illustrated in Figure 53 and in Figure 54.

Figure 53. Nonbonded Virtual Channel in the PUSH Direction

8 BYTES HAVE BEEN

WRITTEN TO THE DATA MEMORY (IT IS FULL). CURRENT DEPTH = OVERALL CHANNEL DEPTH = 8. INITIAL STATE FOR THIS CHANNEL.

8 FRAMES AT 1 BYTE

Figure 54. Nonbonded Virtual Channel in the PULL Direction

14.2.3.2 Subrate

READ FROM THE DATA MEMORY (IT IS EMPTY). CURRENT DEPTH = OVERALL CHANNEL DEPTH = 8.

8 FRAMES AT 1 BYTE PER FRAME,

Figure 55. Nonbonded Virtual Channel with Subrate and Packed Bytes

14.2.3.3 Bonded Channels

depends on the number of bytes switched per frame, plus the overall data memory depth defined for that channel. byte switched in a frame. The concept is illustrated in Figure 56 and in Figure 57. WRITTEN TO THE DATA MEMORY (IT IS FULL).

Figure 56. Bonded Virtual Channel in the PUSH Direction

128 BYTES HAVE BEEN

WRITTEN TO THE DATA MEMORY (IT IS FULL). CURRENT DEPTH = OVERALL CHANNEL DEPTH = 128.

16 FRAMES AT 8 BYTES PER FRAME,

Figure 57. Bonded Virtual Channel in the PULL Direction

14.2.3.4 External Buffer Access

14.2.3.4.1 Overview

further discussion, the other PCI bus agent will be referred to as the USER . /c110 The total allotment does not exceed 4096 bytes. READ FROM THE DATA MEMORY (IT IS EMPTY). CURRENT DEPTH = OVERALL CHANNEL DEPTH = 128.

For a virtual channel in the push direction, the T8110 fills its internal buffer with incoming TDM serial stream data. Once the internal buffer for that channel is full, the T8110 initiates a burst transfer of that data to the external buffer. For a virtual channel in the pull direction, the T8110 empties its internal buffer to outgoing TDM serial stream data.

14.2.3.4.2 Descriptor Table

table is (512 * 8) = 4 Kbytes. A descriptor table entry contains the following information. channel (DWORD-aligned). This region is read-only for T8110, read-write for the USER . circular (T8110 must stop at end of buffer). — L, lock. This determines whether the T8110 is allowed access to the external buffer for this virtual channel. /c110 UOR. This is a USER -updated offset pointer within the defined 4K external buffer space for this virtual channel. both the T8110 and the USER . write for both the T8110 and the USER . Table 115. Descriptor Table

14.2.3.4.3 External Buffer

internal buffer size for a given virtual channel.

14.2.3.4.4 Transfer Protocol

table control and status flags shows the external buffer not accessible by the T8110. nal buffer data transfer, and what value(s) to update the descriptor table with). Refer to Figure 58 and Table 116. Table 116. Descriptor Table GBS Status Descriptions 000 USER has initialized the external buffer. 001 T8110 has completed with normal status. 010 T8110 has completed with a boundary condition. 011 T8110 has overwritten a portion of the external buffer unread by USER. 100 USER has initialized the T8110 pointer (TF and TOR). 101 T8110 did not complete due to a locked buffer. 110 T8110 did not complete due to stalled buffer (boundary condition). 111 USER has disabled the external buffer.

Figure 58. Descriptor Table Fetch Decode

164 Agere Systems Inc. Data Sheet May 2001and Packet Payload Engine Ambassador T8110 PCI-Based H.100/H.110 Switch

14.2.3.4.5 External Buffer Data Transfer

After the descriptor table fetch, the T8110 then does the following: /c110 It either dumps its internal buffer of gathered TDM data to the external buffer space (push , a PCI memory write burst of internal buffer size) /c110 Or fetches data from the external buffer space into its internal buffer for outgoing TDM data (pull, a PCI memory read burst of internal buffer size). /c110 Or skips the external buffer data transfer (based on descriptor table status, such as a pointer stall, end-of-buffer stall, buffer locked status, which indicate that the external buffer is not currently available to the T8110).

14.2.3.4.6 Descriptor Table Update

The T8110 then updates the descriptor table (second DWORD only), with values calculated based on the descrip- tor table fetch results. The only allowable portions writable by T8110 include the GBS status, TF, and TOR. The transfer is a PCI memory write of 1 DWORD.

14.2.3.5 T8110 Packet Switching, Circuit Operation

Each programmed T8110 virtual channel operates independently, and tracks both its current position in the T8110 internal buffer space and the buffer full (push ) or empty (pull) status, in the scratchpad portion of the virtual chan- nel memory (refer to Section 14.2.1.3). Upon determination of a full (or empty) internal buffer, that channel places an entry into a notify queue and sets a bit in the notify pending memory. Entries in the notify queue get translated fer protocol, the notify pending memory bit for that channel is reset.

14.2.3.5.1 System Errors Due to Packet Switching

Table 117. System Error Register Address 0x00126

7 PMFOB PCI master, fatal error —this bit is set when a T8110-initiated PCI cycle results in abnormal

/c110 Requested PCI target does not respond (master abort). /c110 Requested PCI target terminates (target abort).

6 PMLOB PCI master, external buffer LOCK error—this bit is set when a T8110 descriptor table fetch

5 PMEOB PCI master, external buffer STALL error—this bit is set when a T8110 descriptor table fetch

caught up to USER pointer), and T8110 access to the external buffer is denied.

4 PMWOB PCI master, external buffer STALL error—this bit is set when a T8110 descriptor table fetch

3 PMOOB PCI master, external buffer OVERWRITE warning—this bit is set when a T8110 descriptor

2 PMIOB PCI master, external buffer INITIAL warning—this bit is set when a T8110 descriptor table

1 VCOOB Virtual channel memory, scratchpad OVERFLOW warning—indicates the calculated

scratchpad current depth has exceeded the overall buffer depth (VC programming error).

0 NQOOB NOTIFY_QUEUE OVERFLOW warning—indicates that a request to push (or pull) a

buffer will get overwritten (push ) or contain stale data (pull).

15.1 Absolute Maximum Ratings

periods can adversely affect device reliability.

15.1.1 Handling Precautions

15.2 Crystal Specifications

15.2.1 XTAL1 Crystal

5% capacitors must be connected from XTAL1_IN and XTAL1_OUT to Vss, as shown in the diagram below. bus. Otherwise, a crystal with a lesser tolerance can be used. The crystal specifications are shown below. Table 118. Absolute Maximum Ratings Table 119. XTAL1 Specifications

If an oscillator is used (see Section 7.4.4 on page 79), the signal has to be connected to the XTAL1_IN pin. oscillator must meet the requirements shown below.

15.2.2 XTAL2 Crystal

with a lesser tolerance can be used (see Table 121). DD and XTAL2_OUT should be left unconnected. *1 2 0 Ω maximum for 6.176 MHz crystal. † 24 pF for 6.176 MHz crystal also. ‡ 18 pF for 6.176 MHz crystal also. If an oscillator is used (see Section 7.5.1 on page 81), the signal has to be connected to the XTAL2_IN pin. oscillator must meet the requirements shown below. Table 120. 16.384 MHz Oscillator Requirements Table 121. XTAL2 Specifications Table 122. 6.176 MHz/12.352 MHz Oscillator Requirements

1 MΩT8110

15.2.3 Reset Pulse

15.3 Thermal Considerations for the 272 PBGA

15.4.1 PCI Signals

face timing diagrams can be found in Figure 6—Figure 15, starting on page 25.

15.4.2 Electrical Drive Specifications, CT_C8 and /CT_FRAME

VDD = 3.3 V and VSS = 0.0 V, unless otherwise specified. CT_C8 and /CT_FRAME signals, though this is not explicitly stated as a part of the H.1x0 specification. Table 123. Reset Pulse Table 124. Thermal Considerations

27 Peripheral

Table 125. Electrical Drive Specifications, CT_C8 and /CT_FRAME

15.4.3 All Other Pins

VDD = 3.3 V and Vss = 0.0 V, unless otherwise specified.

15.5 H-Bus Timing

15.5.1 Timing Diagrams

Figure 59. Clock Alignment Table 126. dc Electrical Characteristics, All Other Pins

Note: Bit 1 is the MSB and Bit 8 is the LSB. MSB is always transmitted first in all transfers. Figure 60. Frame Timing Diagram Figure 61. Detailed Clock Skew Timing Diagram

15.6.1 Skew Timing, H-Bus

† Assumes A and B masters in adjacent slots. skew of 30 ns will occur during that clock cycle. generating CT_C8 to have different time constants when acting as primary and secondary clock masters. Table 127. Skew Timing, H-Bus

Table 128. L_SC[3:0] and Frame Group Rise and Fall Time

• Worst-case loading of 50 pF on all outputs.

15.7 Hot-Swap

15.7.1 LPUE (Local Pull-Up Enable)

PRI_REF_IN, NR1_DIV_IN, and NR2_DIV_IN.

15.8 Decoupling

15.9 APLL VDD Filter

late the PICMG Hot Swap specification. Figure 62. APLL VDD Filtering

15.10 PC Board PBGA Considerations

applicable specifications for any PC board requirements.

15.11 Unused Pins

15.12 T8110 Evaluation Boards

15.13 T8110 Ordering Information

Table 129. T8110 Ordering Information

16.1 Pin and Pad Assignments

Figure 63. T8110 Pins by Functional Group, PCI I/F Enabled, Microprocessor I/F Disabled

Figure 64. T8110 Pins by Functional Group, Microprocessor I/F Enabled, PCI I/F Disabled

Agere Systems Inc. 175 Data Sheet May 2001 and Packet Payload Engine Ambassador T8110 PCI-Based H.100/H.110 Switch 5-4406 BOTTOM VIEW A B C D E F G H J K L M Y N P R T U V W 12345678910 1820 19 SPACES @ 1.27 = 24.13

19 SPACES

@ 1.27 = 24.13 0.76 +0.14 –0.16 A1 BALL PAD CORNER

176 Agere Systems Inc. Data Sheet May 2001and Packet Payload Engine Ambassador T8110 PCI-Based H.100/H.110 Switch 5-4406 SIDE VIEW 5-4406 TOP VIEW 1.17 ± 0.05 SEATING PLANE SOLDER BALL0.60 ± 0.10 0.20 0.36 +0.04 –0.06 2.13 +0.19 –0.21 27.00 24.00 +0.70 –0.50 24.00 +0.70 –0.50A1 BALL PAD CORNER 27.00

17 JTAG/Boundary Scan

17.1 The Principle of Boundary-Scan Architecture

referred to as output cells. Input and output is relative to the core logic of the device. **Figure 65. IEEE* 1149.1 Boundary-Scan Architecture** boundary-scan register (boundary scan). /c110 A finite-state machine TAP controller with inputs TCK and TMS. /c110 An n-bit (n = 3) instruction register (IR), holding the current instruction. /c110 A 1-bit bypass register (BYPASS).

• IEEE is a registered trademark of The Institute of Electrical and Electronic Engineers, Inc.

17.1.1 Instruction Register

The instruction register is 3 bits long and the capture value is 001.

17.2 Boundary-Scan Register

Note: The control column of the following table indicates the value for boundary-scan control of this pin. Table 130. Instruction Register EXTEST 000 Places the boundary-scan register in EXTEST mode. SAMPLE 001 Places the boundary-scan register in sample mode. IDCODE 101 Identification code. BYPASS 110, 111 Places the bypass register in the scan chain. HIGH Z 010 Places all outputs and I/Os in 3-state mode. Table 131. Boundary-Scan Register Description

0 VSS A1 Linkage —— —

1 BOUT_CT_D_EN(27) — Controller — — —

2 CT_D27 A2 I/O BOUT_CT_D_EN(27) 0 High Z

3 BOUT_CT_D_EN(24) — Controller — — —

4 CT_D24 A3 I/O BOUT_CT_D_EN(24) 0 High Z

5 BOUT_CT_D_EN(21) — Controller — — —

6 CT_D21 A4 I/O BOUT_CT_D_EN(21) 0 High Z

7 BOUT_CT_D_EN(19) — Controller — — —

8 CT_D19 A5 I/O BOUT_CT_D_EN(19) 0 High Z

9 BOUT_CT_D_EN(16) — Controller — — —

10 CT_D16 A6 I/O BOUT_CT_D_EN(16) 0 High Z

11 BOUT_CT_D_EN(13) — Controller — — —

12 CT_D13 A7 I/O BOUT_CT_D_EN(13) 0 High Z

13 BOUT_CT_D_EN(11) — Controller — — —

14 CT_D11 A8 I/O BOUT_CT_D_EN(11) 0 High Z

15 BOUT_CT_D_EN(8) — Controller — — —

16 CT_D8 A9 I/O BOUT_CT_D_EN(8) 0 High Z

17 BOUT_CT_D_EN(4) — Controller — — —

18 CT_D4 A10 I/O BOUT_CT_D_EN(4) 0 High Z

19 BOUT_CT_D_EN(0) — Controller — — —

20 CT_D0 A11 I/O BOUT_CT_D_EN(0) 0 High Z

17 JTAG/Boundary Scan (continued)

23 CT_C8_A A13 I/O BOUT_CT_A_EN 0 High Z

24 BOUT_CT_NETREF1_En — Controller — — —

25 CT_NETREF1 A14 I/O BOUT_CT_NETREF1_En 0 High Z

26 L_REF0 A15 Input BOUT_CT_NETREF1_En — —

27 L_REF4 A16 Input BOUT_CT_NETREF1_En — —

28 GENERAL_EN — Controller — — —

29 PRI_REF_OUT A17 Output3 GENERAL_EN 0 High Z

30 PRI_REF_IN A18 Clock GENERAL_EN — —

31 NR1_DIV_IN A19 Input GENERAL_EN — —

32 PEN A20 Enable0 GENERAL_EN(0) — 50 K Ω up

33 BOUT_CT_D_EN(29) — Controller — — —

34 CT_D29 B1 I/O BOUT_CT_D_EN(29) 0 High Z

35 BOUT_CT_D_EN(28) — Controller — — —

36 CT_D28 B2 I/O BOUT_CT_D_EN(28) 0 High Z

37 BOUT_CT_D_EN(25) — Controller — — —

38 CT_D25 B3 I/O BOUT_CT_D_EN(25) 0 High Z

39 BOUT_CT_D_EN(22) — Controller — — —

40 CT_D22 B4 I/O BOUT_CT_D_EN(22) 0 High Z

41 BOUT_CT_D_EN(20) — Controller — — —

42 CT_D20 B5 I/O BOUT_CT_D_EN(20) 0 High Z

43 BOUT_CT_D_EN(17) — Controller — — —

44 CT_D17 B6 I/O BOUT_CT_D_EN(17) 0 High Z

45 BOUT_CT_D_EN(14) — Controller — — —

46 CT_D14 B7 I/O BOUT_CT_D_EN(14) 0 High Z

47 BOUT_CT_D_EN(9) — Controller — — —

48 CT_D9 B8 I/O BOUT_CT_D_EN(9) 0 High Z

49 BOUT_CT_D_EN(6) — Controller — — —

50 CT_D6 B9 I/O BOUT_CT_D_EN(6) 0 High Z

51 BOUT_CT_D_EN(5) — Controller — — —

52 CT_D5 B10 I/O BOUT_CT_D_EN(5) 0 High Z

53 BOUT_CT_D_EN(1) — Controller — — —

54 CT_D1 B11 I/O BOUT_CT_D_EN(1) 0 High Z

57 CT_C8_B B13 I/O BOUT_CT_B_EN 0 High Z

Table 131. Boundary-Scan Register Description (continued)

58 BOUT_CT_NETREF2_En —C o n t r o l l e r — — —

59 CT_NETREF2 B14 I/O BOUT_CT_NETREF2_En 0 High Z

60 L_REF1 B15 Input BOUT_CT_NETREF2_En — —

61 L_REF5 B16 Input BOUT_CT_NETREF2_En — —

62 L_REF6 B17 Input BOUT_CT_NETREF2_En — —

63 NR1_SEL_OUT B18 Output3 GENERAL_EN 0 High Z

64 APLL1VDD B19 Linkage — — —

65 XTAL1_IN B20 Linkage — — —

66 VPRECHARGE C1 Linkage — — —

67 BOUT_CT_D_EN(30) — Controller — — —

68 CT_D30 C2 I/O BOUT_CT_D_EN(30) 0 High Z

69 BOUT_CT_D_EN(26) — Controller — — —

70 CT_D26 C3 I/O BOUT_CT_D_EN(26) 0 High Z

71 BOUT_CT_D_EN(23) — Controller — — —

72 CT_D23 C4 I/O BOUT_CT_D_EN(23) 0 High Z

73 BOUT_CT_D_EN(18) — Controller — — —

74 CT_D18 C5 I/O BOUT_CT_D_EN(18) 0 High Z

75 BOUT_CT_D_EN(15) — Controller — — —

76 CT_D15 C6 I/O BOUT_CT_D_EN(15) 0 High Z

77 BOUT_CT_D_EN(12) — Controller — — —

78 CT_D12 C7 I/O BOUT_CT_D_EN(12) 0 High Z

79 BOUT_CT_D_EN(10) — Controller — — —

80 CT_D10 C8 I/O BOUT_CT_D_EN(10) 0 High Z

81 BOUT_CT_D_EN(7) — Controller — — —

82 CT_D7 C9 I/O BOUT_CT_D_EN(7) 0 High Z

83 BOUT_CT_D_EN(2) — Controller — — —

84 CT_D3 C10 I/O BOUT_CT_D_EN(2) High Z

85 BOUT_CT_D_EN(3) — Controller — — —

86 CT_D2 C11 I/O BOUT_CT_D_EN(3) 0 High Z

87 BOUT_FRN_COMP_EN — Controller — — —

89 BOUT_SCBUS_CLOCKS_En — Controller — — —

91 SCLK C14 I/O BOUT_SCBUS_CLOCKS_En 0 50 k Ω up

92 L_REF2 C15 Input BOUT_SCBUS_CLOCKS_En — —

93 L_REF3 C16 Input BOUT_SCBUS_CLOCKS_En — —

94 L_REF7 C17 Input BOUT_SCBUS_CLOCKS_En ——

95 TRST# C18 TRST BOUT_SCBUS_CLOCKS_En — 50 k Ω up

96 XTAL1_OUT C19 Linkage BOUT_SCBUS_CLOCKS_En — —

97 NR2_DIV_IN C20 Input BOUT_SCBUS_CLOCKS_En — —

98 BOUT_GP_EN(0) — Controller — — —

99 GP0 D1 I/O BOUT_GP_EN(0) 0 High Z

100 BOUT_CT_D_EN(31) — Controller — — —

101 CT_D31 D2 I/O BOUT_CT_D_EN(31) 0 High Z

102 BOUT_GP_EN(4) — Controller — — —

103 GP4 D3 I/O BOUT_GP_EN(4) 0 High Z

104 VSS D4 Linkage — — —

105 H110_ENABLE D5 Enable1 BOUT_GP_EN(4) — 20 k Ω

106 VDD D6 Linkage — — —

107 H100_ENABLE D7 Enable0 BOUT_GP_EN(4) — 20 k Ω

108 VSS D8 Linkage — — —

109 BOUT_HMVIP_CLOCKS_En — Controller BOUT_GP_EN(4) — —

112 VDD D11 Linkage — — —

113 BOUT_MVIP_CLOCKS_En — Controller — — —

115 VSS D13 Linkage — — —

116 C2 D14 I/O BOUT_MVIP_CLOCKS_En 0 50 k Ω up

117 VDD D15 Linkage — — —

118 PLOCK D16 Linkage BOUT_MVIP_CLOCKS_En — —

119 VSS D17 Linkage — — —

120 TMS D18 TMS BOUT_MVIP_CLOCKS_En — 50 k Ω up

121 NR2_SEL_OUT D19 Output3 GENERAL_EN 0 High Z

122 PSEL D20 Linkage GENERAL_EN — 20 k Ω

123 BOUT_GP_EN(1) — Controller — — —

124 GP1 E1 I/O BOUT_GP_EN(1) 0 High Z

125 BOUT_GP_EN(2) — Controller — — —

126 GP2 E2 I/O BOUT_GP_EN(2) 0 High Z

127 BOUT_GP_EN(6) — Controller — — —

128 GP5 E3 I/O BOUT_GP_EN(6) 0 High Z

129 BOUT_GP_EN(7) —C o n t r o l l e r — — —

130 GP7 E4 I/O BOUT_GP_EN(7) 0 High Z

131 PTEST E17 Linkage BOUT_GP_EN(7) — 20 k Ω

132 TCK E18 TCK BOUT_GP_EN(7) — 50 k Ω up

133 APLL2V DD E19 Linkage — —

134 XTAL2_IN E20 Linkage BOUT_GP_EN(7) — —

135 BOUT_MB_EN — Controller — — —

136 MB_A0 F1 I/O BOUT_MB_EN 0 20 k Ω

137 BOUT_GP_EN(3) — Controller — — —

138 GP3 F2 I/O BOUT_GP_EN(3) 0 High Z

139 BOUT_GP_EN(5) — Controller — — —

140 GP6 F3 I/O BOUT_GP_EN(5) 0 High Z

141 VDD F4 Linkage — — —

142 VDD F17 Linkage — — —

143 TDI F18 TDI BOUT_GP_EN(5) — 50 k Ω up

144 XTAL2_OUT F19 Linkage BOUT_GP_EN(5) — —

145 TESTMODE F20 Enable0 BOUT_GP_EN(5) — 20 k Ω

146 BOUT_MB_A1_EN — Controller — — —

147 MB_A1 G1 I/O BOUT_MB_A1_EN 0 20 k Ω

148 BOUT_MB_A2_EN — Controller — — —

149 MB_A2 G2 I/O BOUT_MB_A2_EN 0 20 k Ω

150 MB_A3 G3 I/O BOUT_MB_A2_EN 0 20 k Ω

151 OUT_EE_CS_EN — Controller — — —

152 EE_CS G4 Output3 OUT_EE_CS_EN 0 High Z

153 PPDN G17 Linkage OUT_EE_CS_EN — 20 k Ω

154 TDO G18 TDO OUT_EE_CS_EN — —

155 OUT_L_SC_En(3) — Controller — — —

156 L_SC3 G19 Output3 OUT_L_SC_En(3) 0 High Z

157 OUT_TCLK_OUT_En — Controller — — —

158 TCLK_OUT G20 Output3 OUT_TCLK_OUT_En 0 High Z

159 MB_A4 H1 I/O BOUT_MB_EN 0 20 k Ω

160 MB_A5 H2 I/O BOUT_MB_EN 0 20 k Ω

161 MB_A6 H3 I/O BOUT_MB_EN 0 20 k Ω

162 VSS H4 Linkage —— —

163 VSS H17 Linkage — — —

164 OUT_L_SC_En(2) — Controller — — —

165 L_SC2 H18 Output3 OUT_L_SC_En(2) 0 High Z

166 OUT_L_SC_En(1) — Controller — — —

167 L_SC1 H19 Output3 OUT_L_SC_En(1) 0 High Z

168 OUT_L_SC_En(0) — Controller — — —

169 L_SC0 H20 Output3 OUT_L_SC_En(0) 0 High Z

170 MB_A8 J1 I/O BOUT_MB_EN 0 20 k Ω

171 MB_A9 J2 I/O BOUT_MB_EN 0 20 k Ω

172 MB_A10 J3 I/O BOUT_MB_EN 0 20 k Ω

173 MB_A7 J4 I/O BOUT_MB_EN 0 20 k Ω

174 LPUE J17 Enable1 BOUT_MB_EN — 50 k Ω up

175 BOUT_L_D_EN(2) — Controller — — —

176 L_D2 J18 I/O BOUT_L_D_EN(2) 0 High Z

177 BOUT_L_D_EN(1) — Controller — — —

178 L_D1 J19 I/O BOUT_L_D_EN(1) 0 High Z

179 BOUT_L_D_EN(0) — Controller — — —

180 L_D0 J20 I/O BOUT_L_D_EN(0) 0 High Z

181 MB_A12 K1 I/O BOUT_MB_EN 0 20 k Ω

182 MB_A13 K2 I/O BOUT_MB_EN 0 20 k Ω

183 MB_A11 K3 I/O BOUT_MB_EN 0 20 k Ω

184 VDD K4 Linkage — — —

185 BOUT_L_D_EN(3) — Controller — — —

186 L_D3 K17 I/O BOUT_L_D_EN(3) 0 High Z

187 BOUT_L_D_EN(6) — Controller — — —

188 L_D6 K18 I/O BOUT_L_D_EN(6) 0 High Z

189 BOUT_L_D_EN(5) —C o n t r o l l e r — — —

190 L_D5 K19 I/O BOUT_L_D_EN(5) 0 High Z

191 BOUT_L_D_EN(4) — Controller — — —

192 L_D4 K20 I/O BOUT_L_D_EN(4) 0 High Z

193 MB_CS0 L1 I/O BOUT_MB_EN 0 20 k Ω

194 MB_CS1 L2 I/O BOUT_MB_EN 0 20 k Ω

195 MB_A14 L3 I/O BOUT_MB_EN 0 20 k Ω

196 MB_A15 L4 I/O BOUT_MB_EN 0 20 k Ω

197 VDD L17 Linkage — — —

198 BOUT_L_D_EN(7) — Controller — — —

199 L_D7 L18 I/O BOUT_L_D_EN(7) 0 High Z

200 BOUT_L_D_EN(9) — Controller — — —

201 L_D9 L19 I/O BOUT_L_D_EN(9) 0 High Z

202 BOUT_L_D_EN(8) — Controller — — —

203 L_D8 L20 I/O BOUT_L_D_EN(8) 0 High Z

204 MB_CS2 M1 I/O BOUT_MB_EN 0 20 k Ω

205 MB_CS3 M2 I/O BOUT_MB_EN 0 20 k Ω

206 MB_CS4 M3 I/O BOUT_MB_EN 0 High Z

207 MB_CS5 M4 I/O BOUT_MB_EN 0 High Z

208 BOUT_L_D_EN(11) — Controller — — —

209 L_D11 M17 I/O BOUT_L_D_EN(11) 0 High Z

210 BOUT_L_D_EN(10) — Controller — — —

211 L_D10 M18 I/O BOUT_L_D_EN(10) 0 High Z

212 BOUT_L_D_EN(13) — Controller — — —

213 L_D13 M19 I/O BOUT_L_D_EN(13) 0 High Z

214 BOUT_L_D_EN(12) — Controller — — —

215 L_D12 M20 I/O BOUT_L_D_EN(12) 0 High Z

216 MB_RD N1 I/O BOUT_MB_EN 0 High Z

217 OUT_MB_CS6_EN — Controller — — —

218 MB_CS6 N2 Output3 OUT_MB_CS6_EN 0 High Z

219 MB_CS7 N3 I/O BOUT_MB_EN 0 High Z

220 VSS N4 Linkage —— —

221 VSS N17 Linkage — — —

222 BOUT_L_D_EN(15) — Controller — — —

223 L_D15 N18 I/O BOUT_L_D_EN(15) 0 High Z

224 BOUT_L_D_EN(14) — Controller — — —

225 L_D14 N19 I/O BOUT_L_D_EN(14) 0 High Z

226 BOUT_L_D_EN(16) — Controller — — —

227 L_D16 N20 I/O BOUT_L_D_EN(16) 0 High Z

228 MB_WR P1 I/O BOUT_MB_EN 0 High Z

229 BOUT_MB_D_En — Controller — — —

230 MB_D14 P2 I/O BOUT_MB_D_En 0 High Z

231 MB_D15 P3 I/O BOUT_MB_D_En 0 High Z

232 MB_D11 P4 I/O BOUT_MB_D_En 0 High Z

233 BOUT_L_D_EN(23) — Controller — — —

234 L_D23 P17 I/O BOUT_L_D_EN(23) 0 High Z

235 BOUT_L_D_EN(19) — Controller — — —

236 L_D19 P18 I/O BOUT_L_D_EN(19) 0 High Z

237 BOUT_L_D_EN(18) — Controller — — —

238 L_D18 P19 I/O BOUT_L_D_EN(18) 0 High Z

239 BOUT_L_D_EN(17) — Controller — — —

240 L_D17 P20 I/O BOUT_L_D_EN(17) 0 High Z

241 MB_D12 R1 I/O BOUT_MB_D_En 0 High Z

242 MB_D13 R2 I/O BOUT_MB_D_En 0 High Z

243 MB_D10 R3 I/O BOUT_MB_D_En 0 High Z

244 VDD R4 Linkage — — —

245 VDD R17 Linkage — — —

246 BOUT_L_D_EN(22) — Controller — — —

247 L_D22 R18 I/O BOUT_L_D_EN(22) 0 High Z

248 BOUT_L_D_EN(21) — Controller — — —

249 L_D21 R19 I/O BOUT_L_D_EN(21) 0 High Z

251 L_D20 R20 I/O BOUT_L_D_EN(20) 0 High Z

252 MB_D8 T1 I/O BOUT_MB_D_En 0 High Z

253 MB_D9 T2 I/O BOUT_MB_D_En 0 High Z

254 MB_D6 T3 I/O BOUT_MB_D_En 0 High Z

255 MB_D7 T4 I/O BOUT_MB_D_En 0 High Z

256 BOUT_L_D_EN(31) —C o n t r o l l e r — — —

257 L_D31 T17 I/O BOUT_L_D_EN(31) 0 High Z

258 BOUT_L_D_EN(26) — Controller — — —

259 L_D26 T18 I/O BOUT_L_D_EN(26) 0 High Z

260 BOUT_L_D_EN(25) — Controller — — —

261 L_D25 T19 I/O BOUT_L_D_EN(25) 0 High Z

262 BOUT_L_D_EN(24) — Controller — — —

263 L_D24 T20 I/O BOUT_L_D_EN(24) 0 High Z

264 MB_D4 U1 I/O BOUT_MB_D_En 0 High Z

265 MB_D5 U2 I/O BOUT_MB_D_En 0 High Z

266 MB_D3 U3 I/O BOUT_MB_D_En 0 High Z

267 VSS U4 Linkage — — —

268 VIO/µP_SELECT U5 Input — — —

269 VDD U6 Linkage — — —

270 INV_PCI_CBE3_EN_N — Controller — — —

271 PCI_CBE3# U7 I/O INV_PCI_CBE3_EN_N 0 High Z

272 V SS U8 Linkage — — —

273 INV_PCI_CBE2_EN_N — Controller — — —

274 PCI_CBE2# U9 I/O INV_PCI_CBE2_EN_N 0 High Z

277 PCI_PAR U11 I/O INV_PCI_PAR_EN_N 0 High Z

278 INV_PCI_CBE1_EN_N — Controller — — —

279 PCI_CBE1# U12 I/O INV_PCI_CBE1_EN_N 0 High Z

280 VSS U13 Linkage — — —

281 INV_PCI_CBE0_EN_N — Controller — — —

282 PCI_CBE0# U14 I/O INV_PCI_CBE0_EN_N 0 High Z

283 VDD U15 Linkage — — —

284 INV_PCI_ADEN_N(3) — Controller — — —

285 PCI_AD3 U16 I/O INV_PCI_ADEN_N(3) 0 High Z

286 VSS U17 Linkage — — —

287 BOUT_L_D_EN(30) — Controller — — —

288 L_D30 U18 I/O BOUT_L_D_EN(30) 0 High Z

289 BOUT_L_D_EN(29) — Controller — — —

290 L_D29 U19 I/O BOUT_L_D_EN(29) 0 High Z

291 BOUT_L_D_EN(27) — Controller — — —

292 L_D27 U20 I/O BOUT_L_D_EN(27) 0 High Z

293 MB_D1 V1 I/O BOUT_MB_D_En 0 High Z

294 MB_D2 V2 I/O BOUT_MB_D_En 0 High Z

295 SYSERR V3 Output3 GENERAL_EN 0 High Z

296 INV_PCI_ADEN_N(31) — Controller — — —

297 PCI_AD31 V4 I/O INV_PCI_ADEN_N(31) 0 High Z

298 INV_PCI_ADEN_N(30) — Controller — — —

299 PCI_AD30 V5 I/O INV_PCI_ADEN_N(30) 0 High Z

300 INV_PCI_ADEN_N(27) — Controller — — —

301 PCI_AD27 V6 I/O INV_PCI_ADEN_N(27) 0 High Z

302 INV_PCI_ADEN_N(23) — Controller — — —

303 PCI_AD23 V7 I/O INV_PCI_ADEN_N(23) 0 High Z

304 INV_PCI_ADEN_N(19) — Controller — — —

305 PCI_AD(19) V8 I/O INV_PCI_ADEN_N(19) 0 High Z

306 INV_PCI_ADEN_N(18) — Controller — — —

307 PCI_AD18 V9 I/O INV_PCI_ADEN_N(18) 0 High Z

308 PCI_LOCK# V10 Input INV_PCI_ADEN_N(18)

309 INV_PCI_CTRL_EN_N — Controller — — —

310 PCI_STOP# V11 I/O INV_PCI_CTRL_EN_N 0 High Z

311 INV_PCI_SERR_OUT_N — Controller — — —

312 PCI_SERR# V12 Output3 INV_PCI_SERR_OUT_N 0 High Z

313 INV_PCI_ADEN_N(15) — Controller — — —

314 PCI_AD15 V13 I/O INV_PCI_ADEN_N(15) 0 High Z

315 INV_PCI_ADEN_N(11) — Controller — — —

316 PCI_AD11 V14 I/O INV_PCI_ADEN_N(11) 0 High Z

317 INV_PCI_ADEN_N(7) — Controller — — —

318 PC_AD7 V15 I/O INV_PCI_ADEN_N(7) 0 High Z

319 INV_PCI_ADEN_N(2) — Controller — — —

320 PCI_AD2 V16 I/O INV_PCI_ADEN_N(2) 0 High Z

321 BOUT_FG_EN(7) — Controller — — —

322 FG7 V17 I/O BOUT_FG_EN(7) 0 High Z

323 BOUT_FG_EN(6) — Controller — — —

324 FG6 V18 I/O BOUT_FG_EN(6) 0 High Z

325 BOUT_FG_EN(5) — Controller — — —

326 FG5 V19 I/O BOUT_FG_EN(5) 0 High Z

327 BOUT_L_D_EN(28) — Controller — — —

328 L_D28 V20 I/O BOUT_L_D_EN(28) 0 High Z

329 MB_D0 W1 I/O BOUT_MB_D_En 0 High Z

330 CLKERR W2 Output3 GENERAL_EN 0 High Z

331 INV_PCI_REQ_EN_N —C o n t r o l l e r — — —

332 PCI_REQ# W3 Output3 INV_PCI_REQ_EN_N 0 High Z

333 PCI_GNT# W4 Input INV_PCI_REQ_EN_N — —

334 INV_PCI_ADEN_N(29) — Controller INV_PCI_REQ_EN_N — —

335 PCI_AD29 W5 I/O INV_PCI_ADEN_N(29) 0 High Z

336 INV_PCI_ADEN_N(26) — Controller — — —

337 PCI_AD26 W6 I/O INV_PCI_ADEN_N(26) 0 High Z

338 INV_PCI_ADEN_N(22) — Controller — — —

339 PCI_AD22 W7 I/O INV_PCI_ADEN_N(22) 0 High Z

340 INV_PCI_ADEN_N(21) — Controller — — —

341 PCI_AD21 W8 I/O INV_PCI_ADEN_N(21) 0 High Z

342 INV_PCI_ADEN_N(17) — Controller — — —

343 PCI_AD17 W9 I/O INV_PCI_ADEN_N(17) 0 High Z

344 PCI_IDSEL# W10 Input — — —

345 PCI_DEVSEL# W11 I/O INV_PCI_CTRL_EN_N 0 High Z

346 INV_PCI_PERR_EN_N — Controller — — —

347 PCI_PERR# W12 I/O INV_PCI_PERR_EN_N 0 High Z

348 INV_PCI_ADEN_N(14) — Controller — — —

349 PCI_AD14 W13 I/O INV_PCI_ADEN_N(14) 0 High Z

350 INV_PCI_ADEN_N(10) — Controller — — —

351 PCI_AD10 W14 I/O INV_PCI_ADEN_N(10) 0 High Z

352 INV_PCI_ADEN_N(9) — Controller — — —

353 PCI_AD9 W15 I/O INV_PCI_ADEN_N(9) 0 High Z

354 INV_PCI_ADEN_N(6) — Controller — — —

355 PCI_AD6 W16 I/O INV_PCI_ADEN_N(6) 0 High Z

356 INV_PCI_ADEN_N(1) — Controller — — —

357 PCI_AD1 W17 I/O INV_PCI_ADEN_N(1) 0 High Z

357 BOUT_FG_EN(4) — Controller — — —

359 FG4 W18 I/O BOUT_FG_EN(4) 0 High Z

360 BOUT_FG_EN(3) — Controller — — —

361 FG3 W19 I/O BOUT_FG_EN(3) 0 High Z

362 BOUT_FG_EN(2) — Controller — — —

363 FG2 W20 I/O BOUT_FG_EN(2) 0 High Z

364 RESET# Y1 Input BOUT_FG_EN(2) — 50 k Ω up

365 PCI_RST# Y2 Input BOUT_FG_EN(2) — —

366 PCI_CLK Y3 Clock BOUT_FG_EN(2) — —

367 INV_OUT_PCI_INTAN — Controller — — —

368 PCI_INTA# Y4 Output3 INV_OUT_PCI_INTAn 0 High Z

369 INV_PCI_ADEN_N(28) — Controller — — —

370 PCI_AD28 Y5 I/O INV_PCI_ADEN_N(28) 0 High Z

371 INV_PCI_ADEN_N(25) — Controller — — —

372 PCI_AD25 Y6 I/O INV_PCI_ADEN_N(25) 0 High Z

373 INV_PCI_ADEN_N(24) — Controller — — —

374 PCI_AD24 Y7 I/O INV_PCI_ADEN_N(24) 0 High Z

375 INV_PCI_ADEN_N(20) — Controller — — —

376 PCI_AD20 Y8 I/O INV_PCI_ADEN_N(20) 0 High Z

377 INV_PCI_ADEN_N(16) — Controller — — —

378 PCI_AD16 Y9 I/O INV_PCI_ADEN_N(16) 0 High Z

379 INV_PCI_FRAME_EN_N — Controller — — —

380 PCI_FRAME# Y10 I/O INV_PCI_FRAME_EN_N 0 High Z

381 INV_PCI_IRDY_EN_N — Controller — — —

382 PCI_IRDY# Y11 I/O INV_PCI_IRDY_EN_N 0 High Z

383 PCI_TRDY# Y12 I/O INV_PCI_CTRL_EN_N 0 High Z

384 INV_PCI_ADEN_N(13) — Controller — — —

385 PCI_AD13 Y13 I/O INV_PCI_ADEN_N(13) 0 High Z

386 INV_PCI_ADEN_N(12) — Controller — — —

387 PCI_AD12 Y14 I/O INV_PCI_ADEN_N(12) 0 High Z

388 INV_PCI_ADEN_N(8) — Controller — — —

389 PCI_AD8 Y15 I/O INV_PCI_ADEN_N(8) 0 High Z

390 INV_PCI_ADEN_N(5) — Controller — — —

391 PCI_AD5 Y16 I/O INV_PCI_ADEN_N(5) 0 High Z

392 INV_PCI_ADEN_N(4) — Controller — — —

393 PCI_AD4 Y17 I/O INV_PCI_ADEN_N(4) 0 High Z

394 INV_PCI_ADEN_N(0) — Controller — — —

395 PC_AD0 Y18 I/O INV_PCI_ADEN_N(0) 0 High Z

396 BOUT_FG_EN(1) — Controller — — —

397 FG1 Y19 I/O BOUT_FG_EN(1) 0 High Z

398 BOUT_FG_EN(0) — Controller — — —

399 FG0 Y20 I/O BOUT_FG_EN(0) 0 High Z

190 Agere Systems Inc. Data Sheet May 2001and Packet Payload Engine Ambassador T8110 PCI-Based H.100/H.110 Switch Appendix A. Constant and Minimum Delay Connections A.1 Connection Definitions A forward connection is defined as one in which the output to time slot has a greater value than the input from time-slot, or, put another way, the delta between them is positive. A reverse connection is defined as one in which the output to time slot has a lesser value than the input from time slot, and the delta between them is negative. For example, going from TS(1) to TS(38) is a forward connection, and the TSΔ is +37, but going from TS(38) to TS(1) is a reverse connection, with a TSΔ of –37: where TSΔ = TS(to) – TS(from). Similarly, a delta can be introduced for streams which will have a bearing in certain exceptions (discussed later): STR Δ = STR(to) – STR(from). There is only one combination which forms a TSΔ of +127 or –127: TS Δ = TS(127) – TS(0) = +127, and but there are two combinations which form TSΔ s of +126 or –126: TS Δ = TS(127) – TS(1) = TS(126) – TS(0) = +126, and there are three combinations which yield +125 or –125, and so on. The user can utilize the TSΔ to control the latency of the resulting connection. In some cases, the latency must be minimized. In other cases, such as a block of connections which must maintain some relative integrity while cross- ing a frame boundary, the required latency of some of the connections may exceed a one frame (>128 time-slots) to maintain the integrity of this virtual frame. The device uses a control bit at each connection memory location, VFC, for controlling latency, allowing each con- nection to select one of two alternating data buffers. A.2 Delay Type Definitions Constant Delay—This is a well-defined, predictable, and linear region of latency in which the to time slot is at least 128 time slots after the from time-slot, but no more than 256 time slots after the from time-slot. Mathematically, constant delay latency is described as follows*, with L denoting latency, and VFC set to the value indicated: Forward connections, VFC = 1: L = 128 + TSΔ (0 ≤ TSΔ ≤ 127) Reverse connections, VFC = 0: L = 256 + TSΔ (–127 ≤ TSΔ ≤ 0) Example: Switching from TS(37) to TS(1) as a constant delay, the delta is –36, so FME is set to 0 and the result- ing latency is 256 – 36 = 220 time slots. Thus, the connection will be made from TS(37) of frame(n) to TS(1) of frame(n + 2). Simple summary: Use constant delay for latencies of 128 to 256 time slots, set VFC = 1 for forward connections, set VFC = 0 for reverse connections. * Since TSΔ = TS(to) –TS(from), the user can modify the equations to solve for either TS(to) or TS(from).

Figure 66. Constant Delay Connection Latency time slot. Exceptions exist at TSΔ s of +1, +2, –126, and –127. Forward connections, VFC = 0: L = TSΔ (3 ≤ TSΔ ≤ 127). Reverse connections, VFC = 1: L = 128 + TSΔ (–125 ≤ TSΔ ≤ 0). frame in the constant delay case. set VFC = 1 for reverse connections. because the to and from streams have been irrelevant in the switching process. two frames due to the interaction of the intrinsic pipeline delays with the double buffering.

been included in the diagram, connected to the main function by dashed lines. Figure 67. Minimum Delay Connection Latency larly, multiply values by four to convert 2.048 Mbits/s values. The latency equations can then be applied directly. Table 132. Special Cases (Exceptions)

Table 133. Mnemonic Summary, Sorted by Name

Table 133. Mnemonic Summary, Sorted by Name (continued)

Table 134. Mnemonic Summary, Sorted by Register

Table 134. Mnemonic Summary, Sorted by Register (continued)

Agere Systems Inc. reserves the right to make changes to the product(s) or inform ation contained herein without notice. No liability is assume d as a result of their use or application. Ambassador is a registered trademark of Agere Systems Inc. Co pyright © 2001 Agere Systems Inc. All Rights Reserved May 2001 DS00 -434CTI (Replaces DS00-012CTI, AY00-030CTI, and AY01-009CTI; must accom pany AY01-021CTI) For additional information, contact your Agere Systems Account Manager or the following: IN TERNE T: http://www .agere.com E-M AIL: docm aster@mi cro.lucent.com N. AM ERIC A: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentow n, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CAN AD A: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC :Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHIN A: Agere Systems (Shanghai) Co ., Ltd., 33/F Jin Mao Towe r, 88 Century Boulevard Pudong, Shanghai 200121 PRC Tel. (86) 21 50471212, FAX (86) 21 50472266 JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chom e, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EU R OP E: D ata Requests: D ATALIN E: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries:G ER MA N Y: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FR AN CE: (33) 1 40 83 68 00 (Paris), SWE D EN : (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN : (34) 1 807 1441 (Madrid)