T8100A

T8100A AGERE | Alldatasheet

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Ambassador TM T8100A, T8102, and T8105 H.100/H.110 Interface and Time-Slot Interchangers Introduction This advisory describes a flaw in some devices that the initial factory test program did not detect. The flaw exists in some version 2 and version 3 T8100A, T8102, and T8105 devices in both the SQFP and BGA package types. An enhanced factory test pro- gram has been in place since January 2000, and all devices shipped after this date are good devices. Problem: Data Memory Error An error in the CAM data memories may cause the corruption of stream data bits and/or bytes. The prob- lem may also occur in the microprocessor read path. Stream data may have an occasional '0' that should be a '1'. An entire bad byte may also occur. The prob- lem going away with lower V DD is a prime indicator of this problem. Not all devices are bad. Workaround There is no workaround for this flaw. Corrective Action Version 2 and version 3 devices that have the second line of markings ending with W01, W02, W03, W04, W05, W06, W07, W08, and W09 may be returned through Lucent's return material authorization (RMA) process for replacement or credit. Devices that have the second line of markings ending with W10, W11, and W12 are known good devices and do not have to be returned. T o return devices, contact your sales person for an RMA number. Enter the RMA number within the following return address: Lucent T echnologies Christa Bromfield 555 Union Blvd., Rm. 31L-30R BU Allentown, P A 18103 Explanation of Version Markings The three versions can be identified by markings on the device and apply to the T8100A, T8102, and T8105. Version 1 If there are only seven digits on the last line of the device code marking, and there is not an S following the 4-digit date code, the device is version 1 and applies to both the SQFP and BGA package types. Version 2 1. If there are seven digits on the last line of the device code followed by a space and the letters V2, the device is version 2; or 2. If there is an S following the 4-digit date code on line 2, the device is version 2. This marking applies to both SQFP and BGA package types. Version 3 1. For the BGA package type, if the first line ends in BAL3, the device is version 3; or 2. For the SQFP package type, if the first line ends in SC3, the device is version 3.

Lucent Technologies Inc. reserves the right to ma ke changes to the product(s) or inform ation contained herein without notice. No liability is assum ed as a result of their use or application. No rights under any patent accompa ny the sale of any such product(s) or inform ation. Ambassador is a trademark of Lucent T echnologies Inc. Co pyright © 2000 Lucent Technologies Inc. All Rights Reserved January 2000 AY00-006CTI (Must accompany AY99-030NTNB-4 and DS00-028CTI) For additional information, contact your M icroelectronics Group Account M anager or the following: IN TERNE T: http://www .lucent.com/micro E-M AIL: docm aster@mi cro.lucent.com N. AM ERICA : Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown , PA 18103 1-800-372-2447, FAX 610-712-4106 (In C AN ADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC : Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 C HIN A: M icroelectronics Group, Lucent Technologies (C hina) C o., Ltd., A-F2, 23/F, Zao Fong U niverse Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. C hina Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: M icroelectronics Group, Lucent Technologies Japan Ltd., 7-18, H igashi-G otanda 2-chom e, Shinagaw a-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EU R O PE : D ata Requests: M ICR O ELEC TR O N ICS GR OU P DATALIN E: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries:GE R MA N Y: (49) 89 95086 0 (Munich), U N ITED KIN GDO M : (44) 1344 865 900 (Ascot), FR AN CE : (33) 1 40 83 68 00 (Paris), SWE D EN : (46) 8 594 607 00 (Stockholm), FIN LAND : (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN : (34) 1 807 1441 (Madrid)

November 1999, Rev. 4 Exceptions and Clarifications for Ambassador TM T8100A, T8102, and T8105 H.100/H.110 Interface and Time-Slot Interchangers Device Exceptions Users of the Ambassador T8100A, T8102, and T8105 devices should be aware of the following device operation exceptions and the associated solu- tions: 1. When a compatibility clock is programmed as a slave, and the board generates A or B clocks, the watchdog will indicate an error on the A or B clocks it generates. The error will be reported even though the generated clocks are good. Workaround : Use the master board to accurately monitor the clocks. 2. When a compatibility clock is programmed as a slave, and the clock selector is set to A or B clocks with slide phase alignment, the slave board does not lock and the generated frame continues sliding. Workaround : None. Product Status: Device redesign required. 3. Models of the Ambassador T8100A, T8102, and T8105 devices exhibit intermittent corrupted time- slot data. H.100 stream 0 time slot 1 (for outgoing data) and H.100 stream 1 time slot 127 (for incoming data at 8.192 MHz, time slot 63 for 4.096 MHz, and time slot 31 for 2.048 MHz) are the most likely stream/time slots to be corrupted. However, intermittent time-slot corruption may occur in other stream/time slots. The time-slot corruption problem occurs when a T810x device is used in slave-timing mode, as described in Section 2.5 of the Data Sheet. In a typical slave timing application, a T810x device is set to phase align to an incoming bitclock/frame reference pair (i.e., slave to CT_C8_A/FRAME_A, CT_C8_B/FRAME_B, C4/FR_COMP , etc.). Both SNAP and SLIDE alignment modes are affected. Devices that don't require phase alignment to these clocks (i.e., the primary bus master) should not exhibit stream data corruption. Root Cause: The analog PLL has an error which introduces an unexpected 6 ns—7 ns of skew. This skew causes the phase alignment circuit to fail intermittently, whether in the SNAP or SLIDE mode. An intermittent SLIDE produces an internal frame signal that does not align and phase lock with an incoming frame reference. An intermittent SNAP forces a reset of the internal counters and results in corrupted stream data. Workaround : There is no workaround. The solu- tion is a fix to the silicon. Samples are scheduled for release in August 1999. 4. Version 2 models of the Ambassador T8100A, T8102, and T8105 devices can exhibit intermittent corrupted time slot data in one specific configura- tion. The problem occurs when a master T810x device is given an 8 kHz signal as the timing reference and multiplies it up to 2.048 MHz or 4.096 MHz in the digital PLL (DPLL). The DPLL introduces sufficient jitter on the A or B master output clocks that slave devices falsely interpret as a loss of sync and either snap or slide align to this false sync indication. This, in turn, causes corruption of time slot data. Any master timing ref- erence that does not make use of the DPLL does not exhibit the problem. Workaround : Do not use an 8 kHz signal as the A or B master timing reference, since this requires use of the DPLL. Instead, supply a jitter-free tim- ing reference at any of the other allowable fre- Product Status: The solution is a fix to the silicon.

Lucent T echnologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Ambassador is a trademark of Lucent T echnologies Inc. Copyright © 1999 Lucent T echnologies Inc. All Rights Reserved Printed in U.S.A. November 1999 AY99-030NTNB-4 (Replaces AY99-030NTNB-3 and must accompany DS00-028CTI) For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, P A 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA P ACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent T echnologies (China) Co., Ltd., A-F2, 23/F , Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P . R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAP AN: Microelectronics Group, Lucent T echnologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, T okyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DA T ALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 T echnical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), IT AL Y: (39) 02 6608131 (Milan), SP AIN: (34) 1 807 1441 (Madrid) Advisory November 1999and T8105 H.100/H.110 Interface and Time-Slot Interchangers Exceptions and Clarifications for Ambassador T8100A, T8102, Device Clarifications The three device clarifications listed in this space have been incorporated into DS00-028CTI.

Ambassador TM T8100A, T8102, and T8105 H.100/H.110 Interfaces and Time-Slot Interchangers

1 Product Overview

1.1 Features

■ Complete solution for interfacing board-level cir- cuitry to the H.100 telephony bus ■ H.100 compliant interface; all mandatory signals ■ Programmable connections to any of the 4096 time slots on the H.100 bus ■ Up to 16 local serial inputs and 16 local serial outputs, programmable for 2.048 Mbits/s, 4.096 Mbits/s, and 8.192 Mbits/s operation per CHI specifications ■ Programmable switching between local time slots, up to 1024 connections ■ Subrate switching of nibbles, dibits, or bits ■ Backward compatible to T8100 through software ■ Programmable switching between local time slots and H.100 bus, up to 512 (T8102, T8105 only) connections ■ Choice of frame integrity or minimum latency switching on a per-time-slot basis — Frame integrity to ensure proper switching of wideband data — Minimum latency switching to reduce delay in voice channels ■ On-chip phase-locked loop (PLL) for H.100, MVIP *, or SC-Bus clock operation in master or slave clock modes ■ Serial TDM bus rate and format conversion between most standard buses ■ Optional 8-bit parallel input and/or 8-bit parallel output for local TDM interfaces ■ High-performance microprocessor interface — Provides access to device configuration regis- ters and to time-slot data — Supports both Motorola† nonmultiplexed and Intel‡ multiplexed/nonmultiplexed modes ■ T wo independently programmable groups of up to 12 framing signals each ■ Devices available in 0.25 micron technology ■ 3.3 V supply with 5 V tolerant inputs and TTL-com- patible outputs ■ Boundary-scan testing support ■ 208-pin, plastic SQFP package ■ 217-ball BGA package (industrial temperature range)

1.2 Description

These products in the Ambassador T8100 family pro- vide a complete time-slot switch and an interface for the H.100/H.110 time-division multiplexed (TDM) buses. The T8100 family includes devices with hier- archical switching as well as a capacity of up to 512 local to H.100 connections. The hierarchical switch- ing allows up to 1024 local connections without using H.100 bus bandwidth. The family also includes the T8102 device for a low-cost solution in nonhierarchi- cal systems. All three TSI chips are backward compatible with the bus standards MVIP -90 and Dialogic's§ SC-Bus, as well as supporting the newer standards, H-MVIP and ECTF H.100. Other features include a built-in PLL for H.100, MVIP, or SC-Bus clock operation in master or slave clock modes and two independently program- mable groups of up to 12 framing signals each. Pack- aged in both a 208-pin SQFP and a 217-ball BGA, the T8100 TSI devices provide an economic solution for the computer telephony market. * MVIP is a registered trademark of GO-MVIP , Inc. † Motorola is a registered trademark of Motorola, Inc. ‡ Intel is a registered trademark of Intel Corporation. § Dialogic is a registered trademark of Dialogic Corporation.

2 Lucent Technologies Inc. Advance Data Sheet November 1999H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105 Table of Contents Contents Page 1.4

1.5 Selecting Between T8105, T8102, T8100A,

1.9 Phase Alignment of Referenced and

2.2.1 Constant Frame Delay and Minimum

2.2.6 Software to Reset the Local Connection

2.3.5 H-Bus Rate Selection and Connection

2.4 Subrate Switching for the

2.5.8.2 CKMD, CKND, CKRD: Clocks, Main,

NETREF, Resource Dividers

2.5.9.3 Example of LREF Pairing on a T8100A 58

3.3.2 H.100/H.110 Data Pin Series

3.4 Using the LAR, AMR, and IDR for

3.4.1 Setting Up Local Connections (T8100A,

4.6.1 Electrical Drive Specifications—CT_C8

4.10.1 Microprocessor Access

4.10.2 Microprocessor Access Motorola Write

4.10.3 Microprocessor Access Intel Demultiplexed

Figure 7. Local Memory (T8100A, T8105 Only), Figure 8. Simplified Local Memory State Figure 10. Simplified H-Bus State Timing, Figure 14. Unpacking Example Using Local Figure 15. Constant Delay/Minimum Delay Figure 17. A, B, and C Clock Fallback State Figure 22. Local-to-Local Connection Figure 23. CAM Programming, H-Bus-to-Local Figure 28. ac Electrical Characteristics, Figure 29. Microprocessor Access Figure 30. Microprocessor Access Intel Figure 31. Microprocessor Access Motorola Figure 32. Microprocessor Access Motorola Figure 33. Microprocessor Access Intel Figure 34. Microprocessor Access Intel

Table 43. HSL: H-Bus Stream Control, Low Byte, Table 44. HSL: H-Bus Stream Control, High Byte, Table 46. CKM: Clocks, Main Clock Selection, Table 47. CKN: Clocks, NETREF Selections, Table 48. CKP: Clocks, Programmable Outputs, Table 49. CKR: Clocks, Resource Selection, Table 50. CKS: Clocks, Secondary (Fallback) Table 51. CK32 and CK10: Clocks, Locals 3, 2, 1, Table 55. FRHA, Frame Group A High Address Table 56. FRHB, Frame Group B High Address Table 57. FRPH: Frame Group B, Programmed Table 58. CLKERR1 and CLKERR2: Error Indicator Table 59. CLKERR3: Error Indicator and Current Table 60. SYSERR: System Error Register, Table 67. GMODE: Table 70. IDR: Indirect Data Register, Local Table 71. IDR: Indirect Data Register, H-Bus Table 74. Electrical Drive Specifications—CT_C8 Table 75. dc Electrical Characteristics, All Table 76. ac Electrical Characteristics, Timing, Table 77. ac Electrical Characteristics, Skew Table 79. ac Electrical Characteristics, Local Table 80. L_SC[3:0] and Frame Group Rise and Table 82. Clock Register Programming Profile for

1 Product Overview (continued)

1.3 Pin Information

Figure 1. 208 SQFP—Top View

1.3 Pin Information (continued)

Figure 2. 217 PBGA—Top View

Table 1. Pin Descriptions: Clocking and Framing Pins I Local Frame Reference Inputs. 50 kΩ internal pull-up. Schmitt in, 50 kΩ internal pull-up. Schmitt in, 50 kΩ internal pull-up. 8.192 MHz, 16.384 MHz, frame (8 kHz), or secondary (NETREF). O Frame Group A. 8 mA drive, 3-state. O Frame Group B. 8 mA drive, 3-state. PRIREFOUT 58 P5 O Output from Primary Clock Selector/Divider. 8 mA drive. may be driven with RESET line. 50 kΩ internal pull-up. 4MHZIN 54 U2 I PLL #1 Rate Multiplier. Can be 2.048 MHz or 4.096 MHz. may be driven with RESET line. 50 kΩ internal pull-up. 3MHZIN 1 A1 I PLL #2 Rate Multiplier. Input, 50 kΩ internal pull-up. XTALIN 47 R2 I 16.384 MHz Crystal Connection or External Clock Input. XT ALOUT 48 T1 O 16.384 MHz Crystal, Feedback Connection. TCLKOUT 203 C4 O Selected output to drive framers. 8 mA drive, 3-state.

Table 2. Pin Descriptions: Local Streams Pins Table 3. Pin Descriptions: H-Bus Pins 24 mA drive, Schmitt in. No pull-up. compliant, 24 mA drive. Schmitt in. No pull-up. Schmitt in, 50 kΩ internal pull-up. or 1.544 MHz. PCI driver. Not internally pulled up. or 1.544 MHz. PCI driver. Not internally pulled up. 24 mA drive, Schmitt in. No pull-up. compliant, 24 mA drive, Schmitt in. No pull-up. 3.3.5 Physical Connections for H.110. CT_Dxx only for H.100, low disables for H.110.

Table 4. Pin Descriptions: Microprocessor Interface Pins Table 5. Pin Descriptions: JTAG Pins I Microprocessor Interface, Address Lines. Internal 20 kΩ pull-down. I/O Microprocessor Interface, Data Lines. 8 mA drive, 50 kΩ internal pull-up. ALE 29 L1 I Address Latch Enable. Internal 20 kΩ pull-down. CS 28 K3 I Chip Select (Active-Low). 50 kΩ internal pull-up. Low]). 50 kΩ internal pull-up. Low]). 50 kΩ internal pull-up. RDY (DT ACK) 25 J3 O Data Ready (Intel), Data Transfer (Motorola [Active-Low]). 8 mA, open drain (user should add pull-up to this line). TCLK 9 E3 I JTAG Clock Input. TMS 8 F4 I JTAG Mode Select. 50 kΩ internal pull-up. TDI 7 D2 I JTAG Data Input. 50 kΩ internal pull-up. TDO 6 C1 O JTAG Data Output. 8 mA drive, 3-state. TRST 5E 4 I JTAG Reset (Active-Low). 50 kΩ internal pull-up.

Table 6. Pin Descriptions: Power Pins Table 7. Pin Descriptions: Other Pins 0.1 µF capacitor to provide additional decoupling. drive, Schmitt in, 50 kΩ internal pull-up. NETREF) or GP Register Bit 6. 8 mA drive, Schmitt in, 50 kΩ internal pull-up.

1212 Lucent Technologies Inc. Advance Data Sheet November 1999H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105

1.4 Ambassador TSI Architecture

The Ambassador programmable TSIs have been designed to meet today’s switching requirements. The T8100A and T8105 TSIs have a hierarchical switching capability. They can switch between the local input bus and the local output bus. They also switch between the H.100/H.110 bus and local bus. The T8102 TSI switches between the H.100/H.110 bus and the local bus. All three TSIs have circuitry for subrate switching and can interface to other computer telephony standards such as MVIP, SC-Bus, and MC-1*.

1.5 Selecting Between T8105, T8102,

T8100A, and T8100

1.6 Enhanced Local Stream Addressing

Local stream addressing has 1024 locations. Separate connection and data memories (T8100A, T8105 only) maintain all necessary information for local stream interconnections. The streams may operate at maxi- mum rate on eight physical inputs and eight physical outputs. Choices for slower input or output rates allow enabling of additional physical inputs or outputs for a maximum of 16 pins each. Data rates are 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s. In addition to the enhanced serial streaming, the local memories may be used for 8-line-serial-in/1-byte-paral- lel-out, 1-byte-parallel-in/8-line-serial-out, or 1-byte- parallel-in/1-byte-parallel-out options. All three data rates are supported in the parallel modes. The addresses for the local memories (T8100A, T8105 only) have been simplified so that stream and time-slot designations are automatically translated to the appro- priate memory address, regardless of rate or serial/par- allel modes. * MC-1 is a multichassis communication standard based on MVIP. The devices support this standard. 1.7 Full H.100 Stream Address Support The devices provide access to the full 4096 H.100 bus slots (32 streams x 128 slots) or any standard subset (H- MVIP has a maximum 24 streams x 128 time slots, for example). The number of stored time-slot addresses is limited to 512 (T8102, T8105 only) at any one time, but these may be updated on the fly. In addi- tion, accesses to and from the H.100 bus can be directed through the 1024 local stream/time slots, giv- ing a total space of 5120 time slots. Data rates are pro- grammable on each of the 32 physical streams, selected in groups of four. The rates are 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s.

1.8 Onboard PLLs and Clock Monitors

The devices use rate multipliers and state machines to generate onboard frequencies for supporting the H.100, H- MVIP, MVIP, MC-1, and SC-Buses. Pins are provided for coupling the internal clock circuitry with commonly available clock adapters and jitter attenua- tors. If external resources are not available, an internal digital phase-locked loop (DPLL) can be used to gener- ate all the bus frequencies and remain synchronized to an 8 kHz reference. One of several clock input refer- ence sources may be selected, and separate input- active detection logic can identify the loss of the individ- ual input references. The entire clocking structure oper- ates from a 16.384 MHz crystal or external input. If this resource is selected, special control logic will cre- ate bit-sliding in the data streams when the reference frame and generated frame are out of phase. The bit- sliding refers to removing a fraction of a bit time per frame until the frames are in phase. Features T8100 T8100A T8102 T8105 Subrate switching — √√ √ Local-to-local connections 1,024 1,024 — 1,024 Local-to-H.100 connections 256 256 512 512 CT_NETREFs 1 22 2

Lucent Technologies Inc. 13 Advance Data Sheet November 1999 H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105

1.10 Interfaces

1.10.1 Microprocessors

The devices provide the user a choice of either Motor- ola or Intel interfacing through an 8-bit data bus, a 2-bit address bus, and multifunction control pins. All access to the devices’ memory blocks and registers use indi- rect addressing.

1.10.2 Framing Groups

T wo groups of programmable framing signals are avail- able. Each group is composed of 12 sequenced lines operating in one of four modes. The devices support 1-bit, 2-bit, 1-byte, and 2-byte pulse widths. Starting position of the pulse sequences are also programma- ble.

1.10.3 General-Purpose Register and I/O

A general-purpose, 8-bit, input/output port is provided as either byte-wide I/O or bit addressed I/O.

1.11 Applications

■ Computer-telephony systems ■ Enhanced service platforms ■ WAN access devices ■ PBXs ■ Wireless base stations

1.12 Application Overview

The integration of computers and telecommunications has enabled a wide range of new communications applications and has fueled an enormous growth in communications markets. A key element in the devel- opment of computer-based communications equipment has been the addition of an auxiliary telecom bus to existing computer systems. Most manufacturers of high-capacity, computer-based telecommunications equipment have incorporated some such telecom bus in their systems. T ypically, these buses and bus interfaces are designed to transport and switch N x 64 kbits/s low-latency telecom traffic between boards within the computer, independent of the com- puter’s I/O and memory buses. At least a half dozen of these PC-based telecom buses emerged in the early 1990s for use within equipment based on ISA/EISA and MCA computers. With the advent of the H.100 bus specification by the Enterprise Computer T elephony Forum, the computer- telephony industry has agreed on a single telecom bus for use with PCI and compact PCI computers. H.100 facilitates interoperation of components, thus providing maximum flexibility to equipment manufacturers, value- added resellers, system integrators, and others build- ing computer-based telecommunications applications.

2 Architecture and Functional

Description

The devices are H.100-compliant and provide a com- plete interface between the H.100 bus and a wide vari- ety of telephony interface components, processors, and other circuits. The bus interface provides all signals needed for the H.100 bus, the H- MVIP and MVIP -90 buses, or the SC-Bus. Local interfaces include 16 serial inputs and 16 serial outputs based on the Lucent T ech- nologies Microelectronics Group concentration high- way interface (CHI). The T8100A and the T8105 include two built-in time-slot interchangers. The first provides a local switching domain with up to 1024 pro- grammable connections between time slots on the local CHI inputs and outputs. The second provides program- mable connections between any time slot on the H.100 bus and any time slot in the local switching domain. The T8105 has 512 programmable connections while the T8100A has 256. The T8102 has only 1 TSI for switching up to 512 programmable connections on the H.100 bus and any time slot in the local switching domain. All Ambassador devices are configured via a microprocessor interface. This interface can also read and write time slot and device data. Onboard clock cir- cuitry, including a DPLL, supports all H.100 clock modes including MVIP and SC-Bus compatibility clocks. The local CHI interfaces support PCM rates of 2.048 Mbits/s, 4.096 Mbits/s, and 8.192 Mbits/s. Each device has internal circuitry to support either minimum latency or multi-time-slot frame integrity. Frame integrity is a requisite feature for applications that switch wide- band data (ISDN H-channels). Minimum latency is advantageous in voice applications. All three TSIs have the following four major sections: ■ Local bus—refers to the local streams. ■ H-bus—refers to the H.100/H.110/H-MVIP and legacy streams. ■ Interface—refers to the microprocessor interface, frame groups, and general-purpose I/O (GPIO). ■ Timing—the rate multipliers, DPLL, and clocking functions.

2 Architecture and Functional Description (continued)

I/Os, though the I/Os are TTL compatible and 5 V tolerant.

• For T8100 and T8100A, there are only 256 locations.

† T8102 does not have local data memory. Figure 3. Block Diagram of the TSI Devices

2.1 Register/Memory Maps

LAR, AMR, and IDR for Connections.

2.1.1 Main Registers

The address bits are used to map a large memory space. All registers default to 0 at powerup. Table 8. Addresses of Programming Registers

2.1.2 Master Control and Status Register

Table 9. Master Control and Status Register MR 7 Master (Software) Reset. A high reinitializes the registers. CER 6 Clock Error Reset. A high resets the error bits of the CLKERR registers. accessed during a write operation (i.e., input from local streams or input from H-bus). HBE 3 H-Bus Enable. On powerup or software reset, all H-bus pins (including clocks) are disabled. HBE must be set high to reenable the 3-stated buffers. LBE 2 Local Bus Enable. Same function as HBE for local data outputs. trol Register Definitions for a description of the CKP register.) 3-stated if disabled. microprocessor, which allow it to finish quickly.

2.1 Register/Memory Maps (continued)

2.1.3 Address Mode Register

Note: All unused AMR values are reserved. Table 10. Address Mode Register 0000 0000 Control Registers. 0001 (aaaa) Local Bus, Data Memory 1. 0010 (aaaa) Local Bus, Data Memory 2. 0100 (aaaa) Local Bus, Connection Memory, Time-Slot Field. 0101 (aaaa) Local Bus, Connection Memory, Stream, and Control Bit Field. 0111 0000 Local Bus, Holding Registers, Reset. CAM, Data Memory 1. Lower 256 Addresses. CAM, Data Memory 1. Upper 256 Addresses (T8102, T8105 only). CAM, Data Memory 2. Lower 256 Addresses. CAM, Data Memory 2. Upper 256 Addresses (T8102, T8105 only). 1011 0000 CAM, Connection, Time-Slot Field. 1011 0001 CAM, Connection, Stream, and Control Bit Field. 1011 0010 CAM, Connection, T ag Field. 1011 0011 CAM, Connection, Subrate Control, T ag Field MSB. 1110 0000 CAM, Even, Make Connection (MKCE). Write to Next Free Location. 1110 0001 CAM, Odd, Make Connection (MKCO). Write to Next Free Location. 1110 0011 CAM, Local, Make Connection (MKCL). Write to Next Free Location. 1110 0100 CAM, Even, Break Connection (BKCE). 1110 0101 CAM, Odd, Break Connection (BKCO). 1110 0111 CAM, Local, Break Connection (BKCL). CAM, Even, Clear Location (CLLE). Lower 256 Range. Requires LAR. CAM, Even, Clear Location (CLLE). Upper 256 Range. Requires LAR (T8102, T8105 only). CAM, Odd, Clear Location (CLLO). Lower 256 Range. Requires LAR. CAM, Odd, Clear Location (CLLO). Upper 256 Range. Requires LAR (T8102, T8105 only). CAM, Local, Clear Location (CLLL). Lower 256 Range. Requires LAR. CAM, Local, Clear Location (CLLL). Upper 256 Range. Requires LAR (T8102, T8105 only). CAM, Even, Read Location (RDCE). Lower 256 Range. Requires LAR, IDR Holds Results. CAM, Even, Read Location (RDCE). Upper 256 Range. Requires LAR, IDR Holds Results (T8102, T8105 only). CAM, Odd, Read Location (RDCO). Lower 256 Range. Requires LAR, IDR Holds Results. CAM, Odd, Read Location (RDCO). Upper 256 Range. Requires LAR, IDR Holds Results (T8102, T8105 only). CAM, Local, Read Location (RDCL). Lower 256 Range. Requires LAR, IDR Holds Results. CAM, Local, Read Location (RDCL). Upper 256 Range. Requires LAR, IDR Holds Results (T8102, T8105 only). 1111 0000 CAM, Even, Find Entry (FENE). IDR Holds Results. 1111 0001 CAM, Odd, Find Entry (FENO). IDR Holds Results. 1111 0011 CAM, Local, Find Entry (FENL). IDR Holds Results. 1111 1000 CAM, Even, Reset (RSCE). 1111 1001 CAM, Odd, Reset (RSCO). 1111 1011 CAM, Local, Reset (RSCL). 1111 1100 CAM, Holding Registers, Reset (RCH). 1111 1111 CAM, Initialize (CI). Reset All CAM Locations and Holding Registers.

2.1.4 Control Register Memory Space

icant bit) and LSB (least significant bit) are shown. Table 11. Control Register Memory Space

1818 Lucent Technologies Inc.

2.1.4 Control Register Memory Space (continued)

ters and their interactions with the overall architecture. Table 12. CKM: Clocks, Main Clock Selection, 0x00 Table 13. CKN: Clocks, NETREF Selections, 0x01 Table 14. CKP: Clocks, Programmable Outputs, Table 15. CKR: Clocks, Resource Selection, 0x03 Table 16. CKS: Clocks, Secondary (Fallback) Table 17. CK32: Clocks, Locals 3 and 2, 0x05 Table 18. CK10: Clocks, Locals 1 and 0, 0x06

7 Phase Alignment Enable

6 Phase Alignment Select

5 Compatibility Clock Direction

4 Input Clock Invert

3 Input Clock Select, MSB

2 Input Clock Select

1 Input Clock Select

0 Input Clock Select, LSB

7 NETREF1 Output Enable

6 NETREF2 Output Enable

5 Bypass Select

7 TCLK Select, MSB

6 TCLK Select

5 TCLK Select, LSB

4 CT_C8 Pins, Input Type Select

3 CT_C8A Output Enable

2 CT_C8B Output Enable

1 CT_C8 Pins, Output T ype Select

7 Resource Select, MSB

6 Resource Select, LSB

5 PLL #1 Bypass

4 PLL #1 Rate Select

3 PLL #2 Bypass

2 PLL #2 Rate Select

1 SCLK Output Select, MSB

0 SCLK Output Select, LSB

7 Secondary Resource Select, MSB

6 Secondary Resource Select, LSB

5 Fallback T ype Select, MSB

4 Fallback T ype Select, LSB

3 Fallback, Force Selection of Secondary Input

2 Secondary Input Clock Select, MSB

1 Secondary Input Clock Select

0 Secondary Input Clock Select, LSB

7 Local Clock 3 Select, MSB

6 Local Clock 3 Select

5 Local Clock 3 Select

4 Local Clock 3 Select, LSB

3 Local Clock 2 Select, MSB

2 Local Clock 2 Select

1 Local Clock 2 Select

0 Local Clock 2 Select, LSB

7 Local Clock 1 Select, MSB

6 Local Clock 1 Select

5 Local Clock 1 Select

4 Local Clock 1 Select, LSB

3 Local Clock 0 Select, MSB

2 Local Clock 0 Select

1 Local Clock 0 Select

0 Local Clock 0 Select, LSB

Table 19. CKMD: Clocks, Main Divider; CKND: Table 20. LBS: Local Stream Control, 0x0C Table 21. CON: Connection Delay Type, 0x0E Table 22. HSL: H-Bus Stream Control, Low Byte, Table 23. HSH: H-Bus Stream Control, High Byte, Table 24. GPD, General-Purpose Direction Control

7 Divide Value, MSB

6 Divide Value

5 Divide Value

4 Divide Value

3 Divide Value

2 Divide Value

1 Divide Value

0 Divide Value, LSB

7 Parallel/Serial Select, MSB

6 Parallel/Serial Select, LSB

5 Local Group A Rate Select, MSB

4 Local Group A Rate Select, LSB

3 Local Group B Rate Select, MSB

2 Local Group B Rate Select, LSB

1 Local Group C Rate Select, MSB

0 Local Group C Rate Select, LSB

7 Reserved

6 Enable GPD (bitwise general-purpose

5 Select NETREF1/NETREF2 as main clock in.

4 L_REF type select (stand-alone or paired)

3 Invert L_REF Frame Strobe

2 Invert L_REF Bit Clock

1 Disable Connection-by-Connection Delay

0 Global FME Setting

7 H-Bus Group D Rate Select, MSB

6 H-Bus Group D Rate Select, LSB

5 H-Bus Group C Rate Select, MSB

4 H-Bus Group C Rate Select, LSB

3 H-Bus Group B Rate Select, MSB

2 H-Bus Group B Rate Select, LSB

1 H-Bus Group A Rate Select, MSB

0 H-Bus Group A Rate Select, LSB

7 H-Bus Group H Rate Select, MSB

6 H-Bus Group H Rate Select, LSB

5 H-Bus Group G Rate Select, MSB

4 H-Bus Group G Rate Select, LSB

3 H-Bus Group F Rate Select, MSB

2 H-Bus Group F Rate Select, LSB

1 H-Bus Group E Rate Select, MSB

0 H-Bus Group E Rate Select, LSB

7 Direction Control for GPR Bit 7, 0 = In; 1 = Out. 6 Direction Control for GPR Bit 6, 0 = In; 1 = Out. 5 Direction Control for GPR Bit 5, 0 = In; 1 = Out. 4 Direction Control for GPR Bit 4, 0 = In; 1 = Out. 3 Direction Control for GPR Bit 3, 0 = In; 1 = Out. 2 Direction Control for GPR Bit 2, 0 = In; 1 = Out. 1 Direction Control for GPR Bit 1, 0 = In; 1 = Out. 0 Direction Control for GPR Bit 0, 0 = In; 1 = Out.

2020 Lucent Technologies Inc. Table 25. GPR: General-Purpose I/O Register, 0x18 Table 26. FRLA: Frame Group A, Start Address Table 27. FRHA: Frame Group A, High Address and Table 28. FRLB: Frame Group B, Start Address Table 29. FRHB: Frame Group B, High Address and

7 General-Purpose I/O, MSB

6 General-Purpose I/O

5 General-Purpose I/O

4 General-Purpose I/O

3 General-Purpose I/O

2 General-Purpose I/O

1 General-Purpose I/O

0 General-Purpose I/O, LSB

7 Start Address, Bit 7, or Programmed Output,

6 Start Address, Bit 6, or Programmed Output,

5 Start Address, Bit 5, or Programmed Output,

4 Start Address, Bit 4, or Programmed Output,

3 Start Address, Bit 3, or Programmed Output,

2 Start Address, Bit 2, or Programmed Output,

1 Start Address, Bit 1, or Programmed Output,

0 Start Address, LSB, or Programmed Output,

7 Rate Select, MSB

6 Rate Select, LSB

5 Pulse Width Select, MSB

4 Pulse Width Select, LSB

3 Frame Invert, or Programmed Output, Bit 11

2 Start Address, MSB, or Programmed Output,

1 Start Address, Bit 9, or Programmed Output,

0 Start Address, Bit 8, or Programmed Output,

7 Start Address, Bit 7

6 Start Address, Bit 6

5 Start Address, Bit 5

4 Start Address, Bit 4

3 Start Address, Bit 3

2 Start Address, Bit 2

1 Start Address, Bit 1

0 Start Address, LSB

3 Frame Inversion Select

2 Start Address, MSB

1 Start Address, Bit 9

0 Start Address, Bit 8

Table 30. FRPL: Frame Group B, Programmed Table 31. FRPH: Frame Group B, Programmed Table 32. CLKERR1: Clock Error Register, Error Table 33. CLKERR2: Clock Error Register, Current Table 34. SYSERR: System Error Register, 0x2A Table 35. CKW: Clock Error/Watchdog Masking Table 36. CLKERR3: Clock Error Register, Current

7 Programmed Output, Bit 7

6 Programmed Output, Bit 6

5 Programmed Output, Bit 5

4 Programmed Output, Bit 4

3 Programmed Output, Bit 3

2 Programmed Output, Bit 2

1 Programmed Output, Bit 1

0 Programmed Output, Bit 0

7 Group A Output Pins Select, MSB

6 Group A Output Pins Select, LSB

4 Group B Output Pins Select

3 Programmed Output, Bit 11

2 Programmed Output, Bit 10

1 Programmed Output, Bit 9

0 Programmed Output, Bit 8

7 C8A or Frame A Error

6 C8B or Frame B Error

4 C16+ or C16– Error

3 C4n or C2 Error

1 SCLK Error

0 NETREF Error

7 C8A or Frame A Fault Status

6 C8B or Frame B Fault Status

4 C16+ or C16– Fault Status

3 C4n or C2 Fault Status

1 SCLK Fault Status

0 NETREF[2:1] Fault Status

7 Even CAM Underflow Error (No Match)

6 Odd CAM Underflow Error (No Match)

5 Local CAM Underflow Error (No Match)

4 Even CAM Overflow or No-Match Error

3 Odd CAM Overflow or No-Match Error

2 Local CAM Overflow or No-Match Error

1 H-Bus Data Memory Access Error

0 Fallback Enable Indicator

7 C8A and Frame A Error Mask

6 C8B and Frame B Error Mask

4 C16+ and C16– Error Mask

1 SCLK Error Mask

0 NETREF1 Error Mask

5 NETREF2 Error

4 NETREF1 Error

0 NETREF2 Error Mask

2222 Lucent Technologies Inc. Table 37. DIAG1: Diagnostics Register 1, 0x30 Table 38. DIAG2: Diagnostics Register 2, 0x31 Table 39. DIAG3: Diagnostics Register 3, 0x32 Table 40. DEV_ID: Device Identification Register, Table 41. GMODE: Global Mode Register, 0xFF

7 Frame Group A Output Select, MSB

6 Frame Group A Output Select, LSB

5 Frame Group B Output Select, MSB

4 Frame Group B Output Select, LSB

3 Memory Fill Enable

2 Memory Fill Pattern Select, MSB

1 Memory Fill Pattern Select, LSB

0 Memory Fill Status Bit (Read Only)

7 Frame Groups Cycle Test Enable

6 Break State Counter into Subsections

5 Bypass Internal Frame with /FR_COMPn

3 Enable State Counter Parallel Load

2 Parallel Load Value of State Counter, MSB

1 Parallel Load Value of State Counter, Bit 9

0 Parallel Load Value of State Counter, Bit 8

7 Parallel Load Value of State Counter, Bit 7

6 Parallel Load Value of State Counter, Bit 6

5 Parallel Load Value of State Counter, Bit 5

4 Parallel Load Value of State Counter, Bit 4

3 Parallel Load Value of State Counter, Bit 3

2 Parallel Load Value of State Counter, Bit 2

1 Parallel Load Value of State Counter, Bit 1

0 Parallel Load Value of State Counter, LSB

7 Device Identification Number, MSB

6 Device Identification Number

5 Device Identification Number

4 Device Identification Number, LSB

3 Device Version Number, MSB

2 Device Version Number

1 Device Version Number

0 Device Version Number, LSB

7 Mode Emulation Set 2 (ME2)

6 Mode Emulation Set 1 (ME1)

5 Subrate Enable (SE)

3 EMUL, MSB

0 EMUL, LSB

2.2 Local Bus Section

Figure 4 shows the local bus section function diagram. associated with it by one time slot. Figure 4. Local Bus Section Function and local data memory for time-slot interchanging.

1024 LOCATIONS

2.2 Local Bus Section (continued)

2.2.1 Constant Frame Delay and Minimum Delay Connections

Figure 5. Local Bus Memory Connection Modes

2.2.2 Serial and Parallel

read of the data memory. Unused S/P or P/S converters are nonfunctional in these modes. Note: The normal serial-to-serial local streaming is not available simultaneously with any of the parallel modes.

2.2.3 Data Rates and Time-Slot Allocation

to process 1024 nonblocking local-to-local connections. group B is operating below 8.192 Mbits/s. regardless of their activation or rate.

8.192 Mbits/s time slots: first group A from 0 through 7,

illustrate how the memory utilization works. into four groups of 4, correspond to the 16 streams. The columns correspond to 64 time-slot addresses. Figure 6. Local Streams, Memory Structure

2.2.3 Data Rates and Time-Slot Allocation (continued)

Examples of how the memory is filled are found in Figure 7. virtual memory space of 4 x 64 locations is created from unused locations in other parts of the memory. Figure 7. Local Memory (T8100A, T8105 Only), Fill Patterns

Figure 7. Local Memory (T8100A, T8105 Only), Fill Patterns (continued) skipped), and at 2.048 Mbits/s, every second even location is scanned.

2.2.4 LBS: Local Stream Control, 0x0C

Table 42. LBS: Local Stream Control, 0x0C P/S 7—6 P/S = 00. Serial In/Serial Out. The SGb bits are enabled when SGa ≠ 11. The SGc bits are enabled when SGb ≠ 11. P/S = 01. Serial In/Parallel Out. SGa sets input (serial) rate using the rate definition within this table. SGc sets the output (parallel) rate using the rate definition within this table. P/S = 10. Parallel In/Serial Out. SGa sets input (parallel) rate. SGc sets output (serial) rate. P/S = 11. Parallel In/Parallel Out. SGa sets input (parallel) rate. SGc sets output (parallel) rate.

2.2.5 State Counter Operation

tures. The H-bus memories are discussed in Section 2.3 H-Bus Section. Figure 8. Simplified Local Memory State Timing, 65.536 MHz Clock

2.2.6 Software to Reset the Local Connection Memory

1. Monitor Diag-1, 0x30, bit 0. This bit is set when the operation is complete (steps 1 through 3).
2. Write IDR = 0x00. This brings the device out of diagnostics mode.

address. The upper 6 bits are cleared to zero. The lower 10 bits will have an address.

3030 Lucent Technologies Inc.

2.3 H-Bus Section

2.3.1 Memory Architecture

each, and one CAM for all 16 local input/output pairs. Figure 9. The combined comparison plus retrieval SRAM (actually, a register file) is tied to each CAM. and as illustrated in Figure 5.

2.3 H-Bus Section (continued)

2.3.1 Memory Architecture (continued)

Figure 9. CAM Architecture above 512 simplex if the connection type is broadcast, i.e., from one to many.

3 CAMS, MAXIMUM OF 48 ACCESSES PER 976 ns

3232 Lucent Technologies Inc. Advance Data Sheet November 1999H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105 Description (continued)

2.3.2 CAM Operation and Commands

The three CAMs operate in parallel. Each CAM’s com- parand field is compared with the state counter (Sec- tion 2.2.5 State Counter Operation) which holds the existing stream and time-slot value*. If there is a match, the CAM issues a hit. If there is more than one match, then it is considered a multiple hit. Likewise, no match is a miss. As a part of the state counter, a bit is toggled for read/write. The read/write bit is stored in the CAM, so it becomes part of the value to be compared. If the comparison for a write yields a hit, then there is a request for write access to the data memory for the incoming data from the H-bus. If the comparison for a read yields a hit, then there is a request for a read access from the data memory for outgoing data to the H-bus. A miss implies no action. Any multiple hit within one CAM block is treated as a controlled error although it is not reported. The action taken is to acknowledge the hit which corresponds to the lowest physical address of the CAM. A multiple hit is assigned to be more than one valid connection. These are prioritized such that the match with the lowest physical address (i.e., closest to CAM location 0x0) is the address which is processed. Thus, errors are handled in a controlled manner. Multiple hits can occur because multiple loca- tions are assigned to the same time slot. Good soft- ware and careful coding can help avoid this problem. A controlled error has no impact on performance, and the CAM contents are not changed as a result of the error. The data SRAMs are actually dual-port register files which will process both writes and reads on each clock cycle of the clock. The devices can process a read and write request from each CAM and two microprocessor requests during the time of one address comparison. Due to the fixed order of operations, the data SRAM cannot overflow or underflow like the CAMs. The timing is shown in Figure 10. * As mentioned in Section 2.2.5 State Counter Operation, for each stream and time-slot value, the state counter goes through four functional states for each stream and time slot. These states are used to synchronize the CAMs, pipeline register files, data SRAMs, and microprocessor accesses just as they are used to synchronize local memory operations and the frame groups. (Microprocessor accesses to the memories are initiated asynchronously, though the actual microprocessor cycles are synchronous.)

2.3.2 CAM Operation and Commands (continued)

Figure 10. Simplified H-Bus State Timing, 65.536 MHz Clock

3434 Lucent Technologies Inc. Advance Data Sheet November 1999H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105 Description (continued) A number of commands are available to control the CAMs. Connections can be made or broken, entry data can be searched for, individual locations may be read or cleared, or the CAMs can be reset. The address mode register (AMR) (see Section 2.1 Register/Mem- ory Maps) is used to issue the CAM control commands. Some commands require the use of the lower address register (LAR), and some use the IDR as a transfer reg- ister. The tags in each CAM’s associated register file refer- ence the storage location of the data being transferred, so each CAM/tag location also has control information. The three control bits are read-to/write-from data SRAM (i.e., a direction bit, located in the CAM and used during the comparison operations), a pattern mode enable, which bypasses the data SRAM and out- puts the tag directly into the specified time slot for writes to the bus, and an SRAM buffer select that con- trols the minimum delay or constant delay select, equivalent to the local memory’s (T8100A, T8105 only) selection of minimum or constant delay. In addition, the CAM carries a valid entry bit. This is an identifier for the status of the CAM (and corresponding register file) location. If the bit is low, as all validity bits are after a reset, then the location is available to be written into. When data is written into a location, then this bit is set, indicating that this is a valid entry. If spe- cific data is no longer valid, such as when a connection is broken, then the bit is cleared. The CAM commands make use of either one or two cycles. The two cycles are described pictorially in Fig- ure 11. The reader will note that matching and retrieval are actually separate cycles. The need for two cycles accounts for the requirement of the pipeline register files. Detailed descriptions of the commands follow: The basic make connection command is referred to as MKCn, where n is the CAM designator*. The MKCn uses two CAM cycles: first, the CAM is searched to determine where to find the next free location (as deter- mined by the validity bits), and during the second cycle, the next empty location is written into. The MKCn com- mand uses holding registers which convey the connec- tion information to the CAM and its associated register file. The four holding registers contain the lower con- nection address (i.e., time slot), the upper connection address (stream plus control bits), the tag LSBs, the subrate control (7 bits), and the tag MSB. An attempt to write to a full CAM (all 512 locations fully occupied in the T8102 and T8105) results in an overflow error flagged through the system error register, SYSERR (see Section 2.7 Error Registers). Note: A single MKCn command only specifies one- half of a connection. The MKCn specifies the connection address and a pointer to the data memory, but a second connection address and pointer to the same data memory location must also be provided for a complete connection. * The H-bus CAM covering the 16 even-numbered H-bus streams is designated E, the H-bus CAM covering the 16 odd-numbered H-bus streams is designated O, and the CAM that services the 16 local stream pairs is designated L.

Figure 11. Illustration of CAM Cycles

3636 Lucent Technologies Inc. Advance Data Sheet November 1999H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105

2 Architecture and Functional Descrip-

tion (continued) If the user determines that a stream/time slot is no longer valid, then the validity bit may be cleared by pre- senting the connection address to the CAM and by using the BKCn, break connection, command. The connection that the user intends to break, which con- sists of the time slot, and the stream plus control bits, but not the tag, is transferred to the holding registers prior to issuing this command. This is a two-cycle com- mand: during the first cycle, the connection address is presented to the CAM to identify which physical loca- tion holds that connection address, and then, in the second cycle, the validity bit is cleared for the identified physical location. If there is a miss, it flags a no-match error through the underflow bit in SYSERR. Note: A complete connection break requires two BKCn commands, one for each half of the con- nection, as with the MKCn command. The clear location (upper/lower) command, CLLn, is a one-cycle command. The LAR contains the physical address (i.e., the physical CAM location) to be cleared (when AMR bit 5 equals 1, the lower bits, 0—255, are cleared; when 0, the upper bits, 256—511, are cleared). When it is presented to the CAM, the validity bit is cleared, returning the location to an empty status (i.e., it becomes available for new make connection commands). The CLLn can also be regarded as the second cycle of a break connection command. CLLn is valuable if several outputs are driven from a common input (broadcast) and the user wishes to break one of the output connections, but leave the others intact. When the physical location in the CAM is identified, either by software tracking or by use of the find entry command (later in this section), then the CLLn can be issued. If the user wishes to poll the CAM for its contents, then the RDCn or read CAM (upper/lower) command can be used to query a particular location (AMR bit 5: when 1, equals 0—255, when 0, equals 256—511 [T8102, T8105 only]) in a specific block using the LAR for the location address. The contents of the CAM and tag location are transferred to the holding registers, and then the time slot, stream plus control, and tag are returned (in sequence) from four consecutive IDR reads (see Section 3.4.2 Setting Up H-Bus Connec- tions on page 75 for more details). The MSB of the time slot is the validity bit. The actual RDCn operation is one-cycle. The converse of the RDCn is the FENn, or find entry command. It can be thought of as the first cycle of a BKCn command. Only time slot and stream plus con- trol bits are necessary for identifying the location. The tag is not needed. The values returned (in sequence) from two consecutive IDR reads (T8102, T8105 only) or just one read (T8100A) (see Section 3.4.2 Setting Up H-Bus Connections on page 75 for more details) to the IDR is the physical location of the entry in the CAM block, bits [7:0] then bit 8, if it is found. If the entry is not found, then the underflow error bit in the SYSERR reg- ister will be set. FENn is a one-cycle command. RSCn is the reset CAM command, and this renders all locations in one CAM block invalid. This can be consid- ered a CLLn for all locations in the CAM. Two special resets are the RCH command, which resets only the holding registers, and the CI command, which resets all three CAM blocks and the holding registers. All resets are one-cycle.

2.3.3 H-Bus Access

There are 32 bidirectional pins available for accessing the H-bus. The direction of the pins is selected by the CAM read and write bits. Data rates for the pins are selected in accordance with the H.100/H.110 specifica- tions. Unassigned time slots on the H-bus are 3-stated. Details about rate selection are provided below. T wo bits of the 13-bit address are used to select the CAM block as indicated in Figure 9. The remaining 11 bits plus a read/write bit form a comparand that is stored in a CAM location.

2.3.4 L-Bus Access

and time slot, the H-bus data memory will provide the actual data, not the local connection.

2.3.5 H-Bus Rate Selection and Connection Address Format

SGb programs streams 4—7, and SGa programs streams 0—3. Table 43. HSL: H-Bus Stream Control, Low Byte, 0x10 6 H-Bus Group D Rate Select, LSB. SGc 5 H-Bus Group C Rate Select, MSB. Programs streams 8—11. 4 H-Bus Group C Rate Select, LSB. SGb 3 H-Bus Group B Rate Select, MSB. Programs streams 4—7. 2 H-Bus Group B Rate Select, LSB. SGa 1 H-Bus Group A Rate Select, MSB. Programs streams 0—3. 0 H-Bus Group A Rate Select, LSB.

2.3.5 H-Bus Rate Selection and Connection Address Format (continued)

Table 44. HSH: H-Bus Stream Control, High Byte, 0x11 ming examples for setting up connections can be found in Section 3.3 Basic Connections. 6 H-Bus Group H Rate Select, LSB. SGg 5 H-Bus Group G Rate Select, MSB. Programs streams 24—27. 4 H-Bus Group G Rate Select, LSB. SGf 3 H-Bus Group F Rate Select, MSB. Programs streams 20—23. 2 H-Bus Group F Rate Select, LSB. SGe 1 H-Bus Group E Rate Select, MSB. Programs streams 16—19. 0 H-Bus Group E Rate Select, LSB.

2.4 Subrate Switching for the Ambassador

2.4.1 Description, Operation, and Application

in 2.4.7 Example of a Practical Application on page 43.

2.4.2 Definitions

propagated at the same data rate, namely 64 kbits/s. has increased by a factor of 8. data, the byte is fully packed or densely packed. packed bytes. Any portion of a byte may be used. An example is shown in Figure 12. Figure 12. Subrate Switching Example OUTPUT DURING TIME SLOT n + 5.

4040 Lucent Technologies Inc.

2.4.4 Using the Existing Architecture

will continue to track stream and time-slot addresses. the H.100/H.110 bus as described previously. Table 45. Permitted Tag Extensions addressed by the tag extensions.

2.4 Subrate Switching for the Ambassador Family (continued)

2.4.4 Using the Existing Architecture (continued)

Figure 13 illustrates the changes to the architecture of the Ambassador family. (and will only handle) four IDR reads for an RDC command. Figure 13. Modifications for Subrate Switching

4242 Lucent Technologies Inc.

2.4.5 Limitations

rate piece can be switched to the appropriate output. switching fabric (see Figure 14).

4 TIME SLOTS

1 TIME SLOT

framing for subrate connections. Figure 15. Constant Delay/Minimum Delay Example

2.4.7 Example of a Practical Application

through the voice channels with minimum latency.

1. The ability to extract 1 or 2 bits from any time slot

presented separately to a host CPU.

1. The ability to inject a 1 or 2 bit stream into any
2. The bit positions to be extracted/injected must be

viously occupying those positions.

1. The ability to switch full time slots presented to it

while performing injection/extraction. ble as well, even within a single time slot.

2.5 Clocking Section

diagram of the devices clocking section. tal with a lesser tolerance can be used. pin, and XT ALOUT should be left unconnected. form to ±32 ppm in a bus master situation.

2.5 Clocking Section (continued)

• The path for XT ALIN divide-by-4 is for fallback only.

Figure 16. Clocking Section

4 MHz

2 MHz

65.536 MHz

16.384 MHz

2.048 MHz

4.096 MHz

8.192 MHz

Lucent Technologies Inc. 45 Advance Data Sheet November 1999 H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105 tion (continued)

2.5.1 Clock and NETREF Selection

Three selectors provide device input clocking. The clock selector and frame selector operate from a com- mon set of selection options in register CKM (see Sec- tion 2.5.8 Clock Control Register Definitions for register details), where FRAMEA is selected along with clock C8A and FRAMEB is selected along with clock C8B. T ypically, one of the local references (L_REF[0:7]) will be selected when the devices are operating as mas- ters, though the local oscillator is also available. As a slave, the most common selections will be one of the bus types. Each bus type has a state machine associ- ated with it for determining the frame sync. All clock inputs are sampled to check for proper switching. If the expected clock edge does not occur, and there is no switching on CT_NETREF for 125 µs, a bit correspond- ing to the errant clock is set in the CLKERR register (see Section 2.7 Error Registers for more details). NETREF can be created from one of the local refer- ences or from the oscillator independent of the clock generation.

2.5.2 Dividers and Rate Multipliers

The clock and NETREF selections are routed to divid- ers*. In the case of NETREF , the divider is usually used to reduce a bit rate clock to 8 kHz, so the most common divisors will be 1, 193 (1.544 MHz/8 kHz), and 256 (2.048 MHz/8 kHz), although a full range of values (from 1—256) is possi- ble. For the clock selector, the signal will most often be routed through the main divider when the devices are operating as masters or through the resource divider when operating as slaves. Both the main and resource dividers are fully programmable. The ultimate destination for the main or resource divider is intended to be PLL #1. PLL #1 accepts either a 2.048 MHz or 4.096 MHz input and will rate multiply up to 65.536 MHz. The divisor of the main or resource dividers is chosen in conjunction with the rate select of the PLL, i.e., a divisor which generates a 4.096 MHz output and a rate selection of x16, or a divisor which generates a 2.048 MHz output and a rate selection of x32. This provides a great deal of flexibility in adapting to a variety of (external) clock adapters and jitter atten- uators while acting as a master, as well as slaving to several bus types. A digital PLL that can rate multiply to either 2.048 MHz or 4.096 MHz from an 8 kHz source in the absence of an external clock adapter is also provided. PLL #1 can be bypassed for diagnostic purposes or if an external clock adapter is used that provides a high-speed output (65.536 MHz). The input to the DPLL is an 8 kHz sig- nal. A second rate multiplier is provided for supporting T1 applications. It is optimized around either a 1.544 MHz or 3.088 MHz input rate which multiplies to 24.704 MHz and is then divided down to provide 50% duty cycle clocks of 12.352 MHz, though the direct 24.704 MHz is available as well. A bypass is provided so that an exter- nal clock can be buffered through the TCLK output. The internal oscillator or the various outputs derived from PLL #1 can also be selected for the TCLK output.

2.5.3 State Machines

The purpose of the state machines is to generate internal control signals for the remainder of the circuitry and to provide all bus clocks when operating as a mas- ter. The state machines operate from the 65.536 MHz clock generated by PLL #1, and they are time refer- enced to the frame sync derived from the selected clock and frame inputs. As a master, the time sync is based on the device’s own generated frame. The dominant internal control signals are a noninverted 32.768 MHz clock, an inverted 16.384 MHz state clock, and a noninverted 122 ns wide sync pulse centered around the beginning of a frame. The memories are synchronized to the 65.536 MHz clock.

2.5.4 Frame Sync

Frame sync is not generated in absence of an external frame clock. The state machinces will randomly syn- chronize to the 65.536 MHz clock.

2.5.5 Bit Sliding (Frame Locking)

The devices generate frame signals based on the incoming clock and frame references and device gen- erated clock signals. When slaving, it is sometimes necessary to align the edges of this generated frame signal to the incoming frame reference. * If the A clocks have been selected as the clock source through the CKM register (described in Section 2.5.8 Clock Control Register Definitions), then the CT_C8A is the signal sent to the main and resource dividers; likewise, selecting B clocks results in sending CT_C8B; the MVIP selection sends /C4; the H-MVIP selection sends the recovered /C16 (derived from differential inputs); select- ing SC2 sends SCLKX2; and SC4/8 sends SCLK to the dividers.

4646 Lucent Technologies Inc. Advance Data Sheet November 1999H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105 tion (continued)

2.5.5 Bit Sliding (Frame Locking) (continued)

The devices generate frame signals based on the incoming clock and frame references and device gen- erated clock signals. When slaving, it is sometimes necessary to align the edges of this generated frame signal to the incoming frame reference. T o accomplish this, the devices will compare the referenced frames with the current state of its clock state machine, and if the difference exceeds one

65.536 MHz clock cycle, the entire stream will have a

fraction of a bit time removed from each frame; this is referred to as bit sliding. The process will repeat until the measurements fall within one clock cycle. The actual bit sliding will take place by reducing the gener- ated frame by one 65.536 MHz clock cycle at the beginning of the frame. This means that the frame edges will phase-align at the rate of approximately 15.26 ns per frame. The maximum phase difference is slightly less than one frame or 124.985 µs. Thus, it will require approximately 8000 frames, or 1 second, to phase-align the frame. This is mean time interval error (MTIE) complaint. The alternatives to bit sliding are snap alignment and no alignment. Snap alignment refers to an instanta- neous phase alignment, i.e., a reset at the frame boundary. This mode is common to other devices. If no alignment is chosen, the device’s generated frame is frequency-locked to the incoming frame sync, but not phase-aligned.

2.5.6 MTIE

MTIE is defined in A T&T technical reference TR62411. MTIE is a characteristic of wander. Wander is defined as clock phase deviations that are less than 10 Hz in frequency. MTIE defines the amplitude of the wander. The maximum amplitude, in the DS1/T1 world, is 1 µs (about 1.5 bit times). This is measured by sampling the delta of actual clock edges from the ideal positions over 2048 bit times (1.326 ms). The secondary requirement is that no two edges may deviate by more than 81 ns (1/8 bit time). Apply this to the essentially E1-like timing in the H.100/110/ MVIP /SC-Bus worlds: 1.5 bit times is about 750 ns 2048 samples is 1 ms 1/8 bit time is about 61 ns

2.5.6.1 MTIE Compliance

T810X is MTIE compliant; however, the user must pay attention to the system application. The T810X requires Stratum 4e clocks, which are already sup- posed to meet 32 ppm stability and 1 µs MTIE compli- ance, and will in turn remain Stratum 4e on the out- bound side. External trunks, T1 or E1, must be run through framers (and a jitter attenuator, if not present in the framer) to help ensure the input requirement. Given this, the T810X is compliant in that it will not introduce phase hits into the system which are uncontrolled, nei- ther as high frequency (jitter) nor as low frequency (wander). For a given clock, the T810X should respond in such a way that the wander does not perturb the outbound clocks greater than 61 ns per 2.048 MHz cycle, or more than a total of 750 ns over any 1 ms measuring period. These numbers are aided by the analog PLL. Any phase hit is smoothed to 800 ps/65 MHz clock cycle which is 25.6 ns/2.048 MHz clock cycle. Thus, the 61 ns/bit time is met. The 750 ns number is constrained by the input requirement. Given that the inbound side will be no greater than 750 ns over the 1 ms sampling period, the T810X's outbound clocks will show a maximum deviation in the 1 ms period on the order of 315 ns. In truth, framers, with accurate crystals, tend to absorb much of the wander in slip buffers, so this num- ber should be very small. While not a specific requirement of Stratum 4e, all T810X products do provide holdover capability. The T810X will respond, in a controlled fashion, to a change of clock source. Again, the measurement method for this uses the MTIE specification. The worst-case response will be a 25.6 ns shift of clock edge per

0.048 MHz clock cycle less than the MTIE specifica-

tion.

2.5.6.2 Relationship of the Bit Slider to MTIE

Strictly speaking, the bit slider is not related to MTIE in that MTIE makes no provision for frame wander. The bit slider itself however, will not introduce more than 15.26 ns/frame of additional shift, when enabled. The slider does not affect the PLL or the clocks on a con- stant basis, it simply walks the generated frame into alignment with the received frame. Thus, the stability of the clock edges remains constant in the long term, but individual edges may deviate by an additional amount, making the edge-to-edge absolute maximum 25.6 ns + 15.3 ns = 40.9 ns. The critical item to relating MTIE with the bit slider is that the bit slider won't make the T810X fail MTIE.

2.5.6.3 Using the Bit Slider

The bit slider is primarily intended for maintaining the local side of an application. Specifically, some DSPs have limited synchronizing ability and once they are phase-aligned with the frame, a loss of frame sync can be disruptive. The bit slider allows a change of source to gracefully realign to a new frame without tripping up the synchronization. There is limited benefit on the H.100 side—snap mode is equivalent to slide in terms of A/B clock fail-over, but the local side is much differ- ent.

2.5.6 MTIE (continued)

2.5.6.3 Using the Bit Slider (continued)

frame alignment with external trunks, instead of just frequency locking to external trunks.

2.5.7 Clock Fallback

Figure 17. A, B, and C Clock Fallback State Diagram

4848 Lucent Technologies Inc.

2.5.7 Clock Fallback (continued)

■ Fallback must be enabled in register CKS. the CKSEL bits in the CKM register. CLKERR3 registers (Section 2.7 Error Registers). device’s registers when a fallback condition is detected. isters when a fallback condition is detected.

1. Clear the CKW register to prevent any more clock errors.
2. Clear CKM bit 5 (CCD) to be a slave.
3. Clear CKP bits 2 and 3 to prevent sourcing a compatility clock.
4. Set CKM bit 5 (CCD) to be a master again.
5. Set CKP bits 2 and 3 to drive the appropriate A or B clocks.
6. Clear SYSERR and CLKERR bits via MCR.
7. Set the appropriate bits in CKW to enable watchdogs.

Figure 18. Programming Sequence

2.5.8 Clock Control Register Definitions

Table 46. CKM: Clocks, Main Clock Selection, 0x00 with an inversion selected from register CKP . A pictorial view of the various clocks is shown in Section 4.8.1 Clock Alignment. P AE 7 Phase Alignment Enable. P AE = 0, Retains frequency lock without phase alignment. P AE = 1, Enables phase alignment. P AS = 0, Phase alignment, snap. P AS = 1, Phase alignment, slide. CCD = 0, Slave, monitors compatibility signals. CCD = 1, Master, drives compatibility signals. CKSEL = 0000, Internal oscillator. if 0 then CT_NETREF1 is selected, if 1 CT_NETREF2). CKSEL = 0010, A clocks (C8A & FRAMEA); ECTF or MC-1. CKSEL = 0011, B clocks (C8B & FRAMEB); ECTF or MC-1. MVIP is selected, /C4 is selected as the clock reference for PLL #1. these bits select pairs of synchronized inputs.

2.5.8 Clock Control Register Definitions (continued)

Table 47. CKN: Clocks, NETREF Selections, 0x01 NR12EN 7—6 NR12EN enables the selection between NETREF1 and NETREF2. NR12EN = 01, Enable NETREF2 for output, route NETREF1 input to the L_SCs. NR12EN = 10, Enable NETREF1 for output, route NETREF2 input to the L_SCs. NDB = 1, NETREF selector goes directly to NETREF divider. NRI 4 NRI inverts the output of the NETREF selector. NRSEL = 0000, Internal oscillator divided by 8. NRSEL = 0001, Internal oscillator. NRSEL = 0010, Select NETREF1 as input. NRSEL = 0011, Select NETREF2 as input. NRSEL = 1000—1111, Local references 0—7.

Table 48. CKP: Clocks, Programmable Outputs, 0x02 PTS = 001, Oscillator, buffered output. PTS = 010, PLL #2, direct output . PTS = 011, PLL #2, output divided by 2. PTS = 100, 2.048 MHz from state machines. PTS = 101, 4.096 MHz from state machines. PTS = 110, 8.192 MHz from state machines. PTS = 111, 16.384 MHz from state machines. C8IS 4 C8IS = 0, MC-1 (A and B clocks inputs interpreted as /C4 with /FRAME). C8IS = 1, ECTF (A and B clocks inputs interpreted as C8 with /FRAME). CAE 3 CAE = 0, Disable CT_C8A & /CT_FRAMEA outputs. CBE 2 CBE = 0, Disable CT_C8B & /CT_FRAMEB outputs. C8C4 1 C8C4 = 0, Inverted 4.096 MHz (MC-1 output mode). C8C4 = 1, Noninverted 8.192 MHz (ECTF output mode). CFW 0 CFW = 0, Narrow (122 ns) /FR_COMP . CFW = 1, Wide (244 ns) /FR_COMP .

Table 49. CKR: Clocks, Resource Selection, 0x03 CRS 7—6 The CRS[7:6] bits are used to select the input to PLL #1. CRS = 00, External input (through the 4MHzIN pin). P1B 5 P1B and P1R control PLL #1. P1B = 0, Normal PLL #1 operation. P1R 4 P1R = 0, PLL #1 rate multiplier = 16. P1R = 1, PLL #1 rate multiplier = 32. P2B 3 P2B and P2R control PLL #2. P2B = 0, Normal PLL #2 operation. P2R 2 P2R = 0, PLL #2 rate multiplier = 8. P2R = 1, PLL #2 rate multiplier = 16. SCS 1—0 The SCS[1:0] bits are used to program the outgoing SC-Bus compatibility signals. SCS = 00, SC-Bus outputs 3-stated. SCS = 11, SCLK @ 8.192 MHz, SCLKX2 @ phase shifted 8.192 MHz.

Table 50. CKS: Clocks, Secondary (Fallback) Selection, 0x04 choose a new source for PLL #1. FRS = 00, External input (through the 4MHzIN pin). Note: The decode is the same as that of the CRS bits (in the clock resource register, CKR). FTS 5—4 FTS determines the basic fallback mode (see Section 2.5.8.1 Basic Fallback Mode). FTS = 01, This disables fallback. FTS = 10, This is one of the two major fallback selections. also be used as a software-initiated fallback. FF = 1, Force use of secondary (fallback) resources. FCSEL = 000, Internal oscillator divided by 4. FCSEL = 010, A clocks (C8A & FRAMEA); ECTF or MC-1. FCSEL = 011, B clocks (C8B & FRAMEB); ECTF or MC-1. FCSEL = 101—111, Selects local references 1—3.

5454 Lucent Technologies Inc. Advance Data Sheet November 1999H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105 tion (continued)

2.5.8.1 Basic Fallback Mode

Note: The fallback mechanism is sticky in that the device will not fallback again if the clocks which were used for fallback fail. The four modes are described below. FTS 00 The resource multiplexer is bypassed, thus selection of this mode of operation assumes that PLL #1 has been set up for a x16 multiply (in CKR). The PLL selection cannot be changed during fallback, so both primary and secondary choices must supply the same fre- quency into PLL #1. Thus, in the case of FTS = 00, it is assumed that the primary clock selec- tion has been set up for 4.096 MHz. FTS 01 The secondary selections will be ignored. The clock error registers will continue to report tran- sient and stuck errors (if unmasked by CKW), but will not induce the fallback sequence. There are three reasons to use this: as an aid in initializing the T8100, as a diagnostic tool, or in a software-only fallback system. This last item requires some additional explanation. There is a provision in the ECTF H.100 and H.110 specifications which provide for a piece of hardware to support both hardware and soft- ware based fallback. In the software-only selection, the part must still report clock fail- ures. This is accomplished through the CLK- ERR pin, which provides the interrupt to the host, and CLKERR1, CLKERR2, CLKERR3, and CKW, which provide the details of the fail- ures. An interrupt will thus trigger a software sequence which will reprogram the clocks. In the hardware based fallback, the selection is automatic with the intent of maintaining stable operation until the software can service the device. FTS 10 The choice to move into fallback is triggered by an error on the main (primary) clock selection, as defined by the lower 4 bits of CKM. The main clock selection will have as few as one signal associated with it (main clock selection = NETREF) or as many as five (main clock selection = H- MVIP, which is /C16+, /C16-, /C4, C2, and /FR_COMP). Thus, a failure on any clock in the main selection will induce fall- back. Note that these signals must be unmasked, as well. So in the case of NETREF above, the lowest bit of CKW must be set. In the case of H- MVIP, at least bits 3, 4, and 5 must be set in CKW. Any additional CKW bits which are set (but not required) will flag a failure on the CLKERR pin and will be set in the CLKERR registers but will not induce a fallback. Further, if fallback is initiated, the CLKERR and the SYSERR pins will go high. The fallback will occur to the selections made in the CKS register. One additional note: this does not apply to the local reference inputs (selections 1000—1111 in the lower 4 bits of CKM). Since these typically come from fram- ers or HDLC controllers, these devices have their own error reporting systems. FTS 11 This selection induces fallback on the failure of either the A or B clocks independent of the main clock selection. (A and B must be unmasked in CKW.) Since this is intended for H.100 and H.110, it would be unwise to pro- gram the main selection to be anything other than A clocks or B clocks. For H.100, the FTS = 11 selection also enables a state machine which controls the compatibility clocks. If bit 5 has been set in the primary clock programming and is also programmed to drive either the A or B clocks, then a self-detected failure will cause the T8100 to remove its clocks from the H.100 bus, both its main (A or B clock set) and the compatibility clocks. Likewise, if bit 5 was not set in the primary clock programming and if the part is slaving to one set (A or B) and driving the other (B or A, respectively) then a failure detected on the clock it is slaving to will auto- matically cause the device to drive the compat- ibility clocks. In this way, an H.100 system with an A and B clock set can maintain the opera- tion of compatibility clocks in addition to main- taining H.100 clocking.

2.5.8.1 Basic Fallback Mode (continued)

Table 51. CK32 and CK10: Clocks, Locals 3, 2, 1, and 0, 0x05 and 0x06 streams or as a secondary NETREF . These are programmed using CK32 and CK10, which are presented below. CK32 LSC3 7—4 LSCn = 0000, Output low. LSCn = 0001, Local frame (positive pulse). LSCn = 0010, NETREF (Sec8K). LSCn = 1001, Local frame, inverted. LSCn = 1010, NETREF , inverted (negative pulse). LSCn = 1100, 2.048 MHz, inverted. LSCn = 1101, 4.096 MHz, inverted. LSCn = 1110, 8.192 MHz, inverted. 128, and 256, output is 50% duty cycle. shorter than high-level duration). whose width is one full clock period. and 128, output is 50% duty cycle. second half of the divider clock period. the binary equivalent of 192, which is 0xC0.

2.5.8.2 CKMD, CKND, CKRD: Clocks, Main, NETREF, Resource Dividers, 0x07, 0x08, and 0x09 (continued)

and use of the bit(s) for a particular feature is described in the section which pertains to the feature. Table 52. CON Register 0x0E GPDENB 6 0: Disables the GPD register. 1: Enables the GPD register. NETSEL 5 0: Select NETREF_1. LREFENB 4 0: LREF’s are 8 unsynchronized inputs. 1: LREF’s are 4 pairs of synchronized inputs. LREFIFS 3 0: LREF frame strobe is not inverted. 1: LREF frame strobe is inverted. LREFIBC 2 0: LREF bit clock is not inverted. 1: LREF bit clock is inverted. CED 1 0: Individual FME bits are used for all transfers. 1: Value of GFME (CON register bit 0) is used for all transfers. GFME 0 0: Only reverse connections provide constant delay. 1: Only forward connections provide constant delay.

2.5.9 LREF Pairing

The Ambassador devices have a feature which is programmable by software called LREF pairing (a pair of pins). LREF bit clock is routed to the dividers and finally to the analog PLL.

2.5.9.1 LREF Port Configuration

control bit, the CON register has 2 additional control bits for inverting the frame strobe and bit clock. Table 53. LREF Pairs Table 54. CKM (0x00) CKSEL Values to Select LREF Pairs to select one of the LREF pairs as the input.

1. If the CKSEL value is LREF4—LREF7 (0x1100—0x1111) as the input source, LREF pairing will not function.
2. CKSEL must be programmed to select LREF0—LREF3 in order to have LREF pairing.
3. Each LREF pair must be phase-locked together. Otherwise, the device timing will function incorrectly, causing unpredictable results.

sets LREF4 as frame sync input. sets LREF5 as frame sync input. sets LREF6 as frame sync input. sets LREF7 as frame sync input.

5858 Lucent Technologies Inc. Advance Data Sheet November 1999H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105 tion (continued)

2.5.9 LREF Pairing (continued)

2.5.9.2 Operation

If LREF pairing is enabled and CKM has a CKSEL value of 0x1000 to 0x1011, then the corresponding internal frame event is sent to the main clock genera- tion circuit in order for the internally generated clocks to synchronize to the frame event. The T8100A, T8102, and T8105 only synchronize to the frame inputs on LREF[7:4]. The frame input on LREF[7:4] becomes the internal frame synchronization signal. Also, since the devices will derive their timing from the bit clock input on LREF[3:0], the divider(s) and CKR must be pro- grammed. The inverting bit in the CON register, bit 2, causes the bit clock to be inverted. This allows the sampling of the frame (LREF[7:4]) to occur on either the rising or falling edge of the bit clock input on LREF[3:0]. The inverting bit in the CON register, bit 3, causes the frame clock to be inverted. This allows the internal clock generator to synchronize to either a rising or falling transition of the frame input on LREF[7:4]. The divider registers must be set up for the correct divide factor. The register that is programmed depends on which path is chosen. If the LREF bit clock is, for example, 8.192 MHz and it is not going to be sent to the PRIREFOUT for external jitter attenuation, then the resource divider would be programmed. A value of 0x03 gives a divide by 4, and the input to the analog PLL is 2.048 MHz. The CKR register also has to be programmed for the correct PLL multiplier. Another fea- ture of LREF pairing is that the bit clock does not have to be 8.192 MHz. For example, a 1.544 MHz clock can be input, sent to PRIREFOUT , and converted to a

2.048 MHz clock, which is then input on the 4MHzIN

pin.

2.5.9.3 Example of LREF Pairing on a T8100A

■ The T8100A PCI card has a framer on it and two phase-locked clock outputs: — An 8 kHz frame clock going to LREF4. — An 8.192 MHz bit clock going to LREF0. ■ The CON register is programmed for LREF pairing: LREFENB bit 4 = 1. ■ The frame strobe and the bit clock are not inverted, so LREFIFS bit 3 = 0 and LREFIBC bit 2 = 0. ■ The CKM register is programmed to be a master with phase and snap alignment, and CKSEL[3:0] is set for LREF0. The value of CKM is, therefore, 0xA8. ■ CKR is programmed to 0x50, which sets the PLL multiplier to 32. ■ The resource divider, CKRD, is programmed to 0x03, which divides the 8.192 MHz clock by 4. ■ The T8100A derives its memory and state machine clocks from the 8.192 MHz input on LREF0. ■ The frame synchronization clock will be input to the state machines, and the T8100A will phase lock to the framer's 8 kHz clock that is input on LREF4.

2.5.9.4 Advantages of LREF Pairing

LREF pairing provides the user of the T8100A, T8102, or T8105 with another option for selecting a pair of clocks from which to derive internal timing. With the use of the CON register, the user has a very flexible arrangement regarding the orientation of the LREF pair that can be input to the T8100A, T8102, or T8105.

2.6 Interface Section

2.6.1 Microprocessor Interface

The grouping of the read, write, chip select, and address latch enable signals, along with the data bus and the address bus, permit access to the devices using Intel nonmultiplexed interface (ALE = low), Motor- ola nonmultiplexed interface (ALE = high), or Intel multi- plexed interface (ALE = active). ALE controls the microprocessor mode. All control and status registers and data and connection memory accesses are con- trolled through this interface. All accesses are indirect, following the pin descriptions in T able 1 and Table 2. Programming examples and a more detailed discus- sion of the indirect accesses can be found in Section 3 Using the TSI Devices.

2.6.2 General-Purpose Register

A simple, general-purpose I/O register is available. The GPR has eight dedicated pins. The GPR corresponds with I/O pins GP[0:7]. GP6 and GP7 are unavailable if bit 5 of register CKN is low (see Section 2.5.8 Clock Control Register Definitions). The GPD register (0x17) is a write-only register. It sets the direction bit in the GPR register (0x18). T o verify what is written to the GPD register, the GPR register has to be read and the direction bits checked. If a bit in the GPD is zero, the corresponding bit in the GPR is set to one and the pin is configured as an input. If a bit in the GPD is a one, then the corresponding bit in the GPR is zero and the pin is configured as an output. Also, bit 6 in the CON register (0x0E) must be set to one to enable writing of the GPD register. Since the GPD is a write-only register, software will have to keep track of the current GPR settings, which reflect what is in the GPD.

2.6 Interface Section (continued)

2.6.3 Framing Groups

first frame pulse can be positioned anywhere within the frame: therefore, simply defining the start of a virtual frame. pulse from the frame boundary. Table 55. FRHA, Frame Group A High Address and Control, 0x21 Table 56. FRHB, Frame Group B High Address and Control, 0x23 Rate 7—6 Rate = 00, Frame group disabled, 3-state. T ype 5—4 T ype = 00, Bit-wide pulse. T ype = 01, Double bit-wide pulse. T ype = 10, Byte-wide pulse. T ype = 11, Double byte-wide pulse. FAI 3 FAI = 0, Normal pulse. Hi Start 2—0 Hi Start = Upper 3 bits of group start address or programmed output. Rate 7—6 Rate = 00, Frame group disabled, 3-state. T ype 5—4 T ype = 00, Bit-wide pulse. T ype = 01, Double bit-wide pulse. T ype = 10, Byte-wide pulse. T ype = 11, Double byte-wide pulse. FAI 3 FAI = 0, Normal pulse. Hi Start 2—0 Hi Start = Upper 3 bits of group start address.

6060 Lucent Technologies Inc. Advance Data Sheet November 1999H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105 tion (continued)

2.6.3 Framing Groups (continued)

There are two groups of frame pulses. Each frame group consists of 12 output pins, which are enabled sequentially after a programmed starting point. The 12 outputs of the frame group are pulsed in sequence, once every 8 bit times, where the bit time is set by the rate option. The groups are denoted group A and group B. This section describes framing group A. Framing group B is made up of similar registers. A pair of regis- ters controls each group. Two registers, FRLA and FRHA, control the spacing of the 12 frame pulses (rate), their pulse width, polarity, and the offset of the first pulse from the frame boundary. The FRPL and FRPH registers are also used in configuring the frame groups; however, for this discussion they are equal to zero. With FRPL and FRPH equal to zero, the frame group A bits [0:11] are output on pins FGA[0:11] and frame group B bits are routed to group B output pins FGB[0:11]. FRHA has 5 control bits and 3 upper offset bits. FRLA has 8 bits for the lower part of the offset. Thus, the offset is 11 bits. The 11-bit offset corre- sponds to 2 11 values which allow programming offsets from 0 ns to 125 µs. Note that the resolution is less than 1 data bit. For example, if the frame group clock is programmed to 2.048 MHz, the resolution is 0.125 (one eighth) of a data bit.

2.6.3.1 Frame Group Timing

The frame boundary is the point where /CT_FRAME is low and CT_C8 is starting its low-to-high transition. The offset sets the first output (pin FGA0) relative to the frame boundary. With a zero offset, the rising edge of the first frame group is coincident with the first falling edge of the 8.192 MHz clock, output at the LS_C[3:0] port, after the start of the frame boundary. Referring to Figure 28, the rising edges of the 8.192 MHz, 4.096 MHz, and 2.048 MHz clocks are all coincident and occur in the center of CT_FRAME (not shown in Figure 28). This is the start of the following: ■ Physical frame. ■ The first data bit of the first time slot on the CT bus and the local bus. Because of the complexity of the device and other design considerations, with a frame group offset of zero, the first frame pulse starts after 1 bit clock (1/16.384 MHz) with respect to the start of the frame boundary. T o have the frame group start at the frame boundary, the 11-bit offset is all ones (0x7FF). That is, FRLA is 0xFF and the lower 3 bits (bits [2:0]) of FRHA are 1. The 11-bit offset allows the user to position the starting frame pulse anywhere within the 125 ms frame. The frame pulse can be adjusted in increments of 61 ns (1/16.384 MHz). The control bits in the FRHA register enable the user to invert the frame group pulse and to adjust the width of these pulses. In addition to sequenced pulses, the frame groups can be used as simple programmed output registers. When group A is used as a programmed output, the bits are sent from the FRLA [0x20] and FRHA [0x21] registers. Bits [0:7] of the programmed output come from bits [0:7] of FRLA [0x20]. Bits [8:10] of the programmed output come from the high start (bits [0:2]) of FRHA [0x21], and bit 11 of the programmed output comes from the FAI bit (bit 3) of FRHA [0x21]. When group B is used as a programmed output, bits 0:7 of the output come from bits 0:7 of separate register FRPL [0x24], and bits [8:11] of the output come from bits 0:3 of another register FRPH [0x25]. The upper nibble of FRPH [0x25] also has output routing functions associ- ated with it. Register FRPH [0x25] is illustrated in T able 57; see Figure 19 for a diagram of the selection options.

2.6.3.1 Frame Group Timing (continued)

Table 57. FRPH: Frame Group B, Programmed Output, High, 0x25 Figure 19. Frame Group Output Options FAO 7—6 FAO = 00, Frame group A bits FGA[0:11] on output pins FGA[0:11]. FAO = 01, Programmed output A bits FGA[0:11] on output pins FGA[0:11]. FGA[0:5] on output pins FGA[6:11]. group B bits FGA[0:5] on output pins FGA[6:11]. FBO 4 FBO = 0, Frame group B routed to group B output pins. FBO = 1, Programmed output B routed to group B output pins. Hi Prog 3—0 Hi Prog = Upper 4 bits of programmed output B. mode. Type bits have no effect in the programmed modes.

6262 Lucent Technologies Inc.

2.7 Error Registers

and CKS should be programmed last. whether the failure is permanent or transient in nature. are monitored for a loss of signal at 1 MHz. because the counter would have been reset. NRT should not be used to monitor for a clock failure. Table 58. CLKERR1 and CLKERR2: Error Indicator and Current Status, 0x28 and 0x29 T able 58 describes both CLKERR1 and CLKERR2. 7 CA => Reports failures on CT_C8A or /CT_FRAMEA. 6 CB => Reports failures on CT_C8B or /CT_FRAMEB. 5 CF => Reports failures on /FR_COMP . 4 C16 => Reports failures on /C16+ or /C16–. 3 C42 => Reports failures on /C4 or C2. 2 SC => Reports failures on SCLK.

1 SC2 => Reports failures on

0 NR => Reports failures on CT_NETREF1 or CT_NETREF2. 8 kHz only.

2.7 Error Registers (continued)

functions as the mask bit for CT_NETREF2 errors. reset their respective registers. Table 59. CLKERR3: Error Indicator and Current Status, 0x2C Note: Bits [7:4] are read only, bits [3:0] are read/write. Table 60. SYSERR: System Error Register, 0x2A in the CLKERR1 and CLKERR2 registers but will not set the FBE flag in SYSERR. RES 7—6 Reserved bit position. Read only. N2E => Reports failures on CT_NETREF2. N1E => Reports failures on CT_NETREF1. RES 3—1 Reserved bit position. Read/write. N2N = 0, Disable error reporting on NETREF2. N2N = 1, Enable error reporting on NETREF2. CUE 7 CUE => Even CAM underflow, set by an unmatched comparison. CUO 6 CUO => Odd CAM underflow, set by an unmatched comparison. CUL 5 CUL => Local CAM underflow, set by an unmatched comparison. COE 4 COE => Even CAM overflow, set by a write to a full CAM. COO 3 COO => Odd CAM overflow, set by a write to a full CAM. COL 2 COL => Local CAM overflow, set by a write to a full CAM. RES 1 RES => Reserved bit position. back operations are in effect*.

2.8 The JTAG Test Access Port

2.8.1 Overview of the JTAG Architecture

active-low signal that resets the circuit. value sampled on the rising edge of TCK controls the state transitions. The state diagram underlying the T AP controller is shown below. cal structure, and its different cell types is given in T able 62. nontargeted devices in board environments as defined by the standard.

2.8.2 Overview of the JTAG Instructions

The JT AG block supports the public instructions as shown in the table below. Table 61. JTAG Instruction Set

2.8 The JTAG Test Access Port (continued)

2.8.3 Elements of JTAG Logic

and keeping it low throughout the test. Table 62. JTAG Scan Register

• Verilog is registered trademark of Cadence Design Systems, Inc.

66 I CK_3MHZIN 121—132 O FGA[11:0]

67 O SYSERR 64 CC Controls cells 121—132

68 O CLKERR 133 Bdir C16N_MINUSA

0 CC Controls cells 67:68 134 Bdir C16N_PLUSA

1 CC Controls cells 69:76 136 Bdir C2

77 I RESTN 5 CC Controls cells 133—136

78 O RDY 137 Bdir SCLKX2NA

79 I WRN 7 CC Controls cell 137

80 I RDN 138 Bdir SCLKA

81 I CSN 6 CC Controls cell 138

82 I ALE 139 Bdir CT_C8_BA

83 I A0 140 Bdir CT_FRAME_BNA

84 I A1 3 CC Controls cells 139—140

44 CC Controls cells 85:88 4 CC Controls cell 141

97 I CK_4MHZIN 8 CC Controls cell 142

98 O PRIREFOUT 143 Bdir CT_C8_AA

45 CC Controls cell 98 144 Bdir CT_FRAME_ANA

99 O TESTOUT1 2 CC Controls cells 143—144

100 O REFCLK1O 145—176 Bdir CT_D[0:31]

46 CC Controls cells 99, 100 9—40 CC Controls cells 145—176

101 Bdir FROMDJA T 177—192 O LDO[0:15]

43 CC Controls cell 101 47—62 CC Controls cells 177—192

102 Bdir TODJA T 193 O XCS

42 CC Controls cell 102 0 CC Controls cell 193

41 CC Controls cells 103—108 210 O TCLKOUT

63 CC Controls cells 109—120

6666 Lucent Technologies Inc. Advance Data Sheet November 1999H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105 tion (continued)

2.9 Testing and Diagnostics

The devices have several testing operations: ■ JTAG ■ Forced output testing ■ Onboard diagnostics During manufacturing, the devices are run through standard functional and electrical testing.

2.9.1 Testing Operations

JTAG is used primarily to test the array portion of the devices. It will not provide coverage for the CAMs, reg- ister files, SRAMs, or PLLs. In JT AG, the manufacturer provides a drop-in control block and scan-chain which ties internal points to registers on the periphery of the devices, which are, in turn, tied to the I/O pins. Serial bit patterns are shifted into the devices through the TDI pin, and the results can be observed at the I/O and at a corresponding JTAG serial output, TDO. Since this JTAG conforms to the JT AG standard, the TDI and TDO can be linked to the JT AGs of other devices for sys- temic testing. The TTS pin must be low for JT AG opera- tions to work. The TTS pin has an internal pull-down resistor that defaults the devices to JT AG operations. In forced output testing, the outputs are set to a particu- lar state to measure their dc parameters. This can also be used in applications for board-level diagnostics. Forced output testing is selected by setting the TTS (test type select) pin high. In this mode, the JT AG clock pin, TCLK, will act as an input pin. All outputs will be enabled, and each output provides either an inverting or normal response to the input pin. Adjacent pins alternate inverting and normal function (i.e., a checker- board pattern).

2.9.2 Diagnostics

The devices have onboard diagnostic modes for testing the frame groups, SRAMs and CAMs, and some inter- nal structures. These are intended for testing some of the devices’ resources while in an application environ- ment (rather than a manufacturing test environment). The diagnostics allow critical internal nodes to be out- put through the frame groups, or to have the frame groups operated in special cyclical manner, or to pro- vide automatic filling of all memories (including CAMs) with one of four selected patterns. The diagnostics are activated and selected using three registers: DIAG1 [0x30], DIAG2 [0x31], or DIAG3 [0x32]. DIAG1 is used to select the frame group pins as either monitors for internal nodes or normal operation (i.e., as frame groups or programmed outputs). DIAG1 is also used to control the memory fill diagnostic. DIAG2 and DIAG3 modify the normal operation of the frame groups and the main state counter. Normally, the frame groups begin their cascade sequence when the state counter (i.e., the frame-synchronized master counter of the devices) reaches a value equal to the frame group’s starting address. DIAG2 and DIAG3 allow the state counter to be modified for one of two dif- ferent tests. When using the diagnostics in the pattern fill modes, refer to Appendix C.

2.9 Testing and Diagnostics (continued)

2.9.2 Diagnostics (continued)

Table 63. DIAG1: Diagnostics Register 1, 0x30 DFA = 01, State counter bits [10:0] routed to frame group pins [10:0], pin 11 = L. 4 MHz read, 4 MHz write, 2 MHz read, and 2 MHz write. DFB = 01, State counter bits [10:0] routed to frame group pins [10:0], pin 11 = L. local connection memory (T8100A, T8105 only) address routed to pins [9:0]. DFB = 11, Pin 11 gets local CAM hit flag, and pins [10:0] get CAM state counter. DMF = 1, Fill all memories with the pattern selected by DMP . DMP = 00, Checkerboard 0—even locations get 0x55, odd locations get 0xAA. DMP = 01, Checkerboard 1—even locations get 0xAA, odd locations get 0x55. DMP = 11, Data locations equal inverted address bits [7:0]. tion remains until the user clears this bit.

Table 64. DIAG2: Diagnostics Register 2, 0x31 Table 65. DIAG3: Diagnostics Register 3, 0x32 waiting for a frame signal to synchronize the start. cycle as a modulo-n counter where the n value is determined by (DSH and DSL). DSL 7—0 State counter bits [7:0].

Lucent Technologies Inc. 69 Advance Data Sheet November 1999 H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105

3 Using the TSI Devices

3.1 Resets

3.1.1 Hardware Reset

A hardware reset utilizes the (active-low) RESET pin. On activation, it immediately places all outputs into 3-state. Individual output sections must be re-enabled by setting the appropriate bits high in the MCR register. Internally, the local memory (T8100A, T8105 only) is in an undefined state, all CAM empty bits are set, all state machines are reset, and all registers are cleared to zero.

3.1.2 Software Reset

This is accomplished by setting the MSB of the master control and status register (see Section 2.1.2 Master Control and Status Register). The local and H-bus con- nections are rendered invalid, all registers are cleared except MCR, CLKERR1, CLKERR2, CLKERR3, and SYSERR (these registers are cleared with separate MCR control bits); the state machines are also reset. Writing the value 0xE0 to the MCR is a full software reset. Writing 0x0E enables all pin groups (though indi- vidual pins still require setup). This soft reset is clocked by the crystal.

3.1.3 Power-On Reset

No power-on reset is available. It is expected that the host microprocessor or applications board will provide an external control to the RESET pin for performing a hardware reset. The PLLs must not be enabled prior to establishing a stable supply voltage. There are two methods to accomplish this: ■ Tie the En1 and En2 pins to the same line that drives the RESET , which forces the PLLs into an off condi- tion while the devices reset asynchronously. ■ Add external capacitors from En1 to ground and from En2 to ground. (The values of the capacitors should be 1 µF or greater.) The capacitors will form RC cir- cuits with the En1 and En2 internal pull-ups and will charge up to enable the PLLs after several millisec- onds. The RC circuit affects the power-on reset for the PLLs. The long rise time provides some delay.

3 Using the TSI Devices (continued)

3.2 Device Settings

3.2.1 Architecture

Table 66. Device Identification Register, 0xFE Version device identification always identifies the physical device type. Table 67. GMODE: Global Mode Register, 0xFF (bits returned on readback reflect what the user should have them set to for the various modes), bit 4 is reserved. ME[2:1] 7—6 Read/write. Only the T8105 can be written to emulate either a T8102 or a T8100A. T8102, 512 connections (no local connections). T8100A, converts 512 connections to 256 connections. RES 4 Reserved bit position. Read/write.

3.3 Basic Connections

3.3 V (since the device’s nominal V

PLLs. PLL connections are shown in Figure 20.

3.3.1 LPUE Control Pins

default is pull-ups enabled. ups are re-enabled with backside power turning on. Table 68. LPUE Control Pins Figure 20. External Connection to PLLs even if only data lines 16—31 are used. CompactPCI Hot Swap specification.

24 RESET 65 T oDJA T

26 WR 66— 71 GP[5:0]

27 RD 192— 185 LDI[7:0]

28 CS 201— 194 LDI[15:8]

7272 Lucent Technologies Inc.

3.3 Basic Connections (continued)

left floating, since they could oscillate. nal components are required to meet specifications. CT_C8A, CT_FRAMEA, CT_C8B, and CT_FRAMEB. resistor and, in addition, a 10 kΩ pull-down resistor. ically go to the microprocessor.

3.3.6 PC Board BGA Considerations

• Switched low for insertion/removal.

Figure 21. Physical Connections for H.110

3.4.1 Setting Up Local Connections (T8100A, T8105

be made to the address in the connection memory. 7 bits comprising time slot). and CKW registers should be programmed last. Table 69. Time-Slot Bit Decoding

2 Mbits/s

4 Mbits/s

8 Mbits/s

3.4 Using the LAR, AMR, and IDR for Connections (continued)

3.4.1 Setting Up Local Connections (T8100A, T8105 Only) (continued)

Table 70. IDR: Indirect Data Register, Local Connections Only The second transfer requires that data in the IDR be defined as follows. of the registers and memory contents. slot which corresponds to the connection memory location. Figure 22. Local-to-Local Connection Programming (T8100A, T8105 Only) and stream LSB) is routed to the time slot instead of data. CHE 4 Enables the time-slot connection; a low in this bit forces 3-state during the time slot. Address 3—0 All 4 bits are used for the stream address of the desired data memory location.

3.4.2 Setting Up H-Bus Connections

Table 71. IDR: Indirect Data Register, H-Bus Connections Only block address is carried in the AMR, this reduces the number of bits that are necessary to establish a connection. the control field contains only 3 control bits. that the IDR be loaded with the same command value as the AMR rather than a don’t care or dummy value. are required. The tag is unnecessary for identifying a connection. disabled, only three transfers are required and the T8100A follows the same programming model as the T8100. retrieve the 8-bit physical address for the T8100A. Address 4—0 All 5 bits are used for the stream address of the desired data memory location.

3.4.2 Setting Up H-Bus Connections (continued)

Figure 23 illustrates how a CAM connection is made from the perspective of registers and the memory locations. point to the same location in the H-bus data memory. local and H-bus-to-local switching examples from Figure 22 and Figure 23 are reused in code examples #2 and #3. The connections are referred to in stream, time-slot format. Figure 23. CAM Programming, H-Bus-to-Local Connection

Figure 23. CAM Programming, H-Bus-to-Local Connection (continued)

78 Lucent Technologies Inc. Advance Data Sheet November 1999H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105

3.4.3 Programming Examples

;All programming examples included are in a pseudoassembler format. ;The basic commands used are the “move direct” and “move indirect.” ;A move direct command is indicated by the letters “MD” followed by ;the register name, then the data. Similarly, a move indirect command ;is indicated by the letters “MI” followed by the register name, then by ;data or another register reference (the register may not be indirect). ;The semicolon delineates comments. Direct data is followed by the ;letter “h” for Hex and “b” for binary. ;*****EXAMPLE #1 - Set Up Clocks, Local Bus, H-Bus, and Framers MD,AMR,00h ;Define control space ;all specific register names are equivalent ;to the LAR addresses (from Table 11) ;Main Clock Register MD,IDR,0C2h ;Load IDR with values for bit slider on, slave mode, ;and synced to ECTF Bus A Clocks MI,CKM,IDR ;The data in IDR is moved into CKM via the LAR register. ;NETREF Registers MD,IDR,88h ;Set up NETREF from Local Reference 0, 2.048 MHz bit clock in, divided value ;value out (i.e., 8 kHz), enable the DJAT connections MI,CKN,IDR ;Move the data to CKN MD,IDR,0FFh ;Set up NETREF divider with divide-by-256 MI,CKND,IDR ;Move the data to CKND ;Programmable Clocks MD,IDR,26h ;This selects the oscillator for the TCLKOUT, A Clock outputs off, and ;driving ECTF B Clocks MI,CKP,IDR ;Move the data ;**Clock Resources MD,IDR,40h ;Synced to bus so select Resource divider, x16 on PLL #1 & x8 PLL #2, SC Clocks off MI,CKR,IDR ;Make it so MD,IDR,01h ;Set up Resource divider with divide-by-2 for 4 MHz signal into PLL #1 MI,CKRD,IDR ;Move the data to divider

Lucent Technologies Inc. 79 Advance Data Sheet November 1999 H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105

3.4.3 Programming Examples (continued)

;Secondary Controls (Fallback) MD,IDR,35h ;Enable ECTF Fallback: Become the new A Clock master on A Clock failure, ;synchronizes to a bit clock on local reference 1, but requires the main divider ;with external input (assumes a CLAD is between the divider and 4MHzIn). MI,CKS,IDR ;Move the data to CKS MD,IDR,0FFh ;Set up Main divider with divide-by-256 MI,CKMD,IDR ;Move the data to divider ;Local Clocks MD,IDR,0E4h ;Local Selected Clock 3 gets inverted 8.192 MHz, LSC2 gets MI,CK32,IDR ;Move it to CK32 MD,IDR,80h ;LSC1 is high & LSC0 is low MI,CK10,IDR ;Move it to CK10 MD,IDR,30h ;8 Streams at 8 Mbits/s MI,LBS,IDR ;Define input streams per IDR MD,IDR,0AAh ;Define H-Bus Streams 0 - 15 for 4 Mbits/s MI,HSL,IDR ;Do it MD,IDR,0FFh ;Define H-Bus Streams 16-31 for 8 Mbits/s MI,HSH,IDR ;Engage MD,IDR,00h ;This sequence sets up Group A MI,FRLA,IDR ; to start coincident MI,FRLB,IDR ; with the Frame MI,FRPH,IDR ; boundary and Group B MD,IDR,0F0h ; to start halfway through MI,FRHA,IDR ; the Frame. The Groups MD,IDR,0F4h ; operate in normal framing mode MI,FRHB,IDR ; at 8 Mbits/s and are Double Byte wide. ;Note: FRPH sets up the correct routing. ;*******Connect the devices to the outside world MD,MCR,0Eh ; Enable H-Bus Streams & Clock, Local Streams, local ; Clocks including Framers

80 Lucent Technologies Inc. Advance Data Sheet November 1999H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105 ;*****EXAMPLE #2 - Setting up Local Connections (T8100A, T8105 only) ; Use 8 Mbits/s rate set up from Example #1... ; Send data FROM Stream/Time Slot 14, 7 TO Stream/Time Slot 3, 29. ; To transfer data the local input 14, 7 to the local ; output 3, 29 the following programming steps are required. MD,LAR,1Dh ;Set up lower address, i.e., Time Slot 29 MD,AMR,43h ; Set up upper address bits (Stream 3), and point to the ; the Time Slot field of the connection memory MI,IDR,07h ;Put a “7” in the Time Slot field of connection location 3,29 ;Syntactically, “MI,IDR,data” is a special case since IDR is not the final recipient of the data MD,AMR,53h ;Maintain the same upper address, but get ready to load the ; remaining connection info (upper bits + control) MI,IDR,0001_1110b ;This decodes as follows: XCS bit low, pattern mode off ; (not set), frame bit low, time slot enabled, and stream = 1110b (14) ;*****EXAMPLE #3 - Setting up H-Bus Connections, No Subrate ; Use rate set up from Example #1... ; Send data from Stream 14/Time Slot 7 of the H.100 bus to Stream 3/Time Slot 29 ; on the Local side. The data is coming in at 4 Mbits/s from E-CAM, and is sent ; out at 8 Mbits/s to through L-CAM. We’re using Data Memory location 49 to hold ; the actual data. LAR is not used for the CAM connection setups; it is used for ; reading specific CAM locations or writing and reading the associated Data ; Memory Locations. MD,AMR,0B0h ;Point to the Time-Slot holding register MI,IDR,07h ;This is the Time-Slot value (7) for the H-Bus address MD,AMR,0B1h ;Point to the upper bits of the connection MI,IDR,000_01110b :Set up a write into data memory from ECTF bus, ; disable pattern mode, minimum delay, ; and set stream number equal to 01110b (14). MD,AMR,0B2h ;Point to tag field MI,IDR,31h ;Use location 49 of the associated Data RAM to store the data MD,AMR,0B3h ;Point to the subrate control and TAG MSB field; MI,IDR,00h ;MSB of location 49 is 0; MD,AMR,0E0h ;Write to next free location in the Even CAM MI,IDR,0E0h ;The command is executed with the indirect to IDR which ;uses the same command value as in the AMR.

Lucent Technologies Inc. 81 Advance Data Sheet November 1999 H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105 ;Optional: Test CAM Busy bit TEST: MD,ACC,MCR ;Move MCR contents into (host’s) accumulator (for example) AND,01h ;Logical AND, i.e., mask off all but LSB of the MCR register JNZ TEST ;If the LSB is zero (not busy), continue, else jump back and ;retest CONTINUE: MD,AMR,0B0h ;Point to the Time-Slot holding register MI,IDR,1Dh ;This is the Time-Slot value (29) for the Local address MD,AMR,0B1h ;Point to the upper bits of the connection MI,IDR,100_00011b :Set up a read from data memory to Local pins, ; disable pattern mode, minimum delay, and set ; stream number equal to 00011b (3). MD,AMR,0B2h ;Point to tag field MI,IDR,31h ;Use location 49 of the associated Data RAM to store the data MD,AMR,0B3h; MI,IDR,00h; MD,AMR,0E3h ;Write to next free location in the Local CAM MI,IDR,0E3h ;The command is executed with the indirect to IDR ;CAM Busy bit can be tested here

3.4.4 Miscellaneous Commands

These commands (i.e., 0x70, 0xF8, all reset commands in the AMR register) require two writes: first the value is written to the AMR register; then the same value is written to the IDR register. After writing to the IDR register, the command will be executed.

82 Lucent Technologies Inc. Advance Data Sheet November 1999H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105

4 Electrical Characteristics

4.1 Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.

4.2 Handling Precautions

Although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance = 1500Ω , capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes: Description Symbol Min Max Unit Supply Voltage V DD —3 . 6 V XT ALIN and XT ALOUT Pins — V SS VDD V Voltage Applied to I/O Pins — V SS – 0.5 V DD + 3.4 V Operating T emperature: 208-pin SQFP 217-ball BGA −40 Storage T emperature T stg –55 125 °C HBM ESD Threshold Voltage Device Rating T8100A, T8102, T8105 2500 V

4 Electrical Characteristics (continued)

4.3 Crystal Information

Table 72. Crystal Specifications as the clocking source while mastering the bus. Otherwise, a crystal with a lesser tolerance can be used. Table 73. Use of an Oscillator as an Alternative to Using a Crystal lator must meet the requirements shown below.

4.4 Reset Pulse

4.5 Thermal Considerations

4.5.1 Thermal Considerations for the 208 SQFP

4.5.2 Thermal Considerations for the 217 PBGA

23 Peripheral

4.6.1 Electrical Drive Specifications—CT_C8 and /CT_FRAME

Table 74. Electrical Drive Specifications—CT_C8 and /CT_FRAME VDD = 3.3 V and VSS = 0.0 V unless otherwise specified. CT_C8 and /CT_FRAME signals, though this is not explicitly stated as a part of the H.100 Specification. Table 75. dc Electrical Characteristics, All Other Pins VDD = 3.3 V and VSS = 0.0 V unless otherwise specified.

• Circuit simulation indicates a typical current of 175 mA and a worst-case current of 275 mA. This parameter is not tested in production.

4.8.1 Clock Alignment

Figure 24. Clock Alignment

4.8.2 Frame Diagram

Note: Bit 1 is the MSB. Bit 8 is the LSB. MSB is always transmitted first in all transfers. Figure 25. Frame Diagram

4.8.3 Detailed Timing Diagram

Figure 26. Detailed Timing Diagram

1 BIT CELL

1. The rise and fall times are determined by the edge rate in V/ns. A maximum edge rate is the fastest rate at which a clock transitions.
2. Measuring conditions, data lines: VTH (threshold voltage) = 1.4 V , VHI (test high voltage) = 2.4 V , VLO (test low voltage) = 0.4 V , input sig-
3. When RESET is active, every output driver is 3-stated.
4. tC8P minimum and maximum are under free-run conditions assuming ±32 ppm clock accuracy.
5. Noncumulative, tC8P requirements still need to be met.
6. Measured at the transmitter.
7. Measured at the receiver.
8. tDV = maximum clock cable delay + maximum data cable delay + maximum data HiZ to output time = 12 ns + 35 ns + 22 ns = 69 ns. Maxi-

mum clock cable delay and maximum data cable delay are worst-case numbers based on electrical simulation.

1. tDOZ and tZDO apply at every time-slot boundary.
2. F (phase correction) results from PLL timing corrections.

4.8.5 Detailed Clock Skew Diagram

Figure 27. Detailed Clock Skew Diagram

1. Assumes A and B masters in adjacent slots.
2. When static skew is 10 ns and, in the same clock cycle, each clock performs a 10 ns phase correction in opposite directions, a maximum

skew of 30 ns will occur during that clock cycle.

1. Meeting the skew requirements in T able 10 and the requirements of Section 2.3 H-Bus Section could require the PLLs generating CT_C8 to

have different time constants when acting as primary and secondary clock masters.

4.8.7 Reset and Power On

Table 78. Reset and Power On Table 79. ac Electrical Characteristics, Local Streams, and Frames Table 80. L_SC[3:0] and Frame Group Rise and Fall Time

• Worst-case loading of 50 pF on all outputs except CT_D[31:0]. CT_D[31:0] drives 200 pF .

• Frame group is shown with an offset of four (4).

Note: LDO7 is the MSB, LDO0 is the LSB. MSB is always transmitted first in all transfers. Figure 28. ac Electrical Characteristics, Local Streams, and Frames

8.192 Mbits/s

4.096 Mbits/s

2.048 Mbits/s

4.10.1 Microprocessor Access Intel Multiplexed Write and Read Cycles

For Intel write and read cycles, when RDY is low, wait-states are inserted. RDY is brought high when tIACC is met. This is true for both read and write cycles. Figure 29. Microprocessor Access Intel Multiplexed Write Cycle Figure 30. Microprocessor Access Intel Multiplexed Read Cycle

4.10.2 Microprocessor Access Motorola Write and Read Cycles

Figure 31. Microprocessor Access Motorola Write Cycle Figure 32. Microprocessor Access Motorola Read Cycle

4.10.3 Microprocessor Access Intel Demultiplexed Write and Read Cycles

Figure 33. Microprocessor Access Intel Demultiplexed Write Cycle Figure 34. Microprocessor Access Intel Demultiplexed Read Cycle Table 81. Microprocessor Access Timing

94 Lucent Technologies Inc. Advance Data Sheet November 1999H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105

5 Outline Diagrams

5.1 208-Pin Square Quad Flat Package (SQFP) Dimensions are in millimeters. Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat- ics to assist your design efforts, please contact your Lucent Technologies Microelectronics Group Account Manager. 5-2196(F) 156 105 30.60 ± 0.20 157208 53 104 28.00 ± 0.20 28.00 ± 0.20 30.60 ± 0.20 PIN #1 IDENTIFIER ZONE

4.10 MAX

0.08 3.40 ± 0.20 SEATING PLANE 0.25 MIN0.50 TYP DETAIL BDETAIL A 0.50/0.75 GAGE PLANE SEATING PLANE

1.30 REF

0.25 DETAIL A DETAIL B 0.17/0.27 0.10 M 0.090/0.200

Lucent Technologies Inc. 95 Advance Data Sheet November 1999 H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105

5 Outline Diagrams (continued)

5.2 217-Ball Plastic Ball Grid Array (PBGA) Dimensions are in millimeters. Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat- ics to assist your design efforts, please contact your Lucent T echnologies Microelectronics Group Account Manager. 5-6562(F) SEATING PLANE SOLDER BALL0.60 ± 0.10 0.20 A B C D E F G H J K L M N P R T U 1 2 3 4 5 6 7 8 9 1 01 1 1 21 31 41 51 6 1 7 16 SPACES @ 1.27 = 20.32 A1 BALL CORNER

16 SPACES

@ 1.27 = 20.32 0.75 ± 0.15 PWB MOLD COMPOUND 23.00 ± 0.20 23.00 ± 0.20 19.50 +0.70 –0.00 19.50 +0.70 –0.00A1 BALL IDENTIFIER ZONE SIDE VIEW BOTTOM VIEW TOP VIEW

9696 Lucent Technologies Inc. Advance Data Sheet November 1999H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105

6 Ordering Information

Device Part Number Package Comcode T8100A- - -SC-DB 208-Pin SQFP 108296146 T8100A- - -BAL-DB 217-Ball PBGA 108296138 T8102- - -SC-DB 208-Pin SQFP 108296161 T8102- - -BAL-DB 217-Ball PBGA 108296153 T8105- - -SC-DB 208-Pin SQFP 108296187 T8105- - -BAL-DB 217-Ball PBGA 108296179 Version 3 Device Part Number Package Comcode T8105- - -BAL3-BB 217-Ball PBGA 108553397 T8105- - -SC3-DB 208-Pin SQFP 108553561 T8102- - -SC3-DB 208-Pin SQFP 108553587 T8102- - -BAL3-DB 217-Ball PBGA 108553579 T8100A- -BAL3-DB 217-Ball PBGA 108553595 T8100A- -SC3-DB 208-Pin SQFP 108553603

Lucent Technologies Inc. 97 Advance Data Sheet November 1999 H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105 Appendix A. Application of Clock Modes In the diagrams that follow, four clock modes are illus- trated using Figure 16, the clocking diagram, as the basis of each illustration. The key signal paths are shown in solid lines, and unused paths with narrow dashes. Two examples also indicate fallback paths. A register profile (programming values) for all four exam- ples is on the last page of the appendix. Figure 35 shows the devices in bus master operation, so they must link to either an 8 kHz recovered frame reference or a 2.048 MHz recovered bit clock reference from the E1 framers. In addition, the devices can pro- vide one of the basic resource clocks to run the fram- ers. In this case, the TCLKOUT is selecting the device’s 16.384 MHz oscillator. The framers are returning a

2.048 MHz bit clock which is selected through the clock

selector. It is not divided, so the main divider is bypassed (divide-by-1), the clock is smoothed through an external DJA T , and the smooth 2.048 MHz signal is routed to PLL #1 through the clock resource selector. PLL #1 multiplies the 2.048 MHz input up to

65.536 MHz which, in turn, runs the rest of each

device, all bus clocks, and the local clocks (if desired). If the devices are not providing NETREF generation, then the NETREF from the bus is routed to the local clocks via the NETREF internal/external selector. Since the NETREF generation resources are not needed here, the TODJA T and FROMDJA T pins are free for use with the general-purpose register as bits GP6 and GP7, respectively. Figure 36 shows the T1 version of a bus master. In this scenario, a 1.544 MHz recovered bit clock from the framers is routed to a multiclock adapter (with built-in jitter attenuation) which produces smooth 4.096 MHz and 3.088 MHz outputs. The 4.096 MHz output is routed up to PLL #1 for a times-16 rate multiplication to 65.536 MHz. This drives the bus clocks and the local clocks. The smooth 3.088 MHz is also rate multiplied times 8. This produces a 24.704 MHz clock. This is divided back down to produce a smooth 12.352 MHz which is fed back to the framers. (PLL outputs produce one tightly bound edge and one with significant phase jitter. Dividing a higher-frequency signal based on its clean edge produces a lower frequency with two clean edges.) Figure 37 shows an H- MVIP slave arrangement for E1. In this example, the C16 differential clocks provide the main source for PLL #1. The 16.384 MHz signal is divided down to 4.096 MHz and then rate multiplied up to 65.536 MHz for driving the rest of each device. The frame sync for the state machines is derived from the /FRAME and C16 inputs as well as the state informa- tion provided by C2 and /C4. Note: The bit slider is enabled for a smooth phase alignment between the internal frame and the frame sync. The bus clocks are not driven, but the local clocks are available. A path for NETREF is shown as well, also based on a 2.048 MHz input. The signal is smoothed and then divided down to an 8 kHz signal via the NETREF divider. The internal oscillator is again chosen for routing to the framers via TCLKOUT . Figure 38 shows an H- MVIP slave for T1. This is identi- cal to the E1 case with regard to slaving, and a NETREF path is illustrated in this example, too. The NETREF divider has been changed to accommodate the 1.544 MHz bit clock rate. The primary difference is the use of the C16 clock through the main divider to generate a 2.048 MHz signal which can be routed off- chip and adapted to a 1.544 MHz signal using an exter- nal device. The 1.544 MHz signal is returned to each device via the 3MHzIN for rate multiplication up to 24.704 MHz and then division to a clean 12.352 MHz signal which is routed to the framers via TCLKOUT .

Figure 35. E1, CT Bus Master, Compatibility Clock Master, Clock Source = 2.048 MHz from Trunk

2 MHz DJAT

Figure 36. T1, CT Bus Master, Compatibility Clock Master, Clock Source = 1.544 MHz from Trunk

1.544 MHz

100 Lucent Technologies Inc. Figure 37. E1, Slave to CT Bus, Clock Source Is Either a 16 MHz or a 4 MHz or a 2 MHz and Frame, NETREF

Figure 38. T1, Slave to CT Bus, Clock Source Is Either a 16 MHz or a 4 MHz or a 2 MHz and Frame, NETREF

1.5 MHz DJAT

102 Lucent Technologies Inc. Table 82. Clock Register Programming Profile for the Four Previous Examples is covered by registers CKM, CKR, CKMD, and CKRD. Note:CKR does include an example of running PLL #1 at X32 for E1 master and X16 for all other cases. (uninitialized clocks, for example) from changing the operating mode.

Lucent Technologies Inc. 103 Advance Data Sheet November 1999 H.100/H.110 Interfaces and Time-Slot Interchangers Ambassador T8100A, T8102, and T8105 Appendix B. Minimum Delay and Constant Delay Connections B.1 Connection Definitions Forward A forward connection is defined as one Connection in which the output (to) time slot has a greater value than the input (from) time slot, or put another way, the delta between them is positive. Reverse A reverse connection is defined as one Connection in which the output (to) time slot has a lesser value than the input (from) time slot, and the delta between them is negative. So, for example, going from TS(1) to TS(38) is a for- ward connection, and the TSΔ is +37, but going from TS(38) to TS(1) is a reverse connection, with a TSΔ of –37: where TSΔ = TS(to) – TS(from). Similarly, a delta can be introduced for streams which will have a bearing in certain exceptions (discussed later): STR Δ = STR(to) – STR(from) There is only one combination which forms a TSΔ of +127 or –127: TS Δ = TS(127) – TS(0) = +127, and but there are two combinations which form TSΔs of +126 or –126: TS Δ = TS(127) – TS(1) = TS(126) – TS(0) = +126, and there are three combinations which yield +125 or –125, and so on. The user can utilize the TSΔ to control the latency of the resulting connection. In some cases, the latency must be minimized. In other cases, such as a block of connections which must maintain some relative integ- rity while crossing a frame boundary, the required latency of some of the connections may exceed one frame (>128 time slots) to maintain the integrity of this virtual frame. Each device contains several bits for controlling latency. Each connection has a bit which is used for selecting one of two alternating data buffers. These bits are set in the local connection memory (T8100A, T8105 only) for local switching or in the tag register field of the CAM section for H-bus switching. There are also 2 bits in the CON register, address 0x0E, which can control the buffer selection on a chip-wide basis. Bit 1 of the register overrides the indiv idual FME bits. Bit 0 becomes the global, chip-wide, FME setting.

104104 Lucent Technologies Inc. 256 time slots after the from time slot. to solve for either TS(to) or TS(from). Frame(n) to TS(1) of Frame(n + 2). Figure 39. Constant Delay Connections, CON[1:0] = 0X

delays with the double buffering. Table 83. Table of Special Cases (Exceptions) main function by dashed lines. Figure 40. Minimum Delay Connections, CON[1:0] = 0X

106106 Lucent Technologies Inc. Forward Connections: L = TSΔ (3 ≤ TSΔ ≤ 127). Reverse Connections: L = 256 + TSΔ (–127 ≤ TSΔ ≤ 0). 0 of CON for the FME value in Table 83. Figure 41. Mixed Minimum/Constant Delay Connections, CON[1:0 = 10]

Figure 42. Extended Linear (Mixed Minimum/Constant) Delay, CON[1:0] = 11 tents, however, there is some bit manipulation involved.

Lucent Technologies Inc. reserves the right to ma ke changes to the product(s) or inform ation contained herein without notice. No liability is assum ed as a result of their use or application. No rights under any patent accompa ny the sale of any such product(s) or inform ation. Ambassador is a trademark of Lucent T echnologies Inc. Co pyright © 1999 Lucent Technologies Inc. All Rights Reserved N ovember 1999 DS00-028CTI (Replaces DS98-387NTN B, DA99-002NTN B, DA99-003NT N B) For additional information, contact your M icroelectronics Group Account M anager or the following: IN TERNE T: http://www .lucent.com/micro E-M AIL: docm aster@mi cro.lucent.com N. AM ERICA : Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown , PA 18103 1-800-372-2447, FAX 610-712-4106 (In C AN ADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC : Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 C HIN A: M icroelectronics Group, Lucent Technologies (C hina) C o., Ltd., A-F2, 23/F, Zao Fong U niverse Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. C hina Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: M icroelectronics Group, Lucent Technologies Japan Ltd., 7-18, H igashi-G otanda 2-chom e, Shinagaw a-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EU R O PE : D ata Requests: M ICR O ELEC TR O N ICS GR OU P DATALIN E: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries:GE R MA N Y: (49) 89 95086 0 (Munich), U N ITED KIN GDO M : (44) 1344 865 900 (Ascot), FR AN CE : (33) 1 40 83 68 00 (Paris), SWE D EN : (46) 8 594 607 00 (Stockholm), FIN LAND : (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN : (34) 1 807 1441 (Madrid)