T8100 AGERE | Alldatasheet
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H.100/H.110 Interface and Time-Slot Interchanger This advisory details two changes to the AmbassadorTM T8100 H.100/H.110 Interface and Time-Slot Interchanger Preliminary Data Sheet: DS98-195NTNB. Change Affecting Page 15, Section 2.1.3 Address Mode Register Problem: There is a minor bug in the T8100. If a write is issued to the address mode register (AMR) address 0x70 (local bus, holding registers, and reset), the T8100’s RDY line gets stuck low (not ready state). Workaround: T o solve this, issue another write command to any of the four direct registers (MCR, LAR, AMR, or IDR) and the RDY signal will reset. Change Affecting Page 38, Section 2.4.2 Dividers and Rate Multipliers There is an anomaly in the digital phase-lock loop (DPLL) performance of the device. The behavior affects all versions of the T8100 but has been corrected in the T8100A, T8102, and T8105. This anomaly affects applica- tions that use the DPLL for CT bus clock generation. When used for clocking, the DPLL uses the 16.384 MHz internal oscillator to rate multiply an 8 kHz input sig- nal. In order for the DPLL to lock to the 8.000000 kHz signal, the required internal oscillator frequency range should be centered at 16.388 MHz. A frequency of 16.384 MHz is too low for the DPLL to perform properly. If this crystal adaptation is used for the DPLL, there are several limitations. First, do not select the crystal as a fallback clock source. When the crystal is a clock source, the generated clocks are all multiples of the crystal. In that case, they will be offset by the same ratio as the crystal. Second, do not use TCLKOUT. It is also derived from the crystal and will be offset by the same ratio. Third, the watchdogs will be slightly more sensitive due to the increased clock frequency. In designs affected by these limitations, conversion to the T8100A is recom- mended.
Lucent Technologies Inc. reserves the right to ma ke changes to the product(s) or inform ation contained herein without notice. No liability is assum ed as a result of their use or application. No rights under any patent accompa ny the sale of any such product(s) or inform ation. Ambassador is a trademark of Lucent T echnologies Inc. Co pyright © 1999 Lucent Technologies Inc. All Rights Reserved Ma rch 1999 AY99-019NTNB (R eplaces AY99-011NTNB and must accompa ny D S98-195NTNB) For additional information, contact your M icroelectronics Group Account M anager or the following: IN TERNE T: http://www .lucent.com/micro E-M AIL: docm aster@mi cro.lucent.com N. AM ERICA : Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown , PA 18103 1-800-372-2447, FAX 610-712-4106 (In C AN ADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC : Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 C HIN A: M icroelectronics Group, Lucent Technologies (C hina) C o., Ltd., A-F2, 23/F, Zao Fong U niverse Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. C hina Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: M icroelectronics Group, Lucent Technologies Japan Ltd., 7-18, H igashi-G otanda 2-chom e, Shinagaw a-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EU R O PE : D ata Requests: M ICR O ELEC TR O N ICS GR OU P DATALIN E: Tel. (44) 1189 324 299, FAX (44) 1189 328 148 Technical Inquiries:GE R MA N Y: (49) 89 95086 0 (Munich), U N ITED KIN GDO M : (44) 1344 865 900 (Ascot), FR AN CE : (33) 1 40 83 68 00 (Paris), SWE D EN : (46) 8 594 607 00 (Stockholm), FIN LAND : (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN : (34) 1 807 1441 (Madrid)
H.100/H.110 Interface and Time-Slot Interchanger
1 Product Overview
1.1 Introduction
Increasingly, enhanced telephony services are pro- vided by equipment based on mass-market com- puter-telephony architectures. The H.100 time- division multiplexed (TDM) bus has emerged as the industry standard used in these systems. The Ambassador T8100 is a single device that provides a complete interface for H.100/H.110-based systems. The T8100 will support the newer bus standards, H-MVIP * and ECTF H.100, but remain downward compatible with MVIP -90 and Dialogic’s† SC-Bus. Data can be buffered in either minimum delay or con- stant delay modes on a connection-by-connection basis. The T8100 will take advantage of new technology: it is based on 0.35 micron feature sizes and a robust standard-cell library. It utilizes associative memory (content addressable memories [CAM]) in addition to traditional static RAM and register file structures for the connection and data memories. The T8100 oper- ates on a single 3.3 V supply, but all inputs are 5 V tolerant and standard TTL output levels are main- tained.
1.2 Features
■ Complete solution for interfacing board-level cir- cuitry to the H.100 telephony bus ■ H.100 compliant interface; all mandatory signals ■ Programmable connections to any of the 4096 time slots on the H.100 bus ■ Up to 16 local serial inputs and 16 local serial outputs, programmable for 2.048 Mbits/s, 4.096 Mbits/s, and 8.192 Mbits/s operation per CHI specifications ■ Programmable switching between local time slots, up to 1024 connections ■ Programmable switching between local time slots and H.100 bus, up to 256 connections ■ Choice of frame integrity or minimum latency switching on a per-time-slot basis — Frame integrity to ensure proper switching of wideband data — Minimum latency switching to reduce delay in voice channels ■ On-chip phase-locked loop (PLL) for H.100, MVIP, or SC-Bus clock operation in master or slave clock modes ■ Serial TDM bus rate and format conversion between most standard buses ■ Optional 8-bit parallel input and/or 8-bit parallel output for local TDM interfaces ■ High-performance microprocessor interface — Provides access to device configuration regis- ters and to time-slot data — Supports both Motorola‡ nonmultiplexed and Intel§ multiplexed/nonmultiplexed modes ■ T wo independently programmable groups of up to 12 framing signals each ■ 3.3 V supply with 5 V tolerant inputs and TTL-com- patible outputs ■ Boundary-scan testing support ■ 208-pin, plastic SQFP package ■ 217-pin BGA package (industrial temperature range) * MVIP is a registered trademark of GO-MVIP , Inc. † Dialogic is a registered trademark of Dialogic Corporation. ‡ Motorola is a registered trademark of Motorola, Inc. § Intel is a registered trademark of Intel Corporation.
2 Lucent Technologies Inc. Preliminary Data Sheet August 1998H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100 Table of Contents Contents Page
1.7 Phase Alignment of Referenced and
2.2.1 Constant Frame Delay and Minimum
2.3.5 H-Bus Rate Selection and Connection
2.4.7 CKMD, CKND, CKRD: Clocks, Main,
NETREF, Resource Dividers, 0x07, 0x08, Contents Page
3.3 Using the LAR, AMR, and IDR for
4.4 dc Electrical Characteristics, H-Bus
4.4.1 Electrical Drive Specifications—CT_C8
4.6 H-Bus Timing (Extract from H.100 4.6.4 ac Electrical Characteristics, Timing, 4.3.6 ac Electrical Characteristics, Skew 4.7 ac Electrical Characteristics, Local 4.8 ac Electrical Characteristics, Micro-
4.8.1 Microprocessor Access
4.8.2 Microprocessor Access Motorola Write
4.8.3 Microprocessor Access Intel Demultiplexed
Figure 8. Simplified Local Memory State Timing, Figure 10. Simplified H-Bus State Timing, Figure 13. A, B, and C Clock Fallback State Figure 17. Local-to-Local Connection Figure 18. CAM Programming, H-Bus-to-Local Figure 23. ac Electrical Characteristics, Local Figure 24. Microprocessor Access Intel Multi- Figure 25. Microprocessor Access Intel Multi- Figure 26. Microprocessor Access Motorola Figure 27. Microprocessor Access Motorola Figure 28. Microprocessor Access Intel Figure 29. Microprocessor Access Intel Figure 30. E1, CT Bus Master, Compatibility Clock Figure 31. T1, CT Bus Master, Compatibility Clock Figure 32. E1, Slave to CT Bus, Clock Source Is
2 MHz and Frame, NETREF
Figure 33. T1, Slave to CT Bus, Clock Source Is
2 MHz and Frame, NETREF Source
Figure 34. Constant Delay Connections, Figure 35. Minimum Delay Connections, Figure 36. Mixed Minimum/Constant Delay Con- Figure 37. Extended Linear (Mixed Minimum/Con-
Table 1. Pin Descriptions: Clocking and Framing Table 4. Pin Descriptions: Microprocessor Interface Table 12. CKM: Clocks, Main Clock Selection, Table 13. CKN: Clocks, NETREF Selections, Table 14. CKP: Clocks, Programmable Outputs, Table 15. CKR: Clocks, Resource Selection, Table 16. CKS: Clocks, Secondary (Fallback) Table 19. CKMD: Clocks, Main Divider; CKND: Table 22. HSL: H-Bus Stream Control, Low Table 23. HSH: H-Bus Stream Control, High Table 24. GPR: General-Purpose I/O Register, Table 25. FRLA: Frame Group A, Start Address Table 26. FRHA: Frame Group A, High Address Table 27. FRLB: Frame Group B, Start Address Table 28. FRHB: Frame Group B, High Address Table 29. FRPL: Frame Group B, Programmed Table 30. FRPH: Frame Group B, Programmed Table 31. CLKERR1: Clock Error Register, Error Table 32. CLKERR2: Clock Error Register, Current Table 33. SYSERR: System Error Register, Table 34. CKW: Clock Error/Watchdog Masking Table 39. CKM: Clocks, Main Clock Selection, Table 40. CKN: Clocks, NETREF Selections, Table 41. CKP: Clocks, Programmable Outputs, Table 42. CKR: Clocks, Resource Selection, Table 43. CKS: Clocks, Secondary (Fallback) Table 44. CK32 and CK10: Clocks, Locals 3, 2, 1, Table 45. FRHA, Frame Group A High Address Table 46. FRHB, Frame Group B High Address Table 47. FRPH: Frame Group B, Programmed Table 48. CLKERR1 and CLKERR2: Error Indicator Table 49. SYSERR: System Error Register, Table 53. IDR: Indirect Data Register, Local Table 54. IDR: Indirect Data Register, H-Bus Table 57. Electrical Drive Specifications—CT_C8 Table 58. dc Electrical Characteristics, All Other Table 59. ac Electrical Characteristics, Timing, Table 60. ac Electrical Characteristics, Skew Table 62. ac Electrical Characteristics, Local Table 63. Microprocessor Access Timing (See Table 64. Clock Register Programming Profile for
1 Product Overview (continued)
1.3 Pin Information
Figure 1. Pin Diagram
1.3 Pin Information (continued)
Figure 2. 217 PBGA—Top View Table 1. Pin Descriptions: Clocking and Framing Pins I Local Frame Reference Inputs. 50 kΩ internal pull-up. drive, Schmitt in, 50 kΩ internal pull-up.
Table 1. Pin Descriptions: Clocking and Framing Pins (continued) drive, Schmitt in, 50 kΩ internal pull-up. ondary (NETREF). 8 mA drive, 3-state. O Frame Group A. 8 mA drive, 3-state. O Frame Group B. 8 mA drive, 3-state. PRIREFOUT 58 P5 O Output from Primary Clock Selector/Divider. 8 mA drive. ground, even if PLL #1 is not used. 4MHZIN 54 U2 I PLL #1 Rate Multiplier. Can be 2.048 MHz or 4.096 MHz. ing only if both PLL #2 and 3MHZIN are not used. left floating only if both PLL #2 and 3MHZIN are not used. 3MHZIN 1 A1 I PLL #2 Rate Multiplier. Input, 50 kΩ internal pull-up. XT ALOUT 48 T1 O 16.384 MHz Crystal, Feedback Connection. TCLKOUT 203 C4 O Selected output to drive framers. 8 mA drive, 3-state.
Table 2. Pin Descriptions: Local Streams Pins Table 3. Pin Descriptions: H-Bus Pins 24 mA drive, Schmitt in. No pull-up. compliant, 24 mA drive. Schmitt in. No pull-up. Schmitt in, 50 kΩ internal pull-up. in. Not internally pulled up. 24 mA drive, Schmitt in. No pull-up. compliant, 24 mA drive, Schmitt in. No pull-up. CT_Dxx only for H.100, low disables for H.110.
Table 4. Pin Descriptions: Microprocessor Interface Pins Table 5. Pin Descriptions: JTAG Pins Table 6. Pin Descriptions: Power Pins I Microprocessor Interface, Address Lines. Internal 20 kΩ pull-down. I/O Microprocessor Interface, Data Lines. 8 mA drive, 50 kΩ internal pull-up. ALE 29 L1 I Address Latch Enable. Internal 20 kΩ pull-down. CS 28 K3 I Chip Select (Active-Low). 50 kΩ internal pull-up. Low]). 50 kΩ internal pull-up. Low]). 50 kΩ internal pull-up. RDY (DTACK ) 25 J3 O Data Ready (Intel), Data Transfer (Motorola [Active-Low]). 8 mA, open drain (user should add pull-up to this line). SYSERR 12 F3 O System Error. Logical OR of all CLKERR and SYSERR register flags. TCLK 9 E3 I JTAG Clock Input. TMS 8 F4 I JTAG Mode Select. 50 kΩ internal pull-up. TDI 7 D2 I JTAG Data Input. 50 kΩ internal pull-up. TDO 6 C1 O JTAG Data Output. 8 mA drive, 3-state. TRST 5E 4 I JTAG Reset (Active-Low). 50 kΩ internal pull-up.
Table 7. Pin Descriptions: Other Pins (for NETREF) or GP Register Bit 6. and Drivers or GP Register Bit 7. output test, internal pulldown.
1.4 Enhanced Local Stream Addressing
regardless of rate or serial/parallel modes. the 32 physical streams, selected in groups of four.
Lucent Technologies Inc. 11 Preliminary Data Sheet August 1998 H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100
1.6 Onboard PLLs and Clock Monitors
The T8100 uses rate multipliers and state machines to generate onboard frequencies for supporting the H.100, H- MVIP, MVIP, MC-1, and SC-Buses. Pins are provided for coupling the internal clock circuitry with commonly available clock adapters and jitter attenua- tors. If external resources are not available, an internal digital phase-locked loop (DPLL) can be used to gener- ate all the bus frequencies and remain synchronized to an 8 kHz reference. One of several clock input refer- ence sources may be selected, and separate input- active detection logic can identify the loss of the individ- ual input references. The entire clocking structure oper- ates from a 16.384 MHz crystal or external input. If this resource is selected, special control logic will cre- ate bit-sliding in the data streams when the reference frame and generated frame are out of phase. The bit- sliding refers to removing a fraction of a bit time per frame until the frames are in phase.
1.8 Interfaces
1.8.1 Microprocessors
The T8100 provides the user a choice of either Motor- ola or Intel interfacing through an 8-bit data bus, a 2-bit address bus, and multifunction control pins. All access to T8100 memory blocks and registers use indirect addressing.
1.8.2 Framing Groups
T wo groups of programmable framing signals are avail- able. Each group is composed of 12 sequenced lines operating in one of four modes. The T8100 supports 1-bit, 2-bit, 1-byte, and 2-byte pulse widths. Starting position of the pulse sequences are also programma- ble.
1.8.3 General-Purpose Register and I/O
A general-purpose register is provided as either a byte- wide input or byte-wide output through a separate set of pins.
1.9 Applications
■ Computer-telephony systems ■ Enhanced service platforms ■ WAN access devices ■ PBXs ■ Wireless base stations
1.10 Application Overview
The integration of computers and telecommunications has enabled a wide range of new communications applications and has fueled an enormous growth in communications markets. A key element in the devel- opment of computer-based communications equipment has been the addition of an auxiliary telecom bus to existing computer systems. Most manufacturers of high-capacity, computer-based telecommunications equipment have incorporated some such telecom bus in their systems. Typically, these buses and bus interfaces are designed to transport and switch N x 64 kbits/s low-latency telecom traffic between boards within the computer, independent of the com- puter’s I/O and memory buses. At least a half dozen of these PC-based telecom buses emerged in the early 1990s for use within equipment based on ISA/EISA and MCA computers. With the advent of the H.100 bus specification by the Enterprise Computer T elephony Forum, the computer- telephony industry has agreed on a single telecom bus for use with PCI and compact PCI computers. H.100 facilitates interoperation of components, thus providing maximum flexibility to equipment manufacturers, value- added resellers, system integrators, and others build- ing computer-based telecommunications applications.
1212 Lucent Technologies Inc. Preliminary Data Sheet August 1998H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100
2 Architecture and Functional Descrip-
The T8100 is an H.100-compliant device that provides a complete interface between the H.100 bus and a wide variety of telephony interface components, pro- cessors, and other circuits. The bus interface provides all signals needed for the H.100 bus, the H- MVIP and MVIP -90 buses, or the SC-Bus. Local interfaces include 16 serial inputs and 16 serial outputs based on the Lucent Technologies Microelectronics Group con- centration highway interface (CHI). Two built-in time- slot interchangers are included. The first provides a local switching domain with up to 1024 programmable connections between time slots on the local CHI inputs and outputs. The second supports up to 256 program- mable connections between any time slot on the H.100 bus and any time slot in the local switching domain. The Ambassador is configured via a microprocessor interface. This interface can also read and write time slot and device data. Onboard clock circuitry, including a DPLL, supports all H.100 clock modes including MVIP and SC-Bus compatibility clocks. The local CHI interfaces support PCM rates of 2.048 Mbits/s, 4.096 Mbits/s, and 8.192 Mbits/s. The T8100 has internal circuitry to support either minimum latency or multi-time-slot frame integrity. Frame integrity is a requisite feature for applications that switch wide- band data (ISDN H-channels). Minimum latency is advantageous in voice applications. The T8100 has four major sections: ■ Local bus—refers to the local streams. ■ H-Bus—refers to the H.100/H.110/H-MVIP and legacy streams. ■ Interface—refers to the microprocessor interface, frame groups, and general-purpose I/O (GPIO). ■ Timing—the rate multipliers, DPLL, and clocking functions. Figure 3 shows a T8100 block diagram. The T8100 operates on a 3.3 V supply for both the core and I/Os, though the I/Os are TTL compatible and 5 V tolerant.
2 Architecture and Functional Description (continued)
Figure 3. Block Diagram of the T8100
2.1 Register/Memory Maps
2.1.1 Main Registers
The address bits are used to map a large memory space. All registers default to 0 at powerup. Table 8. Addresses of Programming Registers
2.1.2 Master Control and Status Register
Table 9. Master Control and Status Register 7M R Master (Software) Reset. A high reinitializes the T8100 registers. 6C E R Clock Error Reset. A high resets the error bits of the CLKERR registers. accessed during a write operation (i.e., input from local streams or input from H-Bus). 3H B E H-Bus Enable. On powerup or software reset, all H-Bus pins (including clocks) are disabled. HBE must be set high to reenable the 3-stated buffers. 2L B E Local Bus Enable. Same function as HBE for local data outputs. microprocessor, which allow it to finish quickly.
2.1 Register/Memory Maps (continued)
2.1.3 Address Mode Register
Note: All unused AMR values are reserved. Table 10. Address Mode Register 0000 0000 Control Registers. 0001 (aaaa) Local Bus, Data Memory 1. 0010 (aaaa) Local Bus, Data Memory 2. 0100 (aaaa) Local Bus, Connection Memory, Time-Slot Field. 0101 (aaaa) Local Bus, Connection Memory, Stream, and Control Bit Field. 0111 0000 Local Bus, Holding Registers, Reset. 1011 0000 CAM, Connection, Time-Slot Field. 1011 0001 CAM, Connection, Stream, and Control Bit Field. 1011 0010 CAM, Connection, T ag Field. 1110 0000 CAM, Even, Make Connection (MKCE). Write to next free location. 1110 0001 CAM, Odd, Make Connection (MKCO). Write to next free location. 1110 0011 CAM, Local, Make Connection (MKCL). Write to next free location. 1110 0100 CAM, Even, Break Connection (BKCE). 1110 0101 CAM, Odd, Break Connection (BKCO). 1110 0111 CAM, Local, Break Connection (BKCL). 1110 1000 CAM, Even, Clear Location (CLLE). Requires LAR. 1110 1001 CAM, Odd, Clear Location (CLLO). Requires LAR. 1110 1011 CAM, Local, Clear Location (CLLL). Requires LAR. 1110 1100 CAM, Even, Read Location (RDCE). Requires LAR, IDR holds results. 1110 1101 CAM, Odd, Read Location (RDCO). Requires LAR, IDR holds results. 1110 1111 CAM, Local, Read Location (RDCL). Requires LAR, IDR holds results. 1111 0000 CAM, Even, Find Entry (FENE). IDR holds results. 1111 0001 CAM, Odd, Find Entry (FENO). IDR holds results. 1111 0011 CAM, Local, Find Entry (FENL). IDR holds results. 1111 1000 CAM, Even, Reset (RSCE). 1111 1001 CAM, Odd, Reset (RSCO). 1111 1011 CAM, Local, Reset (RSCL). 1111 1100 CAM, Holding Registers, Reset (RCH). 1111 1111 CAM, Initialize (CI). Reset all CAM locations and holding registers.
2.1.4 Control Register Memory Space
Function of LAR values when AMR = 0x00. All control registers reset to 0x00. Table 11. Control Register Memory Space
2.1.4 Control Register Memory Space (continued)
ters and their interactions with the overall architecture. Table 12. CKM: Clocks, Main Clock Selection, 0x00 Table 13. CKN: Clocks, NETREF Selections, 0x01 Table 15. CKR: Clocks, Resource Selection, 0x03 Table 17. CK32: Clocks, Locals 3 and 2, 0x05 Table 18. CK10: Clocks, Locals 1 and 0, 0x06
7 Phase Alignment Enable
6 Phase Alignment Select
5 Compatibility Clock Direction
4 Input Clock Invert
3 Input Clock Select, MSB
2 Input Clock Select
1 Input Clock Select
0 Input Clock Select, LSB
7 Output Enable
6 I/O Select
5 Bypass Select
7 TCLK Select, MSB
6 TCLK Select
5 TCLK Select, LSB
4 CT_C8 Pins, Input T ype Select
3 CT_C8A Output Enable
2 CT_C8B Output Enable
1 CT_C8 Pins, Output Type Select
7 Resource Select, MSB
6 Resource Select, LSB
5 PLL #1 Bypass
4 PLL #1 Rate Select
3 PLL #2 Bypass
2 PLL #2 Rate Select
1 SCLK Output Select, MSB
0 SCLK Output Select, LSB
7 Secondary Resource Select, MSB
6 Secondary Resource Select, LSB
5 Fallback Type Select, MSB
4 Fallback Type Select, LSB
3 Fallback, Force Selection of Secondary Input
2 Secondary Input Clock Select, MSB
1 Secondary Input Clock Select
0 Secondary Input Clock Select, LSB
7 Local Clock 3 Select, MSB
6 Local Clock 3 Select
5 Local Clock 3 Select
4 Local Clock 3 Select, LSB
3 Local Clock 2 Select, MSB
2 Local Clock 2 Select
1 Local Clock 2 Select
0 Local Clock 2 Select, LSB
7 Local Clock 1 Select, MSB
6 Local Clock 1 Select
5 Local Clock 1 Select
4 Local Clock 1 Select, LSB
3 Local Clock 0 Select, MSB
2 Local Clock 0 Select
1 Local Clock 0 Select
0 Local Clock 0 Select, LSB
1818 Lucent Technologies Inc. Table 20. LBS: Local Stream Control, 0x0C Table 21. CON: Connection Delay Type, 0x0E Table 22. HSL: H-Bus Stream Control, Low Byte, Table 23. HSH: H-Bus Stream Control, High Byte, Table 24. GPR: General-Purpose I/O Register, 0x18
7 Divide Value, MSB
6 Divide Value
5 Divide Value
4 Divide Value
3 Divide Value
2 Divide Value
1 Divide Value
0 Divide Value, LSB
7 Parallel/Serial Select, MSB
6 Parallel/Serial Select, LSB
5 Local Group A Rate Select, MSB
4 Local Group A Rate Select, LSB
3 Local Group B Rate Select, MSB
2 Local Group B Rate Select, LSB
1 Local Group C Rate Select, MSB
0 Local Group C Rate Select, LSB
7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 Reserved
2 Reserved
1 Disabled Connection-by-Connection Delay
0 Enable Linear Delay
7 H-Bus Group D Rate Select, MSB
6 H-Bus Group D Rate Select, LSB
5 H-Bus Group C Rate Select, MSB
4 H-Bus Group C Rate Select, LSB
3 H-Bus Group B Rate Select, MSB
2 H-Bus Group B Rate Select, LSB
1 H-Bus Group A Rate Select, MSB
0 H-Bus Group A Rate Select, LSB
7 H-Bus Group H Rate Select, MSB
6 H-Bus Group H Rate Select, LSB
5 H-Bus Group G Rate Select, MSB
4 H-Bus Group G Rate Select, LSB
3 H-Bus Group F Rate Select, MSB
2 H-Bus Group F Rate Select, LSB
1 H-Bus Group E Rate Select, MSB
0 H-Bus Group E Rate Select, LSB
7 General-Purpose I/O, MSB
6 General-Purpose I/O
5 General-Purpose I/O
4 General-Purpose I/O
3 General-Purpose I/O
2 General-Purpose I/O
1 General-Purpose I/O
0 General-Purpose I/O, LSB
Table 26. FRHA: Frame Group A, High Address and Table 28. FRHB: Frame Group B, High Address and
7 Start Address, Bit 7, or Programmed Output,
6 Start Address, Bit 6, or Programmed Output,
5 Start Address, Bit 5, or Programmed Output,
4 Start Address, Bit 4, or Programmed Output,
3 Start Address, Bit 3, or Programmed Output,
2 Start Address, Bit 2, or Programmed Output,
1 Start Address, Bit 1, or Programmed Output,
0 Start Address, LSB, or Programmed Output,
7 Rate Select, MSB
6 Rate Select, LSB
5 Pulse Width Select, MSB
4 Pulse Width Select, LSB
3 Frame Invert, or Programmed Output, Bit 11
2 Start Address, MSB, or Programmed Output,
1 Start Address, Bit 9, or Programmed Output,
0 Start Address, Bit 8, or Programmed Output,
7 Start Address, Bit 7
6 Start Address, Bit 6
5 Start Address, Bit 5
4 Start Address, Bit 4
3 Start Address, Bit 3
2 Start Address, Bit 2
1 Start Address, Bit 1
0 Start Address, LSB
3 Frame Inversion Select
2 Start Address, MSB
1 Start Address, Bit 9
0 Start Address, Bit 8
7 Programmed Output, Bit 7
6 Programmed Output, Bit 6
5 Programmed Output, Bit 5
4 Programmed Output, Bit 4
3 Programmed Output, Bit 3
2 Programmed Output, Bit 2
1 Programmed Output, Bit 1
0 Programmed Output, Bit 0
7 Group A Output Pins Select, MSB
6 Group A Output Pins Select, LSB
4 Group B Output Pins Select
3 Programmed Output, Bit 11
2 Programmed Output, Bit 10
1 Programmed Output, Bit 9
0 Programmed Output, Bit 8
2020 Lucent Technologies Inc. Table 33. SYSERR: System Error Register, 0x2A Table 35. DIAG1: Diagnostics Register 1, 0x30 Table 36. DIAG2: Diagnostics Register 2, 0x31 Table 37. DIAG3: Diagnostics Register 3, 0x32
7 C8A or Frame A Error
6 C8B or Frame B Error
5 FR_COMPn Error
4 C16+ or C16– Error
3 C4n or C2 Error
1 SCLK Error
7 C8A or Frame A Fault Status
6 C8B or Frame B Fault Status
5 FR_COMPn Fault Status
4 C16+ or C16– Fault Status
3 C4n or C2 Fault Status
1 SCLK Fault Status
0 NETREF Fault Status
7 Even CAM Underflow Error (No Match)
6 Odd CAM Underflow Error (No Match)
5 Local CAM Underflow Error (No Match)
4 Even CAM Overflow or No-Match Error
3 Odd CAM Overflow or No-Match Error
2 Local CAM Overflow or No-Match Error
0 Fallback Enable Indicator
7 C8A and Frame A Error Mask
6 C8B and Frame B Error Mask
5 FR_COMPn Error Mask
4 C16+ and C16– Error Mask
3 C4n and C2 Error Mask
1 SCLK Error Mask
0 NETREF Error Mask
7 Frame Group A Output Select, MSB
6 Frame Group A Output Select, LSB
5 Frame Group B Output Select, MSB
4 Frame Group B Output Select, LSB
3 Memory Fill Enable
2 Memory Fill Pattern Select, MSB
1 Memory Fill Pattern Select, LSB
0 Memory Fill Status Bit (Read Only)
7 Frame Groups Cycle T est Enable
6 Break State Counter into Subsections
5 Bypass Internal Frame with FR_COMPn
3 Enable State Counter Parallel Load
2 Parallel Load Value of State Counter, MSB
1 Parallel Load Value of State Counter, Bit 9
0 Parallel Load Value of State Counter, Bit 8
7 Parallel Load Value of State Counter, Bit 7
6 Parallel Load Value of State Counter, Bit 6
5 Parallel Load Value of State Counter, Bit 5
4 Parallel Load Value of State Counter, Bit 4
3 Parallel Load Value of State Counter, Bit 3
2 Parallel Load Value of State Counter, Bit 2
1 Parallel Load Value of State Counter, Bit 1
0 Parallel Load Value of State Counter, LSB
2.2 Local Bus Section
Figure 4 shows the local bus section function diagram. associated with it by one time slot. Figure 4. Local Bus Section Function
1024 LOCATIONS
2.2 Local Bus Section (continued)
2.2.1 Constant Frame Delay and Minimum Delay Connections
nections which create the delay types referred to as minimum delay and constant delay. Figure 5. Local Bus Memory Connection Modes
Lucent Technologies Inc. 23 Preliminary Data Sheet August 1998 H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100 tion (continued)
2.2.2 Serial and Parallel
Nominally, the memory will be accessed by serial data streams which will require conversion of serial-to-paral- lel (S/P) for write accesses and parallel-to-serial (P/S) for read accesses. Since the local memory can have up to 16 serial inputs and 16 serial outputs, there will be a maximum of 16 S/P converters and 16 P/S converters operating simultaneously. If desired, eight of the S/P converters, local inputs 0—7, can be bypassed for a direct parallel write to the data memory. Likewise, eight of the P/S converters, local outputs 0—7, can be bypassed for a direct parallel read of the data memory. Unused S/P or P/S converters are nonfunctional in these modes. Note: The normal serial-to-serial local streaming is not available simultaneously with any of the parallel modes.
2.2.3 Data Rates and Time-Slot Allocation
At its maximum, the T8100 will be able to process 1024 nonblocking-to-local connections. The data rate
8.192 Mbits/s corresponds to 128 time slots,
4.096 Mbits/s corresponds to 64 time slots, and
2.048 Mbits/s corresponds to 32 time slots. Since dif- ferent data rates require different amounts of memory, the local memory can be filled in a number of ways. A nonblocking switch permits any time slot on any stream to be switched to another time slot on any stream in any direction. The local streams are arranged in three groups: A, B, and C. Group A corresponds to the local data pins 0— 7, group B with local data pins 8—11, and group C with local data pins 12—15. The groups may be operated at any of the three data rates: 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s; however, group B is activated only when group A is operating below 8.192 Mbits/s. Likewise, group C is activated when group B is operating below 8.192 Mbits/s. Note: In order to efficiently fill the memory, the mem- ory locations are read or filled in the same order regardless of their activation or rate. The streams are scanned in intervals equal to
8.192 Mbits/s time slots: first group A from 0 through 7,
then group B from 8 through 11, then group C from 12 through 15. If a group is active, the data is input from or output to the streams in that group. If a group is operat- ing below 8.192 Mbits/s and has already been scanned (at the 8.192 Mbits/s rate), then the data transfer opera- tion is ignored. For T8100 addressing, the user directly provides stream and time-slot information. The T8100 will map this into the physical memory, regardless of which stream groups are active or at what rate. While this makes programming simpler, it makes the internal operation more difficult to understand. Several dia- grams are required to illustrate how the memory utiliza- tion works. Unassigned time slots in the local output section are 3- stated. Therefore, multiple lines can be connected together.
2.2.3 Data Rates and Time-Slot Allocation (continued)
correspond to 64 time-slot addresses. Figure 6. Local Streams, Memory Structure
Examples of how the memory is filled are found in Figure 7. Figure 7. Local Memory, Fill Patterns
Figure 7. Local Memory, Fill Patterns (continued) every second even location is scanned.
2.2.4 LBS: Local Stream Control, 0x0C
Table 38. LBS: Local Stream Control, 0x0C by the stream and time-slot designators, rather than physical address locations, to simplify the queries. P/S 7—6 P/S = 00. Serial In/Serial Out. be identical so both inputs and outputs share the same 2 bits for programming. The SGb bits are enabled when SGa ≠ 11. The SGc bits are enabled when SGb ≠ 11. P/S = 01. Serial In/Parallel Out. SGa sets input (serial) rate using the rate definition within this table. SGc sets the output (parallel) rate using the rate definition within this table. P/S = 10. Parallel In/Serial Out. SGa sets input (parallel) rate. SGc sets output (serial) rate. P/S = 11. Parallel In/Parallel Out. SGa sets input (parallel) rate. SGc sets output (parallel) rate.
2.2.5 State Counter Operation
discussed in Section 2.3 H-Bus Section. Figure 8. Simplified Local Memory State Timing, 65.536 MHz Clock
2.3 H-Bus Section
2.3.1 Memory Architecture
internal clock speed of 15.26 ns (65.536 MHz) is used. Figure 9. The combined comparison plus retrieval SRAM (actually, a register file) is tied to each CAM. and as illustrated in Figure 5. to the maximum number of connections required (256).
2.3 H-Bus Section (continued)
2.3.1 Memory Architecture (continued)
Figure 9. CAM Architecture connection type is broadcast, i.e., from one to many.
3 CAMS, MAXIMUM OF 48 ACCESSES PER 976 ns
Lucent Technologies Inc. 31 Preliminary Data Sheet August 1998 H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100 tion (continued)
2.3.2 CAM Operation and Commands
The three CAMs operate in parallel. Each CAM’s com- parand field is compared with the state counter (Sec- tion 2.2.5 State Counter Operation) which holds the existing stream and time-slot value*. If there is a match, the CAM issues a hit. If there is more than one match, then it is considered a multiple hit. Likewise, no match is a miss. As a part of the state counter, a bit is toggled for read/write. The read/write bit is stored in the CAM, so it becomes part of the value to be compared. If the comparison for a write yields a hit, then there is a request for write access to the data memory for the incoming data from the H-Bus. If the comparison for a read yields a hit, then there is a request for a read access from the data memory for outgoing data to the H-Bus. Any multiple hit within one CAM block is treated as a controlled error although it is not reported. The action taken is to acknowledge the hit which corre- sponds to the lowest physical address of the CAM. A miss implies no action. A multiple hit is assigned to be more than one valid connection. These are prioritized such that the match with the lowest physical address (i.e., closest to CAM location 0x0) is the address which is processed. Thus, errors are handled in a controlled manner. Multiple hits can occur because multiple loca- tions are assigned to the same time slot. Bad software can cause this problem. A controlled error has no impact on performance, and the CAM contents are not changed as a result of the error. The data SRAMs are actually dual-port register files which will process both writes and reads on each clock cycle of the clock. The T8100 can process a read and write request from each CAM and two microprocessor requests during the time of one address comparison. Due to the fixed order of operations, the data SRAM cannot overflow or under- flow like the CAMs. The timing is shown in Figure 10. * As mentioned in Section 2.2.5 State Counter Operation, for each stream and time-slot value, the state counter goes through four functional states for each stream and time slot. These states are used to synchronize the CAMs, pipeline register files, data SRAMs, and microprocessor accesses just as they are used to synchronize local memory operations and the frame groups. (Microprocessor accesses to the memories are initiated asynchronously, though the actual microprocessor cycles are synchronous.)
2.3.2 CAM Operation and Commands (continued)
Figure 10. Simplified H-Bus State Timing, 65.536 MHz Clock
Lucent Technologies Inc. 33 Preliminary Data Sheet August 1998 H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100 tion (continued) A number of commands are available to control the CAMs. Connections can be made or broken, entry data can be searched for, individual locations may be read or cleared, or the CAMs can be reset. The address mode register (AMR) (see Section 2.1 Register/Mem- ory Maps) is used to issue the CAM control commands. Some commands require the use of the lower address register (LAR), and some use the IDR as a transfer reg- ister. The tags in each CAM’s associated register file refer- ence the storage location of the data being transferred, so each CAM/tag location also has control information. The three control bits are read-to/write-from data SRAM (i.e., a direction bit, located in the CAM and used during the comparison operations), a pattern mode enable, which bypasses the data SRAM and out- puts the tag directly into the specified time slot for writes to the bus, and an SRAM buffer select that con- trols the minimum delay or constant delay select, equivalent to the local memory’s selection of minimum or constant delay. In addition, the CAM carries a valid entry bit. This is an identifier for the status of the CAM (and corresponding register file) location. If the bit is low, as all validity bits are after a reset, then the location is available to be written into. When data is written into a location, then this bit is set, indicating that this is a valid entry. If spe- cific data is no longer valid, such as when a connection is broken, then the bit is cleared. The CAM commands make use of either one or two cycles. The two cycles are described pictorially in Fig- ure 11. The reader will note that matching and retrieval are actually separate cycles. The need for two cycles accounts for the requirement of the pipeline register files. Detailed descriptions of the commands follow: The basic make connection command is referred to as MKCn, where n is the CAM designator*. The MKCn uses two CAM cycles: first, the CAM is searched to determine where to find the next free location (as deter- mined by the validity bits), and during the second cycle, the next empty location is written into. The MKCn com- mand uses holding registers which convey the connec- tion information to the CAM and its associated register file. The three holding registers contain the lower con- nection address (i.e., time slot), the upper connection address (stream plus control bits), and the tag. An attempt to write to a full CAM (all 256 locations fully occupied) results in an overflow error flagged through the system error register, SYSERR (see Section 2.6 Error Registers). Note: A single MKCn command only specifies one half of a connection. The MKCn specifies the con- nection address and a pointer to the data mem- ory, but a second connection address and pointer to the same data memory location must also be provided for a complete connection. * The H-Bus CAM covering the 16 even-numbered H-Bus streams is designated E, the H-Bus CAM covering the 16 odd-numbered H- Bus streams is designated O, and the CAM that services the 16 local stream pairs is designated L.
Figure 11. Illustration of CAM Cycles
Lucent Technologies Inc. 35 Preliminary Data Sheet August 1998 H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100 tion (continued) If the user determines that a stream/time slot is no longer valid, then the validity bit may be cleared by pre- senting the connection address to the CAM and by using the BKCn, break connection, command. The connection that the user intends to break, which con- sists of the time slot, and the stream plus control bits, but not the tag, is transferred to the holding registers prior to issuing this command. This is a two-cycle com- mand: during the first cycle, the connection address is presented to the CAM to identify which physical loca- tion holds that connection address, and then, in the second cycle, the validity bit is cleared for the identified physical location. If there is a miss, it flags a no-match error through the underflow bit in SYSERR. Note: A complete connection break requires two BKCn commands, one for each half of the con- nection, as with the MKCn command. The clear location command, CLLn, is a one-cycle command. The LAR contains the physical address (i.e., the physical CAM location) to be cleared. When it is presented to the CAM, the validity bit is cleared, return- ing the location to an empty status (i.e., it becomes available for new make connection commands). The CLLn can also be regarded as the second cycle of a break connection command. CLLn is valuable if several outputs are driven from a common input (broadcast) and the user wishes to break one of the output connec- tions, but leave the others intact. When the physical location in the CAM is identified, either by software tracking or by use of the find entry command (later in this section), then the CLLn can be issued. If the user wishes to poll the CAM for its contents, then the RDCn or read CAM command can be used to query a particular location (0—255) in a specific block using the LAR for the location address. The contents of the CAM and tag location are transferred to the holding registers, and then the time slot, stream plus control, and tag are returned (in sequence) from three consec- utive IDR reads. The actual RDCn operation is one- cycle. The converse of the RDCn is the FENn, or find entry command. It can be thought of as the first cycle of a BKCn command. Only time slot and stream plus con- trol bits are necessary for identifying the location. The tag is not needed. The value returned to the IDR is the physical location of the entry in the CAM block, if it is found. If the entry is not found, then the underflow error bit in the SYSERR register will be set. FENn is a one- cycle command. RSCn is the reset CAM command, and this renders all locations in one CAM block invalid. This can be consid- ered a CLLn for all locations in the CAM. Two special resets are the RCH command, which resets only the holding registers, and the CI command, which resets all three CAM blocks and the holding registers. All resets are one-cycle.
2.3.3 H-Bus Access
There are 32 bidirectional pins available for accessing the H-Bus. The direction of the pins is selected by the CAM read and write bits. Data rates for the pins are selected in accordance with the H.100/H.110 specifica- tions. Unassigned time slots on the H-bus are 3-stated. Details about rate selection are provided below. Two bits of the 13-bit address are used to select the CAM block as indicated in Figure 9. The remaining 11 bits plus a read/write bit form a comparand that is stored in a CAM location.
3636 Lucent Technologies Inc. Preliminary Data Sheet August 1998H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100 tion (continued)
2.3.4 L-Bus Access
The input and output of the CAM have the appropriate links to the local stream pins so that the H-Bus streams may be routed to and from the local bus streams. The LBS register (Section 2.2.4 LBS: Local Stream Control, 0x0C) programs the local stream rates even if accessed by the CAMs. T o address the local bus CAM block, the two most significant address bits of the phys- ical address are set to the appropriate values as described in Figure 9. The other bits form the com- parand along with a read/write bit. When the CAM is outputting data to the local bus, it has priority over the local bus memory. In other words, if both the local bus and H-Bus access the same local stream and time slot, the H-Bus data memory will provide the actual data, not the local connection. Operating rates are selected in a manner similar to the local side. Two registers, HSH and HSL, shown below, define the operation of the 32 streams. Again, SGx refers to stream groups: HSH holds SGh—SGe where SGh programs streams 28—31, SGg programs streams 24—27, SGf programs streams 20—23, and SGe programs streams 16—19. HSL holds SGd—SGa where SGd programs streams 12—15, SGc programs streams 8—11, SGb programs streams 4—7, and SGa programs streams 0—3. SGn = 00, 3-state SGn = 01, 2.048 Mbits/s SGn = 10, 4.096 Mbits/s SGn = 11, 8.192 Mbits/s A quick summary: The CAMs and the pipeline register files operate as connection memories. The key CAM operation is based on 11 bits of stream and time slot plus 1 bit of read/ write in the CAM locations compared against the state counter which tracks the current stream and time slots (Section 2.2.5 State Counter Operation). Each H-Bus CAM is looking for matches on 16 of the 32 H-Bus streams, and the local CAM is looking for a match on 16 local inputs and 16 local outputs per time slot. Thirteen bits are required to cover the 5120 possible time slots, but the MSB, LSB combination is used to determine which H-Bus CAM is accessed: even H-Bus (0, 0), odd H-Bus (0, 1). The local H-Bus is accessed by selecting the upper 2 MSBs, both equal to 1. The CAM address can be thought of as following this for- mat: This format is rate independent. The CAM select field is part of the address mode register (AMR) for CAM com- mands (Section 2.1.3 Address Mode Register and Sec- tion 2.3.2 CAM Operation and Commands). Program- ming examples for setting up connections can be found in Section 3.2 Basic Connections.
2.4 Clocking Section
The clocking section performs several functions which are detailed in the following paragraphs. In general, when the T8100 is a bus master, it will have one or more companion devices which provide the basic clock extraction and jitter attenuation from a source (such as a trunk). As a slave, the T8100 can work independently of, or in conjunction with, external resources. Examples of different operating modes are provided in Appendix A. Refer to Figure 12 for a block diagram of the T8100 clocking section. When the T8100 is used as a bus master, an input clock of a tolerance of ±32 ppm is required. This can come from several sources. For example: ■ ±32 ppm crystal tolerance is the suggested value if either the DPLL is used or fallback to the oscillator is enabled while mastering the bus. Otherwise, a crys- tal with a lesser tolerance can be used. ■ If a crystal is not used, a 16.384 MHz (±32 ppm toler- ance or less) signal must be provided to the XTALIN pin, and XTALOUT should be left unconnected. ■ The L_REF inputs can also be used and must con- form to ±32 ppm in a bus master situation. SGh SGg SGf SGe SGd SGc SGb SGa CAM Select Field Time-Slot Field Stream Field 2 bits 7 bits 4 bits
2.4 Clocking Section (continued)
- The path for XT ALIN divide-by-4 is for fallback only.
Figure 12. Clocking Section
4 MHz
2 MHz
65.536 MHz
16.384 MHz
2.048 MHz
4.096 MHz
8.192 MHz
3838 Lucent Technologies Inc. Preliminary Data Sheet August 1998H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100 tion (continued)
2.4.1 Clock and NETREF Selection
The inputs to the T8100 clocking come from three selectors. The clock selector and frame selector oper- ate from a common set of selection options in register CKM (see Section 2.4.6 Clock Control Register Defini- tions for register details), where FRAMEA is selected along with clock C8A and FRAMEB is selected along with clock C8B. T ypically, one of the local references (LREF[0:7]) will be selected when the T8100 is operat- ing as a master, though the local oscillator is also avail- able. As a slave, the most common selections will be one of the bus types. Each bus type has a state machine associated with it for determining the frame sync. All clock inputs are sampled to check for proper switching. If the expected clock edge does not occur, and there is no switching on CT_NETREF for 125 µs, a bit corresponding to the errant clock is set in the CLK- ERR register (see Section 2.6 Error Registers for more details). NETREF can be created from one of the local references or from the oscillator independent of the clock generation.
2.4.2 Dividers and Rate Multipliers
The clock and NETREF selections are routed to divid- ers*. In the case of NETREF , the divider is usually used to reduce a bit rate clock to 8 kHz, so the most common divisors will be 1, 193 (1.544 MHz/8 kHz), and 256 (2.048 MHz/8 kHz), although a full range of values (from 1—256) is possi- ble. For the clock selector, the signal will most often be routed through the main divider when the T8100 is operating as a master or through the resource divider when operating as a slave. Both the main and resource dividers are fully programmable. The ultimate destination for the main or resource divider is intended to be PLL #1. PLL #1 accepts either a 2.048 MHz or 4.096 MHz input and will rate multiply up to 65.536 MHz. The divisor of the main or resource dividers is chosen in conjunction with the rate select of the PLL, i.e., a divisor which generates a 4.096 MHz output and a rate selection of x16, or a divisor which generates a 2.048 MHz output and a rate selection of x32. This provides a great deal of flexibility in adapting to a variety of (external) clock adapters and jitter atten- uators while acting as a master, as well as slaving to several bus types. A digital PLL that can rate multiply to either 2.048 MHz or 4.096 MHz from an 8 kHz source in the absence of an external clock adapter is also provided. PLL #1 can be bypassed for diagnostic purposes or if an external clock adapter is used that provides a high-speed output (65.536 MHz). The input to the DPLL is for an 8 kHz signal only. A second rate multiplier is provided for supporting T1 applications. It is optimized around either a 1.544 MHz or 3.088 MHz input rate which multiplies to 24.704 MHz and is then divided down to provide 50% duty cycle clocks of 12.352 MHz, though the direct 24.704 MHz is available as well. A bypass is provided so that an exter- nal clock can be buffered through the TCLK output. The internal oscillator or the various outputs derived from PLL #1 can also be selected for the TCLK output. * If the A clocks have been selected as the clock source through the CKM register (described in Section 2.4.6 Clock Control Register Definitions), then the CT_C8A is the signal sent to the main and resource dividers; likewise, selecting B clocks results in sending CT_C8B; the MVIP selection sends /C4; the H-MVIP selection sends the recovered /C16 (derived from differential inputs); select- ing SC2 sends SCLKX2 ; and SC4/8 sends SCLK to the dividers.
Lucent Technologies Inc. 39 Preliminary Data Sheet August 1998 H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100 tion (continued)
2.4.3 State Machines
The purpose of the state machines is to generate internal control signals for the remainder of the T8100 circuitry and to provide all bus clocks when operating as a master. The state machines operate from the
65.536 MHz clock generated by PLL #1, and they are
time referenced to the frame sync derived from the selected clock and frame inputs. As a master, the time sync is based on the T8100’s own generated frame. The dominant internal control signals are a noninverted 32.768 MHz clock, an inverted 16.384 MHz state clock, and a noninverted 122 ns wide sync pulse centered around the beginning of a frame. The memories are synchronized to the 65.536 MHz clock.
2.4.4 Bit Sliding (Frame Locking)
The T8100 generates its own frame signal based on the incoming clock and frame references and its gener- ated clock signals. When slaving, it is sometimes nec- essary to align the edges of this generated frame signal to the incoming frame reference. T o accomplish this, the T8100 will compare the referenced frames with the current state of its clock state machine, and if the difference exceeds one
65.536 MHz clock cycle, the entire stream will have a
fraction of a bit time removed from each frame; this is referred to as bit sliding. The process will repeat until the measurements fall within one clock cycle. The actual bit sliding will take place by reducing the gener- ated frame by one 65.536 MHz clock cycle at the beginning of the frame. This means that the frame edges will phase-align at the rate of approximately 15.26 ns per frame. The maximum phase difference is slightly less than one frame or 124.985 µs. Thus, it will require approximately 8000 frames, or 1 second, to phase-align the frame. This is also mean time interval error (MTIE) compliant; performing phase adjustment of 162 ns per 1.326 ms of total sample time. Refer to the MTIE specifications document (A TT 62411). The alternatives to bit sliding are snap alignment and no alignment. Snap alignment refers to an instanta- neous phase alignment, i.e., a reset at the frame boundary. This mode is common to other devices. If no alignment is chosen, the T8100’s generated frame is frequency-locked to the incoming frame sync, but not phase-aligned.
2.4.5 Clock Fallback
The following conditions must be met before fallback is initiated: ■ Fallback must be enabled in register CKS. ■ Failure of one or more of the clocks selected through the CKSEL bits in the CKM register. ■ All clocks which comprise the selection from CKSEL must be unmasked in register CKW (see Section 2.6 Error Registers). The T8100 contains a fallback register which enables a backup set of controls for the clock resources during a clock failure. In addition, a fallback state machine pro- vides some basic decision-making for controlling some of the clock outputs when the feature is enabled. While slaving to the bus, the primary course of action in fall- back is the swap between the A-clocks and B-clocks as the primary synchronization sources. A slave may become a master only under software control; i.e., there is no automatic promotion mechanism. As a mas- ter, the T8100 can detect its own failures and remove its clocks from the bus. If it detects a failure on the other main set (e.g., B master detects failures on the A mas- ter), then it can assume the role as the primary syn- chronization source by driving all compatibility clocks (H- MVIP and SC-Bus). Clock failures are flagged through the CLKERR1 and CLKERR2 registers (Sec- tion 2.6 Error Registers). Additional fallback details are discussed in relationship to the clock registers in the next section. The divide-by-4 block for XT ALIN, shown in Figure 12, is used only for fallback. See Figure 13 for a diagram of the basic state machine which controls the A, B, and C (compatibility) clocks.
2.4.5 Clock Fallback (continued)
Figure 13. A, B, and C Clock Fallback State Diagram
2.4.6 Clock Control Register Definitions
Table 39. CKM: Clocks, Main Clock Selection, 0x00 with an inversion selected from register CKP . A pictorial view of the various clocks may be seen in Section 4.6.1 Clock Alignment. P AE 7 Phase Alignment Enable.
2.4.6 Clock Control Register Definitions (continued)
Table 40. CKN: Clocks, NETREF Selections, 0x01 Note: When the NIO bit is high, general-purpose register (GPR), bits 6 and 7 are available. NRI 4 NRI inverts the output of the NETREF selector.
Table 41. CKP: Clocks, Programmable Outputs, 0x02
- MC-1 is a multichassis communication standard based on MVIP. The T8100 supports this standard.
C8IS 4 C8IS is used to invert the synchronization on C8A and C8B when they are selected for input. nals to be output on C8A and C8B (for supporting for either ECTF or MC-1* applications). CFW selects the output width of the compatibility frame.
Table 42. CKR: Clocks, Resource Selection, 0x03 CRS 7—6 The CRS[7:6] bits are used to select the input to PLL #1. P1B 5 P1B and P1R control PLL #1. P2B 3 P2B and P2R control PLL #2. SCS 1—0 The SCS[1:0] bits are used to program the outgoing SC-Bus compatibility signals.
Table 43. CKS: Clocks, Secondary (Fallback) Selection, 0x04 PLL #1 has been set for x16. If PLL #1 is set for x32, then use FCSEL = 8 kHz local reference, FRS = 10, and FTS = 10. FRS 7—6 FRS provides an alternate clock resource selection. FTS determines the basic fallback mode. FRS forces the clock resource selector to choose a new source for PLL #1. Note: The decode is the same as that of the CRS bits (in the clock resource register, CKR). FTS = 00, Fallback from main clock to the oscillator divided by 4* when main clock fails. tialization and diagnostic purposes only. FTS = 10, Fallback from main selection to secondary source (FCSEL).
2.6 Error Registers), then clocks are changed to the selection indicated by FCSEL, the A or B
SYSERR register will also note when a fallback has occurred. FF 3 FF is used as a test of the fallback, but can also be used as a software-initiated fallback.
Table 44. CK32 and CK10: Clocks, Locals 3, 2, 1, and 0, 0x05 and 0x06
2.4.7 CKMD, CKND, CKRD: Clocks, Main, NETREF,
one-half of a (selected) clock cycle in width. the binary equivalent of 192 which is 0xC0.
2.5 Interface Section
2.5.1 Microprocessor Interface
2.5 Interface Section (continued)
2.5.2 General-Purpose Register
2.4.6 Clock Control Register Definitions).
2.5.3 Framing Groups
Table 45. FRHA, Frame Group A High Address and Control, 0x21 Table 46. FRHB, Frame Group B High Address and Control, 0x23
4848 Lucent Technologies Inc.
2.5.3 Framing Groups (continued)
grammed to 2.048 MHz, the resolution is 0.125 of a bit. CT_C8 is starting its low-to-high transition.
4 MHz, and 2 MHz of the L_SC[3:0] clocks that occur in
sent from the FRLA [0x20] and FRHA [0x21] registers. see Figure 14 for a diagram of the selection options. Table 47. FRPH: Frame Group B, Programmed Output, High, 0x25 enabling the mode. T ype bits have no effect in the programmed modes.
Figure 14. Frame Group Output Options
5050 Lucent Technologies Inc.
2.6 Error Registers
and CKS should be programmed last. whether the failure is permanent or transient in nature. a transient clock can force a fallback. tion 2.1 Register/Memory Maps). Table 49. SYSERR: System Error Register, 0x2A ters but will not set the FBE flag in SYSERR.
7 CA => Reports failures on CT_C8A
6 CB => Reports failures on CT_C8B
5 CF => Reports failures on
4 C16 => Reports failures on /C16+ or
3 C42 => Reports failures on /C4 or C2
2 SC => Reports failures on SCLK
1 SC2 => Reports failures on SCLKX2
0 NR => Reports failures on
2.7 The JTAG Test Access Port
2.7.1 Overview of the JTAG Architecture
active-low signal that resets the circuit. value sampled on the rising edge of TCK controls the state transitions. The state diagram underlying the TAP controller is shown below. cal structure, and its different cell types is given in T able 51. nontargeted devices in board environments as defined by the standard.
2.7.2 Overview of the JTAG Instructions
The JT AG block supports the public instructions as shown in the table below. Table 50. T8100 JTAG Instruction Set
2.7 The JTAG Test Access Port (continued)
2.7.3 Elements of JTAG Logic
Table 51. T8100 JTAG Scan Register
66 I CK_3MHZIN
67 O SYSERR
68 O CLKERR
0 CC Controls cells 67:68
1 CC Controls cells 69:76
77 I RESTN
78 O RDY
79 I WRN
80 I RDN
81 I CSN
82 I ALE
83 I A0
84 I A1
44 CC Controls cells 85:88
97 I CK_4MHZIN
98 O PRIREFOUT
45 CC Controls cell 98
99 O TESTOUT1
100 O REFCLK1O
46 CC Controls cells 99, 100
101 Bdir FROMDJA T
43 CC Controls cell 101
102 Bdir TODJA T
42 CC Controls cell 102
41 CC Controls cells 103—108
63 CC Controls cells 109—120
64 CC Controls cells 121—132
133 Bdir C16N_MINUSA
134 Bdir C16N_PLUSA
135 Bdir C4N
136 Bdir C2
5 CC Controls cells 133—136
137 Bdir SCLKX2NA
7 CC Controls cell 137
138 Bdir SCLKA
6 CC Controls cell 138
139 Bdir CT_C8_BA
140 Bdir CT_FRAME_BNA
3 CC Controls cells 139—140
141 Bdir FRN_COMP A
4 CC Controls cell 141
142 Bdir CT_NETREF
8 CC Controls cell 142
143 Bdir CT_C8_AA
144 Bdir CT_FRAME_ANA
2 CC Controls cells 143—144
193 O XCS
0 CC Controls cell 193
210 O PMCTCLKO
65 CC Controls cell 65
Lucent Technologies Inc. 53 Preliminary Data Sheet August 1998 H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100 tion (continued)
2.8 Testing and Diagnostics
There are several testing operations available for the T8100: ■ JTAG ■ Forced output testing ■ Onboard diagnostics During manufacturing, the T8100 is run through stan- dard functional and electrical testing.
2.8.1 Testing Operations
JTAG is used primarily to test the array portion of the T8100. It will not provide coverage for the CAMs, regis- ter files, SRAMs, or PLLs. In JTAG, the manufacturer provides a drop-in control block and scan-chain which ties internal points to registers on the periphery of the T8100, which are, in turn, tied to the I/O pins. Serial bit patterns are shifted into the T8100 through the TDI pin, and the results can be observed at the I/O and at a cor- responding JT AG serial output, TDO. Since this JTAG conforms to the JTAG standard, the TDI and TDO can be linked to the JTAGs of other devices for systemic testing. The TTS pin must be low for JTAG operations to work. The TTS pin has an internal pull-down resistor that defaults the T8100 to JT AG operations. In forced output testing, the outputs are set to a particu- lar state to measure their dc parameters. This can also be used in applications for board-level diagnostics. Forced output testing is selected by setting the TTS (test type select) pin high. In this mode, the JTAG clock pin, TCK, will act as an input pin. All outputs will be enabled, and each output provides either an inverting or normal response to the input pin. Adjacent pins alternate inverting and normal function (i.e., a checker- board pattern).
2.8.2 Diagnostics
The T8100 has onboard diagnostic modes for testing the frame groups, SRAMs and CAMs, and some inter- nal structures. These are intended for testing some of the T8100 resources while it is in an application envi- ronment (rather than a manufacturing test environ- ment). The diagnostics allow critical internal nodes to be out- put through the frame groups, or to have the frame groups operated in special cyclical manner, or to pro- vide automatic filling of all memories (including CAMs) with one of four selected patterns. The diagnostics are activated and selected using three registers: DIAG1 [0x30], DIAG2 [0x31], or DIAG3 [0x32]. DIAG1 is used to select the frame group pins as either monitors for internal nodes or normal operation (i.e., as frame groups or programmed outputs). DIAG1 is also used to control the memory fill diagnostic. DIAG2 and DIAG3 modify the normal operation of the frame groups and the main state counter. Normally, the frame groups begin their cascade sequence when the state counter (i.e., the frame-synchronized master counter of the T8100) reaches a value equal to the frame group’s starting address. DIAG2 and DIAG3 allow the state counter to be modified for one of two dif- ferent tests.
5454 Lucent Technologies Inc. Preliminary Data Sheet August 1998H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100 tion (continued)
2.8 Testing and Diagnostics (continued)
2.8.2 Diagnostics (continued)
The three registers are presented in order below: The register fields are interpreted as follows: DFA—Diagnostics, Frame Pin Selects, Group A: DFn = 00, Normal operation DFn = 01, State counter bits [10:0] routed to frame group pins [10:0], pin 11 = L DFn = 10, Even CAM hit routed to pin 11, pin 10 has odd CAM hit, pins [9:0] have local data memory address DFn = 11, Pin 11 gets CUE error bit, pin 10 gets CUO error bit, pin 9 gets CUL error bit, pin 8 gets COE error bit, pins [5:0] get page pointers—
8 MHz read, 8 MHz write, 4 MHz read,
4 MHz write, 2 MHz read, and 2 MHz write
DFB—Diagnostics, Frame Pin Selects, Group B: DFn = 00, Normal operation DFn = 01, State counter bits [10:0] routed to frame group pins [10:0], pin 11 = L DFn = 10, CAM state register [1:0] indicating four sub- states, routed to pins [11:10], and local con- nection memory address routed to pins [9:0] DFn = 11, Pin 11 gets local CAM hit flag, and pins [10:0] get CAM state counter DMF—Diagnostics, Memory, Fill Test Enable: DMF = 0, Normal operation DMF = 1, Fill all memories with the pattern selected by DMP DMP—Diagnostics, Memory, Fill Test Pattern Select: DMP = 00, Checkerboard 0—even locations get 0x55, odd locations get 0xAA DMP = 01, Checkerboard 1—even locations get 0xAA, odd locations get 0x55 DMP = 10, Data locations equal address bits [7:0] (CAMs are filled with their physical address) DMP = 11, Data locations equal inverted address bits [7:0] DMD—Diagnostics, Memory, Done Indicator: This is a status bit which indicates that the chosen memory pattern has been written to all locations. Addi- tional writes to the memory are disabled and reads are enabled. This condition remains until the user clears this bit. DFC—Diagnostics, Frame Groups Cycle Test Mode: DFC = 0, Normal operation DFC = 1, Cycle test mode enabled; forces the frame groups to constantly cycle without waiting for a frame signal to synchronize the start. DSB—Diagnostics, State Counter, Break Carry Bits: DSB = 0, Normal operation DSB = 1, Breaks the carry bits between the subsec- tions of the state counter so that the state counter is operating as three counters run- ning in parallel. (This can be viewed on the frame pins using the DFn = 01 selection described above.) Status counter bits [0:3] and [4:7] run as modulo-16 counters, and bits [8:10] run as a modulo-8 counter. DXF—Diagnostics, External Frame Input: DXF = 0, Normal operation DXF = 1, Forces /FR_COMP to act as a direct input signal for T8100 framing. This effectively bypasses the internally generated frame sig- nal. The user is again cautioned since the external frame can operate asynchronously to the generated clocks if care is not taken. DSE—Diagnostics, State Counter, Enable Parallel Load: DSE = 0, Normal operation DSE = 1, Forces the state counter to load the value held in DSH and DSL and continuously cycle as a modulo-n counter where the n value is determined by (DSH and DSL). With the DSE pin high, the state counter is no longer syn- chronized to the frame signal. DSH—Diagnostics, State Counter, High Bits of Par- allel Load: DSH = State counter bits [10:8] DSL—Diagnostics, State Counter, Low Bits of Par- allel Load: DSL = State counter bits [7:0] DFA DFB DMF DMP DMD DFC DSB DXF (Res.) DSE DSH DSL
3 Using the T8100
3.1 Resets
3.1.1 Hardware Reset
A hardware reset utilizes the (active-low) RESET pin. by setting the appropriate bits high in the MCR register. and all registers are cleared to zero.
3.1.2 Software Reset
3.1.3 Power-On Reset
tion while the T8100 resets asynchronously. the PLLs. The long rise time provides some delay.
3.2 Basic Connections
Figure 15. External Connection to PLLs
5656 Lucent Technologies Inc.
3 Using the T8100 (continued)
3.2 Basic Connections (continued)
3.2.3 PC Board Considerations
Figure 16. Physical Connections for H.110
3.3 Using the LAR, AMR, and IDR for Con-
3.3.1 Setting Up Local Connections
be made to the address in the connection memory. 7 bits comprising time slot). and CKW registers should be programmed last. Table 52. Time-Slot Bit Decoding
2 Mbits/s
4 Mbits/s
8 Mbits/s
3.3 Using the LAR, AMR, and IDR for Connections (continued)
3.3.1 Setting Up Local Connections (continued)
Table 53. IDR: Indirect Data Register, Local Connections Only of the registers and memory contents. slot which corresponds to the connection memory location. Figure 17. Local-to-Local Connection Programming and stream LSB) is routed to the time slot instead of data. and constant delay settings. CHE 4 Enables the time-slot connection; a low in this bit forces 3-state during the time slot. Address 3—0 All 4 bits are used for the stream address of the desired data memory location.
3.3.2 Setting Up H-Bus Connections
Table 54. IDR: Indirect Data Register, H-Bus Connections Only Address 4—0 All 5 bits are used for the stream address of the desired data memory location. of bits which are necessary to establish a connection. the LAR is not required for setting up the connection. contains only three control bits. sary for identifying a connection.
3.3.2 Setting Up H-Bus Connections (continued)
Figure 18. CAM Programming, H-Bus-to-Local Connection
Figure 18. CAM Programming, H-Bus-to-Local Connection (continued)
62 Lucent Technologies Inc. Preliminary Data Sheet August 1998H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100
3.3.3 Programming Examples
;All programming examples included are in a pseudoassembler format. ;The basic commands used are the “move direct” and “move indirect.” ;A move direct command is indicated by the letters “MD” followed by ;the register name, then the data. Similarly, a move indirect command ;is indicated by the letters “MI” followed by the register name, then by ;data or another register reference (the register may not be indirect). ;The semicolon delineates comments. Direct data is followed by the ;letter “h” for Hex and “b” for binary. ;*****EXAMPLE #1 - Set Up Clocks, Local Bus, H-Bus, and Framers MD,AMR,00h ;Define control space ;all specific register names are equivalent ;to the LAR addresses (from Table 11) ;Main Clock Register MD,IDR,0C2h ;Load IDR with values for bit slider on, slave mode, ;and synced to ECTF Bus A Clocks MI,CKM,IDR ;The data in IDR is moved into CKM via the LAR register. ;NETREF Registers MD,IDR,88h ;Set up NETREF from Local Reference 0, 2.048 MHz bit clock in, divided value ;value out (i.e., 8 kHz), enable the DJAT connections MI,CKN,IDR ;Move the data to CKN MD,IDR,0FFh ;Set up NETREF divider with divide-by-256 MI,CKND,IDR ;Move the data to CKND ;Programmable Clocks MD,IDR,26h ;This selects the oscillator for the TCLKO, A Clock outputs off, and ;driving ECTF B Clocks MI,CKP,IDR ;Move the data ;**Clock Resources MD,IDR,40h ;Synced to bus so select Resource divider, x16 on PLL #1 & x8 PLL #2, SC Clocks off MI,CKR,IDR ;Make it so MD,IDR,01h ;Set up Resource divider with divide-by-2 for 4 MHz signal into PLL #1 MI,CKRD,IDR ;Move the data to divider
Lucent Technologies Inc. 63 Preliminary Data Sheet August 1998 H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100
3.3.3 Programming Examples (continued)
;Secondary Controls (Fallback) MD,IDR,35h ;Enable ECTF Fallback: Become the new A Clock master on A Clock failure, ;synchronizes to a bit clock on local reference 1, but requires the main divider ;with external input (assumes a CLAD is between the divider and 4MHzIn). MI,CKS,IDR ;Move the data to CKS MD,IDR,0FFh ;Set up Main divider with divide-by-256 MI,CKMD,IDR ;Move the data to divider ;Local Clocks MD,IDR,0E4h ;Local Selected Clock 3 gets inverted 8.192 MHz, LSC2 gets MI,CK32,IDR ;Move it to CK32 MD,IDR,80h ;LSC1 is high & LSC0 is low MI,CK10,IDR ;Move it to CK10 MD,IDR,30h ;8 Streams at 8 Mbits/s MI,LBS,IDR ;Define input streams per IDR MD,IDR,0AAh ;Define H-Bus Streams 0 - 15 for 4 Mbits/s MI,HSL,IDR ;Do it MD,IDR,0FFh ;Define H-Bus Streams 16-31 for 8 Mbits/s MI,HSH,IDR ;Engage MD,IDR,00h ;This sequence sets up Group A MI,FRLA,IDR ; to start coincident MI,FRLB,IDR ; with the Frame MI,FRPH,IDR ; boundary and Group B MD,IDR,0F0h ; to start halfway through MI,FRHA,IDR ; the Frame. The Groups MD,IDR,0F4h ; operate in normal framing mode MI,FRHB,IDR ; at 8 Mbits/s and are Double Byte wide. ;Note: FRPH sets up the correct routing. ;*******Connect the T8100 to the outside world MD,MCR,0Eh ; Enable H-Bus Streams & Clock, Local Streams, local ; Clocks including Framers
64 Lucent Technologies Inc. Preliminary Data Sheet August 1998H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100 ;*****EXAMPLE #2 - Setting up Local Connections ; Use 8 Mbits/s rate set up from Example #1... ; Send data from Stream 7/Time Slot 60 to Stream 0/Time Slot 2 ; The data is coming from Data Location Stream 07h, Time Slot 3Ch, and is ; being accessed by Connection Memory Location Stream 00h, Time Slot 02h ; in the next frame (unframed operation). MD,LAR,1Dh ;Set up lower address, i.e., Time Slot 29 MD,AMR,43h ; Set up upper address bits (Stream 3), and point to the ; the Time Slot field of the connection memory MI,IDR,07h ;Put a “7” in the Time Slot field of connection location 3,29 ;Syntactically, “MI,IDR,data” is a special case since IDR is not the final recipient of the data MD,AMR,53h ;Maintain the same upper address, but get ready to load the ; remaining connection info (upper bits + control) MI,IDR,0001_1110b ;This decodes as follows: XCS bit low, pattern mode off ; (not set), frame bit low, time slot enabled, and stream = 1110b (14) ;*****EXAMPLE #3 - Setting up H-Bus Connections ; Use rate set up from Example #1... ; Send data from Stream 14/Time Slot 7 of the H.100 bus to Stream 3/Time Slot 29 ; on the Local side. The data is coming in at 4 Mbits/s from E-CAM, and is sent ; out at 8 Mbits/s to through L-CAM. We’re using Data Memory location 49 to hold ; the actual data. LAR is not used for the CAM connection setups; it is used for ; reading specific CAM locations or writing and reading the associated Data ; Memory Locations. MD,AMR,0B0h ;Point to the Time-Slot holding register MI,IDR,07h ;This is the Time-Slot value (7) for the H-Bus address MD,AMR,0B1h ;Point to the upper bits of the connection MI,IDR,000_01110b :Set up a write into data memory from ECTF bus, ; disable pattern mode, minimum delay, ; and set stream number equal to 01110b (14). MD,AMR,0B2h ;Point to tag field MI,IDR,31h ;Use location 49 of the associated Data RAM to store the data MD,AMR,0E0h ;Write to next free location in the Even CAM MI,IDR,0E0h ;The command is executed with the indirect to IDR which ;uses the same command value as in the AMR.
Lucent Technologies Inc. 65 Preliminary Data Sheet August 1998 H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100 ;Optional: Test CAM Busy bit TEST: MD,ACC,MCR ;Move MCR contents into (host’s) accumulator (for example) AND,01h ;Logical AND, i.e., mask off all but LSB of the MCR register JNZ TEST ;If the LSB is zero (not busy), continue, else jump back and ;retest CONTINUE: MD,AMR,0B0h ;Point to the Time-Slot holding register MI,IDR,1Dh ;This is the Time-Slot value (29) for the Local address MD,AMR,0B1h ;Point to the upper bits of the connection MI,IDR,100_00011b :Set up a read from data memory to Local pins, ; disable pattern mode, minimum delay, and set ; stream number equal to 00011b (3). MD,AMR,0C2h ;Point to tag field MI,IDR,31h ;Use location 49 of the associated Data RAM to store the data MD,AMR,0E3h ;Write to next free location in the Local CAM MI,IDR,0E3h ;The command is executed with the indirect to IDR ;CAM Busy bit can be tested here
3.2.4 Miscellaneous Commands
These commands (i.e., 0x70, 0xF8, all reset commands in the AMR register) require two writes: first the value is written to the AMR register; then the same value is written to the IDR register. After writing to the IDR register, the command will be executed.
66 Lucent Technologies Inc. Preliminary Data Sheet August 1998H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100
4 Electrical Characteristics
4.1 Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.
4.2 Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance = 1500Ω , capacitance = 100 pF) is widely used and therefore can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters: Description Symbol Min Max Unit Supply Voltage V DD — 3.6 V XTALIN and XTALOUT Pins — V SS VDD V Voltage Applied to I/O Pins — V SS – 0.5 V DD + 3.4 V Operating T emperature: 208-pin SQFP 217-pin BGA −40 Storage T emperature T stg –55 125 °C HBM ESD Threshold Voltage Device Rating T8100 2500 V
4 Electrical Characteristics (continued)
4.3 Crystal Oscillator
Table 55. Crystal Oscillator Table 56. Alternative to Crystal Oscillator
4.4.1 Electrical Drive Specifications—CT_C8 and /CT_FRAME
Table 57. Electrical Drive Specifications—CT_C8 and /CT_FRAME VDD = 3.3 and VSS = 0.0 unless otherwise specified. CT_C8 and /CT_FRAME signals, though this is not explicitly stated as a part of the H.100 Specification.
Table 58. dc Electrical Characteristics, All Other Pins VDD = 3.3 and VSS = 0.0 unless otherwise specified.
- Circuit simulation indicates a worst-case current of 450 mA. This parameter is not tested in production.
4.6.1 Clock Alignment
Figure 19. Clock Alignment
4.6.2 Frame Diagram
Note: Bit 1 is the MSB. Bit 8 is the LSB. MSB is always transmitted first in all transfers. Figure 20. Frame Diagram
4.6.3 Detailed Timing Diagram
Figure 21. Detailed Timing Diagram
1 BIT CELL
- The rise and fall times are determined by the edge rate in V/ns. A maximum edge rate is the fastest rate at which a clock transitions.
- Measuring conditions, data lines: VTH (threshold voltage) = 1.4 V , VHI (test high voltage) = 2.4 V , VLO (test low voltage) = 0.4 V , input signal
- When RESET is active, every output driver is 3-stated.
- tC8P minimum and maximum are under free-run conditions assuming ±32 ppm clock accuracy.
- Noncumulative, tC8P requirements still need to be met.
- Measured at the transmitter.
- Measured at the receiver.
delay and maximum data cable delay are worst-case numbers based on electrical simulation.
- tDOZ and tZDO apply at every time-slot boundary.
- F (phase correction) results from PLL timing corrections.
4.6.5 Detailed Clock Skew Diagram
Figure 22. Detailed Clock Skew Diagram
- Assumes A and B masters in adjacent slots.
- When static skew is 10 ns and, in the same clock cycle, each clock performs a 10 ns phase correction in opposite directions, a maximum
skew of 30 ns will occur during that clock cycle.
- Meeting the skew requirements in T able 10 and the requirements of Section 2.3 H-Bus Section could require the PLLs generating CT_C8
to have different time constants when acting as primary and secondary clock masters.
4.6.7 Reset and Power On
Table 61. Reset and Power On
Table 62. ac Electrical Characteristics, Local Streams, and Frames Note: LDO7 is the MSB, LDO0 is the LSB. MSB is always transmitted first in all transfers. Figure 23. ac Electrical Characteristics, Local Streams, and Frames
8.192 Mbits/s
4.096 Mbits/s
2.048 Mbits/s
4.8.1 Microprocessor Access Intel Multiplexed Write and Read Cycles
For Intel write and read cycles, when RDY is low, wait-states are inserted. RDY is brought high when tIACC is met. This is true for both read and write cycles. Figure 24. Microprocessor Access Intel Multiplexed Write Cycle Figure 25. Microprocessor Access Intel Multiplexed Read Cycle
4.8.2 Microprocessor Access Motorola Write and Read Cycles
Figure 26. Microprocessor Access Motorola Write Cycle Figure 27. Microprocessor Access Motorola Read Cycle
4.8.3 Microprocessor Access Intel Demultiplexed Write Cycle
Figure 28. Microprocessor Access Intel Demultiplexed Write Cycle Figure 29. Microprocessor Access Intel Demultiplexed Read Cycle Table 63. Microprocessor Access Timing (See Figure 24 through Figure 29.)
78 Lucent Technologies Inc. Preliminary Data Sheet August 1998H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100
5 Outline Diagram
5.1 208-Pin Square Quad Flat Package (SQFP) 5-2196(F) Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Lucent T echnologies Microelectronics Group Account Manager. 156 105 30.60 ± 0.20 157208 53 104 28.00 ± 0.20 28.00 ± 0.20 30.60 ± 0.20 PIN #1 IDENTIFIER ZONE
4.10 MAX
0.08 3.40 ± 0.20 SEATING PLANE 0.25 MIN0.50 TYP DETAIL BDETAIL A 0.50/0.75 GAGE PLANE SEATING PLANE
1.30 REF
0.25 DETAIL A DETAIL B 0.17/0.27 0.10 M 0.090/0.200
Lucent Technologies Inc. 79 Preliminary Data Sheet August 1998 H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100
5 Outline Diagram (continued)
5.2 217-Pin Ball Grid Array (PBGA) 5-6562(F)
6 Ordering Information
Device Part No. Description Package Comcode T8100- - -SC Ambassador H.100 Interface 208-Pin SQFP 108125873 T8100- - -BAL Ambassador H.100 Interface 217-Pin BGA 108194184 SEATING PLANE SOLDER BALL0.60 ± 0.10 0.20 A B C D E F G H J K L M N P R T U 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 16 SPACES @ 1.27 = 20.32 A1 BALL CORNER
16 SPACES
@ 1.27 = 20.32 0.75 ± 0.15 PWB MOLD COMPOUND 23.00 ± 0.20 23.00 ± 0.20 19.50 +0.70 –0.00 19.50 +0.70 –0.00A1 BALL IDENTIFIER ZONE SIDE VIEW BOTTOM VIEW TOP VIEW
8080 Lucent Technologies Inc. Preliminary Data Sheet August 1998H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100 Appendix A. Application of Clock Modes In the diagrams that follow, four clock modes are illus- trated using Figure 12, the T8100 clocking diagram, as the basis of each illustration. The key signal paths are shown in solid lines, and unused paths with narrow dashes. T wo examples also indicate fallback paths. A register profile (programming values) for all four exam- ples is on the last page of the appendix. In Figure 30, the T8100 is operating as a bus master, so it must link to either an 8 kHz recovered frame refer- ence or 2.048 MHz recovered bit clock reference from the E1 framers. In addition, the T8100 can provide one of the basic resource clocks to run the framers. In this case, the TCLK is selecting the T8100’s 16.384 MHz oscillator. The framers are returning a
2.048 MHz bit clock which is selected through the clock
selector. It is not divided, so the main divider is bypassed (divide-by-1), the clock is smoothed through an external DJA T , and the smooth 2.048 MHz signal is routed to PLL #1 through the clock resource selector. PLL #1 multiplies the 2.048 MHz input up to
65.536 MHz which, in turn, runs the rest of the T8100,
all bus clocks, and the local clocks (if desired). If the T8100 is not providing NETREF generation, then the NETREF from the bus is routed to the local clocks via the NETREF internal/external selector. Since the NETREF generation resources are not needed here, the TODJA T and FROMDJA T pins are free for use with the general-purpose register as bits GP6 and GP7, respectively. Figure 31 shows the T1 version of a bus master. In this scenario, a 1.544 MHz recovered bit clock from the framers is routed to a multiclock adapter (with built-in jitter attenuation) which produces smooth 4.096 MHz and 3.088 MHz outputs. The 4.096 MHz is routed up to PLL #1 for a times-16 rate multiplication to 65.536 MHz. This drives the bus clocks and the local clocks. The smooth 3.088 MHz is also rate multiplied times 8. This produces a 24.704 MHz clock. This is divided back down to produce a smooth 12.352 MHz which is fed back to the framers. (PLL outputs produce one tightly bound edge and one with significant phase jitter. Dividing a higher-frequency signal based on its clean edge produces a lower frequency with two clean edges.) Figure 32 shows an H- MVIP slave arrangement for E1. In this example, the C16 differential clocks provide the main source for PLL #1. The 16.384 MHz signal is divided down to 4.096 MHz and then rate multiplied up to 65.536 MHz for driving the rest of the T8100. The frame sync for the state machines is derived from the /FRAME and C16 inputs as well as the state informa- tion provided by C2 and /C4. Note: The bit slider is enabled for a smooth phase alignment between the internal frame and the frame sync. The bus clocks are not driven, but the local clocks are available. A path for NETREF is shown as well, also based on a 2.048 MHz input. The signal is smoothed and then divided down to an 8 kHz signal via the NETREF divider. The internal oscillator is again chosen for routing to the framers via TCLK. Figure 33 shows an H- MVIP slave for T1. This is identi- cal to the E1 case with regard to slaving, and a NETREF path is illustrated in this example, too. The NETREF divider has been changed to accommodate the 1.544 MHz bit clock rate. The primary difference is the use of the C16 clock through the main divider to generate a 2.048 MHz signal which can be routed off- chip and adapted to a 1.544 MHz signal using an exter- nal device. The 1.544 MHz signal is returned to the T8100 via the 3MHzIN for rate multiplication up to 24.704 MHz and then division to a clean 12.352 MHz signal which is routed to the framers via TCLK.
Figure 30. E1, CT Bus Master, Compatibility Clock Master, Clock Source = 2.048 MHz from Trunk
Figure 31. T1, CT Bus Master, Compatibility Clock Master, Clock Source = 1.544 MHz from Trunk
1.544 MHz
Figure 32. E1, Slave to CT Bus, Clock Source Is Either a 16 MHz or a 4 MHz or a 2 MHz and Frame, NETREF
2 MHz DJAT
Figure 33. T1, Slave to CT Bus, Clock Source Is Either a 16 MHz or a 4 MHz or a 2 MHz and Frame, NETREF
1.5 MHz DJAT
Table 64. Clock Register Programming Profile for the Four Previous Examples is covered by registers CKM, CKR, CKMD, and CKRD. Note: CKR does include an example of running PLL #1 at X32 for E1 master and X16 for all other cases. (uninitialized clocks, for example) from changing the operating mode.
8686 Lucent Technologies Inc. Preliminary Data Sheet August 1998H.100/H.110 Interface and Time-Slot Interchanger Ambassador T8100 Appendix B. Minimum Delay and Con- stant Delay Connections B.1 Connection Definitions Forward A forward connection is defined as one Connection in which the output (to) time slot has a greater value than the input (from) time slot, or put another way, the delta between them is positive. Reverse A reverse connection is defined as one Connection in which the input (from) time slot has a lesser value than the output (to) time slot, and the delta between them is negative. So, for example, going from TS(1) to TS(38) is a for- ward connection, and the TSΔ is +37, but going from TS(38) to TS(1) is a reverse connection, with a TSΔ of –37: where TSΔ = TS(to) – TS(from). Similarly, a delta can be introduced for streams which will have a bearing in certain exceptions (discussed later): STR Δ = STR(to) – STR(from) There is only one combination which forms a TSΔ of +127 or –127: TS Δ = TS(127) – TS(0) = +127, and but there are two combinations which form TSΔs of +126 or –126: TS Δ = TS(127) – TS(1) = TS(126) – TS(0) = +126, and there are three combinations which yield +125 or –125, and so on. The user can utilize the TSΔ to control the latency of the resulting connection. In some cases, the latency must be minimized. In other cases, such as a block of connections which must maintain some relative integ- rity while crossing a frame boundary, the required latency of some of the connections may exceed one frame (>128 time slots) to maintain the integrity of this virtual frame. The T8100 contains several bits for controlling latency. Each connection has a bit which is used for selecting one of two alternating data buffers. These bits are set in the local connection memory for local switching or in the tag register files of the CAM section for H-Bus switching. There are also 2 bits in the CON register, address 0x0E, which can control the buffer selection on a chip-wide basis. Bit 1 of the register overrides the individual FME bits. Bit 0 becomes the global, chip- wide, FME setting.
to solve for either TS(to) or TS(from). Frame(n) to TS(1) of Frame(n + 2). Figure 34. Constant Delay Connections, CON[1:0] = 0X
8888 Lucent Technologies Inc. delays with the double buffering. Table 65. Table of Special Cases (Exceptions) main function by dashed lines. 0 and a STRΔ of 0. This is a stream and time-slot switching to itself. Loopback on the local bus, e.g., LDO_0 to LDI_0 is permissible. Figure 35. Minimum Delay Connections, CON[1:0] = 0X
Forward Connections: L = TSΔ (3 ≤ TSΔ ≤ 127). 0 of CON for the FME value in Table 65. Figure 36. Mixed Minimum/Constant Delay Connections, CON[1:0 = 10]
rights under any patent accom pany the sale of any such product(s) or inform ation. Ambassador is a trademark of Lucent Technologies Inc. Co pyright © 1998 Lucent Technologies Inc. Figure 37. Extended Linear (Mixed Minim um/Constant) Delay, C ON[1:0] = 11