T80C5112-S3REV

T80C5112_00 ATMEL | Alldatasheet

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Rev. B - November 10, 2000 1 Preliminary T80C5112 8-bit Microcontroller with A/D converter 1. Description The T80C5112 is a high performance ROM/OTP version of the 80C51 8-bit microcontroller. The T80C5112 retains all the features of the standard 80C51 with 8 Kbytes ROM/OTP program memory, 256 bytes of internal RAM, a 8-source , 4-level interrupt system, an on-chip oscillator and two timer/counters. The T80C5112 is dedicated for analog interfacing applications. For this, it has an 10-bit, 8 channels A/D converter and a five channels Programmable Counter Array. In addition, the T80C5112 has a Hardware Watchdog Timer with its own low power oscillator, a versatile serial channel that facilitates multiprocessor communication (EUART) with an independent baud rate generator, a SPI serial bus controller and a X2 speed improvement mechanism. The X2 feature allows to keep the same CPU power at a divided by two oscillator frequency. The fully static design of the T80C5112 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The T80C5112 has 3 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the peripherals are still operating. In the quiet mode, the A/D converter only is operating. In the power-down mode the RAM is saved and all other functions are inoperative. Two oscillators source, crystal and RC, provide a versatile power management. The T80C5112 is proposed in 48/52 pin count packages with Port 0 and Port 2 (address / data busses). 2. Features

• 80C51 Compatible
• Five I/O ports
• Two 16-bit timer/counters
• 256 bytes RAM
• 8Kbytes ROM/OTP program memory with 64 bytes encryption array and 3 security levels.
• High-Speed Architecture
• 33MHz @ 5V (66 MHz equivalent)
• 20MHz @ 3V (40 MHz equivalent)
• X2 Speed Improvement capability (6 clocks/ machine cycle)
• 10-bit, 8 channels A/D converter
• Hardware Watchdog Timer with integrated low power oscillator (20mA) and Reset-Out
• Programmable I/O mode: standard C51, input only, push-pull, open drain.
• Asynchronous port reset, Power On Reset
• Full duplex Enhanced UART with baud rate generator
• SPI, master/slave mode
• Dual system clock
• Crystal or ceramic oscillator with hardware set up (32 KHz or 33/40 MHz)
• Internal RC oscillator (12 MHz)
• Programmable prescaler
• Active oscillator during reset defined by hardware set up
• Timer 0 subclock mode for Real Time Clock.
• Programmable counter array with High speed output, Compare / Capture, Pulse Width Modulation and Watchdog timer capabilities
• Interrupt Structure with:
• 8 Interrupt sources,
• 4 interrupt priority levels
• Power Control modes:
• Idle mode
• Power-down mode
• Power-off Flag, Power fail detect, Power on Reset
• Power supply: 2.7 to 5.5V
• Temperature ranges: Commercial (0 to 70C) and Industrial (-40 to 85 C), optionnal extented
• Package:LQFP48 (body 7*7*1.4mm), PLCC52

2 Rev. B - November 10, 2000 Preliminary T80C5112 3. Block Diagram Timer 0 INT RAM 256 RxD TxD XTAL2 XTAL1 EUART CPU Timer 1 INT1 CtrlINT0 C51 CORE (2) (3) (2) (3) Port 1 Port 3 Parallel I/O PortsP1 IB-bus Vpp Watch Dog Vss Vcc (2)(2) (1): Alternate function of Port 1 (2): Alternate function of Port 3 ROM /OTP

8 K *8

(1)(1) (3) (3): Alternate function of Port 4 Port 4 (2) (2) (2) PCA MISO (3) MOSI (3) SPSCK (3) SPI RC Osc BRG Port 0 Port 2 SS (3) EA Vref generatorALE PSEN RST

• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR, AUXR1
• I/O port registers: P0, P1, P2, P3, P4, P1M1, P1M2, P3M1, P3M2, P4M1, P4M2
• Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1
• Serial I/O port registers: SADDR, SADEN, SBUF, SCON, BRL, BDRCON
• Power and clock control registers: CKCON0, CKCON1, OSCCON, CKSEL, PCON, CKRL
• Interrupt system registers: IE, IE1, IPL0, IPL1, IPH0, IPH1
• WatchDog Timer: WDTRST, WDTPRG
• SPI: SPCON, SPSTA, SPDAT
• PCA: CCAP0L, CCAP1L, CCAP2L, CCAP3L, CCAP4L, CCAP0H, CCAP1H, CCAP2H, CCAP3H, CCAP4H, CCAPM0, CCAPM1, CCAPM2, CCAPM3, CCAPM4, CL, CH, CMOD, CCON
• ADC: ADCCON, ADCCLK, ADCDATH, ADCDATL, ADCF

Table 1. SFR Addresses and Reset Values

4 Rev. B - November 10, 2000 Preliminary T80C5112 5. Pin Configuration *NIC: No Internal Connection 21 22 26 252423 29 2827 30 31 6 5 4 3 2 7 15 2 5 1 50 49 47 46 45 44 4348 42 41 40 3938 P4.7/AIN7 RST P4.4/AIN4/MISO P4.6/AIN6/SPSCK P4.5/AIN5/MOSI EA P1.0/WR P1.1/RD P4.2/AIN2/SS P4.1/AIN1/T1 P4.3/AIN3/INT1 P3.0/RxD P0.0 P3.1/TxD P0.1 P0.5 P0.2 P0.3 P0.6 P1.2/ECI P0.7P2.1 VPP P3.6 XTAL2/P3.5 XTAL1/P3.4 ALE PSEN P3.3/T0 P3.2/INT0 P1.5/CEX2 P1.6/CEX3 PLCC52 13 14 18 171615 21 2019 22 23 LQFP48 P1.3/CEX0 25P1.4/CEX1 P4.0/AIN0 32 33 48 47 P0.4 P1.7/CEX4 P4.7/AIN7 RST P4.4/AIN4/MISO P4.6/AIN6/SPSCK P4.5/AIN5/MOSI EA P1.0/ WR P1.1/RD P4.2/AIN2/SS P4.1/AIN1/T1 P4.3/AIN3/INT1 P4.0/AIN0 VREF VSS + AVSS P2.7 P2.6 P2.5 P2.4 P2.3 V2.2 VCC + AVCC P2.0 P3.7 P2.0 VSS AVSS P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 AVCC + VCC P3.7 VPP NIC P3.1/TxD P3.0/RxD P0.0 P0.5 P0.1 P0.2 P0.6 P1.2/ECI P0.7 P1.3/CEX0 P0.4 VREF P2.1 P0.3 7*7*1.4 mm P3.5 XTAL2 XTAL1 ALE PSEN P3.3/T0 P3.2/INT0 P1.5/CEX2 P1.6/CEX3 P1.4/CEX1 P1.7/CEX4 P3.4 P3.6

Rev. B - November 10, 2000 5 Preliminary T80C5112 MNEMONIC PIN NUMBER TYPE NAME AND FUNCTIONLQFP PLCC V SS XX I Ground: 0V reference. V CC XX I Power Supply: This is the power supply voltage for normal, idle and power- down operation. AV SS XI Analog Ground: 0V reference. AV CC I Analog Power Supply: This is the power supply voltage for normal and idle operation of the A/D VREF X X I VREF : A/D converter positive reference input. VPP X X I Vpp : Programming Supply Voltage: This pin also receives the 12V programming pulse which will start the EPROM programming and the manufacturer test modes. P1.0-P1.7 X X I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. Alternate functions for Port 1 include: I/O WR (P1.0): External data memory write strobe I/O RD (P1.1):External data memory readstrobe I/O ECI (P1.2):External Clock for the PCA I/O CEX0 (P1.3): Capture/Compare External I/O for PCA module 0 I/O CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 I/O CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 I/O CEX3 (P1.6): Capture/Compare External I/O for PCA module 3 I/O CEX4 (P1.7): Capture/Compare External I/O for PCA module 4 P3.0-P3.7 XX I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. P3.4 and P3.5 are valid I/O pins only when the T80C5112 is using the internal RC oscillator, OSCB. P3.6 is an input only pin Port 3 also serves the special features of the 80C51 family, as listed below. I/O RXD (P3.0): Serial input port I/O TXD (P3.1): Serial output port I/O INT0 (P3.2):External interrupt 0 I/O T0 (P3.3):Timer 0 external input I/O XTAL1 (P3.4): Input to the inverting oscillator amplifier and input to the internal clock generator circuits, selected by hardware set upa I/O XTAL2 (P3.5): Output from the inverting oscillator amplifier, selected by hardware set up P4.0-P4.7 X X I/O Port 4: Port 4 is an 8-bit bidirectional I/O port. Each bit can be set as pure CMOS input or as push-pull output. Port 4 is also the input port of the Analog to digital converter and used for oscillator and reset. I/O AIN0 (P4.0):A/D converter input 0 I/O AIN1 (P4.1):A/D converter input 1 T1: Timer 1 external input I/O AIN2 (P4.2):A/D converter input 2 SS: Slave select input of the SPI controller

6 Rev. B - November 10, 2000 Preliminary T80C5112 I/O AIN3 (P4.3):A/D converter input 3 INT1: External interrupt 1 I/O AIN4 (P4.4):A/D converter input 4 MISO: Master IN, Slave OUT of the SPI controller I/O AIN5 (P4.5):A/D converter input 5 MOSI: Master OUT, Slave IN of the SPI controller I/O AIN6 (P4.6):A/D converter input 6 SPSCK: Clock I/O of the SPI controlle I/O AIN7 (P4.7):A/D converter input 7 P0.0-P0.7 X X I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them ßoat and can be used as high impedance inputs. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. P2.0-P2.7 X X I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. RST X X I RST: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to V SS permits a power-on reset using only an external capacitor to VCC. If the hardware watchdog reaches its time-out, the reset pin becomes an output during the time the internal reset is activated. ALE X X O Address Latch Enable:Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE can be disabled by setting SFRÕs AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches. PSEN X X O Program Store ENable: The read strobe to external program memory. When executing code from the external program memory,PSEN is activated twice each machine cycle, except that twoPSEN activations are skipped during each access to external data memory.PSEN is not activated during fetches from internal program memory. EA X X I External Access Enable:EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 1FFFH . If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 1FFFH. EA must be held low for ROMless devices. If security level 1 is programmed,EA will be internally latched on Reset. XTAL1 X I XTAL1 : Input to the inverting oscillator amplifier and input to the internal clock generator circuits, selected by hardware set upb XTAL2 X O XTAL2 : Output from the inverting oscillator amplifier, selected by hardware set up a. Hardware set up : +Configuration bits programmed with the code for ROM version +Configuration bits for EPROM version b. Hardware set up : +Configuration bits programmed with the code for ROM version +Configuration bits for EPROM version

Rev. B - November 10, 2000 7 Preliminary T80C5112 6. Clock system 6.1. Overview The T80C5112 oscillator system provides a reliable clocking system with full mastering of speed versus CPU power trade off. Several clocks sources are possible:

• External clock input
• High speed crystal or ceramic oscillator
• Low speed crystal oscillator
• Integrated high speed RC oscillator
• The low speed RC oscillator of the watchdog is a backup clocking source when no clock are selected in active or idle modes. The selected clock source can be divided by 2-512 before clocking the CPU and the peripherals. When X2 function is set, the CPU need 6 clock periods per cycle. Active oscillator at reset is defined by bits in a configuration byte programmed on an OTP programmer or by metal mask. Clocking is controlled by several SFR registers : OSCON, CKCON0, CKCON1, CKRL. 6.2. Blocks description The T80C5112 includes the following oscillators:
• Crystal oscillator, with two possible gains optimized for 32 kHz or 33 MHz.
• Integrated high speed RC oscillator, with typical frequency of 12 MHz
• Integrated low speed, low power RC oscillator, with typical frequency of 200 kHz; this oscillator is used to clock the hardware watchdog and as back up oscillator when the CPU receives no clock signal in active or idle modes. 6.2.1. Crystal oscillator : OSCA The crystal oscillator uses two external pins, XTAL1 for input and XTAL2 for output. XT_SP in configuration byte allows to select between two possible gains optimized for 32 kHz or 33 MHz. Both crystal and ceramic resonnators can be used. OSCAEN in OSCCON register is an enable signal for the crystal oscillator or the external oscillator input. When the crystal oscillator is not selected, XTAL1 can be used as a standard C51 I/O port, and X2 can be used as a standard C51 I/O port. 6.2.2. Integrated high speed RC oscillator : OSCB The high speed RC oscillator do not need any external component; its typical frequency is 12 MHz. Note that the on chip oscillator has a +-25% frequency tolerance and for that reason may not be suitable for use in some applications. OSCBEN in OSCCON register is an enable signal for the high speed RC oscillator.

8 Rev. B - November 10, 2000 Preliminary T80C5112 6.2.3. Integrated low speed, low power RC oscillator : OSCC The low speed, low power RC oscillator is used to clock the hardware watchdog and do not need any external component; its typical frequency is 200 kHz. This oscillator is also used as back up oscillator when the CPU receive no clock signal in active or idle modes. RCLF_OFF is the configuration bit used to switch on or off the low speed RC oscillator. Note that the on chip oscillator has a +-25% frequency tolerance and for that reason may not be suitable for use in some applications. 6.2.4. Clock selector CKS bit in CKS register is used to select from crystal to RC oscillator. OSCBEN bit in OSCCON register is used to enable the RC oscillator. OSCAEN bit in OSCCON register is used to enable the crystal oscillator or the external oscillator input. If both oscillators are disabled, the low speed oscillator, OSCC is used as a backup source for the CPU and the peripherals. This feature provides a stand alone low frequency mode which can be activated when needed. 6.2.5. Clock prescaler Before supplying the CPU and the peripherals, the main clock is divided by a factor to 2 to 512, as defined by the CKRL register. The CPU needs from 12 to 256*12 clock periods per instruction. This allows:

• To accept any cyclic ratio to be accepted on XTAL1 input.
• To reduce the CPU power consumption. The X2 bit allows to bypass the clock prescaler ; in this case, the CPU need only 6 clock periods per machine cycle. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%

Figure 1. Functional block diagram

• An hardware RESET select Xtal_Osc or RC_Osc depending on the RST_OSC configuration bit 6.4.2. Functional modes : 6.4.2.1. NORMAL MODES :
• CPU and Peripherals clock depend on the software selection using CKCON0, CKCON1, CKSEL and CKRL registers
• CKS bit selects either Xtal_Osc or RC_Osc
• CKRL register determines the frequency of the selected clock, unless X2 bit is set. In this case the prescaler/divider is not used, so CPU core needs only 6-clock period per machine cycle. According to the value of the peripheral X2 individual bit, each peripherals need 6 or 12 clock period per instructions.
• It is always possible to switch dynamicaly by software from Xtal_Osc to RC_Osc, and vice versa by changing CKS bit, a synchronization cell allowing to avoid any spike during transition. Xtal2 Xtal1 PwdRC WD clock PwdOsc Ckrl Reload 8-bit Prescaler-Divider ResetB OscOut Xtal_Osc RC_Osc XT_SP OSCBEN OSCAEN CKS RCLF_Osc RCLF_OFF Mux Filter RCLF_OFF OSCA OSCB OSCC CkIdle Ck Idle Cpu clock Peripherals clock Pwd CkOut CkAdc Quiet OSCBEN OSCAEN :128 A/D clock Sub Clock Timer 0 clock

10 Rev. B - November 10, 2000 Preliminary T80C5112 6.4.2.2. IDLE MODES :

• IDLE modes are achieved by using any instruction that writes into PCON.0 sfr
• IDLE modes A and B depend on previous software sequence, prior to writing into PCON.0 register :
• IDLE MOD E A : Xtal_Osc is running (OSCAEN = 1) and selected (CKS = 1)
• IDLE MODE B : RC_Osc is running (OSCBEN = 1) and selected (CKS = 0)
• The unused oscillator Xtal_Osc or RC_Osc can be stopped by software by clearing OSCAEN or OSCBEN respectively.
• Exit from IDLE mode is acheived by Reset, or by activation of an enabled interrupt.
• In both case, PCON.0 is cleared by hardware.
• Exit from IDLE modes will leave the ocillators control bits OSCAEN, OSCBEN and CKS unchanged. 6.4.2.3. POWER DOWN MODES :
• POWER DOWN modes are achieved by using any instruction that writes into PCON.1 sfr
• Exit from POWER DOWN mode is acheived either by an harware Reset, by an external interruption.
• By RST signal : The CPU will restart in the mode defined by RST_OSC.
• By INT0 or INT1 interruptions, if enabled. The ocillators control bits OSCAEN, OSCBEN and CKS will not be changed, so the selected oscillator before entering into Power-down will be activated. 6.4.2.4. Prescaler Divider :
• An hardware RESET selects the prescaler divider :
• CKRL = FFh: internal clock = OscOut / 2 (Standard C51 feature)
• X 2=0 ,
• SEL_OSC signal selects Xtal_Osc or RC_Osc, depending on the value of the RST_OSC configuration bit.
• After Reset, any value between FFh down to 00h can be written by software into CKRL sfr in order to divide frequency of the selected oscillator:
• CKRL = 00h : minimum frequency = OscOut / 512
• CKRL = FFh : maximum frequency = OscOut / 2 PD IDLE CKS OSCBEN OSCAEN RCLF _OFF Selected Mode Comment 0 0 1 X 1 X NORMAL MODE A OSCA: XTAL clock X X 1 X 0 1 INVALID no active clock 0 0 1 0 0 0 RESCUE MODE OSCC: Low speed RC clock active 0 0 0 1 X X NORMAL MODE B, OSCB: high speed RC clock X X 0 0 X 1 INVALID 0 0 0 0 0 0 RESCUE MODE OSCC: Low speed RC clock active 0 1 1 X 1 X IDLE MODE A The CPU is off, OSCA supplies the peripherics 0 1 0 1 X X IDLE MODE B The CPU is off, OSCB supplies the peripherics 1XX X 1 0 POWER DOWN MODE with WD The CPU and peripherics are off, but OSCC is still running for WD

1 X X X X 1 TOTAL POWER DOWN

The CPU is off, OSCA and OSCB are stopped OSCC is stopped

Rev. B - November 10, 2000 11 Preliminary T80C5112

• A software instruction which set X2 bit desactivates the precaler/divider, so the internal clock is either Xtal_Osc or RC_Osc depending on SEL_OSC bit. 6.5. Timer 0 : Clock Inputs

Figure 2. Timer 0 : Clock Inputs SCLKT 0=1: Timer 0 uses the special Sub Clock as clock input. CKRL prescaler must be set to FF (division factor 2) in order to assure a proper count on Timer 0. (RTC) function. The power consumption will be very low as the CPU is in idle mode at 32 KHz most of the time.

Description

7:5 - Program memory lock bits See chapter program memory for the deÞnition of these bits.. SCLKT0 CkIdle :6 T0 pin Sub Clock C/T OSCCON TMOD Gate INT0 TR0 Timer 0 Control

12 Rev. B - November 10, 2000 Preliminary T80C5112 Initial value after erasing : 1111 111X 6.6.2. Clock control register The clock control register is used to define the clock system behavior OSCCON - Clock Control Register (86h) Reset Value = 0XXX X0 "RST_OSC" "RST_OSC" b Not bit addressable

4 RST_OSC Selected oscillator at reset

This bit is used to deÞne the value of some bits controlling the oscillator activity at reset: 1: The crystal oscillator is sectected and active 0: The RC oscillator is selected; it is also active if the WDRC is inactive.

3 XT_SP Crystal oscillator speed

This bit is used to deÞne the performance of the crystal oscillator. 1: High speed, up to 33 MHz 0: Low speed, low power, optimised for 32 kHz.

2 EXT_RST External Reset

This bit deÞnes the behavior of the P3.6/RST pin 1: P3.6/RST is the reset pin 0: P3.6/RST is an input pin

1 OSCC_OFF Control for watchdog RC oscillator

This bit is used to switch the watchdog RC oscillator and the watchdog source 1: WDRC oscillator is off; the watchdog is clocked by the main oscillator. 0: WDRC oscillator is on and clock the watchdog 0 - Reserved The value read from this bit is indeterminate. Do not reset this bit. 7 6 5 4 3 2 1 0 - - - - - SCLKT0 OSCBEN OSCAEN Bit Number Bit Mnemonic The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. SCLKT0 Sub Clock Timer0 Cleared by software to select T0 pin Set by software to select T0 Sub Clock

1 OSCBEN Enable RC oscillator

This bit is used to enable the high speed RC oscillator 0: The oscillator is disabled 1: The oscillator is enabled.

0 OSCAEN Enable crystal oscillator

This bit is used to enable the crystal oscillator 0: The oscillator is disabled 1: The oscillator is enabled. Bit Number Bit Mnemonic

Rev. B - November 10, 2000 13 Preliminary T80C5112 6.6.3. Clock selection register The clock selectionl register is used to define the clock system behavior CKSEL - Clock Selection Register (85h) Reset Value = XXXX XXX "RST_OSC" b Not bit addressable 6.6.4. Clock prescaler register This register is used to reload the clock prescaler of the CPU and peripheral clock. CKRL - Clock prescaler Register (97h) Reset Value = 1111 1111b Not bit addressable 6.6.5. Clock control register This register is used to control the X2 mode of the CPU and peripheral clock. Table 2. CKCON0 Register The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 - Reserved The value read from this bit is indeterminate. Do not set this bit.

0 CKS Active oscillator selection

This bit is used to select the active oscillator 1: The crystal oscillator is selected 0: The high speed RC oscillator is selected. 7 6 5 4 3 2 1 0 M Bit Number Bit Mnemonic 7:0 CKRL 0000 0000b: Division factor equal 512 1111 1111b: Division factor equal 2 M: Division factor equal 2*(256-M)

14 Rev. B - November 10, 2000 Preliminary T80C5112 CKCON0 - Clock Control Register (8Fh) Reset Value = X000 0000b Not bit addressable Table 3. CKCON1 Register 6 WdX2 Watchdog clock(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 5 PcaX2 Programmable Counter Array clock(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 4 SiX2 Enhanced UART clock (Mode 0 and 2)(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 3 - Reserved 2 T1X2 Timer1 clock(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle 1 T0X2 Timer0 clock(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle

0 X2 CPU clock

Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2" bits. 7 6 5 4 3 2 1 0 - - - - - - BRGX2 SPIX2 Bit Number Bit Mnemonic 0 SPIX2 SPI clock(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle

Rev. B - November 10, 2000 15 Preliminary T80C5112 7. Reset and Power Management 7.1. Introduction The power monitoring and management can be used to supervise the Power Supply (VDD) and to start up properly when T80C5112 is powered up. It consists of the features listed below and explained hereafter:

• Power on Reset
• Power-Fail reset
• Power-Off flag
• Idle mode
• Power-Down mode
• Reduced EMI mode All these features are controlled by several registers, the Power Control register (PCON) and the Auxiliary register (AUXR) detailed at the end of this chapter. AUX register not available on all versions. 7.2. Functional description Figure 3 shows the block diagram of the possible sources of microcontroller reset.

Figure 3. Reset sources Notes:RST pin available only on 48 and 52 pins versions. Notes:RST pin available only on LPC versions. RST/Vpp pin provided the EXT_RST bit of the configuration byte is high. This module set the POF bit vhen Vcc is below the memory data retention voltage. The behavior or POR and PFD is shown on Figure 4. The Power-Fail Detector (PFD) is controlled by RSTD bit in PCON register. The PFD is disabled upon reset. below VRST for at least 60 ns. If the power supply rises again over VRST+ (2), the internal reset completes after 24 CPU clock periods. If RSTD is reset, the power supply monitoring is disabled.

1. The internal reset is not propagated on the RST pin.

2 See AC/DC section for the specifications of Vrst. Figure 4. Power Fail Reset timing diagram allows to detect this condition. POF is set by hardware during a reset which follows a power-up or a power-fail. accuracy. It is recommended to clear and not to take in account the POF value after exit from a power down mode with VDD reduction.

18 Rev. B - November 10, 2000 Preliminary T80C5112 7.6. Registers 7.6.1. PCON: Power configuration register Table 4. PCON Register The value of port pins in the different operating modes is shown on the figure below. Table 5. Pin Conditions in Special Operating Modes

7 SMOD1 Double Baud Rate bit

Set to double the Baud Rate when Timer 1 is used and mode 1, 2 or 3 is selected in SCON register.

6 SMOD0

When cleared, read/write accesses to SCON.7 are to SM0 bit and read/write accesses to SCON.6 are to SM1 bit. When set, read/write accesses to SCON.7 are to FE bit and read/write accesses to SCON.6 are to OVR bit. SCON is Serial Port Control register.

5 RSTD

Reset Detector Disable bit Clear to disable the Power-Fail detector. Set to enable the Power-Fail detector.

4 POF

Set by hardware when VDD rises above V RET+ to indicate that the Power Supply has been set off. Must be cleared by software.

3 GF1 General Purpose flag 1

One use is to indicate wether an interrupt occurred during normal operation or during Idle mode.

2 GF0 General Purpose flag 0

One use is to indicate wether an interrupt occurred during normal operation or during Idle mode. 1 PD Power-Down Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Power-Down mode. If IDL and PD are both set, PD takes precedence.

0 IDL

Cleared by hardware when an interrupt or reset occurs. Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence. Mode Program Memory Port 1 pins Port 3 pins Port 4 pins Reset DonÕt care Weak High Weak High Weak High Idle Internal Data Data Data Power-Down Internal Data Data Data

signal can be disabled by setting AO bit. Table 6. AUXR Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.

0 AO ALE Output bit

Clear to restore ALE operation during internal fetches. Set to disable ALE operation during internal fetches.

generate an internal reset. It will also drive an output RESET HIGH pulse at the emulator RST-pin. used. In this case the WDT will also use the low speed crystal oscillator. WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) or 1024 (1FFFH) and this will reset the device. be executed within the time required to prevent a WDT reset. Table 7. WDTRST Register Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.

Table 8. WDTPRG Register resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reseted during the interrupt service routine. WDT just before entering powerdown.

7 T4 Reserved

3 T0 WDT overßow select bit

2 S2 WDT Time-out select bit 2

1 S1 WDT Time-out select bit 1

0 S0 WDT Time-out select bit 0

22 Rev. B - November 10, 2000 Preliminary T80C5112 8.1.1.2. Power down and OSCC active In Power Down mode the low speed RC oscillator never stops. If the WDT is active before entering power down, the T80C5112 will be reseted once and will start executing the program code. The software may then decide to leave the WDT inactive. If the high speed RC oscillator is selected at reset, this mode may be used to periodically awake the T80C5112 and check for an external event while keeping the average consumption at a very low level. There are 2 methods of exiting Power Down mode: by a hardware or watchdog reset or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power Down is exited with hardware or watch dog reset, servicing the WDT should occur as it normally should whenever the T80C5112 is reset. Exiting Power Down with an interrupt is significantly different. As the WDT and interrupt are asynchronous events, the WDT may overflow within a few states of exiting of powerdown. To limit the probability of such an event, it is suggested that the WDT be reseted during the interrupt service routine. 8.1.1.3. Idle mode In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the T80C5112 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode.

At least 39 pins of the T80C5112 may be used as I/Os when a two-pin external oscillator. Table 9. Number of available I/O versus pin number open drain, and input only. Two configuration registers for each port choose the output type for each port pin. Table 10. Port Output Configuration settings using PxM1 and PxM2 registers pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. to overpower the weak pull-up and take the voltage on the port pin below its input threshold. pull-up turns on for a brief time, two CPU clocks, in order to pull the port pin high quickly. Then it turns off again. The quasi-bidirectional port configuration is shown in Figure 5.

Figure 5. Quasi-Bidirectional Output bidirectional mode. The open drain port configuration is shown in Figure 6. Figure 6. Open Drain Output

2 CPU

26 Rev. B - November 10, 2000 Preliminary T80C5112 9.3. Registers Table 11. P1M1 Register Table 12. P1M2 Register Table 13. P3M1 Register Table 14. P3M2 Register Table 15. P4M1 Register 7 : 0 P1M1.x Port Output configuration bit See Table 10. for conÞguration deÞnition 7 6 5 4 3 2 1 0 Bit Number Bit Mnemonic 7 : 0 P1M2.x Port Output configuration bit See Table 10. for conÞguration deÞnition 7 6 5 4 3 2 1 0 Bit Number Bit Mnemonic 7 : 0 P3M1.x Port Output configuration bit See Table 10. for conÞguration deÞnition 7 6 5 4 3 2 1 0 Bit Number Bit Mnemonic 7 : 0 P3M2.x Port Output configuration bit See Table 10. for conÞguration deÞnition 7 6 5 4 3 2 1 0

Rev. B - November 10, 2000 27 Preliminary T80C5112 Reset value 0000 0000 Table 16. P4M2 Register 7 : 0 P4M1.x Port Output configuration bit See Table 10. for conÞguration deÞnition 7 6 5 4 3 2 1 0 Bit Number Bit Mnemonic 7: 0 P4M2.x Port Output configuration bit See Table 10. for conÞguration deÞnition

1. Dual Data Pointer Register Ddptr

The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. DPS = AUXR1/bit0 (See Table 17.) that allows the program code to switch between them (Refer to Figure 9). Figure 9. Use of Dual Pointer

Table 17. AUXR1: Auxiliary Register 1 value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. pointer and the other one as a "destination" pointer. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.

0 DPS Data Pointer Selection

30 Rev. B - November 10, 2000 Preliminary T80C5112 ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added 00A2 AUXR1 EQU 0A2H 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST

0008 LOOP:

0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.

Figure 12. UART Timings in Modes 2 and 3 feature is enabled (SM2 bit in SCON register is set). the CPU is not interrupted by command frames addressed to other devices. deviceÕs address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address. register in mode 0 has no effect). flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be1111 1111b.

Rev. B - November 10, 2000 33 Preliminary T80C5112 The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a donÕt-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g.1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a donÕt care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g.1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g.1111 0001b). 11.2.2. Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as donÕt-care bits, e.g.: SADDR 0101 0110b SADEN 1111 1100b Broadcast =SADDR OR SADEN 1111 111Xb The use of donÕt-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A: SADDR 1111 0001b SADEN11111010b Broadcast 1111 1X11b, Slave B: SADDR 1111 0011b SADEN11111001b Broadcast 1111 1X11B, Slave C: SADDR= 1111 0010b SADEN11111101b Broadcast 1111 1111b For slaves A and B, bit 2 is a donÕt care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. 11.2.3. Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses areXXXX XXXXb(all donÕt-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. 11.3. Baud Rate Selection for UART for mode 1 and 3 The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers.

Rev. B - November 10, 2000 35 Preliminary T80C5112

• for UART Example of computed value when X2=1, SMOD1=1, SPD=1 Example of computed value when X2=0, SMOD1=0, SPD=0 The baud rate generator can be used for mode 1 or 3 (refer to figures 13 ), but also for mode 0 for both UARTs, thanks to the bit SRC located in BDRCON register (Table 20) 11.4. UARTs registers SADEN - Slave Address Mask Register for UART (B9h) Reset Value = 0000 0000b SADDR - Slave Address Register for UART (A9h) Reset Value = 0000 0000b Baud Rates FXTAL = 16.384 MHz FXTAL = 24MHz BRL Error (%) BRL Error (%) 115200 247 1.23 243 0.16 57600 238 1.23 230 0.16 38400 229 1.23 217 0.16 28800 220 1.23 204 0.16 19200 203 0.63 178 0.16 9600 149 0.31 100 0.16 4800 43 1.23 - - Baud Rates FOSC = 16.384 MHz FOSC = 24MHz BRL Error (%) BRL Error (%) 4800 247 1.23 243 0.16 2400 238 1.23 230 0.16 1200 220 1.23 202 3.55 600 185 0.16 152 0.16 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Baud_Rate = 2SMOD1 x 2X2 x FXTAL 2 x 2 x 6(1-SPD) x 16 x [256 - (BRL)] (BRL) = 256 - 2SMOD1 x 2X2 x FXTAL 2 x 2 x 6(1-SPD) x 16 x Baud_Rate

36 Rev. B - November 10, 2000 Preliminary T80C5112 SBUF - Serial Buffer Register for UART (99h) Reset Value = XXXX XXXXb BRL - Baud Rate Reload Register for the internal baud rate generator, UART UART(9Ah) Reset Value = 0000 0000b 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Table 18. SCON Register

7 FE Framing Error bit (SMOD0=1) for UART

Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. Refer to SM1 for serial port mode selection.

6 SM1 Serial port Mode bit 1 for UART

5 SM2 Serial port Mode 2 bit / Multiprocessor Communication Enable bit for UART

Clear to disable multiprocessor communication feature. should be cleared in mode 0.

4 REN Reception Enable bit for UART

Clear to disable serial reception. Set to enable serial reception. 3 TB8 Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3 for UART. Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit.

2 RB8 Receiver Bit 8 / Ninth bit received in modes 2 and 3 for UART

Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.

1 TI Transmit Interrupt flag for UART

Clear to acknowledge interrupt.

0 RI Receive Interrupt flag for UART

Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 11. and Figure 12. in the other modes.

Table 19. PCON Register Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesnÕt affect the value of this bit.

7 SMOD1 Serial port Mode bit 1 for UART

Set to select double baud rate in mode 1, 2 or 3.

6 SMOD0 Serial port Mode bit 0 for UART

Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register.

5 RSTD Reset Detector Disable Bit

4 POF Power-Off Flag

Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.

3 GF1 General purpose Flag

Cleared by user for general purpose usage. Set by user for general purpose usage.

2 GF0 General purpose Flag

Cleared by user for general purpose usage. Set by user for general purpose usage.

1 PD Power-Down mode bit

Cleared by hardware when reset occurs. Set to enter power-down mode.

0 IDL Idle mode bit

Clear by hardware when interrupt or reset occurs.

Table 20. BDRCON Register The value read from this bit is indeterminate. Do not set this bit.

4 BRR

Clear to stop the internal Baud Rate Generator. Set to start the internal Baud Rate Generator.

3 TBCK

Clear to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator.

2 RBCK

Clear to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator.

1 SPD

Clear to select the SLOW Baud Rate Generator. Set to select the FAST Baud Rate Generator.

0 SRC

Clear to select FOSC /12 as the Baud Rate Generator (FOSC /6 in X2 mode). Set to select the internal Baud Rate Generator for UARTs in mode 0.

1. Serial Port Interface (SPI)

the MCU and peripheral devices, including other MCUs.

• Full-duplex, three-wire synchronous transfers
• Master or Slave operation
• Eight programmable Master clock rates
• Serial clock with programmable polarity and phase
• Master Mode fault error flag with MCU interrupt capability
• Write collision flag protection 12.3. Signal Description Figure 15 shows a typical SPI bus configuration using one Master controller and many Slave peripherals. The bus is made of three wires connecting all the devices:

Figure 15. Typical SPI bus signal to a Slave. A byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB)last.

3 Slave 3

signal to the Master. A byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last. lines. It is driven by the Master for eight clock cycles which allows to exchange one byte on the serial lines. be selected at a time by the Master for a transmission. (SPSTA) to prevent multiple masters from driving MOSI and SCK (See Error conditions). A high level on theSS pin puts the MISO line of a Slave SPI in a high-impedance state.

• The device is configured as a Master and the SSDIS control bit in SPCON is set. This kind of configuration can be found when only one Master is driving the network and there is no way that theSS pin will be pulled low. Therefore, the MODF flag in the SPSTA will never be set1.
• The Device is configured as a Slave with CPHA and SSDIS control bits set2. This kind of configuration can happen when the system comprises one Master and one Slave only. Therefore, the device should always be selected and there is no raison that the Master uses the SS pin to select the communicating Slave device. 12.3.5. Baud rate In Master mode, the baud rate can be selected from a baud rate generator which is controled by three bits in the SPCON register: SPR2, SPR1 and SPR0. The Master clock is chosen from one of seven clock rates resulting from the division of the internal clock by 2, 4, 8, 16, 32, 64 or 128, or an external clock. Table 21 gives the different clock rates selected by SPR2:SPR1:SPR0:

Table 21. SPI Master baud rate selection

1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA = Õ0Õ because in this mode, theSS is used to start the transmission.

000 F CkIdle /2 2

001 F CkIdle /4 4

010 F CkIdle /8 8

011 F CkIdle/16 16

100 F CkIdle /32 32

101 F CkIdleH /64 64

110 F CkIdle /128 128

111 External clock Output of BRG

Figure 17. Full-Duplex Master-Slave Interconnection Status register (SPSTA) with the SPIF bit set, and then reading the SPDAT. established again, the data present in the SPDAT is resent. the transmission is complete. In a Slave SPI module, data enters the shift register under the control of the SCK from the Master SPI module.

1. A Slave SPI must complete the write to the SPDAT (shift register) at least one bus cycle

already in the shift register from the previous transmission. should be identical for the Master SPI device and the communicating Slave device.

1. The SPI module should be configured as a Master before it is enabled (SPEN set). Also the Master SPI should be configured before the Slave SPI.
2. The SPI module should be configured as a Slave before it is enabled (SPEN set).
3. The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed.
4. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = Õ0Õ).

the actual mode of the device. MODF is set to warn that there may have a multi-master conflict for system control.

• An SPI receiver/error CPU interrupt request is generated.
• The SPEN bit in SPCON is cleared. This disable the SPI.
• The MSTR bit in SPCON is cleared. When SS DISable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set when theSS signal becomes Õ0Õ. However, as stated before, for a system with one Master, if theSS pin of the Master device is pulled low, there is no way that another Master is attempting to drive the network. In this case, to prevent the MODF flag from being set, software can set the SSDIS bit in the SPCON register and therefore making the SS pin as a general purpose I/O pin. Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set, followed by a write to the SPCON register. SPEN Control bit may be restored to its original set state after the MODF bit has been cleared. 12.4.3.2. Write Collision (WCOL) A Write COLlision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done during a transmit sequence. WCOL does not cause an interruption, and the transfer continues uninterrupted. Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an access to SPDAT. 12.4.3.3. Overrun Condition An overrun condition occurs when the Master device tries to send several data bytes and the Slave devise has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read of the SPDAT returns this byte. All others bytes are lost. This condition is not detected by the SPI peripheral. 12.4.4. Interrupts Two SPI status flags can generate a CPU interrupt requests:

Table 22. SPI Interrupts bit generates transmitter CPU interrupt requests. of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt requests.

Figure 21. SPI Interrupt Requests Generation describes in the following paragraphs.

• Selects one of the Master clock rates,
• Configure the SPI module as Master or Slave,
• Selects serial clock polarity and phase,
• Enables the SPI module,
• Frees theSS pin for a general purpose Table 23 describes this register and explains the use of each bit:

Table 23. Serial Peripheral Control Register

7 SPR2 RW Serial Peripheral Rate 2

6 SPEN RW

5 SSDIS RW

4 MSTR RW

3 CPOL RW

2 CPHA RW

• Data transfer complete
• Write collision
• Inconsistent logic level onSS pin (mode fault error) Table 24 describes the SPSTA register and explains the use of every bit in the register: Reset Value= 00X0XXXXb

Table 24. Serial Peripheral Status and Control register

1 SPR1 RW

0 SPR0 RW

7 SPIF R

Set by hardware to indicate that the data transfer has been completed.

6 WCOL R

Set by hardware to indicate that a collision has been detected.

4 MODF R

approved by a clearing sequence.

places data directly into the shift register. No transmit buffer is available in this model. A Read of the SPDAT returns the value located in the receive buffer and not the content of the shift register. Table 25. Serial Peripheral Data Register SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no on-going exchange.

• Do not change SPR2, SPR1 and SPR0
• Do not change CPHA and CPOL
• Do not change MSTR
• Clearing SPEN would immediately disable the peripheral
• Writing to the SPDAT will cause an overflow 7 6 5 4 3 2 1 0 R7 R6 R5 R4 R3 R2 R1 R0

Rev. B - November 10, 2000 49 Preliminary T80C5112 13. Programmable Counter Array PCA The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/ counter which serves as the time base for an array of five compare/ capture modules. Its clock input can be programmed to count any one of the following signals:

• Oscillator frequency ¸ 12 (¸ 6 in X2 mode)
• Oscillator frequency¸ 4( ¸ 2 in X2 mode)
• Timer 0 overflow
• External input on ECI (P1.2) Each compare/capture modules can be programmed in any one of the following modes:
• rising and/or falling edge capture,
• software timer,
• high-speed output, or
• pulse width modulator. Module 4 can also be programmed as a watchdog timer (See Section "PCA Watchdog Timer", page 58). When the compare/capture modules are programmed in the capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt vector. The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins are listed below. If the port is not used for the PCA, it can still be used for standard I/O. The PCA timer is a common time base for all five modules (See Figure 22). The timer count source is determined from the CPS1 and CPS0 bits in theCMOD SFR (See Table 26) and can be programmed to run at:
• 1/12 the oscillator frequency. (Or 1/6 in X2 Mode)
• 1/4 the oscillator frequency. (Or 1/2 in X2 Mode)
• The Timer 0 overflow.
• The input on the ECI pin (P1.2). PCA component External I/O Pin 16-bit Counter P1.2 / ECI 16-bit Module 0 P1.3 / CEX0 16-bit Module 1 P1.4 / CEX1 16-bit Module 2 P1.5 / CEX2 16-bit Module 3 P1.6 / CEX3 16-bit Module 4 P1.7 / CEX4

Figure 22. PCA Timer/Counter Table 26. CMOD: PCA Counter Mode Register idle Mode. CIDL = 1 programs it to be gated off during idle. WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. active value will be 1. The value read from a reserved bit is indeterminate. CPS1 PCA Count Pulse Select bit 1. CPS0 PCA Count Pulse Select bit 0. CPS1 CPS0 Selected PCA input. 0 0 Internal clock f osc/12 ( Or fosc/6 in X2 Mode). 0 1 Internal clock f osc/4 ( Or fosc/2 in X2 Mode). interrupt. ECF = 0 disables that function of CF.

The CMOD SFR includes three additional bits associated with the PCA (See Figure 22 and Table 26).

• The CIDL bit which allows the PCA to stop during idle mode.
• The WDTE bit which enables or disables the watchdog function on module 4.
• The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows. The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module (Refer to Table 27).
• Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this bit.
• Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software.
• Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software.

Table 27. CCON: PCA Counter Control Register The watchdog timer function is implemented in module 4 (See Figure 25). can only be cleared by software. by software to turn the PCA counter off.

• Not implemented, reserved for future use.

active value will be 1. The value read from a reserved bit is indeterminate.

Figure 23. PCA Interrupt System

• 16-bit Capture, positive-edge triggered,
• 16-bit Capture, negative-edge triggered,
• 16-bit Capture, both positive and negative-edge triggered,
• 16-bit Software Timer,
• 16-bit High Speed Output,
• 8-bit Pulse Width Modulator. In addition, module 4 can be used as a Watchdog Timer. Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (See Table 28). The registers contain the bits that control the mode that each module will operate in.
• The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module.
• PWM (CCAPMn.1) enables the pulse width modulation mode.
• The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module's capture/compare register.
• The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module's capture/compare register.
• The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition.
• The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. Table 29 shows the CCAPMn settings for the various PCA functions. CF CR CCON 0xD8CCF4 CCF3 CCF2 CCF1 CCF0 Module 4 Module 3 Module 2 Module 1 Module 0 ECF PCA Timer/Counter ECCFn CCAPMn.0CMOD.0 IE.6 IE.7 To Interrupt priority decoder EC EA

Table 28. CCAPMn: PCA Modules Compare/Capture Control Registers Table 29. PCA Module Modes (CCAPMn Registers) active value will be 1. The value read from a reserved bit is indeterminate. ECOMn Enable Comparator. ECOMn = 1 enables the comparator function. CAPPn Capture Positive, CAPPn = 1 enables positive edge capture. CAPNn Capture Negative, CAPNn = 1 enables negative edge capture. register causes the CCFn bit in CCON to be set, flagging an interrupt. register causes the CEXn pin to toggle.

Table 30. CCAPnH: PCA Modules Capture/Compare Registers High Table 31. CCAPnL: PCA Modules Capture/Compare Registers Low Table 32. CH: PCA Counter High Table 33. CL: PCA Counter Low ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated (Refer to Figure 24).

Figure 24. PCA Capture Mode

Figure 25. PCA Compare Mode and PCA Watchdog Timer match could happen. Writing to CCAPnH will set the ECOM bit. and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register. bits in the module's CCAPMn SFR must be set (See Figure 26). A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.

Figure 26. PCA High Speed Output Mode and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register.

PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode. Figure 27. PCA PWM Mode will not cause the RST pin to be driven high.

• 1. periodically change the compare value so it will never match the PCA timer,
• 2. periodically change the PCA timer value so it will never match the compare values, or
• 3. disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it. The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option. This watchdog timer wonÕt generate a reset out on the reset pin. CL CCAPnH CCAPnL ECOMn CCAPMn, n= 0 to 4 0xDA to 0xDE CAPNn MATn TOGn PWMn ECCFnCAPPn 8 bit comparator CEXn Ò0Ó Ò1Ó <Enable PCA counter/timer Overßow

Rev. B - November 10, 2000 59 Preliminary T80C5112 14. Analog-to-Digital Converter (ADC) 14.1. Introduction This section describes the on-chip 10 bit analog-to-digital converter of the T80C5112. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10 bit- cascaded potentiometric ADC. Three kind of conversion are available:

• Standard conversion (7-8 bits).
• Precision conversion (8-9 bits).
• Accurate conversion (10 bits). For the precision conversion, set bits PSIDLE and ADSST in ADCON register to start the conversion. The chip is in a idle mode, the CPU doesnÕt run but the peripherals are always running. This mode allows digital noise to be lower, to ensure precise conversion. For the accurate conversion, set bits QUIETM and ADSST in ADCON register to start the conversion. The chip is in a pseudo-idle mode, the AD is the only peripheral running. This mode allows digital noise to be as low as possible, to ensure high precision conversion. For these modes it is necessary to work with end of conversion interrupt, which is the only way to wake up the chip. If another interrupt occurs during the precision conversion, it will be treated only after this conversion is ended. 14.2. Features
• 8 channels with multiplexed inputs
• 10-bit cascaded potentiometric ADC
• Conversion time 40 micro-seconds
• Zero Error (offset) +/- 2 LSB max
• External Positive Reference Voltage Range 2.4 to Vcc
• Internal Positive Reference Voltage 2.4 Volt. If Vref is used as output, the load must be higher than 18 kOhm.
• ADCIN Range 0 to Vcc
• Integral non-linearity typical 1 LSB, max. 2 LSB
• Differential non-linearity typical 0.5 LSB, max. 1 LSB
• Conversion Complete Flag or Conversion Complete Interrupt
• Selected ADC Clock 14.3. ADC I/O Functions AINx are general I/O that are shared with the ADC channels. The channel select bit in ADCF register define which ADC channel pin will be used as ADCIN. The remaining ADC channels pins can be used as general purpose I/O or as the alternate function that is available. Writes to the port register which arenÕt selected by the ADCF will not have any effect.

When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN in ADCON register. In this mode the power dissipation is about 1uW. The voltage reference can be either internal or external. As input, the Vref pin is used to enter the voltage reference for the A/D conversion. load must greater than 18 kOms. the interrupt the bit ADEOC must be cleared by software. Figure 31. ADC interrupt structure Table 35. ADCON Register

7 QUIETM

Set to put in quiet mode during conversion. Cleared by hardware after completion of the conversion.

6 PSIDLE

Set to put in idle mode during conversion. Cleared by hardware after completion of the conversion.

Table 36. ADCLK Register Table 37. ADDH Register

5 ADEN

Clear for Standby mode (power dissipation 1 uW).

4 ADEOC

Set by hardware when ADC result is ready to be read. This flag can generate an interrupt. Must be cleared by software.

3 ADSST

Set to start an A/D conversion. Cleared by hardware after completion of the conversion.

7 SELREF

Set to enable the internal voltage reference. Clear to disable the internal voltage reference.

Table 38. ADDL Register Table 39. ADCF Register The value read from these bits are indeterminate. Do not set these bits.

(timers 0, 1), serial port interrupt, PCA, SPI and A/D. These interrupts are shown in Figure 32.. Figure 32. Interrupt Control System bit in the Interrupt Priority register (See Table 44.) and in the Interrupt Priority High register (See Table 46.). Table 40. shows the bit values and priority levels associated with each combination.

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt canÕt be interrupted by any other interrupt source. Table 40. Priority bit level values Table 41. Address vectors

Table 42. IE Register Clear to disable all interrupts. Set to enable all interrupts. Clear to disable the the PCA interrupt. Set to enable the the PCA interrupt. The value read from this bit is indeterminate. Do not set this bit. Clear to disable serial port interrupt. Set to enable serial port interrupt.

3 ET1

Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt.

2 EX1

Clear to disable external interrupt 1. Set to enable external interrupt 1.

1 ET0

Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt.

0 EX0

Clear to disable external interrupt 0. Set to enable external interrupt 0.

Table 43. IE1 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.

2 ESPI

Clear to disable the SPI interrupt. Set to enable the SPI interrupt.

1 EADC

Clear to disable the ADC interrupt. Set to enable the ADC interrupt. The value read from this bit is indeterminate. Do not set this bit.

Table 44. IPL0 Register The value read from this bit is indeterminate. Do not set this bit.

6 PPCL PCA Counter Interrupt Priority bit

The value read from this bit is indeterminate. Do not set this bit.

4 PSL Serial port Priority bit

Refer to PSH for priority level.

3 PT1L Timer 1 overflow interrupt Priority bit

Refer to PT1H for priority level.

2 PX1L External interrupt 1 Priority bit

Refer to PX1H for priority level.

1 PT0L Timer 0 overflow interrupt Priority bit

Refer to PT0H for priority level.

0 PX0L External interrupt 0 Priority bit

Refer to PX0H for priority level.

Table 45. IPL1 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. 2 PSPI SPI Interrupt Priority level less significant bit. Refer to PSPIH for priority level. 1 PADC ADC Interrupt Priority level less significant bit. Refer to PADCH for priority level. The value read from this bit is indeterminate. Do not set this bit.

Table 46. IPH0 Register The value read from this bit is indeterminate. Do not set this bit.

6 PPCH

The value read from this bit is indeterminate. Do not set this bit.

4 PSH

3 PT1H

2 PX1H

1 PT0H

0 PX0H

Table 47. IPH1 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.

2 PSPIH

1 PADCH

The value read from this bit is indeterminate. Do not set this bit.

The program Lock system, when programmed, protects the on-chip program against software piracy. state, will return the code in its original, unmodified form. should be programmed with random values. in Section ÒSignature bytesÓ, page 75. Refer to Section ÒVerify algorithmÓ, page 76. Table 48. Program Lock bits

1 U U

2 P U MOVC instruction executed from external program memory are disabled from fetching

EA is sampled and latched on reset.

3 U P

The program Lock system, when programmed, protects the on-chip program against software piracy. the encryption array in the unprogrammed state, will return the code in its original, unmodified form. should be programmed with random values. WARNING: Security level 2 and higher should only be programmed after EPROM verification. Table 49. Program Lock bits

1 U U U

2 P U U

programming of the EPROM is disabled..

3 U P U

4 U U P Same as 3, also external execution is disabled.

Control and program signals must be held at the levels indicated in Table 50. Program Signals: ALE/ PROG, RST/VPP. Table 50. EPROM Set-Up Modes

Figure 33. Set-Up Modes Configuration applied during byte programming from 25 to 1.

• Step 1: Activate the combination of control signals.
• Step 2: Input the valid address on the address lines.
• Step 3: Input the appropriate data on the data lines.
• Step 4: RaiseRST/VPP from VCC to VPP (typical 12.75V).
• Step 5: Pulse ALE/PROG once.
• Step 6: LowerRST/VPP from VPP to VCC Repeat step 2 through 6 changing the address and data for the entire array or until the end of the object file is reached (See Figure 34). 17.3.4. Verify algorithm Code array verify must be done after each byte or block of bytes is programmed. In either case, a complete verify of the programmed array will ensure reliable programming of the T80C5112. P 2.7 is used to enable data output. To verify the T80C5112 code the following sequence must be exercised:
• Step 1: Activate the combination of program and control signals.
• Step 2: Input the valid address on the address lines.
• Step 3: Read data on the data lines. Repeat step 2 through 3 changing the address for the entire array verification (See Figure 34). The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the code array is well encrypted. +5V VCC P0.0-P0.7 P1.0-P1.7 P2.0-P2.5 P3.4-P3.5 VSS GND D0-D7 A0-A7 A8-A15 RST RST/VPP ALE/ PR OG PSEN P2.6 P2.7 P3.3 P3.7 P3.6 XTAL14 to 6 MHz CONTROL SIGNALS* PROGRAM SIGNALS* * See Table 49. for proper value on these inputs EA+5V

Figure 34. Programming and Verification Signal’s Waveform Erasure leaves all the EPROM cells in a 1Õs state (FF). of about 25 mm, should be sufficient. An exposure of 1 hour is recommended with most of standard erasers. label be placed over the window. content of the signature byte for the T80C5112. Table 51. Signature Bytes Content

78 Rev. B - November 10, 2000 Preliminary T80C5112 18. Electrical Characteristics 18.1. Absolute Maximum Ratings(1) Ambiant Temperature Under Bias: C = commercial 0°Ct o7 0°C I = industrial -40°Ct o8 5°C Storage Temperature -65°Ct o+1 5 0°C Voltage on VCC to VSS- 0 . 5Vt o+7V Voltage on VPP to VSS- 0 . 5Vt o+1 3V Voltage on Any Pin to VSS- 0 . 5Vt oVCC + 0.5 V Power Dissipation1 W(2) NOTES 1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. 2. This value is based on the maximum allowable die temperature and the thermal resistance of the package. 18.2. Power consumption measurement Since the introduction of the first C51 devices, every manufacturer made operating Icc measurements under reset, which made sense for the designs were the CPU was running under reset. In our new devices, the CPU is no more active during reset, so the power consumption is very low but is not really representative of what will happen in the customer system. ThatÕs why, while keeping measurements under Reset, we present a new way to measure the operating Icc: Using an internal test ROM, the following code is executed: Label: SJMP Label (80 FE) Ports 1, 3, 4 are disconnected, RST = Vcc, XTAL2 is not connected and XTAL1 is driven by the clock. This is much more representative of the real operating Icc.

Table 52. DC Parameters in Standard Voltage

Table 53. DC Parameters for Low Voltage

1. I CC under reset is measured with all output pins disconnected; XTAL1 driven with TCLCH , TCHCL = 5 ns (see Figure 39.), VIL = VSS + 0.5 V ,
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH ,TCHCL = 5 ns, VIL =V SS + 0.5 V , VIH =V CC - 0.5 V; XTAL2

N.C; Vpp = RST = VSS (see Figure 37.).

a list of all the characters and what they stand for. AVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. TA =0t o+ 7 0°C (commercial temperature range); VSS =0V ;V CC =5V ± 10%; -V ranges. TA = -40°Ct o+ 8 5°C (industrial temperature range); VSS =0V ; V CC =5V ± 10%; -V ranges. TA =0t o+ 7 0°C (commercial temperature range); VSS =0V ;2 . 7V<V CC < 5.5 V; -L range. TA = -40°Ct o+ 8 5°C (industrial temperature range); VSS =0V ;2 . 7V<V CC < 5.5 V; -L range. Table 55. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE andPSEN signals. Table 55. Load Capacitance versus speed range, in pF Table 57., Table 60. and Table 61. give the description of each AC symbols. Table 57., Table 59. and Table 62. give for each range the AC parameter.

Table 56. Max frequency for derating formula regarding the speed grade

Table 57. AC Parameters for Fix Clock

30 MHz

40 MHz

20 MHz

30 MHz Units

Table 58. AC Parameters for a Variable Clock: derating formula Figure 40. External Program Memory Read Cycle

12 TCLCL

Rev. B - November 10, 2000 87 Preliminary T80C5112 18.6.4. External Data Memory Characteristics Symbol Parameter TRLRH RD Pulse Width TWLWH WR Pulse Width TRLDV RD to Valid Data In TRHDX Data Hold AfterRD TRHDZ Data Float AfterRD TLLDV ALE to Valid Data In TAV DV Address to Valid Data In TLLWL ALE to WR or RD TA VWL Address toWR or RD TQVWX Data Valid toWR Transition TQVWH Data set-up toWR High TWHQX Data Hold AfterWR TRLAZ RD Low to Address Float TWHLH RD or WR High to ALE high

Table 59. AC Parameters for a Fix Clock

Table 60. AC Parameters for a Variable Clock: derating formula Figure 41. External Data Memory Write Cycle

Figure 42. External Data Memory Read Cycle Table 62. AC Parameters for a Fix Clock Table 61. Symbol Description

Table 63. AC Parameters for a Variable Clock: derating formula Figure 43. Shift Register Timing Waveforms

Figure 44. EPROM Programming and Verification Waveforms

Figure 47. Float Waveforms to float when a 100 mV change from the loaded VOH /VOL level occurs. IOL /IOH ³± 20mA.

Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two. Figure 48. Clock Waveforms are incorporated in the AC specifications.

Table 64. Maximum Clock Frequency

Table 65. Possible order entries