T7630

T7630 AGERE | Alldatasheet

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Features

The T7630 Dual T1/E1 T erminator consists of two independent, highly integrated, software-config- urable, full-featured short-haul transceiver/framers. The T7630 provides glueless interconnection from a T1/E1 line to a digital PCM system. Minimal external clocks are needed. Only a system clock/frame sync and a phase-locked line rate clock are required. Sys- tem diagnostic and performance monitoring capabil- ity with integrated programmable test pattern generator/detector and loopback modes is provided. Power Requirements and Package ■ Single 5 V ± 5% supply. ■ Low power: 375 mW per channel maximum. ■ 144-pin TQFP package. ■ Operating temperature range: –40 °C to +85 °C. T1/E1 Line Interface Features ■ Full T1/E1 pulse template compliance. ■ Receiver provides equalization for up to 11 dB of loss. ■ Digital clock and data recovery. ■ Line coding: B8ZS, HDB3, ZCS, and AMI. ■ Line interface coupling and matching networks for T1 and E1 (120 Ω and 75 Ω ). T1/E1 Framer Features ■ Supports T1 framing modes ESF , D4, SLC ® -96, T1DM DDS. ■ Supports G.704 basic and CRC-4 multiframe for- mat E1 framing and procedures consistent with G.706. ■ Supports unframed transmission format. ■ T1 signaling modes: transparent; ESF 2-state, 4-state, and 16-state; D4 2-state and 4-state; SLC -96 2-state, 4-state, 9-state and 16-state. E1 signaling modes: transparent and CAS. ■ Alarm reporting and performance monitoring per AT & T, ANSI*, and ITU-T standards. ■ Programmable, independent transmit and receive system interfaces at a 2.048 MHz, 4.096 MHz, or 8.192 MHz data rate. ■ System interface master mode for generation of system frame sync from the line source. ■ Internal phase-locked loop (with external VCXO) for generation of system clock from the line source. Facility Data Link Features ■ HDLC or transparent modes. ■ Automatic transmission and detection of ANSI T1.403 FDL performance report message and bit- oriented codes. ■ 64-byte FIFO in both transmit and receive direc- tions. Microprocessor Interface ■ 33 MHz, 8-bit data interface, no wait-states. ■ Intel† or Motorola‡ interface modes with multi- plexed or demultiplexed buses. ■ Directly addressable control registers.

Applications

■ Customer Premises Equipment— CSU/DSU, routers, digital PBX, channel banks (CB), base transceiver stations (BTS-picocell), small switches, and digital subscriber loop access multiplexers (DSLAM). ■ Loop/Access—DLC/IDLC, DCS, BTS (microcell/ macrocell), DSLAMs, and multiplexers (terminal, synchronous/asynchronous, add drop). ■ Central Office—Digital switches, DCS, CB, access concentrators, remote switch modules (RSM), and DSLAMs. ■ Test Equipment—T ransmission/BERT tester. * ANSI is a registered trademark of American National Standards Institute, Inc. † Intel is a registered trademark of Intel Corporation. ‡ Motorola is a registered trademark of Motorola, Inc.

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) October 2000 2 Lucent Technologies Inc.

Lucent Technologies Inc. 3 Preliminary Data Sheet October 2000 T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) Table of Contents (continued) Contents Page

Table 45. Summary of the Deactivation of SSTSSLB and SSTSLLB Modes as a Function

Table of Contents (continued) Table Page Preliminary Data Sheet T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) October 2000 8 Lucent Technologies Inc. T able 93. Exchange Termination and Exchange T ermination Remote T able 94. Network T ermination and Network T ermination Remote

Table 100. CRC-4 Errors at NT1 from NT2 Counter Registers (FRM_SR16—FRM_SR17) ((610—611); Table 108. ET -RE Severely Errored Seconds Counter (FRM_SR32—FRM_SR33) ((620—621); (C20—C21))..158 Table 115. NT1-RE Bursty Errored Seconds Counter (FRM_SR46—FRM_SR47) ((62E—62F); (C2E—C2F))..159 Table 116. NT1-RE Severely Errored Seconds Counter (FRM_SR48—FRM_SR49 ((630—631); Table 122. Transmit Framer Table 123. Received Signaling Registers: DS1 Format (FRM_RSR0—FRM_RSR23) ((640—658); Table 124. Receive Signaling Registers: CEPT Format (FRM_RSR0—FRM_RSR31) ((640—65F); Table 125. Summary of Interrupt Group Enable Registers (FRM_PR0—FRM_PR7) ((660—667); Table 140. Severely Errored Second Threshold Registers (FRM_PR12—FRM_PR13) ((66C—66D;

Table of Contents (continued) Table Page Preliminary Data Sheet T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) October 2000 10 Lucent Technologies Inc. T able 144. NT1 Remote End Errored Event Enable Registers T able 145. Automatic AIS to the System and Automatic Loopback Enable Register (FRM_PR19) (673; C73) .. 170 T able 155. T ransmission of Remote Frame Alarm and CEPT T able 161. T able 163. CEPT Time Slot 16 X-Bit Remote Multiframe Alarm T able 166. DS1 System Interface Control and CEPT FDL Source Control Register (FRM_PR43) (68B; C8B).. 181 T able 172. CHI T ransmit Time-Slot Enable Registers (FRM_PR49—FRM_PR52) ((691—694); (C91—C94))... 185 T able 173. CHI Receive Time-Slot Enable Registers (FRM_PR53—FRM_PR56) ((695—698); (C95—C98)) ... 185 T able 180. T ransmit Signaling Registers: DS1 Format T able 181. T ransmit Signaling Registers: CEPT Format

Table 193. FDL T ransmit Table 197. Receive

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II) October 2000 12 Lucent Technologies Inc. Lucent T echnologies Inc. Feature Descriptions ■ T wo independent T1/E1 channels each consisting of a T1/E1 short-haul line interface and a T1/E1 framer with HDLC formatting on the facility data link inter- face. ■ Memory-mapped read and write registers. ■ Maskable interrupt events. ■ Hardware and software resets. ■ Onboard software-selectable pseudorandom test pattern generator and detector for line performance monitoring. ■ 3-state outputs. ■ Single 5 V ± 5% supply. ■ Low power consumption: 750 mW max. T1/E1 Line Interface Features ■ T ransmitter includes transmit encoder (B8ZS or HDB3), pulse shaping, and line driver. ■ Five pulse equalization settings for template compli- ance at DSX cross connect. ■ Receive includes equalization, digital clock and data recovery (immune to false lock), and receive decoder. ■ CEPT/E1 interference immunity as required by G.703. ■ T ransmit jitter <0.02 UI. ■ Receive generated jitter <0.05 UI. ■ Jitter attenuator selectable for use in transmit or receive path. Jitter attenuation characteristics are data pattern independent. ■ For use with 100 Ω DS1 twisted-pair, 120 Ω E1 twisted-pair, and 75 Ω E1 coaxial cable. ■ Common transformer for transmit/receive. ■ Analog LOS alarm for signals less than –18 dB for greater than 1 ms or 10-bit to 255-bit symbol periods (selectable). ■ Digital LOS alarm for 100 zeros (DS1) or 255 zeros (E1). ■ Diagnostic loopback modes. ■ Compliant with A T&T CB119(10/79); ANSI T1.102(93), T1. CORE(12/95), GR-820-CORE(11/94), GR-1244- CORE(6/95). T1/E1 Framer Features ■ Framing formats: — Compliant with T1 standards ANSI T1.231 (1993), A T&T TR54016, A T&T TR62411 (1998). — Unframed, transparent transmission in T1 and E1 formats. — DS1 extended superframe (ESF). — DS1 superframe (SF): D4; SLC -96; T1DM DDS; T1DM DDS with FDL access. — DS1 independent transmit and receive framing modes when using the ESF and D4 formats. — Compliant with ITU CEPT framing recommenda- tion: 1. G.704 and G.706 basic frame format. CRC-4 multiframe search algorithm. 3. G.706 Annex B: CRC-4 multiframe search algo- rithm with 400 ms timer for interworking of CRC-4 and non-CRC-4 equipment. 4. G.706 Section 4.3.2 Note 2: monitoring of 915 CRC-4 checksum errors for loss of frame state. ■ Framer line codes: — DS1: alternate mark inversion (AMI); binary eight zero code suppression (B8ZS); per-channel zero code suppression; decoding bipolar violation monitor; monitoring of eight or fifteen bit intervals without positive or negative pulses error indica- tion. — DS1 independent transmit and receive path line code formats when using AMI/ZCS and B8ZS coding. — ITU-CEPT: AMI; high-density bipolar 3 (HDB3) encoding and decoding bipolar violation monitor- ing, monitoring of four bit intervals without positive or negative pulses error indication. — Single-rail option.

Lucent Technologies Inc. 13 Preliminary Data Sheet October 2000 T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) Lucent T echnologies Inc. Feature Descriptions (continued) ■ Signaling: — DS1: extended superframe 2-state, 4-state, and 16-state per-channel robbed bit. — DS1: D4 superframe 2-state and 4-state per- channel robbed bit. — DS1: SLC -96 superframe 2-state, 4-state, 9-state, and 16-state per-channel robbed bit. — DS1: channel-24 message-oriented signaling. — ITU CEPT: channel associated signaling (CAS). — T ransparent (all data channels). ■ Alarm reporting, performance monitoring, and main- tenance: ANSI T1.403-1995, A T&T TR 54016, and ITU G.826 standard error checking. — Error and status counters. — Bipolar violations. — Errored frame alignment signals. — Errored CRC checksum block. — CEPT: received E bit = 0. — Errored, severely errored, and unavailable sec- onds. — Selectable errored event monitoring for errored and severely errored seconds processing with programmable thresholds for errored and severely errored second monitoring. — CEPT: Selectable automatic transmission of E bit to the line. — CEPT: Sa6 coded remote end CRC-4 error E bit = 0 events. — Programmable automatic and on-demand alarm transmission. 1. Automatic transmission of remote frame alarm to the line while in loss of frame alignment state. 2. Automatic transmission of alarm indication sig- nal (AIS) to the system while in loss of frame alignment state. — Multiple loopback modes. — Optional automatic line and payload loopback activate and deactivate modes. — CEPT nailed-up connect loopback and CEPT nailed-up broadcast transmission TS-X in TS-0 transmit mode. — Selectable test patterns for line transmission. — Detection of framed and unframed pseudorandom and quasi-random test patterns. — Programmable squelch and idle codes. ■ System interface: — Autonomous transmit and receive system inter- faces. — Independent transmit and receive frame synchro- nization input signals. — Independent transmit and receive system inter- face clock. — 2.048 Mbits/s, 2.048 MHz concentration highway interface (CHI) default mode. — Optional 4.096 Mbits/s and 8.192 Mbits/s data rates. — Optional 4.096 MHz, 8.192 MHz, and 16.384 MHz frequency system clock. — Programmable clock edge for latching frame syn- chronization signals. — Programmable clock edge for latching transmit and receive data. — Programmable bit and byte offset. — Programmable CHI master mode for the genera- tion of the transmit CHI FS from internal logic with timing derived from the receive line clock signal. ■ Digital phase comparator for clock generation in the receive and transmit paths. Facility Data Link Features ■ HDLC or transparent mode. ■ Automatic transmission of the ESF performance report messages (PRM). ■ Detection of the ESF PRM. ■ Detection of the ANSI ESF FDL bit-oriented codes. ■ 64-byte FIFO in both transmit and receive directions. ■ Programmable FIFO full- and empty-level interrupt. ■ SLC -96: FDL transmit and receive register access of D bits. User-Programmable Microprocessor Inter- face ■ 33 MHz read and write access with no wait-states. ■ 12-bit address, 8-bit data interface. ■ Programmable Intel or Motorola interface modes. ■ Demultiplexed or multiplexed address and data bus. ■ Directly addressable internal registers. ■ No clock required.

14 Lucent Technologies Inc. Lucent T echnologies Inc. Figure 1. T7630 Block Diagram (One of Two Channels)

Lucent Technologies Inc. 15 Preliminary Data Sheet October 2000 T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) Lucent T echnologies Inc. Functional Description (continued) The Lucent T7630 Dual T1/E1 T erminator (Terminator- II) provides two complete T1/E1 interfaces each con- sisting of a fully integrated, full-featured, short-haul line interface transceiver and a full-featured primary rate framer with an HDLC formatter for facility data link access. The T7630 provides glueless interconnection from a T1 or E1 analog line interface to devices inter- facing to its CHI; for example, the T7270 Time-Slot Interchanger or T7115A Synchronous Protocol Data Formatter. The line interface receiver performs clock and data recovery using a digital phase-locked loop, thereby avoiding false lock conditions that are common when recovering sparse data patterns with an analog imple- mentation. The receiver’s equalization circuit guaran- tees a high level of interference immunity. The receive line unit monitors the amplitude at the receive input for analog loss of signal (ALOS) detection and the pulse density of the receive signal for digital loss of signal (DLOS) detection. The receive line unit may be pro- grammed to detect bipolar violations. The line interface unit may be optionally bypassed. It is recommended that the LIU/framer interface be placed in dual-rail mode, which allows the framers error/event detector to detect and report code and bipolar violation (BPV) errors. The line interface unit’s transmit equalization is done with low-impedance output drivers that provide shaped waveforms to the transformer, guaranteeing template conformance. The transmitter will interface to the digital cross connect (DSX) at lengths up to 655 feet for DS1 operation, and line impedances of 75 Ω or 120 Ω for CEPT -E1 operation. The transmit line unit monitors nonfunctional links due to faults at the primary of the transmit transformer and periods of no data transmis- sion. The line codes supported in the framer unit include AMI, T1 B8ZS, per-channel T1 zero code suppression and ITU-CEPT HDB3. The T7630 supports T1 D4, T1DM, and SLC -96 SF , ESF; ITU-CEPT -E1 basic frame; ITU-CEPT -E1 time slot 0 multiframe; and time slot 16 multiframe formats. The receive framer monitors the following alarms: loss of receive clock, loss of frame, alarm indication signal (AIS), remote frame alarms, and remote multiframe alarms. These alarms are detected as defined by the appropriate ANSI, A T&T , and ITU standards. Performance monitoring as specified by A T&T , ANSI, and ITU is provided through counters monitoring bipo- lar violation, frame bit errors, CRC errors, CEPT E bit = 0 conditions, CEPT Sa6 codes, errored events, errored seconds, bursty errored seconds, severely errored sec- onds, and unavailable seconds. In-band loopback activation and deactivation codes can be transmitted to the line via the payload or the facility data link. In-band loopback activation and deac- tivation codes in the payload or the facility data link are detected. System, payload, and line loopbacks are programma- ble. The default system interface is a 2.048 Mbits/s data and 2.048 MHz clock CHI serial bus. This CHI interface consists of independent transmit and receive paths. The CHI interface can be reconfigured into several modes: a 2.048 Mbits/s data interface and 4.096 MHz clock interface, a 4.096 Mbits/s data interface and 4.096 MHz clock interface, a 4.096 Mbits/s data inter- face and 8.192 MHz clock interface, a 8.192 Mbits/s data interface and 8.192 MHz clock interface, and 8.192 Mbits/s data interface and 16.384 MHz clock interface. The signaling formats supported are T1 per-channel robbed-bit signaling (RBS), channel-24 message-ori- ented signaling (MOS), and ITU-CEPT -E1 channel- associated signaling (CAS). In the T1, RBS mode voice and data channels are programmable. The entire pay- load can be programmed into a data-only (no signaling channels) mode, i.e., transparent mode. Signaling access can be through the on-chip signaling registers or the system CHI port in the associated signaling mode. Data and its associated signaling information can be accessed through the CHI in either DS1 or CEPT -E1 modes. Extraction and insertion of the facility data link in ESF , T1DM, SLC -96, or CEPT -E1 modes are provided through a four-port serial interface or through a micro- processor-accessed, 64-byte FIFO either with HDLC formatting or transparently. In the T7630’s SLC -96 or CEPT -E1 frame formats, a facility data link (FDL) is pro- vided for FDL access. The bit-oriented ESF data-link messages defined in ANSI T1.403-1995 are monitored by the receive framer’s facility data link unit and are transmitted by the transmit framer FDL The receive framer includes a two-frame elastic store buffer for jitter attenuations that performs control slips and provides indication of slip directions. Accessing internal registers is done via the demulti- plexed/multiplexed address and data bus microproces- sor interface using either the Intel 80188 (or 80X88) interface protocol with independent read and write sig- nals or the Motorola MC680X0 or M68360 interface protocol with address and data strobe signals.

16 Lucent Technologies Inc. Lucent T echnologies Inc. (TQFP) with 20 mils lead pitch. Figure 2. T7630 Block Diagram: Receive Section (One of Two Channels)

• MESSAGE-ORIENTED MESSAGES
• BIT -ORIENTED MESSAGES – ANSI T1.403-1989 ESF FORMAT: – DDS ACCESS – SLC-96 FORMA T AND MONITOR: RECEIVE FACILITY DATA LINK EXTRACTER RFRMCK FRONT END RECEIVE ANALOGANALOG CLOCK AND LINE INTERFACE UNIT BYP ASS RPD-LIU, RND-LIU, RPDE, RNDE, RLCKE RPD, RND, RLCK RECEIVE PA TTERN MONITOR: – QUASI-RANDOM: 2 20 – 1 – PSEUDORANDOM: 2 15 – 1 – ANSI T1.403 BIT-ORIENTED AND ESF-FDL ACTIVA TE AND DEACTIVA TE LINE LOOPBACK CODES – CEPT AUXILIARY PA TTERN (CEPT = 01) – CEPT ACTIVA TE AND DEACTIVA TE LOOPBACK – CEPT Sa6 CODES – T1/E1 CRC ERRORS RECEIVE FDL HDLC EXTRACTER: – 64-byte RECEIVE FIFO – TRANSPARENT MODE (NO HDLC FRAMING) – MICROPROCESSOR ACCESS TCHIDA T A TCHIDAT AB FRAMER RLCK-LIU CODES TEST PATTERN DETECTOR – MARK (ALLONES) – QRSS (QUASI-RANDOM: 2 20 – 1) – 25 – 1 – 26 – 1 (53) – 29 – 1 (511) – 211 – 1 (2047) – 215 – 1 (PSEUDORANDOM) – 220 – 1 – 223 – 1 – 1:1 (AL TERNATING 10)

Figure 3. T7630 Block Diagram: Transmit Section (One of Two Channels)

• BIT -ORIENTED MESSAGES
• MESSAGE-ORIENTED MESSAGES TRANSMIT FDL HDLC INSERTER: – 64-byte TRANSMIT FIFO – TRANSP ARENT MODE – MICROPROCESSOR ACCESS (NO HDLC FRAMING) INSERTER: TFDLCK TFDL LINE FORMA T ENCODER (AMI; B8ZS; HDB3) TLCK, TND, TPD AUTOMATIC AND ON-DEMAND COMMANDS: – AIS (LINE, SYSTEM, FDL) – LOOPBACKS – REMOTE FRAME ALARMS (RFA) – CEPT E BIT = 0 – CEPT TS16 AIS – CEPT TS16 RPA TRANSMIT ELASTIC STORE BUFFER (2 FRAMES) RECEIVE CONCENTRA TION HIGHWAY INTERFACE (RA TE ADAPTER) RCHICK RCHIFS RCHIDA T A TRANSMIT ALARM MONITOR: – LOSS OF SYSTEM BIFRAME ALIGNMENT – SYSTEM ALARM INDICA TION SIGNAL (AIS) RCHIDA TAB TRANSMIT SIGNALING INSERTER: – DS1 ROBBED-BIT SIGNALING (RBS) – CEPT CHANNEL ASSOCIA TED AND – CONCENTRA TION HIGHWAY ACCESS – MICROPROCESSOR ACCESS COMMON-CHANNEL SIGNALING LOSS OF TLCK TEST PATTERN GENERATOR – MARK (ALL1s) – QRSS – 25 – 1 – 26 – 1 (53) – 29 – 1 (511) – 211 – 1 (2047) – 215 – 1 – 220 – 1 – 223 – 1 – 1:1 (ALTERNATING 10) PLLCK

18 Lucent Technologies Inc. Lucent T echnologies Inc. The package type and pin assignment for the T7630 (Terminator-II) is illustrated in Figure 4. Figure 4. Pin Assignment

T able 1 and T able 2 show the list of T7630 pins and a functional description for each. Table 1. Pin Descriptions-Channel 1 and Channel 2

• Iu indicates an internal pull-up.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. ‡ Asserting this pin low will initially force RDY to a low state. GRND P Digital Ground Reference. when SYSCK clock, pin 3/35, is absent. when RLCK clock, pin 47/135, is absent. PLL circuitry (refer to the Phase-Lock Loop Circuit section). A P Analog Ground Reference. Receive Negative Rail Data. Valid when the FRAMER pin is strapped to 0 V .

20 Lucent Technologies Inc. Lucent T echnologies Inc. Table 1. Pin Descriptions-Channel 1 and Channel 2 (continued)

• Iu indicates an internal pull-up.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. ‡ Asserting this pin low will initially force RDY to a low state. Receive Positive Rail Data. Valid when the FRAMER pin is strapped to 0 V . data latched by the rising edge of RLCK. DDA P Analog 5 V Power Supply. 5 V ± 5%. GRNDX P Transmit Line Driver Ground Reference. 16 22 V DD XP Transmit Line Driver 5 V Power Supply. 5 V ± 5%. VDD P 5 V Power Supply. 5 V ± 5%. enable defaults for CEPT operation. 141 41 FRAMER I u Framer Mode. Strap to VDD to enable integrated LIU and framer operation. driven by the transmit framer. † Iu Reset (Active-Low). Asserting this pin low resets the channel. framer positive NRZ output data. Data changes on the rising edge of TLCK. In the single-rail mode, TPD = transmit framer data.

• Iu indicates an internal pull-up.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. ‡ Asserting this pin low will initially force RDY to a low state. framer negative NRZ output data. Data changes on the rising edge of TLCK. In the single-rail mode, TND = 0. changes on the rising edge of TLCK. used by the receive framer to latch RPD and RND data. (CKSEL = 1) or a primary line rate clock for SYSCK (CKSEL = 0). elastic store. During loss of frame alignment, this signal is forced to 1. zation pulse generated by the receive framer. CEPT CRC-4 multiframe synchronization pulse in the receive framer. data link bit changes on the falling edge of RFDLCK. 126 56 TCHICK I TransmitrCHI Clock. This clock must be free of jitter. generates the 8 kHz frame sync to control the CHI.

22 Lucent Technologies Inc. Lucent T echnologies Inc.

• Iu indicates an internal pull-up.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. ‡ Asserting this pin low will initially force RDY to a low state. state for all inactive time slots. state for all inactive time slots. recovered receive line interface unit clock or the RLCK input signal. PLL circuitry (refer to the Phase-Lock Loop Circuit section. tion pulse in the transmit framer. This signal is active-high. framer. This signal is active-high. bits on the falling edge of TFDLCK. the NOT -FAS frame time slot 0. This clock must be free of jitter.

Table 2. Pin Descriptions-Global

• Iu indicates an internal pull-up. Id indicates an internal pull-down.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. ‡ Asserting this pin low will initially force RDY to a low state. microprocessor protocol (MODE3 or MODE4). bus with the contents of the addressed register while RD is low. read accesses; this pin is asserted low for write accesses. mode. Strap to VDD to enable the multiplexed address and data bus mode. data bus used for read and write accesses. High-impedance output. output may not be wire OR connected to any other logic output.

24 Lucent Technologies Inc. Lucent T echnologies Inc. Table 2. Pin Descriptions-Global (continued)

• Iu indicates an internal pull-up.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. of a read or write access; DT ACK is 1 otherwise. mode to generate the READY signal. of TCK from the boundary-scan test circuitry. TCK for the boundary-scan test circuitry.

106 JT AGTRST

nously initialize/reset the boundary-scan test logic.

• Iu indicates an internal pull-up. Id indicates an internal pull-down.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. ‡ Asserting this pin low will initially force RDY to a low state. of a read or write access; DT ACK is 1 otherwise. mode to generate the READY signal. of TCK from the boundary-scan test circuitry. TCK for the boundary-scan test circuitry. nously initialize/reset the boundary-scan test logic.

The T7630 LIU diagram is shown in Figure 5. Only a single transceiver is shown here for illustration purposes. Figure 5. Block Diagram of Line Interface Unit: Single Channel and data decoding are performed.

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II) October 2000 26 Lucent Technologies Inc. Lucent T echnologies Inc. Line Interface Unit: Receive (continued) Jitter Accommodation and Jitter Transfer Without the Jitter Attenuator The RLIU is designed to accommodate large amounts of input jitter. The RLIU’s jitter performance exceeds the requirements shown in the RLIU specification T able 5 and Table 6. T ypical receiver performance with- out the jitter attenuator in the path is shown in Figures 6—9. T ypical receiver performance with the jit- ter attenuator is given in Figures 12—15. Jitter transfer is independent of input ones density on the line inter- face. Receive Line Interface Configuration Modes Zero Substitution Decoding (CODE) When single-rail operation is selected with DUAL = 0 (register LIU_REG3, bit 3), the LIU B8ZS/HDB3 zero substitution decoding can be selected via the CODE bit (register LIU_REG3, bit 2). If CODE = 1, the B8ZS/ HDB3 decoding function is enabled in the receive path. Decoded receive data appears at the internal LIU-to- framer RPD interface (RPD-LIU). Code violations, including BPVs, appear at the internal LIU-to-framer RND_BPV interface (RND-LIU). If CODE = 0, the receive data is passed unaltered to RPD-LIU, and all bipolar violations (such as two consecutive ones if the same polarity) appear at RND-LIU. The default configu- ration is single-rail, DUAL = 0, with the decoding active, CODE = 1. If DUAL = 0, the receive framer must be programmed to the single-rail mode and the receive framer’s internal LIU-to-framer RPD input will be the receive data port. If DUAL = 0, then the receive framer’s bipolar violation count will increment by one whenever the internal LIU- to-framer RND_BPV signal is one. The bipolar violation count is incremented on the rising edge of the receive framer’s RLCK clock signal. Receive Line Interface Unit (RLIU) Alarms Analog Loss of Signal (ALOS) Alarm. An analog sig- nal detector monitors the receive signal amplitude and reports its status in the ALOS alarm bit ALOS (register LIU_REG0, bit 0). ALOS is indicated (ALOS = 1) if the amplitude at the RRING and RTIP inputs drops below a voltage approximately 18 dB below the nominal signal amplitude. The ALOS alarm condition will clear when the receive signal amplitude returns to a level greater than 14 dB below normal. The ALOS alarm status bit will latch the alarm and remain set until being cleared by a read (clear on read). Upon the transition from ALOS = 0 to ALOS = 1, a microprocessor interrupt will be generated if the ALOS interrupt enable bit ALOSIE (register LIU_REG1, bit 0) is set. The reset default is ALOSIE = 0. The ALOS circuitry provides 4 dB of hysteresis to pre- vent alarm chattering. The time required to detect ALOS is selectable. When ALTIMER = 0 (register LIU_REG4, bit 0), ALOS is declared between 1 ms and 2.6 ms after losing signal as required by I.431(3/93) and ETS-300-233 (5/94). If ALTIMER = 1, ALOS is declared between 10-bit and 255-bit symbol periods after losing signal as required by G.775 (11/95). The timing is derived from the SYSCK clock. The detection time is independent of signal amplitude before the loss condition occurs. Normally, ALTIMER = 1 would be used only in E1 mode since no T1/DS1 standards require this mode. In T1/DS1 mode, this bit should nor- mally be zero. The reset default is ALTIMER = 0. The behavior of the receiver RLIU outputs under ALOS conditions is dependent on the loss shutdown (LOSSD) control bit (register LIU_REG3, bit 4) in conjunction with the receive alarm indication select (RCVAIS) con- trol bit (register LIU_REG4, bit 1) as described in the Loss Shutdown (LOSSD) and Receiver AIS (RCVAIS) section on page 27. When operating on long-haul loops, the receive input signal will routinely be well below the 20 dB ALOS level. Therefore, when the transmit equalization is programmed to any of the long- haul settings shown in T able 8, the ALOS function is completely disabled. Digital Loss of Signal (DLOS) Alarm. A (DLOS) detector guarantees the received signal quality as defined in the appropriate ANSI, Bellcore, and ITU standards. The DLOS alarm is reported in the RLIU alarm status register (register LIU_REG0, bit 1). For DS1 operation, digital loss of signal (DLOS = 1) is indi- cated if 100 or more consecutive zeros occur in the receive data stream. The DLOS condition is deacti- vated when the average ones density of at least 12.5% is received in 100 contiguous pulse positions. The DLOS alarm status bit will latch the alarm and remain set until being cleared by a read (clear on read). The LOSSTD control bit (register LIU_REG2, bit 2) selects the conformance protocols for the DLOS alarm indica- tion per T able 3. Setting LOSSTD = 1 adds an addi- tional constraint that there are less than 15 consecutive zeros in the DS1 data stream before DLOS is deacti- vated. The reset default is LOSSTD = 0.

consecutive zeros occur in the receive data stream. is set. The reset default is DLOSIE = 0. transient. The reset default is PFLALM = 0. Table 3. DLOS Standard Select mined state when a DLOS or ALOS alarm occurs. runs (at the INTSYSCK/16 frequency). RLCK-LIU free runs (at the INTSYSCK/16 frequency). The default reset state is LOSSD = 0 and RCVAIS = 0. Table 4. LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes) the HDB3/B8ZS code violations, as defined in the appropriate standards, are reflected on the RND-LIU output.

3232 Lucent Technologies Inc. Preliminary Data Sheet T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) October 2000 Lucent T echnologies Inc. Line Interface Unit: Transmit Output Pulse Generation The line interface transmitter accepts a line rate clock and NRZ data in single-rail mode (DUAL = 0) or posi- tive and negative NRZ data in dual-rail mode (DUAL = 1) from the transmit framer unit or, optionally, the sys- tem interface. The line interface transmitter converts this data to a balanced bipolar signal (AMI format) with optional B8ZS(DS1)/HDB3(E1) encoding and optional jitter attenuation. Low-impedance output drivers pro- duce the line transmit pulses. Positive ones are output as positive pulses on TTIP , and negative ones are out- put as positive pulses on TRING. Binary zeros are con- verted to null pulses. In DSX-1 applications, transmit pulse shaping is con- trolled by the on-chip pulse-width controller and pulse equalizer. The pulse-width controller produces high- speed timing signals to accurately control the transmit pulse widths. This eliminates the need for a tightly con- trolled transmit clock duty cycle that is usually required in discrete implementations. The pulse equalizer con- trols the amplitudes and shapes of the pulses. Different pulse equalizations are selected through settings of EQ2, EQ1, and EQ0 bits (register LIU_REG6, bits 0 to 2) as described in T able 7, Transmit Line Interface Short-Haul Equalizer/Rate Control below. The reset default state of the equalization bits EQ2, EQ1, and EQ0 can be predetermined by setting the DS1_CEPT pin. The default transmit equalization is EQ2, EQ1, and EQ0 = 000 (0 dB T1/DS1) when DS1_CEPT = 1; EQ2, EQ1, and EQ0 = 110 (CEPT 120 Ω /75 Ω ) when DS1_CEPT = 0. This feature aids in transmitting AIS at the correct rate upon completion of hardware reset; See LIU transmitter alarm indication signal generator (XLAIS) on T able 33. Table 7. Transmit Line Interface Short-Haul Equalizer/Rate Control * In DS1 mode, the distance to the DSX for 22-Gauge PIC (ABAM) cable is specified. Use the maximum cable loss figures for other cable types. In CEPT mode, equalization is specified for coaxial or twisted-pair cable. † Reset default state is EQ2, EQ1, and EQ0 = 000 when pin DS1_CEPT = 1 and EQ2, EQ1, and EQ0 = 110 when pin DS1_CEPT = 0. ‡ Loss measured at 772 kHz. § In 75 Ω applications, Option 1 is recommended over Option 2 for lower LIU power dissipation. Option 2 allows for the use of the same trans- former as in CEPT 120 Ω applications (see Line Interface Unit: Line Circuitry section). Short-Haul Applications EQ2 EQ1 EQ0 Service Clock Rate Transmitter Equalization *† Maximum Cable Loss to DSX ‡ Feet Meters dB 0 0 0 DSX-1 1.544 MHz 0 to 131 0 to 40 0.6 0 0 1 131 to 262 40 to 80 1.2 0 1 0 262 to 393 80 to 120 1.8 0 1 1 393 to 524 120 to 160 2.4 1 0 0 524 to 655 160 to 200 3.0

101 C E P T

§ 2.048 MHz 75 Ω (Option 2) —1 1 0 120 Ω or 75 Ω (Option 1)

111 N o t U s e d

Lucent Technologies Inc. 33 Preliminary Data Sheet October 2000 T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) Lucent T echnologies Inc. Line Interface Unit: Transmit (continued) LIU Transmitter Configuration Modes LIU Transmitter Zero Substitution Encoding (CODE) LIU transmitter zero substitution (B8ZS/HDB3) encod- ing can be activated only in the single-rail (DUAL = 0) system/framer interface mode. It is activated by setting CODE = 1 (register LIU_REG3, bit 2). Data transmitted from the framer interface on TPD-LIU will be B8ZS/ HDB3 encoded before appearing on TTIP and TRING at the line interface. LIU Transmitter Alarm Indication Signal Generator (XLAIS) When the transmit alarm indication signal control is set (XLAIS = 1) for a given channel (see register LIU_REG5, bit 1), a continuous stream of bipolar ones is transmitted to the line interface. The internal LIU to framer TPD interface (TPD) and internal LIU to framer TND interface (TND) signals are ignored during this mode. The XLAIS control is ignored when a remote loopback (RLOOP) is selected using loopback control bits LOOP A and LOOPB (register LIU_REG5, bits 2 to 3). The clock source used for the alarm indication sig- nal is TLCK if present or INTSYSCK if TLCK is not present. The clock tolerance must meet the nominal transmission specifications of 1.544 MHz ± 32 ppm for DS1 (T1) or 2.048 MHz ± 50 ppm CEPT (E1). The XLAIS bit is defaulted to 1 on hardware reset allowing the transmitter to send AIS as soon as clocks are available, without needing to write the LIU regis- ters *. Because the transmit equalization bits are needed to determine the correct system rate (DS1/E1), the reset default state of the equalization bits EQ2, EQ1, EQ0 (register LIU_REG6, bits 0—2) can be pre- determined by setting the DS1_CEPT pin (see T able 7). The default transmit equalization is EQ2, EQ1, and EQ0 = 000 (0 dB T1/DS1) when DS1_CEPT = 1, and EQ2, EQ1, and EQ0 = 110 (CEPT 120 Ω /75 Ω ) when DS1_CEPT = 0. The transmit equalization bits can be subsequently programmed to any state by writ- ing the LIU register regardless of the state of the DS1_CEPT pin. The DS1_CEPT pin is only used to determine the reset default state of the equalization bits. LIU Transmitter Alarms Loss of LIU Transmit Clock (LOTC) Alarm A loss of LIU transmit clock alarm (LOTC = 1, see reg- ister LIU_REG0, bit 3) is indicated if any of the clocks used in the LIU transmitter paths are absent. This includes loss of TLCK-LIU input, loss of RLCK-LIU dur- ing remote loopback, loss of jitter attenuator output clock (when enabled in transmit path), or the internal loss of clock from the pulse-width controller. For all of these conditions, the LIU transmitter timing clock is lost and no data can be driven onto the line. Output drivers TTIP and TRING are placed in a high-impedance state when this alarm is active. The LOTC alarm asserts between 3 µs and 16 µs after the clock is lost and deasserts immediately after detecting the first clock edge. The LOTC alarm status bit will latch the alarm and remain set until being cleared by a read (clear on read). Upon the transition from LOTC = 0 to LOTC = 1, an interrupt will be generated if the LOTC interrupt enable bit LOTCIE (register LIU_REG1, bit 3) is set. The reset default is LOTCIE = 0. An LOTC alarm may occur when RLOOP is activated and deactivated due to the phase transient that occurs as TLCK-LIU switches its source to and from RLCK- LIU. Setting the RLOOP alarm prevention PRLALM = 1 (register LIU_REG4, bit 3) prevents the LOTC alarm from occurring at the activation and deactivation of RLOOP but allows the alarm to operate normally dur- ing the RLOOP active period. The reset default is PRLALM = 0. LIU Transmitter Driver Monitor (TDM) Alarm The transmit driver monitor detects two conditions: a nonfunctional link due to faults on the primary of the transmit line transformer and periods of no data trans- mission. The TDM alarm (register LIU_REG0, bit 2) is the OR’d function of both faults and provides informa- tion about the integrity of the LIU transmitter signal path. * If TLCK from the framer is present, automatic transmission of AIS upon reset will occur only if the CHI common control register FRM_PR45 bit 0 = 0, the default, or low-frequency PLLCK mode. In this case, PLLCK will be equal to the line transmit rate, either 1.544 MHz for DS1 or 2.048 MHz for CEPT.

Table 8. DSX-1 Pulse Template Corner Points (from CB119, T1.102) During DS1 operation, the LIU transmitter TTIP and TRING pins will perform as specified in T able 9. Table 9. DS1 Transmitter Specifications

1. With the line circuitry specified in T able 14.
2. Measured in a 2 kHz band around the specified frequency.
3. Using Lucent transformer 2795B and components in Table 14.
4. Below the power at 772 kHz.

1.544 MHz5 29 39 — dB

During E1 operation, the LIU transmitter TTIP and TRING pins will perform as specified in T able 10. Table 10. CEPT Transmitter Specifications

1. With the line circuitry specified in Table 14, measured at the transformer secondary.
2. Using Lucent transformer 2795D or 2795C and components in Table 14.

tion. The jitter attenuator will smooth the gapped clock. output port when the applied input signal has no jitter. peak-to-peak intrinsic jitter.

1.25 Hz can be selected in CEPT operation by setting

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II) October 2000 38 Lucent Technologies Inc. Lucent T echnologies Inc. Line Interface Unit: Jitter Attenuator (continued) Jitter Accommodation The minimum jitter accommodation of the jitter attenuator occurs when the SYSCK frequency and the input clock’s long-term average frequency are at their extreme frequency tolerances. When the jitter attenuator is used in the LIU transmit path, the minimum accommodation is 28 UI peak-to-peak at the highest jitter frequency of 15 kHz. Typical receiver jitter accommodation curves including the jitter attenuator in the LIU receive path are given in Figures 12 and 14. When the jitter attenuator is placed in the data path, a difference between the SYSCK/16 frequency and the incom- ing line rate for receive applications, or the TCLK rate for transmit applications will result in degraded low- frequency jitter accommodation performance. The peak-to-peak jitter accommodation (JApp) for frequencies from above the corner frequency of the jitter attenuator (Fc) to approximately 100 Hz is given by the following equation: where: fdata = 1.544 MHz for DS1 or 2.048 MHz for E1, for JABW0 = 0, fc = 3.8 Hz for DS1 or 10 Hz for E1, and for JABW0 = 1, fc = 1.25 Hz for E1, ýfsysclk = SYSCK tolerance in ppm, ýfdata = data tolerance in ppm. Note that for lower corner frequencies the jitter accommodation is more sensitive to clock tolerance than for higher corner frequencies. When JABW0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on SYSCK should be tightened to ±20 ppm in order to meet the jitter accommodation requirements of TBR12/13 as given in G.823 for line data rates of ±50 ppm. Jitter Attenuator Enable (Transmit or Receive Path) The jitter attenuator is placed in the LIU receive path by setting JAR = 1 (register LIU_REG3, bit 0). The jitter atten- uator is selected in the LIU transmit path by setting JA T = 1 (register LIU_REG3, bit 1). When JAR = 1 and JA T = 1 or when JAR = 0 and JA T = 0, the jitter attenuator is disabled. Note that the power consumption increases slightly on a per-channel basis when the jitter attenuator is active. The reset default case is JAR = JA T = 0. JApp 64 2f sysclkΔΔ fdata–() fdata 2πfc  UI=

Block Diagram of Line Interface Unit: Single Channel. mit driver input to the receive analog front-end circuitry. the DLOS alarm monitors the looped data. framer interface and sends the data back to the line. transmit data, and the transmit AIS inputs are ignored. in isolating failures between systems. activation and deactivation of RLOOP . Table 11. Loopback Control

1. The reset default condition is LOOP A = LOOPB = 0 (no loopback).
2. During the transmit AIS condition, the looped data will be the
3. Transmit AIS request is ignored.

= 0) approximately 5 ms before data is applied. ance capability of approximately 8 kΩ .

42 Lucent Technologies Inc. Lucent T echnologies Inc. loop used for timing recovery has 8 UI delay. Table 12. SYSCK (16x, CKSEL = 1) Timing 13 as given in G.823 for line data rates of ±50 ppm. rate reference clock are defined in Table 13. Table 13. SYSCK (1x, CKSEL 13 as given in G.823 for line data rates of ±50 ppm.

14, based on the specific application. Figure 16. Line Termination Circuitry

44 Lucent Technologies Inc. Lucent T echnologies Inc. Table 14. Termination Components by Application1

1. Resistor tolerances are ±1%. T ransformer turns ratio tolerances are ±2%.
2. Use Lucent 2795B transformer.
3. For CEPT 75 Ω applications, Option 1 is recommended over Option 2 for lower device power dissipation. Option 2 increases power dissipa-

tion by 13 mW per channel when driving 50% ones data. Option 2 allows for the use of the same transformer as in CEPT 120 Ω applications.

1. Use Lucent 2795D transformer.
2. Use Lucent 2795C transformer.
3. A ±5% tolerance is allowed for the transmit load termination.

receiver and the equivalent output circuit of the transmitter can be assumed to be as shown in Figure 17.

• Approximately 0.3 V—2.0 V peak.

†Approximate pulse voltage source (peak). Figure 17. T7630 Line Interface Unit Approximate Equivalent Analog I/O Circuits

46 Lucent Technologies Inc. Lucent T echnologies Inc. transmit and receive framer units. Figure 18. Block Diagram of Framer Line Interface

48 Lucent Technologies Inc. Lucent T echnologies Inc. Table 15. AMI Encoding with a one. The line format (shown in T able 16) limits the data rate of each time slot from 64 kbits/s to 56 kbits/s. (as defined in the signaling control registers with the F and G bits). Table 16. DS1 ZCS Encoding with the original string of eight zeros. on either RPD or RND). Both excessive zeros and coding violations are indicated as bipolar violations.

represents a violation of the bipolar rule, and B represents an inserted pulse conforming to the AMI rule. Table 17. DS1 B8ZS Encoding The line code used for CEPT is described in ITU Rec. G.703 Section 6.1 as high-density bipolar of order 3 (HDB3). Table 18. ITU HDB3 Coding and without CRC-4 multiframe formatting. This section describes these framing formats. T1 system is the lowest level of hierarchy on the North American T -carrier system, as shown in Figure 20. Table 19. T -Carrier Hierarchy

50 Lucent Technologies Inc. Lucent T echnologies Inc. Figure 20. T1 Frame Structure (FRM_PR26 bit 3 or bit 4 must be set to 1). data and insert it into bit 7 of time slot one of the system data; the other bits of time slot 1 are set to 0. Frame integrity is maintained in both the transmit and receive framer sections.

Figure 21. T1 Transparent Frame Structure will insert the 193rd bit of the receive line data into bit 8 of time slot 1 of the transmit system data. bits in time slot 1 are set to zero.

32 TIME-SLOT CHI FRAMETIME SLOT 2 TIME SLOT 3 TIME SLOT 31 TIME SLOT 32

0000000 F B I T

52 Lucent Technologies Inc. Lucent T echnologies Inc. D4 superframe format consists of 12 DS1 frames. Table 20 shows the structure of the D4 superframe. Table 20. D4 Superframe Format

1. Frame 1 is transmitted first.
2. Following ANSI T1.403, the bits are numbered 0—2315. Bit 0 is transmitted first. Bits in each DS0 time slot are numbered 1 through 8, and bit

1 of each DS0 is transmitted first.

1. The remote alarm forces bit 2 of each time slot to a 0-state when enabled. The Japanese remote alarm forces framing bit 12 (bit number

2123) to a 1-state when enabled.

1. Signaling option none uses bit 8 for traffic data.
2. Frames 6 and 12 contain the robbed-bit signaling information in bit 8 of each voice channel, when enabled.

The receive framer uses both the FT and FS framing bits during its frame alignment procedure. facility data link timing is shown in Figure 22 below. Table 21. DDS Channel-24 Format

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II) October 2000 54 Lucent Technologies Inc. Lucent T echnologies Inc. Frame Formats (continued) External TFDL Source. Data may be inserted and extracted from the SLC -96 data link from either the external facility data link (TFDL) ports or the SLC -96 data stack. Source selection is controlled by FRM_PR21 bit 6 and FRM_PR29 bit 5—bit 7. The transmit framer synchronizes on TFDL = 000111000111 . . . and forces a superframe boundary based on this pattern. When sourcing an external bit stream, it is the system’s responsibility to ensure that TFDL data contain the line switch field. Table 22. SLC -96 Data Link Block Format Data Link Block Bit Definition Bit Value D 1 (leftmost bit) C 1—concentrator bit 0 or 1 D 2 C 2—concentrator bit 0 or 1 D 3 C 3—concentrator bit 0 or 1 D 4 C 4—concentrator bit 0 or 1 D 5 C 5—concentrator bit 0 or 1 D 6 C 6—concentrator bit 0 or 1 D 7 C 7—concentrator bit 0 or 1 D 8 C 8—concentrator bit 0 or 1 D 9 C 9—concentrator bit 0 or 1 D 10 C 10—concentrator bit 0 or 1 D 11 C 11—concentrator bit 0 or 1 D 12 Spoiler bit 1 0 D 13 Spoiler bit 2 1 D 14 Spoiler bit 3 0 D 15 M 1—maintenance bit 0 or 1 D 16 M 2—maintenance bit 0 or 1 D 17 M 3—maintenance bit 0 or 1 D 18 A1—alarm bit 0 or 1 D 19 A2—alarm bit 0 or 1 D 20 S1—line-switch bit Defined in T able 23 D 21 S2—line-switch bit Defined in T able 23 D 22 S3—line-switch bit Defined in T able 23 D 23 S4—line-switch bit Defined in T able 23 D 24 (rightmost bit) Spoiler bit 4 1

Table 23. SLC -96 Line Switch Message Codes the FDL information in the SLC -96 frame format. parameter registers FRM_PR21 bit 6 = 1 and FRM_PR29 bit 5—bit 7 = x10 (binary). is halted and neither the receive stack interrupt nor receive stack flag are asserted. Table 24. Transmit and Receive SLC -96 Stack Structure

1111 I d l e

1110 S w i t c h l i n e A r e c e i v e

1101 S w i t c h l i n e B t r a n s m i t

1100 S w i t c h l i n e C t r a n s m i t

1010 S w i t c h l i n e D t r a n s m i t

0101 S w i t c h l i n e B t r a n s m i t a n d r e c e i v e

0100 S w i t c h l i n e B t r a n s m i t a n d r e c e i v e

0010 S w i t c h l i n e B t r a n s m i t a n d r e c e i v e

1 C 2 C 3 C 4 C 5 C 6 C 7 C 8

the transmit SLC -96 superframe structure. is not updated when superframe alignment is lost.

56 Lucent Technologies Inc. Lucent T echnologies Inc. alignment, error checking, and facility data link transport. T able 25 shows the ESF frame format. Table 25. Extended Superframe (ESF) Structure

1. Frame 1 is transmitted first.
2. The remote alarm is a repeated 1111111100000000 pattern in the DL when enabled.
3. Following ANSI T1.403, the bits are numbered 0—4361. Bit 0 is transmitted first. Bits in each DS0 time slot are numbered 1 through 8, and bit

1 of each DS0 is transmitted first.

1. The C1 to C6 bits are the cyclic redundancy check-6 (CRC-6) checksum bits calculated over the previous extended superframe.
2. Signaling option none uses bit 8 for traffic data.
3. Frames 6, 12, 18, and 24 contain the robbed-bit signaling information in bit 8 of each voice channel, when enabled.

and diagnostics (4 kbits/s).

■ For the purpose of CRC-6 calculation only, every F bit in ESF(n) is set to 1. ESF(n) is altered in no other way. first bit of ESF(n) is the coefficient of the term x4631 and the last bit of ESF(n) is the coefficient of the term x0. position of the framing bits. detect a loss of frame alignment is given is T able 26. Table 26. T1 Loss of Frame Alignment Criteria the LFA state, the system may transmit an alarm indication signal (AIS) to the system interface. T or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1. 2 errored FT bits out of 4 consecutive FT bits if PRM_PR10 bit 2 = 0. SLC -96 2 errored frame bits (F T or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1. 2 errored FT bits out of 4 consecutive FT bits if FRM_PR10 bit 2 = 0. DDS: Frame 3 errored frame bits (FT or FS) or channel 24 FAS pattern out of 12 consecutive frame bits.

58 Lucent Technologies Inc. Lucent T echnologies Inc. for establishing T1 frame and superframe alignment. Table 27. T1 Frame Alignment Procedures frame alignment is determined. S bits must be received error-free to establish superframe alignment. frame alignment is established, then superframe alignment is determined. first valid superframe bit sequence 000111000111. error-free. In the DDS format, there is no search for a superframe structure.

T o enable signaling, register FRM_PR44 bit 0 (TSIG) must be set to 0. and G bits. T able 28 shows the state of the transmitted signaling bits as a function of the F and G bits. Table 28. Robbed-Bit Signaling Options

• See register FRM_PR43 bit 3 and bit 4.

setting the F and G bits in the transmit signaling direction. from either 0 to 1 or 1 to 0, of the transmitted signaling bit. In the line receive direction, this signaling mode functions identically to the preceding transmit path description.

60 Lucent Technologies Inc. Lucent T echnologies Inc. superframe, while A’ and B’ are transmitted into the next successive SLC -96 12-frame signaling superframe. In the line receive direction, this signaling mode functions identically to the preceding transmit path description. Table 30. 16-State Signaling Format

frame structures are illustrated in Figure 24. Figure 24. ITU 2.048 Basic Frame, CRC-4 Multiframe, and Channel Associated Signaling Multiframe

17 TO 31 ARE ASSIGNED TO TELEPHONE

CHANNELS NUMBERED FROM 1 TO 30.

8 kHz. The allocation of bits numbered 1 to 8 of the frame is shown in T able 31. Table 31. Allocation of Bits 1 to 8 of the FAS Frame and the NOT FAS Frame digital paths crossing an international border. in avoiding simulations of the frame alignment signal. alarm condition, set to one. to one on links crossing an international border. ■ MSB = most significant bit and is transmitted first. ■ LSB = least significant bit and is transmitted last. ister (FRM_PR26) on page 174). slot of the transmit line interface. Figure 25. CEPT Transparent Frame Structure payload is transmitted unmodified to the CHI. of receive line data is performed and data is transmitted to the CHI as programmed.

Lucent Technologies Inc. 63 Preliminary Data Sheet October 2000 T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) Lucent T echnologies Inc. Frame Formats (continued) CEPT Loss of Basic Frame Alignment (LFA) Frame alignment is assumed to be lost when: ■ As described in ITU Rec. G.706 Section 4.1.1, three consecutive incorrect frame alignment signals have been received. ■ So as to limit the effect of spurious frame alignment signals, when bit 2 in time slot 0 in NOT FAS frames have been received with an error on three consecu- tive occasions. ■ Optionally, as described in ITU Rec. G.706 Section 4.3.2, by exceeding a count of >914 errored CRC-4 blocks out of 1000, with the understanding that a count of ≥915 errored CRC blocks indicates false frame alignment. ■ On demand via the control registers. In the LFA state: ■ No additional FAS or NOT FAS errors are processed. ■ The received remote frame alarm (received A bit) is deactivated. ■ All NOT -FAS bit (Si bit, A bit, and Sa4 to Sa8 bits) processing is halted. ■ Receive Sa6 status bits are set to 0. ■ Receive Sa6 code monitoring and counting is halted. ■ All receive Sa stack data updates are halted. The receive Sa stack ready, register FRM_SR4 bit 6 and bit 7, is set to 0. If enabled, the receive Sa stack interrupt bit is set to 0. ■ Receive data link (RFDL) is set to 1 and RFDCLK maintains previous alignment. ■ Optionally, the remote alarm indication (A = 1) may be automatically transmitted to the line if register FRM_PR27 bit 0 is set to 1. ■ Optionally, the alarm indication signal (AIS) may be automatically transmitted to the system if register FRM_PR19 bit 0 is set to 1. ■ If CRC-4 is enabled, loss of CRC-4 multiframe align- ment is forced. ■ If CRC-4 is enabled, the monitoring and processing of CRC-4 checksum errors is halted. ■ If CRC-4 is enabled, all monitoring and processing of received E-bit information is halted. ■ If CRC-4 is enabled, the receive continuous E-bit alarm is deactivated. ■ If CRC-4 is enabled, optionally, E bit = 0 is transmit- ted to the line for the duration of loss of CRC-4 multi- frame alignment if register FRM_PR28 bit 4 is set to ■ If time slot 16 signaling is enabled, loss of the signal- ing multiframe alignment is forced. ■ If time slot 16 signaling is enabled, updating of the signaling data is halted. CEPT Loss of Frame Alignment Recovery Algorithm The receive framer begins the search for basic frame alignment one bit position beyond the position where the LFA state was detected. As defined in ITU Rec. G.706.4.1.2, frame alignment will be assumed to have been recovered when the following sequence is detected: ■ For the first time, the presence of the correct frame alignment signal in frame ■ The absence of the frame alignment signal in the fol- lowing frame detected by verifying that bit 2 of the basic frame is a 1 in frame n + 1. ■ For the second time, the presence of the correct frame alignment in the next frame, n + 2. Failure to meet the second or third bullet above will ini- tiate a new basic frame search in frame n + 2.

64 Lucent Technologies Inc. Lucent T echnologies Inc. T able 32 for the complete CRC-4 multiframe. Table 32. ITU CRC-4 Multiframe Structure C1 to C4 = cyclic redundancy check-4 (CRC-4) bits. E = CRC-4 error indication bits. A = remote frame alarm (RFA) bit (active-high); referred to as the A bit. should be set to a binary 1 state.

• The receive E-bit processor will halt the monitoring of the received E bit during the loss of CRC-4 multiframe alignment.

2 C 2 0 011011

4 C 3 0 011011

6 C 4 0 011011

10 C2 0 0 1 1 0 1 1

12 C3 0 0 1 1 0 1 1

13 E 1 A Sa4 Sa5 Sa6 Sa7 Sa8

14 C4 0 0 1 1 0 1 1

15 E 1 A Sa4 Sa5 Sa6 Sa7 Sa8

Lucent Technologies Inc. 65 Preliminary Data Sheet October 2000 T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) Lucent T echnologies Inc. Frame Formats (continued) The CRC-4 word, located in submultiframe N, is the remainder after multiplication by x4 and then division (modulo 2) by the generator polynomial x4 + x + 1, of the polynomial representation of the submultiframe N – 1. Representing the contents of the submultiframe check block as a polynomial, the first bit in the block, i.e., frame 0, bit 1 or frame 8, bit 1, is taken as being the most significant bit and the least significant bit in the check block is frame 7 or frame 15, bit 256. Similarly, C 1 is defined to be the most significant bit of the remainder and C4 the least significant bit of the remain- der. The encoding procedure, as described in ITU Rec. ■ The CRC-4 bits in the SMF are replaced by binary zeros. ■ The SMF is then acted upon the multiplication/divi- sion process referred to above. ■ The remainder resulting from the multiplication/divi- sion process is stored, ready for insertion into the respective CRC-4 locations of the next SMF . The decoding procedure, as described in ITU Rec. ■ A received SMF is acted upon by the multiplication/ division process referred to above, after having its CRC-4 bits extracted and replaced by zeros. ■ The remainder resulting from this division process is then stored and subsequently compared on a bit-by- bit basis with the CRC bits received in the next SMF . ■ If the remainder calculated in the decoder exactly corresponds to the CRC-4 bits received in the next SMF , it is assumed that the checked SMF is error- free. CEPT Loss of CRC-4 Multiframe Alignment (LTS0MFA) Loss of basic frame alignment forces the receive framer into a loss of CRC-4 multiframe alignment state. This state is reported by way of the status registers FRM_SR1 bit 2. Once basic frame alignment is achieved, a new search for CRC-4 multiframe align- ment is initiated. During a loss of CRC-4 multiframe alignment state: ■ The CRC-4 error counter is halted. ■ The CRC-4 error monitoring circuit for errored sec- onds and severely errored seconds is halted. ■ The received E-bit counter is halted. ■ The received E-bit monitoring circuit for errored sec- onds and severely errored seconds at the remote end interface is halted. ■ Receive continuous E-bit monitoring is halted. ■ All receive Sa6 code monitoring and counting func- tions are halted. ■ The updating of the receive Sa stack is halted and the receive Sa stack interrupt is deactivated. ■ Optionally, A = 1 may be automatically transmitted to the line if register FRM_PR27 bit 2 is set to 1. ■ Optionally, E = 0 may be automatically transmitted to the line if register FRM_PR28 bit 4 is set to 1. ■ Optionally, if LTS0MFA monitoring in the perfor- mance counters is enabled, by setting registers FRM_PR14 through FRM_PR17 bit 1 to 1, then these counts are incremented once per second for the duration of the LTS0MFA state.

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II) October 2000 66 Lucent Technologies Inc. Lucent T echnologies Inc. Frame Formats (continued) CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms Several optional algorithms exist in the receive framer. These are selected through programming of register FRM_PR9. CRC-4 Multiframe Alignment Algorithm with 8 ms Timer The default algorithm is as described in ITU Rec. G.706 Section 4.2. The recommendation states that if a condition of assumed frame alignment has been achieved, CRC-4 multiframe alignment is deemed to have occurred if at least two valid CRC-4 multiframe alignment signals can be located within 8 ms, the time separating two CRC-4 multiframe signals being 2 ms or a multiple of 2 ms. The search for the CRC-4 multi- frame alignment signal is made only in bit 1 of NOT FAS frames. If multiframe alignment cannot be achieved within 8 ms, it is assumed that frame align- ment is due to a spurious frame alignment signal and a new parallel search for basic frame alignment is initi- ated. The new search for the basic frame alignment is started at the point just after the location of the assumed spurious frame alignment signal. During this parallel search for basic frame alignment, there is no indication to the system of a receive loss of frame align- ment (RLFA) state. During the parallel search for basic frame alignment and while in primary basic frame align- ment, data will flow through the receive framer to the system interface as defined by the current primary frame alignment. The receive framer will continuously search for CRC-4 multiframe alignment. CRC-4 Multiframe Alignment Algorithm with 100 ms Timer The CRC-4 multiframe alignment with 100 ms timer mode is enabled by setting FRM_PR9 to 0XXXX1X1 (binary). This CRC-4 multiframe reframe mode starts a 100 ms timer upon detection of basic frame alignment. This is a parallel timer to the 8 ms timer. If CRC-4 multi- frame alignment cannot be achieved within the time limit of 100 ms due to the CRC-4 procedure not being implemented at the transmitting side, then an indication is given and actions are taken equivalent to those spec- ified for loss of basic frame alignment, namely: ■ Optional automatic transmission of A = 0 to the line if register FRM_PR27 bit 3 is set to 1. ■ Optional automatic transmission of E = 0 to the line if register FRM_PR28 bit 5 is set to 1. ■ Optional automatic transmission of AIS to the system if register FRM_PR19 bit 1 is set to 1.

Figure 26. Receive CRC-4 Multiframe Search Algorithm Using the 100 ms Internal Timer

• OPTIONALLY DISABLE TRAFFIC BY TRANSMITTING AIS TO THE SYSTEM
• OPTIONALLY TRANSMIT A = 1 AND E = 0 TO LINE
• INHIBIT INCOMING CRC-4 PERFORMANCE MONITORING BFA SEARCH? IN PRIMARY BFA:
• ENABLE TRAFFIC TO THE SYSTEM
• TRANSMIT A = 0 AND OPTIONALLY E = 0 TO THE LINE
• START 8 ms AND 100 ms TIMERS
• ENABLE PRIMARY BFA LOSS CHECKING PROCESS CRC-4 MFA SEARCH (ITU REC. G.706, SECTION 4.2 - NOTE 2 ) CAN CRC-4 MFA BE FOUND IN 8 ms? PARALLEL BFA SEARCH 100 ms TIMER ELAPSED? YES NO NO NO YES YES ASSUME CRC-4 MULTIFRAME ALIGNMENT:
• CONFIRM PRIMARY BFA ASSOCIATED WITH CRC-4 MFA
• ADJUST PRIMARY BFA IF NECESSARY SET 100 ms TIMER EXPIRATION STATUS BIT TO THE 1 STATE:
• OPTIONALLY TRANSMIT A BIT = 1 TO THE LINE INTERFACE FOR THE DURATION OF LTS0MFA = 1
• OPTIONALLY TRANSMIT AIS TO THE SYSTEM INTERFACE FOR THE START CRC-4 PERFORMANCE MONITORING: CRC-4 COUNT > 914 IN 1 SECOND OR CONTINUE CRC-4 PERFORMANCE MONITORING: YES YES NO NO DURATION OF LTS0MFA = 1 IS 100 ms TRX = 1 YES NO SET INTERNAL 100 ms TIMER EXPIRATION STATUS BIT TO 0:
• IF TRANSMITTING A BIT = 1 TO THE LINE INTERFACE, TRANSMIT A BIT = 0
• IF TRANSMITTING AIS TO THE SYSTEM INTERFACE, ENABLE DATA TRANSMISSION TO THE SYSTEM INTERFACE LFA = 1? GOOD? IS YES NO 100 ms TRX = 1 INTERNAL SET INTERNAL 100 ms TIMER EXPIRATION STATUS BIT TO 1: PRIMARY
• IF TRANSMITTING E = 0 TO THE LINE INTERFACE, TRANSMIT E BIT = 1
• OPTIONALLY TRANSMIT E BIT = 0 TO THE LINE INTERFACE FOR THE DURATION OF LTSOMFA = 1

68 Lucent Technologies Inc. Lucent T echnologies Inc. Figure 27. When the interworking algorithm is enabled, multiframe alignment algorithm. the primary basic frame alignment. — On-demand reframe is requested. CRC-4 multiframe alignment process below it. ciated with loss of the primary basic frame alignment. sequence found during the parallel search. plete framing process, and the algorithm is reset.

Figure 27. Receive CRC-4 Multiframe Search Algorithm for Automatic, CRC-4/Non-CRC-4 Equipment

• OPTIONALLY DISABLE TRAFFIC BY TRANSMITTING AIS TO THE SYSTEM
• OPTIONALLY TRANSMIT A BIT = 1 AND E BIT = 0 TO LINE
• INHIBIT INCOMING CRC-4 PERFORMANCE MONITORING BFA SEARCH? IN PRIMARY BFA:
• ENABLE TRAFFIC NOT TRANSMITTING AIS TO THE SYSTEM
• TRANSMIT A = 0 AND OPTIONALLY E = 0 TO THE LINE
• START 400 ms TIMER
• ENABLE PRIMARY BFA LOSS CHECKING PROCESS CRC-4 MFA SEARCH (ITU REC. G.706, SECTION 4.2) CAN CRC-4 MFA BE FOUND IN 8 ms? PARALLEL BFA SEARCH 400 ms TIMER ELAPSED? YES NO NO NO YES YES ASSUME CRC-4-TO-CRC-4 INTERWORKING:
• CONFIRM PRIMARY BFA ASSOCIATED WITH CRC-4 MFA
• ADJUST PRIMARY BFA IF NECESSARY START CRC-4 PERFORMANCE MONITORING: CRC-4 COUNT > 914 IN 1 SECOND OR CONTINUE CRC-4 PERFORMANCE MONITORING: YES YES NO NO
• KEEP A = 0 IN OUTGOING CRC-4 DATA ASSUME CRC-4-TO-NON-CRC-4 INTERWORKING:
• TRANSMIT A BIT = 0 TO THE LINE INTERFACE
• STOP INCOMING CRC-4 PROCESSING
• CONFIRM PRIMARY BFA
• TRANSMIT E BIT = 0 TO THE LINE INTERFACE
• INDICATE “NO CRC-4 MFA” PRIMARY LFA = 1?

70 Lucent Technologies Inc. Lucent T echnologies Inc. CAS multiframe to the CRC-4 multiframe is arbitrary. Table 33. ITU CEPT Time Slot 16 Channel Associated Signaling Multiframe Structure Frame 0 bits 1—4 define the time slot 16 multiframe alignment. X0—X2 = time slot 16 spare bits defined in FRM_PR41 bit 0—bit 2. YM = yellow alarm, time slot 16 remote multiframe alarm (RMA) bit (1 = alarm condition).

10 A 10 B10 C 10 D 10 A25 B25 C 25 D 25

11 A 11 B11 C 11 D 11 A26 B26 C 26 D 26

12 A 12 B12 C 12 D 12 A27 B27 C 27 D 27

13 A 13 B13 C 13 D 13 A28 B28 C 28 D 28

14 A 14 B14 C 14 D 14 A29 B29 C 29 D 29

15 A 15 B15 C 15 D 15 A30 B30 C 30 D 30

Lucent Technologies Inc. 71 Preliminary Data Sheet October 2000 T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) Lucent T echnologies Inc. Frame Formats (continued) CEPT Loss of Time Slot 16 Multiframe Align- ment (LTS16MFA) Loss of basic frame alignment forces the receive framer into a loss of time slot 16 signaling multiframe align- ment state. In addition, as defined in ITU Rec. G.732 Section 5.2, time slot 16 signaling multiframe is assumed lost when two consecutive time slot 16 multi- frame 4-bit all-zero patterns is received with an error. Also, the time slot 16 multiframe is assumed lost when, for a period of two multiframes, all bits in time slot 16 are in state 0. This state is reported by way of the sta- tus registers FRM_SR1 bit 1. Once basic frame align- ment is achieved, the receive framer will initiate a search for the time slot 16 multiframe alignment. During a loss of time slot 16 multiframe alignment state: ■ The updating of the signaling data is halted. ■ The received control bits forced to the binary 1 state. ■ The received remote multiframe alarm indication sta- tus bit is forced to the binary 0 state. ■ Optionally, the transmit framer can transmit to the line the time slot 16 signaling remote multiframe alarm if register FRM_PR41 bit 4 is set to 1. ■ Optionally, the transmit framer can transmit the alarm indication signal (AIS) in the system transmit time slot 16 data if register FRM_PR44 bit 6 is set to 1. CEPT Loss of Time Slot 16 Multiframe Align- ment Recovery Algorithm The time slot 16 multiframe alignment recovery algo- rithm is as described in ITU Rec. G.732 Section 5.2. The recommendation states that if a condition of assumed frame alignment has been achieved, time slot 16 multiframe alignment is deemed to have occurred when the 4-bit time slot 16 multiframe pattern of 0000 is found in time slot 16 for the first time, and the preced- ing time slot 16 contained at least one bit in the binary 1 state. CEPT Time Slot 0 FAS/NOT FAS Control Bits FAS/NOT FAS Si- and E-Bit Source The Si bit can be used as an 8 kbits/s data link to and from the remote end, or in the CRC-4 mode, it can be used to provide added protection against false frame alignment. The sources for the Si bits that are transmit- ted to the line are the following: ■ CEPT with no CRC-4 and FRM_PR28 bit 0 = 1: the TSiF control bit (FRM_PR28 bit 1) is transmitted in bit 1 of all FAS frames and the TSiNF control bit (FRM_PR28 bit 2) is transmitted in bit 1 of all NOT FAS frames. ■ The CHI system interface (CEPT with no CRC-4 and FRM_PR28 bit 0 = 0) This option requires the received system data (RCHI- DA TA) to maintain a biframe alignment pattern where frames containing Si bit information for the NOT FAS frames have bit 2 of time slot 0 in the binary 1 state fol- lowed by frames containing Si bit information for the FAS frames that have bit 2 of time slot 0 in the binary 0 state. This ensures the proper alignment of the Si received system data to the transmit line Si data. Whenever this requirement is not met by the system, the transmit framer will enter a loss of biframe align- ment condition (indication is given in the status regis- ters) and then search for the pattern; in the loss of biframe alignment state, transmitted line data is cor- rupted (only when the system interface is sourcing Sa or Si data). When the transmit framer locates a new biframe alignment pattern, an indication is given in the status registers and the transmit framer resumes nor- mal operations. ■ CEPT with CRC-4†: manual transmission of E bit = 0: — If FRM_PR28 bit 0 = 0, then the TSiF bit (FRM_PR28 bit 1) is transmitted in bit 1 of frame 13 (E bit) and the TSiNF bit (FRM_PR28 bit 2) is transmitted in bit 1 of frame 15 (E bit). — If FRM_PR28 bit 0 = 1, then each time 0 is written into TSiF (FRM_PR28 bit 1) one E bit = 0 is trans- mitted in frame 13, and each time 0 is written into TSiNF (FRM_PR28 bit 2) one E bit = 0 is transmit- ted in frame 15. * Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system transparently, FRM_PR29 must first be momentarily written to 001xxxxx (binary). Otherwise, the transmit framer will not be able to locate the biframe alignment. The receive E-bit processor will halt the monitoring of received E bits during loss of CRC-4 multiframe alignment.

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II) October 2000 72 Lucent Technologies Inc. Lucent T echnologies Inc. CEPT Time Slot 0 FAS/NOT FAS Control Bits (continued) ■ CEPT with CRC-41, automatic transmission of E bit = 0: — Optionally, one transmitted E bit is set to 0 by the transmit framer, as described in ITU Rec. G.704 Section 2.3.3.4, for each received errored CRC-4 submultiframe detected by the receive framer if FRM_PR28 bit 3 = 1. — Optionally, as described in ITU Rec. G.704 Sec- tion 2.3.3.4, both E bits are set to 0 while in a received loss of CRC-4 multiframe alignment state 2 if FRM_PR28 bit 4 = 1. — Optionally, when the 100 ms or 400 ms timer is enabled and the timer has expired, as described in ITU Rec. G.706 Section B.2.2, both E bits are set to 0 for the duration of the loss of CRC-4 multi- frame alignment state 2 if FRM_PR28 bit 5 = 1. Otherwise, the E bits are transmitted to the line in the 1 state. NOT FAS A-Bit (CEPT Remote Frame Alarm) Sources The A bit, as described in ITU Rec. G.704 Section 2.3.2 T able 4a/G.704, is the remote alarm indication bit. In undisturbed conditions, this bit is set to 0 and trans- mitted to the line. In the loss of frame alignment (LFA) state, this bit may be set to 1 and transmitted to the line as determined by register FRM_PR27. The A bit is set to 1 and transmitted to the line for the following condi- tions: ■ Setting the transmit A bit = 1 control bit by setting register FRM_PR27 bit 7 to 1. ■ Optionally for the following alarm conditions as selected through programming register FRM_PR27. — The duration of loss of basic frame alignment as described in ITU Rec. G.706 Section 4.1.1 3, or ITU Rec. G.706 Section 4.3.24 if register FRM_PR27 bit 0 = 1. — The duration of loss of CRC-4 multiframe align- ment if register FRM_PR27 bit 2 = 1. — The duration of loss of signaling time slot 16 multi- frame alignment if register FRM_PR27 bit 1 = 1. — The duration of loss of CRC-4 multiframe align- ment after either the 100 ms or 400 ms timer expires if register FRM_PR27 bit 3 = 1. — The duration of receive Sa6_8hex 5 if register FRM_PR27 bit 4 = 1. — The duration of receive Sa6_Chex5 if register FRM_PR27 bit 5 = 1. NOT FAS Sa-Bit Sources6 The Sa bits, Sa4—Sa8, in the NOT FAS frame can be a 4 kbits/s data link to and from the remote end. The sources and value for the Sa bits are: ■ The Sa source register FRM_PR29 bit 0—bit 4 if FRM_PR29 bit 7—bit 5 = 000 (binary) and FRM_PR30 bit 4—bit 0 = 11111 (binary). ■ The facility data link external input (TFDL) if register FRM_PR29 bit 7 = 1 and register FRM_PR21 bit 6 = 1. ■ The internal FDL-HDLC if register FRM_PR29 bit 7 = 1 and register FRM_PR21 bit 6 = 0. ■ The Sa transmit stack if register FRM_PR29 bit 7—bit 5 are set to 01x (binary). ■ The CHI system interface if register FRM_PR29 bit 7—bit 5 are set to 001 (binary). This option requires the received system data (RCHIDA T A) to maintain a biframe alignment pattern where (1) frames containing Sa bit information have bit 2 of time slot 0 in the binary 1 state and (2) these NOT FAS frames are followed by frames not containing Sa bit information, the FAS frames, which have bit 2 of time slot 0 in the binary 0 state. This ensures the proper alignment of the Sa received system data to the transmit line Sa data. Whenever this requirement is not met by the system, the transmit framer will enter a loss of biframe alignment condition indicated in the status register, FRM_SR1 bit 4, and then search for the pattern. In the loss of biframe align- ment state, transmitted line data is corrupted (only when the system interface is sourcing Sa or Si data). When the transmit framer locates a new biframe alignment pattern, an indication is given in the status registers and the transmit framer resumes normal operations. 1. The receive E-bit processor will halt the monitoring of received E bits during loss of CRC-4 multiframe alignment. 2. Whenever loss of frame alignment occurs, then loss of CRC-4 multiframe alignment is forced. Once frame alignment is estab- lished, then and only then, is the search for CRC-4 multiframe alignment initiated. The receive framer unit, when programmed for CRC-4, can be in a state of LFA and LTS0MFA or in a state of L TS0MFA only, but cannot be in a state of LFA only. 3. LFA is due to framing bit errors. 4. LFA is due to detecting 915 out of 1000 received CRC-4 errored blocks. 5. See T able 41 Sa6 Bit Coding Recognized by the Receive Framer, for a definition of this Sa6 pattern. 6. Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system transparently, FRM_PR29 must first be momentarily written to 001xxxxx (binary). Otherwise, the transmit framer will not be able to locate the biframe alignment.

■ The Sa received stack, registers FRM_SR54—FRM_SR63, if the T7630 is programmed in the Sa stack mode. ■ The system transmit interface. and receive Sa bit for the FDL can be selected by setting register FRM_PR43 bit 0—bit 2 as shown in Table 166. Figure 28. Facility Data Link Access Timing of the Transmit and Receive Framer Sections in the CEPT

74 Lucent Technologies Inc. Lucent T echnologies Inc. Sa stack consists of ten 8-bit registers that contain 16 NOT FAS frames of Sa information as shown in Table 34. The transmit stack data may be transmitted either in non-CRC-4 mode or in CRC-4 mode to the line. receive stack interrupts are deactivated. Table 34. Transmit and Receive Sa Stack Structure to the transmit CRC-4 multiframe structure.

1 Sa4-1 Sa4-3 Sa4-5 Sa4-7 Sa4-9 Sa4-11 Sa4-13 Sa4-15

2 Sa4-17 Sa4-19 Sa4-21 Sa4-23 Sa4-25 Sa4-27 Sa4-29 Sa4-31

3 Sa5-1 Sa5-3 Sa5-5 Sa5-7 Sa5-9 Sa5-11 Sa5-13 Sa5-15

4 Sa5-17 Sa5-19 Sa5-21 Sa5-23 Sa5-25 Sa5-27 Sa5-29 Sa5-31

5 Sa6-1 Sa6-3 Sa6-5 Sa6-7 Sa6-9 Sa6-11 Sa6-13 Sa6-15

6 Sa6-17 Sa6-19 Sa6-21 Sa6-23 Sa6-25 Sa6-27 Sa6-29 Sa6-31

7 Sa7-1 Sa7-3 Sa7-5 Sa7-7 Sa7-9 Sa7-11 Sa7-13 Sa7-15

8 Sa7-17 Sa7-19 Sa7-21 Sa7-23 Sa7-25 Sa7-27 Sa7-29 Sa7-31

9 Sa8-1 Sa8-3 Sa8-5 Sa8-7 Sa8-9 Sa8-11 Sa8-13 Sa8-15

10 Sa8-17 Sa8-19 Sa8-21 Sa8-23 Sa8-25 Sa8-27 Sa8-29 Sa8-31

Figure 29. Transmit and Receive Sa Stack Accessing Protocol

• BASIC FRAME ALIGNMENT FOUND, OR,
• CRC-4 MULTIFRAME ALIGNMENT FOUND.

31 FRAMES

REGISTERS DURING THIS 1-FRAME INTERVAL. DURING THIS 1-FRAME INTERVAL. CRC-4 DOUBLE MULTIFRAME, ALIGNED TO THE CRC-4 MULTIFRAME. THE INTERNAL RECEIVE STACK INFORMATION REGISTERS. (32 FRAMES), AND DATA IS EXTRACTED ONLY IN THE FRAME ALIGNED STATE. DATA IS EXTRACTED ONLY IN CRC-4 MULTIFRAME ALIGNED STATE.

1 FRAME

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II) October 2000 76 Lucent Technologies Inc. Lucent T echnologies Inc. CEPT Time Slot 0 FAS/NOT FAS Control Bits (continued) Interrupts indicating the transmit Sa stack or the receive Sa stack are ready for system access are avail- able, see register FRM_SR4 bit 6 and bit 7. CEPT Time Slot 16 X0—X2 Control Bits Each of the three X bits in frame 0 of the time slot 16 multiframe can be used as a 0.5 kbits/s data link to and from the remote end. The transmitted line X bits are sourced from control register FRM_PR41 bit 0—bit 2. In the loss of TS16 multiframe alignment (LTS16MFA) state, receive X bits are set to 1 in status register FRM_SR53. Signaling Access Signaling information can be accessed by three differ- ent methods: transparently through the CHI, via the control registers, or via the CHI associated signaling mode. Transparent Signaling This mode is enabled by setting register FRM_PR44 bit 0 to 1. Data at the received RCHIDA T A interface passes through the framer undisturbed. The framer generates an arbitrary signaling multiframe in the transmit and receive directions to facilitate the access of signaling information at the system interface. DS1: Robbed-Bit Signaling Microprocessor Control Registers T o enable signaling, register FRM_PR44 bit 0 must be set to 0 (default). The information written into the F and G bits of the transmit signaling registers, FRM_TSR0— FRM_TSR23, defines the robbed-bit signaling mode for each channel for both the transmit and receive direc- tions. The per-channel programming allows the system to combine voice channels with data channels within the same frame. The receive-channel robbed-bit signaling mode is always defined by the state of the F and G bits in the corresponding transmit signaling registers for that channel. The received signaling data is stored in the receive signaling registers, FRM_RSR0— FRM_RSR23, while receive framer is in both the frame and superframe alignment states. Updating the receive signaling registers can be inhibited on-demand, by set- ting register FRM_PR44 bit 3 to 1, or automatically when either a framing error event, a loss of frame, or superframe alignment state is detected or a controlled slip event occurs. The signaling inhibit state is valid for at least 32 frames after any one of the following: a framing errored event, a loss of frame and/or super- frame alignment state, or a controlled slip event. In the common channel signaling mode, data written in the transmit signaling registers is transmitted in chan- nel 24 of the transmit line bit stream. The F and G bits are ignored in this mode. The received signaling data from channel 24 is stored in receive signaling registers FRM_RSR0—FRM_RSR23 for T1. Associated Signaling Mode This mode is enabled by setting register FRM_PR44 bit 2 to 1. Signaling information in the associated signaling mode (ASM) is allocated an 8-bit system time slot in conjunc- tion with the pay load data information for a particular channel. The default system data rate in the ASM mode is 4.096 Mbits/s. Each system channel consists of an 8-bit payload time slot followed by its correspond- ing 8-bit signaling time slot. The format of the signaling byte is identical to that of the signaling registers. In the ASM mode, writing the transmit signaling regis- ters will corrupt the transmit signaling data. In the trans- mit signaling register ASM (TSR-ASM) format, enabled by setting register FRM_PR44 bit 2 and bit 5 to 1, the system must write into the F and G bit 1 of the transmit signaling registers to program the robbed-bit signaling state mode of each DS0. The ABCD bits are sourced from the RCHI ports when TSR-ASM mode is enabled. 1. All other bits in the signaling registers are ignored, while the F and G bits in the received RCHIDA T A stream are ignored.

T able 35 illustrates the ASM time-slot format for valid channels. Table 35. Associated Signaling Mode CHI 2-Byte Time-Slot Format for DS1 Frames

• X indicates bits that are undefined by the framer.

echoed back to the system in the received signaling information. the programmable idle code in register FRM_PR23 (default = 7F (hex)), while the signaling byte is ignored. Table 36. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels

• X indicates bits which are undefined by the framer.

T o enable signaling, register FRM_PR44 bit 0 must be set to 0 (default). ABCD bits of time slot 16 transmitted to the line. The received signaling data from time slot 16 is stored in receive signaling registers FRM_RSR0—FRM_RSR31. ated 8-bit signaling time slot. The format of the signaling byte is identical to the signaling registers. T able 37 illustrates the ASM time-slot format for valid CEPT E1 time slots. Table 37. Associated Signaling Mode CHI 2-Byte Time-Slot Format for CEPT

• In the CEPT formats, these bits are undefined.

80 Lucent Technologies Inc. Lucent T echnologies Inc. Figure 34. Timing Specification for RCRCMFS in CEPT Mode Figure 35. Timing Specification for TFS, TLCK, and TPD in CEPT Mode Figure 36. Timing Specification for TFS, TLCK, TPD, and TSSFS in CEPT Mode

11 CLOCK CYCLES

82 Lucent Technologies Inc. Lucent T echnologies Inc. Table 38. Red Alarm or Loss of Frame Alignment Conditions

1. Yellow alarm or the remote frame alarm (FRM_SR1 bit 0).

alarm (commonly referred to as a yellow alarm) as for the different framing formats is shown in Table 39. Table 39. Remote Frame Alarm Conditions

1. Blue alarm or the alarm indication signal (AIS).

out of service. Detection of an incoming alarm indication signal is defined in T able 40. Table 40. Alarm Indication Signal Conditions D4 2 errored frame bits (F T or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1. 2 errored FT bits out of 4 consecutive FT bits if PRM_PR10 bit 2 = 0. SLC -96 2 errored frame bits (F T or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1. 2 errored FT bits out of 4 consecutive FT bits if FRM_PR10 bit 2 = 0. DDS: Frame 3 errored frame bits (F T or FS) or channel 24 FAS pattern out of 12 consecutive frame bits. errors is enabled in FRM_PR9. loss of frame alignment due to excessive CRC-6 errors is enabled in FRM_PR9. Superframe: D4 Bit 2 of all time slots in the 0 state. Superframe: D4-Japanese The twelfth framing bit in the 1 state in two out of three consecutive superframes. Superframe: DDS Bit 6 of time slot 24 in the 0 state. Extended Superframe (ESF) An alternating pattern of eight ones followed by eight zeros in the ESF data link. CEPT: Basic Frame Bit 3 of the NOT FAS frame in the 1 state in three consecutive frames. CEPT: Signaling Multiframe Bit 6 of the time slot 16 signaling frame in the 1 state. two consecutive double frame periods (386 bits). by setting register FRM_PR10 bit 1 to 0. been found. This is enabled by setting register FRM_PR10 bit 1 to 1.

1. The SLIP condition (FRM_SR3 bit 6 and bit 7).

and the read address pointer from the transmit CHI are equal*. the received frame being less than that of the system frame. One system frame is deleted. received frame being greater than that of the system frame. One system frame is repeated.

1. The loss of framer receive clock (LOFRMRLCK, pins 2 and 38).

does not toggle for 250 µs. The alarm is disabled on the first transition of SYSCK.

1. The loss of PLL clock (LOPLLCK, pins 39 and 143).

alarm is disabled 250 µs after the first transition of PLLCK. Timing for LOPLLCK is shown in Figure 39. Figure 39. Timing for Generation of LOPLLCK (Pin 39/143)

1. Received bipolar violation errors alarm, FRM_SR3 bit 0.

This alarm indicates any bipolar decoding error or detection of excessive zeros.

1. Received excessive CRC errors alarm, FRM_SR3 bit 3.

• After a reset, the read and write pointers of the receive path elastic store will be set to a known state.

84 Lucent Technologies Inc. Lucent T echnologies Inc.

1. The CEPT continuous E-bit alarm (CREBIT)

≥991 received E bits = 0 events. — Simultaneously no LFA occurred. — CRC-4 multiframe alignment is achieved. FRM_PR9 bit 0, bit 4, and bit 5 are set to 1. FRM_PR9 bit 0, bit 4, and bit 5 are set to 1.

1. Failed state alarm or the unavailable state alarm,
2. The 4-bit Sa6 codes (FRM_SR2 bit 3—bit 7).

indicated in status register FRM_SR2 bit 3—bit 7. Table 41. Sa6 Bit Coding Recognized by the for a definition of this Sa6 pattern.

structure and are only used for counting NT1 events. Table 42. Sa6 Bit Coding Recognized by the Receive Frame-Synchronous Bit Stream The reference points for receive CRC-4, E bit, and Sa6 decoding are illustrated in Figure 40. Figure 40. The T and V Reference Points for a Typical CEPT E1 Application

1. CEPT auxiliary pattern alarm (AUXP) (FRM_SR1 bit 6).

(binary) pattern as shown in Table 43. Table 43. AUXP Synchronization and Clear Sychronization Process

86 Lucent Technologies Inc. Lucent T echnologies Inc. as required by system needs. DS1 errors are reported in the ET error registers, FRM_SR20 through FRM_SR35. Table 44. Event Counters Definition bit errors (FRM_PR10 bit 2 = 0). bit errors (FRM_PR10 bit 2 = 0). SF: DDS Any F T, FS, or time slot 24 FAS bit error. CEPT Any FAS (0011011) or NOT FAS (bit 2) bit error. CEPT with CRC ≥915 checksum errors in a one second interval. DS1: non ESF Any framing bit errors within a one second interval. DS1: ESF Any CRC-6 errors within a one second interval. Any framing errors within a one second interval. Any CRC-4 errors within a one second interval. Any E bit = 0 event within a one second interval.

Table 44. Event Counters Definition (continued) consecutive seconds which were not severely errored. within a one second interval. within a one second interval. within a one second interval. code events within a one second interval. code events within a one second interval.

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II) October 2000 88 Lucent Technologies Inc. Lucent T echnologies Inc. Alarms and Performance Monitoring (continued) Loopback and Transmission Modes Primary Loopback Modes Framer primary loopback mode is controlled by register FRM_PR24. There are seven primary loopback and transmission test modes supported: ■ Line loopback (LLB). ■ Board loopback (BLB). ■ Single time-slot system loopback (STSSLB). ■ Single time-slot line loopback (STSLLB). ■ CEPT nailed-up broadcast transmission (CNUBT). ■ Payload loopback (PLLB). ■ CEPT nailed-up connect loopback (CNUCLB). The loopback and transmission modes are described in detail below: ■ The LLB mode loops the receive line data and clock back to the transmit line. The received data is pro- cessed by the receive framer and transmitted to the system interface. This mode can be selected by set- ting register FRM_PR24 to 001xxxxx (binary). ■ The BLB mode loops the receive system data back to the system after: — The transmit framer processes the data, and — The receive framer processes the data. — In the BLB mode, AIS is always transmitted to the line interface. This mode can be selected by set- ting register FRM_PR24 to 010xxxxx (binary). ■ The STSSLB mode loops one and only one received system time slot back to the transmit system inter- face. The selected looped back time-slot data is not processed by either the transmit framer or the receive framer. The selected time slot does not pass through the receive elastic store buffer and therefore will not be affected by system-AIS, RLFA conditions, or controlled slips events. Once selected, the desired time-slot position has the programmable idle code in register FRM_PR22 transmitted to the line interface one frame before implementing the loopback and for the duration of the loopback. This mode can be selected by setting register FRM_PR24 to 011A 4A3A2A1A0, where A4A3A2A1A0 is the binary address of the selected time slot. ■ The STSLLB mode loops one and only one received line time slot back to the transmit line. The selected time-slot data is looped to the line after being pro- cessed by the receive framer, and it passes through the receive elastic store. The selected time slot has the programmable idle code in register FRM_PR22 transmitted to the system interface one frame before implementing the loopback and for the duration of the loopback. In CEPT, selecting time slot 0 has the effect of deactivating the current loopback mode while no other action will be taken (time slot 0 will not be looped back to the line and should not be cho- sen). This mode can be selected by setting register FRM_PR24 to 100A 4A3A2A1A0, where A4A3A2A1A0 is the binary address of the selected time slot. ■ The CNUBT mode transmits received-line time slot X to the system in time slots X and time slot 0 (of the next frame). Any time slot can be broadcast. This mode can be selected by setting register FRM_PR24 to 101A 4A3A2A1A0 where A4A3A2A1A0 is the binary address of the selected time slot. ■ The PLLB mode loops the received line data and clock back to the transmit line while inserting (replac- ing) the facility data link in the looped back data. Two variations of the payload loopback are available. In the pass through framing/CRC bit mode (chosen by setting register FRM_PR24 to 111xxxxx (binary)), the framing and CRC bits are looped back to the line transmit data. In the regenerated framing/CRC bit mode (chosen by setting register FRM_PR24 to 110xxxxx (binary) and register FRM_PR10 bit 3 to 0), the framing and CRC bits are regenerated by the transmit framer. The payload loopback is only avail- able for ESF and CEPT modes. ■ The CNUCLB mode loops received system time slot X back to the system in time slot 0. The selected time slot is not routed through the receive elastic store buffer and therefore will not be affected by system- AIS, RLFA conditions, or controlled slips. Any time slot can be looped back to the system. Time slot X transmitted to the line is not affected by this loopback mode. Looping received system time slot 0 has no effect on time slot 0 transmitted to the line, i.e., the transmit framer will always overwrite the FAS and NOT FAS data in time slot 0 transmitted to the line. This mode can be selected by setting register FRM_PR24 to 110A 4A3A2A1A0 and register FRM_PR10 bit 3 to 1, where A4A3A2A1A0 is the binary address of the selected time slot.

primary loopback and test transmission modes. Table 45. Summary of the Deactivation of SSTSSLB and SSTSLLB Modes as a Function of Activating the primary loopback and test transmission modes.

these sources may be active at the same time. Signaling must be inhibited while sending these test patterns. register FRM_PR20 bit 0 to 1. — Valid transmit facility data link (TFDL) bit information. Figure 42. 20-Stage Shift Register Used to Generate the Quasi-Random Signal described by ITU Rec. 0.151 and illustrated in Figure 43. — Valid transmit facility data link (TFDL) bit data.

92 Lucent Technologies Inc. Lucent T echnologies Inc. Figure 43. 15-Stage Shift Register Used to Generate the Pseudorandom Signal — Valid transmit facility data link (TFDL) bit data. error can be inserted into the transmitted test pattern by toggling register FRM_PR69 bit 1 from 0 to 1. Table 46. Register FRM_PR69 Test Patterns

cated by register FRM_SR7 bit 7 = 1. of 192 bits of pattern plus 1 bit of framing information. successful detection of these two test patterns. if more than 32 errors occur within a single frame. resumes scanning for pattern candidates.

1. Bit errors in the received test pattern are indicated

Table 47. Register FRM_PR70 Test Patterns

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II) October 2000 94 Lucent Technologies Inc. Lucent T echnologies Inc. Alarms and Performance Monitoring (continued) The pattern detector continuously monitors the received line for the particular pattern selected in register FRM_PR70 bit 7—bit 4 (DPTRN). T o establish detector lock to the pattern, 256 sequential bits must be detected. Once the detector has locked onto the selected pattern, it will remain locked to the established alignment and count all unexpected bits as single bit errors until register FRM_PR70 bit 2 (DBLKSEL) is set to 0. T o select a pattern or change the pattern to be detected, the following programming sequence must be followed. ■ DBLKSEL (register FRM_PR70 bit 2) is set to 0. ■ The new pattern to be detected is selected by setting register FRM_PR70 bit 7—bit 4 to the desired value. ■ DBLKSEL (register FRM_PR70 bit 2) is set to 1.

Table 48. Automatic Enable Commands

96 Lucent Technologies Inc. Lucent T echnologies Inc. Table 49. On-Demand Commands DDS Bit 6 in time slot 24 = 0. receive signaling registers.

■ The FDL pins (RFDL, RFDLCK, TFDL, and TFDLCK). Figure 28 shows the timing of these signals. Figure 44. T7630 Facility Data Link Access Timing of the Transmit and Receive Framer Sections ted by the transmit FDL section and recognized and stored by the receive FDL section. detected, register FDL_SR0 bit 7 (FRANSI) is set. FIFO (register FDL_SR4) along with a status of frame (SF) byte. FDL receive FIFO (register FDL_SR4) along with a status of frame (SF) byte.

98 Lucent Technologies Inc. Lucent T echnologies Inc. processing. Incoming data link bits are stored in the FDL receive FIFO (register FDL_SR4). match character and all subsequent bytes are placed into the FDL receive FIFO. The FDL interface to the receive framer is illustrated in Figure 45. Figure 45. Block Diagram for the Receive Facility Data Link Interface detection of a valid BOM and then cleared when read. ten into the received ANSI FDL status register FDL_SR3 when the entire code is received. 10 using register FDL_PR0 bit 4—bit 7.

The received ANSI FDL status byte, register FDL_SR3, has the following format. Table 50. Receive ANSI Code receive FDL FIFO along with the status of frame byte. Table 51. Performance Report Message Structure*

• The rightmost bit (bit 1) is transmitted first for all fields except for the 2 bytes of the FCS that are transmitted leftmost bit (bit 8) first.

The definition of each PRM field is shown in Table 52, and octet content is shown in Table 53.

2 SAPI C/R EA

3 TEI EA

4 Control

5 G 3L VG 4U 1U 2G 5S LG 6

6 F ES EL BG 1 R G 2 N mN l

7 G 3L VG 4U 1U 2G 5S LG 6

8 F ES EL BG 1 R G 2 N mN l

9 G 3L VG 4U 1U 2G 5S LG 6

10 FE SE LB G1 R G2 Nm Nl

11 G3 LV G4 U1 U2 G5 SL G6

12 FE SE LB G1 R G2 Nm Nl

15 Flag

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II) October 2000 100 Lucent Technologies Inc. Lucent T echnologies Inc. Facility Data Link (FDL) (continued) Table 52. FDL Performance Report Message Field Definition Table 53. Octet Contents and Definition

Contents

1 01111110 Opening LAPD Flag 2 00111000 00111010 From CI: SAPI = 14, C/R = 0, EA = 0 From Carrier: SAPI = 14, C/R = 1, EA = 0 3 00000001 TEI = 0, EA = 1 4 00000011 Unacknowledged Frame 5, 6 Variable Data for Latest Second (T) 7, 8 Variable Data for Previous Second (T – 1) 9, 10 Variable Data for Earlier Second (T – 2) 11, 12 Variable Data for Earlier Second (T – 3) 13, 14 Variable CRC-16 Frame Check Sequence 15 01111110 Closing LAPD Flag

frames, reconstructs data bytes, provides bit destuffing as necessary, and loads parallel data in the receive FIFO. bytes are stored in the receive FIFO. The SF byte has the following format. Table 54. Receive Status of Frame Byte

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II) October 2000 102 Lucent Technologies Inc. Lucent T echnologies Inc. Facility Data Link (FDL) (continued) The receive queue status bits, register FDL_SR2 bit 0—bit 6 (FRQS), are updated as bytes are loaded into the receive FIFO. The SF status byte is included in the byte count. When the first SF status byte is placed in the FIFO, register FDL_SR0 bit 4 (FREOF) is set to 1, and the status freezes until the FIFO is read. As bytes are read from the FIFO, the queue status decrements until it reads 1. The byte read when register FDL_SR2 bit 0—bit 6 = 0000001 and the FREOF bit is 1 is the SF status byte describing the error status of the frame just read. Once the first SF status byte is read from the FIFO, the FIFO status is updated to report the number of bytes to the next SF status byte, if any, or the number of additional bytes present. When FREOF is 0, no SF status byte is currently present in the FIFO, and the FRQS bits report the number of bytes present. As bytes are read from the FIFO, the queue status decrements with each read until it reads 0 when the FIFO is totally empty. The FREOF bit is also 0 when the FIFO is completely empty. Thus, the FRQS and FREOF bits provide a mechanism to recognize the end of 1 frame and the beginning of another. Reading the FDL receiver status register does not affect the FIFO buffers. In the event of a receiver overrun, an SF status byte is written to the receive FIFO. Multiple SF status bytes can be present in the FIFO. The FRQS reports only the number of bytes to the first SF status byte. If FRQS is 0, do not read the receive FIFO. A read will result in corruption of receive FIFO. T o allow users to tailor receiver FIFO service intervals to their systems, the receiver interrupt level bits in register FDL_PR6 bit 0—bit 5 (FRIL) are provided. These bits are coded in binary and determine when the receiver full interrupt, register FDL_SR0 bit 3 (FRF), is asserted. The interrupt pin transition can be masked by setting register FDL_PR2 bit 3 (FRFIE) to 0. The value programmed in the FRIL bits equals the total number of bytes necessary to be present in the FIFO to trigger an FRF interrupt. The FRF interrupt alone is not sufficient to determine the number of bytes to read, since some of the bytes may be SF status bytes. The FRQS bits and FREOF bit allow the user to determine the number of bytes to read. The FREOF interrupt can be the only interrupt for the final frame of a group of frames, since the number of bytes received to the end of the frame cannot be sufficient to trigger an FRF interrupt. Programming Note: Since the receiver writing to the receive FIFO and the host reading from the receive FIFO are asynchronous events, it is possible for a host read to put the number of bytes in the receive FIFO just below the programmed FRIL level and a receiver write to put it back above the FRIL level. This causes a new FRF interrupt and has the potential to cause software problems. It is recommended that during service of the FRF interrupt, the FRF interrupt be masked FRFIE = 0 and the interrupt register be read at the end of the service routine, discarding any FRF interrupt seen before unmasking the FRF interrupt. Receiver Overrun A receiver overrun occurs if the 64-byte limit of the receiver FIFO is exceeded, i.e., data has been received faster than it has been read out of the receive FIFO. Upon overrun, an SF status byte with the overrun bit (bit 5) set to 1 replaces the last byte in the FIFO. The SF status byte can have other error conditions present. For example, it is unlikely the CRC is correct. Thus, care should be taken to prioritize the possible frame errors in the software service routine. The last byte in the FIFO is overwritten with the SF status byte regardless of the type of byte (data or SF status) being overwritten. The overrun condition is reported in register FDL_SR0 bit 5 and causes the interrupt pin to be asserted if it is not masked (register FDL_PR2 bit 5 (FROVIE)). Data is ignored until the condition is cleared and a new frame begins. The overrun condition is cleared by reading register FDL_SR0 bit 5 and reading at least 1 byte from the receive FIFO. Because multiple frames can be present in the FIFO, good frames as well as the overrun frame can be present. The host can determine the overrun frame by looking at the SF status byte.

The FDL interface of the transmit framer is shown in Figure 46, indicating the priority of the FDL sources. mission. Idle code is generated by the FDL unit when no other transmission is enabled. The FDL transmitter is enabled by setting register FDL_PR1 bit 3 to 1. Figure 46. Block Diagram for the Transmit Facility Data Link Interface the ANSI T1.403 ESF bit-oriented messages automatically through the FDL bit in the frame. register FDL_PR10 bit 7 (FTANSI) is set to 1.

104 Lucent Technologies Inc. Lucent T echnologies Inc. transmits the ANSI performance report message once every second. and closing flags) to the PRM messages and transmits it to the framer for transmission to the line. T ables 51—53 show the complete format of the PRM HDLC packet. Table 55. HDLC Frame Format 16 bits preceding the closing flag are the frame check sequence, cyclic redundancy check (CRC), bits. is assumed to have been inserted and is deleted (bit destuffing).

Lucent Technologies Inc. 105 Preliminary Data Sheet October 2000 T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) Lucent T echnologies Inc. Facility Data Link (FDL) (continued) Flags* All flags have the bit pattern 01111110 and are used for frame synchronization. The FDL HDLC block automati- cally sends two flags between frames. If the chip-con- figuration register FDL_PR0 bit 1 (FLAGS) is cleared to 0, the ones idle byte (11111111) is sent between frames if no data is present in the FIFO. If FLAGS is set to 1, the FDL HDLC block sends continuous flags when the transmit FIFO is empty. The FDL HDLC does not transmit consecutive frames with a shared flag; there- fore, two successive flags will not share the intermedi- ate 0. An opening flag is generated at the beginning of a frame (indicated by the presence of data in the transmit FIFO and the transmitter enable register FDL_PR1 bit 3 = 1). Data is transmitted per the HDLC protocol until a byte is read from the FIFO while register FDL_PR3 bit 7 (FTFC) set to 1. The FDL HDLC block follows this last user data byte with the CRC sequence and a clos- ing flag. The receiver recognizes the 01111110 pattern as a flag. T wo successive flags may or may not share the intermediate 0 bit and are identified as two flags (i.e., both 011111101111110 and 0111111001111110 are recognized as flags by the FDL HDLC block). When the second flag is identified, it is treated as the closing flag. As mentioned above, a flag sequence in the user data or CRC bits is prevented by zero-bit insertion and dele- tion. The HDLC receiver recognizes a single flag between frames as both a closing and opening flag. Aborts An abort is indicated by the bit pattern of the sequence 01111111. A frame can be aborted by writing a 1 to register FDL_PR3 bit 6 (FT ABT). This causes the last byte written to the transmit FIFO to be replaced with the abort sequence upon transmission. Once a byte is tagged by a write to FT ABT , it cannot be cleared by subsequent writes to register FDL_PR3. FTABT has higher priority than FDL transmit frame complete (FTFC), but FTABT and FTFC should never be set to 1 simultaneously since this causes the transmitter to enter an invalid state requiring a transmitter reset to clear. A frame should not be aborted in the very first byte following the opening flag. An easy way to avoid this situation is to first write a dummy byte into the queue and then write the abort command to the queue. When receiving a frame, the receiver recognizes the abort sequence whenever it receives a 0 followed by seven consecutive ones. The receive FDL unit will abort a frame whenever the receive framer detects a loss of frame alignment. This results in the abort bit, and possibly the bad byte count bit and/or bad CRC bits, being set in the status of frame status byte (see Table 54) which is appended to the receive data queue. All subsequent bytes are ignored until a valid opening flag is received. Idles In accordance with the HDLC protocol, the HDLC block recognizes 15 or more contiguous received ones as idle. When the HDLC block receives 15 contiguous ones, the receiver idle bit register FDL_SR0 bit 6 (RIDL) is set. For transmission, the ones idle byte is defined as the binary pattern 11111111 (FF (hex)). If the FLAGS con- trol bit in register FDL_PR0 bit 1 is 0, the ones idle byte is sent as the time-fill byte between frames. A time-fill byte is sent when the transmit FIFO is empty and the transmitter has completed transmission of all previous frames. Frames are sent back-to-back otherwise. CRC-16 For given user data bits, 16 additional bits that consti- tute an error-detecting code (CRC-16) are added by the transmitter. As called for in the HDLC protocol, the frame check sequence bits are transmitted most signifi- cant bit first and are bit stuffed. The cyclic redundancy check (or frame check sequence) is calculated as a function of the transmitted bits by using the ITU-T stan- dard polynomial: x 16 + x 12 + x 5 + 1 The transmitter can be instructed to transmit a cor- rupted CRC by setting register FDL_PR2 bit 7 (FTB- CRC) to 1. As long as the FTBCRC bit is set, the CRC is corrupted for each frame transmitted by logically flip- ping the least significant bit of the transmitted CRC. The receiver performs the same calculation on the received bits after destuffing and compares the results to the received CRC-16 bits. An error indication occurs if, and only if, there is a mismatch. * Regardless of the time-fill byte used, there always is an opening and closing flag with each frame. Back-to-back frames are sepa- rated by two flags.

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II) October 2000 106 Lucent Technologies Inc. Lucent T echnologies Inc. Facility Data Link (FDL) (continued) Transmit FDL FIFO T ransmit FDL data is loaded into the 64-byte transmit FIFO via the transmit FDL data register, FDL_PR4. The transmit FDL status register indicates how many addi- tional bytes can be added to the transmit FIFO. The transmit FDL interrupt trigger level register FDL_PR3 bit 0—bit 5 (FTIL) can be programmed to tailor service time intervals to the system environment. The transmit- ter empty interrupt bit is set in the FDL interrupt status register FDL_SR0 bit 1 (FTEM) when the transmit FIFO has sufficient empty space to add the number of bytes specified in register FDL_PR3 bit 0—bit 5. There is no interrupt indicated for a transmitter overrun that is writing more data than empty spaces exist. Overrun- ning the transmitter causes the last valid data byte writ- ten to be repeatedly overwritten, resulting in missing data in the frame. Data associated with multiple frames can be written to the transmit FIFO by the controlling microprocessor. However, all frames must be explicitly tagged with a transmit frame complete, register FDL_PR3 bit 7 (FTFC), or a transmit abort, register FDL_PR3 bit 6 (FTABT). The FTFC is tagged onto the last byte of a frame written into the transmitter FIFO and instructs the transmitter to end the frame and attach the CRC and closing flag following the tagged byte. Once written, the FTFC cannot be changed by another write to register FDL_PR3. If FTFC is not written before the last data byte is read out for transmission, an underrun occurs (FDL_SR0 bit 2). When the transmitter has completed a frame, with a closing flag or an abort sequence, reg- ister FDL_SR0 bit 0 (FTDONE) is set to 1. An interrupt is generated if FDL_PR2 bit 0 (FTDIE) is set to 1. Sending 1-Byte Frames Sending 1-byte frames with an empty transmit FIFO is not recommended. If the FIFO is empty, writing two data bytes to the FIFO before setting FTFC provides a minimum of eight TFDLCK periods to set FTFC. When 1 byte is written to the FIFO, FTFC must be written within 1 TFDLCK period to guarantee that it is effective. Thus, 1-byte frames are subject to underrun aborts. One-byte frames cannot be aborted with FT ABT. Plac- ing the transmitter in ones-idle mode, register FDL_PR0 bit 1 (FLAGS) = 0, lessens the frequency of underruns. If the transmit FIFO is not empty, then 1-byte frames present no problems. Transmitter Underrun After writing a byte to the transmit queue, the user has eight TFDLCK cycles in which to write the next byte before a transmitter underrun occurs. An underrun occurs when the transmitter has finished transmitting all the bytes in the queue, but the frame has not yet been closed by setting FTFC. When a transmitter underrun occurs, the abort sequence is sent at the end of the last valid byte transmitted. A FTDONE interrupt is generated, and the transmitter reports an underrun abort until the interrupt status register is read. Using the Transmitter Status and Fill Level The transmitter-interrupt level bits, register FDL_PR3 bit 0—bit 5, allow the user to instruct the FDL HDLC block to interrupt the host processor whenever the transmitter has a predetermined number of empty loca- tions. The number of locations selected determines the time between transmitter empty, register FRM_SR0 bit 1 (FTEM), interrupts. The transmitter status bits, regis- ter FDL_SR1, report the number of empty locations in the FDL transmitter FIFO. The transmitter empty dynamic bit, register FDL_SR1 bit 7 (FTED), like the FTEM interrupt bit, is set to 1 when the number of empty locations is less than or equal to the pro- grammed empty level. FTED returns to 0 when the transmitter is filled to above the programmed empty level. Polled interrupt systems can use FTED to deter- mine when they can write to the FDL transmit FIFO.

Lucent Technologies Inc. 107 Preliminary Data Sheet October 2000 T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) Lucent T echnologies Inc. Facility Data Link (FDL) (continued) Transparent Mode The FDL HDLC block can be programmed to operate in the transparent mode by setting register FDL_PR9 bit 6 (FTRANS) to 1. In the transparent mode of operation, no HDLC processing is performed on user data. The transparent mode can be exited at any time by setting FDL_PR9 bit 6 (FTRANS) to 0. It is recommended that the transmitter be disabled when changing in and out of transparent mode. The transmitter should be reset by setting FDL_PR1 bit 5 (FTR) to 1 whenever the mode is changed. In the transmit direction, the FDL HDLC takes data from the transmit FIFO and transmits that data exactly bit-for-bit on the TFDL interface. Transmit data is octet- aligned to the first TFDLCK after the transmitter has been enabled. The bits are transmitted least significant bit first. When there is no data in the transmit FIFO, the FDL HDLC either transmits all ones, or transmits the programmed HDLC transmitter idle character (register FDL_PR5) if register FDL_PR9 bit 6 (FMA TCH) is set to 1. To cause the transmit idle character to be sent first, the character must be programmed before the transmitter is enabled. The transmitter empty interrupt, register FDL_SR0 bit 1 (FTEM), acts as in the HDLC mode. The transmitter- done interrupt, register FDL_SR0 bit 0 (FTDONE), is used to report an empty FDL transmit FIFO. The FTDONE interrupt thus provides a way to determine transmission end. Register FDL_SR0 bit 2 (FTUNDABT) interrupt is not active in the transparent mode. In the receive direction, the FDL HDLC block loads received data from the RFDL interface directly into the receive FIFO bit-for-bit. The data is assumed to be least significant bit first. If FMA TCH register FDL_PR9 bit 6 is 0, the receiver begins loading data into the receive FIFO beginning with the first RFDLCK detected after the receiver has been enabled. If the FMA TCH bit is set to 1, the receiver does not begin loading data into the FIFO until the receiver match character has been detected. The search for the receiver match character is in a sliding window fashion if register FDL_PR9 bit 4 (FALOCT) bit is 0 (align to octet), or only on octet boundaries if FALOCT is set to 1. The octet boundary is aligned relative to the first RFDLCK after the receiver has been enabled. The matched character and all sub- sequent bytes are placed in the receive FIFO. An FDL receiver reset, register FDL_PR1 bit 4 (FRR) = 1, causes the receiver to realign to the match character if FMA TCH is set to 1. The receiver full (FRF) and receiver overrun (FROVERUN) interrupts in register FDL_SR0 act as in the HDLC mode. The received end of frame (FREOF) and receiver idle (FRIDL) interrupts are not used in the transparent mode. The match status (FMSTA T) bit is set to 1 when the receiver match character is first rec- ognized. If the FMA TCH bit is 0, the FMST A T (FDL_PR9 bit 3) bit is set to 1 automatically when the first bit is received, and the octet offset status bits (FDL_PR9 bit 0—bit 2) read 000. If the FMA TCH bit is programmed to 1, the FMSTA T bit is set to 1 upon rec- ognition of the first receiver match character, and the octet offset status bits indicate the offset relative to the octet boundary at which the receiver match character was recognized. The octet offset status bits have no meaning until the FMST A T bit is set to 1. An octet offset of 111 indicates byte alignment. An interrupt for recognition of the match character can be generated by setting the FRIL level to 1. Since the matched character is the first byte written to the FIFO, the FRF interrupt occurs with the writing of the match character to the receive FIFO. Programming Note: The match bit (FMA TCH) affects both the transmitter and the receiver. Care should be taken to correctly program both the transmit idle char- acter and the receive match character before setting FMA TCH. If the transmit idle character is programmed to FF (hex), the FMA TCH bit appears to affect only the receiver.

108 Lucent Technologies Inc. Lucent T echnologies Inc. The operation of the receiver in transparent mode is summarized in T able 56. Table 56. Receiver Operation in Transparent Mode The serial link interface can operate in two diagnostic loopback modes: (1) local loopback and (2) remote loopback. cannot be enabled simultaneously. ■ TFDLCK clocks both the transmitter and the receiver. ■ The transmitter and receiver must both be enabled. ■ The transmitter output is internally connected to the receiver input. ■ The RFDL input is ignored. ■ The communication between the transmit and receive FIFO buffers and the microprocessor continues normally. FDL_PR1 bit 2, is set. Data loaded to receive FIFO immediately. recognized. No data to receive FIFO until match is detected.

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II) October 2000 110 Lucent Technologies Inc. Lucent T echnologies Inc. Phase-Lock Loop Circuit The T7630 allows for independent transmit path and receive path clocking. The device provides outputs to control variable clock oscillators on both the transmit and receive paths. As such, the system may have both the transmit and receive paths phase-locked to two autonomous clock sources. The block diagram of the T7630 phase detector cir- cuitry is shown in Figure 49. The T7630 uses elastic store buffers (two frames) to accommodate the transfer of data from the system interface clock rate of

2.048 Mbits/s to the line interface clock rate of either

1.544 Mbits/s or 2.048 Mbits/s. The transmit line side of the T7630 does not have any mechanism to monitor data overruns or underruns (slips) in its elastic store buffer. This interface relies on the requirement that the PLLCK clock signal (variable) is phase-locked to the RCHICK clock signal (reference). When this require- ment is not met, uncontrolled slips may occur in the transmit elastic store buffer that would result in corrupt- ing data and no indication will be given. T ypically, a variable clock oscillator (VCXO) is used to drive the PLLCK signal. The T7630 provides a phase error sig- nal (PLLCK-EPLL) that can be used to control the VCXO. The PLLCK-EPLL signal is generated by moni- toring the divided-down PLLCK (DIV-PLLCK) and RCHICK (DIV-RCHICK) signals. The DIV-RCHICK sig- nal is used as the reference to determine the phase dif- ference between DIV-RCHICK and DIV-PLLCK. While DIV-RCHICK and DIVPLLCK are phase-locked, the PLLCK-EPLL signal is in a high-impedance state. A phase difference between DIV-RCHICK and DIV- PLLCK drives PLLCK-EPLL to either 5 V or 0 V . An appropriate loop filter, for example, an RC circuit with R = 1 kΩ and C = 0.1 µF) is used to filter these PLLCK- EPLL pulses to control the VCXO. The system can force TCHICK to be phase-locked to RLCK by using RLCK as a reference signal to control a VCXO that is sourcing the TCHICK signal. The T7630 uses the receive line signal (RLCK) as the reference and the TCHICK signal as the variable signal. The T7630 provides a phase error signal (TCHICK-EPLL) that can be used to control the VCXO generating TCH- ICK. The TCHICK-EPLL signal is generated by moni- toring the divided-down TCHICK signal (DIV-TCHICK) and RLCK (DIV-RLCK) signals. The DIV-RLCK signal is used as the reference to determine the phase differ- ence between DIV-TCHICK and DIV-RLCK. While DIV- RLCK and DIV-TCHICK are phase-locked, the TCH- ICK-EPLL signal is in a high-impedance state. A phase difference between DIV-RLCK and DIV-TCHICK drives TCHICK-EPLL to either 5 V or 0 V . An appropriate loop filter, for example, an RC circuit with R = 1 kΩ and C = 0.1 µF , is used to filter these TCHICK-EPLL pulses to control the VCXO. In this mode, the T7630 can be programmed to act as a master timing source and is capable of generating the system frame synchroniza- tion signal through the TCHIFS pin by setting FRM_PR45 bit 4 to 1.

Figure 49. T7630 Phase Detector Circuitry

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II) October 2000 112 Lucent Technologies Inc. Lucent T echnologies Inc. Framer-System (CHI) Interface DS1 Modes The DS1 framing formats require rate adaptation from the 1.544 Mbits/s line interface bit stream to the system interface which functions at multiples of a 2.048 Mbits/s bit stream. The rate adaptation results in the need for eight stuffed time slots on the system interface since there are only 24 DS1 (1.544 Mbits/s) payload time slots while there are 32 system (2.048 Mbits/s) time slots. Placement of the stuffed time slots is defined by register FRM_PR43 bit 0—bit 2. CEPT Modes The framer maps the line time slots into the corre- sponding system time slot one-to-one. Framing time slot 0, the FAS and NFAS bytes, are placed in system time slot 0. Receive Elastic Store The receive interface between the framer and the sys- tem (CHI) includes a two-frame elastic store buffer to enable rate adaptation. The receive line elastic store buffer contains circuitry that monitors the read and write pointers for potential data overrun and underrun (slips) conditions. Whenever this slip circuitry deter- mines that a slip may occur in the receive elastic store buffer, it will adjust the read pointer such that a con- trolled slip is performed. The controlled slip is imple- mented by dropping or repeating a complete frame at the frame boundaries. The occurrence of controlled slips in the receive elastic store are indicated in the sta- tus register FRM_SR3 bit 6 and bit 7. Transmit Elastic Store The transmit interface between the framer and the sys- tem (CHI) includes a two-frame elastic store buffer to enable rate adaptation. The line transmit clock applied to PLLCK (pins 7/31) must be phase-locked to RCHICK. No indication of a slip in the transmit elastic store is given. Concentration Highway Interface Each framer has a dual, high-speed, serial interface to the system known as the CHI. This flexible bus archi- tecture allows the user to directly interface to other Lucent components which use this interface, as well as to Mitel* and AMD † TDM highway interfaces, with no glue logic. Configured via the highway control registers FRM_PR45 through FRM_PR66, this interface can be set up in a number of different configurations. The following is a list of the CHI features: ■ Lucent T echnologies standard interface for communi- cation devices. ■ T wo pairs of transmit and receive paths to carry data in 8-bit time slots. ■ Programmable definition of highways through offset and clock-edge options which are independent for transmit and receive directions. ■ Programmable idle code substitution of received time slots. ■ Programmable 3-state control of each transmit time slot. ■ Independent transmit and receive framing signals to synchronize each direction of data flow. ■ An 8 kHz frame synchronization signal internally generated from the received line clock. ■ Compatible with Mitel and AMD PCM highways. Supported is the optional configuration of the CHI which presents the signaling information along with the data in any framing modes when the device is pro- grammed for the associated signaling mode (ASM). This mode is discussed in the signaling section. Data can be transmitted or received on either one of two interface ports, called CHIDA T A and CHIDA TAB. The user-supplied clocks (RCHICLK and TCHICLK) control the timing on the transmit or receive paths. Indi- vidual time slots are referenced to the frame synchroni- zation (RCHIFS and TCHIFS) pulses. Each frame consists of 32 time slots at a programmable data rate of 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s requiring a clock (TCHICK and RCHICK) of the same rate. The clock and data rates of the transmit and receive high- ways are programmed independently. * Mitel is a registered trademark of Mitel Corporation. † AMD is a registered trademark of Advanced Micro Devices, Inc.

interface to a high-impedance state for the interval of the disabled time slots. The CHI parameters that define the receive and transmit paths are given in T able 57. Table 57. Summary of the T7630’s Concentration Highway Interface Parameters forced to a high-impedance state for all CHI transmitted time slots. CHI path is not affected by this mode. allows two CHIs to interleave frames on a common bus. CHIMM = 1 mode is identical to the timing for TCHIFS in CHIMM = 0 mode. falling (or rising) edge of RCHICK. data rate. The default state (00) enables the 2.048 Mbits/s.

114 Lucent Technologies Inc. Lucent T echnologies Inc. the falling (or rising) edge of TCHICK. the falling (or rising) edge of RCHICK. time slot. A 0 forces the CHI transmit highway time slot to be 3-stated. ister FRM_PR22 to the line interface. active time slot. A 0 enables TCHIDA T A; a 1 enables the TCHIDA T AB. time slot. A 0 enables RCHIDA T A; a 1 enables the RCHIDA T AB. set is the number of TCHICK cycles by which the first bit is delayed. is the number of RCHICK cycles by which the first bit is delayed. 16 bits where 8 bits are data and the remaining 8 bits are signaling information. 3 bits define the location of the eight stuffed CHI (unused) time slots. Table 57. Summary of the T7630’s Concentration Highway Interface Parameters (continued)

0). The frames are 125 µs long and consist of 32 contiguous time slots. In DS1 frame modes, the CHI frame consists of 24 payload time slots and eight stuffed (unused) time slots. In CEPT frame modes, the CHI frame consists of 32 payload time slots.

• The position of the stuffed time is controlled by register FRM_PR43 bit 0—bit 2.

Figure 50. Nominal Concentration Highway Interface Timing (for FRM_PR43 bit 0—bit 2 = 100 (Binary))

8.192 Mbits/s CHI:

4.096 Mbits/s CHI:

2.048 Mbits/s CHI:

24 VALID TIME SLOTS HIGH IMPEDANCE FRAME 2TCHIDA T A

32 VALID TIME SLOTS

24 VALID TIME SLOTS

8 STUFFED

116 Lucent Technologies Inc. Lucent T echnologies Inc. mode is valid only for 4.096 Mbits/s and 8.192 Mbits/s CHI rates. Figure 51. CHIDTS Mode Concentration Highway Interface Timing

8.192 Mbits/s CHI

4.096 Mbits/s CHI

(RCHDTS) = 0). The frames are 125 µs long and consist of 32 contiguous 16-bit time slots. In CEPT modes, each frame consists of 32 time slots. Each time slot consists of two octets. Figure 52. Associated Signaling Mode Concentration Highway Interface Timing and CHIDTS enabled (registers FRM_PR65 bit 1 (TCHIDTS) = 1 and FRM_PR66 bit 1 (RCHIDTS) = 1).

• High-impedance state for TCHIDA TA and not received (don’t care) for RCHIDA TA.

Figure 53. CHI Timing with ASM and CHIDTS Enabled

1 TIME SLOT

8.192 Mbits/s CHI WITH ASM (ASSOCIA TED SIGNALING MODE) ENABLED

120 Lucent Technologies Inc. Lucent T echnologies Inc. ■ T esting the connections between ICs on a particular board. ■ Observation of signals to the IC pins during normal operating functions. ■ Controlling the built-in self-test (BIST) of an IC. T7630 does not support BS-BIST . Figure 57. Block Diagram of the T7630's Boundary-Scan Test Logic *IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.

edge rises. Figure 58 shows the TAP controller state diagram. Figure 58. BS TAP Controller State Diagram

122 Lucent Technologies Inc. Lucent T echnologies Inc. Table 59. TAP Controller States in the Data Register Branch Table 60. TAP Controller States in the Instruction Register Branch SELECT DR This state is used for branching to the test data register control. TCK in the state. The TDO output driver is active. EXIT (1/2) DR This temporary state causes a branch to a subsequent state. P AUSE DR The input and output of test data can be interrupted in this state. the falling edge of TCK in this state. SELECT IR This state is used for branching to the instruction register control. parallel to the rising edge of TCK in this state. of TCK in the state. The TDO output driver is active. EXIT (1/2) IR This temporary state causes a branch to a subsequent state. P AUSE IR The input and output of instructions can be interrupted in this state. to the falling edge of TCK in this state.

The instruction register (IR) is 4 bits in length. T able 61 shows the BS instructions implemented by the T7630. Table 61. T7630’s Boundary-Scan Instructions IDCODE 0001 Identification NORMAL Read Manuf. logic-reset controller state and at powerup. ported by T7630 and their effect on the devices' pins. tion selects the BS register as the test data register. in the UPDA TE-DR state on the falling edge of TCK.

124 Lucent Technologies Inc. Lucent T echnologies Inc. appears first when the data is being read out. boundary-scan register bit-to-pin assignment is to be determined. on the rising edge of TCK in the CAPTURE-DR state. The 32-bit data is organized into four sections as follows. Table 62. IDCODE Register pattern at the T7630 outputs does not become corrupted.

erwise, the alarm status register bit remains set. Table 63. Microprocessor Configuration Modes

• A L E_AS may be connected to ground in this mode.

† The DT ACK signal is asynchronous to the MPCLK signal.

126 Lucent Technologies Inc. Lucent T echnologies Inc. same set of pins in all modes. Table 64. Mode [1—4] Microprocessor Pin Definitions becomes an interval 2.048 MHz clock derived from the CHI clock. † The DT ACK output is asynchronous to MPCLK. ‡ MPCLK is needed if RDY output is required to be synchronous to MPCLK. § In the default (reset) mode, INTERRUPT is active-high. It can be made active-low by setting register GREG4 bit 6 to 1.

75 RD _R/W R/W Input — Read/Write

77 ALE _AS AS Input Active-Low Address Strobe

78 CS CS Input Active-Low Chip Select

99 INTERRUPT INTERRUPT * Output Active-High/

100 RDY_DT ACK DTACK † Output Active-Low Data Acknowledge

101 MPCLK MPCLK Input — Microprocessor Clock

77 ALE _AS AS Input — Address Strobe

99 INTERRUPT INTERRUPT * Output Active-High/Low Interrupt

75 RD _R/W RD Input Active-Low Read

77 ALE _AS ALE Input Active-Low Address Latch Enable

100 RDY_DT ACK RDY ‡ Output Active-High Ready

77 ALE _AS ALE Input — Address Latch Enable

MODE 4) is required to be synchronous to MPCLK. Table 65. Microprocessor Input Clock Specifications registers which are common to all the circuit blocks on T7630. REGBANK1 is reserved and must not be written. REGBANK[2, 5] are attached to the LIU circuit blocks. REGBANK[3, 6] are attached to the framer circuit blocks. found in the appropriate sections of this document. In these descriptions, all addresses are given in hexadecimal.

1. An inadvertant write to an out-of-range address may be corrected by a device reset.

Table 66. T7630 Register Address Map

• Core registers are common to all circuit blocks on T7630.

capacitive load of 50 pF . The AD[7:0] outputs are rated for a 100 pF load.

128 Lucent Technologies Inc. Lucent T echnologies Inc. falling edge of ALE_AS signal is used to latch the address bus. Table 67. Microprocessor Interface I/O Timing Specifications

Table 67. Microprocessor Interface I/O Timing Specifications (continued) Note: The read and write timing diagrams for all four microprocessor interface modes are shown in Figure 59—Figure 66.

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II) October 2000 134 Lucent Technologies Inc. Lucent T echnologies Inc. Reset Both hardware and software resets are provided. Hardware Reset (Pin 43/139) Hardware reset is enabled by asserting RESET to 0. Each channel has independent resets, RESET1 (pin 139) for channel 1 and RESET2 (pin 43) for channel 2. The device is in an inactive condition when RESET is 0, and becomes active when RESET is returned to 1. Eight cycles of the LIU receive line clock, i.e., 5.2 µs for T1 or 3.9 µs for E1, is required to guarantee a complete reset. Upon completion of a reset cycle, the LIU regis- ter default values are controlled by the setting of DS1/CEPT (pin 40/142), as given in T able 7. Transmit Line Interface Short-Haul Equalizer/Rate Control. If DS1/CEPT is 1, the defaults are set for DS1 with line equalization for a 1 ft. to 131 ft. span. If DS1/CEPT is 0, the defaults are set for CEPT with a line equalization for 120 Ω twisted pair or 75 Ω coax option 1. Hardware reset of a single channel returns all LIU, framer, and FDL registers of that channel to their default values, as listed in the individual register descriptions and register maps, T able 197—Table 202. Reset of a single channel does not reset the global reg- isters. Hardware reset of both channels simultaneously, both pin 43 and pin 139 set to 0, results in a complete device reset including a reset of the global registers. Software Reset/Software Restart Independent software reset for each functional block of the device is available. The LIU may be placed in restart through register LIU_REG2 bit 5 (REST ART). The framer may be reset through register FRM_PR26 bit 0 (SWRESET), or placed in restart through FRM_PR26 bit 1 (SWREST ART). The FDL receiver may be reset through register FDL_PR26 bit 1 (FRR), and the FDL transmitter may be reset through FDL_PR1 bit 5 (FTR). The reset functions, framer SWRESET (framer software reset), FDL FRR (FDL receiver reset), and FTR (FDL transmitter reset), reset the block and return all parameter/control registers for the block to their default values. The restart functions, LIU REST ART and framer SWRESTART (framer soft- ware restart), reset the block but do not alter the value of the parameter/control registers.

T able 68 is an overview of the register architecture. The table is a summary of the register function and address. Complete detail of each register is given in the following sections. Table 68. Register Summary

605 C05

606 C06

136 Lucent Technologies Inc. Lucent T echnologies Inc. Table 68. Register Summary (continued)

138 Lucent Technologies Inc. Lucent T echnologies Inc.

registers is 000 (hex) to 007 (hex). These registers control both channels of the terminator. terminal control register, device identification register, and global internal interface control register. The default values are shown in parentheses. Table 69. Global Register Set (0x000—0x008) The following section describes the global registers in Tables 70—75.

140 Lucent Technologies Inc. Lucent T echnologies Inc. A bit set to 1 indicates the block has recently generated an interrupt. This register is cleared on read. Table 70. Primary Block Interrupt Status Register (GREG0) (000) This register enables the individual blocks to assert the interrupt pin. Table 71. Primary Block Interrupt Enable Register (GREG1) (001) 0L I U 1 I N T Line Interface Unit 1 Interrupt. A 1 indicates LIU1 generated an interrupt. 1 FRMR1INT Framer 1 Interrupt. A 1 indicates framer 1 generated an interrupt. 2 FDL1INT Facility Data Link 1 Interrupt. A 1 indicates FDL1 generated an interrupt. 4L I U 2 I N T Line Interface Unit 2 Interrupt. A 1 indicates LIU2 generated an interrupt. 5 FRMR2INT Framer 2 Interrupt. A 1 indicates framer 2 generated an interrupt. 6 FDL2INT Facility Data Link 2 Interrupt. A 1 indicates FDL2 generated an interrupt. 0L I U 1 I E Line Interface 1 Interrupt Enable. A 1 enables LIU1 interrupts. 1 FRMR1IE Framer 1 Interrupt Enable. A 1 enables framer 1 interrupts. 2 FDL1IE Facility Data Link 1 Interrupt Enable. A 1 enables FDL1 interrupts. 4L I U 2 I E Line Interface 2 Interrupt Enable. A 1 enables LIU2 interrupts. 5 FRMR2IE Framer 2 Interrupt Enable. A 1 enables framer 2 interrupts. 6 FDL2IE Facility Data Link 2 Interrupt Enable. A 1 enables FDL2 interrupts.

This register enables the framer inputs RCHIDA TA1 and RCHIDA T AB1 to be driven by various internal sources. sources to drive these inputs. Table 72. Global Loopback Control Register (GREG2) (002) This register enables the framer inputs RCHIDA TA2 and RCHIDA T AB2 to be driven by various internal sources. sources to drive these inputs. Table 73. Global Loopback Control Register (GREG3) (003) 0T I D 1 — R I D 1TCHIDATA1 to RCHIDATA1 Connection. 1 TSD1—RID1 TCHIDATAB1 to RCHIDATA1 Connection. 2T I D 2 — R I D 1TCHIDATA2 to RCHIDATA1 Connection. 3 TSD2—RID1 TCHIDATAB2 to RCHIDATA1 Connection. 4 TSD1—RSD1 TCHIDATAB1 to RCHIDATAB1 Connection. 5 TID1—RSD1 TCHIDATA1 to RCHIDATAB1 Connection. 6 TSD2—RSD1 TCHIDATAB2 to RCHIDATAB1 Connection. 7 TID2—RSD1 TCHIDATA2 to RCHIDATAB1 Connection. 0T I D 2 — R I D 2TCHIDATA2 to RCHIDATA2 Connection. 1 TSD2—RID2 TCHIDATAB2 to RCHIDATA2 Connection. 2T I D 1 — R I D 2TCHIDATA1 to RCHIDATA2 Connection. 3 TSD1—RID2 TCHIDATAB1 to RCHIDATA2 Connection. 4 TSD2—RSD2 TCHIDATAB2 to RCHIDATAB2 Connection. 5 TID2—RSD2 TCHIDATA2 to RCHIDATAB2 Connection. 6 TSD1—RSD2 TCHIDATAB1 to RCHIDATAB2 Connection. 7 TID1—RSD2 TCHIDATA1 to RCHIDATAB2 Connection.

142 Lucent Technologies Inc. Lucent T echnologies Inc. polarity (bit 6), and source of framer resets (bit 7). Table 74. Global Control Register (GREG4) (004) These bits define the device and version number. Table 75. Device ID and Version Registers (GREG5— GREG7) (005—007) pulse (SECOND). A 1 enables framer 2 to source the output second pulse. 6A L I E Active-Low Interrupt Enable. A 1 enables active-low interrupt.

these register banks, the bit map is identical for both LIU1 and LIU2. ters, and configuration registers. LIU_REG1 contains the individual interrupt enable bits for the alarms in LIU_REG0. The default values are shown in parentheses. The following sections describe the LIU registers in more detail. Table 76. Line Interface Units Register Set

• The logic value, in parentheses below each bit definition, is the default state upon completion of hardware reset.

† These bits must be written to 1.

144 Lucent Technologies Inc. Lucent T echnologies Inc. responding alarm conditions no longer exist. set even after a microprocessor read. This is a read-only register. Table 77. LIU Alarm Status Register (LIU_REG0) (400, A00) to generate an interrupt. Otherwise, the alarm is disabled from generating an interrupt. with an alarm event will operate normally even if the interrupt is not enabled. Table 78. LIU Alarm Interrupt Enable Register (LIU_REG1) (401, A01)

• See T7630 Device Advisory for signal timing requirements.

an analog loss of signal condition/event. digital loss of signal condition/event. a transmit driver monitor alarm condition/event. detected a loss of transmit clock condition/event.

face channels 1 and 2. All the control bits (with the exception of LOSSTD) are active-high. Table 79. LIU Control Register (LIU_REG2) (402, A02) Table 80. LIU Control Register (LIU_REG3) (403, A03). Note: These registers must be written to 1 for the LIU-to-framer interface to be functional.

2 LOSSTD The LOSSTD bit selects the conformance protocol for the DLOS receiver alarm

000009 for DS1 and ITU-T G.775 for CEPT.

5 REST ART The REST ART bit is used for device initialization through the microprocessor inter-

the microprocessor registers state will not be altered by a restart action.

0 JAR The JAR bit is used to enable and disable the jitter attenuator function in the receive

control bit can be set, but not both. JAR = 1 places jitter attenuator in the receive path.

1 JA T The JA T bit is used to enable and disable the jitter attenuator function in the transmit

control bit can be set, but not both. JA T = 1 places jitter attenuator in the transmit path.

2 CODE The CODE bit is used to enable and disable the B8ZS/HDB3 zero substitution coding

decoding functions. The default value is CODE = 1.

146 Lucent Technologies Inc. Lucent T echnologies Inc. Table 81. LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes) (from Table 4) Table 82. LIU Register (LIU_REG4) (404, A04)

00 D L O S Normal Data Recovered Clock

01 A L O S AIS (all ones) Free Runs

01 D L O S AIS (all ones) Free Runs

selects 1 ms—2.6 ms. ALTIMER = 1 selects 10 bit to 255 bit periods.

1 RCVAIS The RCVAIS bit selects the shut down function for the receiver during ALOS alarm

(ALOS). RCVAIS operates in conjunction with the LOSSD bit. See LIU-REG3. 2 PFLALM PFLALM prevents the DLOS alarm from occurring during FLLOOP activation. PFLALM = 1 activates the PFLALM function.

3 PRLALM PRLALM prevents the LOTC alarm from occurring during RLOOP activation/deacti-

vation. PRLALM = 1 activates the PRLALM function.

4 PHIZALM PHIZALM prevents the TDM alarm from occurring when the driver are in a high-

impedance state. PHIZALM = 1 activates the PHIZALM function. 5 JABW0 JABW0 = 1 selects the lower bandwidth jitter attenuator option in CEPT mode.

of this register is 02 (hex). Table 83. LIU Configuration Register (LIU_REG5) (405, A05) Table 84. Loopback Control (from Table 11)

• The reset default condition is LOOP A = LOOPB = 0 (no loopback).

† During the transmit AIS condition, the looped data will be the transmitted data from the framer or system interface and not the all ones signal. ‡ T ransmit AIS request is ignored. and 06 (hex) in CEPT when DS1/CEPT (pin 40/142) is set to 0. Table 85. LIU Configuration Register (LIU_REG6) (406, A06) 0 PWRDN PWRDN = 1 activates powerdown. source is present. The default value is XLAIS = 1.

2 LOOPB The LOOP A bit is used in conjunction with LOOPB to select the channel loopback

0 EQ0 The EQ0, EQ1, and EQ2 bits select the type of service (DS1 or CEPT) and the

associated transmitter cable equalization/line build out/termination impedances.

148 Lucent Technologies Inc. Lucent T echnologies Inc. Table 86. Transmit Line Interface Short-Haul Equalizer/Rate Control (from Table 7)

• In DS1 mode, the distance to the DSX for 22-Gauge PIC (ABAM) cable is specified. Use the maximum cable loss figures for other cable types.

In CEPT mode, equalization is specified for coaxial or twisted-pair cable. † Reset default state is EQ2, EQ1, and EQ0 = 000 when pin DS1_CEPT = 1 and EQ2, EQ1, and EQ0 = 110 when pin DS1_CEPT = 0. former as in CEPT 120 Ω applications (see Line Interface Unit: Line Circuitry section). C00 (hex). Within these register banks, the bit map is identical for both FRM1 and FRM2. Table 87. Framer Status and Control Blocks Address Range (Hexadecimal) The complete register map for the framer is given in T able 201 to Table 203. All status registers are clocked with the internal framer receive line clock (RFRMCK). bits are enabled in interrupt enable registers FRM_PR0—FRM_PR7.

On all 16-bit counter registers (FRM_SR8—FRM_SR51), both bytes are cleared only after reading both bytes. followed immediately by a read of the remaining byte of the pair. must be allowed between successive reads of the same COR register to allow it to properly clear. Registers FRM_SR0—FRM_SR63 report the status of each framer. All are clear-on-read, read only registers. isters FRM_PR0—FRM_PR7 are set, and the interrupt for the framer block is enabled in register GREG1. Table 88. Interrupt Status Register (FRM_SR0) (600; C00) 0F A C Facility Alarm Condition. A 1 indicates a facility alarm occurred (go read FRM_SR1). 1R A C Remote Alarm Condition. A 1 indicates a remote alarm occurred (go read FRM_SR2). FRM_SR5, FRM_SR6, and FRM_SR7). has been transmitted and the transmit signaling data buffers are ready for new data. been received and the receive signaling data buffers must be read. ready for more data or the receive framer SLC -96 stack contains new data.

150 Lucent Technologies Inc. Lucent T echnologies Inc. is no longer present at the time of the read, then the bit is cleared on read. Table 89. Facility Alarm Condition Register (FRM_SR1) (601; C01) ment and is currently searching for a new alignment. naling superframe alignment starts once frame alignment is established. mode, register FRM_PR44 bit 0 (TSIG) = 1. SLC -96 is lost. Only valid for SLC -96 mode. This bit is 0 in all other DS1 modes. in bit 0 of this register is the same LFA state as the previous read. (alternating 10 in bit 2 of time slot 0 of each frame) in the receive system data is errored. valid in the CEPT mode. This bit is 0 in all other modes. detected time slot 16 AIS in the CEPT mode. This bit is 0 in the DS1 modes. tern) in the CEPT mode. This bit is 0 in the DS1 modes. pattern from its remote line end.

time of the read, then the bit is cleared on read. Table 90. Remote End Alarm Register (FRM_SR2) (602; C02) nese format remote frame alarm. remote frame alarm in the CEPT mode. containing ≥991 E bit = 0 events in each second. This bit is 0 in the DS1 mode. 3S a 6 = 8 Received Sa6 = 8. A 1 indicates the receive framer detected a Sa6 code equal to 1000. This bit is 0 in the DS1 mode. 4 Sa6 = A Received Sa6 = A. A 1 indicates the receive framer detected a Sa6 code equal to 1010. This bit is 0 in the DS1 mode. 5S a 6 = C Received Sa6 = C. A 1 indicates the receive framer detected a Sa6 code equal to 1100. This bit is 0 in the DS1 mode. 6 Sa6 = E Received Sa6 = E. A 1 indicates the receive framer detected a Sa6 code equal to 1110. This bit is 0 in the DS1 mode. 7S a 6 = F Received Sa6 = F. A 1 indicates the receive framer detected a Sa6 code equal to 1111. This bit is 0 in the DS1 mode.

152 Lucent Technologies Inc. Lucent T echnologies Inc. A bit set to 1 indicates the receive framer has recently received the given errored event. Table 91. Facility Errored Event Register-1 (FRM_SR3) (603; C03) 2 CRCE CRC Errored. A 1 indicates the receive framer detected CRC errors. 13 or 15 of the time slot 0 of CRC-4 multiframe. This bit is 0 in the DS1 modes. formed a control slip due to an elastic buffer overflow condition. performed a control slip due to an elastic buffer underflow condition.

Table 92. Facility Event Register-2 (FRM_SR4) (604; C04) ment which differs from the previous alignment. this alignment is established only after primary frame alignment is determined. ence 62411 as a framed 001 pattern where the frame bit is inserted into the pattern. 62411 as a framed 00001 pattern where the frame bit is inserted into the pattern. alignment in the receive framer has been established. SLC -96 D-bit superframe interval. 4 ms of this interrupt. This bit is not updated during LFA. will be transmitted in the next CRC-4 double multiframe interval.

154 Lucent Technologies Inc. Lucent T echnologies Inc. Table 93. Exchange Termination and Exchange Termination Remote End Interface Status Register resulting in a ten-second delay in the reporting of this condition. the exchange termination remote end (ET -RE). errored second at the ET -RE. errored second at the ET -RE. used resulting in a ten-second delay in the reporting of this condition.

Table 94. Network Termination and Network Termination Remote End Interface Status in a ten-second delay in the reporting of this condition. the exchange termination remote end (ET -RE). errored second at the ET -RE. errored second at the NT -RE. used resulting in a ten-second delay in the reporting of this condition.

156 Lucent Technologies Inc. Lucent T echnologies Inc. Table 95. Facility Event Register (FRM_SR7) (607; C07)

• It is possible for one of these bits to be set to 1, if the received line data is all zeros.

This register contains the 16-bit count of received bipolar violations, line code violations, or excessive zeros. Table 96. Bipolar Violation Counter Registers (FRM_SR8—FRM_SR9) ((608—609); (C08—C09)) Table 97. Framing Bit Error Counter Registers (FRM_SR10—FRM_SR11) ((60A—60B); (C0A—C0B)) onds that were not severely errored while in the unavailable state at the ET . secutive seconds that were not severely errored while in the unavailable state at the ET -RE. utive seconds that were not severely errored while in the unavailable state at the NT . tive seconds that were not severely errored while in the unavailable state at the NT -RE. ified by the PTRN configuration bits defined in register FRM_PR70. errors in the pattern that it is currently locked onto. is currently detecting the 215 – 1 pseudorandom pattern*. is currently detecting the 220 – 1 quasi-random pattern*. FRM_SR8 MSB 7—0 BPV15—BPV8 BPVs Counter. FRM_SR9 LSB 7—0 BPV7—BPV0 BPVs Counter. FRM_SR10 MSB 7—0 FBE15—FBE8 Frame Bit Errored Counter. FRM_SR11 LSB 7—0 FBE7—FBE0 Frame Bit Errored Counter.

Table 98. CRC Error Counter Registers (FRM_SR12—FRM_SR13) ((60C—60D); (C0C—C0D)) Table 99. E-Bit Counter Registers (FRM_SR14—FRM_SR15) ((60E—60F); (C0E—C0F)) CRC-4 multiframe. E bits are not counted during loss of CEPT CRC-4 multiframe alignment. Table 101. E Bit at NT1 from NT2 Counter (FRM_SR18—FRM_SR19) ((612—613); (C12—C13)) FRM_SR12 MSB 7—0 CEC15—CEC8 CRC Errored Counter. FRM_SR13 LSB 7—0 CEC7—CEC0 CRC Errored Counter. FRM_SR14 MSB 7—0 REC15—REC8 E-Bit Counter. FRM_SR15 LSB 7—0 REC7—REC0 E-Bit Counter. FRM_SR16 MSB 7—0 CNT15—CNT8 CRC-4 Errors at NT1 Counter. FRM_SR17 LSB 7—0 CNT7—CNT0 CRC-4 Errors at NT1 Counter. FRM_SR18 MSB 7—0 ENT15—ENT8 E Bit at NT1 Counter. FRM_SR19 LSB 7—0 ENT7—ENT0 E Bit at NT1 Counter.

158 Lucent Technologies Inc. Lucent T echnologies Inc. nals. DS1 error conditions are reported in the ET errored registers FRM _SR20—FRM_SR35. Table 102. ET Errored Seconds Counter (FRM_SR20—FRM_SR21) ((614—615); (C14—C15)) Table 103. ET Bursty Errored Seconds Counter (FRM_SR22—FRM_SR23) ((616—617); (C16—C17)) Table 104. ET Severely Errored Seconds Counter (FRM_SR24—FRM_SR25) ((618—619); (C18—C19)) Table 105. ET Unavailable Seconds Counter (FRM_SR26—FRM_SR27) ((61A—61B); (C1A—C1B)) Table 106. ET -RE Errored Seconds Counter (FRM_SR28—FRM_SR29) ((61C—61D); (C1C—C1D)) Table 107. ET -RE Bursty Errored Seconds Counter (FRM_SR30—FRM_SR31) ((61E—61F); (C1E—C1F)) Table 108. ET -RE Severely Errored Seconds Counter (FRM_SR32—FRM_SR33) ((620—621); (C20—C21)) FRM_SR20 MSB 7—0 ETES15—ETES8 ET Errored Seconds Counter. FRM_SR21 LSB 7—0 ETES7—ETES0 ET Errored Seconds Counter. FRM_SR22 MSB 7—0 ETBES15—ETBES8 ET Bursty Errored Seconds Counter. FRM_SR23 LSB 7—0 ETBES7—ETBES0 ET Bursty Errored Seconds Counter. FRM_SR24 MSB 7—0 ETSES15—ETSES8 ET Severely Errored Seconds Counter. FRM_SR25 LSB 7—0 ETSES7—ETSES0 ET Severely Errored Seconds Counter. FRM_SR26 MSB 7—0 ETUS15—ETUS8 ET Unavailable Seconds Counter Bits. FRM_SR27 LSB 7—0 ETUS7—ETUS0 ET Unavailable Seconds Counter Bits. FRM_SR28 MSB 7—0 ETREES15—ETREES8 ET -RE Errored Seconds Counter. FRM_SR29 LSB 7—0 ETREES7—ETREES0 ET -RE Errored Seconds Counter. FRM_SR30 MSB 7—0 ETREBES15—ETREBES8 ET -RE Bursty Errored Seconds Counter. FRM_SR31 LSB 7—0 ETREBES7—ETREBES0 ET -RE Bursty Errored Seconds Counter. FRM_SR32 MSB 7—0 ETRESES15—ETRESES8 ET -RE Severely Errored Seconds Counter. FRM_SR33 LSB 7—0 ETRESES7—ETRESES0 ET -RE Severely Errored Seconds Counter.

Table 109. ET -RE Unavailable Seconds Counter (FRM_SR34—FRM_SR35) ((622—623); (C22—C23)) Table 110. NT1 Errored Seconds Counter (FRM_SR36—FRM_SR37) ((624—625); (C24—C25)) Table 111. NT1 Bursty Errored Seconds Counter (FRM_SR38—FRM_SR39) ((626—627); (C26—C27)) Table 112. NT1 Severely Errored Seconds Counter (FRM_SR40—FRM_SR41) ((628—629); (C28—C29)) Table 113. NT1 Unavailable Seconds Counter (FRM_SR42—FRM_SR43) ((62A—62B); (C2A—C2B)) Table 114. NT1-RE Errored Seconds Counter (FRM_SR44—FRM_SR45) ((62C—62D); (C2C—C2D)) Table 115. NT1-RE Bursty Errored Seconds Counter (FRM_SR46—FRM_SR47) ((62E—62F); (C2E—C2F)) FRM_SR34 MSB 7—0 ETREUS15—ETRESES8 ET -RE Unavailable Seconds Counter. FRM_SR35 LSB 7—0 ETRESES7—ETRESES0 ET -RE Unavailable Seconds Counter. FRM_SR36 MSB 7—0 NTES15—NTES8 NT1 Errored Seconds Counter. FRM_SR37 LSB 7—0 NTES7—NTES0 NT1 Errored Seconds Counter. FRM_SR38 MSB 7—0 NTBES15—NTBES8 NT1 Bursty Errored Seconds Counter. FRM_SR39 LSB 7—0 NTBES7—NTBES0 NT1 Bursty Errored Seconds Counter. FRM_SR40 MSB 7—0 NTSES15—NTSES8 NT1 Severely Errored Seconds Counter. FRM_SR41 LSB 7—0 NTSES7—NTSES0 NT1 Severely Errored Seconds Counter. FRM_SR42 MSB 7—0 NTUS15—NTUS8 NT1 Unavailable Seconds Counter Bits. FRM_SR43 LSB 7—0 NTUS7—NTUS0 NT1 Unavailable Seconds Counter Bits. FRM_SR44 MSB 7—0 NTREES15—NTREES8 NT1-RE Errored Seconds Counter. FRM_SR45 LSB 7—0 NTREES7—NTREES0 NT1-RE Errored Seconds Counter. FRM_SR46 MSB 7—0 NTREBES15—NTREBES8 NT1-RE Bursty Errored Seconds Counter. FRM_SR47 LSB 7—0 NTREBES7—NTREBES0 NT1-RE Bursty Errored Seconds Counter.

160 Lucent Technologies Inc. Lucent T echnologies Inc. Table 116. NT1-RE Severely Errored Seconds Counter (FRM_SR48—FRM_SR49) ((630—631); (C30—C31)) Table 117. NT1-RE Unavailable Seconds Counter (FRM_SR50—FRM_SR51) ((632—633); (C32—C33)) slot 0 and the Si bit of FAS time slot 0 while the receive framer was in basic frame alignment. Table 118. Receive NOT -FAS TS0 Register (FRM_SR52) (634; C34) Table 119. Receive Sa Register (FRM_SR53) (635; C35) FRM_SR48 MSB 7—0 NTRESES15—NTRESES8 NT1-RE Severely Errored Seconds Counter. FRM_SR49 LSB 7—0 NTRESES7—NTRESES0 NT1-RE Severely Errored Seconds Counter. FRM_SR50 MSB 7—0 NTREUS15—NTREUS8 NT1-RE Unavailable Seconds Counter Bits. FRM_SR51 LSB 7—0 NTREUS7—NTREUS0 NT1-RE Unavailable Seconds Counter Bits.

00000 X 2 X 1 X 0

Note: The RSP[1:4] are the received spoiler bits. state. In CRC-4 mode, these registers are only updated during the CRC-4 multiframe alignment state. Table 121. CEPT Sa Receive Stack (FRM_SR54—FRM_SR63) ((636—63F); (C36—C3F))

1 RC 2 RC 3 RC 4 RC 5 RC 6 RC 7 RC 8

162 Lucent Technologies Inc. Lucent T echnologies Inc. Table 123. Received Signaling Registers: DS1 Format (FRM_RSR0—FRM_RSR23) ((640—658); (C40—C58))

1. Bit 6 and Bit 5 of the DS1 receive signaling registers are copied from bit 6 and bit 5 of the DS1 transmit signaling registers.

Table 124. Receive Signaling Registers: CEPT Format (FRM_RSR0—FRM_RSR31) ((640—65F); (C40—C5F))

1. In PCS0 or PCS1 signaling mode, this bit is undefined.

1 Bit 3 Bit 2 Bit 1 Bit 0

Registers FRM_PR0—FRM_PR70 define the mode configuration of each framer. All are read/write registers. These registers are initially set to a default value upon a hardware reset, which is indicated in the register definition. default value of these registers is 00 (hex). corresponding bit in the status register to assert the interrupt pin. Table 125. Summary of Interrupt Group Enable Registers (FRM_PR0—FRM_PR7) ((660—667); (C60—C67))

164 Lucent Technologies Inc. Lucent T echnologies Inc. The default value of this register is 00 (hex). Table 126. Primary Interrupt Group Enable Register (FRM_PR0) (660; C60) 0S R 1 I E Status Register 1 Interrupt Enable Bit. A 1 enables register FRM_SR1 event interrupts. 1S R 2 I E Status Register 2 Interrupt Enable Bit. A 1 enables register FRM_SR2 event interrupts. FRM_SR6, and FRM_SR7 event interrupts. signaling buffers are ready (MOS mode). naling buffers are ready (MOS mode).

bit in registers FRM_SR1—FRM_SR7 is set. The default value of these registers is 00 (hex). Table 127. Interrupt Enable Register (FRM_PR1) (661; C61) Table 128. Interrupt Enable Register (FRM_PR2) (662; C62) Table 129. Interrupt Enable Register (FRM_PR3) (663; C63) Table 130. Interrupt Enable Register (FRM_PR4) (664; C64) Table 131. Interrupt Enable Register (FRM_PR5) (665; C65) Table 132. Interrupt Enable Register (FRM_PR6) (666; C66) Table 133. Interrupt Enable Register (FRM_PR7) (667; C67) the same bit position in the status register. the same bit position in the status register. the same bit position in the status register. the same bit position in the status register. the same bit position in the status register. the same bit position in the status register. the same bit position in the status register.

166 Lucent Technologies Inc. Lucent T echnologies Inc. The default value of this register is C0 (hex). Table 134. Framer Mode Bits Decoding (FRM_PR8) (668; C68) Table 135. Line Code Option Bits Decoding (FRM_PR8) (668; C68)

This register defines the CRC options for the framer. The default setting is 00 (hex). Table 136. CRC Option Bits Decoding (FRM_PR9) (669, C69) The bits in this register enable various control options. The default setting is 00 (hex). Table 137. Alarm Filter Register (FRM_PR10) (66A; C6A) of the Sa6 pattern relative to the receive CRC-4 submultiframe. described in ITU Rec. G.775. modes. A 1 enables the detection of FT and FS framing bit errors. FRM_PR24. A 1 enables CEPT nailed-up connect loopback in register FRM_PR24.

168 Lucent Technologies Inc. Lucent T echnologies Inc. Bit 6 and bit 7 of FRM_PR10 control the evaluation of the bursty errored parameter as defined in T able 138 below. refers to the severely errored second threshold defined in registers FRM_PR12 and FRM_PR13. Table 138. Errored Event Threshold Definition of this register is 00 (hex). Table 139. Errored Second Threshold Register (FRM_PR11) (66B; C6B) bit 7 = 0. The default value of these registers is 00 (hex). 0 0 Default values in T able 44. Event Counters Definition. Other Combinations Reserved. FRM_PR11 EST7—EST0 ES Threshold Register. FRM_PR12 SEST15—SEST8 SES MSB Threshold Register. FRM_PR13 SEST7—SEST0 SES LSB Threshold Register.

of this register is 00 (hex). Table 141. ET1 Errored Event Enable Register (FRM_PR14) (66E; C6E) Table 142. ET1 Remote End Errored Event Enable Register (FRM_PR15) (66F; C6F) responding errored event. The default value of this register is 00 (hex). Table 143. NT1 Errored Event Enable Register (FRM_PR16) (670; C70) Table 144. NT1 Remote End Errored Event Enable Registers (FRM_PR17—FRM_PR18) ((671—672);

• One occurrence of any one of these events causes an errored second count increment and a severely errored second count increment.

170 Lucent Technologies Inc. Lucent T echnologies Inc. The default value of this register is 00 (hex). Table 145. Automatic AIS to the System and Automatic Loopback Enable Register (FRM_PR19) (673; C73) ister 10 (hex), then 00 (hex), and finally 20 (hex)). Table 146. Transmit Test Pattern to the Line Enable Register (FRM_PR20) (674; C74)

• To transmit test signals using this register, registers FRM_PR69 and FRM_PR70 must be set to 00 (hex).

in the loss of receive frame alignment (RLFA) state. of the loss of CRC-4 multiframe alignment state. 3T S A I S Transmit System AIS. A 1 transmits AIS to the system. line loopback on or off commands without system intervention. line ESF FDL loopback on or off command without system intervention. a payload ESF FDL loopback on or off command without system intervention. 0T U F A I S Unframed AIS to Line Interface (All Ones Pattern). 3T Q R S Transmit Quasi-Random Signal to Line Interface (220 – 1) (ANSI T1.403). 4T L L B O N Transmit Framed Payload Line Loopback On Code: 00001. 5T L L B O F F Transmit Framed Payload Line Loopback Off Code: 001. FRM_PR22 is transmitted to the line in all time slots. 7 TICRC Transmit Inverted CRC.

The default value of this register is 00 (hex). Table 147. Framer FDL Control Command Register (FRM_PR21) (675; C75) The value programmed in this register is transmitted as the line idle code. The default value is 7F (hex). Table 148. Framer Transmit Line Idle Code Register (FRM_PR22) (676; C76) Table 149. Framer System Stuffed Time-Slot Code Register (FRM_PR23) (677; C77) 0— Reserved. Must be set to 0. 1— Reserved. Must be set to 0. 2— Reserved. Must be set to 0. 3— Reserved. Must be set to 0. 4 TFDLLAIS Transmit Facility Data Link AIS to the Line. A 1 sends AIS in the line side data link. 1 transmits the ESF performance report message with the C/R bit = 1. in the stuffed time slots to the system (CHI).

172 Lucent Technologies Inc. Lucent T echnologies Inc. back. The default value is 00 (hex) (no loopback). Table 150. Primary Time-Slot Loopback Address Register (FRM_PR24) (678; C78) Table 151. Loopback Decoding of Bits LBC[2:0] in FRM_PR24, Bits 7—5 5—7 LBC0—LBC2 Loopback Control Bits[2:0]. 001 Line Loopback (LLB). The received line data is looped back to the transmit line data. system data, and AIS is sent as the line transmit data. payload in place of the looped back time slot. in place of the looped back time slot. bit 0 is transmitted normally and also placed into time slot 0. the normal format via the CHI. mode is selected if FRM_PR10 bit 3 = 1.

Table 152. Secondary Time-Slot Loopback Address Register (FRM_PR25) (679; C79) Table 153. Loopback Decoding of Bits LBC[1:0] in FRM_PR25, Bits 6—5 0—4 STSLBA0—STSLBA4 Secondary Time-Slot Loopback Address. 5—6 SLBC0—SLBC1 Secondary Loopback Control Bits[1:0]. 01 Secondary Single Time-Slot System Loopback. 10 Secondary Single Time-Slot Line Loopback.

174 Lucent Technologies Inc. Lucent T echnologies Inc. The default value of this register is 00 (hex). Table 154. Framer Reset and Transparent Mode Control Register (FRM_PR26) (67A, C7A) forced to the default values. This bit is self-cleared. state. This bit must be cleared. reframe commands must have this bit in the 0 state first. unmodified to the line and the receive framer to pass line data unmodified to the system. The receive framer is forced not to align to the input receive data. F-bit position of the receive line data into time slot 0, bit 7 of the TCHIDA T A. line time slot 0 is inserted into time slot 0 of TCHIDA TA. unmodified to the line. The receive framer functions normally as programmed. places this bit in the F-bit position of the transmit line data. CEPT: RCHIDA T A time slot 0 is inserted into time slot 0 of the transmit line data. jitter is isolated from the transmit framer.

The default value of this register is 00 (hex). Table 155. Transmission of Remote Frame Alarm and CEPT Automatic Transmission of A Bit = 1 alarm to the line whenever the receive framer detects loss of frame alignment (RLFA). receive framer detects loss of time slot 0 multiframe alignment (RTS0LMFA). 100 ms or 400 ms timers due to loss of multiframe alignment.

4 AARSa6_8 Automatic A Bit on RSa6_8

receive framer detects the Sa6 = 1000 pattern. receive framer detects the Sa6 = 1100 pattern. frame alarm for the D4 frame format.

176 Lucent Technologies Inc. Lucent T echnologies Inc. The default value of this register is 00 (hex). Table 156. CEPT Automatic Transmission of E Bit = 0 Control Register (FRM_PR28) (67C; C7C) (binary). Otherwise, the transmit framer will not be able to locate the biframe alignment. mits system Si data to the line transparently*. bit 1 of the FAS. In CRC-4 mode, this bit is used for E-bit data in frame 13. line in bit 1 of the NOT FAS. In CRC-4 mode, this bit is used for E-bit data in frame 15. E = 0 to the line whenever the receive framer detects a CRC-4 errored checksum. of either the 100 ms or 400 ms timer due to the loss of CRC-4 multiframe alignment.

Table 157. Sa4—Sa8 Source Register (FRM_PR29) (67D; C7D) Table 158. Sa Bits Source Control for Bit 5—Bit 7 in FRM_PR29 (binary). Otherwise, the transmit framer will not be able to locate the biframe alignment. 0—4 TSa4—TSa8 Transmit Sa4—Sa8 Bit. 5—7 SaS5—SaS7 Sa Source Control Bits[2:0]. ently from the system interface*. transparently from the system interface*. FRM_PR30, or transparently from the system interface*. FRM_PR30, or transparently from the system interface*.

178 Lucent Technologies Inc. Lucent T echnologies Inc. default value of this register is 00 (hex). Table 159. Sa4—Sa8 Control Register (FRM_PR30) (67E; C7E) NOT -FAS words. If CRC-4 is enabled, this data is transmitted to the line synchronously to the CRC-4 multiframe. The default value of these registers is 00 (hex). Table 160. Sa Transmit Stack (FRM_PR31—FRM_PR40) ((67F—688); (C7F—C88)) ently from the system interface. DA TA is assumed to carry NOTFAS data that is repeated twice.

the FS bit positions. The default value of these registers is 00 (hex). Table 161. SLC-96 Transmit Stack (FRM_PR31—FRM_PR40) ((67F—688); (C7F—C88)) Table 162. Transmit SLC -96 FDL Format The default value of this register is 00 (hex). Table 163. CEPT Time Slot 16 X-Bit Remote Multiframe Alarm and AIS Control Register (FRM_PR41) CEPT signaling multiframe time slot 16 X bits. 16 signaling multiframe frame. A 0 transmits the X bits transparently. when the receive framer is in the loss of CEPT signaling (RTS16LMFA) state. mission of CEPT time slot 16 signaling remote multiframe alarm.

180 Lucent Technologies Inc. Lucent T echnologies Inc. This register is used for exercising the device in a test mode. In normal operation, it and should be set to 00 (hex). The default value of this register is 00 (hex). Table 164. Framer Exercise Register (FRM_PR42) (68A; C8A) Table 165. Framer Exercises, FRM_PR42 Bit 5—Bit 0 (68A; C8A) FEX0—FEX5 Framer Exercise Bits 0—5 (FEX0—FEX5). See T able 167. FEX6 FEX7 Second Pulse Interval.

Table 165. Framer Exercises, FRM_PR42 Bit 5—Bit 0 (68A; C8A) (continued) The default value of this register is 00 (hex). Table 166. DS1 System Interface Control and CEPT FDL Source Control Register (FRM_PR43) (68B; C8B) content of the stuffed time slot can be programmed using register FRM_PR23. In CEPT mode, bit 0—bit 2 program the Sa bit source of the facility data link. In both DS1 and CEPT modes, only the bit values shown above may be selected. SLC -96 Signaling Control (DS1 Only). A 1 enables the SLC -96 9-state signaling mode. A 0 enables 16-state signaling in the SLC -96 framing mode.

182 Lucent Technologies Inc. Lucent T echnologies Inc. This register programs various signaling modes. The default value is 00 (hex). Table 167. Signaling Mode Register (FRM_PR44) (68C; C8C) device transparently. All channels are treated as data channels. of the signaling combination of ABCD = 0000 to ABCD = 1111. 8 bits are signaling information. 3R S I Receive Signaling Inhibit. A 1 inhibits updating of the receive signaling buffer. ing information from the receive line. time slot 16 during receive loss of time slot 16 signaling multiframe alignment state. slot 16 of the transmit system data.

default value of this register is 00 (hex). Table 168. CHI Common Control Register (FRM_PR45) (68D; C8D) duce a 32 kHz signal on DIV-PLLCK. transmit and receive interfaces. Concentration Highway Interface Data Rate Select.

11 R e s e r v e d

path is not affected by this mode.

184 Lucent Technologies Inc. Lucent T echnologies Inc. This register defines the common attributes of the transmit and receive CHI. The default value is 00 (hex). Table 169. CHI Common Control Register (FRM_PR46) (68E; C8E) The default value of this register is 00 (hex). Table 170. CHI Transmit Control Register (FRM_PR47) (68F; C8F) The default value of this register is 00 (hex). Table 171. CHI Receive Control Register (FRM_PR48) (690; C90) latch in the frame synchronization signal, TCHIFS. latch in the frame synchronization signal, RCHIFS.

time slot. A 0 forces the CHI transmit highway time slot to be 3-stated. The default value of this register is 00 (hex). Table 172. CHI Transmit Time-Slot Enable Registers (FRM_PR49—FRM_PR52) ((691—694); (C91—C94)) the corresponding time slot. The default value of this register is FF (hex). Table 173. CHI Receive Time-Slot Enable Registers (FRM_PR53—FRM_PR56) ((695—698); (C95—C98)) Table 174. CHI Transmit Highway Select Registers (FRM_PR57—FRM_PR60) ((699—69C); (C99—C9C)) FRM_PR49 7—0 TTSE31—TTSE24 Transmit Time-Slot Enable Bits 31—24. FRM_PR50 7—0 TTSE23—TTSE16 Transmit Time-Slot Enable Bits 23—16. FRM_PR51 7—0 TTSE15—TTSE8 Transmit Time-Slot Enable Bits 15—8. FRM_PR52 7—0 TTSE7—TTSE0 Transmit Time-Slot Enable Bits 7—0. FRM_PR53 7—0 RTSE31—RTSE24 Receive Time-Slot Enable Bits 31—24. FRM_PR54 7—0 RTSE23—RTSE16 Receive Time-Slot Enable Bits 23—16. FRM_PR55 7—0 RTSE15—RTSE8 Receive Time-Slot Enable Bits 15—8. FRM_PR56 7—0 RTSE7—RTSE0 Receive Time-Slot Enable Bits 7—0. FRM_PR57 7—0 THS31—THS24 Transmit Highway Select Bits 31—24. FRM_PR58 7—0 THS23—THS16 Transmit Highway Select Bits 23—16. FRM_PR59 7—0 THS15—THS8 Transmit Highway Select Bits 15—8. FRM_PR60 7—0 THS7—THS0 Transmit Highway Select Bits 7—0.

186 Lucent Technologies Inc. Lucent T echnologies Inc. time slot. A 0 enables RCHIDA T A, and a 1 enables RCHIDA T AB. The default value of these registers is 00 (hex). Table 175. CHI Receive Highway Select Registers (FRM_PR61—FRM_PR64) ((69D—6A0); (C9D—CA0)) The default value of this register is 00 (hex). Table 176. CHI Transmit Control Register (FRM_PR65) (6A1; CA1) The default value of this register is 00 (hex). Table 177. CHI Receive Control Register (FRM_PR66) (6A2; CA2) FRM_PR61 7—0 RHS31—RHS24 Receive Highway Select Bits 31—24. FRM_PR62 7—0 RHS23—RHS16 Receive Highway Select Bits 23—16. FRM_PR63 7—0 RHS15—RHS8 Receive Highway Select Bits 15—8. FRM_PR64 7—0 RHS7—RHS0 Receive Highway Select Bits 7—0. ming the byte offset from 0—127. mode. In this mode, the TCHI clock runs at twice the rate of TCHIDA TA. ming the byte offset from 0—127. mode. In this mode, the RCHI clock runs at twice the rate of RCHIDA T A.

Lucent Technologies Inc. 187 Preliminary Data Sheet October 2000 T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) Lucent T echnologies Inc. Framer Register Architecture (continued) Auxiliary Pattern Generator Control Register (FRM_PR69) The following register programs the auxiliary pattern generator in the transmit framer. The default value of this reg- ister is 00 (hex). Table 178. Auxiliary Pattern Generator Control Register (FRM_PR69) (6A5; CA5)*

• To generate test pattern signals using this register, register FRM_PR20 must be set to 00 (hex).

0I T D Invert Transmit Data. Setting this bit to 1 inverts the transmitted pattern. pattern. A 0 results in a framed pattern (T1 and CEPT). Generator Pattern Select. These 4 bits select which random pattern is to be transmitted.

Description

MARK (all ones) (AIS) QRSS (2 20 – 1 with zero suppression) 5 – 1 63 (26 – 1) 511 (29 – 1) 511 (29 – 1) reversed 2047 (211 – 1) 2047 (211 – 1) reversed 215 – 1 220 – 1 220 – 1 223 – 1 1:1 (alternating) Generator Polynomial 1+x–17+x–20 1+x–3+x–5 1+x–1+x–6 1+x–5+x–9 1+x–4+x–9 1+x–9+x–11 1+x–2+x–11 1+x–14+x–15 1+x–3+x–20 1+x–17+x–20 1+x–18+x–23 Standard O.151 O.153 O.152 O.151 O.153 CB113/CB114 O.151

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II) October 2000 188 Lucent Technologies Inc. Lucent T echnologies Inc. Framer Register Architecture (continued) Pattern Detector Control Register (FRM_PR70) The following register programs the pattern detector in the receive framer. The default value of this register is 00 (hex). Table 179. Pattern Detector Control Register (FRM_PR70) (6A6; CA6)*

• T o generate/detect test pattern signals using this register, register FRM_PR20 must be set to 00 (hex).

tern. A 0 results in a search for a framed pattern (T1 and CEPT). Detector Pattern Select. These 4 bits select which random pattern is to be transmitted. MARK (all ones) (AIS) QRSS (2 20 – 1 with zero suppression) 5 – 1 63 (26 – 1) 511 (29 – 1) 511 (29 – 1) reversed 2047 (211 – 1) 2047 (211 – 1) reversed 215 – 1 220 – 1 220 – 1 223 – 1 1:1 (alternating) Generator Polynomial 1+x–17+x–20 1+x–3+x–5 1+x–1+x–6 1+x–5+x–9 1+x–4+x–9 1+x–9+x–11 1+x–2+x–11 1+x–14+x–15 1+x–3+x–20 1+x–17+x–20 1+x–18+x–23 Standard O.151 O.153 O.152 O.151 O.153 CB113/CB114 O.151

Table 180. Transmit Signaling Registers: DS1 Format (FRM_TSR0—FRM_TSR23) ((6E0—6F7); (CE0—CF7)) Table 181. Transmit Signaling Registers: CEPT Format (FRM_TSR0—FRM_TSR31) ((6E0—6FF);

• In PCS0 or PCS1 signaling mode, this bit is undefined.

190 Lucent Technologies Inc. Lucent T echnologies Inc. E00 (hex). Within these register banks, the bit map is identical for both FDL1 and FDL2. Table 182. FDL Register Set (800—80E); (E00—E0E)

upon a hardware reset. These registers are all read/write registers. Default states of all bits in this register group are also indicated in the parameter/control register map. Table 183. FDL Configuration Control Register (FDL_PR0) (800; E00)

• The FRANSIT bits (FDL_PR0 bits 4—7) must be changed only following an FDL reset or when the FDL is idle.

Table 184. FDL Control Register (FDL_PR1) (801; E01) ate a single interrupt before the interrupt bit is cleared by reading register FDL_SR0. (01111110) in the absence of transmit FDL information. This bit resets to 0. codes needed for indicating a valid code. The default is ten (1010 (binary))*. data interface. This bit resets to 0. ignored. This bit resets to 0. receiver into an inactive state. This bit resets to 0. transmitter into an inactive state. This bit resets to 0. 4F R R FDL Receiver Reset. FRR = 1 generates an internal pulse that resets the FDL receiver. OVERRUN interrupts are cleared. This bit resets to 0. and forced to 1 in the transparent mode. This bit resets to 0. receive FDL FIFO. This bit resets to 0. once per second. The PRM is followed by either idles or flags transmitted after the PRM. When this bit is 0, the transmit FDL expects data from the microprocessor interface.

192 Lucent Technologies Inc. Lucent T echnologies Inc. Table 185. FDL Interrupt Mask Control Register (FDL_PR2) (802; E02) grammed empty level (see register FDL_PR3). FTEIE is cleared upon reset. is cleared upon reset and is not used in the transparent mode. grammed full level (see register FDL_PR6). FRFIE is cleared upon reset. receiver. FREOFIE is cleared upon reset and is not used in the transparent mode. cleared upon reset and is not used in the transparent mode. ted frames (for test purposes) until the FTBCRC bit is cleared to 0.

Table 186. FDL Transmitter Configuration Control Register (FDL_PR3) (803; E03)

1. Do not set FT ABT = 1 and FTFC = 1 at the same time.

Table 187. FDL Transmitter FIFO Register (FDL_PR4) (804; E04) Table 188. FDL Transmitter Idle Character Register (FDL_PR5) (805; E05) positions in the transmit FIFO which triggers a transmitter-empty (FTEM) interrupt. FIFO locations is obtained by reading the transmit FDL status register FDL_SR1. ten FTABT . The last value written to FT ABT is available for reading. cleared by writing to this bit. Clearing this bit has no effect on a previously written FTFC. The last value written to FTFC is available for reading.

194 Lucent Technologies Inc. Lucent T echnologies Inc. Table 189. FDL Receiver Interrupt Level Control Register (FDL_PR6) (806; E06) Table 190. FDL Register FDL_PR7 Table 191. FDL Receiver Match Character Register (FDL_PR8) (808; E08)

7 FRANSIE FDL Receiver

condition is generated whenever a valid ANSI code is received. the receive FDL unit searches the incoming bit stream for the receiver match character. ion (register FDL_PR9 bit 4 = 0) or only on byte boundaries (register FDL_PR9 bit 4 = 1).

Table 192. FDL Transparent Control Register (FDL_PR9) (809; E09)

• The octet boundary is relative the first receive clock edge after the receiver has been enabled (ENR, FDL_PR1 bit 2 = 1).

Table 193. FDL Transmit ANSI ESF Bit Codes (FDL_PR10) (80A; E0A) FDL_PR9 bit 3 (FMSTAT) is set to 1. A value of 111 (binary) indicates byte alignment. ister FDL_PR9 bit 0—bit 2) are set to 111 (binary). receive FDL unit searches for the receive match character in a sliding window fashion. bit is 0, the transmitter sends ones idle characters when the transmit FIFO is empty. cessing on incoming or outgoing data. 0X1X2X3X4X50, where the order of transmission is from left to right.

196 Lucent Technologies Inc. Lucent T echnologies Inc. Table 194. FDL Interrupt Status Register (Clear on Read) (FDL_SR0) (80B; E0B) operation of the FIFO. Following an FDL receive FIFO overrun, data extracted prior to the required reset may be corrupted. loaded above the programmed empty level. interrupt is not generated in the transparent mode. register. This interrupt is not generated in the transparent mode. (FDL_PR2 bit 5) is set. This status bit is cleared to 0 by a read of this register*. read of this register. This interrupt is not generated in the transparent mode.

7 FRANSI FDL Receive

FDL_PR6 bit 7 = 1. This status bit is cleared to 0 by a read this register.

Table 195. FDL Transmitter Status Register (FDL_SR1) (80C; E0C)

• The count of FDL_SR1 bits 0—6 includes SF byte.

Table 196. FDL Receiver Status Register (FDL_SR2) (80D; E0D) in bit 0—bit 6 of this status register is the number of bytes including SF byte that may be read from the FIFO. The 6-bit code extracted from the ANSI code 111111110X0X1X2X3X4X50 is stored in this register. Table 197. Receive ANSI FDL Status Register (FDL_SR3) (80E; E0E) FDL reset to restore proper FDL operation. Table 198. FDL Receiver FIFO Register (FDL_SR4) (807; E07) transmit FIFO*. The bits are encoded in binary where bit 0 is the least significant bit. bit 0 is the least significant bit*. bytes up to and including the first SF byte. 0—7 FRD0—FRD7 FDL Receive Data. The user data received via the FDL block are read through this register.

198 Lucent Technologies Inc. Lucent T echnologies Inc. Table 199. Global Register Set Table 200. Line Interface Unit Register Set*

• The logic value in parentheses below each bit definition is the default state upon completion of hardware reset.

† These bits must be written to 1.

Table 201. Framer Unit Status Register Map

• Unbracketed contents are valid for DS1 modes. Bracketed contents, [], are valid for CEPT mode.

200 Lucent Technologies Inc. Lucent T echnologies Inc. Table 201. Framer Unit Status Register Map (continued)

• Unbracketed contents are valid for DS1 modes. Bracketed contents, [], are valid for CEPT mode.

Table 202. Receive Signaling Registers Map modes, these bits are in the 0 state and should be ignored. † In the DS1 signaling modes, these registers contain unknown data. ‡ In DS1 4-state and 2-state signaling, these bits contain unknown data. § In DS1 2-state signaling, these bits contain unknown data. ** In the CEPT signaling modes, the A-, B-, C-, D-, and P-bit information of these registers contains unknown data.

202 Lucent Technologies Inc. Lucent T echnologies Inc. Table 203. Framer Unit Parameter Register Map

660 C60

661 C61

662 C62

663 C63

664 C64

665 C65

666 C66

667 C67

668 C68

669 C69

670 C70

671 C71

672 C72

673 C73

674 C74

Table 203. Framer Unit Parameter Register Map (continued)

675 C75

676 C76

677 C77

678 C78

679 C79

680 C80

681 C81

682 C82

683 C83

689 C89

204 Lucent Technologies Inc. Lucent T echnologies Inc.

690 C90

691 C91

692 C92

693 C93

694 C94

695 C95

696 C96

697 C97

698 C98

699 C99

Table 204. Transmit Signaling Registers Map received signaling registers. In the CEPT signaling modes, these bits are ignored. † These bits contain unknown data. ‡ In DS1 4-state and 2-state signaling modes, these bits contain unknown data. § In DS1 2-state signaling mode, these bits contain unknown data. ** In the CEPT signaling modes, the A-, B-, C-, D-, and P-bit information of these registers contains unknown data. †† In the DS1 signaling modes, these registers contain unknown data.

206 Lucent Technologies Inc. Lucent T echnologies Inc. Table 205. Facility Data Link Register Map

800 E00

801 E01

802 E02

803 E03

804 E04

805 E05

806 E06

808 E08

809 E09

807 E07

periods can adversely affect device reliability. Table 206. ESD Threshold Voltage

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II) October 2000 208 Lucent Technologies Inc. Lucent T echnologies Inc.

Electrical Characteristics

Logic Interface Characteristics Table 207. Logic Interface Characteristics (TA = –40 °C to +85 °C, VDD = 5.0 V ± 5%, VSS = 0) All inputs are driven between 2.4 V and 0.4 V . JTAGTDI, JTAGTCK, and JT AGTMS pins. An internal 50 kΩ pull-down is provided on the JT AGRST pin.

Lucent Technologies Inc. 209 Preliminary Data Sheet October 2000 T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II) Lucent T echnologies Inc. Outline Diagram 144-Pin TQFP Dimensions are in millimeters. 5-3815(F)r.6 DETAIL A 0.45/0.75 GAGE PLANE SEATING PLANE

1.00 REF

0.25 DETAIL B 0.19/0.27 0.08 M 0.106/0.200

1.60 MAX

0.08

0.50 TYP

1.40 ± 0.05 0.05/0.15 DETAIL A DETAIL B PIN #1 IDENTIFIER ZONE 20.00 ± 0.20 22.00 ± 0.20 109144 37 72 108 20.00 ± 0.20 22.00 ± 0.20

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II) October 2000 Lucent T echnologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. SLC is a registered trademark of Lucent T echnologies. Copyright © 2000 Lucent T echnologies Inc. All Rights Reserved October 2000 DS00-191TIC (Replaces DS98-234TIC) For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro, or for FPGA information, http://www.lucent.com/orca E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent T echnologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, P A 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA P ACIFIC: Microelectronics Group, Lucent T echnologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent T echnologies (China) Co., Ltd., A-F2, 23/F , Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P . R. China Tel. (86) 21 6440 0468, ext. 325, FAX (86) 21 6440 0652 JAP AN: Microelectronics Group, Lucent T echnologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, T okyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DA T ALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 T echnical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), IT AL Y: (39) 02 6608131 (Milan), SP AIN: (34) 1 807 1441 (Madrid)

Ordering Information

Device Code Package Temperature Comcode (Ordering Number) T - 7630 - - - TL - DB 144-Pin TQFP –40 °C to +85 °C 107913337