T7570 AGERE | Alldatasheet
Document overview
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Technical content
Features
n Programmable internal hybrid-balance network n Programmable transmit gain — 19.4 dB range, 0.1 dB step size n Programmable receive gain — 19.4 dB range, 0.1 dB step size n Dual-programmable PCM interface — Up to 64 time slots per frame — Variable data rate (64 kHz to 4.096 MHz) — Two timing modes n Programmable m -law or A-law companding n 300 W drive receive amplifier n Analog and digital loopbacks n On-chip sample-and-hold, autozero, and precision voltage reference n Single 5 V power supply n Latch-up free, low-power CMOS technology — 70 mW typical operating power dissipation — 1.5 mW typical standby power dissipation n Serial microprocessor-control interface n 6-pin parallel I/O latch n TTL- and CMOS-compatible digital I/O n Meets or exceeds D3/D4 (as per Lucent PUB 43801), ITU-T (formerly CCITT) G.711—G.714, and LSSGR requirements n Operating temperature range: –40 C to +85 C
Description
The Lucent Technologies Microelectronics Group T7570 Programmable PCM Codec with Hybrid-Bal- ance Filter is a programmable PCM codec with an internal hybrid-balance network filter. It provides ana- log-to-digital and digital-to-analog conversion, as well as the transmit and receive filtering necessary to interface a voice telephone circuit to a time-division multiplexed (TDM) system. Programmable features include transmit gain setting over a 19.4 dB range and receive gain setting over a 19.4 dB range. An internal filter can be programmed to provide hybrid balancing over a wide range of loop impedances for both active and transformer subscriber line interface circuits (SLIC). The device is programmed over a low pin-count, standard, serial, microprocessor-control interface. A 6-pin parallel input/output latch is provided to control interface circuits. Each of these pins can be individu- ally programmed to be an input or an output. The T7570 is fabricated by using a low-power CMOS technology, requires a single 5 V supply, and is avail- able in a 28-pin PLCC package for surface mounting.
2 Lucent Technologies Inc. T7570 Programmable PCM Codec Data Sheet with Hybrid-Balance Filter October 1996 Table of Contents Content Page
Table 1. Pin Description
1 GND —
. All analog and digital signals are referenced to this pin. Receive Analog Power Amplifier Output. output as a voice-frequency signal. Connections may be made to or traces may be routed through this pin. Do not make connections to or route traces through pins 4 and 5. written into the ILR appears at the corresponding IL pins. mode using the internal time-slot assignment counter). on the falling edges of BCLK.
11 CO O
when is low. It can be connected to CI if required.
12 CI I
is low. It can be connected to CO if required.
13 CCLK I
or read from the T7570 via the CI and CO pins.
15 MR I
This logic input must be pulled low for normal operation of the T7570. are reset to the states specified under powerup initialization.
16 BCLK I
MCLK at the start of each frame. MCLK can be used as BCLK.
17 MCLK I
Backplane Line Driver Enable (Active-Low). output pulls low to enable a backplane line driver.
Transmit Analog High-Impedance Input. tializes the T7570 and puts it into the powerdown state. P bit set to 1, as indicated in Table 2.
6 Lucent Technologies Inc. T7570 Programmable PCM Codec Data Sheet with Hybrid-Balance Filter October 1996 Functional Description (continued) Transmit Filter and Encoder (continued) converter has a compressing characteristic according to the standard ITU-T A- or m -coding laws selected by a control instruction (see Tables 2 and 3). A precision on- chip voltage reference helps ensure accurate and highly stable transmission levels. Any offset voltage arising in the gain-set amplifier, the filters, or the com- parator is canceled by an internal autozero circuit. Decoder and Receive Filter PCM data is shifted into the decoder's receive PCM register via the D R 0 or D R 1 pin during the selected time slot on eight falling edges of BCLK. The decoder con- sists of an expanding digital-to-analog convertor with either A- or m -law decoding characteristic, which is selected by the same control instruction used to select the encode law. Following the decoder is a fifth-order, low-pass, switched-capacitor filter with Sin(x)/x correc- tion for the 8 kHz sample and hold. A programmable gain amplifier that is set by writing to the receive gain register is included, followed by a power amplifier capa- ble of driving a 300 W load to 4.0 V peak to peak. PCM Interface The FS X and FS R frame-sync inputs determine the beginning of the 8-bit transmit and receive time slots, respectively. They can have any duration from a single cycle of BCLK high to one MCLK period low. Two differ- ent relationships can be established between the frame-sync inputs and the actual time slots on the PCM buses by setting bit 3 in the control register (see Table 3). Nondelayed data mode is similar to long- frame timing of other codecs for which time slots begin nominally coincident with the rising edge of the appro- priate FS input. The alternative is to use delayed-data mode in which each FS input must be high at least a half-cycle of BCLK earlier than the time slot. The time- slot assignment circuit on the device can only be used with delayed-data timing. The time-slot assignment capability of this device is a subset of the Lucent concentration highway interface. The beginning of the first time slot in a frame is identi- fied by the appropriate FS input. The actual transmit and receive time slots are then determined by the inter- nal time-slot assignment counters. Transmit and receive frames and time slots can be skewed from each other by any number of BCLK cycles by offsetting FS R and FS X . During each assigned trans- mit time slot, the selected D X 0/1 output shifts data out from the PCM register on the rising edges of BCLK. X 0 (or X 1 as appropriate) also pulls low for the first 7.5 bit times of the time slot to control the high- impedance state enable of a backplane line driver. Serial PCM data is shifted into the selected D R 0/1 input during each assigned receive time slot on the falling edges of BCLK. D X 0 or D X 1 and D R 0 or D R 1 are select- able on the T7570 (see the Port Selection section under Programmable Functions). Serial Control Port Programmable register instructions (Table 2) are writ- ten into or read back from the T7570 via the serial con- trol port consisting of the control clock (CCLK), the serial data input (CI) and output (CO), and the chip- select input ( ) (see Figure 6). All instructions require 2 bytes, with the exception of a single-byte powerup/powerdown command. The bits in byte 1 are defined as follows: bit 7 specifies powerup or power- down; bits 6, 5, 4, and 3 specify the register address; bit 2 specifies whether the instruction is a read or a write; bit 1 specifies a one- or two-byte instruction; and bit 0 is not used. To shift control data into the T7570, CCLK must be pulsed high eight times while is low. Data on the CI input is shifted into the serial input register on the fall- ing edge of each CCLK pulse. After all data is shifted in, the contents of the input shift register are decoded and can indicate that a second byte of control data follows. This second byte can either be defined by a second byte wide pulse or can follow the first con- tiguously; it is not mandatory for to return high between the first and second control bytes. At the end of the eighth CCLK pulse in the second con- trol byte, the data is loaded into the appropriate pro- grammable register. can remain low continuously when programming successive registers, if desired. However, should be set high when no data trans- fers are in progress. To read back interface latch data or status information from the T7570, the first byte of the appropriate instruc- tion, as defined in Table 2, is strobed in during the first pulse. must then be taken low for a further eight CCLK cycles, during which the data is shifted onto the CO pin on the rising edges of CCLK. When is high, the CO pin is in the high-impedance state, enabling the CO pins of many devices to be multiplexed together. TS TS CS CS CS CS CS CS CS CS CS
while the device is powered up or down. ond FSX pulse after powerup. the bit functions shown in Tables 3, 5, 6, 7, 8, and 9. Table 2. Programmable Register Instructions Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI and CO pins. X = don't care. P is the powerup/down control bit (0 = powerup, 1 = powerdown); see Powerup/Powerdown Control section. Other register address codes are invalid and should not be used. Write Control Register P 000001X See Table 3. Write Interface Latch Register P 000101X See Table 6. Write Latch Direction Register P 001001X See Table 5. Write Receive Gain Register P 010001X See Table 9. Write Transmit Gain Register P 010101X See Table 8. Write Receive Time Slot/Port P 100101X See Table 7. Write Transmit Time Slot/Port P 101001X See Table 7.
Table 3. Control Register Byte 2 Functions
- State at powerup initialization (bit 4 = 0).
Table 4. Coding Law Conventions Note: The MSB is always the first PCM bit shifted in or out of the T7570. to select the correct internal divider. and DL bits in the control register as shown in Table 3.
and DL bits in the control register as shown in Table 3. programming the receive gain register to all 0s. appropriate instruction to the LDR (see Tables 2 and 5). pins should be programmed as outputs. Table 5. Byte 2 Functions of Latch Direction source, such as the off-hook detect output of a SLIC. ond byte of a read of the ILR. grammed first, followed immediately by the LDR. Table 6. Interface Latch Data Bit Order Bit Number tionship with each other in BCLK period increments. enable two-way space switching to be implemented. only be used in delayed-data timing mode.
0 L1 L2 L3 L4 L5 XX
0 Input
1 Output
Table 7. Time-Slot and Port Assignment Instruction
- T5 is the MSB of the time-slot assignment.
Round n to the nearest integer and convert to binary. This is the code required by byte 2 of this instruction. Some examples are given in Table 8. Table 8. Byte 2 of Transmit Gain Instructions permitted. However, large signals may cause overload.
Round n to the nearest integer and convert to binary. This is the code required by byte 2 of this instruction. Some examples are given in Table 9. Table 9. Byte 2 of Receive Gain Instructions permitted. However, large signals may cause overload. the transmit input relative to the receive output signal. to higher audio-frequency signals. be corrected by the programmable attenuator. pole/zero frequency can be programmed. filter should be deselected to bypass it. nonloaded loop test networks in the United States. balance performance over the voice band.
Figure 3. Block Diagram Hybrid-Balance Filter Network On initial powerup, the hybrid-balance filter is disabled. select pole and zero frequency. program zero frequency in Hybal2 filter. and the hybrid-balance filter designed to replicate it. best balance filter register settings.
already present, an extra-long ground pin on the connector should be used. tance capacitor of at least 10 mF , located near the card edge connector. periods can adversely affect device reliability. Table 10. Human-Body Model ESD Threshold
14 Lucent Technologies Inc. T7570 Programmable PCM Codec Data Sheet with Hybrid-Balance Filter October 1996
Electrical Characteristics
For all tests, TA = –40 °C to +85 °C, VDD = 5 V – 5%, and GND = 0 V, unless otherwise noted. Typical values are for TA = 25 °C and nominal supply values. dc Characteristics Table 11. Digital Interface Table 12. Power Dissipation
Table 13. Analog Interface Table 14. Gain and Dynamic Range
Table 14. Gain and Dynamic Range (continued)
5 V, minimum gain < GR < maxi-
Table 15. Envelope Delay Distortion
Table 16. Noise
- PPSRX is measured with a –50 dBm0 activation signal applied to VFXI.
4600 Hz—7600 Hz — — –30 dB
7600 Hz—8400 Hz — — –40 dB
8400 Hz—50,000 Hz — — –30 dB
Table 17. Distortion Table 18. Crosstalk
- CTR–X and PPSR X are measured with a –50 dBm0 activation signal applied to VFXI.
n All input signals are defined as VIL = 0.4 V, VIH = 2.7 V, tR < 10 ns, tF < 10 ns. n tR is measured from VIL to VIH. tF is measured from VIH to VIL. n Delay times are measured from the input signal valid to the output signal valid. n Setup times are measured from the data input valid to the clock input invalid. n Hold times are measured from the clock signal valid to the data input invalid. n Pulse widths are measured from VIL to VIL or from VIH to VIH. Table 19. Master Clock Timing (See Figures 4 and 5.)
Table 20. PCM Interface Timing (See Figures 4 and 5.)
Table 21. Serial Control Port Timing (See Figure 6.) Table 22. Interface Latch Timing (See Figure 6.) Table 23. Master Reset Pin
Figure 6. Serial Control Port Timing
26 Lucent Technologies Inc. T7570 Programmable PCM Codec Data Sheet with Hybrid-Balance Filter October 1996 Outline Diagrams 28-Pin PLCC Dimensions are shown in inches. 5-2608r.4
1.27 TYP
0.53 MAX
4.57 MAX
0.10 SEATING PLANE
0.51 MIN
11.58 MAX 12.57 MAX
11.58 MAX
12.57 MAX
PIN #1 IDENTIFIER ZONE
27Lucent Technologies Inc. Data Sheet T7570 Programmable PCM Codec October 1996 with Hybrid-Balance Filter
Ordering Information
Device Code Package Temperature Comcode T - 7570 - - - ML2 28-Pin PLCC –40 °C to +85 °C 107055782 T - 7570 - - - ML2 -TR 28-Pin PLCC, Tape and Reel –40 °C to +85 °C 107056525
For additional information, contact your Microelectronics Group Account Manager or the following: INTERNE T: http://www .lucent.com/micro U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103, 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106), e-mail docmaster@mic ro.lucent.com ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 JAPAN : Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagaw a-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 For data requests in Europe: MIC R OELECT R ONICS G R OUP DATALINE: Tel. (44) 1734 324 299, FAX (44) 1734 328 148 For technical inquiries in Europe: CENTRAL EU R OPE : (49) 89 95086 0 (Munich), NORTHERN EU R OPE : (44) 1344 865 900 (Bracknell UK), FRANCE : (33) 1 47 67 47 67 (Paris), SOUTHERN EUR OPE : (39) 2 6601 1800 (Milan) or (34) 1 807 1700 (Madrid) Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Co pyright © 1996 Lucent Technologies Inc. All Rights Reserved October 1996 DS96-223ALC (Replaces DS92-224TCOM and AY93-026TCOM) Printed On Recycled Paper