T7264

T7264 AGERE | Alldatasheet

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Technical content

Features

n U-interface 2B1Q transceiver — Range over 18 kft on 26 AWG — ISDN basic-rate 2B+D — Full-duplex, 2-wire operation — 2B1Q four-level line code — Conforms to ANSI North American Standard T1.601-1992 — Supports NT quiet mode and insertion loss test mode for maintenance n K2 interface — 2B+D data — 512 kbits/s TDM interface — Frame and superframe markers — Embedded operations channel (eoc) — U-interface M bits and crc results — Device control and status n Other — Single +5 V ( 5%) supply — –40 C to +85 C — 44-pin PLCC n Power consumption — Operating 275 mW typical — Idle mode 30 mW typical n Analog front end — On-chip line driver for 2.5 V pulses — On-chip balance network — Sigma-delta A/D converter — Internal 15.36 MHz crystal oscillator — Supports 15.36 MHz external clock input n Digital signal processor — Digital timing recovery (pull range 250 ppm) — Echo cancellation (linear and nonlinear) — Accommodates distortion from bridged taps — Scrambling/descrambling — crc calculations — Selectable LT or NT operation — Start-up sequencing with timers — Activation/deactivation support — Cold start in 3.5 seconds (typical) — Warm start in 200 ms (typical) — U-frame formatting and decoding

Description

The Lucent Technologies Microelectronics Group T7264 U-Interface 2B1Q Transceiver integrated cir- cuit provides full-duplex, basic-rate (2B+D) integrated services digital network (ISDN) communications on a 2-wire digital subscriber loop at either the LT or NT and conforms to the ANSI North American Standard T1.601-1992. The single +5 V CMOS device is pack- aged in a 44-pin plastic leaded chip carrier (PLCC). 5-5161 Figure 1. T7264 Simplified Block Diagram

cessing, control, and access functions). C = crystal oscillator pins. Figure 2. Pin Diagram Table 1. Pin Functions

Table 2. Pin Descriptions

1 DI I

terface at 512 kbits/s. Latched on falling edge of C clock.

2 MTC I

clock. In the NT mode (MODE0 = 0), this input is not used.

3 C O

512 kbits/s K2 Bit Clock Output.

4 DO O

terface at 512 kbits/s. Changes on the rising edge of C clock.

5 F O

+5 V Supply for Digital Circuits. Internally connected together. the transceiver in reset indefinitely without the need to access the K2 interface. 1.0 ms is required before the device is fully functional.

8 FFC I

Freeze Frequency Control (Active-Low). latched on the rising edge of every RCLKEN.

9 ILOSS I

Insertion Loss Test (Active-Low). transceiver performs a reset when this pin returns to its inactive state. 0 Configure for chip being used on the NT end of loop. 1 Configure for chip being used on the LT end of loop. 0 Disables autoreporting of nebe to febe. 1 Enables autoreporting of nebe to febe. Ground Supply for Digital Circuits. Internally connected together.

16 OSYNC O

+5 V Supply for the Crystal Oscillator.

19 GND

Ground Supply for Oscillator.

20 X1 I

Connection #1 for a 15.36 MHz Crystal.

21 X2 I

Connection #2 for a 15.36 MHz Crystal.

23 CKOUT O

24 MCLK I

25 CKSEL I

26 HIGHZ I

High Impedance (Active-Low). Causes all digital outputs to become 3-stated.

28 VCM —

Common-Mode Voltage Reference for the Analog Circuits. as close to this pin and pin 34 as possible.

29 VRP —

Positive Voltage Reference for the Analog Circuits. as close to this pin and pin 34 as possible.

30 VRN —

Negative Voltage Reference for the Analog Circuits. as close to this pin and pin 34 as possible.

31 HN I

Hybrid Network Connection, Negative Side.

32 LOP O

Line Driver Output Terminal, Positive Side. +5 V Supply for Analog Circuits. Ground Supply for Analog Circuits.

35 LON O

Line Driver Output Terminal, Negative Side.

36 HP I

Hybrid Network Connection, Positive Side.

37 SDINN I

Sigma-Delta A/D Converter Input, Negative Side.

38 SDINP I

Sigma-Delta A/D Converter Input, Positive Side.

43 RCLKEN O

Defines receive baud period (rising edge to rising edge).

Table 3. Clock Configuration time of the 10.24 MHz period. Figure 3. Quat Example

15.36 MHz (free-running)

10.24 MHz (phase-locked)

7.68 MHz (free-running)

15.36 MHz

system clock in the LT or to the line clock in the NT. tion, and rate adaption for output onto the K2 interface. proper operation on subscriber loops with bridged taps.

vide the control necessary to complete the state table. over 18 kft of 26 AWG loop cable. pair of 16.9 W resistors, and then drives the 135 W line. Figure 4. Line Interface and Protection

16.9 W – 7%

16.9 W – 1%

the analog circuitry to fully power up before the chip becomes fully functional. three K2 frames, is sufficient to complete the reset process. When the chip is in the reset state, the output of the line driver is at 0 V and the transmit data is also 0 V. Figure 6. RESET Waveform Normal Operation Figure 7. RESET Timing for Synchronized Clocks

1 MCLK PERIOD

2 MCLK PERIODS

1010 Lucent Technologies Inc. Data Sheet April 1998T7264 U-Interface 2B1Q Transceiver Device Interface and Connections (continued) Idle Mode A low-power idle mode is implemented on the T7264 to reduce the power consumption to typically 30 mW when it is not active. All internal coefficients are saved in this idle mode to reduce time for a subsequent start-up. There are three ways that idle mode can be entered: n If the loop is operational, the local deactivation com- mand (ldea) in the LT mode via the K2 interface causes the deactivation procedure specified in the ANSI standard. At the conclusion of the deactivation procedure, shutdown of the line driver and activation of the tone detector occurs. If no tone is detected within 48 ms, the idle mode is entered. This 48 ms window constitutes the RECEIVE RESET criteria in the ANSI standard. n If a failure condition is encountered (e.g., the loop never comes up), a procedure similar to deactivation is followed. The only difference is the duration of the window, which is set internally by the type of failure condition. n As long as either the afrst (via the K2 interface) or the RESET pin is active, the transceiver remains in the powerup reset state. At the cessation of the reset condition, the transceiver changes to the idle state. There are four ways of bringing the device out of the idle mode: n An initiate start-up procedure (istp) command is received via the K2 interface by the device. n A reset (afrst or external RESET) command is received by the device. n A tone is detected by the tone detector. n A command to enter any of the test modes (loopback and insertion loss) is received by the device. Internal timing ensures that the digital signal processor blocks do not change state during the idle mode-to- powerup process. In addition, the start-up process has been designed to prevent glitches on the line as the driver powers up. NT Maintenance ANSI T1.601-1992 defines NT quiet mode operation and an insertion loss measurement, and support for these is available from the T7264. Detection of the trig- ger signals is done by other hardware which notifies the system controller, and the system controller then sig- nals the T7264 as needed to do the following: n To enter the quiet mode, the chip is placed in reset. n When an insertion loss measurement is requested, ILOSS (pin 9) is asserted low. This causes the trans- mitter to continuously send SN1 and places the receiver in reset. When the test is completed or ter- minated, ILOSS is asserted high and the chip is reset. Priority between RESET and ILOSS is described in the Priority section of this document (page 31).

1212 Lucent Technologies Inc. terfaces onto a single higher-speed highway. trunk onto a common interface. only a single U-interface is needed). Figure 10. K2 Interface LT and NT

• • • K2-TO- SYSTEM BACK- PLANE LOGIC K2 NT1 LOGIC F C DI DO 4-WIRE S/T -INTERFACE NT LT
• • • CO SWITCHNT1

reserved for future use and should always be set to 1. obtain proper system-level operation. their value when the transceiver is operational. Table 4. K2 Interface Serial Data Bit Map

• Items differ dependent upon NT or LT mode.

Figure 11. K2 Interface Frame Format

Table 5. B1, B2, D, and S1 Octets (Overview) Table 6. B1, B2, D, and S1 Octets (Functions) first bit of the B1 octet sent or received. first bit of the B2 octet sent or received. is the first bit of the D pair sent or received. DF 5 RSF Receive Superframing. 12.5% duty cycle at an 83.333 Hz rate (12 ms). 0—Last 84 K2 frames of the superframe. 1—First 12 K2 frames and during reset state up to point T6 or T7. DF 6 RF Receive Framing. 50% duty cycle at a 666.66 Hz rate (1.5 ms). 0—Last six K2 frames of the U frame. 0 to 1—Marks every 12th K2 frame of 2B+D data. Corresponds to the first 2B+D data of the U frame. 1—First six K2 frames and during reset state up to point T6 or T7. DF 7 TSF Transmit Superframing. 12.5% duty cycle at an 83.333 Hz rate (12 ms). 0 to 1—Marks the first K2 frame of 2B+D data. Corresponds to the first 2B+D data of the U superframe. 1—First 12 K2 frames and during reset state up to point T6 or T7. DF 8 TF Transmit Framing. 50% duty cycle at a 666.66 Hz rate (1.5 ms). 0—Last six K2 frames of the U frame. 0 to 1—Marks every 12th K2 frame of 2B+D data. Corresponds to the first 2B+D data of the U frame. 1—First six K2 frames and during reset state up to point T6 or T7. S1 1—8 S11—S18 S1 Octet. All bits of the S1 octet are set to 1.

Table 7. UM1 and UM2 Octets—eoc Bits (Overview) Table 8. UM1 and UM2 Octets—eoc Bits (Functions) Additional details on eoc bits can be found in T1.601. UM2 6 DO/DI i5 i6 i7 i8 See next page. 001—LT to NT intermediate address. 010—110—LT to NT, decrement address and pass on. 001—101—NT to LT, increment address and pass on. UM1 4 dm Data or Message Indicator. Information. eoc channel message information. 01010000—Operate 2B+D loopback. 01010001—Operate B1 channel loopback. 01010010—Operate B2 channel loopback. 01010011—Request corrupt crc. 01010100—Notify of corrupted crc.

Table 9. UM2 and UM3 Octet—UCS Bits (Overview) Table 10. UM2 and UM3 Octet—UCS Bits (Functions) K2 except during a start-up when it is forced to a 0 on the K2. 1—Ready to transmit information. to the K2. Transmit should always be set to a 1. from the U to the K2 at the LT. When both ps1 and ps2 are 0, this indicates a dying gasp. warning to the far-end NT without deactivating the local transceiver. to the K2 interface. Transmit should always be set to a 1. MODE1, the febe bit is passed transparently from the U-interface to the K2 interface. 0—Error indication passed to the originator. 1—No error, or feature is not utilized. from the U to the K2 at the LT. When both ps1 and ps2 are 0, this indicates a dying gasp. from the U to the K2 at the LT. 0—The NT is currently in a test mode.

Table 10. UM2 and UM3 Octet—UCS Bits (Functions) (continued) Table 11. DS Octet (Overview)—Device Status Table 12. DS Octet (Functions)—Device Status from the U to the K2 at the LT. 0—Cold and warm start capability. the U to the K2 interface (DONT ). Transmit should always set to a 1. face at the NT and from the U to the K2 interface at the LT. 0—No activity at the S/T-interface. 1—Activity (INFO1 or INFO3) at S/T-interface. at the LT and from the U to the K2 interface at the NT. 0—Request S/T deactivation at the NT. 1—Allow S/T activation at the NT. set to 1 in customer premises equipment. and from the U to the K2 interface at the NT. 0—Failure of intermediate 2B+D transparent element. 1—Transmission path is established between NT and local exchange. DS 1 nebe Near-End Block Error. 0—crc error detected in previously received U frame. DS 2 xact Transceiver Active. 0—Transceiver in reset state. 0 to 1—Detection of a tone or istp = 0. 1 to 0—On reset, 480 ms after loss of sync or deactivation. DS 3 — Undefined. May be either a 1 or a 0. DS 4, 6, 8 — Reserved. In normal operation, these bits are 1. 1 to 0—Initiates the 480 ms loss of synchronization timer.

Table 13. DC Octet (Overview) Table 14. DC Octet (Functions) transmitted by the transceiver to the U-interface. 0—Corrupt crc generation as long as bit is low. 1—Generate correct crc (normal). DC 2 istp Initiate Start-Up. This bit is used to notify the transceiver of an activation request. 0—Initiate start-up (activation request). 1—Reset state (transceiver inactive). DC 4 afrst Adaptive Filter Reset. to MTC synchronization (LT) is not lost. DC 5 ldea Local Deactivation. 1 — Deactivate. DO 2B+D and UM set equal to 1. of signal (on second dea = 0) and held until xact goes low for proper deactivation. DC 6 — Reserved. For normal operation, this bit must be set to 1. 1—LT mode 2B+D = 0 transmitted across the U-interface. 1—NT mode 2B+D = 1 transmitted across the U-interface. ways remains transparent after start-up.

Table 15. K2 Data Out (DO) Bit Levels Table 16. K2 Device Control (DC) Bit Levels

sync word (ISW). The six overhead bits from each of the eight U frames, when taken together, form the 48 M bits. The following diagram shows how U frames, superframes, and M bits are mapped. Figure 12. U-Interface Frame and Superframe shows the different groups of bits in the superframe. Figure 13. U-Interface Superframe Bit Groups

1 ISW CONTROL & STATUS (UCS)

Table 17. U-Interface Bit Assignment

• LT(NT). Values in parentheses () indicate meaning at the NT.

T7264. A K2 frame consists of eight DO octets and eight DI octets which occur every 125 ms (every frame sync). Figure 14 shows the K2 frame structure. Figure 14. K2 Octet Description Figure 15 shows the points of origination and destination of bits on the K2 and U-interfaces at the LT and NT. Figure 15. K2 Functional Description

1 ISW 2B+D eoca1 eoca2 eoca3 act R 1, 5 R 1, 6

2 SW 2B+D eocdm eoci1 eoci2 dea (ps1)* R 2, 5 febe

3 SW 2B+D eoci3 eoci4 eoci5 R 3, 4 (ps2)* crc1 crc2

4 SW 2B+D eoci6 eoci7 eoci8 R 4, 4 (ntm)* crc3 crc4

5 SW 2B+D eoca1 eoca2 eoca3 R 5, 4 (cso)* crc5 crc6

6 SW 2B+D eocdm eoci1 eoci2 R 6, 4 crc7 crc8

7 SW 2B+D eoci3 eoci4 eoci5 uoa (sai)* crc9 crc10

8 SW 2B+D eoci6 eoci7 eoci8 aib (nib)* crc11 crc12

96 K2 frames transferred at a data rate of 512 kbits/s. the DS octet provides indication of a crc error. cates the occurrence of the RSF, TSF, RF, and TF bits. and therefore RSF and TSF occur at different times. Figure 16. K2-to-U Mapping

the activate/deactivate state machine. activation/deactivation state machine. dation occurs on both entry and exit from the condition. coefficients, and cease transmission. ldea = 0 is received instead of detecting loss of signal. ceiver from the K2 input (DI) to the K2 output (DO). back test, istp = 1 and xpcy may be either 0 or 1. Table 18. DC Octet Description (Control) Table 19. DS Octet Description (Status) frames. Continues to corrupt until the condition goes away. istp Initiate Start-up N Sample for three consecutive K2 frames to validate. ldea Local Deactivate Y Sample for three consecutive K2 frames to validate. xpcy Transparency Y Sample for three consecutive K2 frames to validate. afrst Reset Y Sample for three consecutive K2 frames to validate. lpbk Loopback Y Sample for three consecutive K2 frames to validate. nebe Near-end Block Error Presented to K2 interface on frame K95 to K94. xact Transceiver Active Presented to K2 interface as it occurs. oof Out of Sync Presented to K2 interface as it occurs.

and can be used to deactivate a nonlocal link without deactivating the local link. Table 20 shows the effects of the adea and ldea bits at the LT. Table 20. adea, ldea, and dea Function 0 0 dea = 0 is sent downstream, but no local deactivation occurs. frozen, and transmission ceases. 1 0 dea = 1 is sent downstream (normal operation).

Lucent Technologies Inc. 27 Data Sheet April 1998 T7264 U-Interface 2B1Q Transceiver K2 Functional Description (continued) The nebe, febe, rfebe, and ccrc Bits Errors in the received 12-bit crc from the U-interface are indicated via the nebe (near-end block error) bit. The nebe bit is a local status bit that is set to 0 each time a crc error is detected. Errors in transmitted crc can be forced by setting the ccrc (corrupt crc) bit low. Because the crc error detection and corruption is handled via the nebe and ccrc bits, there is no need to have direct control or access to the 12 crc bits via the K2 interface. Normally, the T7264 automatically reflects the nebe bit back to the far end as the ANSI-defined febe (far-end block error) bit. The MODE1 pin (pin 11) and rfebe bit can be used to alter the interaction between nebe and febe as shown in Figure 19. Normally, MODE1 and rfebe are HIGH, so febe is the direct result of the current state of nebe. Now rfebe can be directly used to control the state of febe. The intended application for rfebe and MODE1 is one having multiple U links as shown in T1.601-1992, Figure E1. In this application, a performance monitoring approach called path performance monitoring can be used. This treats all links between the NT and LT as one complete link, or path. Thus, any febes or nebes that occur at an intermediate element should be propagated to an endpoint. In this way, the febe and nebe counts at the endpoints represent the performance of the system as a whole. Figure 20 shows how a multilink system with one inter- mediate element (IE) could use MODE1, rfebe, nebe, febe, and ccrc to propagate crc errors to the endpoints. For simplicity, this figure represents only one direction of propagation of nebe and febe, namely nebes propa- gated toward the LT and febes propagated toward the NT. This circuitry would be duplicated in the opposite direction to form a complete system. At the endpoints, MODE1 = 1 and rfebe = 1, so nebe and febe behave normally. At IE, MODE1 = 0 so that rfebe, rather than nebe, controls the state of febe toward the far end. For clarity, the effect of MODE1 is shown as a coil control for an SPDT relay that selects either nebe or V CC as the upper input to the AND gate. First, consider the case of a nebe occurring at the IE's LT -mode T7264. This means that a crc error occurred from NT to IE. The IE's K2 interface logic connects nebe directly to the ccrc bit of the NT -mode T7264 to force a ccrc error toward the LT. This will now show up as a nebe at the LT, effectively propagating nebe from IE to LT. Now, at the LT, the nebe is reflected back toward the IE as a febe. At the IE, the K2 interface logic connects febe directly to the rfebe bit of the LT-mode T7264. This generates a febe from IE to NT, completing the path for the original crc error. Thus, the result of an error from NT to IE is a nebe reported at the LT and a febe report- ed at the NT. This illustrates how the two links and the IE are treated as a single entity from a performance monitoring standpoint.

ply for the eoc message. In this situation, the K2 interface signals are configured as shown in Table 22. Table 22. Minimal Implementation

3030 Lucent Technologies Inc. Data Sheet April 1998T7264 U-Interface 2B1Q Transceiver Activation and the K2 Interface The signal definitions and start-up states (Table 23 and Figure 21) of the U-interface during activation are as re- quired by T1.601. The T7264 handles these details au- tomatically upon assertion of istp on the K2 interface or detection of a tone on the U-interface. Still, for some us- ers it is useful to know what is happening at the K2 in- terface during the start-up sequence and how the system should be reacting. The following is an explana- tion of what happens during a typical start-up sequence. For simplification, it is assumed that the uoa and sai bits, defined in T1.601-1992, are held at 1 during start- up. 1. From RESET to T6 At each end, xact changes from 0 to 1 to indicate that an activation request has been issued at the near end (via istp) or a wake-up tone has been detected from the far end and the transceiver is beginning the start-up se- quence. All other K2 bits are held in their reset state by the transceiver in the U-to-K2 direction at both the NT and the LT (see Table 15 for these RESET values). In the K2-to-U direction, the 2B+D and U overhead bits are internally overwritten by the transceivers. These bits should be initialized by the system to reflect their de- sired state at the time transparency is achieved. Table 23 lists the values of the overwritten U bits at various stages of activation. 2. At T6 At the NT, oof goes high causing 2B+D transparency from the U to the K2 interface at the NT transceiver. Note that the NT always frames up before the LT, due to the structure of the transceiver start-up algorithms. Before T6, the NT transceiver was forcing 2B+D data on the K2 interface to all 1s. After this, the 2B+D bits on the K2 interface contain whatever is being received at the NT's U-interface on the 2B+D channels from T4 until transparency is established (see Table 23 and Figure 21, signal SL2). M bits in the downstream direction become transparent over the entire link. Prior to this, the NT transceiver was forcing all M bits to 1 in the downstream (U-to-K2) direc- tion, except act, which was being forced to 0. In the downstream direction (K2-to-U) at the LT, M bits are al- ready being passed transparently and have been since T4. At T6, oof = 1 at the NT causes the NT to start pass- ing M bits transparently in the downstream direction. M bits in the upstream direction become transparent at the NT transceiver (K2-to-U). Prior to this, the NT trans- ceiver was internally overwriting the upstream M bits to all 1s per the ANSI standard (see Table 23 and Figure 21, signal SN2). After detecting oof = 1, the NT can set its act = 1, then wait for act = 1 from the LT. The NT is still forcing 2B+D in the upstream direction to all 1s and continues to do so until: a) It receives act = 1 from the LT b) It receives an eoc loopback message from the LT When either of the above occurs, the NT must set xpcy = 0, which enables 2B+D transparency in the up- stream direction. 3. At T7 At the LT, oof goes high causing 2B+D transparency from the U to the K2 interface at the LT transceiver. Be- fore T7, the LT transceiver was forcing 2B+D data on the K2 interface to all 1s. After this, the 2B+D bits on the K2 interface contain whatever is being received at the LT's U-interface on the 2B+D channels. This is all 1s ini- tially, because the NT transceiver at the far end is forc- ing transmission of all 1s on the U-interface 2B+D channels from T1 until the transparency is established (see Table 23 and Figure 21, signal SN1—SN3). M bits in the upstream direction become transparent over the entire link. Prior to this, the LT transceiver was forcing all the M bits to 1 in the upstream (U-to-K2) di- rection, except act, which was being forced to 0. In the upstream (K2-to-U) direction at the NT, M bits are al- ready being passed transparently and have been since T6. At T7, oof = 1 at the LT causes the LT to start pass- ing M bits transparently in the U-to-K2 direction and, thus, affects full M-bit transparency in the upstream di- rection. Since the LT is receiving M4 bits from the NT, it can de- tect when the NT has changed its act bit from 0 to 1. Af- ter getting act = 1 three consecutive times from the NT, the LT may set its xpcy = 0 and act = 1, resulting in 2B+D transparency in the downstream direction over the entire link. Prior to this, the LT transceiver was inter- nally overwriting the downstream 2B+D data to all 0s per T1.601.

has no TE controlling it, the NT can never send act = 1. T1.601. The link is now fully operational. Table 23. Definitions of Signals During Start-Up

• Tones have alternating pattern of four +3s, followed by four –3s, and no SW.

† See Figure 21 for start and/or stop time of this signal. ‡ Signals SN3 and SL3 continue indefinitely (or until deactivation). TN, TL — Tones produced by NT or LT, respectively. SNx, SLx — Pulse patterns produced by NT or LT, respectively. Tx — Notation refers to transition instants defined in Figure 21. Absent — Under superframe, this notation means that only SW is transmitted, not ISW. bits, and indicator bits are transmitted). achieved at both ends of the DSL).

32 Lucent Technologies Inc. Data Sheet April 1998T7264 U-Interface 2B1Q Transceiver Activation and the K2 Interface (continued) 5-5180 Notes: T0 Reset state. T1 Network and NT are awake. T2 NT discontinues transmission, indicating that the NT is ready to receive signal. T3 Network responds to termination of signal and begins transmitting signal toward the NT. T4 Network begins transmitting SL2 toward the NT, indicating that the network is ready to receive SN2. T5 NT begins transmitting SN2 toward the network, indicating that NT has acquired SW frame and detected SL2. T6 NT has acquired superframe marker, and is fully operational. T7 Network has acquired superframe marker, and is fully operational. Figure 21. State Sequence for DSL Transceiver Start-Up

Applications

The T7264 is intended for use in both switch and customer premises equipment including a central office (CO), a private branch exchange (PBX), a 2-wire to 4-wire converter (NT1), and terminal equipment (TE). The physical ter- mination of the U-interface at the network end is referred to as the line termination (LT); the physical termination at the user end is referred to as the network termination (NT). Figure 22 shows a loop configuration using several U- interface devices at various locations. The T7264 provides system access to the U loop through the K2 interface. The K2 interface is a TDM serial interface which provides access to 2B+D data, U-interface maintenance, and T7264 device control/status. Figure 23 shows a 2-wire terminal application with the T7264 providing the U-interface. The T7270 provides the microprocessor with access to the individual octets of the K2 data stream. The B1 and B2 data could be transferred to either a codec for voice communications, such as the T7513A, or to an HDLC controller for data communications, such as the T7121. Another T7121 could provide microprocessor access to D-channel HDLC processing. The microprocessor would control initialization, activation/deactivation, D-channel processing, and maintenance func- tions. AB C D A + C £ 5 s FOR COLD START A + C £ 150 ms FOR WARM START B + D £ 10 s FOR COLD START B + D £ 150 ms FOR WARM START 4 ms £480 ms T0 T1 T5 TN SN1 (OP- TIONAL) FRAMES NT NETWORK NTNETWORK SL1 (OPTIONAL) SL2 SL3 SN2 SN3 TL

2 FRAMES

provide two analog lines. The T7270 forms the interface between the microprocessor, the K2 bus, and the codecs. feeds provide the analog interface to the telephones. Figure 22. Loop Application Figure 23. 2-Wire Terminal Application Figure 24. Digital Pair Gain Application

10.24 MHz

2.048 MHz

34 Lucent Technologies Inc. Data Sheet April 1998T7264 U-Interface 2B1Q Transceiver Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Handling Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM) and charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for the CDM. However, a standard HBM (resistance = 1500 W , capacitance = 100 pF) is widely used and, therefore, can be used for comparison. The HBM ESD threshold presented here was obtained by using these cir- cuit parameters: Recommended Operating Conditions * To meet ANSI T1.601 free-run line rate requirement, NT tolerance is 100 ppm. † x = tolerance of MTC. Parameter Min Typ Max Unit Storage Temperature –55 — 125 °C Lead Temp (soldering or bonding) — — 300 °C Any Pin to GND –0.5 — 6.5 V Power Dissipation (package limit) — — 700 mW ESD Threshold Voltage Device Voltage T7264-ML >500 Parameter Symbol Test Conditions Min Typ Max Unit Ambient Temp TA VDD = 5 V – 5% –40 — 85 °C Any VDD VDD — 4.75 5.0 5.25 V GND to GND VGG — –10 — 10 mV Voltage Ref Capacitor CVR — 0.08 0.1 0.2 mF Master Clock Frequency MCLK — — 15.36 — MHz Master Clock Tolerance MCLK NT Mode LT Mode –225* –225 + x*† 225* 225 – x*† ppm ppm Master Clock Duty Cycle MCLK — 47† — 53 %

April 1998 T7264 U-Interface 2B1Q Transceiver Lucent Technologies Inc. 35

Electrical Characteristics

All characteristics are for a 15.36 MHz crystal, 135 W line load, random 2B+D data, VDD = 5 V – 0.25 V, –40 °C to +85 °C, output capacitance = 50 pF. Table 24. Power Consumption Table 25. Performance Ratings Table 26. Crystal Characteristics: Fundamental Mode Crystal These are the characteristics of a crystal for meeting the –100 ppm requirements of T1.601 for NT operation. change in proportion with any change in Cm . able where TOL = –85 ppm and Cm = 18 fF –20%.

Table 27. Internal PLL Characteristics

• Set by digital PLL; therefore, variations track MTC (LT mode) or U-interface line rate (NT mode).

Table 28. Digital dc Characteristics (Over Operating Ranges) 1992 when the transceiver is used with the proper peripheral circuitry. to the proper transformer and interface circuitry.

April 1998 T7264 U-Interface 2B1Q Transceiver Lucent Technologies Inc. 39 Outline Diagram Dimensions are in millimeters. 5-2506 Notes: Meets all JEDEC standards. Pin 1 index mark may be a dimple or numeric located in zones indicated.

Ordering Information

Code Package Temperature Comcode T7264A- -ML-D 44-pin PLCC –40 °C to +85 °C 107890170 T7264A- -ML-DT 44-pin PLCC –40 °C to +85 °C 107997124 4.57 MAX 1.27 TYP 0.53 MAX 0.10 SEATING PLANE

0.51 MIN

PIN #1 IDENTIFIER ZONE

16.66 MAX

17.65 MAX

16.66 MAX 17.65 MAX

4040 Lucent Technologies Inc. Data Sheet April 1998T7264 U-Interface 2B1Q Transceiver Appendix A. Questions and Answers Introduction The questions and answers are divided into three cate- gories: U-interface, K2 interface, and miscellaneous. For detailed application information, also refer to the application notes Implementation of an ANSI Standard ISDN NT1 Using the Lucent T7262A/63, T7252A, T7270, and an 8-Bit Microcontroller and Performance Factors in Line-Powered 2B1Q Applications. U-Interface Q1 : Is the line interface for the T7264 the same as the T7262A/63? A1 : The interface is different in that the T7262A/63 uses a Lucent 2754G transformer (2.5:1 turns ratio), and the T7264 uses a Lucent 2754H trans- former (1.5:1 turns ratio). Other changes to the line interface include device-side resistors of 16.9 W – 1% and line-side resistors of 16.9 W – 7%. Part of the line-side resistance will likely be a PTC in those applica- tions requiring power cross protection. The T7264 device-side protection is unchanged (521A diodes), and the dc blocking capacitor is unchanged (Illinois Capacitor* 1.0 mF – 5%). Line-side protection must be tailored to individual system needs. Q2 : Why is a higher transformer magnetizing inductance used (as compared to other vendors)? A2 : It has been determined that a higher inductance provides better linearity. Furthermore, it has been found that a higher inductance at the far end pro- vides better receiver performance at the near end and better probability of start-up at long loop lengths. Q3 : Can the T7264 be used with a transformer that has a magnetizing inductance of 20 mH? A3 : The echo canceler and tail canceler are optimized for a transformer inductance of approx- imately 80 mH and will not work with a value this low. Q4 : Are the Lucent U-interface transformers available as surface-mount components? A4 : Not at this time. Q5 : Are there any future plans to make a smaller height 2-wire transformer? A5 : Due to the rigid design specifications for the transformer, vendors have found it difficult to make the transformer any smaller. We are con- tinuing to work with transformer vendors to see if we can come up with a smaller solution. Q6 : The line interface components’ specifications require 16.9 W resistors on the line side of the transformer. We would like to change this value for our application. Can the U-interface line-side circuit be redesigned to change the value of the line-side resistors? A6 : Y es. For example, the line-side resistances can be reflected back to the device side of the trans- former so that, instead of having 16.9 W on each side of the transformer, there are no resistors on the line side of the transformer and 24.4 W resis- tors on the device side (16.9 + 16.9/N 2, where N is the turns ratio of the transformer). However, there may be some performance penalty in this case since the on-chip hybrid network is opti- mized for 16.9 W of resistance on the device side of the transformer. * Illinois Capacitor is a registered trademark of Illinois Capacitor Inc.

Lucent Technologies Inc. 41 Data Sheet April 1998 T7264 U-Interface 2B1Q Transceiver Appendix A. Questions and Answers (continued) Q7 : Why are the line-side resistors (16.9 W ) rated at 7% tolerance in Figure 4 of the data sheet? A7 : This tolerance was determined based on analysis of the output voltage tolerance of the T7262A/63 solution as compared to the T7264 solution, taking into account the tolerances of the transformer, resistors, etc. It is not a standard resistor tolerance, such as 5%, because as much flexibility as possible was desired. The 16.9 W resistor is often a combination of a resistor and a positive temperature coefficient (PTC) surge- protection resistor, and PTCs generally have wider tolerances. Some 2B1Q manufacturers try to match the PTCs in such a way that their variations from the nominal value are in the same direction. How- ever, it is important to use as tight a tolerance as possible for the following reasons: n The 16.9 W resistor is also part of the termina- tion impedance looking into Tip/Ring. ANSI specifies this impedance at 135 W nominal, and the impedance template over the specified frequencies is derived from the return loss requirement (T1.601, Sections 7.1, 7.2, and Figure 19). A tighter tolerance on the 16.9 W resistors allows more margin on the return loss template. n If resistors are unmatched, longitudinal balance (described in T1.601, Section 7.3) may be affected. Designers can experimentally deter- mine the maximum tolerance allowed in their system by varying the 16.9 W resistors slightly and observing the effect on the parameters mentioned above. Q8 : The dc blocking capacitor specified is 1 mF . Can it be increased to at least 2 mF? A8 : Y es. This value can be increased without any det- rimental effect. Q9 : The application diagram in the data sheet shows the loopback relay on the line side of the trans- former. Why is it not shown on the device side? A9 : The relay can be located on the device side between the 521A surge protector and the trans- former, and the local loopback will function prop- erly. It is shown on the line side because in many applications the relay is a DPDT type and is also used for metallic access to some line testing equipment (at an LT, for example). Q10 : If the relay is on the line side, what type should it be? A10 : Relay type is application-dependent. An example of a relay which would work in most cases is an Aromat* DS Series 2 A relay. Q11 : Clarify the meaning of the note concerning the 3000 pF capacitors in the U-line interface figure (Figure 4). A11 : The capacitors are not absolutely required. The ANSI T1.601 specification contains no require- ments on longitudinal noise immunity. Therefore, these capacitors are not required in order to meet the specification. However, there are guidelines in IEC 801-6 which suggest a noise immunity of up to 10 Vrms between 150 kHz and 250 MHz. At these levels, the 10 kHz tone detector in the T7264 may be desensitized such that tone detec- tion is not guaranteed on long loops. The 3000 pF was selected to provide attenuation of this common-mode noise so that tone detector sensitivity is not adversely affected. Since the 3000 pF capacitor was selected based only on guidelines, it is not mandatory, but it is recom- mended in applications which may be susceptible to high levels of common-mode noise. The final decision depends on the specific application. * Aromat is a registered trademark of Aromat Corporation.

4242 Lucent Technologies Inc. Data Sheet April 1998T7264 U-Interface 2B1Q Transceiver Appendix A. Questions and Answers (continued) Q12 : Why must secondary protection, such as the 521A protection diode, be used? A12 : The purpose of the 521A is to protect against metallic surges below the breakdown level of the primary protector. Such metallic surges will be coupled through the transformer and could cause device damage if the currents are high. The 521A does not provide absolute protection for the device, but rather works in conjunction with the built-in protection on the device leads. The breakdown voltage level for secondary pro- tection devices must be chosen to be above the normal working voltage of the signal and typically below the breakdown voltage level of the next stage of protection. The 521A has a minimum breakdown voltage level of 6.95 V and a maxi- mum breakdown voltage of 8.0 V. The chip pins which the 521A protects are pins 36 (HP), 31 (HN), 32 (LOP), and 35 (LON). The 16.9 W resistors will help to protect pins 32 and 35, but pins 31 and 36 will be directly exposed to the voltage across the 521A. The on- chip protection on these pins consists of output diodes and a pair of polysilicon resistors. These pins have been thoroughly tested to ensure that an 8 V level will not damage them; therefore, no third level of protection is needed between the 521A and the HP and HN pins. The 521A has a maximum reverse surge voltage level of 10 V at 50 A. Sustained currents this large are not a concern in this application, since it is assumed that some form of primary protection is being used, such as the Teccor* P2103AA SIDACtor *. Thus, there should never be more than 8.0 V across the 521A, except for possibly an ESD or lightning hit. In these cases, the T7264 is able to withstand at least –500 V (human-body model) on its pins. Another consideration is the capacitive loading that the protection device presents to the target device. This is generally required to be negligible at the operating frequency. From a practical point of view, the device is chosen to meet not only voltage, current, and capacitance requirements, but also to meet price, availability, manufacturing, and second- sourcing requirements. The 521A device is a general-purpose device that meets system requirements for voltage, current, capacitance, price, etc., for some of Lucent’s customers. Other devices which may be acceptable alternates are as follows: Motorola † SA6.0C (through-hole and surface-mount), Microsemi SMSJ6.0C-SMB (sur- face-mount), and SGS-Thomson ‡ SM6T6V8C (surface-mount). Q13 : Bellcore TR-TSY -000078, Section 3.2.4.1, prohib- its using silver metallization, but the 521A protec- tion diodes have silver-plated leads. Does this indicate an incompatibility problem? A13 : Bellcore TR-TSY -000078, Section 3.2.4.1 prohib- its silver “. . . when electromigration is a problem.” The 521A diodes are only used as secondary protection, and, therefore, almost never carry any current. Electromigration occurs only when there is a high current flow for an extended period of time. Since the diodes are never subjected to this condition, electromigration is not a problem, and the silver plating is acceptable. Q14 : Where can information be obtained on lightning and surge protection requirements for 2B1Q products? A14 : ANSI T1.601, Appendix B, provides a list of applicable specifications to which you may refer. Also, there are many manufacturers of overvolt- age protection devices who are familiar with the specifications and would be willing to assist in surge protection design. The ITU-T K series recommendations are also a good source of information on protection, especially Recommen- dation K.11, “Principles of Protection Against Overvoltages and Overcurrents,” which presents an overview of protection principles. * Teccor and SIDACtor are trademarks of Teccor, Inc. † Motorola is a registered trademark of Motorola, Inc. ‡ SGS-Thomson is a registered trademark of SGS-Thomson Microelectronics, Inc.

Lucent Technologies Inc. 43 Data Sheet April 1998 T7264 U-Interface 2B1Q Transceiver Appendix A. Questions and Answers (continued) Q15 : ITU-T specification K.21 describes a lightning surge test for NT1s (see Figure 1/K.21 and Table 1/K.21, Test #1) in which both Tip and Ring are connected to the source and a 1.5 kV voltage surge is applied between this point and the GND of the NT1. What are the protection consid- erations for this test? Are the HP and HN pins susceptible to damage? A15 : The critical component in this test is the trans- former since its breakdown voltage must be greater than 1.5 kV. Assuming this is the case, the only voltage that will make it through to the secondary side of the transformer will be prima- rily due to the interwinding capacitance of the transformer coils. This capacitance will look like an impedance to the common-mode surge and will therefore limit current on the device side of the transformer. The device-side voltage will be clamped by the 521A device. The maximum breakdown voltage of the 521A is 8 V. The 16.9 W resistors will help protect the LOP and LON pins on the T7264 from this voltage. However, this voltage will be seen directly on pins 36 and 31 (HP and HN) on the T7264. The on-chip protection on these pins con- sists of output diodes and a pair of polysilicon resistors. These pins have been thoroughly tested to ensure that an 8 V level will not damage them; therefore, no third level of protection is needed between the 521A and the HP and HN pins. Q16 : How is it possible to guarantee the –0.35 dB power spectrum tolerance on the U-interface? A16 : By trimming to –0.1 dB; the rest of the variation is for power supply, temperature, and aging. Q17 : Is the –100 ppm free-run frequency (NT mode) recommendation met in the T7264? A17 : In the free-run mode, the output frequency is primarily dependent upon the crystal, not the sili- con design. For low-cost crystals, initial toler- ance, temperature, and aging effects may account for two-thirds of this budget, and just a couple of pF of variation in load capacitance will use up the rest. Thus, the –100 ppm goal can be met if the crystal parameters are well controlled. See the Crystal Characteristics information in the data sheet (Table 26). Q18 : It has been noted in some other designs that the crystal has a capacitor from each pin to ground. Changing these capacitances allows the fre- quency to be adjusted to compensate for board parasitics. Can this be done with the T7264 crys- tal? Also, can we use a crystal from our own manufacturer? A18 : The crystal for the T7264 is tuned to a particular load capacitance that does not include external capacitors. The advantage to this is that no exter- nal components are required. The disadvantage is that board parasitics must be very small. The data sheet notes that the board parasitics must be within the range of 0.6 pF – 0.4 pF . Lucent does not require that a particular crystal be used, but we strongly recommend adhering to the crys- tal parameters specified in the data sheet. A crystal which deviates from these parameters can work under most conditions, but we cannot guarantee that it will start up and/or meet the –100 ppm requirement under all operating condi- tions. Q19 : Is there a test pin available for generating a +3/–3 sequence so that pulse templates can be measured easily? A19 : There is no such pin. But a sequence of four +3s, followed by four –3s (and so on) is the 10 kHz wakeup tone (TN, TL in ANSI T1.601, Figure 17) that each transceiver outputs when initiating a start-up. This tone is produced when the K2 bit, istp in the dc octet, is asserted. At the NT, this tone lasts for 9 ms (90 pulses), and at the LT, it lasts for 3 ms (30 pulses). This should be long enough to capture the data on a digitizer or stor- age scope for analysis. Q20 : What are the average cold start and warm start times? A20 : Lab measurements have shown the average cold start time to be about 3.3 s—4.2 s over all loop lengths, and the average warm start time to be around 125 ms—190 ms over all loop lengths. Q21 : What is the U-interface’s response time to an incoming wakeup tone from the LT? A21 : Response time is about 1 ms. Q22 : What is the minimum time for a U-interface reframe after a momentary (<480 ms) loss of synchronization? A22 : Five superframes (60 ms).

4444 Lucent Technologies Inc. Data Sheet April 1998T7264 U-Interface 2B1Q Transceiver Appendix A. Questions and Answers (continued) Q23 : Can the range of the T7264 on the U-interface be specified in terms of loss? What is the range for over straight 24 AWG wire? A23 : ANSI Standard T1.601, Section 5.1, states that transceivers meeting the U-interface standard are intended to operate over cables up to the limits of 18 kft (5.5 km) 1300 W resistance design. Resis- tance design rules specify that a loop (of single- or mixed-gauge cable; e.g., 22 AWG, 24 AWG, and 26 AWG) should have a maximum dc resis- tance of 1300 W , a maximum working length of 18 kft, and a maximum total bridged tap length of 6 kft. The standard states that, in terms of loss, this is equivalent to a maximum insertion loss of 42 dB @ 40 kHz. Lucent has found that, for assessing the condition of actual loops in the field in a 2B1Q system, specifying insertion loss as 33.4 dB @ 20 kHz more closely models ANSI circuit operation. This is equivalent to a straight

26 AWG cable with 1300 W dc resistance

(~15.6 kft). The above goals are for actual loops in the out- side loop plant. These loops may be subjected to noise and jitter. In addition, as mentioned above, there may be bridge taps at various points on the loop. The T1.601 standard defines 15 loops, plus the null, or 0 length loop, which are intended to represent a generic cross section of the actual loop plant. A 2B1Q system must perform over all these loops in the presence of impairments with an error rate of <1e–7. Loop #1 (18 kft, where 16.5 kft is 26 AWG cable and 1.5 kft is 24 AWG cable) is the longest, and so has the most loss (37.6 dB @ 20 kHz and 47.5 dB @ 40 kHz). Note that this is more loss than discussed in the preceding para- graph. The difference is based on test require- ments vs. field deployment. The test requirements are somewhat more stringent than the field goal in order to provide some margin against severe impairments, complex bridged taps, etc. If a transceiver can operate over Loop #1 error- free, it should have adequate range to meet all the other loops specified in T1.601. Loop #1 has no bridged taps, so passing Loop #1 does not guarantee that a transceiver will successfully start up on every loop. Also, due to the complex nature of 2B1Q transceiver start-up algorithms, there may be shorter loops which could cause start-up problems if the transceiver algorithm is not robust. The T7264 has been tested on all of the ANSI loops per the T1.601 standard and passes them all successfully. Two loops com- monly used in the lab to evaluate the perfor- mance of the T7264 silicon are as follows: The T7264 is able to start up and operate error- free on both of these loops. Neither of these loops is specified in the ANSI standard, but both are useful for evaluation purposes. The first loop is used because it is simple to construct and easy to emulate using a lumped parameter cable model, and it is very similar to ANSI Loop #1, but slightly worse. Thus, if a transceiver can start up on this loop and operate error-free, its range will be adequate to meet the longest ANSI loop. The second loop is used because, due to its diffi- cult bridge tap structure and its length, it stresses the transceiver start-up algorithms more than any of the ANSI-defined loops. Thus, if a transceiver can start up on this loop, it should be able to meet any of the ANSI-defined loops which have bridge taps. Also, on a straight 26 AWG loop, the T7264 can successfully start up at lengths up to 21 kft. This fact, combined with reliable start-up on the 15 kft 2BT loop above, illustrates that the T7264 provides ample start-up sensitivity, loop range, and robustness on all ANSI loops. Another parameter of interest is pulse height loss (PHL). PHL can be defined as the loss in dB of the peak of a 2B1Q pulse relative to a 0 length loop. For an 18 kft 26 AWG loop, the PHL is about 36 dB, which is 2 dB worse than on ANSI Loop #1. A signal-to-noise ratio (SNR) measure- ment can be performed on the received signal after all the signal processing is complete (i.e., at the input to the slicer in the decision feedback equalizer). This is a measure of the ratio of the recovered 2B1Q pulse height vs. the noise remaining on the signal. The SNR must be greater than 22 dB in order to operate with a bit error rate of <1e–7. Loop Config- uration Bridge Taps (BT) Loss @ 20 kHz (dB) Loss @ 40 kHz (dB) 18 kft

26 AWG

None 38.7 49.5 15 kft 2 at near end, each 3 kft,

22 AWG

37.1 46.5

Lucent Technologies Inc. 45 Data Sheet April 1998 T7264 U-Interface 2B1Q Transceiver Appendix A. Questions and Answers (continued) A23: (continued) With no impairments, the T7264 SNR is typically 32 dB on the 18 kft 26 AWG loop. When all ANSI- specified impairments are added, the SNR is about 22.7 dB, still leaving adequate margin to guarantee error-free operation over all ANSI loops. Finally, to estimate range over straight 24 AWG cable, the 18 kft loop loss can be used as a limit (since the T7264 can operate successfully with that amount of loss), and the following calcula- tions can be made: = 24 kft Therefore, the operating range over 24 AWG cable is expected to be about 24 kft. Q24 : What cable simulator is used for evaluating the T7264? A24 : The original version of the transceiver was tested using real cable for ANSI loop performance mea- surements. However, currently, the Lucent Tech- nologies Microelectronics Group laboratory uses the TAS2200A* Cable Emulator for evaluation purposes. Q25 : The data sheet states that the T7264 meets the ANSI T1.601-1992 standard. Is there detailed evaluation data available on loops 1 and 4? A25 : The results shown in the following table for some typical devices have been obtained in laboratory testing. Loops 1 and 4 are the most difficult cases. Q26 : What does the energy spectrum of a 2B1Q signal look like? A26 : Figure A1 (curve P1) in the ANSI T1.601 standard gives a good idea of what this spectrum looks like. Q27 : Does the return loss measurement described in ANSI T1.601, Section 7, require that the T7264 terminate a metallic cable with 135 W during powerdown? A27 : No. ANSI and ETSI specifications do not require this. They require that the device be placed in an active mode with the transmitter producing 0 V (same as quiet mode) while performing the return loss measurements. The T7264 is placed in this mode by pulling the RESET pin low. Q28 : How is the T7264 set to quiet mode? A28 : The device is placed in the quiet mode by pulling the RESET pin low. In this mode, the transmitter is on, but is producing 0 V. Q29 : Please clarify the meaning of ANSI Standard T1.601, Section 7.4.2, Jitter Requirement #3. A29 : The intent of this requirement is to ensure that after a deactivation and subsequent activation attempt (warm start), the phase of the receive and transmit signals at the NT will be within the specified limits relative to what they were prior to deactivation. This is needed so that the LT, upon a warm-start attempt, can make an accurate assumption about the phase of the incoming NT signal with respect to its transmit signal. Note that the T7264 meets this requirement by design because the NT phase offset from transmit to receive is always fixed. Q30 : How can proprietary messages be passed across the U-interface? A30 : The embedded operations channel (eoc) provides one way of doing this. ANSI defines 64 8-bit messages which can be used for non- standard applications. They range in value from binary 00010000 to 01000000. There is also a provision for sending bulk data over the eoc. Setting the data/message indicator bit to 0 indicates the current 8-bit eoc word con- tains data that is to be passed transparently with- out being acted on. Note that there is no response time requirement placed on the NT in this case (i.e., the NT does not have to echo the message back to the LT). Also note that as of 1993 this is only an ANSI provision and is not an ANSI requirement. The T7264 does support this provision. * TAS2200A is a trademark of Telecom Analysis Systems Incorpo- rated. Loss of 18 kft 26 AWG loop @ 20 kHz 38.7 dB Loss per kft of 24 AWG cable @ 20 kHz 1.6 dB ANSI Loop # Configuration

1992 ANSI

(dB) 1 LT 1.9 4 LT 7.6 38.7 dB

4646 Lucent Technologies Inc. Data Sheet April 1998T7264 U-Interface 2B1Q Transceiver Appendix A. Questions and Answers (continued) K2 Interface Q31 : How are powerdown and warm start performed in the T7264? A31 : The powerdown/warmstart sequence is as fol- lows: n At the LT, the series of events begins with the assertion of ldea = 1. This causes the device to begin the automatic deactivation sequence. As long as the device control bits (istp, lpbk, and afrst) and the R ESE T and ILOSS pins remain inactive during this time, the LT device con- cludes deactivation by entering the powerdown state. From this condition, the loop can be reactivated by using a warm start. n At the NT, the device receives at least three consecutive ldea = 0 bits from the LT during deactivation. These bits must be read from the K2 interface and interpreted to indicate that a deactivation is occurring. Once this condition is detected, the external controller must set ldea = 1 at the NT, causing the device to freeze its signal processor coefficients and power down when a loss of signal from the LT is detected. During this time, the device control bits (istp, Ipbk, afrst, etc.) and the RESET and ILOSS pins must remain inactive at the NT. From this condition, the loop can be reactivated with a warm start. Q32 : Does the device automatically reset and attempt a cold start if out of frame (oof) occurs after a warm start? A32 : When an oof condition occurs, the device enters a reframing algorithm and attempts to regain syn- chronization. During this time, the device is still active. If, after 480 ms, the device has not regained synchronization, it goes into the deac- tive state, from which the next start-up attempt will result in a cold start. This conforms to the state tables shown in Appendix C of ANSI T1.601. Q33 : What is the purpose of the sksi bit in the device control (DC) octet? A33 : Its primary use is to detect a “stuck at one” condi- tion on the K2 interface. It is reflected back onto the K2 interface as rsksi in the DS octet. Setting sksi to 0 will guarantee that at least one bit (rsksi) will be zero on the received K2 interface. Q34 : What should the state of the other bits in the DC octet be during a local U-loopback? A34 : To perform a loopback, the following sequence of bits are set in the DC octet, where 1 resets the device and puts it into a known state, 2 asserts the loopback, and 3 resets the chip again and removes the loopback. The other DC bits should be kept in their inactive state: Q35 : What is the state of the DO bits when OSYNC goes low momentarily after the link is up? A35 : The 2B+D data and U-overhead bits are passed transparently from the U-interface to the K2 interface. Since this U-information is likely to be invalid during this time, the system should recog- nize this and disregard the data and overhead bits during this time. Note that this situation is dif- ferent than when OSYNC is low prior to a start- up. In the latter case, the 2B+D and overhead bits are internally overwritten by the transceiver to default values until synchronization is achieved (see the data sheet for these values). In either case, the DS bits are always valid. Q36 : ANSI requires 0.75 ms to process the eoc mes- sage at the NT before echoing it. The T7264 data sheet, however, states that the time from when an incoming message becomes available and the next message goes out is 1.75 ms. How can the T7264 meet the standard? A36 : The 0.75 ms in the ANSI requirement refers to the delay between the start of the received U frame and the start of the transmitted U frame. In the eoc bit locations, there are SW/ISW plus 12 2B+D blocks of data between the last bit of one eoc message and the first bit of the next one. This provides an additional 1.46 ms of processing time or a total of 2.21 ms. Of course, some of this time is consumed by the T7264 in moving data between the U and K2 interfaces. After these delays are taken into consideration, 1.75 ms remain to process data. 1. afrst = 1, Ipbk = x, istp = 1, xpcy = x [loopback = inactive] 2. afrst = 0, Ipbk = 0, istp = 1, xpcy = x [loopback = active] 3. afrst = 1, Ipbk = 1, istp = 1, xpcy = x [loopback = inactive]

Lucent Technologies Inc. 47 Data Sheet April 1998 T7264 U-Interface 2B1Q Transceiver Appendix A. Questions and Answers (continued) Q37 : What are the requirements on the transmission and reception of eoc data on the K2 interface? A37 : This is described on page 24, Figure 18, of this data sheet. To summarize, the received eoc data changes at K2 frames 47 and 95 (where frame 0 is marked by the rising edge of RSF). The most recent eoc data is continuously available on the K2 bus in the intervals between frames 47 and 95. The eoc data to be transmitted must be present on the K2 interface at outgoing K2 frames 11 and 59 (where frame 0 is marked by the rising edge of TSF). Since it is sampled only at those times, it does not matter what is present in those bit positions in the intervals between frames K11 and K59. For an LT, normally it will not matter in which K2 frames the eoc data is written and read, as long the read/writes are done at 6 ms intervals (i.e., every 48 K2 frames). This is because there is no critical timing involved between the reception of an eoc message and its response, as there is at an NT. For an NT, ANSI T1.601, Section 8.3.2, specifies that the eoc response must occur in the next available outgoing eoc frame. This means that the system has 13 K2 frames between the reception of a new eoc message at frame K95 (relative to RSF) and the transmission of the response to that message. Thus, the eoc timing at the NT should be referenced to RSF . Because of well- defined timing between RSF and TSF at the NT, there is no reason to use TSF for eoc timing. Q38 : The data sheet states that adea = 0 and Idea = 1 should not be used at the same time; why not? A38 : This mode is not recommended because it could result in a system-level problem. Consider a typi- cal deactivation sequence for a network having a remote NT1 (i.e., an LT -to-NT connection with at least one intermediate element, as shown in ANSI T1.601, Figure E1) . The following table shows the events at the NT and LT when the LT initiates a deactivation. The LT uses adea in the case of an intermediate element to propagate the deactivation bit downstream without shutting itself down (as it would do if ldea were set instead): * This stores the coefficients and prepares the transceiver for deactivation. Deactivation will occur on loss of signal from the intermediate element. † Stores the coefficients and deactivates the LT transmitter (stops transmitting). Notice that adea = 0 and ldea = 1 are permitted at the last step. This is because the NT has already stored its coefficients; however, if Idea = 1 were set earlier (for example, in step 2), the LT might deactivate before the downstream elements had stored their coefficients, and a clean deactivation would not occur. Therefore, to help avoid turning off the LT before all the down- stream elements store their coefficients, this state was defined as invalid. Also, note that Idea = 1 will cause a chip set in the LT mode to store coefficients and deactivate, but it only causes a chip set in the NT mode to store coefficients. Deactivation at the NT only occurs upon loss of the U-interface signal. Note: The preceding deactivation procedure is only an illustration. In a nonrepeater envi- ronment, step 2 could be adea = ldea = 1, which would cause the LT to automatically save its coefficients and, within three or four K2 frames, deactivate. This case assumes that the NT has properly detected dea = 0 and then stored its coeffi- cients within those three or four frames. LT State LT K2 Data In NT K2 Data Out NT Action Normal Operation adea = 1 ldea = 0 dea = 1 — Downstream Deactivate adea = 0 ldea = 0 dea = 0 Set Idea = 1 upon third consecutive dea = 0* After an appropriate amount of time to allow the message to propagate and the NT to react. LT Deactivates ldea = 1 adea = 1 x Detects loss of signal and deactivates

4848 Lucent Technologies Inc. Data Sheet April 1998T7264 U-Interface 2B1Q Transceiver Appendix A. Questions and Answers (continued) Q39 : What is the relationship between istp and ldea? A39 : The istp bit should be set to 1 before or at the same time as ldea is set to 1. Once the chip set is deactivated, setting istp to 0 for at least three K2 frames will initiate start-up. However, it is neces- sary for ldea to be 0 before time T7 (see ANSI Table 5, Figure 16) for the start-up process to be successfully completed. Q40 : When should nebes and febes be counted? A40 : During activation, nebes and febes will occur at each end of the link between the time framing is initially achieved and the time the link is fully operational at each end. These nebe/febe occurrences are normal and are of no interest. Therefore, nebe/febe counters should be reset to zero after the link is fully operational. This is most easily achieved by delaying about 500 ms after getting oof = 1 and then resetting the nebe/febe counters. Q41 : How is the D+ channel for 3-DS0 TDM applica- tions generated (Bellcore TR-TSY -000397)? A41 : Since the crc bits are not passed to the K2 inter- face, the D+ channel cannot be formed directly; those bits must be generated externally. Also, a recent standard ballot addressed this issue by noting that, in general, the form of the D+ channel is application-dependent, so a broad standard is not being developed. Q42 : How does RSF behave during a reframe? A42 : RSF behavior is transparent to the oof (out-of- frame) condition. Whenever the chip thinks it has found an ISW, it forces RSF high. RSF stays high for 12 K2 frames, at which point it goes low until the occurrence of the next ISW. Q43 : Does the K2 F clock do anything strange when a RESET is asserted? This clock is being used to initialize an elastic store, and it seems to be pro- ducing some strange glitches. A43 : There are two ways to reset the chip: 1. Assert the RESET pin low. 2. Assert the K2 afrst bit (DC octet) high. The difference between these two resets is that #1 resets the entire chip, including the on-chip PLL, while #2 resets everything except the PLL. Therefore, for both resets, the counter which con- trols the frequency gets loaded to its initial value, but the counter which controls the phase only gets reset when the RESET pin is asserted. In the case described, this means that with either reset #1 or #2, the frequency counter controlling F will be reinitialized, which could cause a strange duty cycle on F for one clock period. But once this initialization occurs, the F clock immedi- ately starts behaving normally, even if the RESET control remains active (also, in the case of reset #1, the PLL starts to acquire). From a system standpoint, you can always count on F behaving predictably when RESET is released because reset #1 or #2 must be asserted for at least 3 K2 frames, and the F clock duty cycle will stabilize after one K2 frame. So any logic for an elastic store which uses F should initialize upon exit from the reset state. However, be sure to consider the effect the shift in F may have on other parts of the system. Q44 : What is the phase relationship between MTC and F at the LT? A44 : F is phase-locked to MTC by a second-order PLL that has a –3 dB frequency of approximately 0.5 Hz and has about 0.4 dB of peaking.

Lucent Technologies Inc. 49 Data Sheet April 1998 T7264 U-Interface 2B1Q Transceiver Appendix A. Questions and Answers (continued) Miscellaneous Q45 : Does the T7264 have a second source? A45 : It is manufactured at multiple Lucent ME loca- tions, but no second source outside Lucent is currently available. Q46 : Are digital I/Os TTL or CMOS compatible? A46 : Both. All I/Os are CMOS. They are specified at TTL because the current requirement makes this more difficult to meet. At higher output voltages, the current will be less, perhaps 100 mA at 3.5 V. Q47 : What is the current sinking capability of OSYNC? A47 : The OSYNC lead supports a standard TTL load and will sink (or source) 1.6 mA. Q48 : What are the tolerances of the various discrete components around the chip set? A48 : Discrete components and their tolerances are as follows: Q49 : If a switching power regulator is used in the system, is there a frequency to which it should be set? A49 : A switching frequency of 80 kHz or higher multiples, synchronous to the 2B1Q band clock, would be optimal. An 80 kHz clock is available at pin 43 that is synchronous with the 2B1Q signals. Q50 : Please explain how to use the FFC pin in detail and its purpose. A50 : The FFC pin can be used in applications where the MTC clock is switched from one source to another and may have glitches during the switch. One example of this is in DLC applications when the system switches to a protection clock board, and a new MTC clock is used. Before the protec- tion switch, FFC should be brought low to freeze the internal states of the timing recovery circuitry. After the new clock has stabilized, FFC can be brought high again and the T7264 circuitry will lock to the new clock without dropping the U- interface. Without the FFC function, the U-inter- face might be dropped while the new clock is being applied. Q51 : What is the meaning of free-running and phase- locked in Table 3 of this data sheet? A51 : In Table 3, CKOUT is defined to be either 3-stated, 15.36 MHz free-running, 7.68 MHz free- running, or 10.24 MHz phase-locked. Free-run- ning means that the CKOUT clock is directly derived from the 15.36 MHz crystal oscillator clock that is not synchronous with the U-interface line rate. Phase-locked means that the

10.24 MHz CKOUT clock is synchronous with the

U-interface line rate. This clock does not have 50% duty cycle, and will experience occasional duty-cycle adjustments (i.e., phase steps) to keep it synchronous with the U-interface. (See the note at the bottom of Table 3 in the data sheet.) Q52 : What are the filter characteristics of the PLL at the NT? A52 : The –3 dB frequency is approximately 5 Hz; peaking is about 1.2 dB. Q53 : Is it possible to get a T7264-based LT to operate properly with a NT without supplying an MTC clock? A53 : Y es. Tying MTC to +5 V will yield a –100 ppm MTC, which a Lucent NT will be able to lock to in most cases. This configuration should be used for laboratory purposes only. For all serious perfor- mance testing, a –32 ppm (or better) MTC should be used. Q54 : If there are several NT -mode T7264s on a board, can only one crystal be used to run them? A54 : Y es. The following is an explanation of how this is accomplished (refer to Table 3 on page 6 of this data sheet). First, connect a crystal in the normal fashion to one T7264; the V DDO , MCLK, and CKSEL pins should be set per the first entry in Table 3 (+5/0/0). Now set the V DDO , MCLK, and CKSEL pins on all the other T7264s as per the last entry in Table 3 (0/15.36/1), and use the

15.36 MHz signal coming from CKOUT (pin 23)

of the first T7264 to provide the 15.36 MHz input to MCLK (pin 24) on the others. Line-Side Resistors 16.9 W – 7% dc Blocking Capacitor 1.0 mF – 5% Device-Side Resistors 16.9 W – 1% Bypass Capacitors 0.1 mF – 10% Bypass Capacitors 1.0 mF – 10%

5050 Lucent Technologies Inc. Data Sheet April 1998T7264 U-Interface 2B1Q Transceiver Appendix A. Questions and Answers (continued) Q55 : Will the T7264 run in NT mode with the K2 clock slaved to an external backplane? A55 : The T7264 does not support this mode. For those applications where this is an issue, systems designers have generally provided some elastic store on the K2-to-backplane ASIC. The elastic store must be sized according to the amount of jitter which can be introduced into a system and the amount of jitter gain in the system APLLs. For example, assume that the backplane clock is derived from a recovered T1 clock. The worst- case jitter for a T1 line is 0.259 UI at frequencies of 0.001 Hz—10 Hz. Considering that an LT - mode T7264 APLL has jitter peaking of 0.4 dB at 0.15 Hz, the 0.259 UI of jitter could be amplified to 0.271 UI. Since 0.271 UI of 80 kHz is 3.39 ms, this is how much elastic store is required. Note that this is a simplified example: there may be other APLLs in the system (for example, the T1-to-backplane clock APLL), and their peaking must be factored in also. In addition, it is desirable to design in some margin. Q56 : Is there a recommended method for powering the T7264? For example, is it desirable to separate the power supplies, etc.? A56 : The T7264 is not extremely sensitive to power supply schemes. Following standard practices of decoupling power supplies close to the chip and, if power and ground planes are not used, keeping power traces away from high-frequency signals, etc., should yield acceptable results. Separating the T7264 analog power supplies from the digital power supplies near the chip can yield a small improvement, and the same holds true for using power and ground planes vs. discrete traces. Note: If analog and digital power supplies are separated, the XTAL power supply (V DDO ) should be tied to the digital supplies DDD ). Q57 : What is the effect of ramping down the power supply voltage on the device? When will it provide a valid reset? This condition can occur when a line-powered NT1’s line cord is repeatedly plugged in and removed and plugged in again before the power supply has had enough time to fully ramp up. A57 : The device’s reset is more dependent on the RESET pin than the power supply to the device. As long as the proper input conditions on the RESET pin (see Table 32) are met, the device will have a valid reset. Note that this input is a Schmitt-trigger input. Q58 : Does the output jitter of the 9 kHz F clock on an NT -mode T7264 meet the 5% peak-to-peak jitter requirement described in ITU-T I.430, Section 8.3, assuming the S/T transceiver is the T7252A? A58 : Y es, the 5% requirement applies to high- frequency jitter (>50 Hz) at the NT. The T7264 produces approximately 100 ns of high-frequency jitter in the NT mode on F , and the T7252A can accept up to 160 ns of high-frequency jitter on its input clock and still meet the I.430 requirement. Q59 : What should be known before having a T7264- based product conformance tested at Bellcore? A59 : A copy of the Bellcore Test Bed Interface Specifi- cation should be obtained from Bellcore to get the latest requirements. The Bellcore specification, when last reviewed by Lucent, required that a unit under test provide access to the following signals or state indicators. (The T7264 pin name in upper case, or K2 bit name, lower case, which corresponds to the Bellcore-required signal, is enclosed in braces.) Transceiver Status Signals: Fully operational state indicator {oof or OSYNC} Full reset state indicator {xact} Loss-of-frame alignment (opt) {oof or OSYNC} RX crc check indicator (opt) {nebe} Transceiver Control Signals: Transceiver full reset { RESET } Transceiver activation {istp} LT transceiver deactivation {ldea} Transmit M1—M4 bit control {K2 access} Transmit 2B+D payload gating {received act} Continuous scrambled output { ILOSS at NT} test mode {Ipbk at LT} Intertransceiver Signals (LT only): Superframe timing {conditioned tsf}

2.56 MHz clock {CKOUT/4}

Note: T7264 must be optioned for a 10.24 MHz CKOUT. 2B+D Test Access 18-bit bursted clock and corresponding 2B+D serial data stream must be accessible in both transmit and receive directions.

Lucent Technologies Inc. 51 Data Sheet April 1998 T7264 U-Interface 2B1Q Transceiver Appendix A. Questions and Answers (continued) Q60 : In the idle mode, when afrst or RESET is active, the current increases from 6 mA (powerdown mode) to 40 mA—50 mA (normal mode). Is this proper behavior for the T7264? Also, is this a cor- rect interpretation of the data sheet description of idle mode (page 10, third paragraph)? A60 : This behavior is proper for the T7264. The reason more current is needed in the reset state (i.e., RESET pin or afrst bit active) is that much of the analog circuitry (line driver, band gap voltage ref- erences, A/D, and D/A) is powered down during the idle state, but is active during the reset state. Notice that idle and reset are two different states: reset state overrides idle when the RESET pin or afrst is active. The reset state is normally a tran- sient state which only lasts a short time, unless the reset function is being constantly asserted. This means that RESET should not be used indis- criminately as part of a general start-up proce- dure. The meaning of the third paragraph on page 10 in the data sheet is that at the end of a RESET condition, the transceiver will change to the idle state (only momentarily if a start-up request is being made via the istp bit or a far-end wakeup tone). In this way, the data sheet is con- sistent with these results. Q61 : Can you provide detailed information on the active power consumption of the T7264? A61 : When discussing active power measurement figures, it is important to note that the conditions under which power measurements are made are not always completely stated by 2B1Q integrated circuit vendors. For example, loop length is not typically mentioned in regard to power dissipa- tion, yet power dissipation on a short loop is noticeably greater than on a long loop. There are two reasons for the increased power dissipation at shorter loop lengths: 1. The overall loop impedance is smaller, requir- ing a higher current to drive the loop. 2. The far-end transceiver is closer, requiring the near-end transceiver to sink more far-end cur- rent in order to maintain virtual ground at its transmitter outputs. The lab measurements in the following table pro- vide examples of how power dissipation varies with loop length for a specific T7264 with its

15.36 MHz CKOUT output enabled and driving

40 pF (see the next table below for information on CKOUT). Note that power dissipation with a zero length loop (the worst-case loop) is about 35 mW higher than a loop of >3 kft length. Thus, loop length needs to be considered when determining worst-case power numbers. * This is the configuration used in Method B discussed on the next page. Also, in the case of the T7264, the use of the out- put clock CKOUT (pin 23) must be considered since its influence on power dissipation is signifi- cant. Some applications may make use of this clock, while others may leave it 3-stated. The power dissipation of CKOUT is as follows: The methods used to evaluate typical and worst- case power consumption are based on Lucent’s commitment to provide its customers with accu- rate and reliable data. Measurements are per- formed as part of the factory test procedure using automated test equipment. Bench top tests are performed in actual ISDN systems to correlate the automated test data with a typical implemen- tation. A conservative margin is then added to the test results for publication in the data sheets. Loop Configuration Power (mW) 18 kft/26 AWG 273 6 kft/26 AWG 273 3 kft/26 AWG 277 2 kft/26 AWG 280 1 kft/26 AWG 288 0.5 kft/26 AWG 296 0 kft 308

135 W load, ILOSS or lpbk

active, no far-end transceiver* 281.5 CKOUT Frequency (MHz) Power Due to CKOUT 40 pF Load (mW) Power Due to CKOUT No Load (mW) 15.36 21.3 11.0 10.24 17.7 9.1 7.68 12.6 6.6

5252 Lucent Technologies Inc. Data Sheet April 1998T7264 U-Interface 2B1Q Transceiver Appendix A. Questions and Answers (continued) A61: (continued) The following tables provide power consumption data in several formats to allow customers to compare transceiver solutions. The three test condition categories reflected in the tables have been designated Method A, which reflects T7264 data sheet measurements; Method B, which reflects data obtained with a method used by other vendors; and Method C, which details revised T7264 measurements. Method A * This is the worst-case loop. † 3 mW should be added for 85 °C. The test conditions reflected in Method B repre- sent a configuration used by other silicon vendors which eliminates the far-end transceiver from the network. This configuration should not be used to determine a system's total power requirements, but it can be used for comparison purposes among silicon solutions. Method B * The transceiver under test must be in a local U-loopback mode. † 3 mW should be added for 85 °C. ‡ Anticipated customer configuration. The conditions and test results in Method C are the product of recent investigations into the device's mature test data. They can be used to reliably determine system-level power consump- tion requirements. Method C * This is the worst-case loop. † 3 mW should be added for 85 °C. ‡ Anticipated customer configuration. Test Condition Value Loop Configuration 0 kft* Temperature 25 °C † Power Supply Voltage 5 V CKOUT 15.36 MHz Max. Power Consumption 350 mW Test Condition Value Loop Configuration 135 W load only* Temperature 25 °C † Power Supply Voltage 5 V CKOUT 3-stated ‡ Max. Power Consumption 275 mW Test Condition Value Loop Configuration 0 kft* Temperature 25 °C † Power Supply Voltage 5 V CKOUT 3-stated ‡ Max. Power Consumption 300 mW

April 1998 T7264 U-Interface 2B1Q Transceiver Lucent Technologies Inc. 53 Appendix B. Differences Between the T-7264- - -ML, T-7264- - -ML2, and T-7264A- -ML Devices Technology The T -7264- - -ML device is a 0.9 mm CMOS technology device, while the T -7264- - -ML2 and the T -7264A- -ML are 0.6 mm CMOS technology devices. Standard In 1996, the European Telecommunications Standards Institute (ETSI) added a microinterruption immunity require- Section 5.4.5 in ETSI ETR 080 states the following: n A microinterruption is a temporary line interruption due to external mechanical activity on the copper wires con- stituting the transmission path. n The effect of a microinterruption on the transmission system can be a failure of the digital transmission link. n The objective of this requirement is that the presence of a microinterruption of specified maximum length shall not deactivate the system, and the system shall activate if it has deactivated due to longer interruption. Section 6.2.5 in ETSI ETR 080 states the following: n A system shall tolerate a microinterruption up to t = 5 ms, when simulated with a repetition interval of t = 5 ms. Since this is a new requirement, implementers were allowed until the end of 1997 to adhere to this requirement. The T7264 device was upgraded to fully comply with this standard and the device was given an A suffix (T7264A). A proposal was added to the Living List (which is intended to collect issues and observations for a possible future update of ETSI ETR 080) to change the value of the microinterruption requirement from 5 ms to 10 ms. The current T7264A device from Lucent Technologies Microelectronics Group meets and exceeds this new requirement. The above change to the transceiver has been fully verified, and test reports are available upon request.

Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Co pyright © 1998 Lucent Technologies Inc. All Rights Reserved April 1998 DS97-413ISDN (Replaces DS90-184SMOS, AY93-032TCOM, and TN93-003TCOM) For additional information, contact your Microelectronics Group Account Manager or the following: INTERNE T: http://www .lucent.com/micro E-MAIL: docmaster@mic ro.lucent.com N . AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagaw a-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EU R OPE: Data Requests: MICR OELECT R ONICS G R OUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148 Technical Inquiries:GERMAN Y: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Bracknell), FRANCE : (33) 1 41 45 77 00 (Paris), SWEDEN: (46) 8 600 7070 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 2 6601 1800 (Milan), SPAIN: (34) 1 807 1441 (Madrid)