Microcontroller

T7121

Agere Systems

The T7121 HDLC Interface for ISDN (HIFI-64) connects serial communications links carrying HDLC bitsynchronous data frames to 8-bit microcomputer systems. There is an optional transparent mo…

Manufacturer: Agere Systems

Document: 68 Pages / 685Kb

Request Quote Download Datasheet Read online HTML view

Read T7121 online.

T7121 AGERE | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 68

Technical content

Features

n Low-cost device for B-channel (64 kbits/s) or D-channel (16 kbits/s) data transport. n Optional transparent mode—no HDLC framing is performed. n Frame sync (FS) allows a slot-select feature to access an individual time slot in any TDM data stream (e.g., Lucent Technologies Microelectronics Group Concentration Highway Interface [CHI] or subset). n Bit-masking option allows effective data rates of 8, 16, 24, 32, 40, 48, and 56 kbits/s. n Maximum data rate up to 4.096 MHz. n Serial data-transfer pins for direct connection to the Lucent ISDN line transceiver T7250C. n Supports IOM2, K2, GCI, and SLD interface. n Parallel microprocessor interface with either multi- plexed or demultiplexed address and data lines for easy interface with any microprocessor. n Single interrupt output signal with seven maskable interrupt conditions. n Programmable interrupt modes. n Memory-mapped read and write registers. n TTL/CMOS compatible input/output. n 3-state output pins to assist system diagnostics. n Low-power 1.25 m m CMOS: — 30 mW typical operation at 12 MHz. — 5 mW standby mode (typical). n HDLC transceiver: — Stand-alone HDLC framing operation. — 64-byte FIFO in both transmit and receive direc- tions. — Supports block-move instruction. — Multiple frames allowed in FIFO. — Programmable FIFO full- and empty-level inter- rupt.

Description

The T7121 HDLC Interface for ISDN (HIFI-64) con- nects serial communications links carrying HDLC bit- synchronous data frames to 8-bit microcomputer sys- tems. There is an optional transparent mode of oper- ation in which no HDLC processing is performed on user data. The device communicates with the system microprocessor as a memory-mapped peripheral and is controlled by reading and writing 19 internal regis- ters. The chip can be instructed to interrupt the microprocessor when it detects certain events requir- ing microprocessor attention. The HDLC transmitter and receiver are each buffered with 64-byte, ﬁrst-in- ﬁrst-out (FIFO) memory storage. The 64-byte buffer depth reduces the number of status polls or inter- rupts to be processed by the microprocessor, improv- ing overall system efﬁciency. The major blocks are the microprocessor interface, transmit and receive FIFO memory buffers, HDLC processor, and a con- centration highway interface (see Figure 1). The T7121 device is available in a 28-pin, plastic DIP or a 28-pin, plastic, small-outline, J-lead (SOJ) package for surface mounting.

2 Lucent Technologies Inc. Data Sheet April 1997T7121 HDLC Interface for ISDN (HIFI-64)

Lucent Technologies Inc. 3 Data Sheet April 1997 T7121 HDLC Interface for ISDN (HIFI-64) (continued) 5-5027 Figure 1. Block Diagram

Figure 2. Pin Diagram Table 1. Pin Assignments

5 V Power

Table 2. Pin Descriptions

1 ALE I

This signal controls when data is written to the registers. AD0 to be read by the microprocessor.

14 INT O

15 RESET I

(3-state) condition on all outputs. All register bits are forced to their reset values. erup. A full chip reset occurs with or without a clock input.

16 FS I

17 DXB/

Transmit Data B or Time-Slot Control for DXA. user-controlled by the P17CTL bit in the receiver control register (R5—B7). terns from propagating through other devices when DXB is 3-stated. (time-slot control for DXA). when data is being transmitted on DXA over long distances. ing the valid bit positions of data and is high at all other times. the P17CTL bit (R5—B7) to 1 overrides the selection of DXBC (R7—B6).

18 CLKX I

19 DXA O

byte on both transmit data pins. isters 7, 9, 10) with bit 0 or bit 7 sent ﬁrst (TLBIT, R10—B6). terns from propagating through other devices when DXA is 3-stated.

20 DRA I

21 CLKR/DRB I

Receive Clock or Receive Data B. P21CTL is cleared to 0 (default), this pin is the receive data clock (CLKR). independent of transmit clock rate.

23 CLK I

(internal pull-up resistors are provided).

88 Lucent Technologies Inc. Data Sheet April 1997T7121 HDLC Interface for ISDN (HIFI-64) Functional Description Microprocessor Bus Interface Addressing The T7121 is designed to easily interface with 8-bit microprocessors. The microprocessor bus interface allows parallel asynchronous access to a bank of 19 registers (R0—R15 and AR11—AR13). The bus inter- face is compatible with most microprocessors. The reg- isters occupy 16 continuous locations in the memory map of a controlling microprocessor, and the registers are accessed under the control of the following signals: address select (A0—A3 or AD0—AD7), address latch enable (ALE), chip select ( CS ), read ( RD ), and write WR ). When multiplexed address and data lines are used, the ALE signal is used to latch the address present on AD0—AD3 and AD6. AD6 has a special use in the block-move mode. See the Block Move sec- tion under the FIFO Memory Buffers section. ALE should be tied high when separate address and data are used. Registers 11, 12, and 13 have alternate meanings depending on the value of the Alternate (ALT) bit in the chip conﬁguration register (R0—B4). The alternate reg- isters are accessed by setting the ALT bit (R0—B4) to 1. All subsequent addressing of registers 11 through 13 then refers to the alternate registers (AR11—AR13). Returning to the foreground register set is accom- plished by clearing the ALT bit (R0—B4) to 0. Interrupts A programmable interrupt output, INT, is provided to alert the microprocessor when the device needs ser- vice. Associated with the interrupt system are the IPOL bit in register 0 (R0—B1), the interrupt mask register (R14), and the interrupt status register (R15). The polarity of the INT signal (pin 14) is programmable by setting the IPOL bit in register 0 (R0—B1). The inter- rupt mask register can be programmed so that only certain conditions cause the INT signal to be asserted. The interrupt status register (R15) reveals the source of the interrupt. Register 14, the interrupt mask register, controls the operation of the INT pin. Masking an interrupt means that no transition of the INT pin is generated for any occurrence of that interrupt condition. The INT signal is enabled upon the ﬁrst occurrence of any unmasked interrupt condition. The INT signal remains until the interrupt is acknowledged by reading the interrupt sta- tus register (R15). Unmasked interrupts occurring between the ﬁrst unmasked interrupt and the status register read do not cause a transition of the INT pin. If a second interrupt occurs during a read of the interrupt status register (R15), the INT signal is disabled after the read and then reasserts itself. This deassertion can actually be much less than one cycle, and no minimum width is guaranteed. One method to ensure that the second interrupt is detected is to use an edge-sensed INT pin on the processor. If this is not available, the interrupt service routine should reread the interrupt sta- tus register to determine if an interrupt occurred during the clearing of the ﬁrst interrupt. Masking all interrupts effectively disables the INT pin. It is possible to mask a currently active interrupt. Doing so causes a transition of the INT pin from active to inactive if the masked interrupt was the only active interrupt. Likewise, unmasking an interrupt that is cur- rently asserted causes an INT pin transition from inac- tive to active if all other unmasked interrupts were currently inactive. Interruptable conditions are always reported in register 15, even if the interrupt pin transi- tion is masked. Thus, polled interrupt systems are also supported. Note that a transition of the INT pin occurs only if the interrupting condition is unmasked and no other unmasked, unacknowledged interrupt exists. The HIFI-64 allows two modes of interrupt: dynamic and nondynamic. The mode is controlled by setting the DINT (Dynamic INTerrupt) bit in register 0 (R0—B0). If DINT (R0—B0) is 0 (nondynamic mode), the interrupt bits in the interrupt status register (R15) are cleared directly by a read of register 15. The condition causing the interrupt must go away and come back in order to reassert the interrupt. If DINT (R0—B0) is set to 1 (dynamic mode), the transmitter empty (R15—B1) and receiver full (R15—B3) interrupts are cleared only when the condition causing the interrupt has been rem- edied (all other interrupts are cleared by reading the interrupt status register [R15]). In addition, the INT sig- nal (pin 14) remains enabled until the condition(s) causing the interrupt has been remedied. A dynamic version of the transmitter empty interrupt, transmitter empty dynamic (TED), is provided in the transmitter status register (R2—B7). TED behaves dynamically regardless of the value of the DINT bit (R0—B0). TED does not cause a transition of the INT pin. In transparent mode, the REOF , RIDL, and UNDABT interrupts are disabled. TDONE is used to indicate a transmitter underrun and can be used to determine transmission end. Additionally, the MSTAT bit (AR11—B3) can be used as a polled interrupt to deter- mine the beginning of receive data. A transition of the INT pin can be programmed for the beginning of receive data by setting the initial receiver-full interrupt level RIL (R5—B[5—0]) to 1 byte.

Lucent Technologies Inc. 9 Data Sheet April 1997 T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Resets The T7121 is fully reset by either asserting the RESET pin (hardware reset) or by asserting both the TRES (R6—B5) and RRES (R6—B4) bits simultaneously when writing to register 6 (software reset). A full reset results in all registers returning to their default condi- tions and all logic returning to a known state. No clock input is necessary. During a hardware reset, all outputs are 3-stated. Thus, the RESET pin can be used for bed-of-nails testing. During a software reset, outputs are not automatically 3-stated. Output pin states are determined by their default register conﬁguration. Both transmit data pins (DXA and DXB) 3-state since the default register conﬁguration is both transmit pins dis- abled. The INT pin is high. In addition, the transmitter and receiver can be individ- ually reset. When TRES (R6—B5) is high and RRES (R6—B4) is low during a write of register 6, the trans- mitter is independently reset. The transmitter FIFO pointers return to default values, resulting in the loss of any untransmitted data, and the transmitter state machine is returned to the idle state. Transmitter inter- rupts are cleared, except for the TE (R15—B1) inter- rupt, which is asserted and causes a transition on the INT pin if unmasked (TEIE, R14—B1 = 1). Only trans- mit status registers and interrupts change to reﬂect the reset. Disabling the transmitter does not cause an automatic reset. When the transmitter has been active and then subsequently disabled, a TRES is needed to restore it to a known state. When TRES (R6—B5) is low and RRES (R6—B4) is high during a write of register 6, the receiver is inde- pendently reset. A receiver reset causes the receiver FIFO pointers to return to their default values, resulting in the loss of unread data in the FIFO. The receiver is returned to a known state, and all currently asserted receiver interrupts are cleared. The receiver should be reset whenever it was active and subsequently dis- abled to ensure correct operation. Only receiver status and interrupt bits are affected in the register set. Dis- abling the receiver does not cause a receiver reset. FIFO Memory Buffers The HIFI-64 is equipped with a transmit FIFO and a receive FIFO, each with a capacity of 64 bytes. Transmit FIFO Data to be transmitted is loaded via the data register (R3) into the 64-byte transmit FIFO. Multiple frames can be placed in the FIFO. In HDLC mode, the ﬁnal byte of each frame is marked by writing the transmit frame complete bit TFC (R1—B7). The transmitter can also be instructed to abort a frame by using the trans- mit abort bit TABT (R1—B6) (HDLC mode only). Trans- mission status is available in the transmit status register and via the transmit interrupts. The transmitter status register (R2) indicates how many additional bytes can be added to the FIFO. The transmitter inter- rupt trigger level (TIL) can be programmed in the trans- mitter control register (R1—B[5—0]) to tailor service time intervals to the system environment. The transmit- ter empty (TE) interrupt bit is set in the interrupt status register (R15—B1) when the FIFO has sufﬁcient empty space to add the number of bytes speciﬁed in the TIL. If the TE interrupt mask TEIE (R14—B1) is 1, the occur- rence of a TE interrupt condition causes a transition of the interrupt pin if no other unmasked interrupts are currently active. In dynamic interrupt mode (DINT, R0—B0 = 1), this interrupt remains set until the condi- tion is cleared. In nondynamic interrupt mode (DINT, R0—B0 = 0), this interrupt is cleared by reading R15. A TDONE (R15—B0) interrupt occurs for each HDLC frame completed. In the transparent mode, a TDONE interrupt occurs when the transmit FIFO emp- ties. In HDLC mode, an UNDABT (R15—B2) interrupt is issued if the transmitter underruns. There is no interrupt indication of a transmitter overrun that is writing more data than empty spaces exist. Overrunning the transmitter causes the last valid data byte written to be repeatedly overwritten, resulting in missing data in the frame.

1010 Lucent Technologies Inc. Data Sheet April 1997T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Receive FIFO Data received from the serial link interface is stored in the 64-byte receive FIFO. In the HDLC mode, the receiver also places a status of frame (SF) status byte in the receiver FIFO for every completed frame received. Whenever an SF frame status byte is present in the receive FIFO, the EOF bit (R4—B7) is set. The receiver queue status (RQS) bits (R4—B[6—0]) report the number of bytes up to and including the ﬁrst SF frame status byte. If no SF frame status byte is present in the FIFO (EOF , R4—B7 = 0), the count directly reﬂects the number of data bytes available to be read. Depending on frame size, it is possible for multiple frames to be present in the FIFO. The receiver ﬁll level indicator (RIL) can be programmed in the receiver con- trol register (R5—B[5—0]) to tailor the service time interval to the system environment. The receiver full (RF) interrupt bit is set in the interrupt status register (R15—B3) when the FIFO reaches the prepro- grammed full position. The RF interrupt condition is reported in the interrupt register (R15—B3). If the RF interrupt mask RFIE (R14—B3) is 1, the occurrence of an RF interrupt condition causes a transition of the interrupt pin if no other unmasked interrupts are present. In dynamic interrupt mode (DINT, R0—B0 = 1), this interrupt remains set until the condi- tion is cleared. In nondynamic interrupt mode (DINT, R0—B0 = 0), this interrupt is cleared by reading R15. In the HDLC mode, an REOF interrupt is issued when the receiver has identiﬁed the end of a frame and writ- ten the SF status byte for that frame. An overrun inter- rupt is generated when the receiver needs to write either status or data to the FIFO and ﬁnds the FIFO full. An overrun condition causes the last byte of the FIFO to be overwritten with an SF status byte indicating the overrun status. In the HDLC mode, an RIDL interrupt is issued whenever 15 or more continuous 1s have been received. Block Move The block-move mode is intended to support micropro- cessors with a memory-to-memory move instruction. Memory-to-memory move instructions can be faster and reduce the amount of code needed to service the FIFOs. Block-move mode allows the T7121 FIFOs to appear as a block of memory. Systems using block move need to allocate 16 addresses to the T7121 reg- ister set (with AD6 = 0) and 64 addresses to the FIFOs (with AD6 = 1). Block move is available only in the MUXed address and data mode by setting the BM bit in register 0 (R0—B3) to 1. When block move is enabled (BM, R0—B3 = 1) and AD6 is held high during the address cycle of the ALE, the address is translated internally to R3, the data byte register. All writes then go directly to the transmit FIFO, and all reads address the receive FIFO. Normal regis- ter addressing is accomplished by holding AD6 low during the ALE address cycle. Block moves can be dis- abled by clearing the BM bit (R0—B3) to 0. Serial Link Interface The HIFI-64 can interface to a wide variety of serial links. In the simplest interface, the time-slot feature is not used, and the HIFI-64 performs HDLC processing in conjunction with three externally supplied clocks: CLK, CLKR, and CLKX. The maximum data rate fre- quency is 4.096 MHz, and the minimum CLK frequency must be greater than two times the fastest data clock frequency. In the case of a burst clock, the fastest data clock frequency is deﬁned as the clock frequency dur- ing the burst. If the time-slot feature is enabled (HWYEN, R0—B7 = 1), the HIFI-64 is capable of controlling sep- arate transmit and receive time slots on a wide variety of time-division multiplexed (TDM) serial highways. In particular, the HIFI-64 can interface to the Lucent Con- centration Highway—a variable-speed, dual full-duplex serial highway. The HIFI-64 can also interface to a vari- ety of TDM highways containing 64 or fewer time slots (primary-rate interface, SLD, K, K2, GCI, IOM, IOM2, etc.). The IOM, IOM2, and GCI interfaces specify the data clock to be twice the data transmission frequency. In order to comply with this speciﬁcation, a Clock Mode Select (CMS) bit (R8—B6) has been included. The bit has the effect of dividing the data clock by two inter- nally. In CMS mode, the minimum CLK frequency must be greater than the data clock. Enabling the Transmitter and Receiver The HIFI-64 can transmit on either of two transmit data pins (DXA, pin 19, and DXB, pin 17), or can broadcast on both pins by appropriately programming the DXAC (R7—B7) and DXBC (R7—B6) bits in the transmit time- slot control register (R7—B6,B7). If both pins are selected, the same data appears on both. The behavior of pin 17, either DXB or TSCA , is controlled by the P17CTL (R5—B7) bit. The P17CTL bit must be cleared to 0 to enable transmission on DXB. Pin 17 can be con- ﬁgured as TSCA by setting P17CTL to 1. When P17CTL is set to 1, the setting of DXBC (R7—B6) is ignored. While conﬁgured as TSCA , pin 17 is low continually if HWYEN (R0—B7) = 0 and DXAC (R7—B7) = 1.

Table 3. Transmit Pin Behavior 0 0 X X 3-state 3-state Reset condition. 0 1 0 0 3-state 3-state Data can be lost. 1 1 0 0 3-state 3-state Data can be lost.

Lucent Technologies Inc. 13 Data Sheet April 1997 T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Time-Slot Feature The HIFI-64 can be conﬁgured to interface with devices supplying a frame-synchronization signal (FS) to indi- cate the beginning of a single or multiple time-slot sequence. The T7121 can be conﬁgured to interface to TDM highways from 3 to 64 time slots. The HWYEN bit (R0—B7) enables the time-slot feature logic. All highway parameters should be programmed before enabling HWYEN. When HWYEN is 0, any input on the FS pin is ignored. When HWYEN is 1, data transmission begins with the ﬁrst programmed time slot following the ﬁrst detected frame sync, provided that at least one of the transmit pins is enabled and at least one transmit bit is unmasked. The ﬁrst data byte trans- mitted in all cases is FF hex. When transmit highway parameters are changed, such as time slot, the trans- mitter and transmit output pins should be disabled (ENT R6—B3 = 0, DXBC R7—B6 = 0, DXAC R7—B7 = 0). This guarantees that no other time slot is corrupted during reprogramming. When the receiver time slot is changed, the receiver should be disabled (ENR R6—B2 = 0). After reprogramming, 1 TDM frame is necessary to resynchronize. When HWYEN is ﬁrst enabled, the user should wait one TDM frame between enabling HWYEN and enabling the transmit outputs. The highway logic is reset completely to a known state by each FS pulse or by a full chip reset. The T7121 provides a bit masking feature to allow sub- rate operation. The default bit masks are FF hexadeci- mal for the receiver bit mask (R12) and 00 hexadecimal for the transmitter bit mask (R13). The transmitter by default transmits no bits in the selected time slot. To enable transmission of all 8 bits in the selected time slot, the transmitter bit mask (R13) must be changed to FF hexadecimal (see the Bit Masking section for more details). The HIFI-64 determines that an FS has occurred by sampling the FS signal with the appropriate data clock. The polarity of a valid FS is determined by FSPOL (R0—B6). That is, if FSPOL is 0, the FS is considered valid when low. When FSPOL is 1, the FS is consid- ered valid when high. When an FS pulse is provided, at least one FS pulse must be provided for every 512 data clock cycles. The FE bit (R0—B5) controls the edge of the data clock used to sample the FS signal. If FE (R0—B5) is cleared to 0, FS is sampled on a negative edge of the transmit and receive data clocks. If FE is set to 1, FS is sampled on a rising edge of the transmit and receive data clocks. The HIFI-64 can be programmed to transmit data on either a positive or negative edge of the data clock by programming the CLKXI bit (R9—B4). Similarly, the device can be programmed to sample received data on either a positive or negative edge of the data clock by programming the CLKRI bit (R9—B0). The timing of the transmission or reception of the ﬁrst bit relative to the frame-sync pulse then depends on the conﬁguration of three bits: FE (R0—B5), CLKXI (R9—B4), and CLKRI (R9—B0). Figure 12 in the Timing Characteristics sec- tion shows the position of the ﬁrst transmit bit and receive bit relative to the FS for each combination of these register bits. These register conﬁgurations are assumed: HWYEN (R0—B7) = 1 FSPOL (R0—B6) = 1 Figure 13 in the Timing Characteristics section shows an example of bit masking; all other examples assume no masking. Transmission can be over DXA and/or DXB (depending on the conﬁguration of the DXAC and DXBC bits in register 7 [R7—B6,7]), and TSCA is shown to illustrate transmission over DXA with an external driver. DRA or DRB can be used to receive incoming data (depending on conﬁguration of the DRA/ B bit [R8—B7]). The HIFI-64 can be programmed to delay transmission of the ﬁrst bit by using the offset registers. These are the transmit bit offset TBOF (R9—B[7—5]), the transmit time-slot TSLT (R7—B[5—0]), and the transmitter time- slot offset TTSOF (R10—B[5—0]). The transmit bit off- set register moves the transmission of the ﬁrst bit for- ward one bit at a time, up to 7 bits total. The transmitter time-slot offset moves the ﬁrst bit forward by multiples of 8 bits. The combination of the settings of these two registers deﬁnes the position of time slot 0. From that point, the time slot is selected by the value of the trans- mitter time slot TSLT (R7—B[5—0]). The ﬁrst bit is transmitted TBOF + (8 x TTSOF) + (8 x TSLT) = N bit times after the beginning of the TDM frame.

Figure 5. Maximum Bit and Time-Slot Offsets for a Four Time-Slot System times in the assigned time slot. other words, the HIFI-64 can be receiving LSB ﬁrst but transmitting most signiﬁcant bit (MSB) ﬁrst, or vice versa. convention used represents user data in the FIFO with lower-case letters and HDLC data as upper-case letters. slot(s) may not be identical bit-for-bit (i.e., zero-bit insertion and deletion—see the HDLC section of this document).

16 Lucent Technologies Inc. Data Sheet April 1997T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Bit Masking When in the TDM highway mode (HWYEN, R0—B7 = 1), the HIFI-64 can be programmed to mask any combina- tion of bits in a byte. As an example, this feature is used to process 16 kbits/s D-channel data where only 2 bits in each byte are looked at when receiving, and where only 2 bits are transmitted during an 8-bit time slot. Using this option, the HIFI-64 is able to support effective intermediate data rates of 8, 16, 24, 32, 40, 48, and 56 kbits/s. The receiver ignores bit positions that are masked (cleared to 0) in the receiver bit mask register (R12). The trans- mitter outputs high impedance (3-state) during the bit times speciﬁed (cleared to 0) in the transmitter bit mask reg- ister (R13). The user can program any combination of bits to be masked in the receiver and transmitter independently. Upon chip reset, the default is as follows: 1. The receiver defaults to recognize all incoming data as valid (i.e., no masking). 2. The transmitter defaults to a state where all bits are masked. The user must unmask the bits to be transmitted. This eliminates the problem of the HIFI-64 transmitting before the time slot has been programmed in registers 7, 9, and 10. Figures 8 and 9 show how 16 kbits/s operation is achieved by using the bit-masking option.

Note: abcdefgh are not the same as ABCDEFGH due to HDLC processing. Figure 8. 16 kbits/s Operation ARE IGNORED BY THE RECEIVER. ARE IGNORED BY THE RECEIVER.

Note: abcdefgh are not the same as ABCDEFGH due to HDLC processing. Figure 9. 16 kbits/s Operation, MSB First ARE IGNORED BY THE RECEIVER.

assume HWYEN (R0—B7) = 1 and FSPOL (R0—B6) = 1. control, and information ﬁelds for LAPB or LAPD frames are fetched from the transmit FIFO for transmission. sequence or cyclic redundancy check (CRC) bits. assumed to have been inserted and is deleted (bit destufﬁng). Table 4. Example Register Settings

2020 Lucent Technologies Inc. Data Sheet April 1997T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Flags. All ﬂags have the bit pattern 01111110 and are used for frame synchronization. The HIFI-64 automati- cally sends two ﬂags between frames. If the FLAGS bit in the chip-conﬁguration register (R0—B2) is cleared to 0, the 1s idle byte (11111111) is sent between frames if no data is present in the FIFO. Once there is data in the transmit FIFO, an opening ﬂag is sent followed by the frame. If the FLAGS bit (R0—B2) is set to 1, the HIFI- 64 sends continuous ﬂags when the transmit FIFO is empty. During transmission, two successive ﬂags will not share the intermediate 0. The HIFI-64 does not transmit consecutive frames with a shared ﬂag. An opening ﬂag is generated at the beginning of a frame (indicated by the presence of data in the transmit FIFO and the transmitter enabled). Data is transmitted per the HDLC protocol until a byte is read from the FIFO with TFC set. The HIFI-64 follows this byte with the CRC sequence and a closing ﬂag. The receiver recognizes the 01111110 pattern as a ﬂag. Two successive ﬂags may or may not share the intermediate 0 bit and are identiﬁed as two ﬂags (i.e., both 011111101111110 and 0111111001111110 are recognized by the HIFI-64). The received data bytes are stored in the 64-byte receive FIFO delayed by three bytes or delayed by four bytes if operating in the TDM highway mode (i.e., HWYEN, R0—B7 = 1). When another ﬂag is identiﬁed, it is treated as the closing ﬂag. As mentioned above, a ﬂag sequence in the user data or FCS ﬁelds is prevented by zero-bit insertion and deletion. The received CRC bytes are not loaded into the receive FIFO. The HIFI-64 receiver recognizes a single ﬂag between frames as both a closing and open- ing ﬂag. Aborts. The bit pattern of the abort sequence is 01111111, with 0 transmitted ﬁrst. A frame can be aborted by writing a 1 to TABT (R1—B6). This causes the last byte written to the transmit FIFO to be replaced with the abort sequence upon transmission. Once a byte is tagged by a write to TABT, it cannot be cleared by subsequent writes to R1. TABT (R1—B6) and TFC (R1—B7) should never be set to 1 simultaneously since this causes the transmitter to enter an invalid state that requires a transmitter reset to clear. A frame should not be aborted in the very ﬁrst byte following the opening ﬂag. An easy way to avoid this situation is to ﬁrst write a dummy or junk byte into the queue and then write the abort command to the queue. When receiving a frame, the receiver recognizes the abort sequence whenever it receives a 0 followed by seven consecutive 1s. This status results in the abort bit, and possibly the bad byte count bit and/or bad CRC bits, being set in the Status of Frame status byte which is appended to the receive data queue. The last two bytes of user data are assumed to be CRC bits and are not placed in the queue. All subsequent bytes are ignored until a valid opening ﬂag is received. Idles. In accordance with the HDLC protocol, the HIFI- 64 recognizes 15 or more contiguous received 1s as idle. When the HIFI-64 receives 15 contiguous 1s, the receiver idle bit (RIDL, R15—B6) is set in register 15. An interrupt pin transition is generated if no other unmasked interrupts are active and the RIDL interrupt is unmasked; i.e., RIIE (R14—B6) = 1. For transmission, the 1s idle byte is deﬁned as the binary pattern 11111111 (FF hexadecimal). If the FLAGS control bit in the chip conﬁguration register (R0—B2) is 0, the 1s idle byte is sent as the time-ﬁll byte between frames. A time-ﬁll byte is sent when the transmit FIFO is empty and the transmitter has com- pleted transmission of all previous frames. Frames are sent back-to-back otherwise. If the FLAGS bit (R0—B2) is set to 1, ﬂags (01111110) are sent as the time-ﬁll byte between frames. 1s idle is the default time-ﬁll byte. Note: Regardless of the time-ﬁll byte used, there always is an opening and closing ﬂag with each frame. Back-to-back frames are separated by two ﬂags. CRC. For a given frame of bits, 16 additional bits that constitute an error-detecting code are added by the transmitter. As called for in the HDLC protocol, the Frame Check Sequence bits are transmitted most sig- niﬁcant bit ﬁrst and are bit stuffed. The Cyclic Redun- dancy Check (or Frame Check Sequence) is calculated as a function of the transmitted bits by using the ITU-T standard polynomial: x 16 + x12 + x5 + 1 At the other end, the receiver performs the same calcu- lation on the received bits after destufﬁng and com- pares the results to an expected result. An error occurs if, and only if, there is a mismatch. The transmitter can be instructed to transmit a cor- rupted CRC by setting the Transmit Bad CRC bit TBCRC (R14—B7). As long as the TBCRC bit is set, the CRC is corrupted for each frame transmitted by log- ically ﬂipping the least signiﬁcant bit of the transmitted CRC. The receiver calculates and veriﬁes the CRC for an incoming frame. The result of the CRC check is reported in bit 7 of the Status of Frame byte which is placed in the receive FIFO after the last data byte of the frame. The CRC is not stored in the FIFO.

Lucent Technologies Inc. 21 Data Sheet April 1997 T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Transmitter FIFO Data associated with multiple frames can be written to the transmit FIFO by the controlling microprocessor. However, all frames must be explicitly tagged with a Transmit Frame Complete (TFC) bit (R1—B7) or a Transmit Abort (TABT) bit (R1—B6) by writing to regis- ter 1. The TFC is tagged onto the last byte of a frame written into the transmitter FIFO. TFC instructs the transmitter to end the frame by attaching the CRC and closing ﬂag following the tagged byte. Once written, the TFC cannot be changed by another write to R1. If TFC is not written before the last data byte is read out for transmission, an underrun occurs. When the FIFO is empty, writing two data bytes to the FIFO before setting TFC provides a minimum of eight CLKX periods to write TFC. TABT (R1—B6) and TFC (R1—B7) should never be set to 1 simultaneously. This causes the trans- mitter to enter an invalid state requiring a transmitter reset. When the transmitter has completed a frame, with a closing ﬂag or an abort sequence, the TDONE (R15—B0) bit is set to 1. If TDIE (R14—B0) is 1 and no other prior unacknowledged interrupt exists, the INT pin transitions. Sending 1-Byte Frames Sending 1-byte frames with an empty transmit FIFO is not recommended. If the FIFO is empty, writing two data bytes to the FIFO before setting TFC provides a minimum of eight CLKX periods to write TFC. When one byte is written to the FIFO, TFC must be written within 1 CLKX period to guarantee it is effective. Thus, 1-byte frames are subject to underrun aborts. One-byte frames cannot be aborted with TABT. Placing the trans- mitter in 1s idle mode (FLAGS, R0—B2 = 0) lessens the frequency of underruns. If the transmit FIFO is not empty, then 1-byte frames present no problem. Transmitter Underrun After writing a byte to the transmit queue, the user has eight CLKX cycles in which to write the next byte before a transmitter underrun occurs. An underrun occurs when the transmitter has ﬁnished transmitting all the bytes in the queue, but the frame has not yet been closed by writing TFC. When a transmitter underrun occurs, the abort sequence is sent at the end of the last valid byte transmitted. A TDONE interrupt is generated, and the transmitter reports an underrun abort in the interrupt status register (R15—B2). The transmitter enters forced idle (sending FLAGS or IDLES based upon the value in R0—B2) until the interrupt status reg- ister (R15) is read. Using the Transmitter Status and Fill Level The Transmitter-interrupt Level bits (R1—B[5—0]) allow the user to instruct the T7121 to interrupt the host pro- cessor whenever the transmitter has a predetermined number of empty locations. The number of locations selected determines the time between transmitter empty (TE) interrupts. The transmitter status bits (R2—B[6—0]) report the number of empty locations in the transmitter FIFO. The bits are encoded in binary with bit 0 the least signiﬁcant bit. Also found in register 2 is the Transmitter Empty Dynamic bit, TED (R2—B7). This bit, like the TE interrupt bit, is set when the number of empty locations is less than or equal to the pro- grammed empty level. TED returns to 0 when the trans- mitter is ﬁlled to above the programmed empty level. Polled interrupt systems can use TED to determine when they can write to the transmit FIFO. Programming Note: After the transmitter is turned off, a transmitter reset should be performed (TRES, R6, bit 5 = 1) before the transmitter is turned on. After the receiver is turned off, a receiver reset should be per- formed (RRES, R6, bit 4 = 1) before the receiver is turned on. The transmitter and receiver should both be reset individually (i.e., not at the same time) after any concentration highway conﬁguration change. If TRES = RRES = 1 at the same time, a full chip reset is per- formed: all register bits are forced to their reset values. Receiver FIFO The receiver status is available in two ways. First, the queue manager creates a Status of Frame (SF) byte for each HDLC frame and stores this status byte in the FIFO after the last data byte of the associated frame. Thus, a frame containing 24 user data bytes results in 25 bytes present in the receive FIFO. The SF status byte has the following format: STATUS OF FRAME BYTE BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 BAD CRC ABORT OVERRUN BAD BYTE COUNT 0000

2222 Lucent Technologies Inc. Data Sheet April 1997T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Bit 7 of the SF status byte is the CRC status bit. If an incorrect CRC was detected, this bit is set to 1. If the CRC was correct, the bit is 0. Bit 6 of the SF status byte is the abort status. A high (1) indicates the frame associated with this status byte was aborted (i.e., the abort sequence was detected after an opening ﬂag and before a subsequent closing ﬂag). An abort can also cause bits 7 and/or 4 to go high (1). An abort is not reported when a ﬂag is followed by seven 1s. If the Overrun bit (bit 5) is high, it indicates that a receiver FIFO overrun occurred (the 64-byte FIFO size was exceeded; see the Receiver Overrun section). The Bad Byte Count bit (Bit 4) indicates whether or not the bit count received was a multiple of eight (i.e., an integer number of bytes). A high (1) indicates that the bit count received after 0-bit deletion was not a multiple of eight, and a low indicates that the bit count was a multiple of eight. When a non-byte-aligned frame is received, all bits received are present in the receive FIFO. The byte before the SF status byte contains less than eight valid data bits. The nondata bits are the ﬁrst bits of the received CRC. The T7121 provides no indi- cation of how many of the bits in the byte are valid. It is up to the user and the protocol to decide what to do with non-byte-aligned frames. Bits 0 to 3 of the SF status byte are not used and are guaranteed to be 0 when read. A good frame is implied when the SF status byte is 00 hexadecimal. The last byte of a completed frame in the receive FIFO is always the SF status byte. As a frame is received, the two bytes preceding the closing ﬂag are assumed to be the frame check sequence (CRC) bits and are not loaded into the receiver FIFO. Thus, the ﬁnal 2 bytes received in an aborted frame are not placed in the queue, and an aborted frame of 2 bytes or less causes only an SF status byte to appear in the receiver FIFO. The writing of the SF status byte is followed by the REOF (R15—B4) interrupt bit being set. The REOF event triggers an interrupt, unless the interrupt is masked by REOFIE (R14—B4) = 0, whenever no other unmasked interrupts are active. The Receive Queue Status bits (RQS, R4—[6—0]) are updated as bytes are loaded into the receive FIFO. The SF status byte is included in the byte count. When the ﬁrst SF status byte is placed in the FIFO, the EOF (R4—B7) bit is set, and the status freezes until the FIFO is read. As bytes are read from the FIFO, the sta- tus decreases until it reads 1. The byte read when the RQS is "0000001" and the EOF bit is high (1) is the SF status byte describing the error status of the frame just read. Once the ﬁrst SF status byte is read from the FIFO, the FIFO status is updated to report the number of bytes to the next SF status byte, if any, or the number of additional bytes present. When EOF (R4—B7) is low, no SF status byte is currently present in the FIFO, and the RQS bits report the number of bytes present. As bytes are read from the FIFO, the status decreases with each read until it reads 0 when the FIFO is totally empty. The EOF bit is also low when the FIFO is com- pletely empty. Thus, the RQS and EOF bits provide a mechanism to recognize the end of one frame and the beginning of another. Reading the receiver status reg- ister (R4) does not affect the FIFO buffers. In the event of a receiver overrun (see below), an SF status byte is written to the receive FIFO. Multiple SF status bytes can be present in the FIFO. Remember, the RQS reports only the number of bytes to the ﬁrst SF status byte. To allow users to tailor receiver FIFO service intervals to their systems, the Receiver Interrupt Level bits (RIL, R5—B[5—0]) are provided. These bits are coded in binary and determine when the Receiver Full (RF , R15—B3) interrupt is asserted. The interrupt pin transition can be masked by clearing RFIE, R14—B3 to 0. The value programmed in the RIL bits equals the total number of bytes necessary to be present in the FIFO to trigger an RF interrupt. The RF interrupt alone is not sufﬁcient to determine the number of bytes to read as some of the bytes may be SF status bytes. The RQS bits and EOF bit in register 4 allow the user to determine the number of bytes to read. The REOF interrupt can be the only interrupt for the ﬁnal frame of a group of frames, since the number of bytes received to the end of the frame cannot be sufﬁcient to trigger an RF interrupt.

Lucent Technologies Inc. 23 Data Sheet April 1997 T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Programming Note: Since the receiver writing to the receive FIFO and the host reading from the receive FIFO are asynchronous events, it is possible for a host read to put the number of bytes in the receive FIFO just below the programmed RIL level and a receiver write to put it back above the RIL level. This causes a new RF interrupt. This has the potential to cause software prob- lems. It is recommended that during service of the RF interrupt, the RF interrupt be masked RFIE (R14—B3) = 0 and the interrupt register be read at the end of the service routine, discarding any RF interrupt seen, before unmasking the RF interrupt. Programming Note: After the transmitter is turned off, a transmitter reset should be performed (TRES, R6, bit 5 = 1) before the transmitter is turned on. After the receiver is turned off, a receiver reset should be per- formed (RRES, R6, bit 4 = 1) before the receiver is turned on. The transmitter and receiver should both be reset individually (i.e., not at the same time) after any concentration highway conﬁguration change. If TRES = RRES = 1 at the same time, a full chip reset is per- formed: all register bits are forced to their reset values. Receiver Overrun A receiver overrun occurs if the 64-byte limit of the receiver FIFO is exceeded, i.e., data has been received faster than it has been read out of the receive FIFO and written to the system memory. Upon overrun, an SF status byte with the overrun bit (bit 5) set replaces the last byte in the FIFO. The SF status byte can have other error conditions present. For example, it is unlikely the CRC is correct. Thus, care should be taken to prioritize the possible frame errors in the software service routine. The last byte in the FIFO is overwritten with the SF status byte regardless of the type of byte (data or SF status) being overwritten. The overrun con- dition is reported in register 15 (R15—B5) and causes the interrupt pin to be asserted if it is not currently asserted and it is not masked (ROVIE, R14—B5). Data is ignored until the condition is cleared. The overrun condition is cleared by reading register 15 and reading at least 1 byte from the receive FIFO. Because multiple frames can be present in the FIFO, good frames as well as the overrun frame can be present. The host can determine the overrun frame by looking at the SF sta- tus byte. Operational Note (T7121-EL, T7121-PL, T7121-EL2, and T7121-PL2) In HDLC protocol, binary 1s may be transmitted between frames (interframe ﬁll) when no user data is available. Short bursts of interframe ﬁll, not speciﬁed in the current standards, have been encountered when system testing against some switch equipment. Per Lucent’s interpretation of the standards, the device will treat received interframe ﬁll from 1 bit to 5 bits in length as a short packet and report a received end of frame condition in register R15, bit 4 (EOF = 1). A hardware interrupt will be generated if the REOF interrupt is enabled in register R14, bit 4 (REOFIE = 1). This may be a performance issue in some systems due to the extra interrupts that the host processor must service, produced by short bursts of interframe ﬁll from 1 bit to 5 bits in length. The contents of both register R4 (Receiver Status Reg- ister) and the receive FIFO depend on the number of interframe 1s received. If one bit of interframe ﬁll is received, R4 will indicate that an end of frame has occurred, but zero bytes are stored in the receive FIFO (i.e., no Status of Frame byte was written to the FIFO). Data reception can pro- ceed normally without further intervention by the host processor. If 2 bits to 5 bits of interframe ﬁll are received, R4 will indicate that an end of frame has occurred, and that one byte was stored in the receive FIFO. The 1 byte stored in the FIFO is the Status of Frame byte due to the interframe ﬁll and will have a value of 0x90, indicat- ing a bad CRC and bad byte count. This byte should be read out and discarded. After removing the Status of Frame byte from the FIFO, data reception can proceed normally without further intervention by the host micro- processor. If 6 bits or more of interframe ﬁll are received, the device correctly ignores these bits. The FIFO is not written and no interrupts are generated.

2424 Lucent Technologies Inc. Data Sheet April 1997T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) Transparent Mode The HIFI-64 can be programmed to operate in the transparent mode by setting the TRANS bit (AR11—B6) to 1. In the transparent mode of operation, no HDLC processing is performed on user data. The transparent mode can be exited at any time by clearing the TRANS bit to 0. It is recommended that the trans- mitter be disabled (ENT, R6—B3 = 0) when changing in and out of transparent mode. The transmitter should be reset by a TRES whenever the mode is changed. Three alternate registers are provided to control opera- tion in the transparent mode: AR11—Transparent Mode Control AR12—Receive Match Character AR13—Transmitter Idle Character The alternate registers are accessed by setting the ALT bit (R0—B4) to 1. All subsequent addressing of regis- ters 11 through 13 then refer to the alternate registers (AR11—AR13). Returning to the foreground register set is accomplished by clearing the ALT bit (R0—B4) to In the transmit direction, the HIFI-64 takes data from the transmit FIFO and transmits that data exactly bit for bit on the DXA pin, the DXB pin, or both, depending on the conﬁguration of the DXAC and DXBC bits in regis- ter 7 (R7—B6, B7). When there is no data in the trans- mit FIFO, the HIFI-64 either transmits all 1s, or transmits the transmitter idle character programmed in AR13 if the MATCH bit (AR11—B5) is set to 1. To cause the transmit idle character to be sent ﬁrst, the character must be programmed in AR13 before the transmitter is enabled. In non-TDM highway modes, the transmit idle character or the 1s idle character is always sent ﬁrst, even if data is present in the FIFO. In TDM highway mode, the ﬁrst character trans- mitted is FF hexadecimal regardless of the mode. The bits are transmitted least signiﬁcant bit ﬁrst in non-TDM highway mode (HWYEN, R0—B7 = 0). In TDM highway modes (HWYEN = 1), the TLBIT (R10—B6) deter- mines the bit transmission order. Subrate operation using the transmit bit mask is also supported. The transmitter empty (TE) interrupt acts normal. The transmitter-done interrupt (TDONE) is used to report an empty transmit FIFO. The TDONE interrupt thus provides a way to determine transmission end. In transparent mode, a TDONE interrupt is generated when the transmitter is reset, as does a TE interrupt. The UNDABT interrupt is not active in transparent mode. If the HIFI-64 is in the TDM highway mode (HWYEN, R0—B7 = 1), transmit data is octet-aligned to the selected time slot. If HWYEN = 0, transmit data is octet-aligned to the ﬁrst CLKX after the transmitter has been enabled (ENT, R6 B3 = 1). See Figure 3 for details of clock start-up in non-TDM highway modes. In the receive direction, the HIFI-64 loads received data from the DRA or DRB pin (depending on the conﬁgura- tion of the DRA/B bit in register 8 [R8—B7]) directly into the receive FIFO bit for bit. In non-TDM highway modes, the data is assumed to be least signiﬁcant bit ﬁrst. In TDM highway mode, the RLBIT (R11 B6) con- trols the bit order. If the MATCH bit (AR11—B5) is 0, the receiver begins loading data into the receive FIFO, beginning with the ﬁrst CLKR detected after the receiver has been enabled (ENR, R6—B2 = 1). If the MATCH bit (AR11—B5) is set to 1, the receiver does not begin loading data into the FIFO until the receiver match character programmed in AR12 has been detected. The search for the receiver match character is in a sliding window fashion if the ALOCT (Align to Octet) bit (AR11—B4) is 0, or only on octet boundaries if the ALOCT bit is set to 1. The octet boundary is aligned to the receive time slot if HWYEN (R0—B7) = 1 or relative to the ﬁrst CLKR after the receiver has been enabled (ENR, R6—B2 = 1), if HWYEN (R0—B7) = 0. The matched character and all subsequent bytes are placed in the receive FIFO. A receiver reset RRES causes the receiver to realign to the match character if MATCH is set. The receiver full (RF) and receiver overrun (OVERUN) interrupts act as normal. The received end of frame (REOF) and receiver idle (RIDL) interrupts are not used in the transparent mode. The match status (MSTAT) bit (AR11—B4) is set to 1 when the receiver match character is ﬁrst recognized. If the MATCH bit (AR11—B5) is 0, the MSTAT bit (AR11—B4) is set to 1 automatically when the ﬁrst bit is received, and the octet offset status bits (AR11—B[0—2]) read 000. If the MATCH bit (AR11—B5) is programmed to 1, the MSTAT bit (AR11—B4) is set to 1 upon recognition of the ﬁrst receiver match character, and the octet offset status bits (AR11—B[0—2]) indicate the offset relative to the octet boundary at which the receiver match char- acter was recognized. The octet offset status bits have no meaning until the MSTAT bit is set to 1. An octet off- set of 111 indicates byte alignment. An interrupt for recognition of the match character can be generated by setting the RIL level to 1. Since the matched character is the ﬁrst byte written to the FIFO, the RF interrupt occurs with the writing of the match character to the receive FIFO.

transmit idle character is programmed to FF hex, the MATCH bit appears to affect only the receiver. The operation of the receiver in transparent mode is summarized in Table 5. The serial link interface can operate in two diagnostic loopback modes: (1) local loopback and (2) remote loopback. attempt local and remote loopbacks. bits in register 7 (R7—B6 and R7—B7). Table 5. Receiver Operation in Transparent Mode

0 X 0 Serial-to-parallel conversion begins with ﬁrst CLKR after

ENR is set. Data loaded to receive FIFO immediately. 0 0 1 Match user-deﬁned character (AR12) using sliding window. receive FIFO until match is detected. data to receive FIFO until match is detected. to receive FIFO immediately. 1 0 1 Match user-deﬁned character (AR12) using sliding window. receive FIFO until match is detected. time slot. No data to receive FIFO until match is detected.

parameters need not be altered). n CLKX clocks both the transmitter and the receiver. n The DXA and DXB outputs are active, depending on DXAC and DXBC. n The DRA or DRB input is ignored. n The communication between the transmit and receive FIFO buffers and the microprocessor continues normally. Figure 10. Local Loopback Mode

n Receive and transmit bit masks (R12 and R13) should be programmed to the same value. receive time slot is complete. n Received data is retransmitted on the DXA and/or the DXB output, depending on DXAC and DXBC. as usual to the receive FIFO if the receiver is enabled. Figure 11. Remote Loopback Mode unknown state in the chip which only a full reset of the chip can clear.

28 Lucent Technologies Inc. Data Sheet April 1997T7121 HDLC Interface for ISDN (HIFI-64) Functional Description (continued) 3-State Mode The HIFI-64 can be placed in a high-impedance mode for test purposes. In this conﬁguration, all output pins are placed in a 3-state condition. This can be accomplished in two different ways: 1. Asserting the RESET pin 3-states all outputs, clears both the transmit and receive FIFOs, and resets all internal registers to their default values. A full chip reset occurs with or without a clock input. 2. Setting the 3STATE bit (R6—B6) to 1 3-states all outputs without affecting the states of internal registers and FIFOs. This state lasts until both CS and RD are held low; that is, the ﬁrst read of the HIFI-64 resets the 3STATE bit regardless of the register address. Registers can be written while the 3STATE bit is enabled. Setting the receiver reset (RRES) and the transmitter reset (TRES) bits in the operation control register (R6—B4,B5) to 1 simultaneously causes a FIFO and register reset to reset values (outputs are not 3-stated). Other The HIFI-64 can be instructed to transmit a bad CRC for test purposes by programming the TBCRC bit in register 14 (R14—B7) to 1. Bad CRCs are transmitted until the TBCRC bit is cleared. The TEST bit in AR11 is used for manufacture testing and should always be programmed low (0) by the host microprocessor. Powerdown Mode The HIFI-64 can be placed in a low-power mode when not in use by setting the PDWN bit in register 6 (R6—B7) to 1. This has the effect of stopping data clock input signals (CLKR and CLKX) from propagating internally and results in very low power dissipation. Reads and writes to the HIFI-64 can continue normally. The low-power mode is exited by clearing the PDWN bit (R6—B7) to 0. Registers The HIFI-64 contains 19 registers (R0—R15 and AR11—AR13). Registers 11, 12, and 13 have alternate meanings depending on the value of the ALT bit in the Chip Conﬁguration Register (R0—B4). The alternate registers are accessed by setting the ALT bit (R0—B4) to 1. All subsequent addressing of registers 11 through 13 then refers to the alternate registers (AR11—AR13). Returning to the foreground register set is accomplished by clearing the ALT bit (R0—B4) to 0. The primary function of the alternate registers is for transparent-mode operation. A summary of the HIFI-64 register set is given in Table 6.

Table 6. HIFI-64 Register Summary

Numbers in parentheses indicate the value of each bit upon being reset.

Table 7. Register R0—Chip Configuration Register INT pin to behave dynamically. See register 15 for more details. nal (pin 15) is active-high. If this bit is 0, the INT signal is active-low. sent. This bit is active only in HDLC mode. tiplexed address/data bus since it depends on the AD6 pin. to registers (R11—R13) is accomplished by clearing this bit to 0. edge of FS indicates the beginning of a frame. tions are controlled by the CLKX and CLKR inputs.

Do not set TABT and TFC to 1 at the same time.

Table 8. Register R1—Transmitter Control Register (01111111) in place of that byte. A full byte is guaranteed to be transmitted. byte, TABT cannot be cleared by writing to register 1. ten to 0 to begin a new frame.

low during the ALE address cycle. Block move is enabled and disabled by the BM bit in register 0 (R0—B3). Table 9. Register R2—Transmitter Status Register encoded in binary, with bit 0 being the LSB. Table 10. Register R3—Data Byte Register

Table 11. Register R4—Receiver Status Register the number of bytes up to and including the ﬁrst SF byte.

Table 12. Register R5—Receiver Control Register when the receive FIFO is actually full. as CLKR and provides the timing for received data.

RLOOP and LLOOP should not be set to 1 simultaneously.

†Setting RRES and TRES simultaneously returns the registers to their default values without causing the outputs to 3-state. Table 13. Register R6—Operation Control Register the distant end. When this bit is 0, normal transmission occurs. nal receiver. The receive data pin input (either DRA or DRB) is ignored. Clearing this bit to 0 allows normal transmission. are cleared. The receiver is placed in a known state. HDLC mode and set in transparent mode. in signiﬁcantly reduced power dissipation.

same time slot on both pins. Table 14. Register R7—Transmit Time-Slot Control Register slot number for transmission on the chosen pin (DXA and/or DXB). overrides the setting of DXBC. transmitted on the DXA pin (pin 19). Table 15. Register R8—Receiver Time-Slot Control Register for information received on the chosen receive data pin (DRA or DRB).

Table 16. Register R9—Bit Offset Control Register Table 6 for an example of using RBOF . transmitted on the rising edge of CLKX. Figures 13—21 for placement of the ﬁrst transmittable bit position. this offset. See Figure 5 for an example of using TBOF .

Table 17. Register R10—Transmitter Time-Slot Offset Control Register ure 5 for an example of using the TTSOF bits. cant bit of data is transmitted ﬁrst. always least signiﬁcant bit ﬁrst. output is inverted before transmission.

Table 18. Register R11—Receiver Time-Slot Offset Control Register example of using the RTSOF bits. deﬁned as that bit which is read on AD0 when the FIFO is read. always received least signiﬁcant bit ﬁrst. HDLC receiver (or FIFO in the transparent mode).

has been enabled (ENR, R6—B2 = 1) if HWYEN = 0. Table 19. Alternate Register AR11—Transparent-Mode Control Register to the octet boundary* when the receive character was matched. The OCTOF bits are valid when MSTAT (AR11—B3) is set to 1. is 111 (byte alignment), one bit of offset is 000, etc. status bits (AR11—B[0—2]) read 000. match character in a sliding window fashion. See Table 5. AR11 B5 MATCH Pattern Match. MATCH affects both the transmitter and receiver. acters when the transmit FIFO is empty. forms no HDLC processing on incoming or outgoing data. AR11 B7 TEST TEST. This bit is reserved for manufacturing test purposes only.

Table 20. Register R12—Receiver Mask Register masking and subrate operation. Table 21. Alternate Register AR12—Receiver Match Character Register boundaries (ALOCT, AR11—B4 = 1).

Table 22. Register R13—Transmitter Mask Register ures 8 and 9 for examples of bit masking and subrate operation. least signiﬁcant bit transmitted (as deﬁned by TLBIT, R10—B6). Table 23. Alternate Register AR13—Transmitter Idle Character Register any character can be programmed by the user.

but are reported in register 15 when it is read. Table 24. Register R14—Interrupt Mask Register pin transition is generated when the transmit FIFO is completely empty. programmed empty level (see Register 1). TEIE is cleared upon reset. cleared upon reset. UNDIE is not used in transparent mode. grammed full level (see Register 5). RFIE is cleared upon reset. is cleared upon reset. RIIE is not used in transparent mode. transmitted frames (for test purposes) until the TBCRC bit is cleared to 0.

In transparent mode (TRANS, AR11—B6 = 1), TDONE defaults to 1 when a transmitter reset (TRES, R6—B5 = 1) is performed.

Table 25. Register R15—Interrupt Status Register set. This status bit is cleared to 0 by a read of register 15. to 0 only when the transmit FIFO is loaded above the programmed empty level. data is allowed. This interrupt is not generated in transparent mode. bit is cleared to 0 by a read of register 15. R15 B7 RESERVED Program to 0.

Lucent Technologies Inc. 45 Data Sheet April 1997 T7121 HDLC Interface for ISDN (HIFI-64) Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.

Electrical Characteristics

TA = 0 °C to 70 °C, or –40 °C to +85 °C (see Ordering Information). VDD = 5 V – 5%, VSS = 0 V, 100 pF each output. Parameter Symbol Min Max Unit dc Supply Voltage Relative to VSS VDD —7 V Input Voltage Range V I VSS – 0.5 V DD + 0.5 V Storage Temperature Range T stg –40 125 °C Parameter Symbol Test Conditions Min Max Unit Supply Current I DD TA = 70 °C — 15 mA Input Leakage Current: High Level (logic 1) Low Level (logic 0) Low Level (logic 0) I IH IIL ILA VIH = 5.25 V VIL = 0 V (except A3—A0) VIL = 0, A3—A0 –7.5 7.5 A mA mA Input Leakage Current Bidirectional Pins: High Level (logic 1) Low Level (logic 0) I IH IIL VIH = 5.25 V VIL = 0 V –37.5 37.5 mA mA Output 3-state Leakage Current: High Level (logic 1) Low Level (logic 0) I OZH IOZL VOH = 5.25 V VOL = 0 V –30 mA mA Input Voltage: High Level (logic 1) Low Level (logic 0) V IH VIL 2.0 0.8 V Output Voltage: High Level (logic 1) High Level (CMOS 1) Low Level (logic 0) V OH VOHC VOL IOH = –2.4 mA IOHC = –0.24 mA IOL = 2.4 mA 2.4 3.5 0.4 V V V Power Dissipation (nominal 30 mW) PD CLK = 12 MHz, CLKX = CLKR = 4.096 MHz T A = 70 °C TA = 0 °C TA = –40 °C 105 120 mW mW mW Powerdown Mode (nominal 5 mW) PD CLK = 12 MHz, CLKX = CLKR = 4.096 MHz —1 5 m W Input Capacitance Ci — — 4 pF Output Capacitance Co — — 5 pF

System Clock Input (CLK): 0 MHz—12 MHz. Transmit Data Clock (CLKX): no minimum frequency*, <CLK/2 maximum frequency to 4.096 MHz. Receive Data Clock (CLKR): no minimum frequency*, <CLK/2 maximum frequency to 4.096 MHz. conﬁgurations of FE, CLKXI, and CLKRI. Figure 12. FE = 0, CLKXI = 0, CLKRI = 0

Both address and data on AD7—AD0.

This is the time needed to update the receive FIFO status RQS (R4—B[6—0]).

†See Figure 24 for data clock period speciﬁcation. Table 26. Multiplexed Address and Data

Figure 21. Timing for Multiplexed Address/Data

Address on A3—A0, data on AD7—AD0. must remain high during read and write operations. †This is the time needed to update the receive FIFO status RQS (R4 B[6—0]). Table 27. Separate Address and Data

Figure 22. Timing for Separate Address/Data

Table 28. Concentration Highway Timing for CMS = 0

1.Edge of clock used to sample FS (selected by the FE bit [R0—B6]). 2.Edge of ﬁrst bit transmission (see Figures 12—20). Figure 23. Timing for Concentration Highway

1.Edge of clock used to sample FS (selected by the FE bit [R0—B6]). 2.Edge of ﬁrst bit transmission (see Figures 12—20). Figure 24. Timing for Concentration Highway

Edge of clock used to sample FS (selected by the FE bit [R0—B6]).
Edge of ﬁrst bit transmission (see Figures 12—20).
The CLKXI bit (R9—B4) controls the edge on which data is transmitted, and the CLKRI bit (R9—B0) controls the edge on which received

Figure 25. Timing for Concentration Highway Table 29. Concentration Highway Timing for CMS = 1

Lucent Technologies Inc. 59 Data Sheet April 1997 T7121 HDLC Interface for ISDN (HIFI-64) Handling Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to deﬁne the model. No industry-wide standard has been adopted for the CDM. However, a standard HBM (resistance = 1500 W , capacitance = 100 pF) is widely used and therefore can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters: Human-Body Model ESD Threshold Device Voltage T7121 >500 V

60 Lucent Technologies Inc. Data Sheet April 1997T7121 HDLC Interface for ISDN (HIFI-64) Outline Diagrams 28-Pin, Plastic DIP Dimensions are in millimeters. Controlling dimensions are in inches. 5-4410r.1 Package "N" Package Dimensions Maximum Length "L" Maximum Width Without Leads "B" Maximum Width Including Leads "W" Maximum Height Above Board "H" PDIP6 (Plastic Dual In-Line Package) "0.600" Series 28 37.34 13.97 15.49 5.59 W H 0.023 MAX2.54 TYP

0.38 MIN

N PIN #1 IDENTIFIER ZONE L B

Lucent Technologies Inc. 61 Data Sheet April 1997 T7121 HDLC Interface for ISDN (HIFI-64) Outline Diagrams (continued) 28-Pin, Plastic SOJ, Surface Mounting Dimensions are in millimeters. Controlling dimensions are in inches. 5-4413r.1 Package "N" Package Dimensions Maximum Length "L" Maximum Width Without Leads "B" Maximum Width Including Leads "W" Maximum Height Above Board "H" SOJ (Small-Outline J-Lead) 28 18.03 7.62 8.81 3.18

0.020 MAX

0.64 MIN

0.10 SEATING PLANE

1.27 TYP

W N B PIN #1 IDENTIFIER ZONE L

62 Lucent Technologies Inc. Data Sheet April 1997T7121 HDLC Interface for ISDN (HIFI-64)

Ordering Information

Device Code Package Temperature T7121-PL2 28-Pin, Plastic DIP –40 °C to +85 °C T7121-EL2 28-Pin, Plastic SOJ –40 °C to +85 °C

Lucent Technologies Inc. 63 Data Sheet April 1997 T7121 HDLC Interface for ISDN (HIFI-64) Appendix This Appendix is intended to answer questions that may arise when using the T7121 HDLC Interface for ISDN. These questions have been compiled from cus- tomer inquiries. The questions and answers are divided into four operational categories: transparent mode, HDLC mode, general features, and power and ground. Transparent Mode Q1 : Since there is no interrupt due to a MATCH, how can a MATCH be detected as soon as one occurs? A1 : Initially, the receive threshold should be set to 1. An interrupt will then occur on the ﬁrst data byte after the MATCH. Next, the MATCH status should be read and a determination made as to whether the application requires a threshold other than 1; if it does, the threshold should be changed accordingly. Q2 : In transparent mode, the transmit idle character (TIC0—TIC7, AR13) and the receiver match character (RMC0—RMC7, AR12) are set to the same value and local loopback is enabled (LLOOP , R6, b1 = 1). After enabling the transmit- ter and receiver, the interrupt for receiver over- runs occurs, and the receive FIFO is full of match characters (as expected). The end-of-frame bit (EOF , R4, b7) is also set. Is this normal? A2 : Y es, this is normal operation. Although end-of- frame has no meaning in transparent mode, the EOF bit acts as another indication that the receiver has been overrun. Q3 : In the transparent mode, what does a TDONE (R15, bit 0) of 1 mean? A3 : It means the transmit FIFO is empty. If the FIFO is empty in the transparent mode conﬁguration, a TDONE interrupt will immediately occur, along with a TE interrupt, even before enabling the transmitter. HDLC Mode Q4 : If the transmit FIFO is loaded and then enabled, information is sometimes lost (in the HDLC mode), is there an explanation for this? A4 : As soon as the FIFO is loaded, the data is prepared for HDLC transmission. If the micropro- cessor (which is asynchronous with the highway) turns on the transmitter at the wrong time relative to the frame sync, then the ﬁrst byte is missed. The ﬁrst byte is the open ﬂag, so the ﬁrst frame of HDLC data is lost. There are two solutions. The ﬁrst one is to enable the transmitter and then load the FIFO. As long as the FIFO is loaded faster than data can be sent out, the system will operate without any abort interrupts. The second solution is to set the idle character to look like an open ﬂag, then load the FIFO, and then enable the transmitter; this means there is always going to be an open ﬂag. If the idle char- acter is then changed to all 1s before the FIFO is empty, all subsequent frames will have the open ﬂag, as expected, and all 1s will be sent as idle. Q5 : When using the ﬁrst solution described for Q4, 1-byte frames cannot always be sent; why? A5 : One-byte frames may not be sent properly because data may be sent before the close infor- mation register can be written—if the transmitter is enabled when the FIFO is written, data may be sent as soon as the FIFO is written—resulting in a transmit abort. However, in a real HDLC environment, address information plus data usu- ally prevents the problem from occurring. Q6 : Can the T7121 recognize the shared ﬂag between consecutive frames? In other words, can the closing ﬂag of the ﬁrst frame be the open- ing ﬂag of the second frame, i.e., Flag Data1 CRC CRC Flag Data2 . . . . A6 : Y es, this is considered normal operation. Q7 : Regarding the EOF status byte, when the bad byte count bit (bit 4) is activated (high), does the bad CRC bit (bit 7) also activate? A7 : CRC bits are checked on a bit-per-bit basis. Therefore, it is possible, but very unlikely, that a bad byte count could occur without a bad CRC indication.

6464 Lucent Technologies Inc. Data Sheet April 1997T7121 HDLC Interface for ISDN (HIFI-64) Appendix (continued) Q8 : The T7121 is in HDLC mode, and the software views the transmit FIFO as a 32 byte x 2 FIFO. When the TE and TDONE are enabled: 1. After initializing, when the ﬁrst 32 bytes transfer to the FIFO, when is the TE alert set? 2. After writing ﬁnal data into FIFO, setting TFC, and sending out this ﬁnal data, are TE and TDONE asserted at the same time? A8 : 1. The setting of the TIL bits determines when the TE interrupt will be issued. The TE inter- rupt is set in HDLC mode when the chip is reset, so as soon as the TEIE mask bit is set to enable the TE interrupt, the interrupt will be asserted. In normal interrupt mode, it will remain until the interrupt register is read. In dynamic interrupt mode (DINT = 1), the inter- rupt will be asserted until the empty level of the FIFO is greater than the value of the TIL bits; i.e., the TIL bits set the number of empty bytes (bytes available for writing) which must be present for the TE interrupt to occur. That is, if the TIL level is set at 32 bytes and 33 bytes are placed in the transmit FIFO, when the ﬁrst byte is read from the FIFO, the TE interrupt will occur (32 bytes are now empty or available to be written to). 2. TDONE is asserted two TCLKs after the last zero of the closing ﬂag is transmitted; TE is asserted as indicated above. They will not usually come at the same time. Q9 : What happens if the transmit FIFO empties out? Should an abort be received? If this is expected, is there a solution? A9 : If HDLC mode is used, letting the transmit FIFO empty out completely will cause an underrun to occur and an abort to be issued. Set the transmit- ter interrupt level (R1, b[5—0]) to a large enough level to ensure that underruns won’t occur. General Features Q10 : What happens to the highway buffers when the TDM highway mode is not enabled? A10 : In this mode, the device sends out data on every clock. Since the device has no way of knowing when a bit is ﬁnished, i.e., when the last full clock period has ended (except by the start of the next bit clock pulse), the highway transmitter remains enabled. The output will retain the state of the most recent bit. When multiplexing other data onto the highway, an external driver should be added which is enabled only during the period when the T7121 data is on the highway. Q11 : Is there any reason for resetting the receiver, other than at the beginning of operation? A11 : Other than in the case of some type of system crash, no other reason is known. Q12 : Is there any problem with letting the 3-state out- puts ﬂoat? A12 : This is generally not good design practice. The bus might ﬂoat in such a way that other devices, including T7121, would interpret it as valid data. Q13 : Please explain block move. A13 : To use block move, BM (R0, b3) must be set to 0 and use the ALE mode. When the ALE pulse goes low, AD6 must be a one. Then bytes are written into the T7121 FIFO on positive-going edges of WR, and they are read out of the T7121 FIFO when RD is low (timing of data is as shown in Figure 22). The only limit on the number of bytes that are read or written is that CS must be low, and you do not want to write a full FIFO or read an empty one. When block mode is used, the FIFO will read or write from the ﬁrst available byte, just as in normal operation.

making sure not to overﬂow the transmit buffer. with octets having these boundaries. bit (MSB), receive least signiﬁcant bit (LSB) ﬁrst. bit (MSB), receive least signiﬁcant bit (LSB) ﬁrst. Note: The effective data rate is 56 Kbytes/s. the FIFO is initially empty). Table 30. Bit Receiving and Masking Table 31. Bit Transmitting and Masking

66 Lucent Technologies Inc. Data Sheet April 1997T7121 HDLC Interface for ISDN (HIFI-64) Appendix (continued) Power and Ground Q20 : Are there any warning signs that indicate poor grounding practices have been used? A20 : If errors occur which do not appear to be due to software or to the external communications link, then loop the T7121 data path back at the concentration highway. Any data transmitted should be received error-free. If there are errors, poor grounding might be the cause. Look for glitches on RESET and WR leads. Connect RESET to ground and do a software reset; if the error rate improves, RESET is being glitched and improved grounding should help.

Lucent Technologies Inc. 67 Data Sheet April 1997 T7121 HDLC Interface for ISDN (HIFI-64) Notes

April 1997T7121 HDLC Interface for ISDN (HIFI-64) For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106), e-mail docmaster@micro.lucent.com ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 For data requests in Europe: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1734 324 299, FAX (44) 1734 328 148 For technical inquiries in Europe: CENTRAL EUROPE: (49) 89 95086 0 (Munich), NORTHERN EUROPE: (44) 1344 865 900 (Bracknell UK), FRANCE: (33) 1 41 45 77 00 (Paris), SOUTHERN EUROPE: (39) 2 6601 1800 (Milan) or (34) 1 807 1700 (Madrid) Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright © 1997 Lucent Technologies Inc. All Rights Reserved Printed in U.S.A. Printed On Recycled Paper April 1997 DS96-357ISDN (Replaces DS90-087SMOS, AY95-006ISDN, and TN96-010ISDN)

Product Information

T7121 specifications and overview.

Summary

T7121 HDLC Interface for ISDN April 1997

Description

The T7121 HDLC Interface for ISDN (HIFI-64) connects serial communications links carrying HDLC bitsynchronous data frames to 8-bit microcomputer systems. There is an optional transparent mode of operation in which no HDLC processing is performed on user data. The device communicates with the system microprocessor as a memory-mapped peripheral and is controlled by reading and writing 19 internal registers. The chip can be instructed to interrupt the microprocessor when it detects certain events requiring microprocessor attention.

Source title T7121 Datasheet(PDF) - Agere Systems

Related Parts

More parts from the same family.

Browse manufacturer