T7024_07 ATMEL | Alldatasheet
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- Single 3-V Supply Voltage High Power-added Efficient Power Amplifier (Pout Typically 23 dBm) Ramp-controlled Output Power Low-noise Preamplifier (NF Typically 2.1 dB) Biasing for External PIN Diode T/R Switch Current-saving Standby Mode Few External Components Packages: – PSSO20 – QFN20 with Extended Performance 1. Description The T7024 is a monolithic SiGe transmit/receive front-end IC with power amplifier, low-noise amplifier and T/R switch driver. It is especially designed for operation in TDMA systems like Bluetooth ® and WDCT. Due to the ramp-control feature and a very low quiescent current, an external switch transistor for VS is not required. Figure 1-1. Block Diagram PA PA_IN V3_PA_OUT RAMP V2_PA V1_PA LNA LNA_OUT LNA_IN TX/RX/ standby Control PURX_ON VS_LNA SWITCH_OUT R_SWITCH TX RX Bluetooth/ISM 2.4-GHz Front-End IC T7024 4533H–BLURF–07/07
4533H–BLURF–07/07 T7024 2. Pin Configuration Figure 2-1. Pinning PSSO20 Figure 2-2. Pinning QFN20 LNA_IN VS_LNA GND V3_PA_OUT V3_PA_OUT V3_PA_OUT SWITCH_OUT GND GND PA_IN V1_PA GND V2_PA V2_PA RX_ON LNA_OUT GND RAMP R_SWITCH PU T7024 10 6 789 16 20 191817 LNA_OUT RX_ON PU R_SWITCH SWITCH_OUT GND VS_LNA GND LNA_IN GND V3_PA_OUT V3_PA_OUT V3_PA_OUT GND RAMP V2_PA V2_PA GND V1_PA PA_IN T7024 Table 2-1. Pin Description Pins PSSO20 Pins QFN20 Symbol Function 1 4 R_SWITCH Resistor to GND sets the PIN diode current 2 5 SWITCH_OUT Switched current output for PIN diode 3 6 GND Ground 4 7 LNA_IN Low-noise amplifier input 5 9 VS_LNA Supply voltage input for low-noise amplifier 6 8 GND Ground 7 11 V3_PA_OUT Inductor to power supply and matching network for power amplifier output 8 12 V3_PA_OUT Inductor to power supply and matching network for power amplifier output 9 13 V3_PA_OUT Inductor to power supply and matching network for power amplifier output 10 10 GND Ground 11 15 RAMP Power ramping control input 12 16 V2_PA Inductor to power supply for power amplifier 13 17 V2_PA Inductor to power supply for power amplifier 14 14 GND Ground 15 19 V1_PA Supply voltage for power amplifier 16 20 PA_IN Power amplifier input 17 18 GND Ground 18 1 LNA_OUT Low-noise amplifier output 19 2 RX_ON RX active high 20 3 PU Power-up active high Slug Slug GND Ground
4533H–BLURF–07/07 T7024 Electrostatic sensitive device. Observe precautions for handling. 5. Handling Do not operate this part near strong electrostatic fields. This IC meets class 1 ESD test require- ment (HBM in accordance to EIA/JESD22-A114-A (October 97) and class A ESD test requirement (MM) in accordance to EIA/JESD22-A115A. 3. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Value Unit Supply voltage Pins VS_LNA, V1_PA, V2_PA, V3_PA_OUT V S 6V Junction temperature T j 150 °C Storage temperature T stg –40 to +125 °C RF input power LNA P inLNA 5d B m RF input power PA P inPA 10 dBm 4. Thermal Resistance Parameters Symbol Value Unit Junction ambient PSSOP20, slug soldered on PCB R thJA 19 K/W Junction ambient QFN20, slug soldered on PCB R thJA 27 K/W 6. Operating Range All voltages are referred to ground (pins GND and slug). Power supply points are VS_LNA, V1_PA, V2_PA, V3_PA_OUT. The table represents the sum of all supply currents depending on the TX/RX mode. Parameters Symbol Min. Typ. Max. Unit Supply voltage Pins V1_PA, V2_PA and V3_PA_OUT V S 2.7 3.0 4.6 V Supply voltage, pin VS_LNA V S 2.7 3.0 5.5 V Supply current TX, PSSO20 QFN20 Supply current RX IS IS IS 190 165 mA mA mA Standby current, PU = 0 I S_standby 10 µA Ambient temperature T amb –25 +25 +85 °C
4533H–BLURF–07/07 T7024 7. Electrical Characteristics Test conditions (unless otherwise specified): VS = 3.0V, Tamb = 25°C Parameters Test Conditions Symbol Min. Typ. Max. Unit Power Amplifier(1) Supply voltage Pins V1_PA, V2_PA, V3_PA_OUT V S 2.7 3.0 4.6 V Supply current TX, PSSO20 TX, QFN20 IS_TX IS_TX 190 165 mA mA RX (PA off), VRAMP ≤ 0.1V I S_RX 10 µA Standby current Standby I S_standby 10 µA Frequency range TX f 2.4 2.5 GHz Gain-control range TX ∆Gp 60 42 dB Power gain maximum TX, pin PA_IN to V3_PA_OUT Gp 28 30 33 dB Power gain minimum TX, pin PA_IN to V3_PA_OUT Gp –40 –17 dB Ramping voltage maximum TX, power gain (maximum) Pin RAMP V RAMP max 1.7 1.75 1.83 V Ramping voltage minimum TX, power gain (minimum) Pin RAMP VRAMP min 0.1 V Ramping current maximum TX, V RAMP = 1.75V, pin RAMP I RAMP max 0.5 mA Power-added efficiency TX, PSSO20 TX, QFN20 PAE PAE Saturated output power TX, input power = 0 dBm referred to pins V3_PA_OUT Psat 22 23 24 dBm Input matching(2) TX, pin PA_IN Load VSWR < 1.5:1 Output matching(2) TX, pins V3_PA_OUT Load VSWR < 1.5:1 Harmonics at Psat = 23 dBm TX, pins V3_PA_OUT 2 fo –30 dBc TX, pins V3_PA_OUT 3 fo –30 dBc T/R Switch Driver (Current Programming by External Resistor from R_SWITCH to GND) Switch-out current output Standby, pin SWITCH_OUT I S_O_standby 1µ A RX I S_O_RX 1µ A TX at 100Ω IS_O_100 1.7 mA TX at 1.2 kΩ IS_O_1k2 7m A TX at 33 kΩ IS_O_33k 17 mA TX at ∞ IS_O_R 19 mA Low-noise Amplifier(3) Supply voltage All, pin VS_LNA V S 2.7 3.0 5.5 V Supply current RX I S 89 m A Notes: 1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch and duration: load VSWR = 10:1 (all phases) 10s, ZG = 50Ω. 2. With external matching network, load impedance 50 Ω. 3. Low-noise amplifier shall be unconditionally stable. 4. With external matching components. 5. LNA gain can be adjusted with RX_ON voltage according to Figure 9-16 on page 11. Please note, that for RX_ON below 1.4V the T/R switch driver switches to TX mode.
4533H–BLURF–07/07 T7024 Supply current (LNA and control logic) TX (control logic active) Pin VS_LNA IS 0.5 mA Standby current Standby, pin VS_LNA I S_standby 11 0 µ A Frequency range RX f 2.4 2.5 GHz Power gain (5) RX, pin LNA_IN to LNA_OUT Gp 15 16 19 dB Noise figure RX, PSSO20 RX, QFN20 NF NF 2.5 2.1 2.8 2.3 dB dB Gain compression RX, referred to pin LNA_OUT O1dB –9 –7 –6 dBm rd-order input interception point RX IIP3 –16 –14 –13 dBm Input matching(4) RX, pin LNA_IN VSWRin 2:1 Output matching(4) RX, pin LNA_OUT VSWRout 2:1 Logic Input Levels (RX_ON, PU)(5) High input level = ‘1’ pins RX_ON and PU V iH 2.4 V S, LNA V Low input level = ‘0’ V iL 00 . 5 V High input current = ‘1’ V iH = 2.4V I iH 40 60 µA Low input current = ‘0’ I iL 0.2 µA 7. Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS = 3.0V, Tamb = 25°C Parameters Test Conditions Symbol Min. Typ. Max. Unit Notes: 1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch and duration: load VSWR = 10:1 (all phases) 10s, ZG = 50Ω. 2. With external matching network, load impedance 50 Ω. 3. Low-noise amplifier shall be unconditionally stable. 4. With external matching components. 5. LNA gain can be adjusted with RX_ON voltage according to Figure 9-16 on page 11. Please note, that for RX_ON below 1.4V the T/R switch driver switches to TX mode. 8. Control Logic PA and LN A/Antenna Switch Driver PU RX_ON Ramp (1) PA LNA Antenna Switch Driver Operation Mode 0 0 0 off off off standby 0 0 1 on off off (2) 0 1 0 off on off (3) 011 o n o n o f f ( 4 ) 1 0 0 off off on (4) 101 o n o f f o n T X 1 1 0 off on off RX 111 o n o n o f f ( 5 ) Notes: 1. “0” = V RAMP ≤ 0.1V, “1” = VRAMP typically 1.75V, 1.3V < VRAMP < 1.83V controls gain and output power, compare Figure 9-6 on page 7 and Figure 9-10 on page 9 2. Only for special operation, e.g. only PA operation, no LNA/switch driver operation 3. Only for special operation, e.g. no switch driver operation 4. Only for special operation 5. Only for special operation, e.g. separate TX/RX antennas, TX and RX operation at the same time
4533H–BLURF–07/07 T7024 Figure 10-9. Typical Application T7024 (PSSO20 Package) Blocking capacitors depending on application Pin-diode replaced by LED on application-board R1 is selected with DIL-switch 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PU RX ON 3.9p 3.9nH LNA OUT PA IN V1_PA V2_PA 3p3 PA ramp 15nH VS_LNA 1.8p LNA IN Switch Out 5.6nH V3_PA 0p8 PA OUT harm. termination T7024 1p5
4533H–BLURF–07/07 T7024 Figure 10-10. Typical Application T7024 (QFN20 Package) 20 19 18 17 16 6 7 8 9 10 T7024 3p3 V2_PA 1p2.2p RX ON PU Switch Out 1.8p LNA IN VS_LNA 18nH V3_PA 0p8 2p2 PA OUT PA ramp Var V1_PA PA IN LNA OUT harm. termination blocking capacitors depending on application Pin-diode replaced by LED on application-board R1 is selected with DIL-switch 11. Ordering Information Extended Type Number Package Remarks MOQ T7024-TRSY PSSO20 Tube, Pb-free 830 pcs. T7024-TRQY PSSO20 T aped and reeled, Pb-free 4000 pcs. T7024-PGPM QFN20 Taped and reeled Pb free, halogen free 1500 pcs. T7024-PGQM QFN20 Taped and reeled Pb free, halogen free 6000 pcs. Demoboard-T7024-PGM QFN20 Evaluation board QFN 1 Demoboard-T7024-TR PSSO20 Evaluation board PSSO 1
4533H–BLURF–07/07 T7024 12. Package Information specifications according to DIN technical drawings Dimensions in mm 0.18 max. 1.3 2.15 0.575 20 11 11 0 ∅ 0.4 A 0.15 0.12 (20x) CA A B B 6.7 max. 6.75 max. 2.6 0.25 0.65 5.85 0.05+0.09 6.45±0.15 5.4±0.2 4.4±0.1 Issue: 1; 05.06.01 Drawing-No.: 6.543-5078.01-4
4533H–BLURF–07/07 T7024 13. Package Information PB Free 610 2016 3.1 2.6 0.65 nom. specifications according to DIN technical drawings Issue: 1; 19.12.02 Drawing-No.: 6.543-5094.01-4 Package: QFN 20 - 5 x 5 Exposed pad 3.1 x 3.1 Dimensions in mm Not indicated tolerances ± 0.05 0.28 0.6 0.9±0.1 0.05-0.05
4533H–BLURF–07/07 T7024 14. Recommended PCB Land Pattern Figure 14-1. Recommended PCB Land Pattern 15. Revision History Table 14-1. Recommended PCB Land Pattern Signs Sign Description Size A Distance of vias 1.6 mm B Size of slug pattern 3.1 mm C Distance slug to pins 0.33 mm D Diameter of vias 1 mm E Width of pin pattern 0.3 mm F Distance of pin pattern 0.33 mm A C E F D B Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 4533H-BLURF-07/07
- Put datasheet in a new template
- Page 1: Block diagram changed
- Page 13: Figure 10-8 changed
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